Commit | Line | Data |
---|---|---|
c869f77d JK |
1 | /* |
2 | * (c) Copyright 2002-2010, Ralink Technology, Inc. | |
3 | * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org> | |
4 | * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 | |
8 | * as published by the Free Software Foundation | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include "mt7601u.h" | |
17 | #include "mcu.h" | |
18 | #include "eeprom.h" | |
19 | #include "trace.h" | |
20 | #include "initvals_phy.h" | |
21 | ||
22 | #include <linux/etherdevice.h> | |
23 | ||
24 | static void mt7601u_agc_reset(struct mt7601u_dev *dev); | |
25 | ||
26 | static int | |
27 | mt7601u_rf_wr(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 value) | |
28 | { | |
29 | int ret = 0; | |
30 | ||
31 | if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) || | |
32 | WARN_ON(offset > 63)) | |
33 | return -EINVAL; | |
34 | if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) | |
35 | return 0; | |
36 | ||
37 | mutex_lock(&dev->reg_atomic_mutex); | |
38 | ||
39 | if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) { | |
40 | ret = -ETIMEDOUT; | |
41 | goto out; | |
42 | } | |
43 | ||
d43af505 JK |
44 | mt7601u_wr(dev, MT_RF_CSR_CFG, |
45 | FIELD_PREP(MT_RF_CSR_CFG_DATA, value) | | |
46 | FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) | | |
47 | FIELD_PREP(MT_RF_CSR_CFG_REG_ID, offset) | | |
48 | MT_RF_CSR_CFG_WR | | |
49 | MT_RF_CSR_CFG_KICK); | |
c869f77d JK |
50 | trace_rf_write(dev, bank, offset, value); |
51 | out: | |
52 | mutex_unlock(&dev->reg_atomic_mutex); | |
53 | ||
54 | if (ret < 0) | |
55 | dev_err(dev->dev, "Error: RF write %02hhx:%02hhx failed:%d!!\n", | |
56 | bank, offset, ret); | |
57 | ||
58 | return ret; | |
59 | } | |
60 | ||
61 | static int | |
62 | mt7601u_rf_rr(struct mt7601u_dev *dev, u8 bank, u8 offset) | |
63 | { | |
64 | int ret = -ETIMEDOUT; | |
65 | u32 val; | |
66 | ||
67 | if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) || | |
68 | WARN_ON(offset > 63)) | |
69 | return -EINVAL; | |
70 | if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) | |
71 | return 0xff; | |
72 | ||
73 | mutex_lock(&dev->reg_atomic_mutex); | |
74 | ||
75 | if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) | |
76 | goto out; | |
77 | ||
d43af505 JK |
78 | mt7601u_wr(dev, MT_RF_CSR_CFG, |
79 | FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) | | |
80 | FIELD_PREP(MT_RF_CSR_CFG_REG_ID, offset) | | |
81 | MT_RF_CSR_CFG_KICK); | |
c869f77d JK |
82 | |
83 | if (!mt76_poll(dev, MT_RF_CSR_CFG, MT_RF_CSR_CFG_KICK, 0, 100)) | |
84 | goto out; | |
85 | ||
86 | val = mt7601u_rr(dev, MT_RF_CSR_CFG); | |
d43af505 JK |
87 | if (FIELD_GET(MT_RF_CSR_CFG_REG_ID, val) == offset && |
88 | FIELD_GET(MT_RF_CSR_CFG_REG_BANK, val) == bank) { | |
89 | ret = FIELD_GET(MT_RF_CSR_CFG_DATA, val); | |
c869f77d JK |
90 | trace_rf_read(dev, bank, offset, ret); |
91 | } | |
92 | out: | |
93 | mutex_unlock(&dev->reg_atomic_mutex); | |
94 | ||
95 | if (ret < 0) | |
96 | dev_err(dev->dev, "Error: RF read %02hhx:%02hhx failed:%d!!\n", | |
97 | bank, offset, ret); | |
98 | ||
99 | return ret; | |
100 | } | |
101 | ||
102 | static int | |
103 | mt7601u_rf_rmw(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 mask, u8 val) | |
104 | { | |
105 | int ret; | |
106 | ||
107 | ret = mt7601u_rf_rr(dev, bank, offset); | |
108 | if (ret < 0) | |
109 | return ret; | |
110 | val |= ret & ~mask; | |
111 | ret = mt7601u_rf_wr(dev, bank, offset, val); | |
112 | if (ret) | |
113 | return ret; | |
114 | ||
115 | return val; | |
116 | } | |
117 | ||
118 | static int | |
119 | mt7601u_rf_set(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 val) | |
120 | { | |
121 | return mt7601u_rf_rmw(dev, bank, offset, 0, val); | |
122 | } | |
123 | ||
124 | static int | |
125 | mt7601u_rf_clear(struct mt7601u_dev *dev, u8 bank, u8 offset, u8 mask) | |
126 | { | |
127 | return mt7601u_rf_rmw(dev, bank, offset, mask, 0); | |
128 | } | |
129 | ||
130 | static void mt7601u_bbp_wr(struct mt7601u_dev *dev, u8 offset, u8 val) | |
131 | { | |
132 | if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state)) || | |
133 | test_bit(MT7601U_STATE_REMOVED, &dev->state)) | |
134 | return; | |
135 | ||
136 | mutex_lock(&dev->reg_atomic_mutex); | |
137 | ||
138 | if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000)) { | |
139 | dev_err(dev->dev, "Error: BBP write %02hhx failed!!\n", offset); | |
140 | goto out; | |
141 | } | |
142 | ||
143 | mt7601u_wr(dev, MT_BBP_CSR_CFG, | |
d43af505 JK |
144 | FIELD_PREP(MT_BBP_CSR_CFG_VAL, val) | |
145 | FIELD_PREP(MT_BBP_CSR_CFG_REG_NUM, offset) | | |
c869f77d JK |
146 | MT_BBP_CSR_CFG_RW_MODE | MT_BBP_CSR_CFG_BUSY); |
147 | trace_bbp_write(dev, offset, val); | |
148 | out: | |
149 | mutex_unlock(&dev->reg_atomic_mutex); | |
150 | } | |
151 | ||
152 | static int mt7601u_bbp_rr(struct mt7601u_dev *dev, u8 offset) | |
153 | { | |
154 | u32 val; | |
155 | int ret = -ETIMEDOUT; | |
156 | ||
157 | if (WARN_ON(!test_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state))) | |
158 | return -EINVAL; | |
159 | if (test_bit(MT7601U_STATE_REMOVED, &dev->state)) | |
160 | return 0xff; | |
161 | ||
162 | mutex_lock(&dev->reg_atomic_mutex); | |
163 | ||
164 | if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000)) | |
165 | goto out; | |
166 | ||
167 | mt7601u_wr(dev, MT_BBP_CSR_CFG, | |
d43af505 | 168 | FIELD_PREP(MT_BBP_CSR_CFG_REG_NUM, offset) | |
c869f77d JK |
169 | MT_BBP_CSR_CFG_RW_MODE | MT_BBP_CSR_CFG_BUSY | |
170 | MT_BBP_CSR_CFG_READ); | |
171 | ||
172 | if (!mt76_poll(dev, MT_BBP_CSR_CFG, MT_BBP_CSR_CFG_BUSY, 0, 1000)) | |
173 | goto out; | |
174 | ||
175 | val = mt7601u_rr(dev, MT_BBP_CSR_CFG); | |
d43af505 JK |
176 | if (FIELD_GET(MT_BBP_CSR_CFG_REG_NUM, val) == offset) { |
177 | ret = FIELD_GET(MT_BBP_CSR_CFG_VAL, val); | |
c869f77d JK |
178 | trace_bbp_read(dev, offset, ret); |
179 | } | |
180 | out: | |
181 | mutex_unlock(&dev->reg_atomic_mutex); | |
182 | ||
183 | if (ret < 0) | |
184 | dev_err(dev->dev, "Error: BBP read %02hhx failed:%d!!\n", | |
185 | offset, ret); | |
186 | ||
187 | return ret; | |
188 | } | |
189 | ||
190 | static int mt7601u_bbp_rmw(struct mt7601u_dev *dev, u8 offset, u8 mask, u8 val) | |
191 | { | |
192 | int ret; | |
193 | ||
194 | ret = mt7601u_bbp_rr(dev, offset); | |
195 | if (ret < 0) | |
196 | return ret; | |
197 | val |= ret & ~mask; | |
198 | mt7601u_bbp_wr(dev, offset, val); | |
199 | ||
200 | return val; | |
201 | } | |
202 | ||
203 | static u8 mt7601u_bbp_rmc(struct mt7601u_dev *dev, u8 offset, u8 mask, u8 val) | |
204 | { | |
205 | int ret; | |
206 | ||
207 | ret = mt7601u_bbp_rr(dev, offset); | |
208 | if (ret < 0) | |
209 | return ret; | |
210 | val |= ret & ~mask; | |
211 | if (ret != val) | |
212 | mt7601u_bbp_wr(dev, offset, val); | |
213 | ||
214 | return val; | |
215 | } | |
216 | ||
217 | int mt7601u_wait_bbp_ready(struct mt7601u_dev *dev) | |
218 | { | |
219 | int i = 20; | |
220 | u8 val; | |
221 | ||
222 | do { | |
223 | val = mt7601u_bbp_rr(dev, MT_BBP_REG_VERSION); | |
224 | if (val && ~val) | |
225 | break; | |
226 | } while (--i); | |
227 | ||
228 | if (!i) { | |
229 | dev_err(dev->dev, "Error: BBP is not ready\n"); | |
230 | return -EIO; | |
231 | } | |
232 | ||
233 | return 0; | |
234 | } | |
235 | ||
236 | u32 mt7601u_bbp_set_ctrlch(struct mt7601u_dev *dev, bool below) | |
237 | { | |
238 | return mt7601u_bbp_rmc(dev, 3, 0x20, below ? 0x20 : 0); | |
239 | } | |
240 | ||
241 | int mt7601u_phy_get_rssi(struct mt7601u_dev *dev, | |
242 | struct mt7601u_rxwi *rxwi, u16 rate) | |
243 | { | |
244 | static const s8 lna[2][2][3] = { | |
245 | /* main LNA */ { | |
246 | /* bw20 */ { -2, 15, 33 }, | |
247 | /* bw40 */ { 0, 16, 34 } | |
248 | }, | |
249 | /* aux LNA */ { | |
250 | /* bw20 */ { -2, 15, 33 }, | |
251 | /* bw40 */ { -2, 16, 34 } | |
252 | } | |
253 | }; | |
d43af505 JK |
254 | int bw = FIELD_GET(MT_RXWI_RATE_BW, rate); |
255 | int aux_lna = FIELD_GET(MT_RXWI_ANT_AUX_LNA, rxwi->ant); | |
256 | int lna_id = FIELD_GET(MT_RXWI_GAIN_RSSI_LNA_ID, rxwi->gain); | |
c869f77d JK |
257 | int val; |
258 | ||
259 | if (lna_id) /* LNA id can be 0, 2, 3. */ | |
260 | lna_id--; | |
261 | ||
262 | val = 8; | |
263 | val -= lna[aux_lna][bw][lna_id]; | |
d43af505 | 264 | val -= FIELD_GET(MT_RXWI_GAIN_RSSI_VAL, rxwi->gain); |
c869f77d JK |
265 | val -= dev->ee->lna_gain; |
266 | val -= dev->ee->rssi_offset[0]; | |
267 | ||
268 | return val; | |
269 | } | |
270 | ||
271 | static void mt7601u_vco_cal(struct mt7601u_dev *dev) | |
272 | { | |
273 | mt7601u_rf_wr(dev, 0, 4, 0x0a); | |
274 | mt7601u_rf_wr(dev, 0, 5, 0x20); | |
275 | mt7601u_rf_set(dev, 0, 4, BIT(7)); | |
276 | msleep(2); | |
277 | } | |
278 | ||
279 | static int mt7601u_set_bw_filter(struct mt7601u_dev *dev, bool cal) | |
280 | { | |
281 | u32 filter = 0; | |
282 | int ret; | |
283 | ||
284 | if (!cal) | |
285 | filter |= 0x10000; | |
286 | if (dev->bw != MT_BW_20) | |
287 | filter |= 0x00100; | |
288 | ||
289 | /* TX */ | |
290 | ret = mt7601u_mcu_calibrate(dev, MCU_CAL_BW, filter | 1); | |
291 | if (ret) | |
292 | return ret; | |
293 | /* RX */ | |
294 | return mt7601u_mcu_calibrate(dev, MCU_CAL_BW, filter); | |
295 | } | |
296 | ||
297 | static int mt7601u_load_bbp_temp_table_bw(struct mt7601u_dev *dev) | |
298 | { | |
299 | const struct reg_table *t; | |
300 | ||
301 | if (WARN_ON(dev->temp_mode > MT_TEMP_MODE_LOW)) | |
302 | return -EINVAL; | |
303 | ||
304 | t = &bbp_mode_table[dev->temp_mode][dev->bw]; | |
305 | ||
306 | return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, t->regs, t->n); | |
307 | } | |
308 | ||
309 | static int mt7601u_bbp_temp(struct mt7601u_dev *dev, int mode, const char *name) | |
310 | { | |
311 | const struct reg_table *t; | |
312 | int ret; | |
313 | ||
314 | if (dev->temp_mode == mode) | |
315 | return 0; | |
316 | ||
317 | dev->temp_mode = mode; | |
318 | trace_temp_mode(dev, mode); | |
319 | ||
320 | t = bbp_mode_table[dev->temp_mode]; | |
321 | ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, | |
322 | t[2].regs, t[2].n); | |
323 | if (ret) | |
324 | return ret; | |
325 | ||
326 | return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, | |
327 | t[dev->bw].regs, t[dev->bw].n); | |
328 | } | |
329 | ||
330 | static void mt7601u_apply_ch14_fixup(struct mt7601u_dev *dev, int hw_chan) | |
331 | { | |
332 | struct mt7601u_rate_power *t = &dev->ee->power_rate_table; | |
333 | ||
334 | if (hw_chan != 14 || dev->bw != MT_BW_20) { | |
335 | mt7601u_bbp_rmw(dev, 4, 0x20, 0); | |
336 | mt7601u_bbp_wr(dev, 178, 0xff); | |
337 | ||
338 | t->cck[0].bw20 = dev->ee->real_cck_bw20[0]; | |
339 | t->cck[1].bw20 = dev->ee->real_cck_bw20[1]; | |
340 | } else { /* Apply CH14 OBW fixup */ | |
341 | mt7601u_bbp_wr(dev, 4, 0x60); | |
342 | mt7601u_bbp_wr(dev, 178, 0); | |
343 | ||
344 | /* Note: vendor code is buggy here for negative values */ | |
345 | t->cck[0].bw20 = dev->ee->real_cck_bw20[0] - 2; | |
346 | t->cck[1].bw20 = dev->ee->real_cck_bw20[1] - 2; | |
347 | } | |
348 | } | |
349 | ||
350 | static int __mt7601u_phy_set_channel(struct mt7601u_dev *dev, | |
351 | struct cfg80211_chan_def *chandef) | |
352 | { | |
353 | #define FREQ_PLAN_REGS 4 | |
354 | static const u8 freq_plan[14][FREQ_PLAN_REGS] = { | |
355 | { 0x99, 0x99, 0x09, 0x50 }, | |
356 | { 0x46, 0x44, 0x0a, 0x50 }, | |
357 | { 0xec, 0xee, 0x0a, 0x50 }, | |
358 | { 0x99, 0x99, 0x0b, 0x50 }, | |
359 | { 0x46, 0x44, 0x08, 0x51 }, | |
360 | { 0xec, 0xee, 0x08, 0x51 }, | |
361 | { 0x99, 0x99, 0x09, 0x51 }, | |
362 | { 0x46, 0x44, 0x0a, 0x51 }, | |
363 | { 0xec, 0xee, 0x0a, 0x51 }, | |
364 | { 0x99, 0x99, 0x0b, 0x51 }, | |
365 | { 0x46, 0x44, 0x08, 0x52 }, | |
366 | { 0xec, 0xee, 0x08, 0x52 }, | |
367 | { 0x99, 0x99, 0x09, 0x52 }, | |
368 | { 0x33, 0x33, 0x0b, 0x52 }, | |
369 | }; | |
370 | struct mt76_reg_pair channel_freq_plan[FREQ_PLAN_REGS] = { | |
371 | { 17, 0 }, { 18, 0 }, { 19, 0 }, { 20, 0 }, | |
372 | }; | |
373 | struct mt76_reg_pair bbp_settings[3] = { | |
374 | { 62, 0x37 - dev->ee->lna_gain }, | |
375 | { 63, 0x37 - dev->ee->lna_gain }, | |
376 | { 64, 0x37 - dev->ee->lna_gain }, | |
377 | }; | |
378 | ||
379 | struct ieee80211_channel *chan = chandef->chan; | |
380 | enum nl80211_channel_type chan_type = | |
381 | cfg80211_get_chandef_type(chandef); | |
382 | struct mt7601u_rate_power *t = &dev->ee->power_rate_table; | |
383 | int chan_idx; | |
384 | bool chan_ext_below; | |
385 | u8 bw; | |
386 | int i, ret; | |
387 | ||
388 | bw = MT_BW_20; | |
389 | chan_ext_below = (chan_type == NL80211_CHAN_HT40MINUS); | |
390 | chan_idx = chan->hw_value - 1; | |
391 | ||
392 | if (chandef->width == NL80211_CHAN_WIDTH_40) { | |
393 | bw = MT_BW_40; | |
394 | ||
395 | if (chan_idx > 1 && chan_type == NL80211_CHAN_HT40MINUS) | |
396 | chan_idx -= 2; | |
397 | else if (chan_idx < 12 && chan_type == NL80211_CHAN_HT40PLUS) | |
398 | chan_idx += 2; | |
399 | else | |
400 | dev_err(dev->dev, "Error: invalid 40MHz channel!!\n"); | |
401 | } | |
402 | ||
403 | if (bw != dev->bw || chan_ext_below != dev->chan_ext_below) { | |
404 | dev_dbg(dev->dev, "Info: switching HT mode bw:%d below:%d\n", | |
405 | bw, chan_ext_below); | |
406 | ||
407 | mt7601u_bbp_set_bw(dev, bw); | |
408 | ||
409 | mt7601u_bbp_set_ctrlch(dev, chan_ext_below); | |
410 | mt7601u_mac_set_ctrlch(dev, chan_ext_below); | |
411 | dev->chan_ext_below = chan_ext_below; | |
412 | } | |
413 | ||
414 | for (i = 0; i < FREQ_PLAN_REGS; i++) | |
415 | channel_freq_plan[i].value = freq_plan[chan_idx][i]; | |
416 | ||
417 | ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_RF, | |
418 | channel_freq_plan, FREQ_PLAN_REGS); | |
419 | if (ret) | |
420 | return ret; | |
421 | ||
422 | mt7601u_rmw(dev, MT_TX_ALC_CFG_0, 0x3f3f, | |
423 | dev->ee->chan_pwr[chan_idx] & 0x3f); | |
424 | ||
425 | ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, | |
426 | bbp_settings, ARRAY_SIZE(bbp_settings)); | |
427 | if (ret) | |
428 | return ret; | |
429 | ||
430 | mt7601u_vco_cal(dev); | |
431 | mt7601u_bbp_set_bw(dev, bw); | |
432 | ret = mt7601u_set_bw_filter(dev, false); | |
433 | if (ret) | |
434 | return ret; | |
435 | ||
436 | mt7601u_apply_ch14_fixup(dev, chan->hw_value); | |
437 | mt7601u_wr(dev, MT_TX_PWR_CFG_0, int_to_s6(t->ofdm[1].bw20) << 24 | | |
438 | int_to_s6(t->ofdm[0].bw20) << 16 | | |
439 | int_to_s6(t->cck[1].bw20) << 8 | | |
440 | int_to_s6(t->cck[0].bw20)); | |
441 | ||
442 | if (test_bit(MT7601U_STATE_SCANNING, &dev->state)) | |
443 | mt7601u_agc_reset(dev); | |
444 | ||
445 | dev->chandef = *chandef; | |
446 | ||
447 | return 0; | |
448 | } | |
449 | ||
450 | int mt7601u_phy_set_channel(struct mt7601u_dev *dev, | |
451 | struct cfg80211_chan_def *chandef) | |
452 | { | |
453 | int ret; | |
454 | ||
455 | cancel_delayed_work_sync(&dev->cal_work); | |
456 | cancel_delayed_work_sync(&dev->freq_cal.work); | |
457 | ||
458 | mutex_lock(&dev->hw_atomic_mutex); | |
459 | ret = __mt7601u_phy_set_channel(dev, chandef); | |
460 | mutex_unlock(&dev->hw_atomic_mutex); | |
461 | if (ret) | |
462 | return ret; | |
463 | ||
464 | if (test_bit(MT7601U_STATE_SCANNING, &dev->state)) | |
465 | return 0; | |
466 | ||
467 | ieee80211_queue_delayed_work(dev->hw, &dev->cal_work, | |
468 | MT_CALIBRATE_INTERVAL); | |
469 | if (dev->freq_cal.enabled) | |
470 | ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work, | |
471 | MT_FREQ_CAL_INIT_DELAY); | |
472 | return 0; | |
473 | } | |
474 | ||
475 | #define BBP_R47_FLAG GENMASK(2, 0) | |
476 | #define BBP_R47_F_TSSI 0 | |
477 | #define BBP_R47_F_PKT_T 1 | |
478 | #define BBP_R47_F_TX_RATE 2 | |
479 | #define BBP_R47_F_TEMP 4 | |
480 | /** | |
481 | * mt7601u_bbp_r47_get - read value through BBP R47/R49 pair | |
482 | * @dev: pointer to adapter structure | |
483 | * @reg: value of BBP R47 before the operation | |
484 | * @flag: one of the BBP_R47_F_* flags | |
485 | * | |
486 | * Convenience helper for reading values through BBP R47/R49 pair. | |
487 | * Takes old value of BBP R47 as @reg, because callers usually have it | |
488 | * cached already. | |
489 | * | |
490 | * Return: value of BBP R49. | |
491 | */ | |
492 | static u8 mt7601u_bbp_r47_get(struct mt7601u_dev *dev, u8 reg, u8 flag) | |
493 | { | |
494 | flag |= reg & ~BBP_R47_FLAG; | |
495 | mt7601u_bbp_wr(dev, 47, flag); | |
496 | usleep_range(500, 700); | |
497 | return mt7601u_bbp_rr(dev, 49); | |
498 | } | |
499 | ||
500 | static s8 mt7601u_read_bootup_temp(struct mt7601u_dev *dev) | |
501 | { | |
502 | u8 bbp_val, temp; | |
503 | u32 rf_bp, rf_set; | |
504 | int i; | |
505 | ||
506 | rf_set = mt7601u_rr(dev, MT_RF_SETTING_0); | |
507 | rf_bp = mt7601u_rr(dev, MT_RF_BYPASS_0); | |
508 | ||
509 | mt7601u_wr(dev, MT_RF_BYPASS_0, 0); | |
510 | mt7601u_wr(dev, MT_RF_SETTING_0, 0x00000010); | |
511 | mt7601u_wr(dev, MT_RF_BYPASS_0, 0x00000010); | |
512 | ||
513 | bbp_val = mt7601u_bbp_rmw(dev, 47, 0, 0x10); | |
514 | ||
515 | mt7601u_bbp_wr(dev, 22, 0x40); | |
516 | ||
517 | for (i = 100; i && (bbp_val & 0x10); i--) | |
518 | bbp_val = mt7601u_bbp_rr(dev, 47); | |
519 | ||
520 | temp = mt7601u_bbp_r47_get(dev, bbp_val, BBP_R47_F_TEMP); | |
521 | ||
522 | mt7601u_bbp_wr(dev, 22, 0); | |
523 | ||
524 | bbp_val = mt7601u_bbp_rr(dev, 21); | |
525 | bbp_val |= 0x02; | |
526 | mt7601u_bbp_wr(dev, 21, bbp_val); | |
527 | bbp_val &= ~0x02; | |
528 | mt7601u_bbp_wr(dev, 21, bbp_val); | |
529 | ||
530 | mt7601u_wr(dev, MT_RF_BYPASS_0, 0); | |
531 | mt7601u_wr(dev, MT_RF_SETTING_0, rf_set); | |
532 | mt7601u_wr(dev, MT_RF_BYPASS_0, rf_bp); | |
533 | ||
534 | trace_read_temp(dev, temp); | |
535 | return temp; | |
536 | } | |
537 | ||
538 | static s8 mt7601u_read_temp(struct mt7601u_dev *dev) | |
539 | { | |
540 | int i; | |
541 | u8 val; | |
542 | s8 temp; | |
543 | ||
544 | val = mt7601u_bbp_rmw(dev, 47, 0x7f, 0x10); | |
545 | ||
546 | /* Note: this rarely succeeds, temp can change even if it fails. */ | |
547 | for (i = 100; i && (val & 0x10); i--) | |
548 | val = mt7601u_bbp_rr(dev, 47); | |
549 | ||
550 | temp = mt7601u_bbp_r47_get(dev, val, BBP_R47_F_TEMP); | |
551 | ||
552 | trace_read_temp(dev, temp); | |
553 | return temp; | |
554 | } | |
555 | ||
556 | static void mt7601u_rxdc_cal(struct mt7601u_dev *dev) | |
557 | { | |
558 | static const struct mt76_reg_pair intro[] = { | |
559 | { 158, 0x8d }, { 159, 0xfc }, | |
560 | { 158, 0x8c }, { 159, 0x4c }, | |
561 | }, outro[] = { | |
562 | { 158, 0x8d }, { 159, 0xe0 }, | |
563 | }; | |
564 | u32 mac_ctrl; | |
565 | int i, ret; | |
566 | ||
567 | mac_ctrl = mt7601u_rr(dev, MT_MAC_SYS_CTRL); | |
568 | mt7601u_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX); | |
569 | ||
570 | ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, | |
571 | intro, ARRAY_SIZE(intro)); | |
572 | if (ret) | |
573 | dev_err(dev->dev, "%s intro failed:%d\n", __func__, ret); | |
574 | ||
575 | for (i = 20; i; i--) { | |
576 | usleep_range(300, 500); | |
577 | ||
578 | mt7601u_bbp_wr(dev, 158, 0x8c); | |
579 | if (mt7601u_bbp_rr(dev, 159) == 0x0c) | |
580 | break; | |
581 | } | |
582 | if (!i) | |
583 | dev_err(dev->dev, "%s timed out\n", __func__); | |
584 | ||
585 | mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0); | |
586 | ||
587 | ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, | |
588 | outro, ARRAY_SIZE(outro)); | |
589 | if (ret) | |
590 | dev_err(dev->dev, "%s outro failed:%d\n", __func__, ret); | |
591 | ||
592 | mt7601u_wr(dev, MT_MAC_SYS_CTRL, mac_ctrl); | |
593 | } | |
594 | ||
595 | void mt7601u_phy_recalibrate_after_assoc(struct mt7601u_dev *dev) | |
596 | { | |
597 | mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->curr_temp); | |
598 | ||
599 | mt7601u_rxdc_cal(dev); | |
600 | } | |
601 | ||
602 | /* Note: function copied from vendor driver */ | |
603 | static s16 lin2dBd(u16 linear) | |
604 | { | |
605 | short exp = 0; | |
606 | unsigned int mantisa; | |
607 | int app, dBd; | |
608 | ||
609 | if (WARN_ON(!linear)) | |
610 | return -10000; | |
611 | ||
612 | mantisa = linear; | |
613 | ||
614 | exp = fls(mantisa) - 16; | |
615 | if (exp > 0) | |
616 | mantisa >>= exp; | |
617 | else | |
618 | mantisa <<= abs(exp); | |
619 | ||
620 | if (mantisa <= 0xb800) | |
621 | app = (mantisa + (mantisa >> 3) + (mantisa >> 4) - 0x9600); | |
622 | else | |
623 | app = (mantisa - (mantisa >> 3) - (mantisa >> 6) - 0x5a00); | |
624 | if (app < 0) | |
625 | app = 0; | |
626 | ||
627 | dBd = ((15 + exp) << 15) + app; | |
628 | dBd = (dBd << 2) + (dBd << 1) + (dBd >> 6) + (dBd >> 7); | |
629 | dBd = (dBd >> 10); | |
630 | ||
631 | return dBd; | |
632 | } | |
633 | ||
634 | static void | |
635 | mt7601u_set_initial_tssi(struct mt7601u_dev *dev, s16 tssi_db, s16 tssi_hvga_db) | |
636 | { | |
637 | struct tssi_data *d = &dev->ee->tssi_data; | |
638 | int init_offset; | |
639 | ||
640 | init_offset = -((tssi_db * d->slope + d->offset[1]) / 4096) + 10; | |
641 | ||
642 | mt76_rmw(dev, MT_TX_ALC_CFG_1, MT_TX_ALC_CFG_1_TEMP_COMP, | |
643 | int_to_s6(init_offset) & MT_TX_ALC_CFG_1_TEMP_COMP); | |
644 | } | |
645 | ||
646 | static void mt7601u_tssi_dc_gain_cal(struct mt7601u_dev *dev) | |
647 | { | |
648 | u8 rf_vga, rf_mixer, bbp_r47; | |
649 | int i, j; | |
650 | s8 res[4]; | |
651 | s16 tssi_init_db, tssi_init_hvga_db; | |
652 | ||
653 | mt7601u_wr(dev, MT_RF_SETTING_0, 0x00000030); | |
654 | mt7601u_wr(dev, MT_RF_BYPASS_0, 0x000c0030); | |
655 | mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0); | |
656 | ||
657 | mt7601u_bbp_wr(dev, 58, 0); | |
658 | mt7601u_bbp_wr(dev, 241, 0x2); | |
659 | mt7601u_bbp_wr(dev, 23, 0x8); | |
660 | bbp_r47 = mt7601u_bbp_rr(dev, 47); | |
661 | ||
662 | /* Set VGA gain */ | |
663 | rf_vga = mt7601u_rf_rr(dev, 5, 3); | |
664 | mt7601u_rf_wr(dev, 5, 3, 8); | |
665 | ||
666 | /* Mixer disable */ | |
667 | rf_mixer = mt7601u_rf_rr(dev, 4, 39); | |
668 | mt7601u_rf_wr(dev, 4, 39, 0); | |
669 | ||
670 | for (i = 0; i < 4; i++) { | |
671 | mt7601u_rf_wr(dev, 4, 39, (i & 1) ? rf_mixer : 0); | |
672 | ||
673 | mt7601u_bbp_wr(dev, 23, (i < 2) ? 0x08 : 0x02); | |
674 | mt7601u_rf_wr(dev, 5, 3, (i < 2) ? 0x08 : 0x11); | |
675 | ||
676 | /* BBP TSSI initial and soft reset */ | |
677 | mt7601u_bbp_wr(dev, 22, 0); | |
678 | mt7601u_bbp_wr(dev, 244, 0); | |
679 | ||
680 | mt7601u_bbp_wr(dev, 21, 1); | |
681 | udelay(1); | |
682 | mt7601u_bbp_wr(dev, 21, 0); | |
683 | ||
684 | /* TSSI measurement */ | |
685 | mt7601u_bbp_wr(dev, 47, 0x50); | |
686 | mt7601u_bbp_wr(dev, (i & 1) ? 244 : 22, (i & 1) ? 0x31 : 0x40); | |
687 | ||
688 | for (j = 20; j; j--) | |
689 | if (!(mt7601u_bbp_rr(dev, 47) & 0x10)) | |
690 | break; | |
691 | if (!j) | |
692 | dev_err(dev->dev, "%s timed out\n", __func__); | |
693 | ||
694 | /* TSSI read */ | |
695 | mt7601u_bbp_wr(dev, 47, 0x40); | |
696 | res[i] = mt7601u_bbp_rr(dev, 49); | |
697 | } | |
698 | ||
699 | tssi_init_db = lin2dBd((short)res[1] - res[0]); | |
700 | tssi_init_hvga_db = lin2dBd(((short)res[3] - res[2]) * 4); | |
701 | dev->tssi_init = res[0]; | |
702 | dev->tssi_init_hvga = res[2]; | |
703 | dev->tssi_init_hvga_offset_db = tssi_init_hvga_db - tssi_init_db; | |
704 | ||
705 | dev_dbg(dev->dev, | |
706 | "TSSI_init:%hhx db:%hx hvga:%hhx hvga_db:%hx off_db:%hx\n", | |
707 | dev->tssi_init, tssi_init_db, dev->tssi_init_hvga, | |
708 | tssi_init_hvga_db, dev->tssi_init_hvga_offset_db); | |
709 | ||
710 | mt7601u_bbp_wr(dev, 22, 0); | |
711 | mt7601u_bbp_wr(dev, 244, 0); | |
712 | ||
713 | mt7601u_bbp_wr(dev, 21, 1); | |
714 | udelay(1); | |
715 | mt7601u_bbp_wr(dev, 21, 0); | |
716 | ||
717 | mt7601u_wr(dev, MT_RF_BYPASS_0, 0); | |
718 | mt7601u_wr(dev, MT_RF_SETTING_0, 0); | |
719 | ||
720 | mt7601u_rf_wr(dev, 5, 3, rf_vga); | |
721 | mt7601u_rf_wr(dev, 4, 39, rf_mixer); | |
722 | mt7601u_bbp_wr(dev, 47, bbp_r47); | |
723 | ||
724 | mt7601u_set_initial_tssi(dev, tssi_init_db, tssi_init_hvga_db); | |
725 | } | |
726 | ||
727 | static int mt7601u_temp_comp(struct mt7601u_dev *dev, bool on) | |
728 | { | |
729 | int ret, temp, hi_temp = 400, lo_temp = -200; | |
730 | ||
731 | temp = (dev->raw_temp - dev->ee->ref_temp) * MT_EE_TEMPERATURE_SLOPE; | |
732 | dev->curr_temp = temp; | |
733 | ||
734 | /* DPD Calibration */ | |
735 | if (temp - dev->dpd_temp > 450 || temp - dev->dpd_temp < -450) { | |
736 | dev->dpd_temp = temp; | |
737 | ||
738 | ret = mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->dpd_temp); | |
739 | if (ret) | |
740 | return ret; | |
741 | ||
742 | mt7601u_vco_cal(dev); | |
743 | ||
744 | dev_dbg(dev->dev, "Recalibrate DPD\n"); | |
745 | } | |
746 | ||
747 | /* PLL Lock Protect */ | |
748 | if (temp < -50 && !dev->pll_lock_protect) { /* < 20C */ | |
749 | dev->pll_lock_protect = true; | |
750 | ||
751 | mt7601u_rf_wr(dev, 4, 4, 6); | |
752 | mt7601u_rf_clear(dev, 4, 10, 0x30); | |
753 | ||
754 | dev_dbg(dev->dev, "PLL lock protect on - too cold\n"); | |
755 | } else if (temp > 50 && dev->pll_lock_protect) { /* > 30C */ | |
756 | dev->pll_lock_protect = false; | |
757 | ||
758 | mt7601u_rf_wr(dev, 4, 4, 0); | |
759 | mt7601u_rf_rmw(dev, 4, 10, 0x30, 0x10); | |
760 | ||
761 | dev_dbg(dev->dev, "PLL lock protect off\n"); | |
762 | } | |
763 | ||
764 | if (on) { | |
765 | hi_temp -= 50; | |
766 | lo_temp -= 50; | |
767 | } | |
768 | ||
769 | /* BBP CR for H, L, N temperature */ | |
770 | if (temp > hi_temp) | |
771 | return mt7601u_bbp_temp(dev, MT_TEMP_MODE_HIGH, "high"); | |
772 | else if (temp > lo_temp) | |
773 | return mt7601u_bbp_temp(dev, MT_TEMP_MODE_NORMAL, "normal"); | |
774 | else | |
775 | return mt7601u_bbp_temp(dev, MT_TEMP_MODE_LOW, "low"); | |
776 | } | |
777 | ||
778 | /* Note: this is used only with TSSI, we can just use trgt_pwr from eeprom. */ | |
779 | static int mt7601u_current_tx_power(struct mt7601u_dev *dev) | |
780 | { | |
781 | return dev->ee->chan_pwr[dev->chandef.chan->hw_value - 1]; | |
782 | } | |
783 | ||
784 | static bool mt7601u_use_hvga(struct mt7601u_dev *dev) | |
785 | { | |
786 | return !(mt7601u_current_tx_power(dev) > 20); | |
787 | } | |
788 | ||
789 | static s16 | |
790 | mt7601u_phy_rf_pa_mode_val(struct mt7601u_dev *dev, int phy_mode, int tx_rate) | |
791 | { | |
792 | static const s16 decode_tb[] = { 0, 8847, -5734, -5734 }; | |
793 | u32 reg; | |
794 | ||
795 | switch (phy_mode) { | |
796 | case MT_PHY_TYPE_OFDM: | |
797 | tx_rate += 4; | |
798 | case MT_PHY_TYPE_CCK: | |
799 | reg = dev->rf_pa_mode[0]; | |
800 | break; | |
801 | default: | |
802 | reg = dev->rf_pa_mode[1]; | |
803 | break; | |
804 | } | |
805 | ||
806 | return decode_tb[(reg >> (tx_rate * 2)) & 0x3]; | |
807 | } | |
808 | ||
809 | static struct mt7601u_tssi_params | |
810 | mt7601u_tssi_params_get(struct mt7601u_dev *dev) | |
811 | { | |
812 | static const u8 ofdm_pkt2rate[8] = { 6, 4, 2, 0, 7, 5, 3, 1 }; | |
813 | static const int static_power[4] = { 0, -49152, -98304, 49152 }; | |
814 | struct mt7601u_tssi_params p; | |
815 | u8 bbp_r47, pkt_type, tx_rate; | |
816 | struct power_per_rate *rate_table; | |
817 | ||
818 | bbp_r47 = mt7601u_bbp_rr(dev, 47); | |
819 | ||
820 | p.tssi0 = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TSSI); | |
821 | dev->raw_temp = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TEMP); | |
822 | pkt_type = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_PKT_T); | |
823 | ||
824 | p.trgt_power = mt7601u_current_tx_power(dev); | |
825 | ||
826 | switch (pkt_type & 0x03) { | |
827 | case MT_PHY_TYPE_CCK: | |
828 | tx_rate = (pkt_type >> 4) & 0x03; | |
829 | rate_table = dev->ee->power_rate_table.cck; | |
830 | break; | |
831 | ||
832 | case MT_PHY_TYPE_OFDM: | |
833 | tx_rate = ofdm_pkt2rate[(pkt_type >> 4) & 0x07]; | |
834 | rate_table = dev->ee->power_rate_table.ofdm; | |
835 | break; | |
836 | ||
837 | default: | |
838 | tx_rate = mt7601u_bbp_r47_get(dev, bbp_r47, BBP_R47_F_TX_RATE); | |
839 | tx_rate &= 0x7f; | |
840 | rate_table = dev->ee->power_rate_table.ht; | |
841 | break; | |
842 | } | |
843 | ||
844 | if (dev->bw == MT_BW_20) | |
845 | p.trgt_power += rate_table[tx_rate / 2].bw20; | |
846 | else | |
847 | p.trgt_power += rate_table[tx_rate / 2].bw40; | |
848 | ||
849 | p.trgt_power <<= 12; | |
850 | ||
851 | dev_dbg(dev->dev, "tx_rate:%02hhx pwr:%08x\n", tx_rate, p.trgt_power); | |
852 | ||
853 | p.trgt_power += mt7601u_phy_rf_pa_mode_val(dev, pkt_type & 0x03, | |
854 | tx_rate); | |
855 | ||
856 | /* Channel 14, cck, bw20 */ | |
857 | if ((pkt_type & 0x03) == MT_PHY_TYPE_CCK) { | |
858 | if (mt7601u_bbp_rr(dev, 4) & 0x20) | |
859 | p.trgt_power += mt7601u_bbp_rr(dev, 178) ? 18022 : 9830; | |
860 | else | |
861 | p.trgt_power += mt7601u_bbp_rr(dev, 178) ? 819 : 24576; | |
862 | } | |
863 | ||
864 | p.trgt_power += static_power[mt7601u_bbp_rr(dev, 1) & 0x03]; | |
865 | ||
866 | p.trgt_power += dev->ee->tssi_data.tx0_delta_offset; | |
867 | ||
868 | dev_dbg(dev->dev, | |
869 | "tssi:%02hhx t_power:%08x temp:%02hhx pkt_type:%02hhx\n", | |
870 | p.tssi0, p.trgt_power, dev->raw_temp, pkt_type); | |
871 | ||
872 | return p; | |
873 | } | |
874 | ||
875 | static bool mt7601u_tssi_read_ready(struct mt7601u_dev *dev) | |
876 | { | |
877 | return !(mt7601u_bbp_rr(dev, 47) & 0x10); | |
878 | } | |
879 | ||
880 | static int mt7601u_tssi_cal(struct mt7601u_dev *dev) | |
881 | { | |
882 | struct mt7601u_tssi_params params; | |
883 | int curr_pwr, diff_pwr; | |
884 | char tssi_offset; | |
885 | s8 tssi_init; | |
886 | s16 tssi_m_dc, tssi_db; | |
887 | bool hvga; | |
888 | u32 val; | |
889 | ||
890 | if (!dev->ee->tssi_enabled) | |
891 | return 0; | |
892 | ||
893 | hvga = mt7601u_use_hvga(dev); | |
894 | if (!dev->tssi_read_trig) | |
895 | return mt7601u_mcu_tssi_read_kick(dev, hvga); | |
896 | ||
897 | if (!mt7601u_tssi_read_ready(dev)) | |
898 | return 0; | |
899 | ||
900 | params = mt7601u_tssi_params_get(dev); | |
901 | ||
902 | tssi_init = (hvga ? dev->tssi_init_hvga : dev->tssi_init); | |
903 | tssi_m_dc = params.tssi0 - tssi_init; | |
904 | tssi_db = lin2dBd(tssi_m_dc); | |
905 | dev_dbg(dev->dev, "tssi dc:%04hx db:%04hx hvga:%d\n", | |
906 | tssi_m_dc, tssi_db, hvga); | |
907 | ||
908 | if (dev->chandef.chan->hw_value < 5) | |
909 | tssi_offset = dev->ee->tssi_data.offset[0]; | |
910 | else if (dev->chandef.chan->hw_value < 9) | |
911 | tssi_offset = dev->ee->tssi_data.offset[1]; | |
912 | else | |
913 | tssi_offset = dev->ee->tssi_data.offset[2]; | |
914 | ||
915 | if (hvga) | |
916 | tssi_db -= dev->tssi_init_hvga_offset_db; | |
917 | ||
918 | curr_pwr = tssi_db * dev->ee->tssi_data.slope + (tssi_offset << 9); | |
919 | diff_pwr = params.trgt_power - curr_pwr; | |
920 | dev_dbg(dev->dev, "Power curr:%08x diff:%08x\n", curr_pwr, diff_pwr); | |
921 | ||
922 | if (params.tssi0 > 126 && diff_pwr > 0) { | |
923 | dev_err(dev->dev, "Error: TSSI upper saturation\n"); | |
924 | diff_pwr = 0; | |
925 | } | |
926 | if (params.tssi0 - tssi_init < 1 && diff_pwr < 0) { | |
927 | dev_err(dev->dev, "Error: TSSI lower saturation\n"); | |
928 | diff_pwr = 0; | |
929 | } | |
930 | ||
931 | if ((dev->prev_pwr_diff ^ diff_pwr) < 0 && abs(diff_pwr) < 4096 && | |
932 | (abs(diff_pwr) > abs(dev->prev_pwr_diff) || | |
933 | (diff_pwr > 0 && diff_pwr == -dev->prev_pwr_diff))) | |
934 | diff_pwr = 0; | |
935 | else | |
936 | dev->prev_pwr_diff = diff_pwr; | |
937 | ||
938 | diff_pwr += (diff_pwr > 0) ? 2048 : -2048; | |
939 | diff_pwr /= 4096; | |
940 | ||
941 | dev_dbg(dev->dev, "final diff: %08x\n", diff_pwr); | |
942 | ||
943 | val = mt7601u_rr(dev, MT_TX_ALC_CFG_1); | |
d43af505 | 944 | curr_pwr = s6_to_int(FIELD_GET(MT_TX_ALC_CFG_1_TEMP_COMP, val)); |
c869f77d JK |
945 | diff_pwr += curr_pwr; |
946 | val = (val & ~MT_TX_ALC_CFG_1_TEMP_COMP) | int_to_s6(diff_pwr); | |
947 | mt7601u_wr(dev, MT_TX_ALC_CFG_1, val); | |
948 | ||
949 | return mt7601u_mcu_tssi_read_kick(dev, hvga); | |
950 | } | |
951 | ||
952 | static u8 mt7601u_agc_default(struct mt7601u_dev *dev) | |
953 | { | |
954 | return (dev->ee->lna_gain - 8) * 2 + 0x34; | |
955 | } | |
956 | ||
957 | static void mt7601u_agc_reset(struct mt7601u_dev *dev) | |
958 | { | |
959 | u8 agc = mt7601u_agc_default(dev); | |
960 | ||
961 | mt7601u_bbp_wr(dev, 66, agc); | |
962 | } | |
963 | ||
964 | void mt7601u_agc_save(struct mt7601u_dev *dev) | |
965 | { | |
966 | dev->agc_save = mt7601u_bbp_rr(dev, 66); | |
967 | } | |
968 | ||
969 | void mt7601u_agc_restore(struct mt7601u_dev *dev) | |
970 | { | |
971 | mt7601u_bbp_wr(dev, 66, dev->agc_save); | |
972 | } | |
973 | ||
974 | static void mt7601u_agc_tune(struct mt7601u_dev *dev) | |
975 | { | |
976 | u8 val = mt7601u_agc_default(dev); | |
977 | ||
978 | if (test_bit(MT7601U_STATE_SCANNING, &dev->state)) | |
979 | return; | |
980 | ||
981 | /* Note: only in STA mode and not dozing; perhaps do this only if | |
982 | * there is enough rssi updates since last run? | |
983 | * Rssi updates are only on beacons and U2M so should work... | |
984 | */ | |
985 | spin_lock_bh(&dev->con_mon_lock); | |
986 | if (dev->avg_rssi <= -70) | |
987 | val -= 0x20; | |
988 | else if (dev->avg_rssi <= -60) | |
989 | val -= 0x10; | |
990 | spin_unlock_bh(&dev->con_mon_lock); | |
991 | ||
992 | if (val != mt7601u_bbp_rr(dev, 66)) | |
993 | mt7601u_bbp_wr(dev, 66, val); | |
994 | ||
995 | /* TODO: also if lost a lot of beacons try resetting | |
996 | * (see RTMPSetAGCInitValue() call in mlme.c). | |
997 | */ | |
998 | } | |
999 | ||
1000 | static void mt7601u_phy_calibrate(struct work_struct *work) | |
1001 | { | |
1002 | struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev, | |
1003 | cal_work.work); | |
1004 | ||
1005 | mt7601u_agc_tune(dev); | |
1006 | mt7601u_tssi_cal(dev); | |
1007 | /* If TSSI calibration was run it already updated temperature. */ | |
1008 | if (!dev->ee->tssi_enabled) | |
1009 | dev->raw_temp = mt7601u_read_temp(dev); | |
1010 | mt7601u_temp_comp(dev, true); /* TODO: find right value for @on */ | |
1011 | ||
1012 | ieee80211_queue_delayed_work(dev->hw, &dev->cal_work, | |
1013 | MT_CALIBRATE_INTERVAL); | |
1014 | } | |
1015 | ||
1016 | static unsigned long | |
1017 | __mt7601u_phy_freq_cal(struct mt7601u_dev *dev, s8 last_offset, u8 phy_mode) | |
1018 | { | |
1019 | u8 activate_threshold, deactivate_threshold; | |
1020 | ||
1021 | trace_freq_cal_offset(dev, phy_mode, last_offset); | |
1022 | ||
1023 | /* No beacons received - reschedule soon */ | |
1024 | if (last_offset == MT_FREQ_OFFSET_INVALID) | |
1025 | return MT_FREQ_CAL_ADJ_INTERVAL; | |
1026 | ||
1027 | switch (phy_mode) { | |
1028 | case MT_PHY_TYPE_CCK: | |
1029 | activate_threshold = 19; | |
1030 | deactivate_threshold = 5; | |
1031 | break; | |
1032 | case MT_PHY_TYPE_OFDM: | |
1033 | activate_threshold = 102; | |
1034 | deactivate_threshold = 32; | |
1035 | break; | |
1036 | case MT_PHY_TYPE_HT: | |
1037 | case MT_PHY_TYPE_HT_GF: | |
1038 | activate_threshold = 82; | |
1039 | deactivate_threshold = 20; | |
1040 | break; | |
1041 | default: | |
1042 | WARN_ON(1); | |
1043 | return MT_FREQ_CAL_CHECK_INTERVAL; | |
1044 | } | |
1045 | ||
1046 | if (abs(last_offset) >= activate_threshold) | |
1047 | dev->freq_cal.adjusting = true; | |
1048 | else if (abs(last_offset) <= deactivate_threshold) | |
1049 | dev->freq_cal.adjusting = false; | |
1050 | ||
1051 | if (!dev->freq_cal.adjusting) | |
1052 | return MT_FREQ_CAL_CHECK_INTERVAL; | |
1053 | ||
1054 | if (last_offset > deactivate_threshold) { | |
1055 | if (dev->freq_cal.freq > 0) | |
1056 | dev->freq_cal.freq--; | |
1057 | else | |
1058 | dev->freq_cal.adjusting = false; | |
1059 | } else if (last_offset < -deactivate_threshold) { | |
1060 | if (dev->freq_cal.freq < 0xbf) | |
1061 | dev->freq_cal.freq++; | |
1062 | else | |
1063 | dev->freq_cal.adjusting = false; | |
1064 | } | |
1065 | ||
1066 | trace_freq_cal_adjust(dev, dev->freq_cal.freq); | |
1067 | mt7601u_rf_wr(dev, 0, 12, dev->freq_cal.freq); | |
1068 | mt7601u_vco_cal(dev); | |
1069 | ||
1070 | return dev->freq_cal.adjusting ? MT_FREQ_CAL_ADJ_INTERVAL : | |
1071 | MT_FREQ_CAL_CHECK_INTERVAL; | |
1072 | } | |
1073 | ||
1074 | static void mt7601u_phy_freq_cal(struct work_struct *work) | |
1075 | { | |
1076 | struct mt7601u_dev *dev = container_of(work, struct mt7601u_dev, | |
1077 | freq_cal.work.work); | |
1078 | s8 last_offset; | |
1079 | u8 phy_mode; | |
1080 | unsigned long delay; | |
1081 | ||
1082 | spin_lock_bh(&dev->con_mon_lock); | |
1083 | last_offset = dev->bcn_freq_off; | |
1084 | phy_mode = dev->bcn_phy_mode; | |
1085 | spin_unlock_bh(&dev->con_mon_lock); | |
1086 | ||
1087 | delay = __mt7601u_phy_freq_cal(dev, last_offset, phy_mode); | |
1088 | ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work, delay); | |
1089 | ||
1090 | spin_lock_bh(&dev->con_mon_lock); | |
1091 | dev->bcn_freq_off = MT_FREQ_OFFSET_INVALID; | |
1092 | spin_unlock_bh(&dev->con_mon_lock); | |
1093 | } | |
1094 | ||
1095 | void mt7601u_phy_con_cal_onoff(struct mt7601u_dev *dev, | |
1096 | struct ieee80211_bss_conf *info) | |
1097 | { | |
1098 | if (!info->assoc) | |
1099 | cancel_delayed_work_sync(&dev->freq_cal.work); | |
1100 | ||
1101 | /* Start/stop collecting beacon data */ | |
1102 | spin_lock_bh(&dev->con_mon_lock); | |
1103 | ether_addr_copy(dev->ap_bssid, info->bssid); | |
1104 | dev->avg_rssi = 0; | |
1105 | dev->bcn_freq_off = MT_FREQ_OFFSET_INVALID; | |
1106 | spin_unlock_bh(&dev->con_mon_lock); | |
1107 | ||
1108 | dev->freq_cal.freq = dev->ee->rf_freq_off; | |
1109 | dev->freq_cal.enabled = info->assoc; | |
1110 | dev->freq_cal.adjusting = false; | |
1111 | ||
1112 | if (info->assoc) | |
1113 | ieee80211_queue_delayed_work(dev->hw, &dev->freq_cal.work, | |
1114 | MT_FREQ_CAL_INIT_DELAY); | |
1115 | } | |
1116 | ||
1117 | static int mt7601u_init_cal(struct mt7601u_dev *dev) | |
1118 | { | |
1119 | u32 mac_ctrl; | |
1120 | int ret; | |
1121 | ||
1122 | dev->raw_temp = mt7601u_read_bootup_temp(dev); | |
1123 | dev->curr_temp = (dev->raw_temp - dev->ee->ref_temp) * | |
1124 | MT_EE_TEMPERATURE_SLOPE; | |
1125 | dev->dpd_temp = dev->curr_temp; | |
1126 | ||
1127 | mac_ctrl = mt7601u_rr(dev, MT_MAC_SYS_CTRL); | |
1128 | ||
1129 | ret = mt7601u_mcu_calibrate(dev, MCU_CAL_R, 0); | |
1130 | if (ret) | |
1131 | return ret; | |
1132 | ||
1133 | ret = mt7601u_rf_rr(dev, 0, 4); | |
1134 | if (ret < 0) | |
1135 | return ret; | |
1136 | ret |= 0x80; | |
1137 | ret = mt7601u_rf_wr(dev, 0, 4, ret); | |
1138 | if (ret) | |
1139 | return ret; | |
1140 | msleep(2); | |
1141 | ||
1142 | ret = mt7601u_mcu_calibrate(dev, MCU_CAL_TXDCOC, 0); | |
1143 | if (ret) | |
1144 | return ret; | |
1145 | ||
1146 | mt7601u_rxdc_cal(dev); | |
1147 | ||
1148 | ret = mt7601u_set_bw_filter(dev, true); | |
1149 | if (ret) | |
1150 | return ret; | |
1151 | ret = mt7601u_mcu_calibrate(dev, MCU_CAL_LOFT, 0); | |
1152 | if (ret) | |
1153 | return ret; | |
1154 | ret = mt7601u_mcu_calibrate(dev, MCU_CAL_TXIQ, 0); | |
1155 | if (ret) | |
1156 | return ret; | |
1157 | ret = mt7601u_mcu_calibrate(dev, MCU_CAL_RXIQ, 0); | |
1158 | if (ret) | |
1159 | return ret; | |
1160 | ret = mt7601u_mcu_calibrate(dev, MCU_CAL_DPD, dev->dpd_temp); | |
1161 | if (ret) | |
1162 | return ret; | |
1163 | ||
1164 | mt7601u_rxdc_cal(dev); | |
1165 | ||
1166 | mt7601u_tssi_dc_gain_cal(dev); | |
1167 | ||
1168 | mt7601u_wr(dev, MT_MAC_SYS_CTRL, mac_ctrl); | |
1169 | ||
1170 | mt7601u_temp_comp(dev, true); | |
1171 | ||
1172 | return 0; | |
1173 | } | |
1174 | ||
1175 | int mt7601u_bbp_set_bw(struct mt7601u_dev *dev, int bw) | |
1176 | { | |
1177 | u32 val, old; | |
1178 | ||
1179 | if (bw == dev->bw) { | |
1180 | /* Vendor driver does the rmc even when no change is needed. */ | |
1181 | mt7601u_bbp_rmc(dev, 4, 0x18, bw == MT_BW_20 ? 0 : 0x10); | |
1182 | ||
1183 | return 0; | |
1184 | } | |
1185 | dev->bw = bw; | |
1186 | ||
1187 | /* Stop MAC for the time of bw change */ | |
1188 | old = mt7601u_rr(dev, MT_MAC_SYS_CTRL); | |
1189 | val = old & ~(MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX); | |
1190 | mt7601u_wr(dev, MT_MAC_SYS_CTRL, val); | |
1191 | mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX | MT_MAC_STATUS_RX, | |
1192 | 0, 500000); | |
1193 | ||
1194 | mt7601u_bbp_rmc(dev, 4, 0x18, bw == MT_BW_20 ? 0 : 0x10); | |
1195 | ||
1196 | mt7601u_wr(dev, MT_MAC_SYS_CTRL, old); | |
1197 | ||
1198 | return mt7601u_load_bbp_temp_table_bw(dev); | |
1199 | } | |
1200 | ||
1201 | /** | |
1202 | * mt7601u_set_rx_path - set rx path in BBP | |
1203 | * @dev: pointer to adapter structure | |
1204 | * @path: rx path to set values are 0-based | |
1205 | */ | |
1206 | void mt7601u_set_rx_path(struct mt7601u_dev *dev, u8 path) | |
1207 | { | |
1208 | mt7601u_bbp_rmw(dev, 3, 0x18, path << 3); | |
1209 | } | |
1210 | ||
1211 | /** | |
1212 | * mt7601u_set_tx_dac - set which tx DAC to use | |
1213 | * @dev: pointer to adapter structure | |
1214 | * @path: DAC index, values are 0-based | |
1215 | */ | |
1216 | void mt7601u_set_tx_dac(struct mt7601u_dev *dev, u8 dac) | |
1217 | { | |
1218 | mt7601u_bbp_rmc(dev, 1, 0x18, dac << 3); | |
1219 | } | |
1220 | ||
1221 | int mt7601u_phy_init(struct mt7601u_dev *dev) | |
1222 | { | |
1223 | int ret; | |
1224 | ||
1225 | dev->rf_pa_mode[0] = mt7601u_rr(dev, MT_RF_PA_MODE_CFG0); | |
1226 | dev->rf_pa_mode[1] = mt7601u_rr(dev, MT_RF_PA_MODE_CFG1); | |
1227 | ||
1228 | ret = mt7601u_rf_wr(dev, 0, 12, dev->ee->rf_freq_off); | |
1229 | if (ret) | |
1230 | return ret; | |
1231 | ret = mt7601u_write_reg_pairs(dev, 0, rf_central, | |
1232 | ARRAY_SIZE(rf_central)); | |
1233 | if (ret) | |
1234 | return ret; | |
1235 | ret = mt7601u_write_reg_pairs(dev, 0, rf_channel, | |
1236 | ARRAY_SIZE(rf_channel)); | |
1237 | if (ret) | |
1238 | return ret; | |
1239 | ret = mt7601u_write_reg_pairs(dev, 0, rf_vga, ARRAY_SIZE(rf_vga)); | |
1240 | if (ret) | |
1241 | return ret; | |
1242 | ||
1243 | ret = mt7601u_init_cal(dev); | |
1244 | if (ret) | |
1245 | return ret; | |
1246 | ||
1247 | dev->prev_pwr_diff = 100; | |
1248 | ||
1249 | INIT_DELAYED_WORK(&dev->cal_work, mt7601u_phy_calibrate); | |
1250 | INIT_DELAYED_WORK(&dev->freq_cal.work, mt7601u_phy_freq_cal); | |
1251 | ||
1252 | return 0; | |
1253 | } |