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Merge remote-tracking branch 'lightnvm/for-next'
[deliverable/linux.git] / drivers / net / wireless / realtek / rtl8xxxu / rtl8xxxu_core.c
CommitLineData
26f1fad2
JS		 1/*
2 * RTL8XXXU mac80211 USB driver
3 *
eb188062 4 * Copyright (c) 2014 - 2016 Jes Sorensen <Jes.Sorensen@redhat.com>
26f1fad2
JS		 5 *
6 * Portions, notably calibration code:
7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
8 *
9 * This driver was written as a replacement for the vendor provided
10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
11 * their programming interface, I have started adding support for
12 * additional 8xxx chips like the 8192cu, 8188cus, etc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of version 2 of the GNU General Public License as
16 * published by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * more details.
22 */
23
24#include <linux/init.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/errno.h>
28#include <linux/slab.h>
29#include <linux/module.h>
30#include <linux/spinlock.h>
31#include <linux/list.h>
32#include <linux/usb.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/wireless.h>
37#include <linux/firmware.h>
38#include <linux/moduleparam.h>
39#include <net/mac80211.h>
40#include "rtl8xxxu.h"
41#include "rtl8xxxu_regs.h"
42
43#define DRIVER_NAME "rtl8xxxu"
44
599119f6 45int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
26f1fad2 46static bool rtl8xxxu_ht40_2g;
82cce22a 47static bool rtl8xxxu_dma_aggregation;
fd83f122
JS		 48static int rtl8xxxu_dma_agg_timeout = -1;
49static int rtl8xxxu_dma_agg_pages = -1;
26f1fad2
JS		 50
51MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
52MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
53MODULE_LICENSE("GPL");
54MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
55MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
56MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
57MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
58MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
59MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
b001e086 60MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
35a741fe
JS		 61MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
62MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
26f1fad2
JS		 63
64module_param_named(debug, rtl8xxxu_debug, int, 0600);
65MODULE_PARM_DESC(debug, "Set debug mask");
66module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
67MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
82cce22a
JS		 68module_param_named(dma_aggregation, rtl8xxxu_dma_aggregation, bool, 0600);
69MODULE_PARM_DESC(dma_aggregation, "Enable DMA packet aggregation");
fd83f122
JS		 70module_param_named(dma_agg_timeout, rtl8xxxu_dma_agg_timeout, int, 0600);
71MODULE_PARM_DESC(dma_agg_timeout, "Set DMA aggregation timeout (range 1-127)");
72module_param_named(dma_agg_pages, rtl8xxxu_dma_agg_pages, int, 0600);
73MODULE_PARM_DESC(dma_agg_pages, "Set DMA aggregation pages (range 1-127, 0 to disable)");
26f1fad2
JS		 74
75#define USB_VENDOR_ID_REALTEK 0x0bda
26f1fad2
JS		 76#define RTL8XXXU_RX_URBS 32
77#define RTL8XXXU_RX_URB_PENDING_WATER 8
78#define RTL8XXXU_TX_URBS 64
79#define RTL8XXXU_TX_URB_LOW_WATER 25
80#define RTL8XXXU_TX_URB_HIGH_WATER 32
81
82static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
83 struct rtl8xxxu_rx_urb *rx_urb);
84
85static struct ieee80211_rate rtl8xxxu_rates[] = {
86 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
87 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
88 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
89 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
90 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
91 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
92 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
93 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
94 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
95 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
96 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
97 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
98};
99
100static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
57fbcce3 101 { .band = NL80211_BAND_2GHZ, .center_freq = 2412,
26f1fad2 102 .hw_value = 1, .max_power = 30 },
57fbcce3 103 { .band = NL80211_BAND_2GHZ, .center_freq = 2417,
26f1fad2 104 .hw_value = 2, .max_power = 30 },
57fbcce3 105 { .band = NL80211_BAND_2GHZ, .center_freq = 2422,
26f1fad2 106 .hw_value = 3, .max_power = 30 },
57fbcce3 107 { .band = NL80211_BAND_2GHZ, .center_freq = 2427,
26f1fad2 108 .hw_value = 4, .max_power = 30 },
57fbcce3 109 { .band = NL80211_BAND_2GHZ, .center_freq = 2432,
26f1fad2 110 .hw_value = 5, .max_power = 30 },
57fbcce3 111 { .band = NL80211_BAND_2GHZ, .center_freq = 2437,
26f1fad2 112 .hw_value = 6, .max_power = 30 },
57fbcce3 113 { .band = NL80211_BAND_2GHZ, .center_freq = 2442,
26f1fad2 114 .hw_value = 7, .max_power = 30 },
57fbcce3 115 { .band = NL80211_BAND_2GHZ, .center_freq = 2447,
26f1fad2 116 .hw_value = 8, .max_power = 30 },
57fbcce3 117 { .band = NL80211_BAND_2GHZ, .center_freq = 2452,
26f1fad2 118 .hw_value = 9, .max_power = 30 },
57fbcce3 119 { .band = NL80211_BAND_2GHZ, .center_freq = 2457,
26f1fad2 120 .hw_value = 10, .max_power = 30 },
57fbcce3 121 { .band = NL80211_BAND_2GHZ, .center_freq = 2462,
26f1fad2 122 .hw_value = 11, .max_power = 30 },
57fbcce3 123 { .band = NL80211_BAND_2GHZ, .center_freq = 2467,
26f1fad2 124 .hw_value = 12, .max_power = 30 },
57fbcce3 125 { .band = NL80211_BAND_2GHZ, .center_freq = 2472,
26f1fad2 126 .hw_value = 13, .max_power = 30 },
57fbcce3 127 { .band = NL80211_BAND_2GHZ, .center_freq = 2484,
26f1fad2
JS		 128 .hw_value = 14, .max_power = 30 }
129};
130
131static struct ieee80211_supported_band rtl8xxxu_supported_band = {
132 .channels = rtl8xxxu_channels_2g,
133 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
134 .bitrates = rtl8xxxu_rates,
135 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
136};
137
20e3b2e9 138struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[] = {
26f1fad2
JS		 139 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
140 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
141 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
142 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
143 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
144 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
145 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
146 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
147 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
148 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
149 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
150 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
151 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
152 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
153 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
154 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
155 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
156 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
157 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
158 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
159 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
160 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
161};
162
163static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
164 {0x800, 0x80040000}, {0x804, 0x00000003},
165 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
166 {0x810, 0x10001331}, {0x814, 0x020c3d10},
167 {0x818, 0x02200385}, {0x81c, 0x00000000},
168 {0x820, 0x01000100}, {0x824, 0x00390004},
169 {0x828, 0x00000000}, {0x82c, 0x00000000},
170 {0x830, 0x00000000}, {0x834, 0x00000000},
171 {0x838, 0x00000000}, {0x83c, 0x00000000},
172 {0x840, 0x00010000}, {0x844, 0x00000000},
173 {0x848, 0x00000000}, {0x84c, 0x00000000},
174 {0x850, 0x00000000}, {0x854, 0x00000000},
175 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
176 {0x860, 0x66f60110}, {0x864, 0x061f0130},
177 {0x868, 0x00000000}, {0x86c, 0x32323200},
178 {0x870, 0x07000760}, {0x874, 0x22004000},
179 {0x878, 0x00000808}, {0x87c, 0x00000000},
180 {0x880, 0xc0083070}, {0x884, 0x000004d5},
181 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
182 {0x890, 0x00000800}, {0x894, 0xfffffffe},
183 {0x898, 0x40302010}, {0x89c, 0x00706050},
184 {0x900, 0x00000000}, {0x904, 0x00000023},
185 {0x908, 0x00000000}, {0x90c, 0x81121111},
186 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
187 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
188 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
189 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
190 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
191 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
192 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
193 {0xa78, 0x00000900},
194 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
195 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
196 {0xc10, 0x08800000}, {0xc14, 0x40000100},
197 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
198 {0xc20, 0x00000000}, {0xc24, 0x00000000},
199 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
200 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
201 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
202 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
203 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
204 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
205 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
206 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
207 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
208 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
209 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
210 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
211 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
212 {0xc90, 0x00121820}, {0xc94, 0x00000000},
213 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
214 {0xca0, 0x00000000}, {0xca4, 0x00000080},
215 {0xca8, 0x00000000}, {0xcac, 0x00000000},
216 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
217 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
218 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
219 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
220 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
221 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
222 {0xce0, 0x00222222}, {0xce4, 0x00000000},
223 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
224 {0xd00, 0x00080740}, {0xd04, 0x00020401},
225 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
226 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
227 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
228 {0xd30, 0x00000000}, {0xd34, 0x80608000},
229 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
230 {0xd40, 0x00000000}, {0xd44, 0x00000000},
231 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
232 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
233 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
234 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
235 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
236 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
237 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
238 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
239 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
240 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
241 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
242 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
243 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
244 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
245 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
246 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
247 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
248 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
249 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
250 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
251 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
252 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
253 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
254 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
255 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
256 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
257 {0xf00, 0x00000300},
258 {0xffff, 0xffffffff},
259};
260
261static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
262 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
263 {0x800, 0x80040002}, {0x804, 0x00000003},
264 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
265 {0x810, 0x10000330}, {0x814, 0x020c3d10},
266 {0x818, 0x02200385}, {0x81c, 0x00000000},
267 {0x820, 0x01000100}, {0x824, 0x00390004},
268 {0x828, 0x01000100}, {0x82c, 0x00390004},
269 {0x830, 0x27272727}, {0x834, 0x27272727},
270 {0x838, 0x27272727}, {0x83c, 0x27272727},
271 {0x840, 0x00010000}, {0x844, 0x00010000},
272 {0x848, 0x27272727}, {0x84c, 0x27272727},
273 {0x850, 0x00000000}, {0x854, 0x00000000},
274 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
275 {0x860, 0x66e60230}, {0x864, 0x061f0130},
276 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
277 {0x870, 0x07000700}, {0x874, 0x22184000},
278 {0x878, 0x08080808}, {0x87c, 0x00000000},
279 {0x880, 0xc0083070}, {0x884, 0x000004d5},
280 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
281 {0x890, 0x00000800}, {0x894, 0xfffffffe},
282 {0x898, 0x40302010}, {0x89c, 0x00706050},
283 {0x900, 0x00000000}, {0x904, 0x00000023},
284 {0x908, 0x00000000}, {0x90c, 0x81121313},
285 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
286 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
287 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
288 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
289 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
290 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
291 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
292 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
293 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
294 {0xc10, 0x08800000}, {0xc14, 0x40000100},
295 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
296 {0xc20, 0x00000000}, {0xc24, 0x00000000},
297 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
298 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
299 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
300 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
301 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
302 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
303 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
304 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
305 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
306 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
307 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
308 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
309 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
310 {0xc90, 0x00121820}, {0xc94, 0x00000000},
311 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
312 {0xca0, 0x00000000}, {0xca4, 0x00000080},
313 {0xca8, 0x00000000}, {0xcac, 0x00000000},
314 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
315 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
316 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
317 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
318 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
319 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
320 {0xce0, 0x00222222}, {0xce4, 0x00000000},
321 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
322 {0xd00, 0x00080740}, {0xd04, 0x00020403},
323 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
324 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
325 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
326 {0xd30, 0x00000000}, {0xd34, 0x80608000},
327 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
328 {0xd40, 0x00000000}, {0xd44, 0x00000000},
329 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
330 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
331 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
332 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
333 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
334 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
335 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
336 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
337 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
338 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
339 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
340 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
341 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
342 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
343 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
344 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
345 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
346 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
347 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
348 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
349 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
350 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
351 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
352 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
353 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
354 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
355 {0xf00, 0x00000300},
356 {0xffff, 0xffffffff},
357};
358
359static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
360 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
361 {0x040, 0x000c0004}, {0x800, 0x80040000},
362 {0x804, 0x00000001}, {0x808, 0x0000fc00},
363 {0x80c, 0x0000000a}, {0x810, 0x10005388},
364 {0x814, 0x020c3d10}, {0x818, 0x02200385},
365 {0x81c, 0x00000000}, {0x820, 0x01000100},
366 {0x824, 0x00390204}, {0x828, 0x00000000},
367 {0x82c, 0x00000000}, {0x830, 0x00000000},
368 {0x834, 0x00000000}, {0x838, 0x00000000},
369 {0x83c, 0x00000000}, {0x840, 0x00010000},
370 {0x844, 0x00000000}, {0x848, 0x00000000},
371 {0x84c, 0x00000000}, {0x850, 0x00000000},
372 {0x854, 0x00000000}, {0x858, 0x569a569a},
373 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
374 {0x864, 0x061f0130}, {0x868, 0x00000000},
375 {0x86c, 0x20202000}, {0x870, 0x03000300},
376 {0x874, 0x22004000}, {0x878, 0x00000808},
377 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
378 {0x884, 0x000004d5}, {0x888, 0x00000000},
379 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
380 {0x894, 0xfffffffe}, {0x898, 0x40302010},
381 {0x89c, 0x00706050}, {0x900, 0x00000000},
382 {0x904, 0x00000023}, {0x908, 0x00000000},
383 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
384 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
385 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
386 {0xa14, 0x11144028}, {0xa18, 0x00881117},
387 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
388 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
389 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
390 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
391 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
392 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
393 {0xc14, 0x40000100}, {0xc18, 0x08800000},
394 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
395 {0xc24, 0x00000000}, {0xc28, 0x00000000},
396 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
397 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
398 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
399 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
400 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
401 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
402 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
403 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
404 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
405 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
406 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
407 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
408 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
409 {0xc94, 0x00000000}, {0xc98, 0x00121820},
410 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
411 {0xca4, 0x00000080}, {0xca8, 0x00000000},
412 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
413 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
414 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
415 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
416 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
417 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
418 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
419 {0xce4, 0x00000000}, {0xce8, 0x37644302},
420 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
421 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
422 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
423 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
424 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
425 {0xd34, 0x80608000}, {0xd38, 0x00000000},
426 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
427 {0xd44, 0x00000000}, {0xd48, 0x00000000},
428 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
429 {0xd54, 0x00000000}, {0xd58, 0x00000000},
430 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
431 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
432 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
433 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
434 {0xe00, 0x24242424}, {0xe04, 0x24242424},
435 {0xe08, 0x03902024}, {0xe10, 0x24242424},
436 {0xe14, 0x24242424}, {0xe18, 0x24242424},
437 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
438 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
439 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
440 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
441 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
442 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
443 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
444 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
445 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
446 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
447 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
448 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
449 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
450 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
451 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
452 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
453 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
454 {0xf00, 0x00000300},
455 {0xffff, 0xffffffff},
456};
457
458static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
459 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
460 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
461 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
462 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
463 {0xc78, 0x78080001}, {0xc78, 0x77090001},
464 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
465 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
466 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
467 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
468 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
469 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
470 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
471 {0xc78, 0x68180001}, {0xc78, 0x67190001},
472 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
473 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
474 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
475 {0xc78, 0x60200001}, {0xc78, 0x49210001},
476 {0xc78, 0x48220001}, {0xc78, 0x47230001},
477 {0xc78, 0x46240001}, {0xc78, 0x45250001},
478 {0xc78, 0x44260001}, {0xc78, 0x43270001},
479 {0xc78, 0x42280001}, {0xc78, 0x41290001},
480 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
481 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
482 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
483 {0xc78, 0x21300001}, {0xc78, 0x20310001},
484 {0xc78, 0x06320001}, {0xc78, 0x05330001},
485 {0xc78, 0x04340001}, {0xc78, 0x03350001},
486 {0xc78, 0x02360001}, {0xc78, 0x01370001},
487 {0xc78, 0x00380001}, {0xc78, 0x00390001},
488 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
489 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
490 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
491 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
492 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
493 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
494 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
495 {0xc78, 0x78480001}, {0xc78, 0x77490001},
496 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
497 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
498 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
499 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
500 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
501 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
502 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
503 {0xc78, 0x68580001}, {0xc78, 0x67590001},
504 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
505 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
506 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
507 {0xc78, 0x60600001}, {0xc78, 0x49610001},
508 {0xc78, 0x48620001}, {0xc78, 0x47630001},
509 {0xc78, 0x46640001}, {0xc78, 0x45650001},
510 {0xc78, 0x44660001}, {0xc78, 0x43670001},
511 {0xc78, 0x42680001}, {0xc78, 0x41690001},
512 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
513 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
514 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
515 {0xc78, 0x21700001}, {0xc78, 0x20710001},
516 {0xc78, 0x06720001}, {0xc78, 0x05730001},
517 {0xc78, 0x04740001}, {0xc78, 0x03750001},
518 {0xc78, 0x02760001}, {0xc78, 0x01770001},
519 {0xc78, 0x00780001}, {0xc78, 0x00790001},
520 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
521 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
522 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
523 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
524 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
525 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
526 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
527 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
528 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
529 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
530 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
531 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
532 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
533 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
534 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
535 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
536 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
537 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
538 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
539 {0xffff, 0xffffffff}
540};
541
542static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
543 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
544 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
545 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
546 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
547 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
548 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
549 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
550 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
551 {0xc78, 0x73100001}, {0xc78, 0x72110001},
552 {0xc78, 0x71120001}, {0xc78, 0x70130001},
553 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
554 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
555 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
556 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
557 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
558 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
559 {0xc78, 0x63200001}, {0xc78, 0x62210001},
560 {0xc78, 0x61220001}, {0xc78, 0x60230001},
561 {0xc78, 0x46240001}, {0xc78, 0x45250001},
562 {0xc78, 0x44260001}, {0xc78, 0x43270001},
563 {0xc78, 0x42280001}, {0xc78, 0x41290001},
564 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
565 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
566 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
567 {0xc78, 0x21300001}, {0xc78, 0x20310001},
568 {0xc78, 0x06320001}, {0xc78, 0x05330001},
569 {0xc78, 0x04340001}, {0xc78, 0x03350001},
570 {0xc78, 0x02360001}, {0xc78, 0x01370001},
571 {0xc78, 0x00380001}, {0xc78, 0x00390001},
572 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
573 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
574 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
575 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
576 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
577 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
578 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
579 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
580 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
581 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
582 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
583 {0xc78, 0x73500001}, {0xc78, 0x72510001},
584 {0xc78, 0x71520001}, {0xc78, 0x70530001},
585 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
586 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
587 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
588 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
589 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
590 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
591 {0xc78, 0x63600001}, {0xc78, 0x62610001},
592 {0xc78, 0x61620001}, {0xc78, 0x60630001},
593 {0xc78, 0x46640001}, {0xc78, 0x45650001},
594 {0xc78, 0x44660001}, {0xc78, 0x43670001},
595 {0xc78, 0x42680001}, {0xc78, 0x41690001},
596 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
597 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
598 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
599 {0xc78, 0x21700001}, {0xc78, 0x20710001},
600 {0xc78, 0x06720001}, {0xc78, 0x05730001},
601 {0xc78, 0x04740001}, {0xc78, 0x03750001},
602 {0xc78, 0x02760001}, {0xc78, 0x01770001},
603 {0xc78, 0x00780001}, {0xc78, 0x00790001},
604 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
605 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
606 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
607 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
608 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
609 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
610 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
611 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
612 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
613 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
614 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
615 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
616 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
617 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
618 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
619 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
620 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
621 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
622 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
623 {0xffff, 0xffffffff}
624};
625
26f1fad2
JS		 626static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
627 { /* RF_A */
628 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
629 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
630 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
631 .hspiread = REG_HSPI_XA_READBACK,
632 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
633 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
634 },
635 { /* RF_B */
636 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
637 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
638 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
639 .hspiread = REG_HSPI_XB_READBACK,
640 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
641 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
642 },
643};
644
599119f6 645const u32 rtl8xxxu_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
26f1fad2
JS		 646 REG_OFDM0_XA_RX_IQ_IMBALANCE,
647 REG_OFDM0_XB_RX_IQ_IMBALANCE,
648 REG_OFDM0_ENERGY_CCA_THRES,
649 REG_OFDM0_AGCR_SSI_TABLE,
650 REG_OFDM0_XA_TX_IQ_IMBALANCE,
651 REG_OFDM0_XB_TX_IQ_IMBALANCE,
652 REG_OFDM0_XC_TX_AFE,
653 REG_OFDM0_XD_TX_AFE,
654 REG_OFDM0_RX_IQ_EXT_ANTA
655};
656
599119f6 657u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
26f1fad2
JS		 658{
659 struct usb_device *udev = priv->udev;
660 int len;
661 u8 data;
662
663 mutex_lock(&priv->usb_buf_mutex);
664 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
665 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
666 addr, 0, &priv->usb_buf.val8, sizeof(u8),
667 RTW_USB_CONTROL_MSG_TIMEOUT);
668 data = priv->usb_buf.val8;
669 mutex_unlock(&priv->usb_buf_mutex);
670
671 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
672 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",
673 __func__, addr, data, len);
674 return data;
675}
676
599119f6 677u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
26f1fad2
JS		 678{
679 struct usb_device *udev = priv->udev;
680 int len;
681 u16 data;
682
683 mutex_lock(&priv->usb_buf_mutex);
684 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
685 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
686 addr, 0, &priv->usb_buf.val16, sizeof(u16),
687 RTW_USB_CONTROL_MSG_TIMEOUT);
688 data = le16_to_cpu(priv->usb_buf.val16);
689 mutex_unlock(&priv->usb_buf_mutex);
690
691 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
692 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",
693 __func__, addr, data, len);
694 return data;
695}
696
599119f6 697u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
26f1fad2
JS		 698{
699 struct usb_device *udev = priv->udev;
700 int len;
701 u32 data;
702
703 mutex_lock(&priv->usb_buf_mutex);
704 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
705 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
706 addr, 0, &priv->usb_buf.val32, sizeof(u32),
707 RTW_USB_CONTROL_MSG_TIMEOUT);
708 data = le32_to_cpu(priv->usb_buf.val32);
709 mutex_unlock(&priv->usb_buf_mutex);
710
711 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
712 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",
713 __func__, addr, data, len);
714 return data;
715}
716
599119f6 717int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
26f1fad2
JS		 718{
719 struct usb_device *udev = priv->udev;
720 int ret;
721
722 mutex_lock(&priv->usb_buf_mutex);
723 priv->usb_buf.val8 = val;
724 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
725 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
726 addr, 0, &priv->usb_buf.val8, sizeof(u8),
727 RTW_USB_CONTROL_MSG_TIMEOUT);
728
729 mutex_unlock(&priv->usb_buf_mutex);
730
731 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
732 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
733 __func__, addr, val);
734 return ret;
735}
736
599119f6 737int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
26f1fad2
JS		 738{
739 struct usb_device *udev = priv->udev;
740 int ret;
741
742 mutex_lock(&priv->usb_buf_mutex);
743 priv->usb_buf.val16 = cpu_to_le16(val);
744 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
745 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
746 addr, 0, &priv->usb_buf.val16, sizeof(u16),
747 RTW_USB_CONTROL_MSG_TIMEOUT);
748 mutex_unlock(&priv->usb_buf_mutex);
749
750 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
751 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
752 __func__, addr, val);
753 return ret;
754}
755
599119f6 756int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
26f1fad2
JS		 757{
758 struct usb_device *udev = priv->udev;
759 int ret;
760
761 mutex_lock(&priv->usb_buf_mutex);
762 priv->usb_buf.val32 = cpu_to_le32(val);
763 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
764 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
765 addr, 0, &priv->usb_buf.val32, sizeof(u32),
766 RTW_USB_CONTROL_MSG_TIMEOUT);
767 mutex_unlock(&priv->usb_buf_mutex);
768
769 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
770 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
771 __func__, addr, val);
772 return ret;
773}
774
775static int
776rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
777{
778 struct usb_device *udev = priv->udev;
779 int blocksize = priv->fops->writeN_block_size;
780 int ret, i, count, remainder;
781
782 count = len / blocksize;
783 remainder = len % blocksize;
784
785 for (i = 0; i < count; i++) {
786 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
787 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
788 addr, 0, buf, blocksize,
789 RTW_USB_CONTROL_MSG_TIMEOUT);
790 if (ret != blocksize)
791 goto write_error;
792
793 addr += blocksize;
794 buf += blocksize;
795 }
796
797 if (remainder) {
798 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
799 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
800 addr, 0, buf, remainder,
801 RTW_USB_CONTROL_MSG_TIMEOUT);
802 if (ret != remainder)
803 goto write_error;
804 }
805
806 return len;
807
808write_error:
809 dev_info(&udev->dev,
810 "%s: Failed to write block at addr: %04x size: %04x\n",
811 __func__, addr, blocksize);
812 return -EAGAIN;
813}
814
599119f6
JS		 815u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
816 enum rtl8xxxu_rfpath path, u8 reg)
26f1fad2
JS		 817{
818 u32 hssia, val32, retval;
819
820 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
821 if (path != RF_A)
822 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
823 else
824 val32 = hssia;
825
826 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
827 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
828 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
829 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
830 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
831
832 udelay(10);
833
834 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
835 udelay(100);
836
837 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
838 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
839 udelay(10);
840
841 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
842 if (val32 & FPGA0_HSSI_PARM1_PI)
843 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
844 else
845 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
846
847 retval &= 0xfffff;
848
849 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
850 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
851 __func__, reg, retval);
852 return retval;
853}
854
22a31d45
JS		 855/*
856 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
857 * have write issues in high temperature conditions. We may have to
858 * retry writing them.
859 */
599119f6
JS		 860int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
861 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
26f1fad2
JS		 862{
863 int ret, retval;
2949b9ee 864 u32 dataaddr, val32;
26f1fad2
JS		 865
866 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
867 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
868 __func__, reg, data);
869
870 data &= FPGA0_LSSI_PARM_DATA_MASK;
871 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
872
2949b9ee
JS		 873 if (priv->rtl_chip == RTL8192E) {
874 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
875 val32 &= ~0x20000;
876 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
877 }
878
26f1fad2
JS		 879 /* Use XB for path B */
880 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
881 if (ret != sizeof(dataaddr))
882 retval = -EIO;
883 else
884 retval = 0;
885
886 udelay(1);
887
2949b9ee
JS		 888 if (priv->rtl_chip == RTL8192E) {
889 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
890 val32 |= 0x20000;
891 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
892 }
893
26f1fad2
JS		 894 return retval;
895}
896
77e39802 897static int
9c0343d4 898rtl8xxxu_gen1_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len)
26f1fad2
JS		 899{
900 struct device *dev = &priv->udev->dev;
901 int mbox_nr, retry, retval = 0;
902 int mbox_reg, mbox_ext_reg;
903 u8 val8;
904
905 mutex_lock(&priv->h2c_mutex);
906
907 mbox_nr = priv->next_mbox;
908 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
9c0343d4 909 mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2);
26f1fad2
JS		 910
911 /*
912 * MBOX ready?
913 */
914 retry = 100;
915 do {
916 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
917 if (!(val8 & BIT(mbox_nr)))
918 break;
919 } while (retry--);
920
921 if (!retry) {
c7a5a190 922 dev_info(dev, "%s: Mailbox busy\n", __func__);
26f1fad2
JS		 923 retval = -EBUSY;
924 goto error;
925 }
926
927 /*
928 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
929 */
8da91571 930 if (len > sizeof(u32)) {
9c0343d4
JS		 931 rtl8xxxu_write16(priv, mbox_ext_reg, le16_to_cpu(h2c->raw.ext));
932 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
933 dev_info(dev, "H2C_EXT %04x\n",
934 le16_to_cpu(h2c->raw.ext));
935 }
936 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
937 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
938 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
939
940 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
941
942error:
943 mutex_unlock(&priv->h2c_mutex);
944 return retval;
945}
946
947int
948rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len)
949{
950 struct device *dev = &priv->udev->dev;
951 int mbox_nr, retry, retval = 0;
952 int mbox_reg, mbox_ext_reg;
953 u8 val8;
954
955 mutex_lock(&priv->h2c_mutex);
956
957 mbox_nr = priv->next_mbox;
958 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
959 mbox_ext_reg = REG_HMBOX_EXT0_8723B + (mbox_nr * 4);
960
961 /*
962 * MBOX ready?
963 */
964 retry = 100;
965 do {
966 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
967 if (!(val8 & BIT(mbox_nr)))
968 break;
969 } while (retry--);
970
971 if (!retry) {
972 dev_info(dev, "%s: Mailbox busy\n", __func__);
973 retval = -EBUSY;
974 goto error;
975 }
976
977 /*
978 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
979 */
980 if (len > sizeof(u32)) {
981 rtl8xxxu_write32(priv, mbox_ext_reg,
982 le32_to_cpu(h2c->raw_wide.ext));
983 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
984 dev_info(dev, "H2C_EXT %08x\n",
985 le32_to_cpu(h2c->raw_wide.ext));
26f1fad2
JS		 986 }
987 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
988 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
989 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
990
991 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
992
993error:
994 mutex_unlock(&priv->h2c_mutex);
995 return retval;
996}
997
20e3b2e9 998void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv)
26f1fad2
JS		 999{
1000 u8 val8;
1001 u32 val32;
1002
1003 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1004 val8 |= BIT(0) | BIT(3);
1005 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1006
1007 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1008 val32 &= ~(BIT(4) | BIT(5));
1009 val32 |= BIT(3);
1010 if (priv->rf_paths == 2) {
1011 val32 &= ~(BIT(20) | BIT(21));
1012 val32 |= BIT(19);
1013 }
1014 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1015
1016 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1017 val32 &= ~OFDM_RF_PATH_TX_MASK;
1018 if (priv->tx_paths == 2)
1019 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
ba17d824 1020 else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C)
26f1fad2
JS		 1021 val32 |= OFDM_RF_PATH_TX_B;
1022 else
1023 val32 |= OFDM_RF_PATH_TX_A;
1024 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1025
1026 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1027 val32 &= ~FPGA_RF_MODE_JAPAN;
1028 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1029
1030 if (priv->rf_paths == 2)
1031 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1032 else
1033 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1034
1035 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1036 if (priv->rf_paths == 2)
1037 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1038
1039 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1040}
1041
20e3b2e9 1042void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv)
26f1fad2
JS		 1043{
1044 u8 sps0;
1045 u32 val32;
1046
26f1fad2
JS		 1047 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1048
1049 /* RF RX code for preamble power saving */
1050 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1051 val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1052 if (priv->rf_paths == 2)
1053 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1054 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1055
1056 /* Disable TX for four paths */
1057 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1058 val32 &= ~OFDM_RF_PATH_TX_MASK;
1059 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1060
1061 /* Enable power saving */
1062 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1063 val32 |= FPGA_RF_MODE_JAPAN;
1064 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1065
1066 /* AFE control register to power down bits [30:22] */
1067 if (priv->rf_paths == 2)
1068 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1069 else
1070 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1071
1072 /* Power down RF module */
1073 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1074 if (priv->rf_paths == 2)
1075 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1076
1077 sps0 &= ~(BIT(0) | BIT(3));
1078 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1079}
1080
97db5a87 1081static void rtl8xxxu_stop_tx_beacon(struct rtl8xxxu_priv *priv)
26f1fad2
JS		 1082{
1083 u8 val8;
1084
1085 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1086 val8 &= ~BIT(6);
1087 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1088
1089 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1090 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1091 val8 &= ~BIT(0);
1092 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1093}
1094
1095
1096/*
1097 * The rtl8723a has 3 channel groups for it's efuse settings. It only
1098 * supports the 2.4GHz band, so channels 1 - 14:
1099 * group 0: channels 1 - 3
1100 * group 1: channels 4 - 9
1101 * group 2: channels 10 - 14
1102 *
1103 * Note: We index from 0 in the code
1104 */
a46b099c 1105static int rtl8xxxu_gen1_channel_to_group(int channel)
26f1fad2
JS		 1106{
1107 int group;
1108
1109 if (channel < 4)
1110 group = 0;
1111 else if (channel < 10)
1112 group = 1;
1113 else
1114 group = 2;
1115
1116 return group;
1117}
1118
9e24772a
JS		 1119/*
1120 * Valid for rtl8723bu and rtl8192eu
1121 */
599119f6 1122int rtl8xxxu_gen2_channel_to_group(int channel)
e796dab4
JS		 1123{
1124 int group;
1125
1126 if (channel < 3)
1127 group = 0;
1128 else if (channel < 6)
1129 group = 1;
1130 else if (channel < 9)
1131 group = 2;
1132 else if (channel < 12)
1133 group = 3;
1134 else
1135 group = 4;
1136
1137 return group;
1138}
1139
20e3b2e9 1140void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw)
26f1fad2
JS		 1141{
1142 struct rtl8xxxu_priv *priv = hw->priv;
1143 u32 val32, rsr;
1144 u8 val8, opmode;
1145 bool ht = true;
1146 int sec_ch_above, channel;
1147 int i;
1148
1149 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1150 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1151 channel = hw->conf.chandef.chan->hw_value;
1152
1153 switch (hw->conf.chandef.width) {
1154 case NL80211_CHAN_WIDTH_20_NOHT:
1155 ht = false;
1156 case NL80211_CHAN_WIDTH_20:
1157 opmode |= BW_OPMODE_20MHZ;
1158 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1159
1160 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1161 val32 &= ~FPGA_RF_MODE;
1162 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1163
1164 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1165 val32 &= ~FPGA_RF_MODE;
1166 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1167
1168 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1169 val32 |= FPGA0_ANALOG2_20MHZ;
1170 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1171 break;
1172 case NL80211_CHAN_WIDTH_40:
1173 if (hw->conf.chandef.center_freq1 >
1174 hw->conf.chandef.chan->center_freq) {
1175 sec_ch_above = 1;
1176 channel += 2;
1177 } else {
1178 sec_ch_above = 0;
1179 channel -= 2;
1180 }
1181
1182 opmode &= ~BW_OPMODE_20MHZ;
1183 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1184 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1185 if (sec_ch_above)
1186 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1187 else
1188 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1189 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1190
1191 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1192 val32 |= FPGA_RF_MODE;
1193 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1194
1195 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1196 val32 |= FPGA_RF_MODE;
1197 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1198
1199 /*
1200 * Set Control channel to upper or lower. These settings
1201 * are required only for 40MHz
1202 */
1203 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1204 val32 &= ~CCK0_SIDEBAND;
1205 if (!sec_ch_above)
1206 val32 |= CCK0_SIDEBAND;
1207 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1208
1209 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1210 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1211 if (sec_ch_above)
1212 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1213 else
1214 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1215 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1216
1217 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1218 val32 &= ~FPGA0_ANALOG2_20MHZ;
1219 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1220
1221 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1222 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1223 if (sec_ch_above)
1224 val32 |= FPGA0_PS_UPPER_CHANNEL;
1225 else
1226 val32 |= FPGA0_PS_LOWER_CHANNEL;
1227 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1228 break;
1229
1230 default:
1231 break;
1232 }
1233
1234 for (i = RF_A; i < priv->rf_paths; i++) {
1235 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1236 val32 &= ~MODE_AG_CHANNEL_MASK;
1237 val32 |= channel;
1238 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1239 }
1240
1241 if (ht)
1242 val8 = 0x0e;
1243 else
1244 val8 = 0x0a;
1245
1246 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1247 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1248
1249 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1250 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1251
1252 for (i = RF_A; i < priv->rf_paths; i++) {
1253 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1254 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1255 val32 &= ~MODE_AG_CHANNEL_20MHZ;
1256 else
1257 val32 |= MODE_AG_CHANNEL_20MHZ;
1258 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1259 }
1260}
1261
599119f6 1262void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw)
c3f9506f
JS		 1263{
1264 struct rtl8xxxu_priv *priv = hw->priv;
1265 u32 val32, rsr;
368633ce 1266 u8 val8, subchannel;
c3f9506f
JS		 1267 u16 rf_mode_bw;
1268 bool ht = true;
1269 int sec_ch_above, channel;
1270 int i;
1271
1272 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);
1273 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK;
1274 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1275 channel = hw->conf.chandef.chan->hw_value;
1276
1277/* Hack */
1278 subchannel = 0;
1279
1280 switch (hw->conf.chandef.width) {
1281 case NL80211_CHAN_WIDTH_20_NOHT:
1282 ht = false;
1283 case NL80211_CHAN_WIDTH_20:
1284 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20;
1285 subchannel = 0;
1286
1287 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1288 val32 &= ~FPGA_RF_MODE;
1289 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1290
1291 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1292 val32 &= ~FPGA_RF_MODE;
1293 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1294
1295 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
1296 val32 &= ~(BIT(30) | BIT(31));
1297 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
1298
1299 break;
1300 case NL80211_CHAN_WIDTH_40:
1301 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40;
1302
1303 if (hw->conf.chandef.center_freq1 >
1304 hw->conf.chandef.chan->center_freq) {
1305 sec_ch_above = 1;
1306 channel += 2;
1307 } else {
1308 sec_ch_above = 0;
1309 channel -= 2;
1310 }
1311
1312 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1313 val32 |= FPGA_RF_MODE;
1314 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1315
1316 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1317 val32 |= FPGA_RF_MODE;
1318 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1319
1320 /*
1321 * Set Control channel to upper or lower. These settings
1322 * are required only for 40MHz
1323 */
1324 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1325 val32 &= ~CCK0_SIDEBAND;
1326 if (!sec_ch_above)
1327 val32 |= CCK0_SIDEBAND;
1328 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1329
1330 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1331 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1332 if (sec_ch_above)
1333 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1334 else
1335 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1336 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1337
1338 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1339 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1340 if (sec_ch_above)
1341 val32 |= FPGA0_PS_UPPER_CHANNEL;
1342 else
1343 val32 |= FPGA0_PS_LOWER_CHANNEL;
1344 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1345 break;
1346 case NL80211_CHAN_WIDTH_80:
1347 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80;
1348 break;
1349 default:
1350 break;
1351 }
1352
1353 for (i = RF_A; i < priv->rf_paths; i++) {
1354 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1355 val32 &= ~MODE_AG_CHANNEL_MASK;
1356 val32 |= channel;
1357 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1358 }
1359
1360 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw);
1361 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);
1362
1363 if (ht)
1364 val8 = 0x0e;
1365 else
1366 val8 = 0x0a;
1367
1368 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1369 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1370
1371 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1372 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1373
1374 for (i = RF_A; i < priv->rf_paths; i++) {
1375 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1376 val32 &= ~MODE_AG_BW_MASK;
1377 switch(hw->conf.chandef.width) {
1378 case NL80211_CHAN_WIDTH_80:
1379 val32 |= MODE_AG_BW_80MHZ_8723B;
1380 break;
1381 case NL80211_CHAN_WIDTH_40:
1382 val32 |= MODE_AG_BW_40MHZ_8723B;
1383 break;
1384 default:
1385 val32 |= MODE_AG_BW_20MHZ_8723B;
1386 break;
1387 }
1388 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1389 }
1390}
1391
20e3b2e9 1392void
42a3bc7a 1393rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
26f1fad2 1394{
2fc0b8e5 1395 struct rtl8xxxu_power_base *power_base = priv->power_base;
26f1fad2
JS		 1396 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1397 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1398 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1399 u8 val8;
1400 int group, i;
1401
a46b099c 1402 group = rtl8xxxu_gen1_channel_to_group(channel);
26f1fad2 1403
2fc0b8e5
JS		 1404 cck[0] = priv->cck_tx_power_index_A[group] - 1;
1405 cck[1] = priv->cck_tx_power_index_B[group] - 1;
26f1fad2 1406
b591e982
JS		 1407 if (priv->hi_pa) {
1408 if (cck[0] > 0x20)
1409 cck[0] = 0x20;
1410 if (cck[1] > 0x20)
1411 cck[1] = 0x20;
1412 }
1413
26f1fad2
JS		 1414 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1415 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
2fc0b8e5
JS		 1416 if (ofdm[0])
1417 ofdm[0] -= 1;
1418 if (ofdm[1])
1419 ofdm[1] -= 1;
26f1fad2
JS		 1420
1421 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1422 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1423
1424 mcsbase[0] = ofdm[0];
1425 mcsbase[1] = ofdm[1];
1426 if (!ht40) {
1427 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1428 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1429 }
1430
1431 if (priv->tx_paths > 1) {
1432 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1433 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;
1434 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1435 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;
1436 }
1437
1438 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1439 dev_info(&priv->udev->dev,
1440 "%s: Setting TX power CCK A: %02x, "
1441 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1442 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1443
1444 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1445 if (cck[i] > RF6052_MAX_TX_PWR)
1446 cck[i] = RF6052_MAX_TX_PWR;
1447 if (ofdm[i] > RF6052_MAX_TX_PWR)
1448 ofdm[i] = RF6052_MAX_TX_PWR;
1449 }
1450
1451 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1452 val32 &= 0xffff00ff;
1453 val32 |= (cck[0] << 8);
1454 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1455
1456 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1457 val32 &= 0xff;
1458 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1459 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1460
1461 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1462 val32 &= 0xffffff00;
1463 val32 |= cck[1];
1464 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1465
1466 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1467 val32 &= 0xff;
1468 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1469 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1470
1471 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1472 ofdmbase[0] << 16 | ofdmbase[0] << 24;
1473 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
1474 ofdmbase[1] << 16 | ofdmbase[1] << 24;
26f1fad2 1475
2fc0b8e5
JS		 1476 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06,
1477 ofdm_a + power_base->reg_0e00);
1478 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06,
1479 ofdm_b + power_base->reg_0830);
1480
1481 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24,
1482 ofdm_a + power_base->reg_0e04);
1483 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24,
1484 ofdm_b + power_base->reg_0834);
26f1fad2
JS		 1485
1486 mcs_a = mcsbase[0] | mcsbase[0] << 8 |
1487 mcsbase[0] << 16 | mcsbase[0] << 24;
1488 mcs_b = mcsbase[1] | mcsbase[1] << 8 |
1489 mcsbase[1] << 16 | mcsbase[1] << 24;
1490
2fc0b8e5
JS		 1491 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00,
1492 mcs_a + power_base->reg_0e10);
1493 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00,
1494 mcs_b + power_base->reg_083c);
26f1fad2 1495
2fc0b8e5
JS		 1496 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04,
1497 mcs_a + power_base->reg_0e14);
1498 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04,
1499 mcs_b + power_base->reg_0848);
26f1fad2 1500
2fc0b8e5
JS		 1501 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08,
1502 mcs_a + power_base->reg_0e18);
1503 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08,
1504 mcs_b + power_base->reg_084c);
26f1fad2 1505
2fc0b8e5
JS		 1506 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12,
1507 mcs_a + power_base->reg_0e1c);
26f1fad2
JS		 1508 for (i = 0; i < 3; i++) {
1509 if (i != 2)
1510 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
1511 else
1512 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
1513 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
1514 }
2fc0b8e5
JS		 1515 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12,
1516 mcs_b + power_base->reg_0868);
26f1fad2
JS		 1517 for (i = 0; i < 3; i++) {
1518 if (i != 2)
1519 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
1520 else
1521 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
1522 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
1523 }
1524}
1525
1526static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
1527 enum nl80211_iftype linktype)
1528{
a26703f3 1529 u8 val8;
26f1fad2 1530
a26703f3 1531 val8 = rtl8xxxu_read8(priv, REG_MSR);
26f1fad2
JS		 1532 val8 &= ~MSR_LINKTYPE_MASK;
1533
1534 switch (linktype) {
1535 case NL80211_IFTYPE_UNSPECIFIED:
1536 val8 |= MSR_LINKTYPE_NONE;
1537 break;
1538 case NL80211_IFTYPE_ADHOC:
1539 val8 |= MSR_LINKTYPE_ADHOC;
1540 break;
1541 case NL80211_IFTYPE_STATION:
1542 val8 |= MSR_LINKTYPE_STATION;
1543 break;
1544 case NL80211_IFTYPE_AP:
1545 val8 |= MSR_LINKTYPE_AP;
1546 break;
1547 default:
1548 goto out;
1549 }
1550
1551 rtl8xxxu_write8(priv, REG_MSR, val8);
1552out:
1553 return;
1554}
1555
1556static void
1557rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
1558{
1559 u16 val16;
1560
1561 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
1562 RETRY_LIMIT_SHORT_MASK) |
1563 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
1564 RETRY_LIMIT_LONG_MASK);
1565
1566 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
1567}
1568
1569static void
1570rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
1571{
1572 u16 val16;
1573
1574 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
1575 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
1576
1577 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
1578}
1579
1580static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
1581{
1582 struct device *dev = &priv->udev->dev;
1583 char *cut;
1584
1585 switch (priv->chip_cut) {
1586 case 0:
1587 cut = "A";
1588 break;
1589 case 1:
1590 cut = "B";
1591 break;
0e5d435a
JS		 1592 case 2:
1593 cut = "C";
1594 break;
1595 case 3:
1596 cut = "D";
1597 break;
1598 case 4:
1599 cut = "E";
1600 break;
26f1fad2
JS		 1601 default:
1602 cut = "unknown";
1603 }
1604
1605 dev_info(dev,
1606 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
0e5d435a
JS		 1607 priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
1608 priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
1609 priv->has_bluetooth, priv->has_gps, priv->hi_pa);
26f1fad2
JS		 1610
1611 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
1612}
1613
1614static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
1615{
1616 struct device *dev = &priv->udev->dev;
1617 u32 val32, bonding;
1618 u16 val16;
1619
1620 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
1621 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
1622 SYS_CFG_CHIP_VERSION_SHIFT;
1623 if (val32 & SYS_CFG_TRP_VAUX_EN) {
1624 dev_info(dev, "Unsupported test chip\n");
1625 return -ENOTSUPP;
1626 }
1627
1628 if (val32 & SYS_CFG_BT_FUNC) {
35a741fe
JS		 1629 if (priv->chip_cut >= 3) {
1630 sprintf(priv->chip_name, "8723BU");
ba17d824 1631 priv->rtl_chip = RTL8723B;
35a741fe
JS		 1632 } else {
1633 sprintf(priv->chip_name, "8723AU");
0e28b975 1634 priv->usb_interrupts = 1;
ba17d824 1635 priv->rtl_chip = RTL8723A;
35a741fe
JS		 1636 }
1637
26f1fad2
JS		 1638 priv->rf_paths = 1;
1639 priv->rx_paths = 1;
1640 priv->tx_paths = 1;
26f1fad2
JS		 1641
1642 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
1643 if (val32 & MULTI_WIFI_FUNC_EN)
1644 priv->has_wifi = 1;
1645 if (val32 & MULTI_BT_FUNC_EN)
1646 priv->has_bluetooth = 1;
1647 if (val32 & MULTI_GPS_FUNC_EN)
1648 priv->has_gps = 1;
38451998 1649 priv->is_multi_func = 1;
26f1fad2
JS		 1650 } else if (val32 & SYS_CFG_TYPE_ID) {
1651 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
1652 bonding &= HPON_FSM_BONDING_MASK;
55c0b6ae
JS		 1653 if (priv->fops->tx_desc_size ==
1654 sizeof(struct rtl8xxxu_txdesc40)) {
0e5d435a
JS		 1655 if (bonding == HPON_FSM_BONDING_1T2R) {
1656 sprintf(priv->chip_name, "8191EU");
1657 priv->rf_paths = 2;
1658 priv->rx_paths = 2;
1659 priv->tx_paths = 1;
ba17d824 1660 priv->rtl_chip = RTL8191E;
0e5d435a
JS		 1661 } else {
1662 sprintf(priv->chip_name, "8192EU");
1663 priv->rf_paths = 2;
1664 priv->rx_paths = 2;
1665 priv->tx_paths = 2;
ba17d824 1666 priv->rtl_chip = RTL8192E;
0e5d435a
JS		 1667 }
1668 } else if (bonding == HPON_FSM_BONDING_1T2R) {
26f1fad2
JS		 1669 sprintf(priv->chip_name, "8191CU");
1670 priv->rf_paths = 2;
1671 priv->rx_paths = 2;
1672 priv->tx_paths = 1;
0e28b975 1673 priv->usb_interrupts = 1;
ba17d824 1674 priv->rtl_chip = RTL8191C;
26f1fad2
JS		 1675 } else {
1676 sprintf(priv->chip_name, "8192CU");
1677 priv->rf_paths = 2;
1678 priv->rx_paths = 2;
1679 priv->tx_paths = 2;
0e28b975 1680 priv->usb_interrupts = 1;
ba17d824 1681 priv->rtl_chip = RTL8192C;
26f1fad2
JS		 1682 }
1683 priv->has_wifi = 1;
1684 } else {
1685 sprintf(priv->chip_name, "8188CU");
1686 priv->rf_paths = 1;
1687 priv->rx_paths = 1;
1688 priv->tx_paths = 1;
ba17d824 1689 priv->rtl_chip = RTL8188C;
0e28b975 1690 priv->usb_interrupts = 1;
26f1fad2
JS		 1691 priv->has_wifi = 1;
1692 }
1693
ba17d824
JS		 1694 switch (priv->rtl_chip) {
1695 case RTL8188E:
1696 case RTL8192E:
1697 case RTL8723B:
0e5d435a
JS		 1698 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
1699 case SYS_CFG_VENDOR_ID_TSMC:
1700 sprintf(priv->chip_vendor, "TSMC");
1701 break;
1702 case SYS_CFG_VENDOR_ID_SMIC:
1703 sprintf(priv->chip_vendor, "SMIC");
1704 priv->vendor_smic = 1;
1705 break;
1706 case SYS_CFG_VENDOR_ID_UMC:
1707 sprintf(priv->chip_vendor, "UMC");
1708 priv->vendor_umc = 1;
1709 break;
1710 default:
1711 sprintf(priv->chip_vendor, "unknown");
1712 }
1713 break;
1714 default:
1715 if (val32 & SYS_CFG_VENDOR_ID) {
1716 sprintf(priv->chip_vendor, "UMC");
1717 priv->vendor_umc = 1;
1718 } else {
1719 sprintf(priv->chip_vendor, "TSMC");
1720 }
1721 }
26f1fad2
JS		 1722
1723 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
1724 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
1725
1726 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
1727 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
1728 priv->ep_tx_high_queue = 1;
1729 priv->ep_tx_count++;
1730 }
1731
1732 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
1733 priv->ep_tx_normal_queue = 1;
1734 priv->ep_tx_count++;
1735 }
1736
1737 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
1738 priv->ep_tx_low_queue = 1;
1739 priv->ep_tx_count++;
1740 }
1741
1742 /*
1743 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
1744 */
1745 if (!priv->ep_tx_count) {
1746 switch (priv->nr_out_eps) {
35a741fe 1747 case 4:
26f1fad2
JS		 1748 case 3:
1749 priv->ep_tx_low_queue = 1;
1750 priv->ep_tx_count++;
1751 case 2:
1752 priv->ep_tx_normal_queue = 1;
1753 priv->ep_tx_count++;
1754 case 1:
1755 priv->ep_tx_high_queue = 1;
1756 priv->ep_tx_count++;
1757 break;
1758 default:
1759 dev_info(dev, "Unsupported USB TX end-points\n");
1760 return -ENOTSUPP;
1761 }
1762 }
1763
1764 return 0;
1765}
1766
26f1fad2
JS		 1767static int
1768rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
1769{
1770 int i;
1771 u8 val8;
1772 u32 val32;
1773
1774 /* Write Address */
1775 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
1776 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
1777 val8 &= 0xfc;
1778 val8 |= (offset >> 8) & 0x03;
1779 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
1780
1781 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
1782 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
1783
1784 /* Poll for data read */
1785 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1786 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
1787 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1788 if (val32 & BIT(31))
1789 break;
1790 }
1791
1792 if (i == RTL8XXXU_MAX_REG_POLL)
1793 return -EIO;
1794
1795 udelay(50);
1796 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1797
1798 *data = val32 & 0xff;
1799 return 0;
1800}
1801
1802static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
1803{
1804 struct device *dev = &priv->udev->dev;
1805 int i, ret = 0;
1806 u8 val8, word_mask, header, extheader;
1807 u16 val16, efuse_addr, offset;
1808 u32 val32;
1809
1810 val16 = rtl8xxxu_read16(priv, REG_9346CR);
1811 if (val16 & EEPROM_ENABLE)
1812 priv->has_eeprom = 1;
1813 if (val16 & EEPROM_BOOT)
1814 priv->boot_eeprom = 1;
1815
38451998
JS		 1816 if (priv->is_multi_func) {
1817 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
1818 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
1819 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
1820 }
26f1fad2
JS		 1821
1822 dev_dbg(dev, "Booting from %s\n",
1823 priv->boot_eeprom ? "EEPROM" : "EFUSE");
1824
1825 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
1826
1827 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
1828 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
1829 if (!(val16 & SYS_ISO_PWC_EV12V)) {
1830 val16 |= SYS_ISO_PWC_EV12V;
1831 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
1832 }
1833 /* Reset: 0x0000[28], default valid */
1834 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1835 if (!(val16 & SYS_FUNC_ELDR)) {
1836 val16 |= SYS_FUNC_ELDR;
1837 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1838 }
1839
1840 /*
1841 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
1842 */
1843 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
1844 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
1845 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
1846 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
1847 }
1848
1849 /* Default value is 0xff */
3307d840 1850 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
26f1fad2
JS		 1851
1852 efuse_addr = 0;
1853 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
f6c47702
JS		 1854 u16 map_addr;
1855
26f1fad2
JS		 1856 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
1857 if (ret || header == 0xff)
1858 goto exit;
1859
1860 if ((header & 0x1f) == 0x0f) { /* extended header */
1861 offset = (header & 0xe0) >> 5;
1862
1863 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
1864 &extheader);
1865 if (ret)
1866 goto exit;
1867 /* All words disabled */
1868 if ((extheader & 0x0f) == 0x0f)
1869 continue;
1870
1871 offset |= ((extheader & 0xf0) >> 1);
1872 word_mask = extheader & 0x0f;
1873 } else {
1874 offset = (header >> 4) & 0x0f;
1875 word_mask = header & 0x0f;
1876 }
1877
f6c47702
JS		 1878 /* Get word enable value from PG header */
1879
1880 /* We have 8 bits to indicate validity */
1881 map_addr = offset * 8;
1882 if (map_addr >= EFUSE_MAP_LEN) {
1883 dev_warn(dev, "%s: Illegal map_addr (%04x), "
1884 "efuse corrupt!\n",
1885 __func__, map_addr);
26f1fad2
JS		 1886 ret = -EINVAL;
1887 goto exit;
1888 }
f6c47702
JS		 1889 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
1890 /* Check word enable condition in the section */
32a39dd4 1891 if (word_mask & BIT(i)) {
f6c47702 1892 map_addr += 2;
32a39dd4
JS		 1893 continue;
1894 }
1895
1896 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
1897 if (ret)
1898 goto exit;
1899 priv->efuse_wifi.raw[map_addr++] = val8;
1900
1901 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
1902 if (ret)
1903 goto exit;
1904 priv->efuse_wifi.raw[map_addr++] = val8;
f6c47702 1905 }
26f1fad2
JS		 1906 }
1907
1908exit:
1909 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
1910
1911 return ret;
1912}
1913
599119f6 1914void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
d48fe60e
JS		 1915{
1916 u8 val8;
1917 u16 sys_func;
1918
1919 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
53b381c4 1920 val8 &= ~BIT(0);
d48fe60e 1921 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
7d4ccb8b 1922
d48fe60e
JS		 1923 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1924 sys_func &= ~SYS_FUNC_CPU_ENABLE;
1925 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
7d4ccb8b 1926
d48fe60e 1927 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
53b381c4 1928 val8 |= BIT(0);
d48fe60e 1929 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
7d4ccb8b
JS		 1930
1931 sys_func |= SYS_FUNC_CPU_ENABLE;
1932 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
1933}
1934
26f1fad2
JS		 1935static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
1936{
1937 struct device *dev = &priv->udev->dev;
1938 int ret = 0, i;
1939 u32 val32;
1940
1941 /* Poll checksum report */
1942 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
1943 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
1944 if (val32 & MCU_FW_DL_CSUM_REPORT)
1945 break;
1946 }
1947
1948 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
1949 dev_warn(dev, "Firmware checksum poll timed out\n");
1950 ret = -EAGAIN;
1951 goto exit;
1952 }
1953
1954 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
1955 val32 |= MCU_FW_DL_READY;
1956 val32 &= ~MCU_WINT_INIT_READY;
1957 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
1958
d48fe60e
JS		 1959 /*
1960 * Reset the 8051 in order for the firmware to start running,
1961 * otherwise it won't come up on the 8192eu
1962 */
7d4ccb8b 1963 priv->fops->reset_8051(priv);
d48fe60e 1964
26f1fad2
JS		 1965 /* Wait for firmware to become ready */
1966 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
1967 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
1968 if (val32 & MCU_WINT_INIT_READY)
1969 break;
1970
1971 udelay(100);
1972 }
1973
1974 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
1975 dev_warn(dev, "Firmware failed to start\n");
1976 ret = -EAGAIN;
1977 goto exit;
1978 }
1979
3a4be6a0
JS		 1980 /*
1981 * Init H2C command
1982 */
ba17d824 1983 if (priv->rtl_chip == RTL8723B)
3a4be6a0 1984 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f);
26f1fad2
JS		 1985exit:
1986 return ret;
1987}
1988
1989static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
1990{
1991 int pages, remainder, i, ret;
d48fe60e 1992 u8 val8;
26f1fad2
JS		 1993 u16 val16;
1994 u32 val32;
1995 u8 *fwptr;
1996
1997 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
1998 val8 |= 4;
1999 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2000
2001 /* 8051 enable */
2002 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
43154f6f
JS		 2003 val16 |= SYS_FUNC_CPU_ENABLE;
2004 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
26f1fad2 2005
216202ae
JS		 2006 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2007 if (val8 & MCU_FW_RAM_SEL) {
2008 pr_info("do the RAM reset\n");
2009 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
7d4ccb8b 2010 priv->fops->reset_8051(priv);
216202ae
JS		 2011 }
2012
26f1fad2
JS		 2013 /* MCU firmware download enable */
2014 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
ef1c0499
JS		 2015 val8 |= MCU_FW_DL_ENABLE;
2016 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
26f1fad2
JS		 2017
2018 /* 8051 reset */
2019 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
ef1c0499
JS		 2020 val32 &= ~BIT(19);
2021 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
26f1fad2
JS		 2022
2023 /* Reset firmware download checksum */
2024 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
ef1c0499
JS		 2025 val8 |= MCU_FW_DL_CSUM_REPORT;
2026 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
26f1fad2
JS		 2027
2028 pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2029 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2030
2031 fwptr = priv->fw_data->data;
2032
2033 for (i = 0; i < pages; i++) {
2034 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
ef1c0499
JS		 2035 val8 |= i;
2036 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
26f1fad2
JS		 2037
2038 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2039 fwptr, RTL_FW_PAGE_SIZE);
2040 if (ret != RTL_FW_PAGE_SIZE) {
2041 ret = -EAGAIN;
2042 goto fw_abort;
2043 }
2044
2045 fwptr += RTL_FW_PAGE_SIZE;
2046 }
2047
2048 if (remainder) {
2049 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
ef1c0499
JS		 2050 val8 |= i;
2051 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
26f1fad2
JS		 2052 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2053 fwptr, remainder);
2054 if (ret != remainder) {
2055 ret = -EAGAIN;
2056 goto fw_abort;
2057 }
2058 }
2059
2060 ret = 0;
2061fw_abort:
2062 /* MCU firmware download disable */
2063 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
ef1c0499
JS		 2064 val16 &= ~MCU_FW_DL_ENABLE;
2065 rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
26f1fad2
JS		 2066
2067 return ret;
2068}
2069
599119f6 2070int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
26f1fad2
JS		 2071{
2072 struct device *dev = &priv->udev->dev;
2073 const struct firmware *fw;
2074 int ret = 0;
2075 u16 signature;
2076
2077 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2078 if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2079 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2080 ret = -EAGAIN;
2081 goto exit;
2082 }
2083 if (!fw) {
2084 dev_warn(dev, "Firmware data not available\n");
2085 ret = -EINVAL;
2086 goto exit;
2087 }
2088
2089 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
98e27cbd
TK		 2090 if (!priv->fw_data) {
2091 ret = -ENOMEM;
2092 goto exit;
2093 }
26f1fad2
JS		 2094 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2095
2096 signature = le16_to_cpu(priv->fw_data->signature);
2097 switch (signature & 0xfff0) {
0e5d435a 2098 case 0x92e0:
26f1fad2
JS		 2099 case 0x92c0:
2100 case 0x88c0:
35a741fe 2101 case 0x5300:
26f1fad2
JS		 2102 case 0x2300:
2103 break;
2104 default:
2105 ret = -EINVAL;
2106 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2107 __func__, signature);
2108 }
2109
2110 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2111 le16_to_cpu(priv->fw_data->major_version),
2112 priv->fw_data->minor_version, signature);
2113
2114exit:
2115 release_firmware(fw);
2116 return ret;
2117}
2118
6c46ca3b 2119void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
26f1fad2
JS		 2120{
2121 u16 val16;
2122 int i = 100;
2123
2124 /* Inform 8051 to perform reset */
2125 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2126
2127 for (i = 100; i > 0; i--) {
2128 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2129
2130 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2131 dev_dbg(&priv->udev->dev,
2132 "%s: Firmware self reset success!\n", __func__);
2133 break;
2134 }
2135 udelay(50);
2136 }
2137
2138 if (!i) {
2139 /* Force firmware reset */
2140 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2141 val16 &= ~SYS_FUNC_CPU_ENABLE;
2142 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2143 }
2144}
2145
2146static int
c606e662 2147rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv)
26f1fad2 2148{
c606e662 2149 struct rtl8xxxu_reg8val *array = priv->fops->mactable;
26f1fad2
JS		 2150 int i, ret;
2151 u16 reg;
2152 u8 val;
2153
2154 for (i = 0; ; i++) {
2155 reg = array[i].reg;
2156 val = array[i].val;
2157
2158 if (reg == 0xffff && val == 0xff)
2159 break;
2160
2161 ret = rtl8xxxu_write8(priv, reg, val);
2162 if (ret != 1) {
2163 dev_warn(&priv->udev->dev,
c606e662
JS		 2164 "Failed to initialize MAC "
2165 "(reg: %04x, val %02x)\n", reg, val);
26f1fad2
JS		 2166 return -EAGAIN;
2167 }
2168 }
2169
8a59485c 2170 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E)
8baf670b 2171 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
26f1fad2
JS		 2172
2173 return 0;
2174}
2175
599119f6
JS		 2176int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2177 struct rtl8xxxu_reg32val *array)
26f1fad2
JS		 2178{
2179 int i, ret;
2180 u16 reg;
2181 u32 val;
2182
2183 for (i = 0; ; i++) {
2184 reg = array[i].reg;
2185 val = array[i].val;
2186
2187 if (reg == 0xffff && val == 0xffffffff)
2188 break;
2189
2190 ret = rtl8xxxu_write32(priv, reg, val);
2191 if (ret != sizeof(val)) {
2192 dev_warn(&priv->udev->dev,
2193 "Failed to initialize PHY\n");
2194 return -EAGAIN;
2195 }
2196 udelay(1);
2197 }
2198
2199 return 0;
2200}
2201
20e3b2e9 2202void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv)
26f1fad2 2203{
b84cac16 2204 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
04313eb4 2205 u16 val16;
26f1fad2
JS		 2206 u32 val32;
2207
cb877250
JS		 2208 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
2209 udelay(2);
2210 val8 |= AFE_PLL_320_ENABLE;
2211 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
2212 udelay(2);
3ca7b32c 2213
cb877250
JS		 2214 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
2215 udelay(2);
26f1fad2 2216
cb877250
JS		 2217 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2218 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
2219 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
26f1fad2 2220
cb877250
JS		 2221 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
2222 val32 &= ~AFE_XTAL_RF_GATE;
2223 if (priv->has_bluetooth)
2224 val32 &= ~AFE_XTAL_BT_GATE;
2225 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
26f1fad2
JS		 2226
2227 /* 6. 0x1f[7:0] = 0x07 */
2228 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
2229 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
2230
cb877250 2231 if (priv->hi_pa)
abd71bdb
JS		 2232 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
2233 else if (priv->tx_paths == 2)
2234 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
2235 else
26f1fad2
JS		 2236 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
2237
78a84219 2238 if (priv->rtl_chip == RTL8188R && priv->hi_pa &&
26f1fad2
JS		 2239 priv->vendor_umc && priv->chip_cut == 1)
2240 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
c82f8d11
JS		 2241
2242 if (priv->hi_pa)
2243 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
2244 else
2245 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
b84cac16
JS		 2246
2247 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
2248 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
2249 ldohci12 = 0x57;
2250 lpldo = 1;
2251 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
2252 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
cb877250
JS		 2253}
2254
cb877250
JS		 2255/*
2256 * Most of this is black magic retrieved from the old rtl8723au driver
2257 */
2258static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2259{
b84cac16 2260 u8 val8;
cb877250
JS		 2261 u32 val32;
2262
2263 priv->fops->init_phy_bb(priv);
26f1fad2
JS		 2264
2265 if (priv->tx_paths == 1 && priv->rx_paths == 2) {
2266 /*
2267 * For 1T2R boards, patch the registers.
2268 *
2269 * It looks like 8191/2 1T2R boards use path B for TX
2270 */
2271 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
2272 val32 &= ~(BIT(0) | BIT(1));
2273 val32 |= BIT(1);
2274 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
2275
2276 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
2277 val32 &= ~0x300033;
2278 val32 |= 0x200022;
2279 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
2280
2281 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
bd8fe40c 2282 val32 &= ~CCK0_AFE_RX_MASK;
9068308a 2283 val32 &= 0x00ffffff;
bd8fe40c
JS		 2284 val32 |= 0x40000000;
2285 val32 |= CCK0_AFE_RX_ANT_B;
26f1fad2
JS		 2286 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
2287
2288 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2289 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
2290 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
2291 OFDM_RF_PATH_TX_B);
2292 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2293
2294 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
2295 val32 &= ~(BIT(4) | BIT(5));
2296 val32 |= BIT(4);
2297 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
2298
2299 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
2300 val32 &= ~(BIT(27) | BIT(26));
2301 val32 |= BIT(27);
2302 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
2303
2304 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
2305 val32 &= ~(BIT(27) | BIT(26));
2306 val32 |= BIT(27);
2307 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
2308
2309 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
2310 val32 &= ~(BIT(27) | BIT(26));
2311 val32 |= BIT(27);
2312 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
2313
2314 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
2315 val32 &= ~(BIT(27) | BIT(26));
2316 val32 |= BIT(27);
2317 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
2318
2319 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
2320 val32 &= ~(BIT(27) | BIT(26));
2321 val32 |= BIT(27);
2322 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
2323 }
2324
4ef22eb9 2325 if (priv->has_xtalk) {
26f1fad2
JS		 2326 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
2327
4ef22eb9 2328 val8 = priv->xtalk;
26f1fad2
JS		 2329 val32 &= 0xff000fff;
2330 val32 |= ((val8 | (val8 << 6)) << 12);
2331
2332 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
2333 }
2334
8a59485c
JS		 2335 if (priv->rtl_chip == RTL8192E)
2336 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x000f81fb);
2337
26f1fad2
JS		 2338 return 0;
2339}
2340
2341static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
2342 struct rtl8xxxu_rfregval *array,
2343 enum rtl8xxxu_rfpath path)
2344{
2345 int i, ret;
2346 u8 reg;
2347 u32 val;
2348
2349 for (i = 0; ; i++) {
2350 reg = array[i].reg;
2351 val = array[i].val;
2352
2353 if (reg == 0xff && val == 0xffffffff)
2354 break;
2355
2356 switch (reg) {
2357 case 0xfe:
2358 msleep(50);
2359 continue;
2360 case 0xfd:
2361 mdelay(5);
2362 continue;
2363 case 0xfc:
2364 mdelay(1);
2365 continue;
2366 case 0xfb:
2367 udelay(50);
2368 continue;
2369 case 0xfa:
2370 udelay(5);
2371 continue;
2372 case 0xf9:
2373 udelay(1);
2374 continue;
2375 }
2376
26f1fad2
JS		 2377 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
2378 if (ret) {
2379 dev_warn(&priv->udev->dev,
2380 "Failed to initialize RF\n");
2381 return -EAGAIN;
2382 }
2383 udelay(1);
2384 }
2385
2386 return 0;
2387}
2388
599119f6
JS		 2389int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
2390 struct rtl8xxxu_rfregval *table,
2391 enum rtl8xxxu_rfpath path)
26f1fad2
JS		 2392{
2393 u32 val32;
2394 u16 val16, rfsi_rfenv;
2395 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
2396
2397 switch (path) {
2398 case RF_A:
2399 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
2400 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
2401 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
2402 break;
2403 case RF_B:
2404 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
2405 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
2406 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
2407 break;
2408 default:
2409 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
2410 __func__, path + 'A');
2411 return -EINVAL;
2412 }
2413 /* For path B, use XB */
2414 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
2415 rfsi_rfenv &= FPGA0_RF_RFENV;
2416
2417 /*
2418 * These two we might be able to optimize into one
2419 */
2420 val32 = rtl8xxxu_read32(priv, reg_int_oe);
2421 val32 |= BIT(20); /* 0x10 << 16 */
2422 rtl8xxxu_write32(priv, reg_int_oe, val32);
2423 udelay(1);
2424
2425 val32 = rtl8xxxu_read32(priv, reg_int_oe);
2426 val32 |= BIT(4);
2427 rtl8xxxu_write32(priv, reg_int_oe, val32);
2428 udelay(1);
2429
2430 /*
2431 * These two we might be able to optimize into one
2432 */
2433 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2434 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
2435 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2436 udelay(1);
2437
2438 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2439 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
2440 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2441 udelay(1);
2442
2443 rtl8xxxu_init_rf_regs(priv, table, path);
2444
2445 /* For path B, use XB */
2446 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
2447 val16 &= ~FPGA0_RF_RFENV;
2448 val16 |= rfsi_rfenv;
2449 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
2450
2451 return 0;
2452}
2453
2454static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
2455{
2456 int ret = -EBUSY;
2457 int count = 0;
2458 u32 value;
2459
2460 value = LLT_OP_WRITE | address << 8 | data;
2461
2462 rtl8xxxu_write32(priv, REG_LLT_INIT, value);
2463
2464 do {
2465 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
2466 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
2467 ret = 0;
2468 break;
2469 }
2470 } while (count++ < 20);
2471
2472 return ret;
2473}
2474
20e3b2e9 2475int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
26f1fad2
JS		 2476{
2477 int ret;
2478 int i;
2479
2480 for (i = 0; i < last_tx_page; i++) {
2481 ret = rtl8xxxu_llt_write(priv, i, i + 1);
2482 if (ret)
2483 goto exit;
2484 }
2485
2486 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
2487 if (ret)
2488 goto exit;
2489
2490 /* Mark remaining pages as a ring buffer */
2491 for (i = last_tx_page + 1; i < 0xff; i++) {
2492 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
2493 if (ret)
2494 goto exit;
2495 }
2496
2497 /* Let last entry point to the start entry of ring buffer */
2498 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
2499 if (ret)
2500 goto exit;
2501
2502exit:
2503 return ret;
2504}
2505
599119f6 2506int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
74b99bed
JS		 2507{
2508 u32 val32;
2509 int ret = 0;
2510 int i;
2511
2512 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
74b99bed
JS		 2513 val32 |= AUTO_LLT_INIT_LLT;
2514 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
2515
2516 for (i = 500; i; i--) {
2517 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
2518 if (!(val32 & AUTO_LLT_INIT_LLT))
2519 break;
2520 usleep_range(2, 4);
2521 }
2522
4de24819 2523 if (!i) {
74b99bed
JS		 2524 ret = -EBUSY;
2525 dev_warn(&priv->udev->dev, "LLT table init failed\n");
2526 }
74b99bed
JS		 2527
2528 return ret;
2529}
2530
26f1fad2
JS		 2531static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
2532{
2533 u16 val16, hi, lo;
2534 u16 hiq, mgq, bkq, beq, viq, voq;
2535 int hip, mgp, bkp, bep, vip, vop;
2536 int ret = 0;
2537
2538 switch (priv->ep_tx_count) {
2539 case 1:
2540 if (priv->ep_tx_high_queue) {
2541 hi = TRXDMA_QUEUE_HIGH;
2542 } else if (priv->ep_tx_low_queue) {
2543 hi = TRXDMA_QUEUE_LOW;
2544 } else if (priv->ep_tx_normal_queue) {
2545 hi = TRXDMA_QUEUE_NORMAL;
2546 } else {
2547 hi = 0;
2548 ret = -EINVAL;
2549 }
2550
2551 hiq = hi;
2552 mgq = hi;
2553 bkq = hi;
2554 beq = hi;
2555 viq = hi;
2556 voq = hi;
2557
2558 hip = 0;
2559 mgp = 0;
2560 bkp = 0;
2561 bep = 0;
2562 vip = 0;
2563 vop = 0;
2564 break;
2565 case 2:
2566 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
2567 hi = TRXDMA_QUEUE_HIGH;
2568 lo = TRXDMA_QUEUE_LOW;
2569 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
2570 hi = TRXDMA_QUEUE_NORMAL;
2571 lo = TRXDMA_QUEUE_LOW;
2572 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
2573 hi = TRXDMA_QUEUE_HIGH;
2574 lo = TRXDMA_QUEUE_NORMAL;
2575 } else {
2576 ret = -EINVAL;
2577 hi = 0;
2578 lo = 0;
2579 }
2580
2581 hiq = hi;
2582 mgq = hi;
2583 bkq = lo;
2584 beq = lo;
2585 viq = hi;
2586 voq = hi;
2587
2588 hip = 0;
2589 mgp = 0;
2590 bkp = 1;
2591 bep = 1;
2592 vip = 0;
2593 vop = 0;
2594 break;
2595 case 3:
2596 beq = TRXDMA_QUEUE_LOW;
2597 bkq = TRXDMA_QUEUE_LOW;
2598 viq = TRXDMA_QUEUE_NORMAL;
2599 voq = TRXDMA_QUEUE_HIGH;
2600 mgq = TRXDMA_QUEUE_HIGH;
2601 hiq = TRXDMA_QUEUE_HIGH;
2602
2603 hip = hiq ^ 3;
2604 mgp = mgq ^ 3;
2605 bkp = bkq ^ 3;
2606 bep = beq ^ 3;
2607 vip = viq ^ 3;
2608 vop = viq ^ 3;
2609 break;
2610 default:
2611 ret = -EINVAL;
2612 }
2613
2614 /*
2615 * None of the vendor drivers are configuring the beacon
2616 * queue here .... why?
2617 */
2618 if (!ret) {
2619 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
2620 val16 &= 0x7;
2621 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
2622 (viq << TRXDMA_CTRL_VIQ_SHIFT) |
2623 (beq << TRXDMA_CTRL_BEQ_SHIFT) |
2624 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
2625 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
2626 (hiq << TRXDMA_CTRL_HIQ_SHIFT);
2627 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
2628
2629 priv->pipe_out[TXDESC_QUEUE_VO] =
2630 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
2631 priv->pipe_out[TXDESC_QUEUE_VI] =
2632 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
2633 priv->pipe_out[TXDESC_QUEUE_BE] =
2634 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
2635 priv->pipe_out[TXDESC_QUEUE_BK] =
2636 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
2637 priv->pipe_out[TXDESC_QUEUE_BEACON] =
2638 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2639 priv->pipe_out[TXDESC_QUEUE_MGNT] =
2640 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
2641 priv->pipe_out[TXDESC_QUEUE_HIGH] =
2642 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
2643 priv->pipe_out[TXDESC_QUEUE_CMD] =
2644 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2645 }
2646
2647 return ret;
2648}
2649
599119f6
JS		 2650void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok,
2651 int result[][8], int candidate, bool tx_only)
26f1fad2
JS		 2652{
2653 u32 oldval, x, tx0_a, reg;
2654 int y, tx0_c;
2655 u32 val32;
2656
2657 if (!iqk_ok)
2658 return;
2659
2660 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2661 oldval = val32 >> 22;
2662
2663 x = result[candidate][0];
2664 if ((x & 0x00000200) != 0)
2665 x = x | 0xfffffc00;
2666 tx0_a = (x * oldval) >> 8;
2667
2668 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2669 val32 &= ~0x3ff;
2670 val32 |= tx0_a;
2671 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2672
2673 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2674 val32 &= ~BIT(31);
2675 if ((x * oldval >> 7) & 0x1)
2676 val32 |= BIT(31);
2677 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2678
2679 y = result[candidate][1];
2680 if ((y & 0x00000200) != 0)
2681 y = y | 0xfffffc00;
2682 tx0_c = (y * oldval) >> 8;
2683
2684 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
2685 val32 &= ~0xf0000000;
2686 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
2687 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
2688
2689 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2690 val32 &= ~0x003f0000;
2691 val32 |= ((tx0_c & 0x3f) << 16);
2692 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2693
2694 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2695 val32 &= ~BIT(29);
2696 if ((y * oldval >> 7) & 0x1)
2697 val32 |= BIT(29);
2698 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2699
2700 if (tx_only) {
2701 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2702 return;
2703 }
2704
2705 reg = result[candidate][2];
2706
2707 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2708 val32 &= ~0x3ff;
2709 val32 |= (reg & 0x3ff);
2710 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2711
2712 reg = result[candidate][3] & 0x3F;
2713
2714 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2715 val32 &= ~0xfc00;
2716 val32 |= ((reg << 10) & 0xfc00);
2717 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2718
2719 reg = (result[candidate][3] >> 6) & 0xF;
2720
2721 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
2722 val32 &= ~0xf0000000;
2723 val32 |= (reg << 28);
2724 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
2725}
2726
599119f6
JS		 2727void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok,
2728 int result[][8], int candidate, bool tx_only)
26f1fad2
JS		 2729{
2730 u32 oldval, x, tx1_a, reg;
2731 int y, tx1_c;
2732 u32 val32;
2733
2734 if (!iqk_ok)
2735 return;
2736
2737 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2738 oldval = val32 >> 22;
2739
2740 x = result[candidate][4];
2741 if ((x & 0x00000200) != 0)
2742 x = x | 0xfffffc00;
2743 tx1_a = (x * oldval) >> 8;
2744
2745 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2746 val32 &= ~0x3ff;
2747 val32 |= tx1_a;
2748 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2749
2750 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2751 val32 &= ~BIT(27);
2752 if ((x * oldval >> 7) & 0x1)
2753 val32 |= BIT(27);
2754 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2755
2756 y = result[candidate][5];
2757 if ((y & 0x00000200) != 0)
2758 y = y | 0xfffffc00;
2759 tx1_c = (y * oldval) >> 8;
2760
2761 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
2762 val32 &= ~0xf0000000;
2763 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
2764 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
2765
2766 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2767 val32 &= ~0x003f0000;
2768 val32 |= ((tx1_c & 0x3f) << 16);
2769 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2770
2771 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2772 val32 &= ~BIT(25);
2773 if ((y * oldval >> 7) & 0x1)
2774 val32 |= BIT(25);
2775 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2776
2777 if (tx_only) {
2778 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2779 return;
2780 }
2781
2782 reg = result[candidate][6];
2783
2784 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2785 val32 &= ~0x3ff;
2786 val32 |= (reg & 0x3ff);
2787 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2788
2789 reg = result[candidate][7] & 0x3f;
2790
2791 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2792 val32 &= ~0xfc00;
2793 val32 |= ((reg << 10) & 0xfc00);
2794 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2795
2796 reg = (result[candidate][7] >> 6) & 0xf;
2797
2798 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
2799 val32 &= ~0x0000f000;
2800 val32 |= (reg << 12);
2801 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
2802}
2803
2804#define MAX_TOLERANCE 5
2805
2806static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
2807 int result[][8], int c1, int c2)
2808{
2809 u32 i, j, diff, simubitmap, bound = 0;
2810 int candidate[2] = {-1, -1}; /* for path A and path B */
2811 bool retval = true;
2812
2813 if (priv->tx_paths > 1)
2814 bound = 8;
2815 else
2816 bound = 4;
2817
2818 simubitmap = 0;
2819
2820 for (i = 0; i < bound; i++) {
2821 diff = (result[c1][i] > result[c2][i]) ?
2822 (result[c1][i] - result[c2][i]) :
2823 (result[c2][i] - result[c1][i]);
2824 if (diff > MAX_TOLERANCE) {
2825 if ((i == 2 || i == 6) && !simubitmap) {
2826 if (result[c1][i] + result[c1][i + 1] == 0)
2827 candidate[(i / 4)] = c2;
2828 else if (result[c2][i] + result[c2][i + 1] == 0)
2829 candidate[(i / 4)] = c1;
2830 else
2831 simubitmap = simubitmap | (1 << i);
2832 } else {
2833 simubitmap = simubitmap | (1 << i);
2834 }
2835 }
2836 }
2837
2838 if (simubitmap == 0) {
2839 for (i = 0; i < (bound / 4); i++) {
2840 if (candidate[i] >= 0) {
2841 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2842 result[3][j] = result[candidate[i]][j];
2843 retval = false;
2844 }
2845 }
2846 return retval;
2847 } else if (!(simubitmap & 0x0f)) {
2848 /* path A OK */
2849 for (i = 0; i < 4; i++)
2850 result[3][i] = result[c1][i];
2851 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
2852 /* path B OK */
2853 for (i = 4; i < 8; i++)
2854 result[3][i] = result[c1][i];
2855 }
2856
2857 return false;
2858}
2859
599119f6
JS		 2860bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv,
2861 int result[][8], int c1, int c2)
e1547c53
JS		 2862{
2863 u32 i, j, diff, simubitmap, bound = 0;
2864 int candidate[2] = {-1, -1}; /* for path A and path B */
2865 int tmp1, tmp2;
2866 bool retval = true;
2867
2868 if (priv->tx_paths > 1)
2869 bound = 8;
2870 else
2871 bound = 4;
2872
2873 simubitmap = 0;
2874
2875 for (i = 0; i < bound; i++) {
2876 if (i & 1) {
2877 if ((result[c1][i] & 0x00000200))
2878 tmp1 = result[c1][i] | 0xfffffc00;
2879 else
2880 tmp1 = result[c1][i];
2881
2882 if ((result[c2][i]& 0x00000200))
2883 tmp2 = result[c2][i] | 0xfffffc00;
2884 else
2885 tmp2 = result[c2][i];
2886 } else {
2887 tmp1 = result[c1][i];
2888 tmp2 = result[c2][i];
2889 }
2890
2891 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
2892
2893 if (diff > MAX_TOLERANCE) {
2894 if ((i == 2 || i == 6) && !simubitmap) {
2895 if (result[c1][i] + result[c1][i + 1] == 0)
2896 candidate[(i / 4)] = c2;
2897 else if (result[c2][i] + result[c2][i + 1] == 0)
2898 candidate[(i / 4)] = c1;
2899 else
2900 simubitmap = simubitmap | (1 << i);
2901 } else {
2902 simubitmap = simubitmap | (1 << i);
2903 }
2904 }
2905 }
2906
2907 if (simubitmap == 0) {
2908 for (i = 0; i < (bound / 4); i++) {
2909 if (candidate[i] >= 0) {
2910 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2911 result[3][j] = result[candidate[i]][j];
2912 retval = false;
2913 }
2914 }
2915 return retval;
2916 } else {
2917 if (!(simubitmap & 0x03)) {
2918 /* path A TX OK */
2919 for (i = 0; i < 2; i++)
2920 result[3][i] = result[c1][i];
2921 }
2922
2923 if (!(simubitmap & 0x0c)) {
2924 /* path A RX OK */
2925 for (i = 2; i < 4; i++)
2926 result[3][i] = result[c1][i];
2927 }
2928
2929 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
2930 /* path B RX OK */
2931 for (i = 4; i < 6; i++)
2932 result[3][i] = result[c1][i];
2933 }
2934
2935 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
2936 /* path B RX OK */
2937 for (i = 6; i < 8; i++)
2938 result[3][i] = result[c1][i];
2939 }
2940 }
2941
2942 return false;
2943}
2944
599119f6 2945void
26f1fad2
JS		 2946rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
2947{
2948 int i;
2949
2950 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
2951 backup[i] = rtl8xxxu_read8(priv, reg[i]);
2952
2953 backup[i] = rtl8xxxu_read32(priv, reg[i]);
2954}
2955
599119f6
JS		 2956void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
2957 const u32 *reg, u32 *backup)
26f1fad2
JS		 2958{
2959 int i;
2960
2961 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
2962 rtl8xxxu_write8(priv, reg[i], backup[i]);
2963
2964 rtl8xxxu_write32(priv, reg[i], backup[i]);
2965}
2966
599119f6
JS		 2967void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
2968 u32 *backup, int count)
26f1fad2
JS		 2969{
2970 int i;
2971
2972 for (i = 0; i < count; i++)
2973 backup[i] = rtl8xxxu_read32(priv, regs[i]);
2974}
2975
599119f6
JS		 2976void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
2977 u32 *backup, int count)
26f1fad2
JS		 2978{
2979 int i;
2980
2981 for (i = 0; i < count; i++)
2982 rtl8xxxu_write32(priv, regs[i], backup[i]);
2983}
2984
2985
599119f6
JS		 2986void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
2987 bool path_a_on)
26f1fad2
JS		 2988{
2989 u32 path_on;
2990 int i;
2991
26f1fad2 2992 if (priv->tx_paths == 1) {
8634af5e
JS		 2993 path_on = priv->fops->adda_1t_path_on;
2994 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init);
26f1fad2 2995 } else {
8634af5e
JS		 2996 path_on = path_a_on ? priv->fops->adda_2t_path_on_a :
2997 priv->fops->adda_2t_path_on_b;
2998
26f1fad2
JS		 2999 rtl8xxxu_write32(priv, regs[0], path_on);
3000 }
3001
3002 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3003 rtl8xxxu_write32(priv, regs[i], path_on);
3004}
3005
599119f6
JS		 3006void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3007 const u32 *regs, u32 *backup)
26f1fad2
JS		 3008{
3009 int i = 0;
3010
3011 rtl8xxxu_write8(priv, regs[i], 0x3f);
3012
3013 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3014 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3015
3016 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3017}
3018
3019static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3020{
3021 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3022 int result = 0;
3023
3024 /* path-A IQK setting */
3025 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3026 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3027 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3028
3029 val32 = (priv->rf_paths > 1) ? 0x28160202 :
3030 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3031 0x28160502;
3032 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3033
3034 /* path-B IQK setting */
3035 if (priv->rf_paths > 1) {
3036 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3037 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3038 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3039 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3040 }
3041
3042 /* LO calibration setting */
3043 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3044
3045 /* One shot, path A LOK & IQK */
3046 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3047 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3048
3049 mdelay(1);
3050
3051 /* Check failed */
3052 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3053 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3054 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3055 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3056
3057 if (!(reg_eac & BIT(28)) &&
3058 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3059 ((reg_e9c & 0x03ff0000) != 0x00420000))
3060 result |= 0x01;
3061 else /* If TX not OK, ignore RX */
3062 goto out;
3063
3064 /* If TX is OK, check whether RX is OK */
3065 if (!(reg_eac & BIT(27)) &&
3066 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3067 ((reg_eac & 0x03ff0000) != 0x00360000))
3068 result |= 0x02;
3069 else
3070 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3071 __func__);
3072out:
3073 return result;
3074}
3075
3076static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3077{
3078 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3079 int result = 0;
3080
3081 /* One shot, path B LOK & IQK */
3082 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3083 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3084
3085 mdelay(1);
3086
3087 /* Check failed */
3088 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3089 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3090 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3091 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3092 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3093
3094 if (!(reg_eac & BIT(31)) &&
3095 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3096 ((reg_ebc & 0x03ff0000) != 0x00420000))
3097 result |= 0x01;
3098 else
3099 goto out;
3100
3101 if (!(reg_eac & BIT(30)) &&
3102 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3103 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3104 result |= 0x02;
3105 else
3106 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3107 __func__);
3108out:
3109 return result;
3110}
3111
6c46ca3b
JS		 3112static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
3113 int result[][8], int t)
e1547c53 3114{
6c46ca3b
JS		 3115 struct device *dev = &priv->udev->dev;
3116 u32 i, val32;
3117 int path_a_ok, path_b_ok;
3118 int retry = 2;
3119 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
3120 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
3121 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
3122 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
3123 REG_TX_OFDM_BBON, REG_TX_TO_RX,
3124 REG_TX_TO_TX, REG_RX_CCK,
3125 REG_RX_OFDM, REG_RX_WAIT_RIFS,
3126 REG_RX_TO_RX, REG_STANDBY,
3127 REG_SLEEP, REG_PMPD_ANAEN
3128 };
3129 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
3130 REG_TXPAUSE, REG_BEACON_CTRL,
3131 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
3132 };
3133 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
3134 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
3135 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
3136 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
3137 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
3138 };
e1547c53
JS		 3139
3140 /*
6c46ca3b
JS		 3141 * Note: IQ calibration must be performed after loading
3142 * PHY_REG.txt , and radio_a, radio_b.txt
26f1fad2
JS		 3143 */
3144
3145 if (t == 0) {
3146 /* Save ADDA parameters, turn Path A ADDA on */
3147 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
3148 RTL8XXXU_ADDA_REGS);
3149 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3150 rtl8xxxu_save_regs(priv, iqk_bb_regs,
3151 priv->bb_backup, RTL8XXXU_BB_REGS);
3152 }
3153
3154 rtl8xxxu_path_adda_on(priv, adda_regs, true);
3155
3156 if (t == 0) {
3157 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
3158 if (val32 & FPGA0_HSSI_PARM1_PI)
3159 priv->pi_enabled = 1;
3160 }
3161
3162 if (!priv->pi_enabled) {
3163 /* Switch BB to PI mode to do IQ Calibration. */
3164 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
3165 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
3166 }
3167
3168 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3169 val32 &= ~FPGA_RF_MODE_CCK;
3170 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
3171
3172 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
3173 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
3174 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
3175
cabb550e
JS		 3176 if (!priv->no_pape) {
3177 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
3178 val32 |= (FPGA0_RF_PAPE |
3179 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3180 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3181 }
26f1fad2
JS		 3182
3183 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
3184 val32 &= ~BIT(10);
3185 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
3186 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
3187 val32 &= ~BIT(10);
3188 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
3189
3190 if (priv->tx_paths > 1) {
3191 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3192 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
3193 }
3194
3195 /* MAC settings */
3196 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
3197
3198 /* Page B init */
3199 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
3200
3201 if (priv->tx_paths > 1)
3202 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
3203
3204 /* IQ calibration setting */
3205 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3206 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3207 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3208
3209 for (i = 0; i < retry; i++) {
3210 path_a_ok = rtl8xxxu_iqk_path_a(priv);
3211 if (path_a_ok == 0x03) {
3212 val32 = rtl8xxxu_read32(priv,
3213 REG_TX_POWER_BEFORE_IQK_A);
3214 result[t][0] = (val32 >> 16) & 0x3ff;
3215 val32 = rtl8xxxu_read32(priv,
3216 REG_TX_POWER_AFTER_IQK_A);
3217 result[t][1] = (val32 >> 16) & 0x3ff;
3218 val32 = rtl8xxxu_read32(priv,
3219 REG_RX_POWER_BEFORE_IQK_A_2);
3220 result[t][2] = (val32 >> 16) & 0x3ff;
3221 val32 = rtl8xxxu_read32(priv,
3222 REG_RX_POWER_AFTER_IQK_A_2);
3223 result[t][3] = (val32 >> 16) & 0x3ff;
3224 break;
3225 } else if (i == (retry - 1) && path_a_ok == 0x01) {
3226 /* TX IQK OK */
3227 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
3228 __func__);
3229
3230 val32 = rtl8xxxu_read32(priv,
3231 REG_TX_POWER_BEFORE_IQK_A);
3232 result[t][0] = (val32 >> 16) & 0x3ff;
3233 val32 = rtl8xxxu_read32(priv,
3234 REG_TX_POWER_AFTER_IQK_A);
3235 result[t][1] = (val32 >> 16) & 0x3ff;
3236 }
3237 }
3238
3239 if (!path_a_ok)
3240 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
3241
3242 if (priv->tx_paths > 1) {
3243 /*
3244 * Path A into standby
3245 */
3246 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
3247 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3248 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3249
3250 /* Turn Path B ADDA on */
3251 rtl8xxxu_path_adda_on(priv, adda_regs, false);
3252
3253 for (i = 0; i < retry; i++) {
3254 path_b_ok = rtl8xxxu_iqk_path_b(priv);
3255 if (path_b_ok == 0x03) {
3256 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3257 result[t][4] = (val32 >> 16) & 0x3ff;
3258 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3259 result[t][5] = (val32 >> 16) & 0x3ff;
3260 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3261 result[t][6] = (val32 >> 16) & 0x3ff;
3262 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3263 result[t][7] = (val32 >> 16) & 0x3ff;
3264 break;
3265 } else if (i == (retry - 1) && path_b_ok == 0x01) {
3266 /* TX IQK OK */
3267 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3268 result[t][4] = (val32 >> 16) & 0x3ff;
3269 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3270 result[t][5] = (val32 >> 16) & 0x3ff;
3271 }
3272 }
3273
3274 if (!path_b_ok)
3275 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
3276 }
3277
3278 /* Back to BB mode, load original value */
3279 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
3280
3281 if (t) {
3282 if (!priv->pi_enabled) {
3283 /*
3284 * Switch back BB to SI mode after finishing
3285 * IQ Calibration
3286 */
3287 val32 = 0x01000000;
3288 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
3289 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
3290 }
3291
3292 /* Reload ADDA power saving parameters */
3293 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
3294 RTL8XXXU_ADDA_REGS);
3295
3296 /* Reload MAC parameters */
3297 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3298
3299 /* Reload BB parameters */
3300 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
3301 priv->bb_backup, RTL8XXXU_BB_REGS);
3302
3303 /* Restore RX initial gain */
3304 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
3305
3306 if (priv->tx_paths > 1) {
3307 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
3308 0x00032ed3);
3309 }
3310
3311 /* Load 0xe30 IQC default value */
3312 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
3313 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
3314 }
3315}
3316
27c7e89e 3317void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start)
c7a5a190
JS		 3318{
3319 struct h2c_cmd h2c;
3320
c7a5a190
JS		 3321 memset(&h2c, 0, sizeof(struct h2c_cmd));
3322 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION;
3323 h2c.bt_wlan_calibration.data = start;
3324
9c0343d4 3325 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration));
26f1fad2
JS		 3326}
3327
20e3b2e9 3328void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
e1547c53
JS		 3329{
3330 struct device *dev = &priv->udev->dev;
3331 int result[4][8]; /* last is final result */
3332 int i, candidate;
3333 bool path_a_ok, path_b_ok;
3334 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
3335 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
e1547c53
JS		 3336 s32 reg_tmp = 0;
3337 bool simu;
3338
e1547c53
JS		 3339 memset(result, 0, sizeof(result));
3340 candidate = -1;
3341
3342 path_a_ok = false;
3343 path_b_ok = false;
3344
599119f6 3345 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
e1547c53
JS		 3346
3347 for (i = 0; i < 3; i++) {
599119f6 3348 rtl8xxxu_phy_iqcalibrate(priv, result, i);
e1547c53
JS		 3349
3350 if (i == 1) {
599119f6 3351 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
e1547c53
JS		 3352 if (simu) {
3353 candidate = 0;
3354 break;
3355 }
3356 }
3357
3358 if (i == 2) {
599119f6 3359 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
e1547c53
JS		 3360 if (simu) {
3361 candidate = 0;
3362 break;
3363 }
3364
599119f6 3365 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
e1547c53
JS		 3366 if (simu) {
3367 candidate = 1;
3368 } else {
3369 for (i = 0; i < 8; i++)
3370 reg_tmp += result[3][i];
3371
3372 if (reg_tmp)
3373 candidate = 3;
3374 else
3375 candidate = -1;
3376 }
3377 }
3378 }
3379
3380 for (i = 0; i < 4; i++) {
3381 reg_e94 = result[i][0];
3382 reg_e9c = result[i][1];
3383 reg_ea4 = result[i][2];
3384 reg_eac = result[i][3];
3385 reg_eb4 = result[i][4];
3386 reg_ebc = result[i][5];
3387 reg_ec4 = result[i][6];
3388 reg_ecc = result[i][7];
3389 }
3390
3391 if (candidate >= 0) {
3392 reg_e94 = result[candidate][0];
3393 priv->rege94 = reg_e94;
3394 reg_e9c = result[candidate][1];
3395 priv->rege9c = reg_e9c;
3396 reg_ea4 = result[candidate][2];
3397 reg_eac = result[candidate][3];
3398 reg_eb4 = result[candidate][4];
3399 priv->regeb4 = reg_eb4;
3400 reg_ebc = result[candidate][5];
3401 priv->regebc = reg_ebc;
3402 reg_ec4 = result[candidate][6];
3403 reg_ecc = result[candidate][7];
3404 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
3405 dev_dbg(dev,
3406 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
3407 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
3408 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
3409 path_a_ok = true;
3410 path_b_ok = true;
3411 } else {
3412 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
3413 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
3414 }
3415
3416 if (reg_e94 && candidate >= 0)
3417 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
3418 candidate, (reg_ea4 == 0));
3419
3420 if (priv->tx_paths > 1 && reg_eb4)
3421 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
3422 candidate, (reg_ec4 == 0));
3423
04a74a9f 3424 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,
e1547c53 3425 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
e1547c53
JS		 3426}
3427
26f1fad2
JS		 3428static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
3429{
3430 u32 val32;
3431 u32 rf_amode, rf_bmode = 0, lstf;
3432
3433 /* Check continuous TX and Packet TX */
3434 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
3435
3436 if (lstf & OFDM_LSTF_MASK) {
3437 /* Disable all continuous TX */
3438 val32 = lstf & ~OFDM_LSTF_MASK;
3439 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
3440
3441 /* Read original RF mode Path A */
3442 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
3443
3444 /* Set RF mode to standby Path A */
3445 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
3446 (rf_amode & 0x8ffff) | 0x10000);
3447
3448 /* Path-B */
3449 if (priv->tx_paths > 1) {
3450 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
3451 RF6052_REG_AC);
3452
3453 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3454 (rf_bmode & 0x8ffff) | 0x10000);
3455 }
3456 } else {
3457 /* Deal with Packet TX case */
3458 /* block all queues */
3459 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3460 }
3461
3462 /* Start LC calibration */
0d698dec
JS		 3463 if (priv->fops->has_s0s1)
3464 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0);
26f1fad2
JS		 3465 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
3466 val32 |= 0x08000;
3467 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
3468
3469 msleep(100);
3470
0d698dec
JS		 3471 if (priv->fops->has_s0s1)
3472 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0);
3473
26f1fad2
JS		 3474 /* Restore original parameters */
3475 if (lstf & OFDM_LSTF_MASK) {
3476 /* Path-A */
3477 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
3478 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
3479
3480 /* Path-B */
3481 if (priv->tx_paths > 1)
3482 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3483 rf_bmode);
3484 } else /* Deal with Packet TX case */
3485 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
3486}
3487
3488static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
3489{
3490 int i;
3491 u16 reg;
3492
3493 reg = REG_MACID;
3494
3495 for (i = 0; i < ETH_ALEN; i++)
3496 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
3497
3498 return 0;
3499}
3500
3501static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
3502{
3503 int i;
3504 u16 reg;
3505
3506 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
3507
3508 reg = REG_BSSID;
3509
3510 for (i = 0; i < ETH_ALEN; i++)
3511 rtl8xxxu_write8(priv, reg + i, bssid[i]);
3512
3513 return 0;
3514}
3515
3516static void
3517rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
3518{
3519 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
3520 u8 max_agg = 0xf;
3521 int i;
3522
3523 ampdu_factor = 1 << (ampdu_factor + 2);
3524 if (ampdu_factor > max_agg)
3525 ampdu_factor = max_agg;
3526
3527 for (i = 0; i < 4; i++) {
3528 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
6c46ca3b 3529 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
26f1fad2 3530
6c46ca3b
JS		 3531 if ((vals[i] & 0x0f) > ampdu_factor)
3532 vals[i] = (vals[i] & 0xf0) | ampdu_factor;
26f1fad2 3533
6c46ca3b
JS		 3534 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
3535 }
3536}
26f1fad2 3537
6c46ca3b
JS		 3538static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
3539{
3540 u8 val8;
3541
3542 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
3543 val8 &= 0xf8;
3544 val8 |= density;
3545 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
26f1fad2
JS		 3546}
3547
6c46ca3b 3548static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
fe37d5f6
JS		 3549{
3550 u8 val8;
37ba4b62 3551 int count, ret = 0;
fe37d5f6 3552
6c46ca3b
JS		 3553 /* Start of rtl8723AU_card_enable_flow */
3554 /* Act to Cardemu sequence*/
fe37d5f6
JS		 3555 /* Turn off RF */
3556 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
3557
6c46ca3b
JS		 3558 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
3559 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3560 val8 &= ~LEDCFG2_DPDT_SELECT;
3561 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
fe37d5f6
JS		 3562
3563 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
3564 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3565 val8 |= BIT(1);
3566 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3567
3568 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3569 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3570 if ((val8 & BIT(1)) == 0)
3571 break;
3572 udelay(10);
3573 }
3574
3575 if (!count) {
3576 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
3577 __func__);
3578 ret = -EBUSY;
3579 goto exit;
3580 }
3581
fe37d5f6
JS		 3582 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
3583 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3584 val8 |= SYS_ISO_ANALOG_IPS;
3585 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3586
3587 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
3588 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3589 val8 &= ~LDOA15_ENABLE;
3590 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3591
3592exit:
3593 return ret;
3594}
3595
6c46ca3b 3596int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
26f1fad2
JS		 3597{
3598 u8 val8;
3599 u8 val32;
37ba4b62 3600 int count, ret = 0;
26f1fad2
JS		 3601
3602 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3603
3604 /*
3605 * Poll - wait for RX packet to complete
3606 */
3607 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3608 val32 = rtl8xxxu_read32(priv, 0x5f8);
3609 if (!val32)
3610 break;
3611 udelay(10);
3612 }
3613
3614 if (!count) {
3615 dev_warn(&priv->udev->dev,
3616 "%s: RX poll timed out (0x05f8)\n", __func__);
3617 ret = -EBUSY;
3618 goto exit;
3619 }
3620
3621 /* Disable CCK and OFDM, clock gated */
3622 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3623 val8 &= ~SYS_FUNC_BBRSTB;
3624 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3625
3626 udelay(2);
3627
3628 /* Reset baseband */
3629 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3630 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
3631 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3632
3633 /* Reset MAC TRX */
3634 val8 = rtl8xxxu_read8(priv, REG_CR);
3635 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
3636 rtl8xxxu_write8(priv, REG_CR, val8);
3637
3638 /* Reset MAC TRX */
3639 val8 = rtl8xxxu_read8(priv, REG_CR + 1);
3640 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
3641 rtl8xxxu_write8(priv, REG_CR + 1, val8);
3642
3643 /* Respond TX OK to scheduler */
3644 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
3645 val8 |= DUAL_TSF_TX_OK;
3646 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
3647
3648exit:
3649 return ret;
3650}
3651
993dd9b4 3652void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv)
26f1fad2
JS		 3653{
3654 u8 val8;
3655
3656 /* Clear suspend enable and power down enable*/
3657 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3658 val8 &= ~(BIT(3) | BIT(7));
3659 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3660
3661 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
3662 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3663 val8 &= ~BIT(0);
3664 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3665
3666 /* 0x04[12:11] = 11 enable WL suspend*/
3667 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3668 val8 &= ~(BIT(3) | BIT(4));
3669 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3670}
3671
26f1fad2
JS		 3672static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
3673{
3674 u8 val8;
3675
3676 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
3677 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
3678
3679 /* 0x04[12:11] = 01 enable WL suspend */
3680 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3681 val8 &= ~BIT(4);
3682 val8 |= BIT(3);
3683 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3684
3685 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3686 val8 |= BIT(7);
3687 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3688
3689 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
3690 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3691 val8 |= BIT(0);
3692 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3693
3694 return 0;
3695}
3696
6c46ca3b 3697int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv)
430b454c 3698{
145428ec 3699 struct device *dev = &priv->udev->dev;
430b454c
JS		 3700 u32 val32;
3701 int retry, retval;
3702
3703 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3704
3705 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
3706 val32 |= RXPKT_NUM_RW_RELEASE_EN;
3707 rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32);
3708
3709 retry = 100;
3710 retval = -EBUSY;
3711
3712 do {
3713 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
3714 if (val32 & RXPKT_NUM_RXDMA_IDLE) {
3715 retval = 0;
3716 break;
3717 }
3718 } while (retry--);
3719
3720 rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0);
3721 rtl8xxxu_write32(priv, REG_RQPN, 0x80000000);
3722 mdelay(2);
145428ec
JS		 3723
3724 if (!retry)
3725 dev_warn(dev, "Failed to flush FIFO\n");
430b454c
JS		 3726
3727 return retval;
3728}
3729
20e3b2e9 3730void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv)
747bf237
JS		 3731{
3732 /* Fix USB interface interference issue */
3733 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
3734 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
3735 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3736 /*
3737 * This sets TXDMA_OFFSET_DROP_DATA_EN (bit 9) as well as bits
3738 * 8 and 5, for which I have found no documentation.
3739 */
3740 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
3741
3742 /*
3743 * Solve too many protocol error on USB bus.
3744 * Can't do this for 8188/8192 UMC A cut parts
3745 */
3746 if (!(!priv->chip_cut && priv->vendor_umc)) {
3747 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
3748 rtl8xxxu_write8(priv, 0xfe41, 0x94);
3749 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3750
3751 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
3752 rtl8xxxu_write8(priv, 0xfe41, 0x19);
3753 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3754
3755 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
3756 rtl8xxxu_write8(priv, 0xfe41, 0x91);
3757 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3758
3759 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
3760 rtl8xxxu_write8(priv, 0xfe41, 0x81);
3761 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3762 }
3763}
3764
599119f6 3765void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv)
747bf237
JS		 3766{
3767 u32 val32;
3768
3769 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
3770 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
3771 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
3772}
3773
599119f6 3774void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
26f1fad2
JS		 3775{
3776 u8 val8;
3777 u16 val16;
3778 u32 val32;
3779
3780 /*
3781 * Workaround for 8188RU LNA power leakage problem.
3782 */
8d95c808 3783 if (priv->rtl_chip == RTL8188R) {
26f1fad2
JS		 3784 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
3785 val32 |= BIT(1);
3786 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
3787 }
3788
430b454c
JS		 3789 rtl8xxxu_flush_fifo(priv);
3790
26f1fad2
JS		 3791 rtl8xxxu_active_to_lps(priv);
3792
3793 /* Turn off RF */
3794 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
3795
3796 /* Reset Firmware if running in RAM */
3797 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
3798 rtl8xxxu_firmware_self_reset(priv);
3799
3800 /* Reset MCU */
3801 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3802 val16 &= ~SYS_FUNC_CPU_ENABLE;
3803 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3804
3805 /* Reset MCU ready status */
3806 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
3807
3808 rtl8xxxu_active_to_emu(priv);
3809 rtl8xxxu_emu_to_disabled(priv);
3810
3811 /* Reset MCU IO Wrapper */
3812 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3813 val8 &= ~BIT(0);
3814 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3815
3816 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3817 val8 |= BIT(0);
3818 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3819
3820 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
3821 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
3822}
3823
a3a5dac6 3824#ifdef NEED_PS_TDMA
3ca7b32c
JS		 3825static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
3826 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5)
3827{
3828 struct h2c_cmd h2c;
3829
3830 memset(&h2c, 0, sizeof(struct h2c_cmd));
3831 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA;
3832 h2c.b_type_dma.data1 = arg1;
3833 h2c.b_type_dma.data2 = arg2;
3834 h2c.b_type_dma.data3 = arg3;
3835 h2c.b_type_dma.data4 = arg4;
3836 h2c.b_type_dma.data5 = arg5;
9c0343d4 3837 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma));
3ca7b32c 3838}
a3a5dac6 3839#endif
3ca7b32c 3840
599119f6 3841void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv)
fc89a41f
JS		 3842{
3843 u32 val32;
3844
fc89a41f
JS		 3845 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);
3846 val32 &= ~(BIT(22) | BIT(23));
3847 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);
3848}
3849
89c2a097
JS		 3850static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv *priv)
3851{
3852 struct rtl8xxxu_fileops *fops = priv->fops;
3853 u32 hq, lq, nq, eq, pubq;
3854 u32 val32;
3855
3856 hq = 0;
3857 lq = 0;
3858 nq = 0;
3859 eq = 0;
3860 pubq = 0;
3861
3862 if (priv->ep_tx_high_queue)
3863 hq = fops->page_num_hi;
3864 if (priv->ep_tx_low_queue)
3865 lq = fops->page_num_lo;
3866 if (priv->ep_tx_normal_queue)
3867 nq = fops->page_num_norm;
3868
3869 val32 = (nq << RQPN_NPQ_SHIFT) | (eq << RQPN_EPQ_SHIFT);
3870 rtl8xxxu_write32(priv, REG_RQPN_NPQ, val32);
3871
3872 pubq = fops->total_page_num - hq - lq - nq;
3873
3874 val32 = RQPN_LOAD;
3875 val32 |= (hq << RQPN_HI_PQ_SHIFT);
3876 val32 |= (lq << RQPN_LO_PQ_SHIFT);
3877 val32 |= (pubq << RQPN_PUB_PQ_SHIFT);
3878
3879 rtl8xxxu_write32(priv, REG_RQPN, val32);
3880}
3881
26f1fad2
JS		 3882static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
3883{
3884 struct rtl8xxxu_priv *priv = hw->priv;
3885 struct device *dev = &priv->udev->dev;
26f1fad2
JS		 3886 bool macpower;
3887 int ret;
3888 u8 val8;
3889 u16 val16;
3890 u32 val32;
3891
3892 /* Check if MAC is already powered on */
3893 val8 = rtl8xxxu_read8(priv, REG_CR);
3894
3895 /*
3896 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
3897 * initialized. First MAC returns 0xea, second MAC returns 0x00
3898 */
3899 if (val8 == 0xea)
3900 macpower = false;
3901 else
3902 macpower = true;
3903
3904 ret = priv->fops->power_on(priv);
3905 if (ret < 0) {
3906 dev_warn(dev, "%s: Failed power on\n", __func__);
3907 goto exit;
3908 }
3909
efeb8ce7
JS		 3910 if (!macpower)
3911 rtl8xxxu_init_queue_reserved_page(priv);
07bb46be 3912
59b24dad
JS		 3913 ret = rtl8xxxu_init_queue_priority(priv);
3914 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
3915 if (ret)
3916 goto exit;
3917
3918 /*
3919 * Set RX page boundary
3920 */
24e8e7ec 3921 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, priv->fops->trxff_boundary);
59b24dad 3922
a47b9d47
JS		 3923 ret = rtl8xxxu_download_firmware(priv);
3924 dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
3925 if (ret)
3926 goto exit;
3927 ret = rtl8xxxu_start_firmware(priv);
3928 dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
3929 if (ret)
3930 goto exit;
3931
f0d9f5e9
JS		 3932 if (priv->fops->phy_init_antenna_selection)
3933 priv->fops->phy_init_antenna_selection(priv);
3934
c606e662 3935 ret = rtl8xxxu_init_mac(priv);
b7dd8ff9 3936
26f1fad2
JS		 3937 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
3938 if (ret)
3939 goto exit;
3940
3941 ret = rtl8xxxu_init_phy_bb(priv);
3942 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
3943 if (ret)
3944 goto exit;
3945
4062b8ff 3946 ret = priv->fops->init_phy_rf(priv);
26f1fad2
JS		 3947 if (ret)
3948 goto exit;
3949
c157863d 3950 /* RFSW Control - clear bit 14 ?? */
b816901b 3951 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E)
c157863d 3952 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
31133da7
JS		 3953
3954 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
cabb550e
JS		 3955 FPGA0_RF_ANTSWB |
3956 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB) << FPGA0_RF_BD_CTRL_SHIFT);
3957 if (!priv->no_pape) {
3958 val32 |= (FPGA0_RF_PAPE |
3959 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3960 }
c157863d 3961 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
cabb550e 3962
c157863d
JS		 3963 /* 0x860[6:5]= 00 - why? - this sets antenna B */
3964 if (priv->rtl_chip != RTL8192E)
3965 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210);
3966
f2a4163a 3967 if (!macpower) {
1f1b20f1
JS		 3968 /*
3969 * Set TX buffer boundary
3970 */
e02aa3ee 3971 val8 = priv->fops->total_page_num + 1;
1f1b20f1
JS		 3972
3973 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
3974 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
3975 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
3976 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
3977 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
3978 }
3979
26f1fad2 3980 /*
9b323ee9
JS		 3981 * The vendor drivers set PBP for all devices, except 8192e.
3982 * There is no explanation for this in any of the sources.
26f1fad2 3983 */
9b323ee9
JS		 3984 val8 = (priv->fops->pbp_rx << PBP_PAGE_SIZE_RX_SHIFT) |
3985 (priv->fops->pbp_tx << PBP_PAGE_SIZE_TX_SHIFT);
2e7c7b34
JS		 3986 if (priv->rtl_chip != RTL8192E)
3987 rtl8xxxu_write8(priv, REG_PBP, val8);
26f1fad2 3988
59b24dad
JS		 3989 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
3990 if (!macpower) {
3991 ret = priv->fops->llt_init(priv, TX_TOTAL_PAGE_NUM);
3992 if (ret) {
3993 dev_warn(dev, "%s: LLT table init failed\n", __func__);
3994 goto exit;
3995 }
3996
0486e80b
JS		 3997 /*
3998 * Chip specific quirks
3999 */
747bf237 4000 priv->fops->usb_quirks(priv);
0486e80b 4001
59b24dad 4002 /*
e3ebcd74 4003 * Enable TX report and TX report timer for 8723bu/8188eu/...
59b24dad 4004 */
e3ebcd74 4005 if (priv->fops->has_tx_report) {
59b24dad
JS		 4006 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
4007 val8 |= TX_REPORT_CTRL_TIMER_ENABLE;
4008 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
4009 /* Set MAX RPT MACID */
4010 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02);
4011 /* TX report Timer. Unit: 32us */
4012 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0);
4013
4014 /* tmp ps ? */
4015 val8 = rtl8xxxu_read8(priv, 0xa3);
4016 val8 &= 0xf8;
4017 rtl8xxxu_write8(priv, 0xa3, val8);
4018 }
4019 }
4020
26f1fad2
JS		 4021 /*
4022 * Unit in 8 bytes, not obvious what it is used for
4023 */
4024 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
4025
57e5e2e6
JS		 4026 if (priv->rtl_chip == RTL8192E) {
4027 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
4028 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
4029 } else {
4030 /*
4031 * Enable all interrupts - not obvious USB needs to do this
4032 */
4033 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
4034 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
4035 }
26f1fad2
JS		 4036
4037 rtl8xxxu_set_mac(priv);
4038 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
4039
4040 /*
4041 * Configure initial WMAC settings
4042 */
4043 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
26f1fad2
JS		 4044 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
4045 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
4046 rtl8xxxu_write32(priv, REG_RCR, val32);
4047
4048 /*
4049 * Accept all multicast
4050 */
4051 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
4052 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
4053
4054 /*
4055 * Init adaptive controls
4056 */
4057 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4058 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4059 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
4060 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4061
4062 /* CCK = 0x0a, OFDM = 0x10 */
4063 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
4064 rtl8xxxu_set_retry(priv, 0x30, 0x30);
4065 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
4066
4067 /*
4068 * Init EDCA
4069 */
4070 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
4071
4072 /* Set CCK SIFS */
4073 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
4074
4075 /* Set OFDM SIFS */
4076 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
4077
4078 /* TXOP */
4079 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
4080 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
4081 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
4082 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
4083
4084 /* Set data auto rate fallback retry count */
4085 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
4086 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
4087 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
4088 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
4089
4090 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
4091 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
4092 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
4093
4094 /* Set ACK timeout */
4095 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
4096
4097 /*
4098 * Initialize beacon parameters
4099 */
4100 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
4101 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
4102 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
4103 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
4104 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
4105 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
4106
c3690604
JS		 4107 /*
4108 * Initialize burst parameters
4109 */
ba17d824 4110 if (priv->rtl_chip == RTL8723B) {
c3690604
JS		 4111 /*
4112 * For USB high speed set 512B packets
4113 */
4114 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B);
4115 val8 &= ~(BIT(4) | BIT(5));
4116 val8 |= BIT(4);
4117 val8 |= BIT(1) | BIT(2) | BIT(3);
4118 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8);
4119
4120 /*
4121 * For USB high speed set 512B packets
4122 */
4123 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B);
4124 val8 |= BIT(7);
4125 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);
4126
4127 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14);
4128 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 0x5e);
4129 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff);
4130 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18);
4131 rtl8xxxu_write8(priv, REG_PIFS, 0x00);
4132 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, 0x50);
4133 rtl8xxxu_write8(priv, REG_USTIME_EDCA, 0x50);
4134
4135 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
4136 val8 |= BIT(5) | BIT(6);
4137 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
4138 }
4139
3e88ca44
JS		 4140 if (priv->fops->init_aggregation)
4141 priv->fops->init_aggregation(priv);
4142
26f1fad2
JS		 4143 /*
4144 * Enable CCK and OFDM block
4145 */
4146 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4147 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
4148 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4149
4150 /*
4151 * Invalidate all CAM entries - bit 30 is undocumented
4152 */
4153 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
4154
4155 /*
4156 * Start out with default power levels for channel 6, 20MHz
4157 */
e796dab4 4158 priv->fops->set_tx_power(priv, 1, false);
26f1fad2
JS		 4159
4160 /* Let the 8051 take control of antenna setting */
5bdb6b08
JS		 4161 if (priv->rtl_chip != RTL8192E) {
4162 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4163 val8 |= LEDCFG2_DPDT_SELECT;
4164 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4165 }
26f1fad2
JS		 4166
4167 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
4168
4169 /* Disable BAR - not sure if this has any effect on USB */
4170 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
4171
4172 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
4173
9c79bf95
JS		 4174 if (priv->fops->init_statistics)
4175 priv->fops->init_statistics(priv);
4176
b052b7fc
JS		 4177 if (priv->rtl_chip == RTL8192E) {
4178 /*
4179 * 0x4c6[3] 1: RTS BW = Data BW
4180 * 0: RTS BW depends on CCA / secondary CCA result.
4181 */
4182 val8 = rtl8xxxu_read8(priv, REG_QUEUE_CTRL);
4183 val8 &= ~BIT(3);
4184 rtl8xxxu_write8(priv, REG_QUEUE_CTRL, val8);
4185 /*
4186 * Reset USB mode switch setting
4187 */
4188 rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00);
4189 }
4190
fa0f2d48
JS		 4191 rtl8723a_phy_lc_calibrate(priv);
4192
e1547c53 4193 priv->fops->phy_iq_calibrate(priv);
26f1fad2
JS		 4194
4195 /*
4196 * This should enable thermal meter
4197 */
eed145ab 4198 if (priv->fops->gen2_thermal_meter)
72143b9e
JS		 4199 rtl8xxxu_write_rfreg(priv,
4200 RF_A, RF6052_REG_T_METER_8723B, 0x37cf8);
4201 else
4202 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
26f1fad2 4203
26f1fad2
JS		 4204 /* Set NAV_UPPER to 30000us */
4205 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
4206 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
4207
ba17d824 4208 if (priv->rtl_chip == RTL8723A) {
4042e617
JS		 4209 /*
4210 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
4211 * but we need to find root cause.
4212 * This is 8723au only.
4213 */
4214 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4215 if ((val32 & 0xff000000) != 0x83000000) {
4216 val32 |= FPGA_RF_MODE_CCK;
4217 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4218 }
3021e51f
JS		 4219 } else if (priv->rtl_chip == RTL8192E) {
4220 rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00);
26f1fad2
JS		 4221 }
4222
4223 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
4224 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
4225 /* ack for xmit mgmt frames. */
4226 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
4227
e1394fe5
JS		 4228 if (priv->rtl_chip == RTL8192E) {
4229 /*
4230 * Fix LDPC rx hang issue.
4231 */
4232 val32 = rtl8xxxu_read32(priv, REG_AFE_MISC);
4233 rtl8xxxu_write8(priv, REG_8192E_LDOV12_CTRL, 0x75);
4234 val32 &= 0xfff00fff;
4235 val32 |= 0x0007e000;
46b37831 4236 rtl8xxxu_write32(priv, REG_AFE_MISC, val32);
e1394fe5 4237 }
26f1fad2
JS		 4238exit:
4239 return ret;
4240}
4241
26f1fad2
JS		 4242static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
4243 struct ieee80211_key_conf *key, const u8 *mac)
4244{
4245 u32 cmd, val32, addr, ctrl;
4246 int j, i, tmp_debug;
4247
4248 tmp_debug = rtl8xxxu_debug;
4249 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
4250 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
4251
4252 /*
4253 * This is a bit of a hack - the lower bits of the cipher
4254 * suite selector happens to match the cipher index in the CAM
4255 */
4256 addr = key->keyidx << CAM_CMD_KEY_SHIFT;
4257 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
4258
4259 for (j = 5; j >= 0; j--) {
4260 switch (j) {
4261 case 0:
4262 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
4263 break;
4264 case 1:
4265 val32 = mac[2] | (mac[3] << 8) |
4266 (mac[4] << 16) | (mac[5] << 24);
4267 break;
4268 default:
4269 i = (j - 2) << 2;
4270 val32 = key->key[i] | (key->key[i + 1] << 8) |
4271 key->key[i + 2] << 16 | key->key[i + 3] << 24;
4272 break;
4273 }
4274
4275 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
4276 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
4277 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
4278 udelay(100);
4279 }
4280
4281 rtl8xxxu_debug = tmp_debug;
4282}
4283
4284static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
56e4374a 4285 struct ieee80211_vif *vif, const u8 *mac)
26f1fad2
JS		 4286{
4287 struct rtl8xxxu_priv *priv = hw->priv;
4288 u8 val8;
4289
4290 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4291 val8 |= BEACON_DISABLE_TSF_UPDATE;
4292 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4293}
4294
4295static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
4296 struct ieee80211_vif *vif)
4297{
4298 struct rtl8xxxu_priv *priv = hw->priv;
4299 u8 val8;
4300
4301 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4302 val8 &= ~BEACON_DISABLE_TSF_UPDATE;
4303 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4304}
4305
20e3b2e9 4306void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv, u32 ramask, int sgi)
26f1fad2
JS		 4307{
4308 struct h2c_cmd h2c;
4309
f653e690
JS		 4310 memset(&h2c, 0, sizeof(struct h2c_cmd));
4311
26f1fad2
JS		 4312 h2c.ramask.cmd = H2C_SET_RATE_MASK;
4313 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
4314 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
4315
4316 h2c.ramask.arg = 0x80;
4317 if (sgi)
4318 h2c.ramask.arg |= 0x20;
4319
7ff8c1ae 4320 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
8da91571 4321 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));
9c0343d4 4322 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));
26f1fad2
JS		 4323}
4324
599119f6
JS		 4325void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv,
4326 u32 ramask, int sgi)
f653e690
JS		 4327{
4328 struct h2c_cmd h2c;
4329 u8 bw = 0;
4330
4331 memset(&h2c, 0, sizeof(struct h2c_cmd));
4332
4333 h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID;
4334 h2c.b_macid_cfg.ramask0 = ramask & 0xff;
4335 h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff;
4336 h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff;
4337 h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff;
4338
4339 h2c.ramask.arg = 0x80;
4340 h2c.b_macid_cfg.data1 = 0;
4341 if (sgi)
4342 h2c.b_macid_cfg.data1 |= BIT(7);
4343
4344 h2c.b_macid_cfg.data2 = bw;
4345
4346 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
4347 __func__, ramask, h2c.ramask.arg, sizeof(h2c.b_macid_cfg));
9c0343d4 4348 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg));
f653e690
JS		 4349}
4350
20e3b2e9
JS		 4351void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv,
4352 u8 macid, bool connect)
7d794eaa
JS		 4353{
4354 struct h2c_cmd h2c;
4355
4356 memset(&h2c, 0, sizeof(struct h2c_cmd));
4357
4358 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
4359
4360 if (connect)
4361 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
4362 else
4363 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
4364
9c0343d4 4365 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));
7d794eaa
JS		 4366}
4367
599119f6
JS		 4368void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv,
4369 u8 macid, bool connect)
7d794eaa
JS		 4370{
4371 struct h2c_cmd h2c;
4372
4373 memset(&h2c, 0, sizeof(struct h2c_cmd));
4374
4375 h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT;
4376 if (connect)
4377 h2c.media_status_rpt.parm |= BIT(0);
4378 else
4379 h2c.media_status_rpt.parm &= ~BIT(0);
4380
9c0343d4 4381 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt));
7d794eaa
JS		 4382}
4383
91dcbb71
JS		 4384void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv)
4385{
614e389f 4386 u8 agg_ctrl, usb_spec, page_thresh, timeout;
91dcbb71
JS		 4387
4388 usb_spec = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION);
4389 usb_spec &= ~USB_SPEC_USB_AGG_ENABLE;
82cce22a 4390 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, usb_spec);
91dcbb71
JS		 4391
4392 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
4393 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
4394
82cce22a
JS		 4395 if (!rtl8xxxu_dma_aggregation) {
4396 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
4397 return;
4398 }
91dcbb71 4399
82cce22a 4400 agg_ctrl |= TRXDMA_CTRL_RXDMA_AGG_EN;
91dcbb71 4401 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
91dcbb71
JS		 4402
4403 /*
4404 * The number of packets we can take looks to be buffer size / 512
4405 * which matches the 512 byte rounding we have to do when de-muxing
4406 * the packets.
4407 *
4408 * Sample numbers from the vendor driver:
4409 * USB High-Speed mode values:
4410 * RxAggBlockCount = 8 : 512 byte unit
4411 * RxAggBlockTimeout = 6
4412 * RxAggPageCount = 48 : 128 byte unit
4413 * RxAggPageTimeout = 4 or 6 (absolute time 34ms/(2^6))
4414 */
4415
4416 page_thresh = (priv->fops->rx_agg_buf_size / 512);
fd83f122
JS		 4417 if (rtl8xxxu_dma_agg_pages >= 0) {
4418 if (rtl8xxxu_dma_agg_pages <= page_thresh)
4419 timeout = page_thresh;
4420 else if (rtl8xxxu_dma_agg_pages <= 6)
4421 dev_err(&priv->udev->dev,
4422 "%s: dma_agg_pages=%i too small, minium is 6\n",
4423 __func__, rtl8xxxu_dma_agg_pages);
4424 else
4425 dev_err(&priv->udev->dev,
4426 "%s: dma_agg_pages=%i larger than limit %i\n",
4427 __func__, rtl8xxxu_dma_agg_pages, page_thresh);
4428 }
91dcbb71 4429 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH, page_thresh);
614e389f
JS		 4430 /*
4431 * REG_RXDMA_AGG_PG_TH + 1 seems to be the timeout register on
4432 * gen2 chips and rtl8188eu. The rtl8723au seems unhappy if we
4433 * don't set it, so better set both.
4434 */
4435 timeout = 4;
fd83f122
JS		 4436
4437 if (rtl8xxxu_dma_agg_timeout >= 0) {
4438 if (rtl8xxxu_dma_agg_timeout <= 127)
4439 timeout = rtl8xxxu_dma_agg_timeout;
4440 else
4441 dev_err(&priv->udev->dev,
4442 "%s: Invalid dma_agg_timeout: %i\n",
4443 __func__, rtl8xxxu_dma_agg_timeout);
4444 }
4445
614e389f
JS		 4446 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH + 1, timeout);
4447 rtl8xxxu_write8(priv, REG_USB_DMA_AGG_TO, timeout);
91dcbb71
JS		 4448 priv->rx_buf_aggregation = 1;
4449}
4450
26f1fad2
JS		 4451static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
4452{
4453 u32 val32;
4454 u8 rate_idx = 0;
4455
4456 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
4457
4458 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4459 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4460 val32 |= rate_cfg;
4461 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4462
4463 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
4464
4465 while (rate_cfg) {
4466 rate_cfg = (rate_cfg >> 1);
4467 rate_idx++;
4468 }
4469 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
4470}
4471
4472static void
4473rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4474 struct ieee80211_bss_conf *bss_conf, u32 changed)
4475{
4476 struct rtl8xxxu_priv *priv = hw->priv;
4477 struct device *dev = &priv->udev->dev;
4478 struct ieee80211_sta *sta;
4479 u32 val32;
4480 u8 val8;
4481
4482 if (changed & BSS_CHANGED_ASSOC) {
26f1fad2
JS		 4483 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
4484
26f1fad2
JS		 4485 rtl8xxxu_set_linktype(priv, vif->type);
4486
4487 if (bss_conf->assoc) {
4488 u32 ramask;
4489 int sgi = 0;
4490
4491 rcu_read_lock();
4492 sta = ieee80211_find_sta(vif, bss_conf->bssid);
4493 if (!sta) {
4494 dev_info(dev, "%s: ASSOC no sta found\n",
4495 __func__);
4496 rcu_read_unlock();
4497 goto error;
4498 }
4499
4500 if (sta->ht_cap.ht_supported)
4501 dev_info(dev, "%s: HT supported\n", __func__);
4502 if (sta->vht_cap.vht_supported)
4503 dev_info(dev, "%s: VHT supported\n", __func__);
4504
4505 /* TODO: Set bits 28-31 for rate adaptive id */
4506 ramask = (sta->supp_rates[0] & 0xfff) |
4507 sta->ht_cap.mcs.rx_mask[0] << 12 |
4508 sta->ht_cap.mcs.rx_mask[1] << 20;
4509 if (sta->ht_cap.cap &
4510 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
4511 sgi = 1;
4512 rcu_read_unlock();
4513
f653e690 4514 priv->fops->update_rate_mask(priv, ramask, sgi);
26f1fad2 4515
26f1fad2
JS		 4516 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
4517
97db5a87 4518 rtl8xxxu_stop_tx_beacon(priv);
26f1fad2
JS		 4519
4520 /* joinbss sequence */
4521 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
4522 0xc000 | bss_conf->aid);
4523
7d794eaa 4524 priv->fops->report_connect(priv, 0, true);
26f1fad2 4525 } else {
26f1fad2
JS		 4526 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4527 val8 |= BEACON_DISABLE_TSF_UPDATE;
4528 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4529
7d794eaa 4530 priv->fops->report_connect(priv, 0, false);
26f1fad2 4531 }
26f1fad2
JS		 4532 }
4533
4534 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
4535 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
4536 bss_conf->use_short_preamble);
4537 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4538 if (bss_conf->use_short_preamble)
4539 val32 |= RSR_ACK_SHORT_PREAMBLE;
4540 else
4541 val32 &= ~RSR_ACK_SHORT_PREAMBLE;
4542 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4543 }
4544
4545 if (changed & BSS_CHANGED_ERP_SLOT) {
4546 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
4547 bss_conf->use_short_slot);
4548
4549 if (bss_conf->use_short_slot)
4550 val8 = 9;
4551 else
4552 val8 = 20;
4553 rtl8xxxu_write8(priv, REG_SLOT, val8);
4554 }
4555
4556 if (changed & BSS_CHANGED_BSSID) {
4557 dev_dbg(dev, "Changed BSSID!\n");
4558 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
4559 }
4560
4561 if (changed & BSS_CHANGED_BASIC_RATES) {
4562 dev_dbg(dev, "Changed BASIC_RATES!\n");
4563 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
4564 }
4565error:
4566 return;
4567}
4568
4569static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
4570{
4571 u32 rtlqueue;
4572
4573 switch (queue) {
4574 case IEEE80211_AC_VO:
4575 rtlqueue = TXDESC_QUEUE_VO;
4576 break;
4577 case IEEE80211_AC_VI:
4578 rtlqueue = TXDESC_QUEUE_VI;
4579 break;
4580 case IEEE80211_AC_BE:
4581 rtlqueue = TXDESC_QUEUE_BE;
4582 break;
4583 case IEEE80211_AC_BK:
4584 rtlqueue = TXDESC_QUEUE_BK;
4585 break;
4586 default:
4587 rtlqueue = TXDESC_QUEUE_BE;
4588 }
4589
4590 return rtlqueue;
4591}
4592
4593static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
4594{
4595 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4596 u32 queue;
4597
4598 if (ieee80211_is_mgmt(hdr->frame_control))
4599 queue = TXDESC_QUEUE_MGNT;
4600 else
4601 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
4602
4603 return queue;
4604}
4605
179e1742
JS		 4606/*
4607 * Despite newer chips 8723b/8812/8821 having a larger TX descriptor
4608 * format. The descriptor checksum is still only calculated over the
4609 * initial 32 bytes of the descriptor!
4610 */
dbb2896b 4611static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc)
26f1fad2
JS		 4612{
4613 __le16 *ptr = (__le16 *)tx_desc;
4614 u16 csum = 0;
4615 int i;
4616
4617 /*
4618 * Clear csum field before calculation, as the csum field is
4619 * in the middle of the struct.
4620 */
4621 tx_desc->csum = cpu_to_le16(0);
4622
dbb2896b 4623 for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++)
26f1fad2
JS		 4624 csum = csum ^ le16_to_cpu(ptr[i]);
4625
4626 tx_desc->csum |= cpu_to_le16(csum);
4627}
4628
4629static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
4630{
4631 struct rtl8xxxu_tx_urb *tx_urb, *tmp;
4632 unsigned long flags;
4633
4634 spin_lock_irqsave(&priv->tx_urb_lock, flags);
4635 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
4636 list_del(&tx_urb->list);
4637 priv->tx_urb_free_count--;
4638 usb_free_urb(&tx_urb->urb);
4639 }
4640 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4641}
4642
4643static struct rtl8xxxu_tx_urb *
4644rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
4645{
4646 struct rtl8xxxu_tx_urb *tx_urb;
4647 unsigned long flags;
4648
4649 spin_lock_irqsave(&priv->tx_urb_lock, flags);
4650 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
4651 struct rtl8xxxu_tx_urb, list);
4652 if (tx_urb) {
4653 list_del(&tx_urb->list);
4654 priv->tx_urb_free_count--;
4655 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
4656 !priv->tx_stopped) {
4657 priv->tx_stopped = true;
4658 ieee80211_stop_queues(priv->hw);
4659 }
4660 }
4661
4662 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4663
4664 return tx_urb;
4665}
4666
4667static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
4668 struct rtl8xxxu_tx_urb *tx_urb)
4669{
4670 unsigned long flags;
4671
4672 INIT_LIST_HEAD(&tx_urb->list);
4673
4674 spin_lock_irqsave(&priv->tx_urb_lock, flags);
4675
4676 list_add(&tx_urb->list, &priv->tx_urb_free_list);
4677 priv->tx_urb_free_count++;
4678 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
4679 priv->tx_stopped) {
4680 priv->tx_stopped = false;
4681 ieee80211_wake_queues(priv->hw);
4682 }
4683
4684 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4685}
4686
4687static void rtl8xxxu_tx_complete(struct urb *urb)
4688{
4689 struct sk_buff *skb = (struct sk_buff *)urb->context;
4690 struct ieee80211_tx_info *tx_info;
4691 struct ieee80211_hw *hw;
179e1742 4692 struct rtl8xxxu_priv *priv;
26f1fad2
JS		 4693 struct rtl8xxxu_tx_urb *tx_urb =
4694 container_of(urb, struct rtl8xxxu_tx_urb, urb);
4695
4696 tx_info = IEEE80211_SKB_CB(skb);
4697 hw = tx_info->rate_driver_data[0];
179e1742 4698 priv = hw->priv;
26f1fad2 4699
179e1742 4700 skb_pull(skb, priv->fops->tx_desc_size);
26f1fad2
JS		 4701
4702 ieee80211_tx_info_clear_status(tx_info);
4703 tx_info->status.rates[0].idx = -1;
4704 tx_info->status.rates[0].count = 0;
4705
4706 if (!urb->status)
4707 tx_info->flags |= IEEE80211_TX_STAT_ACK;
4708
4709 ieee80211_tx_status_irqsafe(hw, skb);
4710
179e1742 4711 rtl8xxxu_free_tx_urb(priv, tx_urb);
26f1fad2
JS		 4712}
4713
4714static void rtl8xxxu_dump_action(struct device *dev,
4715 struct ieee80211_hdr *hdr)
4716{
4717 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
4718 u16 cap, timeout;
4719
4720 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
4721 return;
4722
4723 switch (mgmt->u.action.u.addba_resp.action_code) {
4724 case WLAN_ACTION_ADDBA_RESP:
4725 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
4726 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
4727 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
4728 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
4729 "status %02x\n",
4730 timeout,
4731 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4732 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4733 (cap >> 1) & 0x1,
4734 le16_to_cpu(mgmt->u.action.u.addba_resp.status));
4735 break;
4736 case WLAN_ACTION_ADDBA_REQ:
4737 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
4738 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
4739 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
4740 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
4741 timeout,
4742 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4743 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4744 (cap >> 1) & 0x1);
4745 break;
4746 default:
4747 dev_info(dev, "action frame %02x\n",
4748 mgmt->u.action.u.addba_resp.action_code);
4749 break;
4750 }
4751}
4752
b59415c2
JS		 4753/*
4754 * Fill in v1 (gen1) specific TX descriptor bits.
4755 * This format is used on 8188cu/8192cu/8723au
4756 */
4757void
4758rtl8xxxu_fill_txdesc_v1(struct ieee80211_hdr *hdr,
4759 struct rtl8xxxu_txdesc32 *tx_desc, u32 rate,
4760 u16 rate_flag, bool sgi, bool short_preamble,
4761 bool ampdu_enable)
4762{
4763 u16 seq_number;
4764
4765 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
4766
4767 tx_desc->txdw5 = cpu_to_le32(rate);
4768
4769 if (ieee80211_is_data(hdr->frame_control))
4770 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
4771
4772 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT);
4773
4774 if (ampdu_enable)
4775 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE);
4776 else
4777 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK);
4778
4779 if (ieee80211_is_mgmt(hdr->frame_control)) {
4780 tx_desc->txdw5 = cpu_to_le32(rate);
4781 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
4782 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT);
4783 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE);
4784 }
4785
4786 if (ieee80211_is_data_qos(hdr->frame_control))
4787 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS);
4788
4789 if (short_preamble)
4790 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE);
4791
4792 if (sgi)
4793 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI);
4794
4795 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
4796 /*
4797 * Use RTS rate 24M - does the mac80211 tell
4798 * us which to use?
4799 */
4800 tx_desc->txdw4 |= cpu_to_le32(DESC_RATE_24M <<
4801 TXDESC32_RTS_RATE_SHIFT);
4802 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE);
4803 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
4804 }
4805}
4806
4807/*
4808 * Fill in v2 (gen2) specific TX descriptor bits.
4809 * This format is used on 8192eu/8723bu
4810 */
4811void
4812rtl8xxxu_fill_txdesc_v2(struct ieee80211_hdr *hdr,
4813 struct rtl8xxxu_txdesc32 *tx_desc32, u32 rate,
4814 u16 rate_flag, bool sgi, bool short_preamble,
4815 bool ampdu_enable)
4816{
4817 struct rtl8xxxu_txdesc40 *tx_desc40;
4818 u16 seq_number;
4819
4820 tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc32;
4821
4822 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
4823
4824 tx_desc40->txdw4 = cpu_to_le32(rate);
4825 if (ieee80211_is_data(hdr->frame_control)) {
4826 tx_desc40->txdw4 |= cpu_to_le32(0x1f <<
4827 TXDESC40_DATA_RATE_FB_SHIFT);
4828 }
4829
4830 tx_desc40->txdw9 = cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT);
4831
4832 if (ampdu_enable)
4833 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE);
4834 else
4835 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK);
4836
4837 if (ieee80211_is_mgmt(hdr->frame_control)) {
4838 tx_desc40->txdw4 = cpu_to_le32(rate);
4839 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_USE_DRIVER_RATE);
4840 tx_desc40->txdw4 |=
4841 cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT);
4842 tx_desc40->txdw4 |= cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE);
4843 }
4844
4845 if (short_preamble)
4846 tx_desc40->txdw5 |= cpu_to_le32(TXDESC40_SHORT_PREAMBLE);
4847
4848 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
4849 /*
4850 * Use RTS rate 24M - does the mac80211 tell
4851 * us which to use?
4852 */
4853 tx_desc40->txdw4 |= cpu_to_le32(DESC_RATE_24M <<
4854 TXDESC40_RTS_RATE_SHIFT);
4855 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE);
4856 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE);
4857 }
4858}
4859
26f1fad2
JS		 4860static void rtl8xxxu_tx(struct ieee80211_hw *hw,
4861 struct ieee80211_tx_control *control,
4862 struct sk_buff *skb)
4863{
4864 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4865 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
4866 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
4867 struct rtl8xxxu_priv *priv = hw->priv;
dbb2896b 4868 struct rtl8xxxu_txdesc32 *tx_desc;
26f1fad2
JS		 4869 struct rtl8xxxu_tx_urb *tx_urb;
4870 struct ieee80211_sta *sta = NULL;
4871 struct ieee80211_vif *vif = tx_info->control.vif;
4872 struct device *dev = &priv->udev->dev;
4873 u32 queue, rate;
4874 u16 pktlen = skb->len;
4875 u16 seq_number;
4876 u16 rate_flag = tx_info->control.rates[0].flags;
179e1742 4877 int tx_desc_size = priv->fops->tx_desc_size;
26f1fad2 4878 int ret;
99afaac4 4879 bool usedesc40, ampdu_enable, sgi = false, short_preamble = false;
26f1fad2 4880
179e1742 4881 if (skb_headroom(skb) < tx_desc_size) {
26f1fad2
JS		 4882 dev_warn(dev,
4883 "%s: Not enough headroom (%i) for tx descriptor\n",
4884 __func__, skb_headroom(skb));
4885 goto error;
4886 }
4887
179e1742 4888 if (unlikely(skb->len > (65535 - tx_desc_size))) {
26f1fad2
JS		 4889 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
4890 __func__, skb->len);
4891 goto error;
4892 }
4893
4894 tx_urb = rtl8xxxu_alloc_tx_urb(priv);
4895 if (!tx_urb) {
4896 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
4897 goto error;
4898 }
4899
4900 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
4901 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
4902 __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
4903
4904 if (ieee80211_is_action(hdr->frame_control))
4905 rtl8xxxu_dump_action(dev, hdr);
4906
cc2646d4 4907 usedesc40 = (tx_desc_size == 40);
26f1fad2
JS		 4908 tx_info->rate_driver_data[0] = hw;
4909
4910 if (control && control->sta)
4911 sta = control->sta;
4912
dbb2896b 4913 tx_desc = (struct rtl8xxxu_txdesc32 *)skb_push(skb, tx_desc_size);
26f1fad2 4914
179e1742 4915 memset(tx_desc, 0, tx_desc_size);
26f1fad2 4916 tx_desc->pkt_size = cpu_to_le16(pktlen);
179e1742 4917 tx_desc->pkt_offset = tx_desc_size;
26f1fad2
JS		 4918
4919 tx_desc->txdw0 =
4920 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
4921 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
4922 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
4923 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
4924
4925 queue = rtl8xxxu_queue_select(hw, skb);
4926 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
4927
4928 if (tx_info->control.hw_key) {
4929 switch (tx_info->control.hw_key->cipher) {
4930 case WLAN_CIPHER_SUITE_WEP40:
4931 case WLAN_CIPHER_SUITE_WEP104:
4932 case WLAN_CIPHER_SUITE_TKIP:
4933 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
4934 break;
4935 case WLAN_CIPHER_SUITE_CCMP:
4936 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
4937 break;
4938 default:
4939 break;
4940 }
4941 }
4942
26f1fad2 4943 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
a40ace4f 4944 ampdu_enable = false;
26f1fad2
JS		 4945 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
4946 if (sta->ht_cap.ht_supported) {
4947 u32 ampdu, val32;
4948
4949 ampdu = (u32)sta->ht_cap.ampdu_density;
4950 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
4951 tx_desc->txdw2 |= cpu_to_le32(val32);
ce2d1dbb 4952
a40ace4f
JS		 4953 ampdu_enable = true;
4954 }
4955 }
4956
be49b1f1
JS		 4957 if (rate_flag & IEEE80211_TX_RC_MCS &&
4958 !ieee80211_is_mgmt(hdr->frame_control))
4c683607
JS		 4959 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
4960 else
4961 rate = tx_rate->hw_value;
4962
3972cc57
JS		 4963 if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
4964 (ieee80211_is_data_qos(hdr->frame_control) &&
4965 sta && sta->ht_cap.cap &
4966 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)))
4967 sgi = true;
4968
99afaac4
JS		 4969 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
4970 (sta && vif && vif->bss_conf.use_short_preamble))
4971 short_preamble = true;
4972
cc2646d4 4973 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
4c683607 4974
b59415c2
JS		 4975 priv->fops->fill_txdesc(hdr, tx_desc, rate, rate_flag,
4976 sgi, short_preamble, ampdu_enable);
26f1fad2
JS		 4977
4978 rtl8xxxu_calc_tx_desc_csum(tx_desc);
4979
4980 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
4981 skb->data, skb->len, rtl8xxxu_tx_complete, skb);
4982
4983 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
4984 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
4985 if (ret) {
4986 usb_unanchor_urb(&tx_urb->urb);
4987 rtl8xxxu_free_tx_urb(priv, tx_urb);
4988 goto error;
4989 }
4990 return;
4991error:
4992 dev_kfree_skb(skb);
4993}
4994
4995static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
4996 struct ieee80211_rx_status *rx_status,
87957081
JS		 4997 struct rtl8723au_phy_stats *phy_stats,
4998 u32 rxmcs)
26f1fad2
JS		 4999{
5000 if (phy_stats->sgi_en)
5001 rx_status->flag |= RX_FLAG_SHORT_GI;
5002
87957081 5003 if (rxmcs < DESC_RATE_6M) {
26f1fad2
JS		 5004 /*
5005 * Handle PHY stats for CCK rates
5006 */
5007 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
5008
5009 switch (cck_agc_rpt & 0xc0) {
5010 case 0xc0:
5011 rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
5012 break;
5013 case 0x80:
5014 rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
5015 break;
5016 case 0x40:
5017 rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
5018 break;
5019 case 0x00:
5020 rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
5021 break;
5022 }
5023 } else {
5024 rx_status->signal =
5025 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
5026 }
5027}
5028
5029static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
5030{
5031 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5032 unsigned long flags;
5033
5034 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5035
5036 list_for_each_entry_safe(rx_urb, tmp,
5037 &priv->rx_urb_pending_list, list) {
5038 list_del(&rx_urb->list);
5039 priv->rx_urb_pending_count--;
5040 usb_free_urb(&rx_urb->urb);
5041 }
5042
5043 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5044}
5045
5046static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
5047 struct rtl8xxxu_rx_urb *rx_urb)
5048{
5049 struct sk_buff *skb;
5050 unsigned long flags;
5051 int pending = 0;
5052
5053 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5054
5055 if (!priv->shutdown) {
5056 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
5057 priv->rx_urb_pending_count++;
5058 pending = priv->rx_urb_pending_count;
5059 } else {
5060 skb = (struct sk_buff *)rx_urb->urb.context;
5061 dev_kfree_skb(skb);
5062 usb_free_urb(&rx_urb->urb);
5063 }
5064
5065 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5066
5067 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
5068 schedule_work(&priv->rx_urb_wq);
5069}
5070
5071static void rtl8xxxu_rx_urb_work(struct work_struct *work)
5072{
5073 struct rtl8xxxu_priv *priv;
5074 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5075 struct list_head local;
5076 struct sk_buff *skb;
5077 unsigned long flags;
5078 int ret;
5079
5080 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
5081 INIT_LIST_HEAD(&local);
5082
5083 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5084
5085 list_splice_init(&priv->rx_urb_pending_list, &local);
5086 priv->rx_urb_pending_count = 0;
5087
5088 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5089
5090 list_for_each_entry_safe(rx_urb, tmp, &local, list) {
5091 list_del_init(&rx_urb->list);
5092 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5093 /*
5094 * If out of memory or temporary error, put it back on the
5095 * queue and try again. Otherwise the device is dead/gone
5096 * and we should drop it.
5097 */
5098 switch (ret) {
5099 case 0:
5100 break;
5101 case -ENOMEM:
5102 case -EAGAIN:
5103 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5104 break;
5105 default:
5106 pr_info("failed to requeue urb %i\n", ret);
5107 skb = (struct sk_buff *)rx_urb->urb.context;
5108 dev_kfree_skb(skb);
5109 usb_free_urb(&rx_urb->urb);
5110 }
5111 }
5112}
5113
a635df8a
JS		 5114static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv,
5115 struct sk_buff *skb)
5116{
5117 struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data;
5118 struct device *dev = &priv->udev->dev;
5119 int len;
5120
5121 len = skb->len - 2;
5122
5123 dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n",
5124 c2h->id, c2h->seq, len, c2h->bt_info.response_source);
5125
5126 switch(c2h->id) {
5127 case C2H_8723B_BT_INFO:
5128 if (c2h->bt_info.response_source >
5129 BT_INFO_SRC_8723B_BT_ACTIVE_SEND)
5130 dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n");
5131 else
5132 dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n");
5133
5134 if (c2h->bt_info.bt_has_reset)
5135 dev_dbg(dev, "BT has been reset\n");
5136 if (c2h->bt_info.tx_rx_mask)
5137 dev_dbg(dev, "BT TRx mask\n");
5138
5139 break;
5140 case C2H_8723B_BT_MP_INFO:
5141 dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n",
5142 c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status);
5143 break;
5144 case C2H_8723B_RA_REPORT:
5145 dev_dbg(dev,
5146 "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n",
5147 c2h->ra_report.rate, c2h->ra_report.dummy0_0,
5148 c2h->ra_report.macid, c2h->ra_report.noisy_state);
5149 break;
5150 default:
5151 dev_info(dev, "Unhandled C2H event %02x seq %02x\n",
5152 c2h->id, c2h->seq);
5153 print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE,
5154 16, 1, c2h->raw.payload, len, false);
5155 break;
5156 }
5157}
5158
2db125d4 5159int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb)
b18cdfdb 5160{
c14ee43b 5161 struct ieee80211_hw *hw = priv->hw;
040b97be
JS		 5162 struct ieee80211_rx_status *rx_status;
5163 struct rtl8xxxu_rxdesc16 *rx_desc;
b18cdfdb 5164 struct rtl8723au_phy_stats *phy_stats;
040b97be
JS		 5165 struct sk_buff *next_skb = NULL;
5166 __le32 *_rx_desc_le;
5167 u32 *_rx_desc;
b18cdfdb 5168 int drvinfo_sz, desc_shift;
040b97be 5169 int i, pkt_cnt, pkt_len, urb_len, pkt_offset;
2cb79eb7 5170
040b97be
JS		 5171 urb_len = skb->len;
5172 pkt_cnt = 0;
b18cdfdb 5173
040b97be
JS		 5174 do {
5175 rx_desc = (struct rtl8xxxu_rxdesc16 *)skb->data;
5176 _rx_desc_le = (__le32 *)skb->data;
5177 _rx_desc = (u32 *)skb->data;
c14ee43b 5178
040b97be
JS		 5179 for (i = 0;
5180 i < (sizeof(struct rtl8xxxu_rxdesc16) / sizeof(u32)); i++)
5181 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
b18cdfdb 5182
040b97be
JS		 5183 /*
5184 * Only read pkt_cnt from the header if we're parsing the
5185 * first packet
5186 */
5187 if (!pkt_cnt)
5188 pkt_cnt = rx_desc->pkt_cnt;
5189 pkt_len = rx_desc->pktlen;
b18cdfdb 5190
040b97be
JS		 5191 drvinfo_sz = rx_desc->drvinfo_sz * 8;
5192 desc_shift = rx_desc->shift;
5193 pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift +
5194 sizeof(struct rtl8xxxu_rxdesc16), 128);
b18cdfdb 5195
040b97be
JS		 5196 if (pkt_cnt > 1)
5197 next_skb = skb_clone(skb, GFP_ATOMIC);
b18cdfdb 5198
040b97be
JS		 5199 rx_status = IEEE80211_SKB_RXCB(skb);
5200 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
b18cdfdb 5201
040b97be 5202 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc16));
b18cdfdb 5203
040b97be
JS		 5204 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
5205
5206 skb_pull(skb, drvinfo_sz + desc_shift);
5207
5208 skb_trim(skb, pkt_len);
5209
5210 if (rx_desc->phy_stats)
5211 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats,
5212 rx_desc->rxmcs);
5213
5214 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
5215 rx_status->flag |= RX_FLAG_MACTIME_START;
5216
5217 if (!rx_desc->swdec)
5218 rx_status->flag |= RX_FLAG_DECRYPTED;
5219 if (rx_desc->crc32)
5220 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
5221 if (rx_desc->bw)
5222 rx_status->flag |= RX_FLAG_40MHZ;
5223
5224 if (rx_desc->rxht) {
5225 rx_status->flag |= RX_FLAG_HT;
5226 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
5227 } else {
5228 rx_status->rate_idx = rx_desc->rxmcs;
5229 }
5230
5231 rx_status->freq = hw->conf.chandef.chan->center_freq;
5232 rx_status->band = hw->conf.chandef.chan->band;
5233
5234 ieee80211_rx_irqsafe(hw, skb);
5235
5236 skb = next_skb;
5237 if (skb)
5238 skb_pull(next_skb, pkt_offset);
b18cdfdb 5239
040b97be
JS		 5240 pkt_cnt--;
5241 urb_len -= pkt_offset;
5242 } while (skb && urb_len > 0 && pkt_cnt > 0);
c14ee43b 5243
b18cdfdb
JS		 5244 return RX_TYPE_DATA_PKT;
5245}
5246
2db125d4 5247int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb)
b18cdfdb 5248{
c14ee43b 5249 struct ieee80211_hw *hw = priv->hw;
2db125d4 5250 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
a49c7ce1
JS		 5251 struct rtl8xxxu_rxdesc24 *rx_desc =
5252 (struct rtl8xxxu_rxdesc24 *)skb->data;
b18cdfdb 5253 struct rtl8723au_phy_stats *phy_stats;
2cb79eb7
JS		 5254 __le32 *_rx_desc_le = (__le32 *)skb->data;
5255 u32 *_rx_desc = (u32 *)skb->data;
b18cdfdb 5256 int drvinfo_sz, desc_shift;
2cb79eb7
JS		 5257 int i;
5258
a49c7ce1 5259 for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++)
2cb79eb7 5260 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
b18cdfdb 5261
c14ee43b
JS		 5262 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
5263
a49c7ce1 5264 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24));
b18cdfdb
JS		 5265
5266 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
5267
5268 drvinfo_sz = rx_desc->drvinfo_sz * 8;
5269 desc_shift = rx_desc->shift;
5270 skb_pull(skb, drvinfo_sz + desc_shift);
5271
e975b87c
JS		 5272 if (rx_desc->rpt_sel) {
5273 struct device *dev = &priv->udev->dev;
5274 dev_dbg(dev, "%s: C2H packet\n", __func__);
a635df8a
JS		 5275 rtl8723bu_handle_c2h(priv, skb);
5276 dev_kfree_skb(skb);
e975b87c
JS		 5277 return RX_TYPE_C2H;
5278 }
5279
87957081
JS		 5280 if (rx_desc->phy_stats)
5281 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats,
5282 rx_desc->rxmcs);
5283
b18cdfdb
JS		 5284 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
5285 rx_status->flag |= RX_FLAG_MACTIME_START;
5286
5287 if (!rx_desc->swdec)
5288 rx_status->flag |= RX_FLAG_DECRYPTED;
5289 if (rx_desc->crc32)
5290 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
5291 if (rx_desc->bw)
5292 rx_status->flag |= RX_FLAG_40MHZ;
5293
5294 if (rx_desc->rxmcs >= DESC_RATE_MCS0) {
5295 rx_status->flag |= RX_FLAG_HT;
5296 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
5297 } else {
5298 rx_status->rate_idx = rx_desc->rxmcs;
5299 }
5300
c14ee43b
JS		 5301 rx_status->freq = hw->conf.chandef.chan->center_freq;
5302 rx_status->band = hw->conf.chandef.chan->band;
5303
a635df8a 5304 ieee80211_rx_irqsafe(hw, skb);
e975b87c 5305 return RX_TYPE_DATA_PKT;
b18cdfdb
JS		 5306}
5307
26f1fad2
JS		 5308static void rtl8xxxu_rx_complete(struct urb *urb)
5309{
5310 struct rtl8xxxu_rx_urb *rx_urb =
5311 container_of(urb, struct rtl8xxxu_rx_urb, urb);
5312 struct ieee80211_hw *hw = rx_urb->hw;
5313 struct rtl8xxxu_priv *priv = hw->priv;
5314 struct sk_buff *skb = (struct sk_buff *)urb->context;
26f1fad2 5315 struct device *dev = &priv->udev->dev;
26f1fad2 5316
26f1fad2
JS		 5317 skb_put(skb, urb->actual_length);
5318
5319 if (urb->status == 0) {
2db125d4 5320 priv->fops->parse_rx_desc(priv, skb);
26f1fad2 5321
26f1fad2
JS		 5322 skb = NULL;
5323 rx_urb->urb.context = NULL;
5324 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5325 } else {
5326 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5327 goto cleanup;
5328 }
5329 return;
5330
5331cleanup:
5332 usb_free_urb(urb);
5333 dev_kfree_skb(skb);
5334 return;
5335}
5336
5337static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
5338 struct rtl8xxxu_rx_urb *rx_urb)
5339{
04319ae2 5340 struct rtl8xxxu_fileops *fops = priv->fops;
26f1fad2
JS		 5341 struct sk_buff *skb;
5342 int skb_size;
a49c7ce1 5343 int ret, rx_desc_sz;
26f1fad2 5344
04319ae2
JS		 5345 rx_desc_sz = fops->rx_desc_size;
5346
1e5b3b3f 5347 if (priv->rx_buf_aggregation && fops->rx_agg_buf_size) {
04319ae2 5348 skb_size = fops->rx_agg_buf_size;
1e5b3b3f
JS		 5349 skb_size += (rx_desc_sz + sizeof(struct rtl8723au_phy_stats));
5350 } else {
04319ae2 5351 skb_size = IEEE80211_MAX_FRAME_LEN;
1e5b3b3f 5352 }
04319ae2 5353
26f1fad2
JS		 5354 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
5355 if (!skb)
5356 return -ENOMEM;
5357
a49c7ce1 5358 memset(skb->data, 0, rx_desc_sz);
26f1fad2
JS		 5359 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
5360 skb_size, rtl8xxxu_rx_complete, skb);
5361 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
5362 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
5363 if (ret)
5364 usb_unanchor_urb(&rx_urb->urb);
5365 return ret;
5366}
5367
5368static void rtl8xxxu_int_complete(struct urb *urb)
5369{
5370 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
5371 struct device *dev = &priv->udev->dev;
5372 int ret;
5373
5374 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5375 if (urb->status == 0) {
5376 usb_anchor_urb(urb, &priv->int_anchor);
5377 ret = usb_submit_urb(urb, GFP_ATOMIC);
5378 if (ret)
5379 usb_unanchor_urb(urb);
5380 } else {
78383ac9 5381 dev_dbg(dev, "%s: Error %i\n", __func__, urb->status);
26f1fad2
JS		 5382 }
5383}
5384
5385
5386static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
5387{
5388 struct rtl8xxxu_priv *priv = hw->priv;
5389 struct urb *urb;
5390 u32 val32;
5391 int ret;
5392
5393 urb = usb_alloc_urb(0, GFP_KERNEL);
5394 if (!urb)
5395 return -ENOMEM;
5396
5397 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
5398 priv->int_buf, USB_INTR_CONTENT_LENGTH,
5399 rtl8xxxu_int_complete, priv, 1);
5400 usb_anchor_urb(urb, &priv->int_anchor);
5401 ret = usb_submit_urb(urb, GFP_KERNEL);
5402 if (ret) {
5403 usb_unanchor_urb(urb);
5404 goto error;
5405 }
5406
5407 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
5408 val32 |= USB_HIMR_CPWM;
5409 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
5410
5411error:
5412 return ret;
5413}
5414
5415static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
5416 struct ieee80211_vif *vif)
5417{
5418 struct rtl8xxxu_priv *priv = hw->priv;
5419 int ret;
5420 u8 val8;
5421
5422 switch (vif->type) {
5423 case NL80211_IFTYPE_STATION:
97db5a87 5424 rtl8xxxu_stop_tx_beacon(priv);
26f1fad2
JS		 5425
5426 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5427 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
5428 BEACON_DISABLE_TSF_UPDATE;
5429 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5430 ret = 0;
5431 break;
5432 default:
5433 ret = -EOPNOTSUPP;
5434 }
5435
5436 rtl8xxxu_set_linktype(priv, vif->type);
5437
5438 return ret;
5439}
5440
5441static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
5442 struct ieee80211_vif *vif)
5443{
5444 struct rtl8xxxu_priv *priv = hw->priv;
5445
5446 dev_dbg(&priv->udev->dev, "%s\n", __func__);
5447}
5448
5449static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
5450{
5451 struct rtl8xxxu_priv *priv = hw->priv;
5452 struct device *dev = &priv->udev->dev;
5453 u16 val16;
5454 int ret = 0, channel;
5455 bool ht40;
5456
5457 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
5458 dev_info(dev,
5459 "%s: channel: %i (changed %08x chandef.width %02x)\n",
5460 __func__, hw->conf.chandef.chan->hw_value,
5461 changed, hw->conf.chandef.width);
5462
5463 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
5464 val16 = ((hw->conf.long_frame_max_tx_count <<
5465 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
5466 ((hw->conf.short_frame_max_tx_count <<
5467 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
5468 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
5469 }
5470
5471 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
5472 switch (hw->conf.chandef.width) {
5473 case NL80211_CHAN_WIDTH_20_NOHT:
5474 case NL80211_CHAN_WIDTH_20:
5475 ht40 = false;
5476 break;
5477 case NL80211_CHAN_WIDTH_40:
5478 ht40 = true;
5479 break;
5480 default:
5481 ret = -ENOTSUPP;
5482 goto exit;
5483 }
5484
5485 channel = hw->conf.chandef.chan->hw_value;
5486
e796dab4 5487 priv->fops->set_tx_power(priv, channel, ht40);
26f1fad2 5488
1ea8e846 5489 priv->fops->config_channel(hw);
26f1fad2
JS		 5490 }
5491
5492exit:
5493 return ret;
5494}
5495
5496static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
5497 struct ieee80211_vif *vif, u16 queue,
5498 const struct ieee80211_tx_queue_params *param)
5499{
5500 struct rtl8xxxu_priv *priv = hw->priv;
5501 struct device *dev = &priv->udev->dev;
5502 u32 val32;
5503 u8 aifs, acm_ctrl, acm_bit;
5504
5505 aifs = param->aifs;
5506
5507 val32 = aifs |
5508 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
5509 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
5510 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
5511
5512 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
5513 dev_dbg(dev,
5514 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
5515 __func__, queue, val32, param->acm, acm_ctrl);
5516
5517 switch (queue) {
5518 case IEEE80211_AC_VO:
5519 acm_bit = ACM_HW_CTRL_VO;
5520 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
5521 break;
5522 case IEEE80211_AC_VI:
5523 acm_bit = ACM_HW_CTRL_VI;
5524 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
5525 break;
5526 case IEEE80211_AC_BE:
5527 acm_bit = ACM_HW_CTRL_BE;
5528 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
5529 break;
5530 case IEEE80211_AC_BK:
5531 acm_bit = ACM_HW_CTRL_BK;
5532 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
5533 break;
5534 default:
5535 acm_bit = 0;
5536 break;
5537 }
5538
5539 if (param->acm)
5540 acm_ctrl |= acm_bit;
5541 else
5542 acm_ctrl &= ~acm_bit;
5543 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
5544
5545 return 0;
5546}
5547
5548static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
5549 unsigned int changed_flags,
5550 unsigned int *total_flags, u64 multicast)
5551{
5552 struct rtl8xxxu_priv *priv = hw->priv;
3bed4bfa 5553 u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
26f1fad2
JS		 5554
5555 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
5556 __func__, changed_flags, *total_flags);
5557
3bed4bfa
BR		 5558 /*
5559 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
5560 */
5561
5562 if (*total_flags & FIF_FCSFAIL)
5563 rcr |= RCR_ACCEPT_CRC32;
5564 else
5565 rcr &= ~RCR_ACCEPT_CRC32;
5566
5567 /*
5568 * FIF_PLCPFAIL not supported?
5569 */
5570
5571 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
5572 rcr &= ~RCR_CHECK_BSSID_BEACON;
5573 else
5574 rcr |= RCR_CHECK_BSSID_BEACON;
5575
5576 if (*total_flags & FIF_CONTROL)
5577 rcr |= RCR_ACCEPT_CTRL_FRAME;
5578 else
5579 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
5580
5581 if (*total_flags & FIF_OTHER_BSS) {
5582 rcr |= RCR_ACCEPT_AP;
5583 rcr &= ~RCR_CHECK_BSSID_MATCH;
5584 } else {
5585 rcr &= ~RCR_ACCEPT_AP;
5586 rcr |= RCR_CHECK_BSSID_MATCH;
5587 }
5588
5589 if (*total_flags & FIF_PSPOLL)
5590 rcr |= RCR_ACCEPT_PM;
5591 else
5592 rcr &= ~RCR_ACCEPT_PM;
5593
5594 /*
5595 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
5596 */
5597
5598 rtl8xxxu_write32(priv, REG_RCR, rcr);
5599
755bda11
JS		 5600 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
5601 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
5602 FIF_PROBE_REQ);
26f1fad2
JS		 5603}
5604
5605static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
5606{
5607 if (rts > 2347)
5608 return -EINVAL;
5609
5610 return 0;
5611}
5612
5613static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5614 struct ieee80211_vif *vif,
5615 struct ieee80211_sta *sta,
5616 struct ieee80211_key_conf *key)
5617{
5618 struct rtl8xxxu_priv *priv = hw->priv;
5619 struct device *dev = &priv->udev->dev;
5620 u8 mac_addr[ETH_ALEN];
5621 u8 val8;
5622 u16 val16;
5623 u32 val32;
5624 int retval = -EOPNOTSUPP;
5625
5626 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
5627 __func__, cmd, key->cipher, key->keyidx);
5628
5629 if (vif->type != NL80211_IFTYPE_STATION)
5630 return -EOPNOTSUPP;
5631
5632 if (key->keyidx > 3)
5633 return -EOPNOTSUPP;
5634
5635 switch (key->cipher) {
5636 case WLAN_CIPHER_SUITE_WEP40:
5637 case WLAN_CIPHER_SUITE_WEP104:
5638
5639 break;
5640 case WLAN_CIPHER_SUITE_CCMP:
5641 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
5642 break;
5643 case WLAN_CIPHER_SUITE_TKIP:
5644 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
5645 default:
5646 return -EOPNOTSUPP;
5647 }
5648
5649 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
5650 dev_dbg(dev, "%s: pairwise key\n", __func__);
5651 ether_addr_copy(mac_addr, sta->addr);
5652 } else {
5653 dev_dbg(dev, "%s: group key\n", __func__);
5654 eth_broadcast_addr(mac_addr);
5655 }
5656
5657 val16 = rtl8xxxu_read16(priv, REG_CR);
5658 val16 |= CR_SECURITY_ENABLE;
5659 rtl8xxxu_write16(priv, REG_CR, val16);
5660
5661 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
5662 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
5663 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
5664 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
5665
5666 switch (cmd) {
5667 case SET_KEY:
5668 key->hw_key_idx = key->keyidx;
5669 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
5670 rtl8xxxu_cam_write(priv, key, mac_addr);
5671 retval = 0;
5672 break;
5673 case DISABLE_KEY:
5674 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
5675 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
5676 key->keyidx << CAM_CMD_KEY_SHIFT;
5677 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
5678 retval = 0;
5679 break;
5680 default:
5681 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
5682 }
5683
5684 return retval;
5685}
5686
5687static int
5688rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
50ea05ef 5689 struct ieee80211_ampdu_params *params)
26f1fad2
JS		 5690{
5691 struct rtl8xxxu_priv *priv = hw->priv;
5692 struct device *dev = &priv->udev->dev;
5693 u8 ampdu_factor, ampdu_density;
50ea05ef
SS		 5694 struct ieee80211_sta *sta = params->sta;
5695 enum ieee80211_ampdu_mlme_action action = params->action;
26f1fad2
JS		 5696
5697 switch (action) {
5698 case IEEE80211_AMPDU_TX_START:
7329dc13 5699 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
26f1fad2
JS		 5700 ampdu_factor = sta->ht_cap.ampdu_factor;
5701 ampdu_density = sta->ht_cap.ampdu_density;
5702 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
5703 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
5704 dev_dbg(dev,
5705 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
5706 ampdu_factor, ampdu_density);
5707 break;
5708 case IEEE80211_AMPDU_TX_STOP_FLUSH:
7329dc13 5709 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
26f1fad2
JS		 5710 rtl8xxxu_set_ampdu_factor(priv, 0);
5711 rtl8xxxu_set_ampdu_min_space(priv, 0);
5712 break;
5713 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
7329dc13 5714 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
26f1fad2
JS		 5715 __func__);
5716 rtl8xxxu_set_ampdu_factor(priv, 0);
5717 rtl8xxxu_set_ampdu_min_space(priv, 0);
5718 break;
5719 case IEEE80211_AMPDU_RX_START:
7329dc13 5720 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
26f1fad2
JS		 5721 break;
5722 case IEEE80211_AMPDU_RX_STOP:
7329dc13 5723 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
26f1fad2
JS		 5724 break;
5725 default:
5726 break;
5727 }
5728 return 0;
5729}
5730
5731static int rtl8xxxu_start(struct ieee80211_hw *hw)
5732{
5733 struct rtl8xxxu_priv *priv = hw->priv;
5734 struct rtl8xxxu_rx_urb *rx_urb;
5735 struct rtl8xxxu_tx_urb *tx_urb;
5736 unsigned long flags;
5737 int ret, i;
5738
5739 ret = 0;
5740
5741 init_usb_anchor(&priv->rx_anchor);
5742 init_usb_anchor(&priv->tx_anchor);
5743 init_usb_anchor(&priv->int_anchor);
5744
db08de94 5745 priv->fops->enable_rf(priv);
0e28b975
JS		 5746 if (priv->usb_interrupts) {
5747 ret = rtl8xxxu_submit_int_urb(hw);
5748 if (ret)
5749 goto exit;
5750 }
26f1fad2
JS		 5751
5752 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
5753 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
5754 if (!tx_urb) {
5755 if (!i)
5756 ret = -ENOMEM;
5757
5758 goto error_out;
5759 }
5760 usb_init_urb(&tx_urb->urb);
5761 INIT_LIST_HEAD(&tx_urb->list);
5762 tx_urb->hw = hw;
5763 list_add(&tx_urb->list, &priv->tx_urb_free_list);
5764 priv->tx_urb_free_count++;
5765 }
5766
5767 priv->tx_stopped = false;
5768
5769 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5770 priv->shutdown = false;
5771 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5772
5773 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
5774 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
5775 if (!rx_urb) {
5776 if (!i)
5777 ret = -ENOMEM;
5778
5779 goto error_out;
5780 }
5781 usb_init_urb(&rx_urb->urb);
5782 INIT_LIST_HEAD(&rx_urb->list);
5783 rx_urb->hw = hw;
5784
5785 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5786 }
5787exit:
5788 /*
c85ea115 5789 * Accept all data and mgmt frames
26f1fad2 5790 */
c85ea115 5791 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
26f1fad2
JS		 5792 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
5793
5794 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
5795
5796 return ret;
5797
5798error_out:
5799 rtl8xxxu_free_tx_resources(priv);
5800 /*
5801 * Disable all data and mgmt frames
5802 */
5803 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5804 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5805
5806 return ret;
5807}
5808
5809static void rtl8xxxu_stop(struct ieee80211_hw *hw)
5810{
5811 struct rtl8xxxu_priv *priv = hw->priv;
5812 unsigned long flags;
5813
5814 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5815
5816 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5817 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5818
5819 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5820 priv->shutdown = true;
5821 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5822
5823 usb_kill_anchored_urbs(&priv->rx_anchor);
5824 usb_kill_anchored_urbs(&priv->tx_anchor);
0e28b975
JS		 5825 if (priv->usb_interrupts)
5826 usb_kill_anchored_urbs(&priv->int_anchor);
26f1fad2 5827
265697eb
JS		 5828 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5829
fc89a41f 5830 priv->fops->disable_rf(priv);
26f1fad2
JS		 5831
5832 /*
5833 * Disable interrupts
5834 */
0e28b975
JS		 5835 if (priv->usb_interrupts)
5836 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
26f1fad2
JS		 5837
5838 rtl8xxxu_free_rx_resources(priv);
5839 rtl8xxxu_free_tx_resources(priv);
5840}
5841
5842static const struct ieee80211_ops rtl8xxxu_ops = {
5843 .tx = rtl8xxxu_tx,
5844 .add_interface = rtl8xxxu_add_interface,
5845 .remove_interface = rtl8xxxu_remove_interface,
5846 .config = rtl8xxxu_config,
5847 .conf_tx = rtl8xxxu_conf_tx,
5848 .bss_info_changed = rtl8xxxu_bss_info_changed,
5849 .configure_filter = rtl8xxxu_configure_filter,
5850 .set_rts_threshold = rtl8xxxu_set_rts_threshold,
5851 .start = rtl8xxxu_start,
5852 .stop = rtl8xxxu_stop,
5853 .sw_scan_start = rtl8xxxu_sw_scan_start,
5854 .sw_scan_complete = rtl8xxxu_sw_scan_complete,
5855 .set_key = rtl8xxxu_set_key,
5856 .ampdu_action = rtl8xxxu_ampdu_action,
5857};
5858
5859static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
5860 struct usb_interface *interface)
5861{
5862 struct usb_interface_descriptor *interface_desc;
5863 struct usb_host_interface *host_interface;
5864 struct usb_endpoint_descriptor *endpoint;
5865 struct device *dev = &priv->udev->dev;
5866 int i, j = 0, endpoints;
5867 u8 dir, xtype, num;
5868 int ret = 0;
5869
5870 host_interface = &interface->altsetting[0];
5871 interface_desc = &host_interface->desc;
5872 endpoints = interface_desc->bNumEndpoints;
5873
5874 for (i = 0; i < endpoints; i++) {
5875 endpoint = &host_interface->endpoint[i].desc;
5876
5877 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
5878 num = usb_endpoint_num(endpoint);
5879 xtype = usb_endpoint_type(endpoint);
5880 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5881 dev_dbg(dev,
5882 "%s: endpoint: dir %02x, # %02x, type %02x\n",
5883 __func__, dir, num, xtype);
5884 if (usb_endpoint_dir_in(endpoint) &&
5885 usb_endpoint_xfer_bulk(endpoint)) {
5886 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5887 dev_dbg(dev, "%s: in endpoint num %i\n",
5888 __func__, num);
5889
5890 if (priv->pipe_in) {
5891 dev_warn(dev,
5892 "%s: Too many IN pipes\n", __func__);
5893 ret = -EINVAL;
5894 goto exit;
5895 }
5896
5897 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
5898 }
5899
5900 if (usb_endpoint_dir_in(endpoint) &&
5901 usb_endpoint_xfer_int(endpoint)) {
5902 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5903 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
5904 __func__, num);
5905
5906 if (priv->pipe_interrupt) {
5907 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
5908 __func__);
5909 ret = -EINVAL;
5910 goto exit;
5911 }
5912
5913 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
5914 }
5915
5916 if (usb_endpoint_dir_out(endpoint) &&
5917 usb_endpoint_xfer_bulk(endpoint)) {
5918 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5919 dev_dbg(dev, "%s: out endpoint num %i\n",
5920 __func__, num);
5921 if (j >= RTL8XXXU_OUT_ENDPOINTS) {
5922 dev_warn(dev,
5923 "%s: Too many OUT pipes\n", __func__);
5924 ret = -EINVAL;
5925 goto exit;
5926 }
5927 priv->out_ep[j++] = num;
5928 }
5929 }
5930exit:
5931 priv->nr_out_eps = j;
5932 return ret;
5933}
5934
5935static int rtl8xxxu_probe(struct usb_interface *interface,
5936 const struct usb_device_id *id)
5937{
5938 struct rtl8xxxu_priv *priv;
5939 struct ieee80211_hw *hw;
5940 struct usb_device *udev;
5941 struct ieee80211_supported_band *sband;
deb6176e 5942 int ret;
26f1fad2
JS		 5943 int untested = 1;
5944
5945 udev = usb_get_dev(interface_to_usbdev(interface));
5946
5947 switch (id->idVendor) {
5948 case USB_VENDOR_ID_REALTEK:
5949 switch(id->idProduct) {
5950 case 0x1724:
5951 case 0x8176:
5952 case 0x8178:
5953 case 0x817f:
5954 untested = 0;
5955 break;
5956 }
5957 break;
5958 case 0x7392:
5959 if (id->idProduct == 0x7811)
5960 untested = 0;
5961 break;
e1d70c9b
JS		 5962 case 0x050d:
5963 if (id->idProduct == 0x1004)
5964 untested = 0;
5965 break;
b81669b9
JS		 5966 case 0x20f4:
5967 if (id->idProduct == 0x648b)
5968 untested = 0;
5969 break;
76a8e07d
JS		 5970 case 0x2001:
5971 if (id->idProduct == 0x3308)
5972 untested = 0;
5973 break;
690a6d26
JS		 5974 case 0x2357:
5975 if (id->idProduct == 0x0109)
5976 untested = 0;
5977 break;
26f1fad2
JS		 5978 default:
5979 break;
5980 }
5981
5982 if (untested) {
eaa4d14c 5983 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE;
26f1fad2
JS		 5984 dev_info(&udev->dev,
5985 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
5986 id->idVendor, id->idProduct);
5987 dev_info(&udev->dev,
5988 "Please report results to Jes.Sorensen@gmail.com\n");
5989 }
5990
5991 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
5992 if (!hw) {
5993 ret = -ENOMEM;
deb6176e 5994 priv = NULL;
26f1fad2
JS		 5995 goto exit;
5996 }
5997
5998 priv = hw->priv;
5999 priv->hw = hw;
6000 priv->udev = udev;
6001 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
6002 mutex_init(&priv->usb_buf_mutex);
6003 mutex_init(&priv->h2c_mutex);
6004 INIT_LIST_HEAD(&priv->tx_urb_free_list);
6005 spin_lock_init(&priv->tx_urb_lock);
6006 INIT_LIST_HEAD(&priv->rx_urb_pending_list);
6007 spin_lock_init(&priv->rx_urb_lock);
6008 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
6009
6010 usb_set_intfdata(interface, hw);
6011
6012 ret = rtl8xxxu_parse_usb(priv, interface);
6013 if (ret)
6014 goto exit;
6015
6016 ret = rtl8xxxu_identify_chip(priv);
6017 if (ret) {
6018 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
6019 goto exit;
6020 }
6021
6022 ret = rtl8xxxu_read_efuse(priv);
6023 if (ret) {
6024 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
6025 goto exit;
6026 }
6027
6028 ret = priv->fops->parse_efuse(priv);
6029 if (ret) {
6030 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
6031 goto exit;
6032 }
6033
6034 rtl8xxxu_print_chipinfo(priv);
6035
6036 ret = priv->fops->load_firmware(priv);
6037 if (ret) {
6038 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
6039 goto exit;
6040 }
6041
6042 ret = rtl8xxxu_init_device(hw);
deb6176e
JS		 6043 if (ret)
6044 goto exit;
26f1fad2
JS		 6045
6046 hw->wiphy->max_scan_ssids = 1;
6047 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
6048 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
6049 hw->queues = 4;
6050
6051 sband = &rtl8xxxu_supported_band;
6052 sband->ht_cap.ht_supported = true;
6053 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
6054 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
6055 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
6056 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
6057 sband->ht_cap.mcs.rx_mask[0] = 0xff;
6058 sband->ht_cap.mcs.rx_mask[4] = 0x01;
6059 if (priv->rf_paths > 1) {
6060 sband->ht_cap.mcs.rx_mask[1] = 0xff;
6061 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
6062 }
6063 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
6064 /*
6065 * Some APs will negotiate HT20_40 in a noisy environment leading
6066 * to miserable performance. Rather than defaulting to this, only
6067 * enable it if explicitly requested at module load time.
6068 */
6069 if (rtl8xxxu_ht40_2g) {
6070 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
6071 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
6072 }
57fbcce3 6073 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
26f1fad2
JS		 6074
6075 hw->wiphy->rts_threshold = 2347;
6076
6077 SET_IEEE80211_DEV(priv->hw, &interface->dev);
6078 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
6079
179e1742 6080 hw->extra_tx_headroom = priv->fops->tx_desc_size;
26f1fad2
JS		 6081 ieee80211_hw_set(hw, SIGNAL_DBM);
6082 /*
6083 * The firmware handles rate control
6084 */
6085 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
6086 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
6087
6088 ret = ieee80211_register_hw(priv->hw);
6089 if (ret) {
6090 dev_err(&udev->dev, "%s: Failed to register: %i\n",
6091 __func__, ret);
6092 goto exit;
6093 }
6094
deb6176e
JS		 6095 return 0;
6096
26f1fad2 6097exit:
deb6176e
JS		 6098 usb_set_intfdata(interface, NULL);
6099
6100 if (priv) {
6101 kfree(priv->fw_data);
6102 mutex_destroy(&priv->usb_buf_mutex);
6103 mutex_destroy(&priv->h2c_mutex);
6104 }
6105 usb_put_dev(udev);
6106
6107 ieee80211_free_hw(hw);
6108
26f1fad2
JS		 6109 return ret;
6110}
6111
6112static void rtl8xxxu_disconnect(struct usb_interface *interface)
6113{
6114 struct rtl8xxxu_priv *priv;
6115 struct ieee80211_hw *hw;
6116
6117 hw = usb_get_intfdata(interface);
6118 priv = hw->priv;
6119
8cae2f1d
JS		 6120 ieee80211_unregister_hw(hw);
6121
6122 priv->fops->power_off(priv);
6123
26f1fad2
JS		 6124 usb_set_intfdata(interface, NULL);
6125
6126 dev_info(&priv->udev->dev, "disconnecting\n");
6127
26f1fad2
JS		 6128 kfree(priv->fw_data);
6129 mutex_destroy(&priv->usb_buf_mutex);
6130 mutex_destroy(&priv->h2c_mutex);
6131
6132 usb_put_dev(priv->udev);
6133 ieee80211_free_hw(hw);
6134}
6135
26f1fad2
JS		 6136static struct usb_device_id dev_table[] = {
6137{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
6138 .driver_info = (unsigned long)&rtl8723au_fops},
6139{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
6140 .driver_info = (unsigned long)&rtl8723au_fops},
6141{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
6142 .driver_info = (unsigned long)&rtl8723au_fops},
3307d840
JS		 6143{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
6144 .driver_info = (unsigned long)&rtl8192eu_fops},
690a6d26
JS		 6145/* Tested by Myckel Habets */
6146{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0109, 0xff, 0xff, 0xff),
6147 .driver_info = (unsigned long)&rtl8192eu_fops},
35a741fe
JS		 6148{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
6149 .driver_info = (unsigned long)&rtl8723bu_fops},
033695bd
KV		 6150#ifdef CONFIG_RTL8XXXU_UNTESTED
6151/* Still supported by rtlwifi */
26f1fad2
JS		 6152{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
6153 .driver_info = (unsigned long)&rtl8192cu_fops},
6154{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
6155 .driver_info = (unsigned long)&rtl8192cu_fops},
6156{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
6157 .driver_info = (unsigned long)&rtl8192cu_fops},
6158/* Tested by Larry Finger */
6159{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
6160 .driver_info = (unsigned long)&rtl8192cu_fops},
e1d70c9b
JS		 6161/* Tested by Andrea Merello */
6162{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
6163 .driver_info = (unsigned long)&rtl8192cu_fops},
b81669b9
JS		 6164/* Tested by Jocelyn Mayer */
6165{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
6166 .driver_info = (unsigned long)&rtl8192cu_fops},
76a8e07d
JS		 6167/* Tested by Stefano Bravi */
6168{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
6169 .driver_info = (unsigned long)&rtl8192cu_fops},
26f1fad2
JS		 6170/* Currently untested 8188 series devices */
6171{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
6172 .driver_info = (unsigned long)&rtl8192cu_fops},
6173{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
6174 .driver_info = (unsigned long)&rtl8192cu_fops},
6175{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
6176 .driver_info = (unsigned long)&rtl8192cu_fops},
6177{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
6178 .driver_info = (unsigned long)&rtl8192cu_fops},
6179{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
6180 .driver_info = (unsigned long)&rtl8192cu_fops},
6181{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
6182 .driver_info = (unsigned long)&rtl8192cu_fops},
6183{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
6184 .driver_info = (unsigned long)&rtl8192cu_fops},
6185{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
6186 .driver_info = (unsigned long)&rtl8192cu_fops},
6187{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
6188 .driver_info = (unsigned long)&rtl8192cu_fops},
6189{USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
6190 .driver_info = (unsigned long)&rtl8192cu_fops},
6191{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
6192 .driver_info = (unsigned long)&rtl8192cu_fops},
6193{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
6194 .driver_info = (unsigned long)&rtl8192cu_fops},
6195{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
6196 .driver_info = (unsigned long)&rtl8192cu_fops},
6197{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
6198 .driver_info = (unsigned long)&rtl8192cu_fops},
6199{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
6200 .driver_info = (unsigned long)&rtl8192cu_fops},
6201{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
6202 .driver_info = (unsigned long)&rtl8192cu_fops},
6203{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
6204 .driver_info = (unsigned long)&rtl8192cu_fops},
6205{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
6206 .driver_info = (unsigned long)&rtl8192cu_fops},
6207{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
6208 .driver_info = (unsigned long)&rtl8192cu_fops},
6209{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
6210 .driver_info = (unsigned long)&rtl8192cu_fops},
6211{USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
6212 .driver_info = (unsigned long)&rtl8192cu_fops},
6213{USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
6214 .driver_info = (unsigned long)&rtl8192cu_fops},
6215{USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
6216 .driver_info = (unsigned long)&rtl8192cu_fops},
26f1fad2
JS		 6217{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
6218 .driver_info = (unsigned long)&rtl8192cu_fops},
6219{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
6220 .driver_info = (unsigned long)&rtl8192cu_fops},
6221{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
6222 .driver_info = (unsigned long)&rtl8192cu_fops},
6223{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
6224 .driver_info = (unsigned long)&rtl8192cu_fops},
6225{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
6226 .driver_info = (unsigned long)&rtl8192cu_fops},
26f1fad2
JS		 6227{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
6228 .driver_info = (unsigned long)&rtl8192cu_fops},
6229{USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
6230 .driver_info = (unsigned long)&rtl8192cu_fops},
6231{USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
6232 .driver_info = (unsigned long)&rtl8192cu_fops},
26f1fad2
JS		 6233{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
6234 .driver_info = (unsigned long)&rtl8192cu_fops},
6235{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
6236 .driver_info = (unsigned long)&rtl8192cu_fops},
6237{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
6238 .driver_info = (unsigned long)&rtl8192cu_fops},
6239{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
6240 .driver_info = (unsigned long)&rtl8192cu_fops},
6241{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
6242 .driver_info = (unsigned long)&rtl8192cu_fops},
6243{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
6244 .driver_info = (unsigned long)&rtl8192cu_fops},
6245{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
6246 .driver_info = (unsigned long)&rtl8192cu_fops},
6247/* Currently untested 8192 series devices */
6248{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
6249 .driver_info = (unsigned long)&rtl8192cu_fops},
26f1fad2
JS		 6250{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
6251 .driver_info = (unsigned long)&rtl8192cu_fops},
6252{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
6253 .driver_info = (unsigned long)&rtl8192cu_fops},
6254{USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
6255 .driver_info = (unsigned long)&rtl8192cu_fops},
6256{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
6257 .driver_info = (unsigned long)&rtl8192cu_fops},
6258{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
6259 .driver_info = (unsigned long)&rtl8192cu_fops},
6260{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
6261 .driver_info = (unsigned long)&rtl8192cu_fops},
6262{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
6263 .driver_info = (unsigned long)&rtl8192cu_fops},
6264{USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
6265 .driver_info = (unsigned long)&rtl8192cu_fops},
6266{USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
6267 .driver_info = (unsigned long)&rtl8192cu_fops},
6268{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
6269 .driver_info = (unsigned long)&rtl8192cu_fops},
6270{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
6271 .driver_info = (unsigned long)&rtl8192cu_fops},
6272{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
6273 .driver_info = (unsigned long)&rtl8192cu_fops},
6274{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
6275 .driver_info = (unsigned long)&rtl8192cu_fops},
6276{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
6277 .driver_info = (unsigned long)&rtl8192cu_fops},
6278{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
6279 .driver_info = (unsigned long)&rtl8192cu_fops},
6280{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
6281 .driver_info = (unsigned long)&rtl8192cu_fops},
6282{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
6283 .driver_info = (unsigned long)&rtl8192cu_fops},
6284{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
6285 .driver_info = (unsigned long)&rtl8192cu_fops},
6286{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
6287 .driver_info = (unsigned long)&rtl8192cu_fops},
6288{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
6289 .driver_info = (unsigned long)&rtl8192cu_fops},
6290{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
6291 .driver_info = (unsigned long)&rtl8192cu_fops},
6292{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
6293 .driver_info = (unsigned long)&rtl8192cu_fops},
6294{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
6295 .driver_info = (unsigned long)&rtl8192cu_fops},
6296#endif
6297{ }
6298};
6299
6300static struct usb_driver rtl8xxxu_driver = {
6301 .name = DRIVER_NAME,
6302 .probe = rtl8xxxu_probe,
6303 .disconnect = rtl8xxxu_disconnect,
6304 .id_table = dev_table,
6a62f9d5 6305 .no_dynamic_id = 1,
26f1fad2
JS		 6306 .disable_hub_initiated_lpm = 1,
6307};
6308
6309static int __init rtl8xxxu_module_init(void)
6310{
6311 int res;
6312
6313 res = usb_register(&rtl8xxxu_driver);
6314 if (res < 0)
6315 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
6316
6317 return res;
6318}
6319
6320static void __exit rtl8xxxu_module_exit(void)
6321{
6322 usb_deregister(&rtl8xxxu_driver);
6323}
6324
6325
6326MODULE_DEVICE_TABLE(usb, dev_table);
6327
6328module_init(rtl8xxxu_module_init);
6329module_exit(rtl8xxxu_module_exit);
Linux kernel - Deliverables
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