[deliverable/linux.git] / drivers / pci / host / pci-dra7xx.c

/*
 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
 *
 * Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
 *
 * Authors: Kishon Vijay Abraham I <kishon@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/of_gpio.h>
#include <linux/pci.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/resource.h>
#include <linux/types.h>

#include "pcie-designware.h"

/* PCIe controller wrapper DRA7XX configuration registers */

#define	PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN		0x0024
#define	PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN		0x0028
#define	ERR_SYS						BIT(0)
#define	ERR_FATAL					BIT(1)
#define	ERR_NONFATAL					BIT(2)
#define	ERR_COR						BIT(3)
#define	ERR_AXI						BIT(4)
#define	ERR_ECRC					BIT(5)
#define	PME_TURN_OFF					BIT(8)
#define	PME_TO_ACK					BIT(9)
#define	PM_PME						BIT(10)
#define	LINK_REQ_RST					BIT(11)
#define	LINK_UP_EVT					BIT(12)
#define	CFG_BME_EVT					BIT(13)
#define	CFG_MSE_EVT					BIT(14)
#define	INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \
			ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \
			LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT)

#define	PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI		0x0034
#define	PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI		0x0038
#define	INTA						BIT(0)
#define	INTB						BIT(1)
#define	INTC						BIT(2)
#define	INTD						BIT(3)
#define	MSI						BIT(4)
#define	LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)

#define	PCIECTRL_DRA7XX_CONF_DEVICE_CMD			0x0104
#define	LTSSM_EN					0x1

#define	PCIECTRL_DRA7XX_CONF_PHY_CS			0x010C
#define	LINK_UP						BIT(16)
#define	DRA7XX_CPU_TO_BUS_ADDR				0x0FFFFFFF

struct dra7xx_pcie {
	void __iomem		*base;
	struct phy		**phy;
	int			phy_count;
	struct device		*dev;
	struct pcie_port	pp;
};

#define to_dra7xx_pcie(x)	container_of((x), struct dra7xx_pcie, pp)

static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
{
	return readl(pcie->base + offset);
}

static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
				      u32 value)
{
	writel(value, pcie->base + offset);
}

static inline u32 dra7xx_pcie_readl_rc(struct pcie_port *pp, u32 offset)
{
	return readl(pp->dbi_base + offset);
}

static inline void dra7xx_pcie_writel_rc(struct pcie_port *pp, u32 offset,
					 u32 value)
{
	writel(value, pp->dbi_base + offset);
}

static int dra7xx_pcie_link_up(struct pcie_port *pp)
{
	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
	u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);

	return !!(reg & LINK_UP);
}

static int dra7xx_pcie_establish_link(struct pcie_port *pp)
{
	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
	u32 reg;

	if (dw_pcie_link_up(pp)) {
		dev_err(pp->dev, "link is already up\n");
		return 0;
	}

	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
	reg |= LTSSM_EN;
	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);

	return dw_pcie_wait_for_link(pp);
}

static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp)
{
	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);

	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
			   ~INTERRUPTS);
	dra7xx_pcie_writel(dra7xx,
			   PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN, INTERRUPTS);
	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
			   ~LEG_EP_INTERRUPTS & ~MSI);

	if (IS_ENABLED(CONFIG_PCI_MSI))
		dra7xx_pcie_writel(dra7xx,
				   PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI, MSI);
	else
		dra7xx_pcie_writel(dra7xx,
				   PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
				   LEG_EP_INTERRUPTS);
}

static void dra7xx_pcie_host_init(struct pcie_port *pp)
{
	pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR;
	pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR;
	pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR;
	pp->cfg1_base &= DRA7XX_CPU_TO_BUS_ADDR;

	dw_pcie_setup_rc(pp);

	dra7xx_pcie_establish_link(pp);
	if (IS_ENABLED(CONFIG_PCI_MSI))
		dw_pcie_msi_init(pp);
	dra7xx_pcie_enable_interrupts(pp);
}

static struct pcie_host_ops dra7xx_pcie_host_ops = {
	.link_up = dra7xx_pcie_link_up,
	.host_init = dra7xx_pcie_host_init,
};

static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
				irq_hw_number_t hwirq)
{
	irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
	irq_set_chip_data(irq, domain->host_data);

	return 0;
}

static const struct irq_domain_ops intx_domain_ops = {
	.map = dra7xx_pcie_intx_map,
};

static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
{
	struct device *dev = pp->dev;
	struct device_node *node = dev->of_node;
	struct device_node *pcie_intc_node =  of_get_next_child(node, NULL);

	if (!pcie_intc_node) {
		dev_err(dev, "No PCIe Intc node found\n");
		return -ENODEV;
	}

	pp->irq_domain = irq_domain_add_linear(pcie_intc_node, 4,
					       &intx_domain_ops, pp);
	if (!pp->irq_domain) {
		dev_err(dev, "Failed to get a INTx IRQ domain\n");
		return -ENODEV;
	}

	return 0;
}

static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
{
	struct pcie_port *pp = arg;
	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
	u32 reg;

	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);

	switch (reg) {
	case MSI:
		dw_handle_msi_irq(pp);
		break;
	case INTA:
	case INTB:
	case INTC:
	case INTD:
		generic_handle_irq(irq_find_mapping(pp->irq_domain, ffs(reg)));
		break;
	}

	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);

	return IRQ_HANDLED;
}


static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
{
	struct dra7xx_pcie *dra7xx = arg;
	u32 reg;

	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);

	if (reg & ERR_SYS)
		dev_dbg(dra7xx->dev, "System Error\n");

	if (reg & ERR_FATAL)
		dev_dbg(dra7xx->dev, "Fatal Error\n");

	if (reg & ERR_NONFATAL)
		dev_dbg(dra7xx->dev, "Non Fatal Error\n");

	if (reg & ERR_COR)
		dev_dbg(dra7xx->dev, "Correctable Error\n");

	if (reg & ERR_AXI)
		dev_dbg(dra7xx->dev, "AXI tag lookup fatal Error\n");

	if (reg & ERR_ECRC)
		dev_dbg(dra7xx->dev, "ECRC Error\n");

	if (reg & PME_TURN_OFF)
		dev_dbg(dra7xx->dev,
			"Power Management Event Turn-Off message received\n");

	if (reg & PME_TO_ACK)
		dev_dbg(dra7xx->dev,
			"Power Management Turn-Off Ack message received\n");

	if (reg & PM_PME)
		dev_dbg(dra7xx->dev,
			"PM Power Management Event message received\n");

	if (reg & LINK_REQ_RST)
		dev_dbg(dra7xx->dev, "Link Request Reset\n");

	if (reg & LINK_UP_EVT)
		dev_dbg(dra7xx->dev, "Link-up state change\n");

	if (reg & CFG_BME_EVT)
		dev_dbg(dra7xx->dev, "CFG 'Bus Master Enable' change\n");

	if (reg & CFG_MSE_EVT)
		dev_dbg(dra7xx->dev, "CFG 'Memory Space Enable' change\n");

	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);

	return IRQ_HANDLED;
}

static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
				       struct platform_device *pdev)
{
	int ret;
	struct pcie_port *pp;
	struct resource *res;
	struct device *dev = &pdev->dev;

	pp = &dra7xx->pp;
	pp->dev = dev;
	pp->ops = &dra7xx_pcie_host_ops;

	pp->irq = platform_get_irq(pdev, 1);
	if (pp->irq < 0) {
		dev_err(dev, "missing IRQ resource\n");
		return -EINVAL;
	}

	ret = devm_request_irq(&pdev->dev, pp->irq,
			       dra7xx_pcie_msi_irq_handler,
			       IRQF_SHARED | IRQF_NO_THREAD,
			       "dra7-pcie-msi",	pp);
	if (ret) {
		dev_err(&pdev->dev, "failed to request irq\n");
		return ret;
	}

	if (!IS_ENABLED(CONFIG_PCI_MSI)) {
		ret = dra7xx_pcie_init_irq_domain(pp);
		if (ret < 0)
			return ret;
	}

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics");
	pp->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
	if (!pp->dbi_base)
		return -ENOMEM;

	ret = dw_pcie_host_init(pp);
	if (ret) {
		dev_err(dra7xx->dev, "failed to initialize host\n");
		return ret;
	}

	return 0;
}

static int __init dra7xx_pcie_probe(struct platform_device *pdev)
{
	u32 reg;
	int ret;
	int irq;
	int i;
	int phy_count;
	struct phy **phy;
	void __iomem *base;
	struct resource *res;
	struct dra7xx_pcie *dra7xx;
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	char name[10];
	int gpio_sel;
	enum of_gpio_flags flags;
	unsigned long gpio_flags;

	dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
	if (!dra7xx)
		return -ENOMEM;

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(dev, "missing IRQ resource\n");
		return -EINVAL;
	}

	ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
			       IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
	if (ret) {
		dev_err(dev, "failed to request irq\n");
		return ret;
	}

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
	base = devm_ioremap_nocache(dev, res->start, resource_size(res));
	if (!base)
		return -ENOMEM;

	phy_count = of_property_count_strings(np, "phy-names");
	if (phy_count < 0) {
		dev_err(dev, "unable to find the strings\n");
		return phy_count;
	}

	phy = devm_kzalloc(dev, sizeof(*phy) * phy_count, GFP_KERNEL);
	if (!phy)
		return -ENOMEM;

	for (i = 0; i < phy_count; i++) {
		snprintf(name, sizeof(name), "pcie-phy%d", i);
		phy[i] = devm_phy_get(dev, name);
		if (IS_ERR(phy[i]))
			return PTR_ERR(phy[i]);

		ret = phy_init(phy[i]);
		if (ret < 0)
			goto err_phy;

		ret = phy_power_on(phy[i]);
		if (ret < 0) {
			phy_exit(phy[i]);
			goto err_phy;
		}
	}

	dra7xx->base = base;
	dra7xx->phy = phy;
	dra7xx->dev = dev;
	dra7xx->phy_count = phy_count;

	pm_runtime_enable(dev);
	ret = pm_runtime_get_sync(dev);
	if (ret < 0) {
		dev_err(dev, "pm_runtime_get_sync failed\n");
		goto err_get_sync;
	}

	gpio_sel = of_get_gpio_flags(dev->of_node, 0, &flags);
	if (gpio_is_valid(gpio_sel)) {
		gpio_flags = (flags & OF_GPIO_ACTIVE_LOW) ?
				GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH;
		ret = devm_gpio_request_one(dev, gpio_sel, gpio_flags,
					    "pcie_reset");
		if (ret) {
			dev_err(&pdev->dev, "gpio%d request failed, ret %d\n",
				gpio_sel, ret);
			goto err_gpio;
		}
	} else if (gpio_sel == -EPROBE_DEFER) {
		ret = -EPROBE_DEFER;
		goto err_gpio;
	}

	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
	reg &= ~LTSSM_EN;
	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);

	platform_set_drvdata(pdev, dra7xx);

	ret = dra7xx_add_pcie_port(dra7xx, pdev);
	if (ret < 0)
		goto err_gpio;

	return 0;

err_gpio:
	pm_runtime_put(dev);

err_get_sync:
	pm_runtime_disable(dev);

err_phy:
	while (--i >= 0) {
		phy_power_off(phy[i]);
		phy_exit(phy[i]);
	}

	return ret;
}

#ifdef CONFIG_PM_SLEEP
static int dra7xx_pcie_suspend(struct device *dev)
{
	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
	struct pcie_port *pp = &dra7xx->pp;
	u32 val;

	/* clear MSE */
	val = dra7xx_pcie_readl_rc(pp, PCI_COMMAND);
	val &= ~PCI_COMMAND_MEMORY;
	dra7xx_pcie_writel_rc(pp, PCI_COMMAND, val);

	return 0;
}

static int dra7xx_pcie_resume(struct device *dev)
{
	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
	struct pcie_port *pp = &dra7xx->pp;
	u32 val;

	/* set MSE */
	val = dra7xx_pcie_readl_rc(pp, PCI_COMMAND);
	val |= PCI_COMMAND_MEMORY;
	dra7xx_pcie_writel_rc(pp, PCI_COMMAND, val);

	return 0;
}

static int dra7xx_pcie_suspend_noirq(struct device *dev)
{
	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
	int count = dra7xx->phy_count;

	while (count--) {
		phy_power_off(dra7xx->phy[count]);
		phy_exit(dra7xx->phy[count]);
	}

	return 0;
}

static int dra7xx_pcie_resume_noirq(struct device *dev)
{
	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
	int phy_count = dra7xx->phy_count;
	int ret;
	int i;

	for (i = 0; i < phy_count; i++) {
		ret = phy_init(dra7xx->phy[i]);
		if (ret < 0)
			goto err_phy;

		ret = phy_power_on(dra7xx->phy[i]);
		if (ret < 0) {
			phy_exit(dra7xx->phy[i]);
			goto err_phy;
		}
	}

	return 0;

err_phy:
	while (--i >= 0) {
		phy_power_off(dra7xx->phy[i]);
		phy_exit(dra7xx->phy[i]);
	}

	return ret;
}
#endif

static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume)
	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
				      dra7xx_pcie_resume_noirq)
};

static const struct of_device_id of_dra7xx_pcie_match[] = {
	{ .compatible = "ti,dra7-pcie", },
	{},
};

static struct platform_driver dra7xx_pcie_driver = {
	.driver = {
		.name	= "dra7-pcie",
		.of_match_table = of_dra7xx_pcie_match,
		.suppress_bind_attrs = true,
		.pm	= &dra7xx_pcie_pm_ops,
	},
};
builtin_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe);
Commit	Line	Data
47ff3de9 KVA	1	/*
	2	* pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
	3	*
	4	* Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
	5	*
	6	* Authors: Kishon Vijay Abraham I <kishon@ti.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
47ff3de9 KVA	13	#include <linux/err.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/irq.h>
	16	#include <linux/irqdomain.h>
	17	#include <linux/kernel.h>
d29438d6	18	#include <linux/init.h>
78bdcad0	19	#include <linux/of_gpio.h>
47ff3de9 KVA	20	#include <linux/pci.h>
	21	#include <linux/phy/phy.h>
	22	#include <linux/platform_device.h>
	23	#include <linux/pm_runtime.h>
	24	#include <linux/resource.h>
	25	#include <linux/types.h>
	26
	27	#include "pcie-designware.h"
	28
	29	/* PCIe controller wrapper DRA7XX configuration registers */
	30
	31	#define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN 0x0024
	32	#define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN 0x0028
	33	#define ERR_SYS BIT(0)
	34	#define ERR_FATAL BIT(1)
	35	#define ERR_NONFATAL BIT(2)
	36	#define ERR_COR BIT(3)
	37	#define ERR_AXI BIT(4)
	38	#define ERR_ECRC BIT(5)
	39	#define PME_TURN_OFF BIT(8)
	40	#define PME_TO_ACK BIT(9)
	41	#define PM_PME BIT(10)
	42	#define LINK_REQ_RST BIT(11)
	43	#define LINK_UP_EVT BIT(12)
	44	#define CFG_BME_EVT BIT(13)
	45	#define CFG_MSE_EVT BIT(14)
	46	#define INTERRUPTS (ERR_SYS \| ERR_FATAL \| ERR_NONFATAL \| ERR_COR \| ERR_AXI \| \
	47	ERR_ECRC \| PME_TURN_OFF \| PME_TO_ACK \| PM_PME \| \
	48	LINK_REQ_RST \| LINK_UP_EVT \| CFG_BME_EVT \| CFG_MSE_EVT)
	49
	50	#define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI 0x0034
	51	#define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI 0x0038
	52	#define INTA BIT(0)
	53	#define INTB BIT(1)
	54	#define INTC BIT(2)
	55	#define INTD BIT(3)
	56	#define MSI BIT(4)
	57	#define LEG_EP_INTERRUPTS (INTA \| INTB \| INTC \| INTD)
	58
	59	#define PCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104
	60	#define LTSSM_EN 0x1
	61
	62	#define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C
	63	#define LINK_UP BIT(16)
883cc17c	64	#define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF
47ff3de9 KVA	65
	66	struct dra7xx_pcie {
	67	void __iomem *base;
	68	struct phy **phy;
	69	int phy_count;
	70	struct device *dev;
	71	struct pcie_port pp;
	72	};
	73
	74	#define to_dra7xx_pcie(x) container_of((x), struct dra7xx_pcie, pp)
	75
	76	static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
	77	{
	78	return readl(pcie->base + offset);
	79	}
	80
	81	static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
	82	u32 value)
	83	{
	84	writel(value, pcie->base + offset);
	85	}
	86
389c7094 KVA	87	static inline u32 dra7xx_pcie_readl_rc(struct pcie_port *pp, u32 offset)
	88	{
	89	return readl(pp->dbi_base + offset);
	90	}
	91
	92	static inline void dra7xx_pcie_writel_rc(struct pcie_port *pp, u32 offset,
	93	u32 value)
	94	{
	95	writel(value, pp->dbi_base + offset);
	96	}
	97
47ff3de9 KVA	98	static int dra7xx_pcie_link_up(struct pcie_port *pp)
	99	{
	100	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
	101	u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
	102
	103	return !!(reg & LINK_UP);
	104	}
	105
	106	static int dra7xx_pcie_establish_link(struct pcie_port *pp)
	107	{
47ff3de9	108	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
6cbb247e	109	u32 reg;
47ff3de9 KVA	110
	111	if (dw_pcie_link_up(pp)) {
	112	dev_err(pp->dev, "link is already up\n");
	113	return 0;
	114	}
	115
	116	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
	117	reg \|= LTSSM_EN;
	118	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
	119
886bc5ce	120	return dw_pcie_wait_for_link(pp);
47ff3de9 KVA	121	}
	122
	123	static void dra7xx_pcie_enable_interrupts(struct pcie_port *pp)
	124	{
	125	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
	126
	127	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
	128	~INTERRUPTS);
	129	dra7xx_pcie_writel(dra7xx,
	130	PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN, INTERRUPTS);
	131	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
	132	~LEG_EP_INTERRUPTS & ~MSI);
	133
	134	if (IS_ENABLED(CONFIG_PCI_MSI))
	135	dra7xx_pcie_writel(dra7xx,
	136	PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI, MSI);
	137	else
	138	dra7xx_pcie_writel(dra7xx,
	139	PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
	140	LEG_EP_INTERRUPTS);
	141	}
	142
	143	static void dra7xx_pcie_host_init(struct pcie_port *pp)
	144	{
9cdce1cd ZW	145	pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR;
	146	pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR;
	147	pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR;
	148	pp->cfg1_base &= DRA7XX_CPU_TO_BUS_ADDR;
883cc17c	149
7e57fd14 JZ	150	dw_pcie_setup_rc(pp);
7e57fd14 JZ	151
47ff3de9 KVA	152	dra7xx_pcie_establish_link(pp);
	153	if (IS_ENABLED(CONFIG_PCI_MSI))
	154	dw_pcie_msi_init(pp);
	155	dra7xx_pcie_enable_interrupts(pp);
	156	}
	157
	158	static struct pcie_host_ops dra7xx_pcie_host_ops = {
	159	.link_up = dra7xx_pcie_link_up,
	160	.host_init = dra7xx_pcie_host_init,
	161	};
	162
	163	static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
	164	irq_hw_number_t hwirq)
	165	{
	166	irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
	167	irq_set_chip_data(irq, domain->host_data);
47ff3de9 KVA	168
	169	return 0;
	170	}
	171
	172	static const struct irq_domain_ops intx_domain_ops = {
	173	.map = dra7xx_pcie_intx_map,
	174	};
	175
	176	static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
	177	{
	178	struct device *dev = pp->dev;
	179	struct device_node *node = dev->of_node;
	180	struct device_node *pcie_intc_node = of_get_next_child(node, NULL);
	181
	182	if (!pcie_intc_node) {
	183	dev_err(dev, "No PCIe Intc node found\n");
991bfef8	184	return -ENODEV;
47ff3de9 KVA	185	}
	186
	187	pp->irq_domain = irq_domain_add_linear(pcie_intc_node, 4,
	188	&intx_domain_ops, pp);
	189	if (!pp->irq_domain) {
	190	dev_err(dev, "Failed to get a INTx IRQ domain\n");
991bfef8	191	return -ENODEV;
47ff3de9 KVA	192	}
	193
	194	return 0;
	195	}
	196
	197	static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
	198	{
	199	struct pcie_port *pp = arg;
	200	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
	201	u32 reg;
	202
	203	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
	204
	205	switch (reg) {
	206	case MSI:
	207	dw_handle_msi_irq(pp);
	208	break;
	209	case INTA:
	210	case INTB:
	211	case INTC:
	212	case INTD:
	213	generic_handle_irq(irq_find_mapping(pp->irq_domain, ffs(reg)));
	214	break;
	215	}
	216
	217	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
	218
	219	return IRQ_HANDLED;
	220	}
	221
	222
	223	static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
	224	{
	225	struct dra7xx_pcie *dra7xx = arg;
	226	u32 reg;
	227
	228	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
	229
	230	if (reg & ERR_SYS)
	231	dev_dbg(dra7xx->dev, "System Error\n");
	232
	233	if (reg & ERR_FATAL)
	234	dev_dbg(dra7xx->dev, "Fatal Error\n");
	235
	236	if (reg & ERR_NONFATAL)
	237	dev_dbg(dra7xx->dev, "Non Fatal Error\n");
	238
	239	if (reg & ERR_COR)
	240	dev_dbg(dra7xx->dev, "Correctable Error\n");
	241
	242	if (reg & ERR_AXI)
	243	dev_dbg(dra7xx->dev, "AXI tag lookup fatal Error\n");
	244
	245	if (reg & ERR_ECRC)
	246	dev_dbg(dra7xx->dev, "ECRC Error\n");
	247
	248	if (reg & PME_TURN_OFF)
	249	dev_dbg(dra7xx->dev,
	250	"Power Management Event Turn-Off message received\n");
	251
	252	if (reg & PME_TO_ACK)
	253	dev_dbg(dra7xx->dev,
	254	"Power Management Turn-Off Ack message received\n");
	255
256	if (reg & PM_PME)
257	dev_dbg(dra7xx->dev,
258	"PM Power Management Event message received\n");
259
260	if (reg & LINK_REQ_RST)
261	dev_dbg(dra7xx->dev, "Link Request Reset\n");
262
263	if (reg & LINK_UP_EVT)
264	dev_dbg(dra7xx->dev, "Link-up state change\n");
265
266	if (reg & CFG_BME_EVT)
267	dev_dbg(dra7xx->dev, "CFG 'Bus Master Enable' change\n");
268
269	if (reg & CFG_MSE_EVT)
270	dev_dbg(dra7xx->dev, "CFG 'Memory Space Enable' change\n");
271
272	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);
273
274	return IRQ_HANDLED;
275	}
276
e73044a0 JH	277	static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
e73044a0 JH	278	struct platform_device *pdev)
47ff3de9 KVA	279	{
	280	int ret;
	281	struct pcie_port *pp;
	282	struct resource *res;
	283	struct device *dev = &pdev->dev;
	284
	285	pp = &dra7xx->pp;
	286	pp->dev = dev;
	287	pp->ops = &dra7xx_pcie_host_ops;
	288
	289	pp->irq = platform_get_irq(pdev, 1);
	290	if (pp->irq < 0) {
	291	dev_err(dev, "missing IRQ resource\n");
	292	return -EINVAL;
	293	}
	294
	295	ret = devm_request_irq(&pdev->dev, pp->irq,
8ff0ef99 GS	296	dra7xx_pcie_msi_irq_handler,
8ff0ef99 GS	297	IRQF_SHARED \| IRQF_NO_THREAD,
47ff3de9 KVA	298	"dra7-pcie-msi", pp);
	299	if (ret) {
	300	dev_err(&pdev->dev, "failed to request irq\n");
	301	return ret;
	302	}
	303
	304	if (!IS_ENABLED(CONFIG_PCI_MSI)) {
	305	ret = dra7xx_pcie_init_irq_domain(pp);
	306	if (ret < 0)
	307	return ret;
	308	}
	309
	310	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics");
	311	pp->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
	312	if (!pp->dbi_base)
	313	return -ENOMEM;
	314
	315	ret = dw_pcie_host_init(pp);
	316	if (ret) {
	317	dev_err(dra7xx->dev, "failed to initialize host\n");
	318	return ret;
	319	}
	320
	321	return 0;
	322	}
	323
	324	static int __init dra7xx_pcie_probe(struct platform_device *pdev)
	325	{
	326	u32 reg;
	327	int ret;
	328	int irq;
	329	int i;
	330	int phy_count;
	331	struct phy **phy;
	332	void __iomem *base;
	333	struct resource *res;
	334	struct dra7xx_pcie *dra7xx;
	335	struct device *dev = &pdev->dev;
	336	struct device_node *np = dev->of_node;
	337	char name[10];
78bdcad0 KVA	338	int gpio_sel;
	339	enum of_gpio_flags flags;
	340	unsigned long gpio_flags;
47ff3de9 KVA	341
	342	dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
	343	if (!dra7xx)
	344	return -ENOMEM;
	345
	346	irq = platform_get_irq(pdev, 0);
	347	if (irq < 0) {
	348	dev_err(dev, "missing IRQ resource\n");
	349	return -EINVAL;
	350	}
	351
	352	ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
	353	IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
	354	if (ret) {
	355	dev_err(dev, "failed to request irq\n");
	356	return ret;
	357	}
	358
	359	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
	360	base = devm_ioremap_nocache(dev, res->start, resource_size(res));
	361	if (!base)
	362	return -ENOMEM;
	363
	364	phy_count = of_property_count_strings(np, "phy-names");
	365	if (phy_count < 0) {
	366	dev_err(dev, "unable to find the strings\n");
	367	return phy_count;
	368	}
	369
	370	phy = devm_kzalloc(dev, sizeof(phy) phy_count, GFP_KERNEL);
	371	if (!phy)
	372	return -ENOMEM;
	373
	374	for (i = 0; i < phy_count; i++) {
	375	snprintf(name, sizeof(name), "pcie-phy%d", i);
	376	phy[i] = devm_phy_get(dev, name);
	377	if (IS_ERR(phy[i]))
	378	return PTR_ERR(phy[i]);
	379
	380	ret = phy_init(phy[i]);
	381	if (ret < 0)
	382	goto err_phy;
	383
	384	ret = phy_power_on(phy[i]);
	385	if (ret < 0) {
	386	phy_exit(phy[i]);
	387	goto err_phy;
	388	}
	389	}
	390
	391	dra7xx->base = base;
	392	dra7xx->phy = phy;
	393	dra7xx->dev = dev;
	394	dra7xx->phy_count = phy_count;
	395
	396	pm_runtime_enable(dev);
	397	ret = pm_runtime_get_sync(dev);
d3f4caa3	398	if (ret < 0) {
47ff3de9	399	dev_err(dev, "pm_runtime_get_sync failed\n");
0e2bdb0e	400	goto err_get_sync;
47ff3de9 KVA	401	}
47ff3de9 KVA	402
78bdcad0 KVA	403	gpio_sel = of_get_gpio_flags(dev->of_node, 0, &flags);
	404	if (gpio_is_valid(gpio_sel)) {
	405	gpio_flags = (flags & OF_GPIO_ACTIVE_LOW) ?
	406	GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH;
	407	ret = devm_gpio_request_one(dev, gpio_sel, gpio_flags,
	408	"pcie_reset");
	409	if (ret) {
	410	dev_err(&pdev->dev, "gpio%d request failed, ret %d\n",
	411	gpio_sel, ret);
	412	goto err_gpio;
	413	}
	414	} else if (gpio_sel == -EPROBE_DEFER) {
	415	ret = -EPROBE_DEFER;
	416	goto err_gpio;
47ff3de9 KVA	417	}
	418
	419	reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
	420	reg &= ~LTSSM_EN;
	421	dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
	422
	423	platform_set_drvdata(pdev, dra7xx);
	424
23926c8d	425	ret = dra7xx_add_pcie_port(dra7xx, pdev);
47ff3de9	426	if (ret < 0)
78bdcad0	427	goto err_gpio;
47ff3de9 KVA	428
	429	return 0;
	430
78bdcad0	431	err_gpio:
47ff3de9	432	pm_runtime_put(dev);
0e2bdb0e KVA	433
0e2bdb0e KVA	434	err_get_sync:
47ff3de9 KVA	435	pm_runtime_disable(dev);
	436
	437	err_phy:
	438	while (--i >= 0) {
	439	phy_power_off(phy[i]);
	440	phy_exit(phy[i]);
	441	}
	442
	443	return ret;
	444	}
	445
e52eb445	446	#ifdef CONFIG_PM_SLEEP
389c7094 KVA	447	static int dra7xx_pcie_suspend(struct device *dev)
	448	{
	449	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
	450	struct pcie_port *pp = &dra7xx->pp;
	451	u32 val;
	452
	453	/* clear MSE */
	454	val = dra7xx_pcie_readl_rc(pp, PCI_COMMAND);
	455	val &= ~PCI_COMMAND_MEMORY;
	456	dra7xx_pcie_writel_rc(pp, PCI_COMMAND, val);
	457
	458	return 0;
	459	}
	460
	461	static int dra7xx_pcie_resume(struct device *dev)
	462	{
	463	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
	464	struct pcie_port *pp = &dra7xx->pp;
	465	u32 val;
	466
	467	/* set MSE */
	468	val = dra7xx_pcie_readl_rc(pp, PCI_COMMAND);
	469	val \|= PCI_COMMAND_MEMORY;
	470	dra7xx_pcie_writel_rc(pp, PCI_COMMAND, val);
	471
	472	return 0;
	473	}
	474
e52eb445 KVA	475	static int dra7xx_pcie_suspend_noirq(struct device *dev)
	476	{
	477	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
	478	int count = dra7xx->phy_count;
	479
	480	while (count--) {
	481	phy_power_off(dra7xx->phy[count]);
	482	phy_exit(dra7xx->phy[count]);
	483	}
	484
	485	return 0;
	486	}
	487
	488	static int dra7xx_pcie_resume_noirq(struct device *dev)
	489	{
	490	struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
	491	int phy_count = dra7xx->phy_count;
	492	int ret;
	493	int i;
	494
	495	for (i = 0; i < phy_count; i++) {
	496	ret = phy_init(dra7xx->phy[i]);
	497	if (ret < 0)
	498	goto err_phy;
	499
	500	ret = phy_power_on(dra7xx->phy[i]);
	501	if (ret < 0) {
	502	phy_exit(dra7xx->phy[i]);
	503	goto err_phy;
	504	}
	505	}
	506
	507	return 0;
	508
	509	err_phy:
	510	while (--i >= 0) {
	511	phy_power_off(dra7xx->phy[i]);
	512	phy_exit(dra7xx->phy[i]);
	513	}
	514
	515	return ret;
	516	}
	517	#endif
	518
	519	static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
389c7094	520	SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume)
e52eb445 KVA	521	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
	522	dra7xx_pcie_resume_noirq)
	523	};
	524
47ff3de9 KVA	525	static const struct of_device_id of_dra7xx_pcie_match[] = {
	526	{ .compatible = "ti,dra7-pcie", },
	527	{},
	528	};
47ff3de9 KVA	529
47ff3de9 KVA	530	static struct platform_driver dra7xx_pcie_driver = {
47ff3de9 KVA	531	.driver = {
47ff3de9 KVA	532	.name = "dra7-pcie",
47ff3de9	533	.of_match_table = of_dra7xx_pcie_match,
d29438d6	534	.suppress_bind_attrs = true,
e52eb445	535	.pm = &dra7xx_pcie_pm_ops,
47ff3de9 KVA	536	},
47ff3de9 KVA	537	};
d29438d6	538	builtin_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe);