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4b1ced84 JH |
1 | /* |
2 | * PCIe host controller driver for Samsung EXYNOS SoCs | |
3 | * | |
4 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * Author: Jingoo Han <jg1.han@samsung.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/gpio.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/kernel.h> | |
caf5548c | 19 | #include <linux/init.h> |
4b1ced84 JH |
20 | #include <linux/of_gpio.h> |
21 | #include <linux/pci.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/resource.h> | |
24 | #include <linux/signal.h> | |
25 | #include <linux/types.h> | |
26 | ||
27 | #include "pcie-designware.h" | |
28 | ||
29 | #define to_exynos_pcie(x) container_of(x, struct exynos_pcie, pp) | |
30 | ||
31 | struct exynos_pcie { | |
32 | void __iomem *elbi_base; | |
33 | void __iomem *phy_base; | |
34 | void __iomem *block_base; | |
35 | int reset_gpio; | |
36 | struct clk *clk; | |
37 | struct clk *bus_clk; | |
38 | struct pcie_port pp; | |
39 | }; | |
40 | ||
41 | /* PCIe ELBI registers */ | |
42 | #define PCIE_IRQ_PULSE 0x000 | |
43 | #define IRQ_INTA_ASSERT (0x1 << 0) | |
44 | #define IRQ_INTB_ASSERT (0x1 << 2) | |
45 | #define IRQ_INTC_ASSERT (0x1 << 4) | |
46 | #define IRQ_INTD_ASSERT (0x1 << 6) | |
47 | #define PCIE_IRQ_LEVEL 0x004 | |
48 | #define PCIE_IRQ_SPECIAL 0x008 | |
49 | #define PCIE_IRQ_EN_PULSE 0x00c | |
50 | #define PCIE_IRQ_EN_LEVEL 0x010 | |
f342d940 | 51 | #define IRQ_MSI_ENABLE (0x1 << 2) |
4b1ced84 JH |
52 | #define PCIE_IRQ_EN_SPECIAL 0x014 |
53 | #define PCIE_PWR_RESET 0x018 | |
54 | #define PCIE_CORE_RESET 0x01c | |
55 | #define PCIE_CORE_RESET_ENABLE (0x1 << 0) | |
56 | #define PCIE_STICKY_RESET 0x020 | |
57 | #define PCIE_NONSTICKY_RESET 0x024 | |
58 | #define PCIE_APP_INIT_RESET 0x028 | |
59 | #define PCIE_APP_LTSSM_ENABLE 0x02c | |
60 | #define PCIE_ELBI_RDLH_LINKUP 0x064 | |
61 | #define PCIE_ELBI_LTSSM_ENABLE 0x1 | |
62 | #define PCIE_ELBI_SLV_AWMISC 0x11c | |
63 | #define PCIE_ELBI_SLV_ARMISC 0x120 | |
64 | #define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21) | |
65 | ||
66 | /* PCIe Purple registers */ | |
67 | #define PCIE_PHY_GLOBAL_RESET 0x000 | |
68 | #define PCIE_PHY_COMMON_RESET 0x004 | |
69 | #define PCIE_PHY_CMN_REG 0x008 | |
70 | #define PCIE_PHY_MAC_RESET 0x00c | |
71 | #define PCIE_PHY_PLL_LOCKED 0x010 | |
72 | #define PCIE_PHY_TRSVREG_RESET 0x020 | |
73 | #define PCIE_PHY_TRSV_RESET 0x024 | |
74 | ||
75 | /* PCIe PHY registers */ | |
76 | #define PCIE_PHY_IMPEDANCE 0x004 | |
77 | #define PCIE_PHY_PLL_DIV_0 0x008 | |
78 | #define PCIE_PHY_PLL_BIAS 0x00c | |
79 | #define PCIE_PHY_DCC_FEEDBACK 0x014 | |
80 | #define PCIE_PHY_PLL_DIV_1 0x05c | |
f62b878b JH |
81 | #define PCIE_PHY_COMMON_POWER 0x064 |
82 | #define PCIE_PHY_COMMON_PD_CMN (0x1 << 3) | |
4b1ced84 JH |
83 | #define PCIE_PHY_TRSV0_EMP_LVL 0x084 |
84 | #define PCIE_PHY_TRSV0_DRV_LVL 0x088 | |
85 | #define PCIE_PHY_TRSV0_RXCDR 0x0ac | |
f62b878b JH |
86 | #define PCIE_PHY_TRSV0_POWER 0x0c4 |
87 | #define PCIE_PHY_TRSV0_PD_TSV (0x1 << 7) | |
4b1ced84 JH |
88 | #define PCIE_PHY_TRSV0_LVCC 0x0dc |
89 | #define PCIE_PHY_TRSV1_EMP_LVL 0x144 | |
90 | #define PCIE_PHY_TRSV1_RXCDR 0x16c | |
f62b878b JH |
91 | #define PCIE_PHY_TRSV1_POWER 0x184 |
92 | #define PCIE_PHY_TRSV1_PD_TSV (0x1 << 7) | |
4b1ced84 JH |
93 | #define PCIE_PHY_TRSV1_LVCC 0x19c |
94 | #define PCIE_PHY_TRSV2_EMP_LVL 0x204 | |
95 | #define PCIE_PHY_TRSV2_RXCDR 0x22c | |
f62b878b JH |
96 | #define PCIE_PHY_TRSV2_POWER 0x244 |
97 | #define PCIE_PHY_TRSV2_PD_TSV (0x1 << 7) | |
4b1ced84 JH |
98 | #define PCIE_PHY_TRSV2_LVCC 0x25c |
99 | #define PCIE_PHY_TRSV3_EMP_LVL 0x2c4 | |
100 | #define PCIE_PHY_TRSV3_RXCDR 0x2ec | |
f62b878b JH |
101 | #define PCIE_PHY_TRSV3_POWER 0x304 |
102 | #define PCIE_PHY_TRSV3_PD_TSV (0x1 << 7) | |
4b1ced84 JH |
103 | #define PCIE_PHY_TRSV3_LVCC 0x31c |
104 | ||
058dd016 SJ |
105 | static inline void exynos_elb_writel(struct exynos_pcie *pcie, u32 val, u32 reg) |
106 | { | |
107 | writel(val, pcie->elbi_base + reg); | |
108 | } | |
109 | ||
110 | static inline u32 exynos_elb_readl(struct exynos_pcie *pcie, u32 reg) | |
111 | { | |
112 | return readl(pcie->elbi_base + reg); | |
113 | } | |
114 | ||
115 | static inline void exynos_phy_writel(struct exynos_pcie *pcie, u32 val, u32 reg) | |
116 | { | |
117 | writel(val, pcie->phy_base + reg); | |
118 | } | |
119 | ||
120 | static inline u32 exynos_phy_readl(struct exynos_pcie *pcie, u32 reg) | |
121 | { | |
122 | return readl(pcie->phy_base + reg); | |
123 | } | |
124 | ||
125 | static inline void exynos_blk_writel(struct exynos_pcie *pcie, u32 val, u32 reg) | |
126 | { | |
127 | writel(val, pcie->block_base + reg); | |
128 | } | |
129 | ||
130 | static inline u32 exynos_blk_readl(struct exynos_pcie *pcie, u32 reg) | |
131 | { | |
132 | return readl(pcie->block_base + reg); | |
133 | } | |
134 | ||
4b1ced84 JH |
135 | static void exynos_pcie_sideband_dbi_w_mode(struct pcie_port *pp, bool on) |
136 | { | |
137 | u32 val; | |
138 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); | |
139 | ||
140 | if (on) { | |
058dd016 | 141 | val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC); |
4b1ced84 | 142 | val |= PCIE_ELBI_SLV_DBI_ENABLE; |
058dd016 | 143 | exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC); |
4b1ced84 | 144 | } else { |
058dd016 | 145 | val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC); |
4b1ced84 | 146 | val &= ~PCIE_ELBI_SLV_DBI_ENABLE; |
058dd016 | 147 | exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC); |
4b1ced84 JH |
148 | } |
149 | } | |
150 | ||
151 | static void exynos_pcie_sideband_dbi_r_mode(struct pcie_port *pp, bool on) | |
152 | { | |
153 | u32 val; | |
154 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); | |
155 | ||
156 | if (on) { | |
058dd016 | 157 | val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC); |
4b1ced84 | 158 | val |= PCIE_ELBI_SLV_DBI_ENABLE; |
058dd016 | 159 | exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC); |
4b1ced84 | 160 | } else { |
058dd016 | 161 | val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC); |
4b1ced84 | 162 | val &= ~PCIE_ELBI_SLV_DBI_ENABLE; |
058dd016 | 163 | exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC); |
4b1ced84 JH |
164 | } |
165 | } | |
166 | ||
167 | static void exynos_pcie_assert_core_reset(struct pcie_port *pp) | |
168 | { | |
169 | u32 val; | |
170 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); | |
4b1ced84 | 171 | |
058dd016 | 172 | val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET); |
4b1ced84 | 173 | val &= ~PCIE_CORE_RESET_ENABLE; |
058dd016 SJ |
174 | exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET); |
175 | exynos_elb_writel(exynos_pcie, 0, PCIE_PWR_RESET); | |
176 | exynos_elb_writel(exynos_pcie, 0, PCIE_STICKY_RESET); | |
177 | exynos_elb_writel(exynos_pcie, 0, PCIE_NONSTICKY_RESET); | |
4b1ced84 JH |
178 | } |
179 | ||
180 | static void exynos_pcie_deassert_core_reset(struct pcie_port *pp) | |
181 | { | |
182 | u32 val; | |
183 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); | |
4b1ced84 | 184 | |
058dd016 | 185 | val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET); |
4b1ced84 | 186 | val |= PCIE_CORE_RESET_ENABLE; |
058dd016 SJ |
187 | |
188 | exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET); | |
189 | exynos_elb_writel(exynos_pcie, 1, PCIE_STICKY_RESET); | |
190 | exynos_elb_writel(exynos_pcie, 1, PCIE_NONSTICKY_RESET); | |
191 | exynos_elb_writel(exynos_pcie, 1, PCIE_APP_INIT_RESET); | |
192 | exynos_elb_writel(exynos_pcie, 0, PCIE_APP_INIT_RESET); | |
193 | exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_MAC_RESET); | |
4b1ced84 JH |
194 | } |
195 | ||
196 | static void exynos_pcie_assert_phy_reset(struct pcie_port *pp) | |
197 | { | |
198 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); | |
4b1ced84 | 199 | |
058dd016 SJ |
200 | exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_MAC_RESET); |
201 | exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_GLOBAL_RESET); | |
4b1ced84 JH |
202 | } |
203 | ||
204 | static void exynos_pcie_deassert_phy_reset(struct pcie_port *pp) | |
205 | { | |
206 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); | |
058dd016 SJ |
207 | |
208 | exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_GLOBAL_RESET); | |
209 | exynos_elb_writel(exynos_pcie, 1, PCIE_PWR_RESET); | |
210 | exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET); | |
211 | exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_CMN_REG); | |
212 | exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSVREG_RESET); | |
213 | exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSV_RESET); | |
4b1ced84 JH |
214 | } |
215 | ||
f62b878b JH |
216 | static void exynos_pcie_power_on_phy(struct pcie_port *pp) |
217 | { | |
218 | u32 val; | |
219 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); | |
220 | ||
221 | val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER); | |
222 | val &= ~PCIE_PHY_COMMON_PD_CMN; | |
223 | exynos_phy_writel(exynos_pcie, val, PCIE_PHY_COMMON_POWER); | |
224 | ||
225 | val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV0_POWER); | |
226 | val &= ~PCIE_PHY_TRSV0_PD_TSV; | |
227 | exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV0_POWER); | |
228 | ||
229 | val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV1_POWER); | |
230 | val &= ~PCIE_PHY_TRSV1_PD_TSV; | |
231 | exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV1_POWER); | |
232 | ||
233 | val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV2_POWER); | |
234 | val &= ~PCIE_PHY_TRSV2_PD_TSV; | |
235 | exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV2_POWER); | |
236 | ||
237 | val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV3_POWER); | |
238 | val &= ~PCIE_PHY_TRSV3_PD_TSV; | |
239 | exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER); | |
240 | } | |
241 | ||
242 | static void exynos_pcie_power_off_phy(struct pcie_port *pp) | |
243 | { | |
244 | u32 val; | |
245 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); | |
246 | ||
247 | val = exynos_phy_readl(exynos_pcie, PCIE_PHY_COMMON_POWER); | |
248 | val |= PCIE_PHY_COMMON_PD_CMN; | |
249 | exynos_phy_writel(exynos_pcie, val, PCIE_PHY_COMMON_POWER); | |
250 | ||
251 | val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV0_POWER); | |
252 | val |= PCIE_PHY_TRSV0_PD_TSV; | |
253 | exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV0_POWER); | |
254 | ||
255 | val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV1_POWER); | |
256 | val |= PCIE_PHY_TRSV1_PD_TSV; | |
257 | exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV1_POWER); | |
258 | ||
259 | val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV2_POWER); | |
260 | val |= PCIE_PHY_TRSV2_PD_TSV; | |
261 | exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV2_POWER); | |
262 | ||
263 | val = exynos_phy_readl(exynos_pcie, PCIE_PHY_TRSV3_POWER); | |
264 | val |= PCIE_PHY_TRSV3_PD_TSV; | |
265 | exynos_phy_writel(exynos_pcie, val, PCIE_PHY_TRSV3_POWER); | |
266 | } | |
267 | ||
4b1ced84 JH |
268 | static void exynos_pcie_init_phy(struct pcie_port *pp) |
269 | { | |
270 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); | |
4b1ced84 JH |
271 | |
272 | /* DCC feedback control off */ | |
058dd016 | 273 | exynos_phy_writel(exynos_pcie, 0x29, PCIE_PHY_DCC_FEEDBACK); |
4b1ced84 JH |
274 | |
275 | /* set TX/RX impedance */ | |
058dd016 | 276 | exynos_phy_writel(exynos_pcie, 0xd5, PCIE_PHY_IMPEDANCE); |
4b1ced84 JH |
277 | |
278 | /* set 50Mhz PHY clock */ | |
058dd016 SJ |
279 | exynos_phy_writel(exynos_pcie, 0x14, PCIE_PHY_PLL_DIV_0); |
280 | exynos_phy_writel(exynos_pcie, 0x12, PCIE_PHY_PLL_DIV_1); | |
4b1ced84 JH |
281 | |
282 | /* set TX Differential output for lane 0 */ | |
058dd016 | 283 | exynos_phy_writel(exynos_pcie, 0x7f, PCIE_PHY_TRSV0_DRV_LVL); |
4b1ced84 JH |
284 | |
285 | /* set TX Pre-emphasis Level Control for lane 0 to minimum */ | |
058dd016 | 286 | exynos_phy_writel(exynos_pcie, 0x0, PCIE_PHY_TRSV0_EMP_LVL); |
4b1ced84 JH |
287 | |
288 | /* set RX clock and data recovery bandwidth */ | |
058dd016 SJ |
289 | exynos_phy_writel(exynos_pcie, 0xe7, PCIE_PHY_PLL_BIAS); |
290 | exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV0_RXCDR); | |
291 | exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV1_RXCDR); | |
292 | exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV2_RXCDR); | |
293 | exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV3_RXCDR); | |
4b1ced84 JH |
294 | |
295 | /* change TX Pre-emphasis Level Control for lanes */ | |
058dd016 SJ |
296 | exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV0_EMP_LVL); |
297 | exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV1_EMP_LVL); | |
298 | exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV2_EMP_LVL); | |
299 | exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV3_EMP_LVL); | |
4b1ced84 JH |
300 | |
301 | /* set LVCC */ | |
058dd016 SJ |
302 | exynos_phy_writel(exynos_pcie, 0x20, PCIE_PHY_TRSV0_LVCC); |
303 | exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV1_LVCC); | |
304 | exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV2_LVCC); | |
305 | exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV3_LVCC); | |
4b1ced84 JH |
306 | } |
307 | ||
308 | static void exynos_pcie_assert_reset(struct pcie_port *pp) | |
309 | { | |
310 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); | |
311 | ||
312 | if (exynos_pcie->reset_gpio >= 0) | |
313 | devm_gpio_request_one(pp->dev, exynos_pcie->reset_gpio, | |
314 | GPIOF_OUT_INIT_HIGH, "RESET"); | |
4b1ced84 JH |
315 | } |
316 | ||
317 | static int exynos_pcie_establish_link(struct pcie_port *pp) | |
318 | { | |
4b1ced84 | 319 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
6cbb247e | 320 | u32 val; |
4b1ced84 JH |
321 | |
322 | if (dw_pcie_link_up(pp)) { | |
323 | dev_err(pp->dev, "Link already up\n"); | |
324 | return 0; | |
325 | } | |
326 | ||
327 | /* assert reset signals */ | |
328 | exynos_pcie_assert_core_reset(pp); | |
329 | exynos_pcie_assert_phy_reset(pp); | |
330 | ||
331 | /* de-assert phy reset */ | |
332 | exynos_pcie_deassert_phy_reset(pp); | |
333 | ||
f62b878b JH |
334 | /* power on phy */ |
335 | exynos_pcie_power_on_phy(pp); | |
336 | ||
4b1ced84 JH |
337 | /* initialize phy */ |
338 | exynos_pcie_init_phy(pp); | |
339 | ||
340 | /* pulse for common reset */ | |
058dd016 | 341 | exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_COMMON_RESET); |
4b1ced84 | 342 | udelay(500); |
058dd016 | 343 | exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET); |
4b1ced84 JH |
344 | |
345 | /* de-assert core reset */ | |
346 | exynos_pcie_deassert_core_reset(pp); | |
347 | ||
348 | /* setup root complex */ | |
349 | dw_pcie_setup_rc(pp); | |
350 | ||
351 | /* assert reset signal */ | |
352 | exynos_pcie_assert_reset(pp); | |
353 | ||
354 | /* assert LTSSM enable */ | |
058dd016 SJ |
355 | exynos_elb_writel(exynos_pcie, PCIE_ELBI_LTSSM_ENABLE, |
356 | PCIE_APP_LTSSM_ENABLE); | |
4b1ced84 JH |
357 | |
358 | /* check if the link is up or not */ | |
886bc5ce JP |
359 | if (!dw_pcie_wait_for_link(pp)) |
360 | return 0; | |
4b1ced84 | 361 | |
6cbb247e BH |
362 | while (exynos_phy_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED) == 0) { |
363 | val = exynos_blk_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED); | |
364 | dev_info(pp->dev, "PLL Locked: 0x%x\n", val); | |
365 | } | |
366 | /* power off phy */ | |
367 | exynos_pcie_power_off_phy(pp); | |
4b1ced84 | 368 | |
886bc5ce | 369 | return -ETIMEDOUT; |
4b1ced84 JH |
370 | } |
371 | ||
372 | static void exynos_pcie_clear_irq_pulse(struct pcie_port *pp) | |
373 | { | |
374 | u32 val; | |
375 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); | |
4b1ced84 | 376 | |
058dd016 SJ |
377 | val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_PULSE); |
378 | exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_PULSE); | |
4b1ced84 JH |
379 | } |
380 | ||
381 | static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp) | |
382 | { | |
383 | u32 val; | |
384 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); | |
4b1ced84 JH |
385 | |
386 | /* enable INTX interrupt */ | |
387 | val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | | |
01d06a9a | 388 | IRQ_INTC_ASSERT | IRQ_INTD_ASSERT; |
058dd016 | 389 | exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_PULSE); |
4b1ced84 JH |
390 | } |
391 | ||
392 | static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) | |
393 | { | |
394 | struct pcie_port *pp = arg; | |
395 | ||
396 | exynos_pcie_clear_irq_pulse(pp); | |
397 | return IRQ_HANDLED; | |
398 | } | |
399 | ||
f342d940 JH |
400 | static irqreturn_t exynos_pcie_msi_irq_handler(int irq, void *arg) |
401 | { | |
402 | struct pcie_port *pp = arg; | |
403 | ||
7f4f16ee | 404 | return dw_handle_msi_irq(pp); |
f342d940 JH |
405 | } |
406 | ||
407 | static void exynos_pcie_msi_init(struct pcie_port *pp) | |
408 | { | |
409 | u32 val; | |
410 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); | |
411 | ||
412 | dw_pcie_msi_init(pp); | |
413 | ||
414 | /* enable MSI interrupt */ | |
415 | val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_EN_LEVEL); | |
416 | val |= IRQ_MSI_ENABLE; | |
417 | exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_LEVEL); | |
f342d940 JH |
418 | } |
419 | ||
4b1ced84 JH |
420 | static void exynos_pcie_enable_interrupts(struct pcie_port *pp) |
421 | { | |
422 | exynos_pcie_enable_irq_pulse(pp); | |
f342d940 JH |
423 | |
424 | if (IS_ENABLED(CONFIG_PCI_MSI)) | |
425 | exynos_pcie_msi_init(pp); | |
4b1ced84 JH |
426 | } |
427 | ||
428 | static inline void exynos_pcie_readl_rc(struct pcie_port *pp, | |
429 | void __iomem *dbi_base, u32 *val) | |
430 | { | |
431 | exynos_pcie_sideband_dbi_r_mode(pp, true); | |
432 | *val = readl(dbi_base); | |
433 | exynos_pcie_sideband_dbi_r_mode(pp, false); | |
4b1ced84 JH |
434 | } |
435 | ||
436 | static inline void exynos_pcie_writel_rc(struct pcie_port *pp, | |
437 | u32 val, void __iomem *dbi_base) | |
438 | { | |
439 | exynos_pcie_sideband_dbi_w_mode(pp, true); | |
440 | writel(val, dbi_base); | |
441 | exynos_pcie_sideband_dbi_w_mode(pp, false); | |
4b1ced84 JH |
442 | } |
443 | ||
444 | static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, | |
445 | u32 *val) | |
446 | { | |
447 | int ret; | |
448 | ||
449 | exynos_pcie_sideband_dbi_r_mode(pp, true); | |
4c45852f | 450 | ret = dw_pcie_cfg_read(pp->dbi_base + where, size, val); |
4b1ced84 JH |
451 | exynos_pcie_sideband_dbi_r_mode(pp, false); |
452 | return ret; | |
453 | } | |
454 | ||
455 | static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, | |
456 | u32 val) | |
457 | { | |
458 | int ret; | |
459 | ||
460 | exynos_pcie_sideband_dbi_w_mode(pp, true); | |
4c45852f | 461 | ret = dw_pcie_cfg_write(pp->dbi_base + where, size, val); |
4b1ced84 JH |
462 | exynos_pcie_sideband_dbi_w_mode(pp, false); |
463 | return ret; | |
464 | } | |
465 | ||
466 | static int exynos_pcie_link_up(struct pcie_port *pp) | |
467 | { | |
468 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); | |
058dd016 | 469 | u32 val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_RDLH_LINKUP); |
4b1ced84 JH |
470 | |
471 | if (val == PCIE_ELBI_LTSSM_ENABLE) | |
472 | return 1; | |
473 | ||
474 | return 0; | |
475 | } | |
476 | ||
477 | static void exynos_pcie_host_init(struct pcie_port *pp) | |
478 | { | |
479 | exynos_pcie_establish_link(pp); | |
480 | exynos_pcie_enable_interrupts(pp); | |
481 | } | |
482 | ||
483 | static struct pcie_host_ops exynos_pcie_host_ops = { | |
484 | .readl_rc = exynos_pcie_readl_rc, | |
485 | .writel_rc = exynos_pcie_writel_rc, | |
486 | .rd_own_conf = exynos_pcie_rd_own_conf, | |
487 | .wr_own_conf = exynos_pcie_wr_own_conf, | |
488 | .link_up = exynos_pcie_link_up, | |
489 | .host_init = exynos_pcie_host_init, | |
490 | }; | |
491 | ||
70b3e89a JH |
492 | static int __init exynos_add_pcie_port(struct pcie_port *pp, |
493 | struct platform_device *pdev) | |
4b1ced84 JH |
494 | { |
495 | int ret; | |
496 | ||
497 | pp->irq = platform_get_irq(pdev, 1); | |
498 | if (!pp->irq) { | |
499 | dev_err(&pdev->dev, "failed to get irq\n"); | |
500 | return -ENODEV; | |
501 | } | |
502 | ret = devm_request_irq(&pdev->dev, pp->irq, exynos_pcie_irq_handler, | |
503 | IRQF_SHARED, "exynos-pcie", pp); | |
504 | if (ret) { | |
505 | dev_err(&pdev->dev, "failed to request irq\n"); | |
506 | return ret; | |
507 | } | |
508 | ||
f342d940 JH |
509 | if (IS_ENABLED(CONFIG_PCI_MSI)) { |
510 | pp->msi_irq = platform_get_irq(pdev, 0); | |
511 | if (!pp->msi_irq) { | |
512 | dev_err(&pdev->dev, "failed to get msi irq\n"); | |
513 | return -ENODEV; | |
514 | } | |
515 | ||
516 | ret = devm_request_irq(&pdev->dev, pp->msi_irq, | |
517 | exynos_pcie_msi_irq_handler, | |
8ff0ef99 GS |
518 | IRQF_SHARED | IRQF_NO_THREAD, |
519 | "exynos-pcie", pp); | |
f342d940 JH |
520 | if (ret) { |
521 | dev_err(&pdev->dev, "failed to request msi irq\n"); | |
522 | return ret; | |
523 | } | |
524 | } | |
525 | ||
4b1ced84 JH |
526 | pp->root_bus_nr = -1; |
527 | pp->ops = &exynos_pcie_host_ops; | |
528 | ||
4b1ced84 JH |
529 | ret = dw_pcie_host_init(pp); |
530 | if (ret) { | |
531 | dev_err(&pdev->dev, "failed to initialize host\n"); | |
532 | return ret; | |
533 | } | |
534 | ||
535 | return 0; | |
536 | } | |
537 | ||
538 | static int __init exynos_pcie_probe(struct platform_device *pdev) | |
539 | { | |
540 | struct exynos_pcie *exynos_pcie; | |
541 | struct pcie_port *pp; | |
542 | struct device_node *np = pdev->dev.of_node; | |
543 | struct resource *elbi_base; | |
544 | struct resource *phy_base; | |
545 | struct resource *block_base; | |
546 | int ret; | |
547 | ||
548 | exynos_pcie = devm_kzalloc(&pdev->dev, sizeof(*exynos_pcie), | |
549 | GFP_KERNEL); | |
755ba5e4 | 550 | if (!exynos_pcie) |
4b1ced84 | 551 | return -ENOMEM; |
4b1ced84 JH |
552 | |
553 | pp = &exynos_pcie->pp; | |
554 | ||
555 | pp->dev = &pdev->dev; | |
556 | ||
557 | exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0); | |
558 | ||
559 | exynos_pcie->clk = devm_clk_get(&pdev->dev, "pcie"); | |
560 | if (IS_ERR(exynos_pcie->clk)) { | |
561 | dev_err(&pdev->dev, "Failed to get pcie rc clock\n"); | |
562 | return PTR_ERR(exynos_pcie->clk); | |
563 | } | |
564 | ret = clk_prepare_enable(exynos_pcie->clk); | |
565 | if (ret) | |
566 | return ret; | |
567 | ||
568 | exynos_pcie->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus"); | |
569 | if (IS_ERR(exynos_pcie->bus_clk)) { | |
570 | dev_err(&pdev->dev, "Failed to get pcie bus clock\n"); | |
571 | ret = PTR_ERR(exynos_pcie->bus_clk); | |
572 | goto fail_clk; | |
573 | } | |
574 | ret = clk_prepare_enable(exynos_pcie->bus_clk); | |
575 | if (ret) | |
576 | goto fail_clk; | |
577 | ||
578 | elbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
579 | exynos_pcie->elbi_base = devm_ioremap_resource(&pdev->dev, elbi_base); | |
f8db3c90 WY |
580 | if (IS_ERR(exynos_pcie->elbi_base)) { |
581 | ret = PTR_ERR(exynos_pcie->elbi_base); | |
582 | goto fail_bus_clk; | |
583 | } | |
4b1ced84 JH |
584 | |
585 | phy_base = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
586 | exynos_pcie->phy_base = devm_ioremap_resource(&pdev->dev, phy_base); | |
f8db3c90 WY |
587 | if (IS_ERR(exynos_pcie->phy_base)) { |
588 | ret = PTR_ERR(exynos_pcie->phy_base); | |
589 | goto fail_bus_clk; | |
590 | } | |
4b1ced84 JH |
591 | |
592 | block_base = platform_get_resource(pdev, IORESOURCE_MEM, 2); | |
593 | exynos_pcie->block_base = devm_ioremap_resource(&pdev->dev, block_base); | |
f8db3c90 WY |
594 | if (IS_ERR(exynos_pcie->block_base)) { |
595 | ret = PTR_ERR(exynos_pcie->block_base); | |
596 | goto fail_bus_clk; | |
597 | } | |
4b1ced84 | 598 | |
70b3e89a | 599 | ret = exynos_add_pcie_port(pp, pdev); |
4b1ced84 JH |
600 | if (ret < 0) |
601 | goto fail_bus_clk; | |
602 | ||
603 | platform_set_drvdata(pdev, exynos_pcie); | |
604 | return 0; | |
605 | ||
606 | fail_bus_clk: | |
607 | clk_disable_unprepare(exynos_pcie->bus_clk); | |
608 | fail_clk: | |
609 | clk_disable_unprepare(exynos_pcie->clk); | |
610 | return ret; | |
611 | } | |
612 | ||
613 | static int __exit exynos_pcie_remove(struct platform_device *pdev) | |
614 | { | |
615 | struct exynos_pcie *exynos_pcie = platform_get_drvdata(pdev); | |
616 | ||
617 | clk_disable_unprepare(exynos_pcie->bus_clk); | |
618 | clk_disable_unprepare(exynos_pcie->clk); | |
619 | ||
620 | return 0; | |
621 | } | |
622 | ||
623 | static const struct of_device_id exynos_pcie_of_match[] = { | |
624 | { .compatible = "samsung,exynos5440-pcie", }, | |
625 | {}, | |
626 | }; | |
4b1ced84 JH |
627 | |
628 | static struct platform_driver exynos_pcie_driver = { | |
629 | .remove = __exit_p(exynos_pcie_remove), | |
630 | .driver = { | |
631 | .name = "exynos-pcie", | |
eb36309a | 632 | .of_match_table = exynos_pcie_of_match, |
4b1ced84 JH |
633 | }, |
634 | }; | |
635 | ||
636 | /* Exynos PCIe driver does not allow module unload */ | |
637 | ||
70b3e89a | 638 | static int __init exynos_pcie_init(void) |
4b1ced84 JH |
639 | { |
640 | return platform_driver_probe(&exynos_pcie_driver, exynos_pcie_probe); | |
641 | } | |
70b3e89a | 642 | subsys_initcall(exynos_pcie_init); |