[deliverable/linux.git] / drivers / pci / host / pci-keystone.c

/*
 * PCIe host controller driver for Texas Instruments Keystone SoCs
 *
 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
 *		http://www.ti.com
 *
 * Author: Murali Karicheri <m-karicheri2@ti.com>
 * Implementation based on pci-exynos.c and pcie-designware.c
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/irqchip/chained_irq.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/init.h>
#include <linux/msi.h>
#include <linux/of_irq.h>
#include <linux/of.h>
#include <linux/of_pci.h>
#include <linux/platform_device.h>
#include <linux/phy/phy.h>
#include <linux/resource.h>
#include <linux/signal.h>

#include "pcie-designware.h"
#include "pci-keystone.h"

#define DRIVER_NAME	"keystone-pcie"

/* driver specific constants */
#define MAX_MSI_HOST_IRQS		8
#define MAX_LEGACY_HOST_IRQS		4

/* DEV_STAT_CTRL */
#define PCIE_CAP_BASE		0x70

/* PCIE controller device IDs */
#define PCIE_RC_K2HK		0xb008
#define PCIE_RC_K2E		0xb009
#define PCIE_RC_K2L		0xb00a

#define to_keystone_pcie(x)	container_of(x, struct keystone_pcie, pp)

static void quirk_limit_mrrs(struct pci_dev *dev)
{
	struct pci_bus *bus = dev->bus;
	struct pci_dev *bridge = bus->self;
	static const struct pci_device_id rc_pci_devids[] = {
		{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK),
		 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
		{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2E),
		 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
		{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L),
		 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
		{ 0, },
	};

	if (pci_is_root_bus(bus))
		return;

	/* look for the host bridge */
	while (!pci_is_root_bus(bus)) {
		bridge = bus->self;
		bus = bus->parent;
	}

	if (bridge) {
		/*
		 * Keystone PCI controller has a h/w limitation of
		 * 256 bytes maximum read request size.  It can't handle
		 * anything higher than this.  So force this limit on
		 * all downstream devices.
		 */
		if (pci_match_id(rc_pci_devids, bridge)) {
			if (pcie_get_readrq(dev) > 256) {
				dev_info(&dev->dev, "limiting MRRS to 256\n");
				pcie_set_readrq(dev, 256);
			}
		}
	}
}
DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs);

static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
{
	struct pcie_port *pp = &ks_pcie->pp;
	unsigned int retries;

	dw_pcie_setup_rc(pp);

	if (dw_pcie_link_up(pp)) {
		dev_err(pp->dev, "Link already up\n");
		return 0;
	}

	/* check if the link is up or not */
	for (retries = 0; retries < 5; retries++) {
		ks_dw_pcie_initiate_link_train(ks_pcie);
		if (!dw_pcie_wait_for_link(pp))
			return 0;
	}

	dev_err(pp->dev, "phy link never came up\n");
	return -ETIMEDOUT;
}

static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
{
	unsigned int irq = irq_desc_get_irq(desc);
	struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
	u32 offset = irq - ks_pcie->msi_host_irqs[0];
	struct pcie_port *pp = &ks_pcie->pp;
	struct irq_chip *chip = irq_desc_get_chip(desc);

	dev_dbg(pp->dev, "%s, irq %d\n", __func__, irq);

	/*
	 * The chained irq handler installation would have replaced normal
	 * interrupt driver handler so we need to take care of mask/unmask and
	 * ack operation.
	 */
	chained_irq_enter(chip, desc);
	ks_dw_pcie_handle_msi_irq(ks_pcie, offset);
	chained_irq_exit(chip, desc);
}

/**
 * ks_pcie_legacy_irq_handler() - Handle legacy interrupt
 * @irq: IRQ line for legacy interrupts
 * @desc: Pointer to irq descriptor
 *
 * Traverse through pending legacy interrupts and invoke handler for each. Also
 * takes care of interrupt controller level mask/ack operation.
 */
static void ks_pcie_legacy_irq_handler(struct irq_desc *desc)
{
	unsigned int irq = irq_desc_get_irq(desc);
	struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
	struct pcie_port *pp = &ks_pcie->pp;
	u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0];
	struct irq_chip *chip = irq_desc_get_chip(desc);

	dev_dbg(pp->dev, ": Handling legacy irq %d\n", irq);

	/*
	 * The chained irq handler installation would have replaced normal
	 * interrupt driver handler so we need to take care of mask/unmask and
	 * ack operation.
	 */
	chained_irq_enter(chip, desc);
	ks_dw_pcie_handle_legacy_irq(ks_pcie, irq_offset);
	chained_irq_exit(chip, desc);
}

static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
					   char *controller, int *num_irqs)
{
	int temp, max_host_irqs, legacy = 1, *host_irqs;
	struct device *dev = ks_pcie->pp.dev;
	struct device_node *np_pcie = dev->of_node, **np_temp;

	if (!strcmp(controller, "msi-interrupt-controller"))
		legacy = 0;

	if (legacy) {
		np_temp = &ks_pcie->legacy_intc_np;
		max_host_irqs = MAX_LEGACY_HOST_IRQS;
		host_irqs = &ks_pcie->legacy_host_irqs[0];
	} else {
		np_temp = &ks_pcie->msi_intc_np;
		max_host_irqs = MAX_MSI_HOST_IRQS;
		host_irqs =  &ks_pcie->msi_host_irqs[0];
	}

	/* interrupt controller is in a child node */
	*np_temp = of_find_node_by_name(np_pcie, controller);
	if (!(*np_temp)) {
		dev_err(dev, "Node for %s is absent\n", controller);
		return -EINVAL;
	}

	temp = of_irq_count(*np_temp);
	if (!temp) {
		dev_err(dev, "No IRQ entries in %s\n", controller);
		return -EINVAL;
	}

	if (temp > max_host_irqs)
		dev_warn(dev, "Too many %s interrupts defined %u\n",
			(legacy ? "legacy" : "MSI"), temp);

	/*
	 * support upto max_host_irqs. In dt from index 0 to 3 (legacy) or 0 to
	 * 7 (MSI)
	 */
	for (temp = 0; temp < max_host_irqs; temp++) {
		host_irqs[temp] = irq_of_parse_and_map(*np_temp, temp);
		if (!host_irqs[temp])
			break;
	}

	if (temp) {
		*num_irqs = temp;
		return 0;
	}

	return -EINVAL;
}

static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie)
{
	int i;

	/* Legacy IRQ */
	for (i = 0; i < ks_pcie->num_legacy_host_irqs; i++) {
		irq_set_chained_handler_and_data(ks_pcie->legacy_host_irqs[i],
						 ks_pcie_legacy_irq_handler,
						 ks_pcie);
	}
	ks_dw_pcie_enable_legacy_irqs(ks_pcie);

	/* MSI IRQ */
	if (IS_ENABLED(CONFIG_PCI_MSI)) {
		for (i = 0; i < ks_pcie->num_msi_host_irqs; i++) {
			irq_set_chained_handler_and_data(ks_pcie->msi_host_irqs[i],
							 ks_pcie_msi_irq_handler,
							 ks_pcie);
		}
	}

	if (ks_pcie->error_irq > 0)
		ks_dw_pcie_enable_error_irq(ks_pcie->va_app_base);
}

/*
 * When a PCI device does not exist during config cycles, keystone host gets a
 * bus error instead of returning 0xffffffff. This handler always returns 0
 * for this kind of faults.
 */
static int keystone_pcie_fault(unsigned long addr, unsigned int fsr,
				struct pt_regs *regs)
{
	unsigned long instr = *(unsigned long *) instruction_pointer(regs);

	if ((instr & 0x0e100090) == 0x00100090) {
		int reg = (instr >> 12) & 15;

		regs->uregs[reg] = -1;
		regs->ARM_pc += 4;
	}

	return 0;
}

static void __init ks_pcie_host_init(struct pcie_port *pp)
{
	struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
	u32 val;

	ks_pcie_establish_link(ks_pcie);
	ks_dw_pcie_setup_rc_app_regs(ks_pcie);
	ks_pcie_setup_interrupts(ks_pcie);
	writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8),
			pp->dbi_base + PCI_IO_BASE);

	/* update the Vendor ID */
	writew(ks_pcie->device_id, pp->dbi_base + PCI_DEVICE_ID);

	/* update the DEV_STAT_CTRL to publish right mrrs */
	val = readl(pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
	val &= ~PCI_EXP_DEVCTL_READRQ;
	/* set the mrrs to 256 bytes */
	val |= BIT(12);
	writel(val, pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);

	/*
	 * PCIe access errors that result into OCP errors are caught by ARM as
	 * "External aborts"
	 */
	hook_fault_code(17, keystone_pcie_fault, SIGBUS, 0,
			"Asynchronous external abort");
}

static struct pcie_host_ops keystone_pcie_host_ops = {
	.rd_other_conf = ks_dw_pcie_rd_other_conf,
	.wr_other_conf = ks_dw_pcie_wr_other_conf,
	.link_up = ks_dw_pcie_link_up,
	.host_init = ks_pcie_host_init,
	.msi_set_irq = ks_dw_pcie_msi_set_irq,
	.msi_clear_irq = ks_dw_pcie_msi_clear_irq,
	.get_msi_addr = ks_dw_pcie_get_msi_addr,
	.msi_host_init = ks_dw_pcie_msi_host_init,
	.scan_bus = ks_dw_pcie_v3_65_scan_bus,
};

static irqreturn_t pcie_err_irq_handler(int irq, void *priv)
{
	struct keystone_pcie *ks_pcie = priv;

	return ks_dw_pcie_handle_error_irq(ks_pcie->pp.dev,
					   ks_pcie->va_app_base);
}

static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
			 struct platform_device *pdev)
{
	struct pcie_port *pp = &ks_pcie->pp;
	int ret;

	ret = ks_pcie_get_irq_controller_info(ks_pcie,
					"legacy-interrupt-controller",
					&ks_pcie->num_legacy_host_irqs);
	if (ret)
		return ret;

	if (IS_ENABLED(CONFIG_PCI_MSI)) {
		ret = ks_pcie_get_irq_controller_info(ks_pcie,
						"msi-interrupt-controller",
						&ks_pcie->num_msi_host_irqs);
		if (ret)
			return ret;
	}

	/*
	 * Index 0 is the platform interrupt for error interrupt
	 * from RC.  This is optional.
	 */
	ks_pcie->error_irq = irq_of_parse_and_map(ks_pcie->np, 0);
	if (ks_pcie->error_irq <= 0)
		dev_info(&pdev->dev, "no error IRQ defined\n");
	else {
		ret = request_irq(ks_pcie->error_irq, pcie_err_irq_handler,
				  IRQF_SHARED, "pcie-error-irq", ks_pcie);
		if (ret < 0) {
			dev_err(&pdev->dev, "failed to request error IRQ %d\n",
				ks_pcie->error_irq);
			return ret;
		}
	}

	pp->root_bus_nr = -1;
	pp->ops = &keystone_pcie_host_ops;
	ret = ks_dw_pcie_host_init(ks_pcie, ks_pcie->msi_intc_np);
	if (ret) {
		dev_err(&pdev->dev, "failed to initialize host\n");
		return ret;
	}

	return 0;
}

static const struct of_device_id ks_pcie_of_match[] = {
	{
		.type = "pci",
		.compatible = "ti,keystone-pcie",
	},
	{ },
};

static int __exit ks_pcie_remove(struct platform_device *pdev)
{
	struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev);

	clk_disable_unprepare(ks_pcie->clk);

	return 0;
}

static int __init ks_pcie_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct keystone_pcie *ks_pcie;
	struct pcie_port *pp;
	struct resource *res;
	void __iomem *reg_p;
	struct phy *phy;
	int ret;

	ks_pcie = devm_kzalloc(&pdev->dev, sizeof(*ks_pcie),
				GFP_KERNEL);
	if (!ks_pcie)
		return -ENOMEM;

	pp = &ks_pcie->pp;

	/* initialize SerDes Phy if present */
	phy = devm_phy_get(dev, "pcie-phy");
	if (PTR_ERR_OR_ZERO(phy) == -EPROBE_DEFER)
		return PTR_ERR(phy);

	if (!IS_ERR_OR_NULL(phy)) {
		ret = phy_init(phy);
		if (ret < 0)
			return ret;
	}

	/* index 2 is to read PCI DEVICE_ID */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
	reg_p = devm_ioremap_resource(dev, res);
	if (IS_ERR(reg_p))
		return PTR_ERR(reg_p);
	ks_pcie->device_id = readl(reg_p) >> 16;
	devm_iounmap(dev, reg_p);
	devm_release_mem_region(dev, res->start, resource_size(res));

	pp->dev = dev;
	ks_pcie->np = dev->of_node;
	platform_set_drvdata(pdev, ks_pcie);
	ks_pcie->clk = devm_clk_get(dev, "pcie");
	if (IS_ERR(ks_pcie->clk)) {
		dev_err(dev, "Failed to get pcie rc clock\n");
		return PTR_ERR(ks_pcie->clk);
	}
	ret = clk_prepare_enable(ks_pcie->clk);
	if (ret)
		return ret;

	ret = ks_add_pcie_port(ks_pcie, pdev);
	if (ret < 0)
		goto fail_clk;

	return 0;
fail_clk:
	clk_disable_unprepare(ks_pcie->clk);

	return ret;
}

static struct platform_driver ks_pcie_driver __refdata = {
	.probe  = ks_pcie_probe,
	.remove = __exit_p(ks_pcie_remove),
	.driver = {
		.name	= "keystone-pcie",
		.of_match_table = of_match_ptr(ks_pcie_of_match),
	},
};
builtin_platform_driver(ks_pcie_driver);
Commit	Line	Data
0c4ffcfe MK	1	/*
	2	* PCIe host controller driver for Texas Instruments Keystone SoCs
	3	*
	4	* Copyright (C) 2013-2014 Texas Instruments., Ltd.
	5	* http://www.ti.com
	6	*
	7	* Author: Murali Karicheri <m-karicheri2@ti.com>
	8	* Implementation based on pci-exynos.c and pcie-designware.c
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/irqchip/chained_irq.h>
	16	#include <linux/clk.h>
	17	#include <linux/delay.h>
025dd3da	18	#include <linux/interrupt.h>
0c4ffcfe	19	#include <linux/irqdomain.h>
1481bf21	20	#include <linux/init.h>
0c4ffcfe MK	21	#include <linux/msi.h>
	22	#include <linux/of_irq.h>
	23	#include <linux/of.h>
	24	#include <linux/of_pci.h>
	25	#include <linux/platform_device.h>
	26	#include <linux/phy/phy.h>
	27	#include <linux/resource.h>
	28	#include <linux/signal.h>
	29
	30	#include "pcie-designware.h"
	31	#include "pci-keystone.h"
	32
	33	#define DRIVER_NAME "keystone-pcie"
	34
	35	/* driver specific constants */
	36	#define MAX_MSI_HOST_IRQS 8
	37	#define MAX_LEGACY_HOST_IRQS 4
	38
0c4ffcfe MK	39	/* DEV_STAT_CTRL */
	40	#define PCIE_CAP_BASE 0x70
	41
c15982df MK	42	/* PCIE controller device IDs */
	43	#define PCIE_RC_K2HK 0xb008
	44	#define PCIE_RC_K2E 0xb009
	45	#define PCIE_RC_K2L 0xb00a
	46
0c4ffcfe MK	47	#define to_keystone_pcie(x) container_of(x, struct keystone_pcie, pp)
0c4ffcfe MK	48
c15982df MK	49	static void quirk_limit_mrrs(struct pci_dev *dev)
	50	{
	51	struct pci_bus *bus = dev->bus;
	52	struct pci_dev *bridge = bus->self;
	53	static const struct pci_device_id rc_pci_devids[] = {
	54	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK),
	55	.class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
	56	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2E),
	57	.class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
	58	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L),
	59	.class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
	60	{ 0, },
	61	};
	62
	63	if (pci_is_root_bus(bus))
	64	return;
	65
	66	/* look for the host bridge */
	67	while (!pci_is_root_bus(bus)) {
	68	bridge = bus->self;
	69	bus = bus->parent;
	70	}
	71
	72	if (bridge) {
	73	/*
	74	* Keystone PCI controller has a h/w limitation of
	75	* 256 bytes maximum read request size. It can't handle
	76	* anything higher than this. So force this limit on
	77	* all downstream devices.
	78	*/
	79	if (pci_match_id(rc_pci_devids, bridge)) {
	80	if (pcie_get_readrq(dev) > 256) {
	81	dev_info(&dev->dev, "limiting MRRS to 256\n");
	82	pcie_set_readrq(dev, 256);
	83	}
	84	}
	85	}
	86	}
	87	DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs);
	88
0c4ffcfe MK	89	static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
	90	{
	91	struct pcie_port *pp = &ks_pcie->pp;
6cbb247e	92	unsigned int retries;
0c4ffcfe MK	93
	94	dw_pcie_setup_rc(pp);
	95
	96	if (dw_pcie_link_up(pp)) {
	97	dev_err(pp->dev, "Link already up\n");
	98	return 0;
	99	}
	100
0c4ffcfe	101	/* check if the link is up or not */
886bc5ce	102	for (retries = 0; retries < 5; retries++) {
6cbb247e	103	ks_dw_pcie_initiate_link_train(ks_pcie);
886bc5ce JP	104	if (!dw_pcie_wait_for_link(pp))
886bc5ce JP	105	return 0;
0c4ffcfe MK	106	}
0c4ffcfe MK	107
6cbb247e	108	dev_err(pp->dev, "phy link never came up\n");
886bc5ce	109	return -ETIMEDOUT;
0c4ffcfe MK	110	}
0c4ffcfe MK	111
bd0b9ac4	112	static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
0c4ffcfe	113	{
97a85964	114	unsigned int irq = irq_desc_get_irq(desc);
0c4ffcfe MK	115	struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
	116	u32 offset = irq - ks_pcie->msi_host_irqs[0];
	117	struct pcie_port *pp = &ks_pcie->pp;
	118	struct irq_chip *chip = irq_desc_get_chip(desc);
	119
4808c35e	120	dev_dbg(pp->dev, "%s, irq %d\n", __func__, irq);
0c4ffcfe MK	121
	122	/*
	123	* The chained irq handler installation would have replaced normal
	124	* interrupt driver handler so we need to take care of mask/unmask and
	125	* ack operation.
	126	*/
	127	chained_irq_enter(chip, desc);
	128	ks_dw_pcie_handle_msi_irq(ks_pcie, offset);
	129	chained_irq_exit(chip, desc);
	130	}
	131
	132	/**
	133	* ks_pcie_legacy_irq_handler() - Handle legacy interrupt
	134	* @irq: IRQ line for legacy interrupts
	135	* @desc: Pointer to irq descriptor
	136	*
	137	* Traverse through pending legacy interrupts and invoke handler for each. Also
	138	* takes care of interrupt controller level mask/ack operation.
	139	*/
bd0b9ac4	140	static void ks_pcie_legacy_irq_handler(struct irq_desc *desc)
0c4ffcfe	141	{
97a85964	142	unsigned int irq = irq_desc_get_irq(desc);
0c4ffcfe MK	143	struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
	144	struct pcie_port *pp = &ks_pcie->pp;
	145	u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0];
	146	struct irq_chip *chip = irq_desc_get_chip(desc);
	147
	148	dev_dbg(pp->dev, ": Handling legacy irq %d\n", irq);
	149
	150	/*
	151	* The chained irq handler installation would have replaced normal
	152	* interrupt driver handler so we need to take care of mask/unmask and
	153	* ack operation.
	154	*/
	155	chained_irq_enter(chip, desc);
	156	ks_dw_pcie_handle_legacy_irq(ks_pcie, irq_offset);
	157	chained_irq_exit(chip, desc);
	158	}
	159
	160	static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
	161	char controller, int num_irqs)
	162	{
1e9f8dcf	163	int temp, max_host_irqs, legacy = 1, *host_irqs;
0c4ffcfe MK	164	struct device *dev = ks_pcie->pp.dev;
	165	struct device_node np_pcie = dev->of_node, *np_temp;
	166
	167	if (!strcmp(controller, "msi-interrupt-controller"))
	168	legacy = 0;
	169
	170	if (legacy) {
	171	np_temp = &ks_pcie->legacy_intc_np;
	172	max_host_irqs = MAX_LEGACY_HOST_IRQS;
	173	host_irqs = &ks_pcie->legacy_host_irqs[0];
	174	} else {
	175	np_temp = &ks_pcie->msi_intc_np;
	176	max_host_irqs = MAX_MSI_HOST_IRQS;
	177	host_irqs = &ks_pcie->msi_host_irqs[0];
	178	}
	179
	180	/* interrupt controller is in a child node */
	181	*np_temp = of_find_node_by_name(np_pcie, controller);
	182	if (!(*np_temp)) {
	183	dev_err(dev, "Node for %s is absent\n", controller);
1e9f8dcf	184	return -EINVAL;
0c4ffcfe	185	}
1e9f8dcf	186
0c4ffcfe	187	temp = of_irq_count(*np_temp);
1e9f8dcf MK	188	if (!temp) {
	189	dev_err(dev, "No IRQ entries in %s\n", controller);
	190	return -EINVAL;
	191	}
	192
0c4ffcfe MK	193	if (temp > max_host_irqs)
	194	dev_warn(dev, "Too many %s interrupts defined %u\n",
	195	(legacy ? "legacy" : "MSI"), temp);
	196
	197	/*
	198	* support upto max_host_irqs. In dt from index 0 to 3 (legacy) or 0 to
	199	* 7 (MSI)
	200	*/
	201	for (temp = 0; temp < max_host_irqs; temp++) {
	202	host_irqs[temp] = irq_of_parse_and_map(*np_temp, temp);
ea3651fe	203	if (!host_irqs[temp])
0c4ffcfe MK	204	break;
0c4ffcfe MK	205	}
1e9f8dcf	206
0c4ffcfe MK	207	if (temp) {
0c4ffcfe MK	208	*num_irqs = temp;
1e9f8dcf	209	return 0;
0c4ffcfe	210	}
1e9f8dcf MK	211
1e9f8dcf MK	212	return -EINVAL;
0c4ffcfe MK	213	}
	214
	215	static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie)
	216	{
	217	int i;
	218
	219	/* Legacy IRQ */
	220	for (i = 0; i < ks_pcie->num_legacy_host_irqs; i++) {
5168a73c TG	221	irq_set_chained_handler_and_data(ks_pcie->legacy_host_irqs[i],
	222	ks_pcie_legacy_irq_handler,
	223	ks_pcie);
0c4ffcfe MK	224	}
	225	ks_dw_pcie_enable_legacy_irqs(ks_pcie);
	226
	227	/* MSI IRQ */
	228	if (IS_ENABLED(CONFIG_PCI_MSI)) {
	229	for (i = 0; i < ks_pcie->num_msi_host_irqs; i++) {
2cf5a03c TG	230	irq_set_chained_handler_and_data(ks_pcie->msi_host_irqs[i],
	231	ks_pcie_msi_irq_handler,
	232	ks_pcie);
0c4ffcfe MK	233	}
0c4ffcfe MK	234	}
025dd3da MK	235
	236	if (ks_pcie->error_irq > 0)
	237	ks_dw_pcie_enable_error_irq(ks_pcie->va_app_base);
0c4ffcfe MK	238	}
	239
	240	/*
	241	* When a PCI device does not exist during config cycles, keystone host gets a
	242	* bus error instead of returning 0xffffffff. This handler always returns 0
	243	* for this kind of faults.
	244	*/
	245	static int keystone_pcie_fault(unsigned long addr, unsigned int fsr,
	246	struct pt_regs *regs)
	247	{
	248	unsigned long instr = (unsigned long ) instruction_pointer(regs);
	249
	250	if ((instr & 0x0e100090) == 0x00100090) {
	251	int reg = (instr >> 12) & 15;
	252
	253	regs->uregs[reg] = -1;
	254	regs->ARM_pc += 4;
	255	}
	256
	257	return 0;
	258	}
	259
	260	static void __init ks_pcie_host_init(struct pcie_port *pp)
	261	{
0c4ffcfe	262	struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
8665a482	263	u32 val;
0c4ffcfe MK	264
	265	ks_pcie_establish_link(ks_pcie);
	266	ks_dw_pcie_setup_rc_app_regs(ks_pcie);
	267	ks_pcie_setup_interrupts(ks_pcie);
	268	writew(PCI_IO_RANGE_TYPE_32 \| (PCI_IO_RANGE_TYPE_32 << 8),
	269	pp->dbi_base + PCI_IO_BASE);
	270
	271	/* update the Vendor ID */
8665a482	272	writew(ks_pcie->device_id, pp->dbi_base + PCI_DEVICE_ID);
0c4ffcfe MK	273
	274	/* update the DEV_STAT_CTRL to publish right mrrs */
	275	val = readl(pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
	276	val &= ~PCI_EXP_DEVCTL_READRQ;
	277	/* set the mrrs to 256 bytes */
	278	val \|= BIT(12);
	279	writel(val, pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
	280
	281	/*
	282	* PCIe access errors that result into OCP errors are caught by ARM as
	283	* "External aborts"
	284	*/
	285	hook_fault_code(17, keystone_pcie_fault, SIGBUS, 0,
	286	"Asynchronous external abort");
	287	}
	288
	289	static struct pcie_host_ops keystone_pcie_host_ops = {
	290	.rd_other_conf = ks_dw_pcie_rd_other_conf,
	291	.wr_other_conf = ks_dw_pcie_wr_other_conf,
	292	.link_up = ks_dw_pcie_link_up,
	293	.host_init = ks_pcie_host_init,
	294	.msi_set_irq = ks_dw_pcie_msi_set_irq,
	295	.msi_clear_irq = ks_dw_pcie_msi_clear_irq,
1104528b	296	.get_msi_addr = ks_dw_pcie_get_msi_addr,
0c4ffcfe MK	297	.msi_host_init = ks_dw_pcie_msi_host_init,
	298	.scan_bus = ks_dw_pcie_v3_65_scan_bus,
	299	};
	300
025dd3da MK	301	static irqreturn_t pcie_err_irq_handler(int irq, void *priv)
	302	{
	303	struct keystone_pcie *ks_pcie = priv;
	304
	305	return ks_dw_pcie_handle_error_irq(ks_pcie->pp.dev,
	306	ks_pcie->va_app_base);
	307	}
	308
0c4ffcfe MK	309	static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
	310	struct platform_device *pdev)
	311	{
	312	struct pcie_port *pp = &ks_pcie->pp;
	313	int ret;
	314
	315	ret = ks_pcie_get_irq_controller_info(ks_pcie,
	316	"legacy-interrupt-controller",
	317	&ks_pcie->num_legacy_host_irqs);
	318	if (ret)
	319	return ret;
	320
	321	if (IS_ENABLED(CONFIG_PCI_MSI)) {
	322	ret = ks_pcie_get_irq_controller_info(ks_pcie,
	323	"msi-interrupt-controller",
	324	&ks_pcie->num_msi_host_irqs);
	325	if (ret)
	326	return ret;
	327	}
	328
025dd3da MK	329	/*
	330	* Index 0 is the platform interrupt for error interrupt
	331	* from RC. This is optional.
	332	*/
	333	ks_pcie->error_irq = irq_of_parse_and_map(ks_pcie->np, 0);
	334	if (ks_pcie->error_irq <= 0)
	335	dev_info(&pdev->dev, "no error IRQ defined\n");
	336	else {
8116acce WY	337	ret = request_irq(ks_pcie->error_irq, pcie_err_irq_handler,
	338	IRQF_SHARED, "pcie-error-irq", ks_pcie);
	339	if (ret < 0) {
025dd3da MK	340	dev_err(&pdev->dev, "failed to request error IRQ %d\n",
	341	ks_pcie->error_irq);
	342	return ret;
	343	}
	344	}
	345
0c4ffcfe MK	346	pp->root_bus_nr = -1;
	347	pp->ops = &keystone_pcie_host_ops;
	348	ret = ks_dw_pcie_host_init(ks_pcie, ks_pcie->msi_intc_np);
	349	if (ret) {
	350	dev_err(&pdev->dev, "failed to initialize host\n");
	351	return ret;
	352	}
	353
1e9f8dcf	354	return 0;
0c4ffcfe MK	355	}
	356
	357	static const struct of_device_id ks_pcie_of_match[] = {
	358	{
	359	.type = "pci",
	360	.compatible = "ti,keystone-pcie",
	361	},
	362	{ },
	363	};
0c4ffcfe MK	364
	365	static int __exit ks_pcie_remove(struct platform_device *pdev)
	366	{
	367	struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev);
	368
	369	clk_disable_unprepare(ks_pcie->clk);
	370
	371	return 0;
	372	}
	373
	374	static int __init ks_pcie_probe(struct platform_device *pdev)
	375	{
	376	struct device *dev = &pdev->dev;
	377	struct keystone_pcie *ks_pcie;
	378	struct pcie_port *pp;
	379	struct resource *res;
	380	void __iomem *reg_p;
	381	struct phy *phy;
1e9f8dcf	382	int ret;
0c4ffcfe MK	383
	384	ks_pcie = devm_kzalloc(&pdev->dev, sizeof(*ks_pcie),
	385	GFP_KERNEL);
66700707	386	if (!ks_pcie)
0c4ffcfe	387	return -ENOMEM;
66700707	388
0c4ffcfe MK	389	pp = &ks_pcie->pp;
0c4ffcfe MK	390
0c4ffcfe MK	391	/* initialize SerDes Phy if present */
0c4ffcfe MK	392	phy = devm_phy_get(dev, "pcie-phy");
25de15c9 SL	393	if (PTR_ERR_OR_ZERO(phy) == -EPROBE_DEFER)
	394	return PTR_ERR(phy);
	395
0c4ffcfe MK	396	if (!IS_ERR_OR_NULL(phy)) {
	397	ret = phy_init(phy);
	398	if (ret < 0)
	399	return ret;
	400	}
	401
4455efc9 MK	402	/* index 2 is to read PCI DEVICE_ID */
4455efc9 MK	403	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
0c4ffcfe MK	404	reg_p = devm_ioremap_resource(dev, res);
	405	if (IS_ERR(reg_p))
	406	return PTR_ERR(reg_p);
8665a482 MK	407	ks_pcie->device_id = readl(reg_p) >> 16;
	408	devm_iounmap(dev, reg_p);
	409	devm_release_mem_region(dev, res->start, resource_size(res));
0c4ffcfe MK	410
0c4ffcfe MK	411	pp->dev = dev;
025dd3da	412	ks_pcie->np = dev->of_node;
0c4ffcfe MK	413	platform_set_drvdata(pdev, ks_pcie);
	414	ks_pcie->clk = devm_clk_get(dev, "pcie");
	415	if (IS_ERR(ks_pcie->clk)) {
	416	dev_err(dev, "Failed to get pcie rc clock\n");
	417	return PTR_ERR(ks_pcie->clk);
	418	}
	419	ret = clk_prepare_enable(ks_pcie->clk);
	420	if (ret)
	421	return ret;
	422
	423	ret = ks_add_pcie_port(ks_pcie, pdev);
	424	if (ret < 0)
	425	goto fail_clk;
	426
	427	return 0;
	428	fail_clk:
	429	clk_disable_unprepare(ks_pcie->clk);
	430
	431	return ret;
	432	}
	433
	434	static struct platform_driver ks_pcie_driver __refdata = {
	435	.probe = ks_pcie_probe,
	436	.remove = __exit_p(ks_pcie_remove),
	437	.driver = {
	438	.name = "keystone-pcie",
0c4ffcfe MK	439	.of_match_table = of_match_ptr(ks_pcie_of_match),
	440	},
	441	};
1481bf21	442	builtin_platform_driver(ks_pcie_driver);