[deliverable/linux.git] / drivers / pci / host / pcie-altera.c

/*
 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
 *
 * Author: Ley Foon Tan <lftan@altera.com>
 * Description: Altera PCIe host controller driver
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/init.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_pci.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#define RP_TX_REG0			0x2000
#define RP_TX_REG1			0x2004
#define RP_TX_CNTRL			0x2008
#define RP_TX_EOP			0x2
#define RP_TX_SOP			0x1
#define RP_RXCPL_STATUS			0x2010
#define RP_RXCPL_EOP			0x2
#define RP_RXCPL_SOP			0x1
#define RP_RXCPL_REG0			0x2014
#define RP_RXCPL_REG1			0x2018
#define P2A_INT_STATUS			0x3060
#define P2A_INT_STS_ALL			0xf
#define P2A_INT_ENABLE			0x3070
#define P2A_INT_ENA_ALL			0xf
#define RP_LTSSM			0x3c64
#define RP_LTSSM_MASK			0x1f
#define LTSSM_L0			0xf

/* TLP configuration type 0 and 1 */
#define TLP_FMTTYPE_CFGRD0		0x04	/* Configuration Read Type 0 */
#define TLP_FMTTYPE_CFGWR0		0x44	/* Configuration Write Type 0 */
#define TLP_FMTTYPE_CFGRD1		0x05	/* Configuration Read Type 1 */
#define TLP_FMTTYPE_CFGWR1		0x45	/* Configuration Write Type 1 */
#define TLP_PAYLOAD_SIZE		0x01
#define TLP_READ_TAG			0x1d
#define TLP_WRITE_TAG			0x10
#define TLP_CFG_DW0(fmttype)		(((fmttype) << 24) | TLP_PAYLOAD_SIZE)
#define TLP_CFG_DW1(reqid, tag, be)	(((reqid) << 16) | (tag << 8) | (be))
#define TLP_CFG_DW2(bus, devfn, offset)	\
				(((bus) << 24) | ((devfn) << 16) | (offset))
#define TLP_REQ_ID(bus, devfn)		(((bus) << 8) | (devfn))
#define TLP_COMP_STATUS(s)		(((s) >> 12) & 7)
#define TLP_HDR_SIZE			3
#define TLP_LOOP			500
#define RP_DEVFN			0

#define LINK_UP_TIMEOUT			5000

#define INTX_NUM			4

#define DWORD_MASK			3

struct altera_pcie {
	struct platform_device	*pdev;
	void __iomem		*cra_base;
	int			irq;
	u8			root_bus_nr;
	struct irq_domain	*irq_domain;
	struct resource		bus_range;
	struct list_head	resources;
};

struct tlp_rp_regpair_t {
	u32 ctrl;
	u32 reg0;
	u32 reg1;
};

static inline void cra_writel(struct altera_pcie *pcie, const u32 value,
			      const u32 reg)
{
	writel_relaxed(value, pcie->cra_base + reg);
}

static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
{
	return readl_relaxed(pcie->cra_base + reg);
}

static bool altera_pcie_link_is_up(struct altera_pcie *pcie)
{
	return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
}

static void altera_pcie_retrain(struct pci_dev *dev)
{
	u16 linkcap, linkstat;
	struct altera_pcie *pcie = dev->bus->sysdata;
	int timeout =  0;

	if (!altera_pcie_link_is_up(pcie))
		return;

	/*
	 * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
	 * current speed is 2.5 GB/s.
	 */
	pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap);

	if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
		return;

	pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &linkstat);
	if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
		pcie_capability_set_word(dev, PCI_EXP_LNKCTL,
					 PCI_EXP_LNKCTL_RL);
		while (!altera_pcie_link_is_up(pcie)) {
			timeout++;
			if (timeout > LINK_UP_TIMEOUT)
				break;
			udelay(5);
		}
	}
}
DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID, altera_pcie_retrain);

/*
 * Altera PCIe port uses BAR0 of RC's configuration space as the translation
 * from PCI bus to native BUS.  Entire DDR region is mapped into PCIe space
 * using these registers, so it can be reached by DMA from EP devices.
 * This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt
 * from EP devices, eventually trigger interrupt to GIC.  The BAR0 of bridge
 * should be hidden during enumeration to avoid the sizing and resource
 * allocation by PCIe core.
 */
static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int  devfn,
				    int offset)
{
	if (pci_is_root_bus(bus) && (devfn == 0) &&
	    (offset == PCI_BASE_ADDRESS_0))
		return true;

	return false;
}

static void tlp_write_tx(struct altera_pcie *pcie,
			 struct tlp_rp_regpair_t *tlp_rp_regdata)
{
	cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0);
	cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1);
	cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);
}

static bool altera_pcie_valid_config(struct altera_pcie *pcie,
				     struct pci_bus *bus, int dev)
{
	/* If there is no link, then there is no device */
	if (bus->number != pcie->root_bus_nr) {
		if (!altera_pcie_link_is_up(pcie))
			return false;
	}

	/* access only one slot on each root port */
	if (bus->number == pcie->root_bus_nr && dev > 0)
		return false;

	/*
	 * Do not read more than one device on the bus directly attached
	 * to root port, root port can only attach to one downstream port.
	 */
	if (bus->primary == pcie->root_bus_nr && dev > 0)
		return false;

	 return true;
}

static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
{
	int i;
	bool sop = 0;
	u32 ctrl;
	u32 reg0, reg1;
	u32 comp_status = 1;

	/*
	 * Minimum 2 loops to read TLP headers and 1 loop to read data
	 * payload.
	 */
	for (i = 0; i < TLP_LOOP; i++) {
		ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
		if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) {
			reg0 = cra_readl(pcie, RP_RXCPL_REG0);
			reg1 = cra_readl(pcie, RP_RXCPL_REG1);

			if (ctrl & RP_RXCPL_SOP) {
				sop = true;
				comp_status = TLP_COMP_STATUS(reg1);
			}

			if (ctrl & RP_RXCPL_EOP) {
				if (comp_status)
					return PCIBIOS_DEVICE_NOT_FOUND;

				if (value)
					*value = reg0;

				return PCIBIOS_SUCCESSFUL;
			}
		}
		udelay(5);
	}

	return PCIBIOS_DEVICE_NOT_FOUND;
}

static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers,
			     u32 data, bool align)
{
	struct tlp_rp_regpair_t tlp_rp_regdata;

	tlp_rp_regdata.reg0 = headers[0];
	tlp_rp_regdata.reg1 = headers[1];
	tlp_rp_regdata.ctrl = RP_TX_SOP;
	tlp_write_tx(pcie, &tlp_rp_regdata);

	if (align) {
		tlp_rp_regdata.reg0 = headers[2];
		tlp_rp_regdata.reg1 = 0;
		tlp_rp_regdata.ctrl = 0;
		tlp_write_tx(pcie, &tlp_rp_regdata);

		tlp_rp_regdata.reg0 = data;
		tlp_rp_regdata.reg1 = 0;
	} else {
		tlp_rp_regdata.reg0 = headers[2];
		tlp_rp_regdata.reg1 = data;
	}

	tlp_rp_regdata.ctrl = RP_TX_EOP;
	tlp_write_tx(pcie, &tlp_rp_regdata);
}

static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
			      int where, u8 byte_en, u32 *value)
{
	u32 headers[TLP_HDR_SIZE];

	if (bus == pcie->root_bus_nr)
		headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD0);
	else
		headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD1);

	headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN),
					TLP_READ_TAG, byte_en);
	headers[2] = TLP_CFG_DW2(bus, devfn, where);

	tlp_write_packet(pcie, headers, 0, false);

	return tlp_read_packet(pcie, value);
}

static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
			       int where, u8 byte_en, u32 value)
{
	u32 headers[TLP_HDR_SIZE];
	int ret;

	if (bus == pcie->root_bus_nr)
		headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR0);
	else
		headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR1);

	headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN),
					TLP_WRITE_TAG, byte_en);
	headers[2] = TLP_CFG_DW2(bus, devfn, where);

	/* check alignment to Qword */
	if ((where & 0x7) == 0)
		tlp_write_packet(pcie, headers, value, true);
	else
		tlp_write_packet(pcie, headers, value, false);

	ret = tlp_read_packet(pcie, NULL);
	if (ret != PCIBIOS_SUCCESSFUL)
		return ret;

	/*
	 * Monitor changes to PCI_PRIMARY_BUS register on root port
	 * and update local copy of root bus number accordingly.
	 */
	if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS))
		pcie->root_bus_nr = (u8)(value);

	return PCIBIOS_SUCCESSFUL;
}

static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
				int where, int size, u32 *value)
{
	struct altera_pcie *pcie = bus->sysdata;
	int ret;
	u32 data;
	u8 byte_en;

	if (altera_pcie_hide_rc_bar(bus, devfn, where))
		return PCIBIOS_BAD_REGISTER_NUMBER;

	if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn))) {
		*value = 0xffffffff;
		return PCIBIOS_DEVICE_NOT_FOUND;
	}

	switch (size) {
	case 1:
		byte_en = 1 << (where & 3);
		break;
	case 2:
		byte_en = 3 << (where & 3);
		break;
	default:
		byte_en = 0xf;
		break;
	}

	ret = tlp_cfg_dword_read(pcie, bus->number, devfn,
				 (where & ~DWORD_MASK), byte_en, &data);
	if (ret != PCIBIOS_SUCCESSFUL)
		return ret;

	switch (size) {
	case 1:
		*value = (data >> (8 * (where & 0x3))) & 0xff;
		break;
	case 2:
		*value = (data >> (8 * (where & 0x2))) & 0xffff;
		break;
	default:
		*value = data;
		break;
	}

	return PCIBIOS_SUCCESSFUL;
}

static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
				 int where, int size, u32 value)
{
	struct altera_pcie *pcie = bus->sysdata;
	u32 data32;
	u32 shift = 8 * (where & 3);
	u8 byte_en;

	if (altera_pcie_hide_rc_bar(bus, devfn, where))
		return PCIBIOS_BAD_REGISTER_NUMBER;

	if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn)))
		return PCIBIOS_DEVICE_NOT_FOUND;

	switch (size) {
	case 1:
		data32 = (value & 0xff) << shift;
		byte_en = 1 << (where & 3);
		break;
	case 2:
		data32 = (value & 0xffff) << shift;
		byte_en = 3 << (where & 3);
		break;
	default:
		data32 = value;
		byte_en = 0xf;
		break;
	}

	return tlp_cfg_dword_write(pcie, bus->number, devfn,
		(where & ~DWORD_MASK), byte_en, data32);
}

static struct pci_ops altera_pcie_ops = {
	.read = altera_pcie_cfg_read,
	.write = altera_pcie_cfg_write,
};

static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
				irq_hw_number_t hwirq)
{
	irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
	irq_set_chip_data(irq, domain->host_data);

	return 0;
}

static const struct irq_domain_ops intx_domain_ops = {
	.map = altera_pcie_intx_map,
};

static void altera_pcie_isr(struct irq_desc *desc)
{
	struct irq_chip *chip = irq_desc_get_chip(desc);
	struct altera_pcie *pcie;
	unsigned long status;
	u32 bit;
	u32 virq;

	chained_irq_enter(chip, desc);
	pcie = irq_desc_get_handler_data(desc);

	while ((status = cra_readl(pcie, P2A_INT_STATUS)
		& P2A_INT_STS_ALL) != 0) {
		for_each_set_bit(bit, &status, INTX_NUM) {
			/* clear interrupts */
			cra_writel(pcie, 1 << bit, P2A_INT_STATUS);

			virq = irq_find_mapping(pcie->irq_domain, bit + 1);
			if (virq)
				generic_handle_irq(virq);
			else
				dev_err(&pcie->pdev->dev,
					"unexpected IRQ, INT%d\n", bit);
		}
	}

	chained_irq_exit(chip, desc);
}

static int altera_pcie_parse_request_of_pci_ranges(struct altera_pcie *pcie)
{
	int err, res_valid = 0;
	struct device *dev = &pcie->pdev->dev;
	struct device_node *np = dev->of_node;
	struct resource_entry *win;

	err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pcie->resources,
					       NULL);
	if (err)
		return err;

	err = devm_request_pci_bus_resources(dev, &pcie->resources);
	if (err)
		goto out_release_res;

	resource_list_for_each_entry(win, &pcie->resources) {
		struct resource *res = win->res;

		if (resource_type(res) == IORESOURCE_MEM)
			res_valid |= !(res->flags & IORESOURCE_PREFETCH);
	}

	if (res_valid)
		return 0;

	dev_err(dev, "non-prefetchable memory resource required\n");
	err = -EINVAL;

out_release_res:
	pci_free_resource_list(&pcie->resources);
	return err;
}

static int altera_pcie_init_irq_domain(struct altera_pcie *pcie)
{
	struct device *dev = &pcie->pdev->dev;
	struct device_node *node = dev->of_node;

	/* Setup INTx */
	pcie->irq_domain = irq_domain_add_linear(node, INTX_NUM + 1,
					&intx_domain_ops, pcie);
	if (!pcie->irq_domain) {
		dev_err(dev, "Failed to get a INTx IRQ domain\n");
		return -ENOMEM;
	}

	return 0;
}

static int altera_pcie_parse_dt(struct altera_pcie *pcie)
{
	struct resource *cra;
	struct platform_device *pdev = pcie->pdev;

	cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra");
	if (!cra) {
		dev_err(&pdev->dev, "no Cra memory resource defined\n");
		return -ENODEV;
	}

	pcie->cra_base = devm_ioremap_resource(&pdev->dev, cra);
	if (IS_ERR(pcie->cra_base)) {
		dev_err(&pdev->dev, "failed to map cra memory\n");
		return PTR_ERR(pcie->cra_base);
	}

	/* setup IRQ */
	pcie->irq = platform_get_irq(pdev, 0);
	if (pcie->irq <= 0) {
		dev_err(&pdev->dev, "failed to get IRQ: %d\n", pcie->irq);
		return -EINVAL;
	}

	irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie);

	return 0;
}

static int altera_pcie_probe(struct platform_device *pdev)
{
	struct altera_pcie *pcie;
	struct pci_bus *bus;
	struct pci_bus *child;
	int ret;

	pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
	if (!pcie)
		return -ENOMEM;

	pcie->pdev = pdev;

	ret = altera_pcie_parse_dt(pcie);
	if (ret) {
		dev_err(&pdev->dev, "Parsing DT failed\n");
		return ret;
	}

	INIT_LIST_HEAD(&pcie->resources);

	ret = altera_pcie_parse_request_of_pci_ranges(pcie);
	if (ret) {
		dev_err(&pdev->dev, "Failed add resources\n");
		return ret;
	}

	ret = altera_pcie_init_irq_domain(pcie);
	if (ret) {
		dev_err(&pdev->dev, "Failed creating IRQ Domain\n");
		return ret;
	}

	/* clear all interrupts */
	cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
	/* enable all interrupts */
	cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);

	bus = pci_scan_root_bus(&pdev->dev, pcie->root_bus_nr, &altera_pcie_ops,
				pcie, &pcie->resources);
	if (!bus)
		return -ENOMEM;

	pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
	pci_assign_unassigned_bus_resources(bus);

	/* Configure PCI Express setting. */
	list_for_each_entry(child, &bus->children, node)
		pcie_bus_configure_settings(child);

	pci_bus_add_devices(bus);

	platform_set_drvdata(pdev, pcie);
	return ret;
}

static const struct of_device_id altera_pcie_of_match[] = {
	{ .compatible = "altr,pcie-root-port-1.0", },
	{},
};

static struct platform_driver altera_pcie_driver = {
	.probe		= altera_pcie_probe,
	.driver = {
		.name	= "altera-pcie",
		.of_match_table = altera_pcie_of_match,
		.suppress_bind_attrs = true,
	},
};

static int altera_pcie_init(void)
{
	return platform_driver_register(&altera_pcie_driver);
}
device_initcall(altera_pcie_init);
Commit	Line	Data
eaa6111b LFT	1	/*
	2	* Copyright Altera Corporation (C) 2013-2015. All rights reserved
	3	*
bb9b54ca PG	4	* Author: Ley Foon Tan <lftan@altera.com>
	5	* Description: Altera PCIe host controller driver
	6	*
eaa6111b LFT	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include <linux/delay.h>
	21	#include <linux/interrupt.h>
	22	#include <linux/irqchip/chained_irq.h>
bb9b54ca	23	#include <linux/init.h>
eaa6111b LFT	24	#include <linux/of_address.h>
	25	#include <linux/of_irq.h>
	26	#include <linux/of_pci.h>
	27	#include <linux/pci.h>
	28	#include <linux/platform_device.h>
	29	#include <linux/slab.h>
	30
	31	#define RP_TX_REG0 0x2000
	32	#define RP_TX_REG1 0x2004
	33	#define RP_TX_CNTRL 0x2008
	34	#define RP_TX_EOP 0x2
	35	#define RP_TX_SOP 0x1
	36	#define RP_RXCPL_STATUS 0x2010
	37	#define RP_RXCPL_EOP 0x2
	38	#define RP_RXCPL_SOP 0x1
	39	#define RP_RXCPL_REG0 0x2014
	40	#define RP_RXCPL_REG1 0x2018
	41	#define P2A_INT_STATUS 0x3060
	42	#define P2A_INT_STS_ALL 0xf
	43	#define P2A_INT_ENABLE 0x3070
	44	#define P2A_INT_ENA_ALL 0xf
	45	#define RP_LTSSM 0x3c64
eff31f40	46	#define RP_LTSSM_MASK 0x1f
eaa6111b LFT	47	#define LTSSM_L0 0xf
	48
	49	/* TLP configuration type 0 and 1 */
	50	#define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */
	51	#define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */
	52	#define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */
	53	#define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */
	54	#define TLP_PAYLOAD_SIZE 0x01
	55	#define TLP_READ_TAG 0x1d
	56	#define TLP_WRITE_TAG 0x10
	57	#define TLP_CFG_DW0(fmttype) (((fmttype) << 24) \| TLP_PAYLOAD_SIZE)
	58	#define TLP_CFG_DW1(reqid, tag, be) (((reqid) << 16) \| (tag << 8) \| (be))
	59	#define TLP_CFG_DW2(bus, devfn, offset) \
	60	(((bus) << 24) \| ((devfn) << 16) \| (offset))
	61	#define TLP_REQ_ID(bus, devfn) (((bus) << 8) \| (devfn))
ea1d3795	62	#define TLP_COMP_STATUS(s) (((s) >> 12) & 7)
eaa6111b LFT	63	#define TLP_HDR_SIZE 3
eaa6111b LFT	64	#define TLP_LOOP 500
23ec5670	65	#define RP_DEVFN 0
eaa6111b	66
3a928e98 LFT	67	#define LINK_UP_TIMEOUT 5000
3a928e98 LFT	68
eaa6111b LFT	69	#define INTX_NUM 4
	70
	71	#define DWORD_MASK 3
	72
	73	struct altera_pcie {
	74	struct platform_device *pdev;
	75	void __iomem *cra_base;
	76	int irq;
	77	u8 root_bus_nr;
	78	struct irq_domain *irq_domain;
	79	struct resource bus_range;
	80	struct list_head resources;
	81	};
	82
	83	struct tlp_rp_regpair_t {
	84	u32 ctrl;
	85	u32 reg0;
	86	u32 reg1;
	87	};
	88
f8be11ae BH	89	static inline void cra_writel(struct altera_pcie *pcie, const u32 value,
	90	const u32 reg)
	91	{
	92	writel_relaxed(value, pcie->cra_base + reg);
	93	}
	94
	95	static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
	96	{
	97	return readl_relaxed(pcie->cra_base + reg);
	98	}
	99
	100	static bool altera_pcie_link_is_up(struct altera_pcie *pcie)
	101	{
	102	return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
	103	}
	104
eaa6111b LFT	105	static void altera_pcie_retrain(struct pci_dev *dev)
	106	{
	107	u16 linkcap, linkstat;
c622032e	108	struct altera_pcie *pcie = dev->bus->sysdata;
3a928e98	109	int timeout = 0;
c622032e LFT	110
	111	if (!altera_pcie_link_is_up(pcie))
	112	return;
eaa6111b LFT	113
	114	/*
	115	* Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
	116	* current speed is 2.5 GB/s.
	117	*/
	118	pcie_capability_read_word(dev, PCI_EXP_LNKCAP, &linkcap);
	119
	120	if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)
	121	return;
	122
	123	pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &linkstat);
3a928e98	124	if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
eaa6111b LFT	125	pcie_capability_set_word(dev, PCI_EXP_LNKCTL,
eaa6111b LFT	126	PCI_EXP_LNKCTL_RL);
3a928e98 LFT	127	while (!altera_pcie_link_is_up(pcie)) {
	128	timeout++;
	129	if (timeout > LINK_UP_TIMEOUT)
	130	break;
	131	udelay(5);
	132	}
	133	}
eaa6111b LFT	134	}
	135	DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID, altera_pcie_retrain);
	136
	137	/*
	138	* Altera PCIe port uses BAR0 of RC's configuration space as the translation
	139	* from PCI bus to native BUS. Entire DDR region is mapped into PCIe space
	140	* using these registers, so it can be reached by DMA from EP devices.
	141	* This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt
	142	* from EP devices, eventually trigger interrupt to GIC. The BAR0 of bridge
	143	* should be hidden during enumeration to avoid the sizing and resource
	144	* allocation by PCIe core.
	145	*/
	146	static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn,
	147	int offset)
	148	{
	149	if (pci_is_root_bus(bus) && (devfn == 0) &&
	150	(offset == PCI_BASE_ADDRESS_0))
	151	return true;
	152
	153	return false;
	154	}
	155
eaa6111b LFT	156	static void tlp_write_tx(struct altera_pcie *pcie,
	157	struct tlp_rp_regpair_t *tlp_rp_regdata)
	158	{
	159	cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0);
	160	cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1);
	161	cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);
	162	}
	163
eaa6111b LFT	164	static bool altera_pcie_valid_config(struct altera_pcie *pcie,
	165	struct pci_bus *bus, int dev)
	166	{
	167	/* If there is no link, then there is no device */
	168	if (bus->number != pcie->root_bus_nr) {
	169	if (!altera_pcie_link_is_up(pcie))
	170	return false;
	171	}
	172
	173	/* access only one slot on each root port */
	174	if (bus->number == pcie->root_bus_nr && dev > 0)
	175	return false;
	176
	177	/*
	178	* Do not read more than one device on the bus directly attached
	179	* to root port, root port can only attach to one downstream port.
	180	*/
	181	if (bus->primary == pcie->root_bus_nr && dev > 0)
	182	return false;
	183
	184	return true;
	185	}
	186
	187	static int tlp_read_packet(struct altera_pcie pcie, u32 value)
	188	{
7f52f314	189	int i;
eaa6111b LFT	190	bool sop = 0;
	191	u32 ctrl;
	192	u32 reg0, reg1;
ea1d3795	193	u32 comp_status = 1;
eaa6111b LFT	194
	195	/*
	196	* Minimum 2 loops to read TLP headers and 1 loop to read data
	197	* payload.
	198	*/
7f52f314	199	for (i = 0; i < TLP_LOOP; i++) {
eaa6111b LFT	200	ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
	201	if ((ctrl & RP_RXCPL_SOP) \|\| (ctrl & RP_RXCPL_EOP) \|\| sop) {
	202	reg0 = cra_readl(pcie, RP_RXCPL_REG0);
	203	reg1 = cra_readl(pcie, RP_RXCPL_REG1);
	204
ea1d3795	205	if (ctrl & RP_RXCPL_SOP) {
eaa6111b	206	sop = true;
ea1d3795 LFT	207	comp_status = TLP_COMP_STATUS(reg1);
ea1d3795 LFT	208	}
eaa6111b LFT	209
eaa6111b LFT	210	if (ctrl & RP_RXCPL_EOP) {
ea1d3795 LFT	211	if (comp_status)
	212	return PCIBIOS_DEVICE_NOT_FOUND;
	213
eaa6111b LFT	214	if (value)
eaa6111b LFT	215	*value = reg0;
ea1d3795	216
eaa6111b LFT	217	return PCIBIOS_SUCCESSFUL;
	218	}
	219	}
	220	udelay(5);
	221	}
	222
ea1d3795	223	return PCIBIOS_DEVICE_NOT_FOUND;
eaa6111b LFT	224	}
	225
	226	static void tlp_write_packet(struct altera_pcie pcie, u32 headers,
	227	u32 data, bool align)
	228	{
	229	struct tlp_rp_regpair_t tlp_rp_regdata;
	230
	231	tlp_rp_regdata.reg0 = headers[0];
	232	tlp_rp_regdata.reg1 = headers[1];
	233	tlp_rp_regdata.ctrl = RP_TX_SOP;
	234	tlp_write_tx(pcie, &tlp_rp_regdata);
	235
	236	if (align) {
	237	tlp_rp_regdata.reg0 = headers[2];
	238	tlp_rp_regdata.reg1 = 0;
	239	tlp_rp_regdata.ctrl = 0;
	240	tlp_write_tx(pcie, &tlp_rp_regdata);
	241
	242	tlp_rp_regdata.reg0 = data;
	243	tlp_rp_regdata.reg1 = 0;
	244	} else {
	245	tlp_rp_regdata.reg0 = headers[2];
	246	tlp_rp_regdata.reg1 = data;
	247	}
	248
	249	tlp_rp_regdata.ctrl = RP_TX_EOP;
	250	tlp_write_tx(pcie, &tlp_rp_regdata);
	251	}
	252
	253	static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,
	254	int where, u8 byte_en, u32 *value)
	255	{
	256	u32 headers[TLP_HDR_SIZE];
	257
	258	if (bus == pcie->root_bus_nr)
	259	headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD0);
	260	else
	261	headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGRD1);
	262
23ec5670	263	headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN),
eaa6111b LFT	264	TLP_READ_TAG, byte_en);
	265	headers[2] = TLP_CFG_DW2(bus, devfn, where);
	266
	267	tlp_write_packet(pcie, headers, 0, false);
	268
	269	return tlp_read_packet(pcie, value);
	270	}
	271
	272	static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,
	273	int where, u8 byte_en, u32 value)
	274	{
	275	u32 headers[TLP_HDR_SIZE];
	276	int ret;
	277
	278	if (bus == pcie->root_bus_nr)
	279	headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR0);
	280	else
	281	headers[0] = TLP_CFG_DW0(TLP_FMTTYPE_CFGWR1);
	282
23ec5670	283	headers[1] = TLP_CFG_DW1(TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN),
eaa6111b LFT	284	TLP_WRITE_TAG, byte_en);
	285	headers[2] = TLP_CFG_DW2(bus, devfn, where);
	286
	287	/* check alignment to Qword */
	288	if ((where & 0x7) == 0)
	289	tlp_write_packet(pcie, headers, value, true);
	290	else
	291	tlp_write_packet(pcie, headers, value, false);
	292
	293	ret = tlp_read_packet(pcie, NULL);
	294	if (ret != PCIBIOS_SUCCESSFUL)
	295	return ret;
	296
	297	/*
	298	* Monitor changes to PCI_PRIMARY_BUS register on root port
	299	* and update local copy of root bus number accordingly.
	300	*/
	301	if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS))
	302	pcie->root_bus_nr = (u8)(value);
	303
	304	return PCIBIOS_SUCCESSFUL;
	305	}
	306
	307	static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,
	308	int where, int size, u32 *value)
	309	{
	310	struct altera_pcie *pcie = bus->sysdata;
	311	int ret;
	312	u32 data;
	313	u8 byte_en;
	314
	315	if (altera_pcie_hide_rc_bar(bus, devfn, where))
	316	return PCIBIOS_BAD_REGISTER_NUMBER;
	317
	318	if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn))) {
	319	*value = 0xffffffff;
	320	return PCIBIOS_DEVICE_NOT_FOUND;
	321	}
	322
	323	switch (size) {
	324	case 1:
	325	byte_en = 1 << (where & 3);
	326	break;
	327	case 2:
	328	byte_en = 3 << (where & 3);
	329	break;
	330	default:
	331	byte_en = 0xf;
	332	break;
	333	}
	334
	335	ret = tlp_cfg_dword_read(pcie, bus->number, devfn,
	336	(where & ~DWORD_MASK), byte_en, &data);
	337	if (ret != PCIBIOS_SUCCESSFUL)
	338	return ret;
	339
	340	switch (size) {
	341	case 1:
	342	value = (data >> (8 (where & 0x3))) & 0xff;
	343	break;
	344	case 2:
	345	value = (data >> (8 (where & 0x2))) & 0xffff;
	346	break;
	347	default:
348	*value = data;
349	break;
350	}
351
352	return PCIBIOS_SUCCESSFUL;
353	}
354
355	static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,
356	int where, int size, u32 value)
357	{
358	struct altera_pcie *pcie = bus->sysdata;
359	u32 data32;
360	u32 shift = 8 * (where & 3);
361	u8 byte_en;
362
363	if (altera_pcie_hide_rc_bar(bus, devfn, where))
364	return PCIBIOS_BAD_REGISTER_NUMBER;
365
366	if (!altera_pcie_valid_config(pcie, bus, PCI_SLOT(devfn)))
367	return PCIBIOS_DEVICE_NOT_FOUND;
368
369	switch (size) {
370	case 1:
371	data32 = (value & 0xff) << shift;
372	byte_en = 1 << (where & 3);
373	break;
374	case 2:
375	data32 = (value & 0xffff) << shift;
376	byte_en = 3 << (where & 3);
377	break;
378	default:
379	data32 = value;
380	byte_en = 0xf;
381	break;
382	}
383
384	return tlp_cfg_dword_write(pcie, bus->number, devfn,
385	(where & ~DWORD_MASK), byte_en, data32);
386	}
387
388	static struct pci_ops altera_pcie_ops = {
389	.read = altera_pcie_cfg_read,
390	.write = altera_pcie_cfg_write,
391	};
392
393	static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
394	irq_hw_number_t hwirq)
395	{
396	irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
397	irq_set_chip_data(irq, domain->host_data);
398
399	return 0;
400	}
401
402	static const struct irq_domain_ops intx_domain_ops = {
403	.map = altera_pcie_intx_map,
404	};
405
406	static void altera_pcie_isr(struct irq_desc *desc)
407	{
408	struct irq_chip *chip = irq_desc_get_chip(desc);
409	struct altera_pcie *pcie;
410	unsigned long status;
411	u32 bit;
412	u32 virq;
413
414	chained_irq_enter(chip, desc);
415	pcie = irq_desc_get_handler_data(desc);
416
417	while ((status = cra_readl(pcie, P2A_INT_STATUS)
418	& P2A_INT_STS_ALL) != 0) {
419	for_each_set_bit(bit, &status, INTX_NUM) {
420	/* clear interrupts */
421	cra_writel(pcie, 1 << bit, P2A_INT_STATUS);
422
423	virq = irq_find_mapping(pcie->irq_domain, bit + 1);
424	if (virq)
425	generic_handle_irq(virq);
426	else
427	dev_err(&pcie->pdev->dev,
428	"unexpected IRQ, INT%d\n", bit);
429	}
430	}
431
432	chained_irq_exit(chip, desc);
433	}
434
eaa6111b LFT	435	static int altera_pcie_parse_request_of_pci_ranges(struct altera_pcie *pcie)
	436	{
	437	int err, res_valid = 0;
	438	struct device *dev = &pcie->pdev->dev;
	439	struct device_node *np = dev->of_node;
	440	struct resource_entry *win;
	441
	442	err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pcie->resources,
	443	NULL);
	444	if (err)
	445	return err;
	446
74462284 BH	447	err = devm_request_pci_bus_resources(dev, &pcie->resources);
	448	if (err)
	449	goto out_release_res;
	450
eaa6111b	451	resource_list_for_each_entry(win, &pcie->resources) {
74462284	452	struct resource *res = win->res;
eaa6111b	453
ba4f6d92	454	if (resource_type(res) == IORESOURCE_MEM)
eaa6111b	455	res_valid \|= !(res->flags & IORESOURCE_PREFETCH);
eaa6111b LFT	456	}
eaa6111b LFT	457
ba4f6d92 BH	458	if (res_valid)
ba4f6d92 BH	459	return 0;
eaa6111b	460
ba4f6d92 BH	461	dev_err(dev, "non-prefetchable memory resource required\n");
ba4f6d92 BH	462	err = -EINVAL;
eaa6111b LFT	463
eaa6111b LFT	464	out_release_res:
ba4f6d92	465	pci_free_resource_list(&pcie->resources);
eaa6111b LFT	466	return err;
	467	}
	468
	469	static int altera_pcie_init_irq_domain(struct altera_pcie *pcie)
	470	{
	471	struct device *dev = &pcie->pdev->dev;
	472	struct device_node *node = dev->of_node;
	473
	474	/* Setup INTx */
99496bd2	475	pcie->irq_domain = irq_domain_add_linear(node, INTX_NUM + 1,
eaa6111b LFT	476	&intx_domain_ops, pcie);
	477	if (!pcie->irq_domain) {
	478	dev_err(dev, "Failed to get a INTx IRQ domain\n");
	479	return -ENOMEM;
	480	}
	481
	482	return 0;
	483	}
	484
	485	static int altera_pcie_parse_dt(struct altera_pcie *pcie)
	486	{
	487	struct resource *cra;
	488	struct platform_device *pdev = pcie->pdev;
	489
	490	cra = platform_get_resource_byname(pdev, IORESOURCE_MEM, "Cra");
	491	if (!cra) {
	492	dev_err(&pdev->dev, "no Cra memory resource defined\n");
	493	return -ENODEV;
	494	}
	495
	496	pcie->cra_base = devm_ioremap_resource(&pdev->dev, cra);
	497	if (IS_ERR(pcie->cra_base)) {
	498	dev_err(&pdev->dev, "failed to map cra memory\n");
	499	return PTR_ERR(pcie->cra_base);
	500	}
	501
	502	/* setup IRQ */
	503	pcie->irq = platform_get_irq(pdev, 0);
	504	if (pcie->irq <= 0) {
	505	dev_err(&pdev->dev, "failed to get IRQ: %d\n", pcie->irq);
	506	return -EINVAL;
	507	}
	508
	509	irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie);
	510
	511	return 0;
	512	}
	513
	514	static int altera_pcie_probe(struct platform_device *pdev)
	515	{
	516	struct altera_pcie *pcie;
	517	struct pci_bus *bus;
	518	struct pci_bus *child;
	519	int ret;
	520
	521	pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
	522	if (!pcie)
	523	return -ENOMEM;
	524
	525	pcie->pdev = pdev;
	526
	527	ret = altera_pcie_parse_dt(pcie);
	528	if (ret) {
	529	dev_err(&pdev->dev, "Parsing DT failed\n");
	530	return ret;
	531	}
	532
	533	INIT_LIST_HEAD(&pcie->resources);
	534
	535	ret = altera_pcie_parse_request_of_pci_ranges(pcie);
	536	if (ret) {
	537	dev_err(&pdev->dev, "Failed add resources\n");
	538	return ret;
	539	}
540
541	ret = altera_pcie_init_irq_domain(pcie);
542	if (ret) {
543	dev_err(&pdev->dev, "Failed creating IRQ Domain\n");
544	return ret;
545	}
546
547	/* clear all interrupts */
548	cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);
549	/* enable all interrupts */
550	cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);
551
552	bus = pci_scan_root_bus(&pdev->dev, pcie->root_bus_nr, &altera_pcie_ops,
553	pcie, &pcie->resources);
554	if (!bus)
555	return -ENOMEM;
556
557	pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
558	pci_assign_unassigned_bus_resources(bus);
559
560	/* Configure PCI Express setting. */
561	list_for_each_entry(child, &bus->children, node)
562	pcie_bus_configure_settings(child);
563
564	pci_bus_add_devices(bus);
565
566	platform_set_drvdata(pdev, pcie);
567	return ret;
568	}
569
570	static const struct of_device_id altera_pcie_of_match[] = {
571	{ .compatible = "altr,pcie-root-port-1.0", },
572	{},
573	};
eaa6111b LFT	574
	575	static struct platform_driver altera_pcie_driver = {
	576	.probe = altera_pcie_probe,
	577	.driver = {
	578	.name = "altera-pcie",
	579	.of_match_table = altera_pcie_of_match,
	580	.suppress_bind_attrs = true,
	581	},
	582	};
	583
	584	static int altera_pcie_init(void)
	585	{
	586	return platform_driver_register(&altera_pcie_driver);
	587	}
bb9b54ca	588	device_initcall(altera_pcie_init);