Commit | Line | Data |
---|---|---|
340cba60 | 1 | /* |
4b1ced84 | 2 | * Synopsys Designware PCIe host controller driver |
340cba60 JH |
3 | * |
4 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * Author: Jingoo Han <jg1.han@samsung.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
f342d940 JH |
14 | #include <linux/irq.h> |
15 | #include <linux/irqdomain.h> | |
340cba60 | 16 | #include <linux/kernel.h> |
f342d940 | 17 | #include <linux/msi.h> |
340cba60 | 18 | #include <linux/of_address.h> |
804f57b1 | 19 | #include <linux/of_pci.h> |
340cba60 JH |
20 | #include <linux/pci.h> |
21 | #include <linux/pci_regs.h> | |
4dd964df | 22 | #include <linux/platform_device.h> |
340cba60 | 23 | #include <linux/types.h> |
886bc5ce | 24 | #include <linux/delay.h> |
340cba60 | 25 | |
4b1ced84 | 26 | #include "pcie-designware.h" |
340cba60 JH |
27 | |
28 | /* Synopsis specific PCIE configuration registers */ | |
29 | #define PCIE_PORT_LINK_CONTROL 0x710 | |
30 | #define PORT_LINK_MODE_MASK (0x3f << 16) | |
4b1ced84 JH |
31 | #define PORT_LINK_MODE_1_LANES (0x1 << 16) |
32 | #define PORT_LINK_MODE_2_LANES (0x3 << 16) | |
340cba60 | 33 | #define PORT_LINK_MODE_4_LANES (0x7 << 16) |
5b0f0738 | 34 | #define PORT_LINK_MODE_8_LANES (0xf << 16) |
340cba60 JH |
35 | |
36 | #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C | |
37 | #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) | |
ed8b472d | 38 | #define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8) |
4b1ced84 JH |
39 | #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) |
40 | #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) | |
41 | #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) | |
5b0f0738 | 42 | #define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8) |
340cba60 JH |
43 | |
44 | #define PCIE_MSI_ADDR_LO 0x820 | |
45 | #define PCIE_MSI_ADDR_HI 0x824 | |
46 | #define PCIE_MSI_INTR0_ENABLE 0x828 | |
47 | #define PCIE_MSI_INTR0_MASK 0x82C | |
48 | #define PCIE_MSI_INTR0_STATUS 0x830 | |
49 | ||
50 | #define PCIE_ATU_VIEWPORT 0x900 | |
51 | #define PCIE_ATU_REGION_INBOUND (0x1 << 31) | |
52 | #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) | |
53 | #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) | |
54 | #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) | |
55 | #define PCIE_ATU_CR1 0x904 | |
56 | #define PCIE_ATU_TYPE_MEM (0x0 << 0) | |
57 | #define PCIE_ATU_TYPE_IO (0x2 << 0) | |
58 | #define PCIE_ATU_TYPE_CFG0 (0x4 << 0) | |
59 | #define PCIE_ATU_TYPE_CFG1 (0x5 << 0) | |
60 | #define PCIE_ATU_CR2 0x908 | |
61 | #define PCIE_ATU_ENABLE (0x1 << 31) | |
62 | #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30) | |
63 | #define PCIE_ATU_LOWER_BASE 0x90C | |
64 | #define PCIE_ATU_UPPER_BASE 0x910 | |
65 | #define PCIE_ATU_LIMIT 0x914 | |
66 | #define PCIE_ATU_LOWER_TARGET 0x918 | |
67 | #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24) | |
68 | #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19) | |
69 | #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) | |
70 | #define PCIE_ATU_UPPER_TARGET 0x91C | |
71 | ||
dac29e6c JP |
72 | /* PCIe Port Logic registers */ |
73 | #define PLR_OFFSET 0x700 | |
74 | #define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c) | |
75 | #define PCIE_PHY_DEBUG_R1_LINK_UP 0x00000010 | |
76 | ||
cbce7900 | 77 | static struct pci_ops dw_pcie_ops; |
340cba60 | 78 | |
4c45852f | 79 | int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val) |
340cba60 | 80 | { |
b6b18f58 GP |
81 | if ((uintptr_t)addr & (size - 1)) { |
82 | *val = 0; | |
83 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
84 | } | |
85 | ||
c003ca99 GP |
86 | if (size == 4) |
87 | *val = readl(addr); | |
340cba60 | 88 | else if (size == 2) |
4c45852f | 89 | *val = readw(addr); |
c003ca99 | 90 | else if (size == 1) |
4c45852f | 91 | *val = readb(addr); |
c003ca99 GP |
92 | else { |
93 | *val = 0; | |
340cba60 | 94 | return PCIBIOS_BAD_REGISTER_NUMBER; |
c003ca99 | 95 | } |
340cba60 JH |
96 | |
97 | return PCIBIOS_SUCCESSFUL; | |
98 | } | |
99 | ||
4c45852f | 100 | int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val) |
340cba60 | 101 | { |
b6b18f58 GP |
102 | if ((uintptr_t)addr & (size - 1)) |
103 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
104 | ||
340cba60 JH |
105 | if (size == 4) |
106 | writel(val, addr); | |
107 | else if (size == 2) | |
4c45852f | 108 | writew(val, addr); |
340cba60 | 109 | else if (size == 1) |
4c45852f | 110 | writeb(val, addr); |
340cba60 JH |
111 | else |
112 | return PCIBIOS_BAD_REGISTER_NUMBER; | |
113 | ||
114 | return PCIBIOS_SUCCESSFUL; | |
115 | } | |
116 | ||
f7b7868c | 117 | static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val) |
340cba60 | 118 | { |
4b1ced84 | 119 | if (pp->ops->readl_rc) |
f7b7868c | 120 | pp->ops->readl_rc(pp, pp->dbi_base + reg, val); |
4b1ced84 | 121 | else |
f7b7868c | 122 | *val = readl(pp->dbi_base + reg); |
340cba60 JH |
123 | } |
124 | ||
f7b7868c | 125 | static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg) |
340cba60 | 126 | { |
4b1ced84 | 127 | if (pp->ops->writel_rc) |
f7b7868c | 128 | pp->ops->writel_rc(pp, val, pp->dbi_base + reg); |
4b1ced84 | 129 | else |
f7b7868c | 130 | writel(val, pp->dbi_base + reg); |
340cba60 JH |
131 | } |
132 | ||
73e40850 BH |
133 | static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, |
134 | u32 *val) | |
340cba60 | 135 | { |
4b1ced84 | 136 | if (pp->ops->rd_own_conf) |
116a489d | 137 | return pp->ops->rd_own_conf(pp, where, size, val); |
4b1ced84 | 138 | |
116a489d | 139 | return dw_pcie_cfg_read(pp->dbi_base + where, size, val); |
340cba60 JH |
140 | } |
141 | ||
73e40850 BH |
142 | static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, |
143 | u32 val) | |
340cba60 | 144 | { |
4b1ced84 | 145 | if (pp->ops->wr_own_conf) |
116a489d | 146 | return pp->ops->wr_own_conf(pp, where, size, val); |
4b1ced84 | 147 | |
116a489d | 148 | return dw_pcie_cfg_write(pp->dbi_base + where, size, val); |
340cba60 JH |
149 | } |
150 | ||
63503c87 JZ |
151 | static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index, |
152 | int type, u64 cpu_addr, u64 pci_addr, u32 size) | |
153 | { | |
17209dfb SV |
154 | u32 val; |
155 | ||
63503c87 JZ |
156 | dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | index, |
157 | PCIE_ATU_VIEWPORT); | |
158 | dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr), PCIE_ATU_LOWER_BASE); | |
159 | dw_pcie_writel_rc(pp, upper_32_bits(cpu_addr), PCIE_ATU_UPPER_BASE); | |
160 | dw_pcie_writel_rc(pp, lower_32_bits(cpu_addr + size - 1), | |
161 | PCIE_ATU_LIMIT); | |
162 | dw_pcie_writel_rc(pp, lower_32_bits(pci_addr), PCIE_ATU_LOWER_TARGET); | |
163 | dw_pcie_writel_rc(pp, upper_32_bits(pci_addr), PCIE_ATU_UPPER_TARGET); | |
164 | dw_pcie_writel_rc(pp, type, PCIE_ATU_CR1); | |
165 | dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); | |
17209dfb SV |
166 | |
167 | /* | |
168 | * Make sure ATU enable takes effect before any subsequent config | |
169 | * and I/O accesses. | |
170 | */ | |
171 | dw_pcie_readl_rc(pp, PCIE_ATU_CR2, &val); | |
63503c87 JZ |
172 | } |
173 | ||
f342d940 JH |
174 | static struct irq_chip dw_msi_irq_chip = { |
175 | .name = "PCI-MSI", | |
280510f1 TG |
176 | .irq_enable = pci_msi_unmask_irq, |
177 | .irq_disable = pci_msi_mask_irq, | |
178 | .irq_mask = pci_msi_mask_irq, | |
179 | .irq_unmask = pci_msi_unmask_irq, | |
f342d940 JH |
180 | }; |
181 | ||
182 | /* MSI int handler */ | |
7f4f16ee | 183 | irqreturn_t dw_handle_msi_irq(struct pcie_port *pp) |
f342d940 JH |
184 | { |
185 | unsigned long val; | |
904d0e78 | 186 | int i, pos, irq; |
7f4f16ee | 187 | irqreturn_t ret = IRQ_NONE; |
f342d940 JH |
188 | |
189 | for (i = 0; i < MAX_MSI_CTRLS; i++) { | |
190 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, | |
191 | (u32 *)&val); | |
192 | if (val) { | |
7f4f16ee | 193 | ret = IRQ_HANDLED; |
f342d940 JH |
194 | pos = 0; |
195 | while ((pos = find_next_bit(&val, 32, pos)) != 32) { | |
904d0e78 PA |
196 | irq = irq_find_mapping(pp->irq_domain, |
197 | i * 32 + pos); | |
ca165892 HH |
198 | dw_pcie_wr_own_conf(pp, |
199 | PCIE_MSI_INTR0_STATUS + i * 12, | |
200 | 4, 1 << pos); | |
904d0e78 | 201 | generic_handle_irq(irq); |
f342d940 JH |
202 | pos++; |
203 | } | |
204 | } | |
f342d940 | 205 | } |
7f4f16ee LS |
206 | |
207 | return ret; | |
f342d940 JH |
208 | } |
209 | ||
210 | void dw_pcie_msi_init(struct pcie_port *pp) | |
211 | { | |
c8947fbb LS |
212 | u64 msi_target; |
213 | ||
f342d940 | 214 | pp->msi_data = __get_free_pages(GFP_KERNEL, 0); |
c8947fbb | 215 | msi_target = virt_to_phys((void *)pp->msi_data); |
f342d940 JH |
216 | |
217 | /* program the msi_data */ | |
218 | dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, | |
c8947fbb LS |
219 | (u32)(msi_target & 0xffffffff)); |
220 | dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, | |
221 | (u32)(msi_target >> 32 & 0xffffffff)); | |
f342d940 JH |
222 | } |
223 | ||
2f37c5a8 MK |
224 | static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq) |
225 | { | |
226 | unsigned int res, bit, val; | |
227 | ||
228 | res = (irq / 32) * 12; | |
229 | bit = irq % 32; | |
230 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); | |
231 | val &= ~(1 << bit); | |
232 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); | |
233 | } | |
234 | ||
be3f48cb | 235 | static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base, |
58275f2f | 236 | unsigned int nvec, unsigned int pos) |
be3f48cb | 237 | { |
2f37c5a8 | 238 | unsigned int i; |
be3f48cb | 239 | |
0b8cfb6a | 240 | for (i = 0; i < nvec; i++) { |
be3f48cb | 241 | irq_set_msi_desc_off(irq_base, i, NULL); |
58275f2f | 242 | /* Disable corresponding interrupt on MSI controller */ |
2f37c5a8 MK |
243 | if (pp->ops->msi_clear_irq) |
244 | pp->ops->msi_clear_irq(pp, pos + i); | |
245 | else | |
246 | dw_pcie_msi_clear_irq(pp, pos + i); | |
be3f48cb | 247 | } |
c8df6ac9 LS |
248 | |
249 | bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec)); | |
be3f48cb BEN |
250 | } |
251 | ||
2f37c5a8 MK |
252 | static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq) |
253 | { | |
254 | unsigned int res, bit, val; | |
255 | ||
256 | res = (irq / 32) * 12; | |
257 | bit = irq % 32; | |
258 | dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val); | |
259 | val |= 1 << bit; | |
260 | dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val); | |
261 | } | |
262 | ||
f342d940 JH |
263 | static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos) |
264 | { | |
c8df6ac9 | 265 | int irq, pos0, i; |
cbce7900 | 266 | struct pcie_port *pp = (struct pcie_port *) msi_desc_to_pci_sysdata(desc); |
f342d940 | 267 | |
c8df6ac9 LS |
268 | pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS, |
269 | order_base_2(no_irqs)); | |
270 | if (pos0 < 0) | |
271 | goto no_valid_irq; | |
f342d940 | 272 | |
904d0e78 PA |
273 | irq = irq_find_mapping(pp->irq_domain, pos0); |
274 | if (!irq) | |
f342d940 JH |
275 | goto no_valid_irq; |
276 | ||
be3f48cb BEN |
277 | /* |
278 | * irq_create_mapping (called from dw_pcie_host_init) pre-allocates | |
279 | * descs so there is no need to allocate descs here. We can therefore | |
280 | * assume that if irq_find_mapping above returns non-zero, then the | |
281 | * descs are also successfully allocated. | |
282 | */ | |
283 | ||
0b8cfb6a | 284 | for (i = 0; i < no_irqs; i++) { |
be3f48cb BEN |
285 | if (irq_set_msi_desc_off(irq, i, desc) != 0) { |
286 | clear_irq_range(pp, irq, i, pos0); | |
287 | goto no_valid_irq; | |
288 | } | |
f342d940 | 289 | /*Enable corresponding interrupt in MSI interrupt controller */ |
2f37c5a8 MK |
290 | if (pp->ops->msi_set_irq) |
291 | pp->ops->msi_set_irq(pp, pos0 + i); | |
292 | else | |
293 | dw_pcie_msi_set_irq(pp, pos0 + i); | |
f342d940 JH |
294 | } |
295 | ||
296 | *pos = pos0; | |
79707374 LS |
297 | desc->nvec_used = no_irqs; |
298 | desc->msi_attrib.multiple = order_base_2(no_irqs); | |
299 | ||
f342d940 JH |
300 | return irq; |
301 | ||
302 | no_valid_irq: | |
303 | *pos = pos0; | |
304 | return -ENOSPC; | |
305 | } | |
306 | ||
ea643e1a | 307 | static void dw_msi_setup_msg(struct pcie_port *pp, unsigned int irq, u32 pos) |
f342d940 | 308 | { |
f342d940 | 309 | struct msi_msg msg; |
c8947fbb | 310 | u64 msi_target; |
f342d940 | 311 | |
450e344e | 312 | if (pp->ops->get_msi_addr) |
c8947fbb | 313 | msi_target = pp->ops->get_msi_addr(pp); |
2f37c5a8 | 314 | else |
c8947fbb LS |
315 | msi_target = virt_to_phys((void *)pp->msi_data); |
316 | ||
317 | msg.address_lo = (u32)(msi_target & 0xffffffff); | |
318 | msg.address_hi = (u32)(msi_target >> 32 & 0xffffffff); | |
24832b4d ML |
319 | |
320 | if (pp->ops->get_msi_data) | |
321 | msg.data = pp->ops->get_msi_data(pp, pos); | |
322 | else | |
323 | msg.data = pos; | |
324 | ||
83a18912 | 325 | pci_write_msi_msg(irq, &msg); |
ea643e1a LS |
326 | } |
327 | ||
328 | static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev, | |
329 | struct msi_desc *desc) | |
330 | { | |
331 | int irq, pos; | |
cbce7900 | 332 | struct pcie_port *pp = pdev->bus->sysdata; |
ea643e1a LS |
333 | |
334 | if (desc->msi_attrib.is_msix) | |
335 | return -EINVAL; | |
336 | ||
337 | irq = assign_irq(1, desc, &pos); | |
338 | if (irq < 0) | |
339 | return irq; | |
340 | ||
341 | dw_msi_setup_msg(pp, irq, pos); | |
f342d940 JH |
342 | |
343 | return 0; | |
344 | } | |
345 | ||
79707374 LS |
346 | static int dw_msi_setup_irqs(struct msi_controller *chip, struct pci_dev *pdev, |
347 | int nvec, int type) | |
348 | { | |
349 | #ifdef CONFIG_PCI_MSI | |
350 | int irq, pos; | |
351 | struct msi_desc *desc; | |
cbce7900 | 352 | struct pcie_port *pp = pdev->bus->sysdata; |
79707374 LS |
353 | |
354 | /* MSI-X interrupts are not supported */ | |
355 | if (type == PCI_CAP_ID_MSIX) | |
356 | return -EINVAL; | |
357 | ||
358 | WARN_ON(!list_is_singular(&pdev->dev.msi_list)); | |
359 | desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list); | |
360 | ||
361 | irq = assign_irq(nvec, desc, &pos); | |
362 | if (irq < 0) | |
363 | return irq; | |
364 | ||
365 | dw_msi_setup_msg(pp, irq, pos); | |
366 | ||
367 | return 0; | |
368 | #else | |
369 | return -EINVAL; | |
370 | #endif | |
371 | } | |
372 | ||
c2791b80 | 373 | static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq) |
f342d940 | 374 | { |
91f8ae82 | 375 | struct irq_data *data = irq_get_irq_data(irq); |
c391f262 | 376 | struct msi_desc *msi = irq_data_get_msi_desc(data); |
cbce7900 | 377 | struct pcie_port *pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi); |
91f8ae82 LS |
378 | |
379 | clear_irq_range(pp, irq, 1, data->hwirq); | |
f342d940 JH |
380 | } |
381 | ||
c2791b80 | 382 | static struct msi_controller dw_pcie_msi_chip = { |
f342d940 | 383 | .setup_irq = dw_msi_setup_irq, |
79707374 | 384 | .setup_irqs = dw_msi_setup_irqs, |
f342d940 JH |
385 | .teardown_irq = dw_msi_teardown_irq, |
386 | }; | |
387 | ||
886bc5ce JP |
388 | int dw_pcie_wait_for_link(struct pcie_port *pp) |
389 | { | |
390 | int retries; | |
391 | ||
392 | /* check if the link is up or not */ | |
393 | for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { | |
394 | if (dw_pcie_link_up(pp)) { | |
395 | dev_info(pp->dev, "link up\n"); | |
396 | return 0; | |
397 | } | |
398 | usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); | |
399 | } | |
400 | ||
401 | dev_err(pp->dev, "phy link never came up\n"); | |
402 | ||
403 | return -ETIMEDOUT; | |
404 | } | |
405 | ||
4b1ced84 JH |
406 | int dw_pcie_link_up(struct pcie_port *pp) |
407 | { | |
dac29e6c JP |
408 | u32 val; |
409 | ||
4b1ced84 JH |
410 | if (pp->ops->link_up) |
411 | return pp->ops->link_up(pp); | |
116a489d | 412 | |
dac29e6c JP |
413 | val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1); |
414 | return val & PCIE_PHY_DEBUG_R1_LINK_UP; | |
4b1ced84 JH |
415 | } |
416 | ||
f342d940 JH |
417 | static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq, |
418 | irq_hw_number_t hwirq) | |
419 | { | |
420 | irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq); | |
421 | irq_set_chip_data(irq, domain->host_data); | |
f342d940 JH |
422 | |
423 | return 0; | |
424 | } | |
425 | ||
426 | static const struct irq_domain_ops msi_domain_ops = { | |
427 | .map = dw_pcie_msi_map, | |
428 | }; | |
429 | ||
a43f32d6 | 430 | int dw_pcie_host_init(struct pcie_port *pp) |
4b1ced84 JH |
431 | { |
432 | struct device_node *np = pp->dev->of_node; | |
4dd964df | 433 | struct platform_device *pdev = to_platform_device(pp->dev); |
cbce7900 | 434 | struct pci_bus *bus, *child; |
4dd964df | 435 | struct resource *cfg_res; |
9cdce1cd | 436 | int i, ret; |
0021d22b ZW |
437 | LIST_HEAD(res); |
438 | struct resource_entry *win; | |
f342d940 | 439 | |
4dd964df KVA |
440 | cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); |
441 | if (cfg_res) { | |
adf70fc0 PA |
442 | pp->cfg0_size = resource_size(cfg_res)/2; |
443 | pp->cfg1_size = resource_size(cfg_res)/2; | |
4dd964df | 444 | pp->cfg0_base = cfg_res->start; |
adf70fc0 | 445 | pp->cfg1_base = cfg_res->start + pp->cfg0_size; |
0f414212 | 446 | } else if (!pp->va_cfg0_base) { |
4dd964df KVA |
447 | dev_err(pp->dev, "missing *config* reg space\n"); |
448 | } | |
449 | ||
0021d22b ZW |
450 | ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base); |
451 | if (ret) | |
452 | return ret; | |
4b1ced84 | 453 | |
12722dbb BH |
454 | ret = devm_request_pci_bus_resources(&pdev->dev, &res); |
455 | if (ret) | |
456 | goto error; | |
457 | ||
4b1ced84 | 458 | /* Get the I/O and memory ranges from DT */ |
0021d22b ZW |
459 | resource_list_for_each_entry(win, &res) { |
460 | switch (resource_type(win->res)) { | |
461 | case IORESOURCE_IO: | |
462 | pp->io = win->res; | |
463 | pp->io->name = "I/O"; | |
464 | pp->io_size = resource_size(pp->io); | |
465 | pp->io_bus_addr = pp->io->start - win->offset; | |
cbce7900 | 466 | ret = pci_remap_iospace(pp->io, pp->io_base); |
7baf69c7 | 467 | if (ret) |
cbce7900 ZW |
468 | dev_warn(pp->dev, "error %d: failed to map resource %pR\n", |
469 | ret, pp->io); | |
0021d22b ZW |
470 | break; |
471 | case IORESOURCE_MEM: | |
472 | pp->mem = win->res; | |
473 | pp->mem->name = "MEM"; | |
474 | pp->mem_size = resource_size(pp->mem); | |
475 | pp->mem_bus_addr = pp->mem->start - win->offset; | |
476 | break; | |
477 | case 0: | |
478 | pp->cfg = win->res; | |
479 | pp->cfg0_size = resource_size(pp->cfg)/2; | |
480 | pp->cfg1_size = resource_size(pp->cfg)/2; | |
481 | pp->cfg0_base = pp->cfg->start; | |
482 | pp->cfg1_base = pp->cfg->start + pp->cfg0_size; | |
483 | break; | |
484 | case IORESOURCE_BUS: | |
485 | pp->busn = win->res; | |
486 | break; | |
4b1ced84 | 487 | } |
4f2ebe00 LS |
488 | } |
489 | ||
4b1ced84 | 490 | if (!pp->dbi_base) { |
0021d22b ZW |
491 | pp->dbi_base = devm_ioremap(pp->dev, pp->cfg->start, |
492 | resource_size(pp->cfg)); | |
4b1ced84 JH |
493 | if (!pp->dbi_base) { |
494 | dev_err(pp->dev, "error with ioremap\n"); | |
27d9cb7e BH |
495 | ret = -ENOMEM; |
496 | goto error; | |
4b1ced84 JH |
497 | } |
498 | } | |
499 | ||
0021d22b | 500 | pp->mem_base = pp->mem->start; |
4b1ced84 | 501 | |
4b1ced84 | 502 | if (!pp->va_cfg0_base) { |
b14a3d17 | 503 | pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base, |
adf70fc0 | 504 | pp->cfg0_size); |
b14a3d17 MK |
505 | if (!pp->va_cfg0_base) { |
506 | dev_err(pp->dev, "error with ioremap in function\n"); | |
27d9cb7e BH |
507 | ret = -ENOMEM; |
508 | goto error; | |
b14a3d17 | 509 | } |
4b1ced84 | 510 | } |
b14a3d17 | 511 | |
4b1ced84 | 512 | if (!pp->va_cfg1_base) { |
b14a3d17 | 513 | pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base, |
adf70fc0 | 514 | pp->cfg1_size); |
b14a3d17 MK |
515 | if (!pp->va_cfg1_base) { |
516 | dev_err(pp->dev, "error with ioremap\n"); | |
27d9cb7e BH |
517 | ret = -ENOMEM; |
518 | goto error; | |
b14a3d17 | 519 | } |
4b1ced84 JH |
520 | } |
521 | ||
907fce09 GP |
522 | ret = of_property_read_u32(np, "num-lanes", &pp->lanes); |
523 | if (ret) | |
524 | pp->lanes = 0; | |
4b1ced84 | 525 | |
f342d940 | 526 | if (IS_ENABLED(CONFIG_PCI_MSI)) { |
b14a3d17 MK |
527 | if (!pp->ops->msi_host_init) { |
528 | pp->irq_domain = irq_domain_add_linear(pp->dev->of_node, | |
529 | MAX_MSI_IRQS, &msi_domain_ops, | |
530 | &dw_pcie_msi_chip); | |
531 | if (!pp->irq_domain) { | |
532 | dev_err(pp->dev, "irq domain init failed\n"); | |
27d9cb7e BH |
533 | ret = -ENXIO; |
534 | goto error; | |
b14a3d17 | 535 | } |
f342d940 | 536 | |
b14a3d17 MK |
537 | for (i = 0; i < MAX_MSI_IRQS; i++) |
538 | irq_create_mapping(pp->irq_domain, i); | |
539 | } else { | |
540 | ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip); | |
541 | if (ret < 0) | |
27d9cb7e | 542 | goto error; |
b14a3d17 | 543 | } |
f342d940 JH |
544 | } |
545 | ||
4b1ced84 JH |
546 | if (pp->ops->host_init) |
547 | pp->ops->host_init(pp); | |
548 | ||
cbce7900 ZW |
549 | pp->root_bus_nr = pp->busn->start; |
550 | if (IS_ENABLED(CONFIG_PCI_MSI)) { | |
551 | bus = pci_scan_root_bus_msi(pp->dev, pp->root_bus_nr, | |
552 | &dw_pcie_ops, pp, &res, | |
553 | &dw_pcie_msi_chip); | |
554 | dw_pcie_msi_chip.dev = pp->dev; | |
555 | } else | |
556 | bus = pci_scan_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops, | |
557 | pp, &res); | |
27d9cb7e BH |
558 | if (!bus) { |
559 | ret = -ENOMEM; | |
560 | goto error; | |
561 | } | |
cbce7900 ZW |
562 | |
563 | if (pp->ops->scan_bus) | |
564 | pp->ops->scan_bus(pp); | |
565 | ||
566 | #ifdef CONFIG_ARM | |
567 | /* support old dtbs that incorrectly describe IRQs */ | |
568 | pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); | |
0815f957 YW |
569 | #endif |
570 | ||
ed00c83c LP |
571 | pci_bus_size_bridges(bus); |
572 | pci_bus_assign_resources(bus); | |
4b1ced84 | 573 | |
ed00c83c LP |
574 | list_for_each_entry(child, &bus->children, node) |
575 | pcie_bus_configure_settings(child); | |
4b1ced84 | 576 | |
cbce7900 | 577 | pci_bus_add_devices(bus); |
4b1ced84 | 578 | return 0; |
27d9cb7e BH |
579 | |
580 | error: | |
581 | pci_free_resource_list(&res); | |
582 | return ret; | |
4b1ced84 JH |
583 | } |
584 | ||
4b1ced84 | 585 | static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, |
340cba60 JH |
586 | u32 devfn, int where, int size, u32 *val) |
587 | { | |
2d91b491 | 588 | int ret, type; |
4c45852f | 589 | u32 busdev, cfg_size; |
2d91b491 JZ |
590 | u64 cpu_addr; |
591 | void __iomem *va_cfg_base; | |
340cba60 | 592 | |
67de2dc3 BH |
593 | if (pp->ops->rd_other_conf) |
594 | return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val); | |
595 | ||
340cba60 JH |
596 | busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | |
597 | PCIE_ATU_FUNC(PCI_FUNC(devfn)); | |
340cba60 JH |
598 | |
599 | if (bus->parent->number == pp->root_bus_nr) { | |
2d91b491 | 600 | type = PCIE_ATU_TYPE_CFG0; |
9cdce1cd | 601 | cpu_addr = pp->cfg0_base; |
2d91b491 JZ |
602 | cfg_size = pp->cfg0_size; |
603 | va_cfg_base = pp->va_cfg0_base; | |
340cba60 | 604 | } else { |
2d91b491 | 605 | type = PCIE_ATU_TYPE_CFG1; |
9cdce1cd | 606 | cpu_addr = pp->cfg1_base; |
2d91b491 JZ |
607 | cfg_size = pp->cfg1_size; |
608 | va_cfg_base = pp->va_cfg1_base; | |
340cba60 JH |
609 | } |
610 | ||
2d91b491 JZ |
611 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, |
612 | type, cpu_addr, | |
613 | busdev, cfg_size); | |
4c45852f | 614 | ret = dw_pcie_cfg_read(va_cfg_base + where, size, val); |
2d91b491 | 615 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, |
9cdce1cd | 616 | PCIE_ATU_TYPE_IO, pp->io_base, |
2d91b491 JZ |
617 | pp->io_bus_addr, pp->io_size); |
618 | ||
340cba60 JH |
619 | return ret; |
620 | } | |
621 | ||
4b1ced84 | 622 | static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus, |
340cba60 JH |
623 | u32 devfn, int where, int size, u32 val) |
624 | { | |
2d91b491 | 625 | int ret, type; |
4c45852f | 626 | u32 busdev, cfg_size; |
2d91b491 JZ |
627 | u64 cpu_addr; |
628 | void __iomem *va_cfg_base; | |
340cba60 | 629 | |
67de2dc3 BH |
630 | if (pp->ops->wr_other_conf) |
631 | return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val); | |
632 | ||
340cba60 JH |
633 | busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) | |
634 | PCIE_ATU_FUNC(PCI_FUNC(devfn)); | |
340cba60 JH |
635 | |
636 | if (bus->parent->number == pp->root_bus_nr) { | |
2d91b491 | 637 | type = PCIE_ATU_TYPE_CFG0; |
9cdce1cd | 638 | cpu_addr = pp->cfg0_base; |
2d91b491 JZ |
639 | cfg_size = pp->cfg0_size; |
640 | va_cfg_base = pp->va_cfg0_base; | |
340cba60 | 641 | } else { |
2d91b491 | 642 | type = PCIE_ATU_TYPE_CFG1; |
9cdce1cd | 643 | cpu_addr = pp->cfg1_base; |
2d91b491 JZ |
644 | cfg_size = pp->cfg1_size; |
645 | va_cfg_base = pp->va_cfg1_base; | |
340cba60 JH |
646 | } |
647 | ||
2d91b491 JZ |
648 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, |
649 | type, cpu_addr, | |
650 | busdev, cfg_size); | |
4c45852f | 651 | ret = dw_pcie_cfg_write(va_cfg_base + where, size, val); |
2d91b491 | 652 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0, |
9cdce1cd | 653 | PCIE_ATU_TYPE_IO, pp->io_base, |
2d91b491 JZ |
654 | pp->io_bus_addr, pp->io_size); |
655 | ||
340cba60 JH |
656 | return ret; |
657 | } | |
658 | ||
4b1ced84 | 659 | static int dw_pcie_valid_config(struct pcie_port *pp, |
340cba60 JH |
660 | struct pci_bus *bus, int dev) |
661 | { | |
662 | /* If there is no link, then there is no device */ | |
663 | if (bus->number != pp->root_bus_nr) { | |
4b1ced84 | 664 | if (!dw_pcie_link_up(pp)) |
340cba60 JH |
665 | return 0; |
666 | } | |
667 | ||
668 | /* access only one slot on each root port */ | |
669 | if (bus->number == pp->root_bus_nr && dev > 0) | |
670 | return 0; | |
671 | ||
672 | /* | |
673 | * do not read more than one device on the bus directly attached | |
674 | * to RC's (Virtual Bridge's) DS side. | |
675 | */ | |
676 | if (bus->primary == pp->root_bus_nr && dev > 0) | |
677 | return 0; | |
678 | ||
679 | return 1; | |
680 | } | |
681 | ||
4b1ced84 | 682 | static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, |
340cba60 JH |
683 | int size, u32 *val) |
684 | { | |
cbce7900 | 685 | struct pcie_port *pp = bus->sysdata; |
340cba60 | 686 | |
4b1ced84 | 687 | if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) { |
340cba60 JH |
688 | *val = 0xffffffff; |
689 | return PCIBIOS_DEVICE_NOT_FOUND; | |
690 | } | |
691 | ||
116a489d BH |
692 | if (bus->number == pp->root_bus_nr) |
693 | return dw_pcie_rd_own_conf(pp, where, size, val); | |
340cba60 | 694 | |
116a489d | 695 | return dw_pcie_rd_other_conf(pp, bus, devfn, where, size, val); |
340cba60 JH |
696 | } |
697 | ||
4b1ced84 | 698 | static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn, |
340cba60 JH |
699 | int where, int size, u32 val) |
700 | { | |
cbce7900 | 701 | struct pcie_port *pp = bus->sysdata; |
340cba60 | 702 | |
4b1ced84 | 703 | if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) |
340cba60 JH |
704 | return PCIBIOS_DEVICE_NOT_FOUND; |
705 | ||
116a489d BH |
706 | if (bus->number == pp->root_bus_nr) |
707 | return dw_pcie_wr_own_conf(pp, where, size, val); | |
340cba60 | 708 | |
116a489d | 709 | return dw_pcie_wr_other_conf(pp, bus, devfn, where, size, val); |
340cba60 JH |
710 | } |
711 | ||
4b1ced84 JH |
712 | static struct pci_ops dw_pcie_ops = { |
713 | .read = dw_pcie_rd_conf, | |
714 | .write = dw_pcie_wr_conf, | |
340cba60 JH |
715 | }; |
716 | ||
4b1ced84 | 717 | void dw_pcie_setup_rc(struct pcie_port *pp) |
340cba60 | 718 | { |
340cba60 | 719 | u32 val; |
340cba60 | 720 | |
66c5c34b | 721 | /* set the number of lanes */ |
f7b7868c | 722 | dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val); |
340cba60 | 723 | val &= ~PORT_LINK_MODE_MASK; |
4b1ced84 JH |
724 | switch (pp->lanes) { |
725 | case 1: | |
726 | val |= PORT_LINK_MODE_1_LANES; | |
727 | break; | |
728 | case 2: | |
729 | val |= PORT_LINK_MODE_2_LANES; | |
730 | break; | |
731 | case 4: | |
732 | val |= PORT_LINK_MODE_4_LANES; | |
733 | break; | |
5b0f0738 ZW |
734 | case 8: |
735 | val |= PORT_LINK_MODE_8_LANES; | |
736 | break; | |
907fce09 GP |
737 | default: |
738 | dev_err(pp->dev, "num-lanes %u: invalid value\n", pp->lanes); | |
739 | return; | |
4b1ced84 | 740 | } |
f7b7868c | 741 | dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL); |
340cba60 JH |
742 | |
743 | /* set link width speed control register */ | |
f7b7868c | 744 | dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val); |
340cba60 | 745 | val &= ~PORT_LOGIC_LINK_WIDTH_MASK; |
4b1ced84 JH |
746 | switch (pp->lanes) { |
747 | case 1: | |
748 | val |= PORT_LOGIC_LINK_WIDTH_1_LANES; | |
749 | break; | |
750 | case 2: | |
751 | val |= PORT_LOGIC_LINK_WIDTH_2_LANES; | |
752 | break; | |
753 | case 4: | |
754 | val |= PORT_LOGIC_LINK_WIDTH_4_LANES; | |
755 | break; | |
5b0f0738 ZW |
756 | case 8: |
757 | val |= PORT_LOGIC_LINK_WIDTH_8_LANES; | |
758 | break; | |
4b1ced84 | 759 | } |
f7b7868c | 760 | dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL); |
340cba60 JH |
761 | |
762 | /* setup RC BARs */ | |
f7b7868c | 763 | dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0); |
dbffdd68 | 764 | dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1); |
340cba60 JH |
765 | |
766 | /* setup interrupt pins */ | |
f7b7868c | 767 | dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val); |
340cba60 JH |
768 | val &= 0xffff00ff; |
769 | val |= 0x00000100; | |
f7b7868c | 770 | dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE); |
340cba60 JH |
771 | |
772 | /* setup bus numbers */ | |
f7b7868c | 773 | dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val); |
340cba60 JH |
774 | val &= 0xff000000; |
775 | val |= 0x00010100; | |
f7b7868c | 776 | dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS); |
340cba60 | 777 | |
340cba60 | 778 | /* setup command register */ |
f7b7868c | 779 | dw_pcie_readl_rc(pp, PCI_COMMAND, &val); |
340cba60 JH |
780 | val &= 0xffff0000; |
781 | val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | | |
782 | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; | |
f7b7868c | 783 | dw_pcie_writel_rc(pp, val, PCI_COMMAND); |
7e57fd14 JZ |
784 | |
785 | /* | |
786 | * If the platform provides ->rd_other_conf, it means the platform | |
787 | * uses its own address translation component rather than ATU, so | |
788 | * we should not program the ATU here. | |
789 | */ | |
790 | if (!pp->ops->rd_other_conf) | |
791 | dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX1, | |
792 | PCIE_ATU_TYPE_MEM, pp->mem_base, | |
793 | pp->mem_bus_addr, pp->mem_size); | |
794 | ||
795 | dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); | |
796 | ||
797 | /* program correct class for RC */ | |
798 | dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); | |
799 | ||
800 | dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); | |
801 | val |= PORT_LOGIC_SPEED_CHANGE; | |
802 | dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); | |
340cba60 | 803 | } |