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[deliverable/linux.git] / drivers / pci / host / pcie-xilinx-nwl.c
CommitLineData
ab597d35
BKG		 1/*
2 * PCIe host controller driver for NWL PCIe Bridge
3 * Based on pcie-xilinx.c, pci-tegra.c
4 *
5 * (C) Copyright 2014 - 2015, Xilinx, Inc.
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/delay.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/irqdomain.h>
17#include <linux/kernel.h>
ff187e77 18#include <linux/init.h>
ab597d35
BKG		 19#include <linux/msi.h>
20#include <linux/of_address.h>
21#include <linux/of_pci.h>
22#include <linux/of_platform.h>
23#include <linux/of_irq.h>
24#include <linux/pci.h>
25#include <linux/platform_device.h>
26#include <linux/irqchip/chained_irq.h>
27
28/* Bridge core config registers */
29#define BRCFG_PCIE_RX0 0x00000000
30#define BRCFG_INTERRUPT 0x00000010
31#define BRCFG_PCIE_RX_MSG_FILTER 0x00000020
32
33/* Egress - Bridge translation registers */
34#define E_BREG_CAPABILITIES 0x00000200
35#define E_BREG_CONTROL 0x00000208
36#define E_BREG_BASE_LO 0x00000210
37#define E_BREG_BASE_HI 0x00000214
38#define E_ECAM_CAPABILITIES 0x00000220
39#define E_ECAM_CONTROL 0x00000228
40#define E_ECAM_BASE_LO 0x00000230
41#define E_ECAM_BASE_HI 0x00000234
42
43/* Ingress - address translations */
44#define I_MSII_CAPABILITIES 0x00000300
45#define I_MSII_CONTROL 0x00000308
46#define I_MSII_BASE_LO 0x00000310
47#define I_MSII_BASE_HI 0x00000314
48
49#define I_ISUB_CONTROL 0x000003E8
50#define SET_ISUB_CONTROL BIT(0)
51/* Rxed msg fifo - Interrupt status registers */
52#define MSGF_MISC_STATUS 0x00000400
53#define MSGF_MISC_MASK 0x00000404
54#define MSGF_LEG_STATUS 0x00000420
55#define MSGF_LEG_MASK 0x00000424
56#define MSGF_MSI_STATUS_LO 0x00000440
57#define MSGF_MSI_STATUS_HI 0x00000444
58#define MSGF_MSI_MASK_LO 0x00000448
59#define MSGF_MSI_MASK_HI 0x0000044C
60
61/* Msg filter mask bits */
62#define CFG_ENABLE_PM_MSG_FWD BIT(1)
63#define CFG_ENABLE_INT_MSG_FWD BIT(2)
64#define CFG_ENABLE_ERR_MSG_FWD BIT(3)
65#define CFG_ENABLE_SLT_MSG_FWD BIT(5)
66#define CFG_ENABLE_VEN_MSG_FWD BIT(7)
67#define CFG_ENABLE_OTH_MSG_FWD BIT(13)
68#define CFG_ENABLE_VEN_MSG_EN BIT(14)
69#define CFG_ENABLE_VEN_MSG_VEN_INV BIT(15)
70#define CFG_ENABLE_VEN_MSG_VEN_ID GENMASK(31, 16)
71#define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \
72 CFG_ENABLE_INT_MSG_FWD | \
73 CFG_ENABLE_ERR_MSG_FWD | \
74 CFG_ENABLE_SLT_MSG_FWD | \
75 CFG_ENABLE_VEN_MSG_FWD | \
76 CFG_ENABLE_OTH_MSG_FWD | \
77 CFG_ENABLE_VEN_MSG_EN | \
78 CFG_ENABLE_VEN_MSG_VEN_INV | \
79 CFG_ENABLE_VEN_MSG_VEN_ID)
80
81/* Misc interrupt status mask bits */
82#define MSGF_MISC_SR_RXMSG_AVAIL BIT(0)
83#define MSGF_MISC_SR_RXMSG_OVER BIT(1)
84#define MSGF_MISC_SR_SLAVE_ERR BIT(4)
85#define MSGF_MISC_SR_MASTER_ERR BIT(5)
86#define MSGF_MISC_SR_I_ADDR_ERR BIT(6)
87#define MSGF_MISC_SR_E_ADDR_ERR BIT(7)
88#define MSGF_MISC_SR_UR_DETECT BIT(20)
89
90#define MSGF_MISC_SR_PCIE_CORE GENMASK(18, 16)
91#define MSGF_MISC_SR_PCIE_CORE_ERR GENMASK(31, 22)
92
93#define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \
94 MSGF_MISC_SR_RXMSG_OVER | \
95 MSGF_MISC_SR_SLAVE_ERR | \
96 MSGF_MISC_SR_MASTER_ERR | \
97 MSGF_MISC_SR_I_ADDR_ERR | \
98 MSGF_MISC_SR_E_ADDR_ERR | \
99 MSGF_MISC_SR_UR_DETECT | \
100 MSGF_MISC_SR_PCIE_CORE | \
101 MSGF_MISC_SR_PCIE_CORE_ERR)
102
103/* Legacy interrupt status mask bits */
104#define MSGF_LEG_SR_INTA BIT(0)
105#define MSGF_LEG_SR_INTB BIT(1)
106#define MSGF_LEG_SR_INTC BIT(2)
107#define MSGF_LEG_SR_INTD BIT(3)
108#define MSGF_LEG_SR_MASKALL (MSGF_LEG_SR_INTA | MSGF_LEG_SR_INTB | \
109 MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD)
110
111/* MSI interrupt status mask bits */
112#define MSGF_MSI_SR_LO_MASK BIT(0)
113#define MSGF_MSI_SR_HI_MASK BIT(0)
114
115#define MSII_PRESENT BIT(0)
116#define MSII_ENABLE BIT(0)
117#define MSII_STATUS_ENABLE BIT(15)
118
119/* Bridge config interrupt mask */
120#define BRCFG_INTERRUPT_MASK BIT(0)
121#define BREG_PRESENT BIT(0)
122#define BREG_ENABLE BIT(0)
123#define BREG_ENABLE_FORCE BIT(1)
124
125/* E_ECAM status mask bits */
126#define E_ECAM_PRESENT BIT(0)
127#define E_ECAM_CR_ENABLE BIT(0)
128#define E_ECAM_SIZE_LOC GENMASK(20, 16)
129#define E_ECAM_SIZE_SHIFT 16
130#define ECAM_BUS_LOC_SHIFT 20
131#define ECAM_DEV_LOC_SHIFT 12
132#define NWL_ECAM_VALUE_DEFAULT 12
133
134#define CFG_DMA_REG_BAR GENMASK(2, 0)
135
136#define INT_PCI_MSI_NR (2 * 32)
137#define INTX_NUM 4
138
139/* Readin the PS_LINKUP */
140#define PS_LINKUP_OFFSET 0x00000238
141#define PCIE_PHY_LINKUP_BIT BIT(0)
142#define PHY_RDY_LINKUP_BIT BIT(1)
143
144/* Parameters for the waiting for link up routine */
145#define LINK_WAIT_MAX_RETRIES 10
146#define LINK_WAIT_USLEEP_MIN 90000
147#define LINK_WAIT_USLEEP_MAX 100000
148
149struct nwl_msi { /* MSI information */
150 struct irq_domain *msi_domain;
151 unsigned long *bitmap;
152 struct irq_domain *dev_domain;
153 struct mutex lock; /* protect bitmap variable */
154 int irq_msi0;
155 int irq_msi1;
156};
157
158struct nwl_pcie {
159 struct device *dev;
160 void __iomem *breg_base;
161 void __iomem *pcireg_base;
162 void __iomem *ecam_base;
163 phys_addr_t phys_breg_base; /* Physical Bridge Register Base */
164 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
165 phys_addr_t phys_ecam_base; /* Physical Configuration Base */
166 u32 breg_size;
167 u32 pcie_reg_size;
168 u32 ecam_size;
169 int irq_intx;
170 int irq_misc;
171 u32 ecam_value;
172 u8 last_busno;
173 u8 root_busno;
174 struct nwl_msi msi;
175 struct irq_domain *legacy_irq_domain;
176};
177
178static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)
179{
180 return readl(pcie->breg_base + off);
181}
182
183static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)
184{
185 writel(val, pcie->breg_base + off);
186}
187
188static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
189{
190 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
191 return true;
192 return false;
193}
194
195static bool nwl_phy_link_up(struct nwl_pcie *pcie)
196{
197 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)
198 return true;
199 return false;
200}
201
202static int nwl_wait_for_link(struct nwl_pcie *pcie)
203{
204 int retries;
205
206 /* check if the link is up or not */
207 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
208 if (nwl_phy_link_up(pcie))
209 return 0;
210 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
211 }
212
213 dev_err(pcie->dev, "PHY link never came up\n");
214 return -ETIMEDOUT;
215}
216
217static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
218{
219 struct nwl_pcie *pcie = bus->sysdata;
220
221 /* Check link before accessing downstream ports */
222 if (bus->number != pcie->root_busno) {
223 if (!nwl_pcie_link_up(pcie))
224 return false;
225 }
226
227 /* Only one device down on each root port */
228 if (bus->number == pcie->root_busno && devfn > 0)
229 return false;
230
231 return true;
232}
233
234/**
235 * nwl_pcie_map_bus - Get configuration base
236 *
237 * @bus: Bus structure of current bus
238 * @devfn: Device/function
239 * @where: Offset from base
240 *
241 * Return: Base address of the configuration space needed to be
242 * accessed.
243 */
244static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
245 int where)
246{
247 struct nwl_pcie *pcie = bus->sysdata;
248 int relbus;
249
250 if (!nwl_pcie_valid_device(bus, devfn))
251 return NULL;
252
253 relbus = (bus->number << ECAM_BUS_LOC_SHIFT) |
254 (devfn << ECAM_DEV_LOC_SHIFT);
255
256 return pcie->ecam_base + relbus + where;
257}
258
259/* PCIe operations */
260static struct pci_ops nwl_pcie_ops = {
261 .map_bus = nwl_pcie_map_bus,
262 .read = pci_generic_config_read,
263 .write = pci_generic_config_write,
264};
265
266static irqreturn_t nwl_pcie_misc_handler(int irq, void *data)
267{
268 struct nwl_pcie *pcie = data;
269 u32 misc_stat;
270
271 /* Checking for misc interrupts */
272 misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
273 MSGF_MISC_SR_MASKALL;
274 if (!misc_stat)
275 return IRQ_NONE;
276
277 if (misc_stat & MSGF_MISC_SR_RXMSG_OVER)
278 dev_err(pcie->dev, "Received Message FIFO Overflow\n");
279
280 if (misc_stat & MSGF_MISC_SR_SLAVE_ERR)
281 dev_err(pcie->dev, "Slave error\n");
282
283 if (misc_stat & MSGF_MISC_SR_MASTER_ERR)
284 dev_err(pcie->dev, "Master error\n");
285
286 if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR)
287 dev_err(pcie->dev,
288 "In Misc Ingress address translation error\n");
289
290 if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR)
291 dev_err(pcie->dev,
292 "In Misc Egress address translation error\n");
293
294 if (misc_stat & MSGF_MISC_SR_PCIE_CORE_ERR)
295 dev_err(pcie->dev, "PCIe Core error\n");
296
297 /* Clear misc interrupt status */
298 nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);
299
300 return IRQ_HANDLED;
301}
302
303static void nwl_pcie_leg_handler(struct irq_desc *desc)
304{
305 struct irq_chip *chip = irq_desc_get_chip(desc);
306 struct nwl_pcie *pcie;
307 unsigned long status;
308 u32 bit;
309 u32 virq;
310
311 chained_irq_enter(chip, desc);
312 pcie = irq_desc_get_handler_data(desc);
313
314 while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
315 MSGF_LEG_SR_MASKALL) != 0) {
316 for_each_set_bit(bit, &status, INTX_NUM) {
317 virq = irq_find_mapping(pcie->legacy_irq_domain,
318 bit + 1);
319 if (virq)
320 generic_handle_irq(virq);
321 }
322 }
323
324 chained_irq_exit(chip, desc);
325}
326
327static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg)
328{
329 struct nwl_msi *msi;
330 unsigned long status;
331 u32 bit;
332 u32 virq;
333
334 msi = &pcie->msi;
335
336 while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {
337 for_each_set_bit(bit, &status, 32) {
338 nwl_bridge_writel(pcie, 1 << bit, status_reg);
339 virq = irq_find_mapping(msi->dev_domain, bit);
340 if (virq)
341 generic_handle_irq(virq);
342 }
343 }
344}
345
346static void nwl_pcie_msi_handler_high(struct irq_desc *desc)
347{
348 struct irq_chip *chip = irq_desc_get_chip(desc);
349 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
350
351 chained_irq_enter(chip, desc);
352 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI);
353 chained_irq_exit(chip, desc);
354}
355
356static void nwl_pcie_msi_handler_low(struct irq_desc *desc)
357{
358 struct irq_chip *chip = irq_desc_get_chip(desc);
359 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
360
361 chained_irq_enter(chip, desc);
362 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO);
363 chained_irq_exit(chip, desc);
364}
365
366static int nwl_legacy_map(struct irq_domain *domain, unsigned int irq,
367 irq_hw_number_t hwirq)
368{
369 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
370 irq_set_chip_data(irq, domain->host_data);
371
372 return 0;
373}
374
375static const struct irq_domain_ops legacy_domain_ops = {
376 .map = nwl_legacy_map,
377};
378
379#ifdef CONFIG_PCI_MSI
380static struct irq_chip nwl_msi_irq_chip = {
381 .name = "nwl_pcie:msi",
382 .irq_enable = unmask_msi_irq,
383 .irq_disable = mask_msi_irq,
384 .irq_mask = mask_msi_irq,
385 .irq_unmask = unmask_msi_irq,
386
387};
388
389static struct msi_domain_info nwl_msi_domain_info = {
390 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
391 MSI_FLAG_MULTI_PCI_MSI),
392 .chip = &nwl_msi_irq_chip,
393};
394#endif
395
396static void nwl_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
397{
398 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
399 phys_addr_t msi_addr = pcie->phys_pcie_reg_base;
400
401 msg->address_lo = lower_32_bits(msi_addr);
402 msg->address_hi = upper_32_bits(msi_addr);
403 msg->data = data->hwirq;
404}
405
406static int nwl_msi_set_affinity(struct irq_data *irq_data,
407 const struct cpumask *mask, bool force)
408{
409 return -EINVAL;
410}
411
412static struct irq_chip nwl_irq_chip = {
413 .name = "Xilinx MSI",
414 .irq_compose_msi_msg = nwl_compose_msi_msg,
415 .irq_set_affinity = nwl_msi_set_affinity,
416};
417
418static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
419 unsigned int nr_irqs, void *args)
420{
421 struct nwl_pcie *pcie = domain->host_data;
422 struct nwl_msi *msi = &pcie->msi;
423 int bit;
424 int i;
425
426 mutex_lock(&msi->lock);
427 bit = bitmap_find_next_zero_area(msi->bitmap, INT_PCI_MSI_NR, 0,
428 nr_irqs, 0);
429 if (bit >= INT_PCI_MSI_NR) {
430 mutex_unlock(&msi->lock);
431 return -ENOSPC;
432 }
433
434 bitmap_set(msi->bitmap, bit, nr_irqs);
435
436 for (i = 0; i < nr_irqs; i++) {
437 irq_domain_set_info(domain, virq + i, bit + i, &nwl_irq_chip,
438 domain->host_data, handle_simple_irq,
439 NULL, NULL);
440 }
441 mutex_unlock(&msi->lock);
442 return 0;
443}
444
445static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq,
446 unsigned int nr_irqs)
447{
448 struct irq_data *data = irq_domain_get_irq_data(domain, virq);
449 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
450 struct nwl_msi *msi = &pcie->msi;
451
452 mutex_lock(&msi->lock);
453 bitmap_clear(msi->bitmap, data->hwirq, nr_irqs);
454 mutex_unlock(&msi->lock);
455}
456
457static const struct irq_domain_ops dev_msi_domain_ops = {
458 .alloc = nwl_irq_domain_alloc,
459 .free = nwl_irq_domain_free,
460};
461
ab597d35
BKG		 462static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)
463{
464#ifdef CONFIG_PCI_MSI
465 struct fwnode_handle *fwnode = of_node_to_fwnode(pcie->dev->of_node);
466 struct nwl_msi *msi = &pcie->msi;
467
468 msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR,
469 &dev_msi_domain_ops, pcie);
470 if (!msi->dev_domain) {
471 dev_err(pcie->dev, "failed to create dev IRQ domain\n");
472 return -ENOMEM;
473 }
474 msi->msi_domain = pci_msi_create_irq_domain(fwnode,
475 &nwl_msi_domain_info,
476 msi->dev_domain);
477 if (!msi->msi_domain) {
478 dev_err(pcie->dev, "failed to create msi IRQ domain\n");
479 irq_domain_remove(msi->dev_domain);
480 return -ENOMEM;
481 }
482#endif
483 return 0;
484}
485
486static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)
487{
488 struct device_node *node = pcie->dev->of_node;
489 struct device_node *legacy_intc_node;
490
491 legacy_intc_node = of_get_next_child(node, NULL);
492 if (!legacy_intc_node) {
493 dev_err(pcie->dev, "No legacy intc node found\n");
494 return -EINVAL;
495 }
496
497 pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node,
498 INTX_NUM,
499 &legacy_domain_ops,
500 pcie);
501
502 if (!pcie->legacy_irq_domain) {
503 dev_err(pcie->dev, "failed to create IRQ domain\n");
504 return -ENOMEM;
505 }
506
507 nwl_pcie_init_msi_irq_domain(pcie);
508 return 0;
509}
510
511static int nwl_pcie_enable_msi(struct nwl_pcie *pcie, struct pci_bus *bus)
512{
513 struct platform_device *pdev = to_platform_device(pcie->dev);
514 struct nwl_msi *msi = &pcie->msi;
515 unsigned long base;
516 int ret;
517 int size = BITS_TO_LONGS(INT_PCI_MSI_NR) * sizeof(long);
518
519 mutex_init(&msi->lock);
520
521 msi->bitmap = kzalloc(size, GFP_KERNEL);
522 if (!msi->bitmap)
523 return -ENOMEM;
524
525 /* Get msi_1 IRQ number */
526 msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1");
527 if (msi->irq_msi1 < 0) {
528 dev_err(&pdev->dev, "failed to get IRQ#%d\n", msi->irq_msi1);
529 ret = -EINVAL;
530 goto err;
531 }
532
533 irq_set_chained_handler_and_data(msi->irq_msi1,
534 nwl_pcie_msi_handler_high, pcie);
535
536 /* Get msi_0 IRQ number */
537 msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0");
538 if (msi->irq_msi0 < 0) {
539 dev_err(&pdev->dev, "failed to get IRQ#%d\n", msi->irq_msi0);
540 ret = -EINVAL;
541 goto err;
542 }
543
544 irq_set_chained_handler_and_data(msi->irq_msi0,
545 nwl_pcie_msi_handler_low, pcie);
546
547 /* Check for msii_present bit */
548 ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;
549 if (!ret) {
550 dev_err(pcie->dev, "MSI not present\n");
551 ret = -EIO;
552 goto err;
553 }
554
555 /* Enable MSII */
556 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
557 MSII_ENABLE, I_MSII_CONTROL);
558
559 /* Enable MSII status */
560 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
561 MSII_STATUS_ENABLE, I_MSII_CONTROL);
562
563 /* setup AFI/FPCI range */
564 base = pcie->phys_pcie_reg_base;
565 nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);
566 nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);
567
568 /*
569 * For high range MSI interrupts: disable, clear any pending,
570 * and enable
571 */
572 nwl_bridge_writel(pcie, (u32)~MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
573
574 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) &
575 MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI);
576
577 nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
578
579 /*
580 * For low range MSI interrupts: disable, clear any pending,
581 * and enable
582 */
583 nwl_bridge_writel(pcie, (u32)~MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
584
585 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &
586 MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO);
587
588 nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
589
590 return 0;
591err:
592 kfree(msi->bitmap);
593 msi->bitmap = NULL;
594 return ret;
595}
596
597static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
598{
599 struct platform_device *pdev = to_platform_device(pcie->dev);
600 u32 breg_val, ecam_val, first_busno = 0;
601 int err;
602
603 breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
604 if (!breg_val) {
605 dev_err(pcie->dev, "BREG is not present\n");
606 return breg_val;
607 }
608
609 /* Write bridge_off to breg base */
610 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),
611 E_BREG_BASE_LO);
612 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),
613 E_BREG_BASE_HI);
614
615 /* Enable BREG */
616 nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,
617 E_BREG_CONTROL);
618
619 /* Disable DMA channel registers */
620 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |
621 CFG_DMA_REG_BAR, BRCFG_PCIE_RX0);
622
623 /* Enable Ingress subtractive decode translation */
624 nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);
625
626 /* Enable msg filtering details */
627 nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,
628 BRCFG_PCIE_RX_MSG_FILTER);
629
630 err = nwl_wait_for_link(pcie);
631 if (err)
632 return err;
633
634 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;
635 if (!ecam_val) {
636 dev_err(pcie->dev, "ECAM is not present\n");
637 return ecam_val;
638 }
639
640 /* Enable ECAM */
641 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
642 E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
643
644 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
645 (pcie->ecam_value << E_ECAM_SIZE_SHIFT),
646 E_ECAM_CONTROL);
647
648 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
649 E_ECAM_BASE_LO);
650 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
651 E_ECAM_BASE_HI);
652
653 /* Get bus range */
654 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);
655 pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT;
656 /* Write primary, secondary and subordinate bus numbers */
657 ecam_val = first_busno;
658 ecam_val |= (first_busno + 1) << 8;
659 ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT);
660 writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS));
661
662 if (nwl_pcie_link_up(pcie))
663 dev_info(pcie->dev, "Link is UP\n");
664 else
665 dev_info(pcie->dev, "Link is DOWN\n");
666
667 /* Get misc IRQ number */
668 pcie->irq_misc = platform_get_irq_byname(pdev, "misc");
669 if (pcie->irq_misc < 0) {
670 dev_err(&pdev->dev, "failed to get misc IRQ %d\n",
671 pcie->irq_misc);
672 return -EINVAL;
673 }
674
675 err = devm_request_irq(pcie->dev, pcie->irq_misc,
676 nwl_pcie_misc_handler, IRQF_SHARED,
677 "nwl_pcie:misc", pcie);
678 if (err) {
679 dev_err(pcie->dev, "fail to register misc IRQ#%d\n",
680 pcie->irq_misc);
681 return err;
682 }
683
684 /* Disable all misc interrupts */
685 nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
686
687 /* Clear pending misc interrupts */
688 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
689 MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS);
690
691 /* Enable all misc interrupts */
692 nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
693
694
695 /* Disable all legacy interrupts */
696 nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
697
698 /* Clear pending legacy interrupts */
699 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
700 MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS);
701
702 /* Enable all legacy interrupts */
703 nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
704
705 /* Enable the bridge config interrupt */
706 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |
707 BRCFG_INTERRUPT_MASK, BRCFG_INTERRUPT);
708
709 return 0;
710}
711
712static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
713 struct platform_device *pdev)
714{
715 struct device_node *node = pcie->dev->of_node;
716 struct resource *res;
717 const char *type;
718
719 /* Check for device type */
720 type = of_get_property(node, "device_type", NULL);
721 if (!type || strcmp(type, "pci")) {
722 dev_err(pcie->dev, "invalid \"device_type\" %s\n", type);
723 return -EINVAL;
724 }
725
726 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
727 pcie->breg_base = devm_ioremap_resource(pcie->dev, res);
728 if (IS_ERR(pcie->breg_base))
729 return PTR_ERR(pcie->breg_base);
730 pcie->phys_breg_base = res->start;
731
732 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg");
733 pcie->pcireg_base = devm_ioremap_resource(pcie->dev, res);
734 if (IS_ERR(pcie->pcireg_base))
735 return PTR_ERR(pcie->pcireg_base);
736 pcie->phys_pcie_reg_base = res->start;
737
738 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
739 pcie->ecam_base = devm_ioremap_resource(pcie->dev, res);
740 if (IS_ERR(pcie->ecam_base))
741 return PTR_ERR(pcie->ecam_base);
742 pcie->phys_ecam_base = res->start;
743
744 /* Get intx IRQ number */
745 pcie->irq_intx = platform_get_irq_byname(pdev, "intx");
746 if (pcie->irq_intx < 0) {
747 dev_err(&pdev->dev, "failed to get intx IRQ %d\n",
748 pcie->irq_intx);
749 return -EINVAL;
750 }
751
752 irq_set_chained_handler_and_data(pcie->irq_intx,
753 nwl_pcie_leg_handler, pcie);
754
755 return 0;
756}
757
758static const struct of_device_id nwl_pcie_of_match[] = {
759 { .compatible = "xlnx,nwl-pcie-2.11", },
760 {}
761};
762
763static int nwl_pcie_probe(struct platform_device *pdev)
764{
765 struct device_node *node = pdev->dev.of_node;
766 struct nwl_pcie *pcie;
767 struct pci_bus *bus;
768 struct pci_bus *child;
769 int err;
770 resource_size_t iobase = 0;
771 LIST_HEAD(res);
772
773 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
774 if (!pcie)
775 return -ENOMEM;
776
777 pcie->dev = &pdev->dev;
778 pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT;
779
780 err = nwl_pcie_parse_dt(pcie, pdev);
781 if (err) {
782 dev_err(pcie->dev, "Parsing DT failed\n");
783 return err;
784 }
785
786 err = nwl_pcie_bridge_init(pcie);
787 if (err) {
dcbb408a 788 dev_err(pcie->dev, "HW Initialization failed\n");
ab597d35
BKG		 789 return err;
790 }
791
792 err = of_pci_get_host_bridge_resources(node, 0, 0xff, &res, &iobase);
793 if (err) {
9061f9be 794 dev_err(pcie->dev, "Getting bridge resources failed\n");
ab597d35
BKG		 795 return err;
796 }
797
21f7fc24
BH		 798 err = devm_request_pci_bus_resources(pcie->dev, &res);
799 if (err)
800 goto error;
801
ab597d35
BKG		 802 err = nwl_pcie_init_irq_domain(pcie);
803 if (err) {
804 dev_err(pcie->dev, "Failed creating IRQ Domain\n");
0bb01307 805 goto error;
ab597d35
BKG		 806 }
807
808 bus = pci_create_root_bus(&pdev->dev, pcie->root_busno,
809 &nwl_pcie_ops, pcie, &res);
0bb01307
BH		 810 if (!bus) {
811 err = -ENOMEM;
812 goto error;
813 }
ab597d35
BKG		 814
815 if (IS_ENABLED(CONFIG_PCI_MSI)) {
816 err = nwl_pcie_enable_msi(pcie, bus);
817 if (err < 0) {
818 dev_err(&pdev->dev,
819 "failed to enable MSI support: %d\n", err);
0bb01307 820 goto error;
ab597d35
BKG		 821 }
822 }
823 pci_scan_child_bus(bus);
824 pci_assign_unassigned_bus_resources(bus);
825 list_for_each_entry(child, &bus->children, node)
826 pcie_bus_configure_settings(child);
827 pci_bus_add_devices(bus);
828 platform_set_drvdata(pdev, pcie);
829 return 0;
0bb01307
BH		 830
831error:
832 pci_free_resource_list(&res);
833 return err;
ab597d35
BKG		 834}
835
ab597d35
BKG		 836static struct platform_driver nwl_pcie_driver = {
837 .driver = {
838 .name = "nwl-pcie",
ff187e77 839 .suppress_bind_attrs = true,
ab597d35
BKG		 840 .of_match_table = nwl_pcie_of_match,
841 },
842 .probe = nwl_pcie_probe,
ab597d35 843};
ff187e77 844builtin_platform_driver(nwl_pcie_driver);
Linux kernel - Deliverables
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