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drivers/pinctrl/intel/pinctrl-baytrail.c: fix build with gcc-4.4
[deliverable/linux.git] / drivers / pinctrl / intel / pinctrl-baytrail.c
CommitLineData
a5d811bb
MN		 1/*
2 * Pinctrl GPIO driver for Intel Baytrail
3 * Copyright (c) 2012-2013, Intel Corporation.
4 *
5 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
a5d811bb
MN		 15 */
16
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/types.h>
21#include <linux/bitops.h>
22#include <linux/interrupt.h>
86e3ef81 23#include <linux/gpio.h>
bf9a5c96 24#include <linux/gpio/driver.h>
a5d811bb 25#include <linux/acpi.h>
a5d811bb
MN		 26#include <linux/platform_device.h>
27#include <linux/seq_file.h>
28#include <linux/io.h>
29#include <linux/pm_runtime.h>
30#include <linux/pinctrl/pinctrl.h>
c501d0b1
CC		 31#include <linux/pinctrl/pinmux.h>
32#include <linux/pinctrl/pinconf.h>
33#include <linux/pinctrl/pinconf-generic.h>
a5d811bb
MN		 34
35/* memory mapped register offsets */
36#define BYT_CONF0_REG 0x000
37#define BYT_CONF1_REG 0x004
38#define BYT_VAL_REG 0x008
39#define BYT_DFT_REG 0x00c
40#define BYT_INT_STAT_REG 0x800
658b476c 41#define BYT_DEBOUNCE_REG 0x9d0
a5d811bb
MN		 42
43/* BYT_CONF0_REG register bits */
3ff95885 44#define BYT_IODEN BIT(31)
ff998356 45#define BYT_DIRECT_IRQ_EN BIT(27)
a5d811bb
MN		 46#define BYT_TRIG_NEG BIT(26)
47#define BYT_TRIG_POS BIT(25)
48#define BYT_TRIG_LVL BIT(24)
658b476c 49#define BYT_DEBOUNCE_EN BIT(20)
3ff95885
MW		 50#define BYT_PULL_STR_SHIFT 9
51#define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT)
52#define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
53#define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
54#define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
55#define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
56#define BYT_PULL_ASSIGN_SHIFT 7
57#define BYT_PULL_ASSIGN_MASK (3 << BYT_PULL_ASSIGN_SHIFT)
58#define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
59#define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
a5d811bb
MN		 60#define BYT_PIN_MUX 0x07
61
62/* BYT_VAL_REG register bits */
63#define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
64#define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
65#define BYT_LEVEL BIT(0)
66
67#define BYT_DIR_MASK (BIT(1) | BIT(2))
68#define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24))
69
fcc18deb
MW		 70#define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | \
71 BYT_PIN_MUX)
72#define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL)
73
658b476c
CC		 74/* BYT_DEBOUNCE_REG bits */
75#define BYT_DEBOUNCE_PULSE_MASK 0x7
76#define BYT_DEBOUNCE_PULSE_375US 1
77#define BYT_DEBOUNCE_PULSE_750US 2
78#define BYT_DEBOUNCE_PULSE_1500US 3
79#define BYT_DEBOUNCE_PULSE_3MS 4
80#define BYT_DEBOUNCE_PULSE_6MS 5
81#define BYT_DEBOUNCE_PULSE_12MS 6
82#define BYT_DEBOUNCE_PULSE_24MS 7
83
a5d811bb
MN		 84#define BYT_NGPIO_SCORE 102
85#define BYT_NGPIO_NCORE 28
86#define BYT_NGPIO_SUS 44
87
42bd0070
CKH		 88#define BYT_SCORE_ACPI_UID "1"
89#define BYT_NCORE_ACPI_UID "2"
90#define BYT_SUS_ACPI_UID "3"
91
c501d0b1
CC		 92/*
93 * This is the function value most pins have for GPIO muxing. If the value
94 * differs from the default one, it must be explicitly mentioned. Otherwise, the
95 * pin control implementation will set the muxing value to default GPIO if it
96 * does not find a match for the requested function.
97 */
98#define BYT_DEFAULT_GPIO_MUX 0
99
c8f5c4c7
CC		 100struct byt_gpio_pin_context {
101 u32 conf0;
102 u32 val;
103};
104
105struct byt_simple_func_mux {
106 const char *name;
107 unsigned short func;
108};
109
110struct byt_mixed_func_mux {
111 const char *name;
112 const unsigned short *func_values;
113};
114
115struct byt_pingroup {
116 const char *name;
117 const unsigned int *pins;
118 size_t npins;
119 unsigned short has_simple_funcs;
120 union {
121 const struct byt_simple_func_mux *simple_funcs;
122 const struct byt_mixed_func_mux *mixed_funcs;
123 };
124 size_t nfuncs;
125};
126
127struct byt_function {
128 const char *name;
129 const char * const *groups;
130 size_t ngroups;
131};
132
133struct byt_community {
134 unsigned int pin_base;
135 size_t npins;
136 const unsigned int *pad_map;
137 void __iomem *reg_base;
138};
139
140#define SIMPLE_FUNC(n, f) \
141 { \
142 .name = (n), \
143 .func = (f), \
144 }
145#define MIXED_FUNC(n, f) \
146 { \
147 .name = (n), \
148 .func_values = (f), \
149 }
150
151#define PIN_GROUP_SIMPLE(n, p, f) \
152 { \
153 .name = (n), \
154 .pins = (p), \
155 .npins = ARRAY_SIZE((p)), \
bbccb9c7
AM		 156 .has_simple_funcs = 1, \
157 { \
158 .simple_funcs = (f), \
159 }, \
c8f5c4c7
CC		 160 .nfuncs = ARRAY_SIZE((f)), \
161 }
162#define PIN_GROUP_MIXED(n, p, f) \
163 { \
164 .name = (n), \
165 .pins = (p), \
166 .npins = ARRAY_SIZE((p)), \
167 .has_simple_funcs = 0, \
bbccb9c7
AM		 168 { \
169 .mixed_funcs = (f), \
170 }, \
c8f5c4c7
CC		 171 .nfuncs = ARRAY_SIZE((f)), \
172 }
173
174#define FUNCTION(n, g) \
175 { \
176 .name = (n), \
177 .groups = (g), \
178 .ngroups = ARRAY_SIZE((g)), \
179 }
180
181#define COMMUNITY(p, n, map) \
182 { \
183 .pin_base = (p), \
184 .npins = (n), \
185 .pad_map = (map),\
186 }
a5d811bb 187
c8f5c4c7
CC		 188struct byt_pinctrl_soc_data {
189 const char *uid;
190 const struct pinctrl_pin_desc *pins;
191 size_t npins;
192 const struct byt_pingroup *groups;
193 size_t ngroups;
194 const struct byt_function *functions;
195 size_t nfunctions;
196 const struct byt_community *communities;
197 size_t ncommunities;
198};
199
71e6ca61
CC		 200struct byt_gpio {
201 struct gpio_chip chip;
202 struct platform_device *pdev;
203 struct pinctrl_dev *pctl_dev;
204 struct pinctrl_desc pctl_desc;
205 raw_spinlock_t lock;
206 const struct byt_pinctrl_soc_data *soc_data;
207 struct byt_community *communities_copy;
208 struct byt_gpio_pin_context *saved_context;
209};
210
c8f5c4c7
CC		 211/* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */
212static const struct pinctrl_pin_desc byt_score_pins[] = {
213 PINCTRL_PIN(0, "SATA_GP0"),
214 PINCTRL_PIN(1, "SATA_GP1"),
215 PINCTRL_PIN(2, "SATA_LED#"),
216 PINCTRL_PIN(3, "PCIE_CLKREQ0"),
217 PINCTRL_PIN(4, "PCIE_CLKREQ1"),
218 PINCTRL_PIN(5, "PCIE_CLKREQ2"),
219 PINCTRL_PIN(6, "PCIE_CLKREQ3"),
220 PINCTRL_PIN(7, "SD3_WP"),
221 PINCTRL_PIN(8, "HDA_RST"),
222 PINCTRL_PIN(9, "HDA_SYNC"),
223 PINCTRL_PIN(10, "HDA_CLK"),
224 PINCTRL_PIN(11, "HDA_SDO"),
225 PINCTRL_PIN(12, "HDA_SDI0"),
226 PINCTRL_PIN(13, "HDA_SDI1"),
227 PINCTRL_PIN(14, "GPIO_S0_SC14"),
228 PINCTRL_PIN(15, "GPIO_S0_SC15"),
229 PINCTRL_PIN(16, "MMC1_CLK"),
230 PINCTRL_PIN(17, "MMC1_D0"),
231 PINCTRL_PIN(18, "MMC1_D1"),
232 PINCTRL_PIN(19, "MMC1_D2"),
233 PINCTRL_PIN(20, "MMC1_D3"),
234 PINCTRL_PIN(21, "MMC1_D4"),
235 PINCTRL_PIN(22, "MMC1_D5"),
236 PINCTRL_PIN(23, "MMC1_D6"),
237 PINCTRL_PIN(24, "MMC1_D7"),
238 PINCTRL_PIN(25, "MMC1_CMD"),
239 PINCTRL_PIN(26, "MMC1_RST"),
240 PINCTRL_PIN(27, "SD2_CLK"),
241 PINCTRL_PIN(28, "SD2_D0"),
242 PINCTRL_PIN(29, "SD2_D1"),
243 PINCTRL_PIN(30, "SD2_D2"),
244 PINCTRL_PIN(31, "SD2_D3_CD"),
245 PINCTRL_PIN(32, "SD2_CMD"),
246 PINCTRL_PIN(33, "SD3_CLK"),
247 PINCTRL_PIN(34, "SD3_D0"),
248 PINCTRL_PIN(35, "SD3_D1"),
249 PINCTRL_PIN(36, "SD3_D2"),
250 PINCTRL_PIN(37, "SD3_D3"),
251 PINCTRL_PIN(38, "SD3_CD"),
252 PINCTRL_PIN(39, "SD3_CMD"),
253 PINCTRL_PIN(40, "SD3_1P8EN"),
254 PINCTRL_PIN(41, "SD3_PWREN#"),
255 PINCTRL_PIN(42, "ILB_LPC_AD0"),
256 PINCTRL_PIN(43, "ILB_LPC_AD1"),
257 PINCTRL_PIN(44, "ILB_LPC_AD2"),
258 PINCTRL_PIN(45, "ILB_LPC_AD3"),
259 PINCTRL_PIN(46, "ILB_LPC_FRAME"),
260 PINCTRL_PIN(47, "ILB_LPC_CLK0"),
261 PINCTRL_PIN(48, "ILB_LPC_CLK1"),
262 PINCTRL_PIN(49, "ILB_LPC_CLKRUN"),
263 PINCTRL_PIN(50, "ILB_LPC_SERIRQ"),
264 PINCTRL_PIN(51, "PCU_SMB_DATA"),
265 PINCTRL_PIN(52, "PCU_SMB_CLK"),
266 PINCTRL_PIN(53, "PCU_SMB_ALERT"),
267 PINCTRL_PIN(54, "ILB_8254_SPKR"),
268 PINCTRL_PIN(55, "GPIO_S0_SC55"),
269 PINCTRL_PIN(56, "GPIO_S0_SC56"),
270 PINCTRL_PIN(57, "GPIO_S0_SC57"),
271 PINCTRL_PIN(58, "GPIO_S0_SC58"),
272 PINCTRL_PIN(59, "GPIO_S0_SC59"),
273 PINCTRL_PIN(60, "GPIO_S0_SC60"),
274 PINCTRL_PIN(61, "GPIO_S0_SC61"),
275 PINCTRL_PIN(62, "LPE_I2S2_CLK"),
276 PINCTRL_PIN(63, "LPE_I2S2_FRM"),
277 PINCTRL_PIN(64, "LPE_I2S2_DATAIN"),
278 PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"),
279 PINCTRL_PIN(66, "SIO_SPI_CS"),
280 PINCTRL_PIN(67, "SIO_SPI_MISO"),
281 PINCTRL_PIN(68, "SIO_SPI_MOSI"),
282 PINCTRL_PIN(69, "SIO_SPI_CLK"),
283 PINCTRL_PIN(70, "SIO_UART1_RXD"),
284 PINCTRL_PIN(71, "SIO_UART1_TXD"),
285 PINCTRL_PIN(72, "SIO_UART1_RTS"),
286 PINCTRL_PIN(73, "SIO_UART1_CTS"),
287 PINCTRL_PIN(74, "SIO_UART2_RXD"),
288 PINCTRL_PIN(75, "SIO_UART2_TXD"),
289 PINCTRL_PIN(76, "SIO_UART2_RTS"),
290 PINCTRL_PIN(77, "SIO_UART2_CTS"),
291 PINCTRL_PIN(78, "SIO_I2C0_DATA"),
292 PINCTRL_PIN(79, "SIO_I2C0_CLK"),
293 PINCTRL_PIN(80, "SIO_I2C1_DATA"),
294 PINCTRL_PIN(81, "SIO_I2C1_CLK"),
295 PINCTRL_PIN(82, "SIO_I2C2_DATA"),
296 PINCTRL_PIN(83, "SIO_I2C2_CLK"),
297 PINCTRL_PIN(84, "SIO_I2C3_DATA"),
298 PINCTRL_PIN(85, "SIO_I2C3_CLK"),
299 PINCTRL_PIN(86, "SIO_I2C4_DATA"),
300 PINCTRL_PIN(87, "SIO_I2C4_CLK"),
301 PINCTRL_PIN(88, "SIO_I2C5_DATA"),
302 PINCTRL_PIN(89, "SIO_I2C5_CLK"),
303 PINCTRL_PIN(90, "SIO_I2C6_DATA"),
304 PINCTRL_PIN(91, "SIO_I2C6_CLK"),
305 PINCTRL_PIN(92, "GPIO_S0_SC92"),
306 PINCTRL_PIN(93, "GPIO_S0_SC93"),
307 PINCTRL_PIN(94, "SIO_PWM0"),
308 PINCTRL_PIN(95, "SIO_PWM1"),
309 PINCTRL_PIN(96, "PMC_PLT_CLK0"),
310 PINCTRL_PIN(97, "PMC_PLT_CLK1"),
311 PINCTRL_PIN(98, "PMC_PLT_CLK2"),
312 PINCTRL_PIN(99, "PMC_PLT_CLK3"),
313 PINCTRL_PIN(100, "PMC_PLT_CLK4"),
314 PINCTRL_PIN(101, "PMC_PLT_CLK5"),
315};
a5d811bb 316
c8f5c4c7
CC		 317static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = {
318 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
319 36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
320 54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
321 52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
322 95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
323 86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
324 80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
325 2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
326 31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
327 24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
328 97, 100,
329};
330
331/* SCORE groups */
332static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 };
333static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 };
334static const struct byt_simple_func_mux byt_score_uart_mux[] = {
335 SIMPLE_FUNC("uart", 1),
336};
337
338static const unsigned int byt_score_pwm0_pins[] = { 94 };
339static const unsigned int byt_score_pwm1_pins[] = { 95 };
340static const struct byt_simple_func_mux byt_score_pwm_mux[] = {
341 SIMPLE_FUNC("pwm", 1),
342};
343
344static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 };
345static const struct byt_simple_func_mux byt_score_spi_mux[] = {
346 SIMPLE_FUNC("spi", 1),
347};
348
349static const unsigned int byt_score_i2c5_pins[] = { 88, 89 };
350static const unsigned int byt_score_i2c6_pins[] = { 90, 91 };
351static const unsigned int byt_score_i2c4_pins[] = { 86, 87 };
352static const unsigned int byt_score_i2c3_pins[] = { 84, 85 };
353static const unsigned int byt_score_i2c2_pins[] = { 82, 83 };
354static const unsigned int byt_score_i2c1_pins[] = { 80, 81 };
355static const unsigned int byt_score_i2c0_pins[] = { 78, 79 };
356static const struct byt_simple_func_mux byt_score_i2c_mux[] = {
357 SIMPLE_FUNC("i2c", 1),
358};
359
360static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 };
361static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 };
362static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 };
363static const struct byt_simple_func_mux byt_score_ssp_mux[] = {
364 SIMPLE_FUNC("ssp", 1),
365};
366
367static const unsigned int byt_score_sdcard_pins[] = {
368 7, 33, 34, 35, 36, 37, 38, 39, 40, 41,
369};
370static const unsigned short byt_score_sdcard_mux_values[] = {
371 2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
372};
373static const struct byt_mixed_func_mux byt_score_sdcard_mux[] = {
374 MIXED_FUNC("sdcard", byt_score_sdcard_mux_values),
375};
376
377static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 };
378static const struct byt_simple_func_mux byt_score_sdio_mux[] = {
379 SIMPLE_FUNC("sdio", 1),
380};
381
382static const unsigned int byt_score_emmc_pins[] = {
383 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
384};
385static const struct byt_simple_func_mux byt_score_emmc_mux[] = {
386 SIMPLE_FUNC("emmc", 1),
387};
388
389static const unsigned int byt_score_ilb_lpc_pins[] = {
390 42, 43, 44, 45, 46, 47, 48, 49, 50,
391};
392static const struct byt_simple_func_mux byt_score_lpc_mux[] = {
393 SIMPLE_FUNC("lpc", 1),
394};
395
396static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 };
397static const struct byt_simple_func_mux byt_score_sata_mux[] = {
398 SIMPLE_FUNC("sata", 1),
399};
400
401static const unsigned int byt_score_plt_clk0_pins[] = { 96 };
402static const unsigned int byt_score_plt_clk1_pins[] = { 97 };
403static const unsigned int byt_score_plt_clk2_pins[] = { 98 };
404static const unsigned int byt_score_plt_clk4_pins[] = { 99 };
405static const unsigned int byt_score_plt_clk5_pins[] = { 100 };
406static const unsigned int byt_score_plt_clk3_pins[] = { 101 };
407static const struct byt_simple_func_mux byt_score_plt_clk_mux[] = {
408 SIMPLE_FUNC("plt_clk", 1),
a5d811bb
MN		 409};
410
c8f5c4c7
CC		 411static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 };
412static const struct byt_simple_func_mux byt_score_smbus_mux[] = {
413 SIMPLE_FUNC("smbus", 1),
414};
415
416static const struct byt_pingroup byt_score_groups[] = {
417 PIN_GROUP_SIMPLE("uart1_grp",
418 byt_score_uart1_pins, byt_score_uart_mux),
419 PIN_GROUP_SIMPLE("uart2_grp",
420 byt_score_uart2_pins, byt_score_uart_mux),
421 PIN_GROUP_SIMPLE("pwm0_grp",
422 byt_score_pwm0_pins, byt_score_pwm_mux),
423 PIN_GROUP_SIMPLE("pwm1_grp",
424 byt_score_pwm1_pins, byt_score_pwm_mux),
425 PIN_GROUP_SIMPLE("ssp2_grp",
426 byt_score_ssp2_pins, byt_score_pwm_mux),
427 PIN_GROUP_SIMPLE("sio_spi_grp",
428 byt_score_sio_spi_pins, byt_score_spi_mux),
429 PIN_GROUP_SIMPLE("i2c5_grp",
430 byt_score_i2c5_pins, byt_score_i2c_mux),
431 PIN_GROUP_SIMPLE("i2c6_grp",
432 byt_score_i2c6_pins, byt_score_i2c_mux),
433 PIN_GROUP_SIMPLE("i2c4_grp",
434 byt_score_i2c4_pins, byt_score_i2c_mux),
435 PIN_GROUP_SIMPLE("i2c3_grp",
436 byt_score_i2c3_pins, byt_score_i2c_mux),
437 PIN_GROUP_SIMPLE("i2c2_grp",
438 byt_score_i2c2_pins, byt_score_i2c_mux),
439 PIN_GROUP_SIMPLE("i2c1_grp",
440 byt_score_i2c1_pins, byt_score_i2c_mux),
441 PIN_GROUP_SIMPLE("i2c0_grp",
442 byt_score_i2c0_pins, byt_score_i2c_mux),
443 PIN_GROUP_SIMPLE("ssp0_grp",
444 byt_score_ssp0_pins, byt_score_ssp_mux),
445 PIN_GROUP_SIMPLE("ssp1_grp",
446 byt_score_ssp1_pins, byt_score_ssp_mux),
447 PIN_GROUP_MIXED("sdcard_grp",
448 byt_score_sdcard_pins, byt_score_sdcard_mux),
449 PIN_GROUP_SIMPLE("sdio_grp",
450 byt_score_sdio_pins, byt_score_sdio_mux),
451 PIN_GROUP_SIMPLE("emmc_grp",
452 byt_score_emmc_pins, byt_score_emmc_mux),
453 PIN_GROUP_SIMPLE("lpc_grp",
454 byt_score_ilb_lpc_pins, byt_score_lpc_mux),
455 PIN_GROUP_SIMPLE("sata_grp",
456 byt_score_sata_pins, byt_score_sata_mux),
457 PIN_GROUP_SIMPLE("plt_clk0_grp",
458 byt_score_plt_clk0_pins, byt_score_plt_clk_mux),
459 PIN_GROUP_SIMPLE("plt_clk1_grp",
460 byt_score_plt_clk1_pins, byt_score_plt_clk_mux),
461 PIN_GROUP_SIMPLE("plt_clk2_grp",
462 byt_score_plt_clk2_pins, byt_score_plt_clk_mux),
463 PIN_GROUP_SIMPLE("plt_clk3_grp",
464 byt_score_plt_clk3_pins, byt_score_plt_clk_mux),
465 PIN_GROUP_SIMPLE("plt_clk4_grp",
466 byt_score_plt_clk4_pins, byt_score_plt_clk_mux),
467 PIN_GROUP_SIMPLE("plt_clk5_grp",
468 byt_score_plt_clk5_pins, byt_score_plt_clk_mux),
469 PIN_GROUP_SIMPLE("smbus_grp",
470 byt_score_smbus_pins, byt_score_smbus_mux),
471};
472
473static const char * const byt_score_uart_groups[] = {
474 "uart1_grp", "uart2_grp",
475};
476static const char * const byt_score_pwm_groups[] = {
477 "pwm0_grp", "pwm1_grp",
478};
479static const char * const byt_score_ssp_groups[] = {
480 "ssp0_grp", "ssp1_grp", "ssp2_grp",
481};
482static const char * const byt_score_spi_groups[] = { "sio_spi_grp" };
483static const char * const byt_score_i2c_groups[] = {
484 "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp",
485 "i2c6_grp",
486};
487static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" };
488static const char * const byt_score_sdio_groups[] = { "sdio_grp" };
489static const char * const byt_score_emmc_groups[] = { "emmc_grp" };
490static const char * const byt_score_lpc_groups[] = { "lpc_grp" };
491static const char * const byt_score_sata_groups[] = { "sata_grp" };
492static const char * const byt_score_plt_clk_groups[] = {
493 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
494 "plt_clk4_grp", "plt_clk5_grp",
495};
496static const char * const byt_score_smbus_groups[] = { "smbus_grp" };
497static const char * const byt_score_gpio_groups[] = {
498 "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp",
499 "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp",
500 "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp",
501 "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp",
502 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
503 "plt_clk4_grp", "plt_clk5_grp", "smbus_grp",
504
505};
506
507static const struct byt_function byt_score_functions[] = {
508 FUNCTION("uart", byt_score_uart_groups),
509 FUNCTION("pwm", byt_score_pwm_groups),
510 FUNCTION("ssp", byt_score_ssp_groups),
511 FUNCTION("spi", byt_score_spi_groups),
512 FUNCTION("i2c", byt_score_i2c_groups),
513 FUNCTION("sdcard", byt_score_sdcard_groups),
514 FUNCTION("sdio", byt_score_sdio_groups),
515 FUNCTION("emmc", byt_score_emmc_groups),
516 FUNCTION("lpc", byt_score_lpc_groups),
517 FUNCTION("sata", byt_score_sata_groups),
518 FUNCTION("plt_clk", byt_score_plt_clk_groups),
519 FUNCTION("smbus", byt_score_smbus_groups),
520 FUNCTION("gpio", byt_score_gpio_groups),
521};
522
523static const struct byt_community byt_score_communities[] = {
524 COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
525};
526
527static const struct byt_pinctrl_soc_data byt_score_soc_data = {
528 .uid = BYT_SCORE_ACPI_UID,
529 .pins = byt_score_pins,
530 .npins = ARRAY_SIZE(byt_score_pins),
531 .groups = byt_score_groups,
532 .ngroups = ARRAY_SIZE(byt_score_groups),
533 .functions = byt_score_functions,
534 .nfunctions = ARRAY_SIZE(byt_score_functions),
535 .communities = byt_score_communities,
536 .ncommunities = ARRAY_SIZE(byt_score_communities),
537};
538
539/* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>] */
540static const struct pinctrl_pin_desc byt_sus_pins[] = {
541 PINCTRL_PIN(0, "GPIO_S50"),
542 PINCTRL_PIN(1, "GPIO_S51"),
543 PINCTRL_PIN(2, "GPIO_S52"),
544 PINCTRL_PIN(3, "GPIO_S53"),
545 PINCTRL_PIN(4, "GPIO_S54"),
546 PINCTRL_PIN(5, "GPIO_S55"),
547 PINCTRL_PIN(6, "GPIO_S56"),
548 PINCTRL_PIN(7, "GPIO_S57"),
549 PINCTRL_PIN(8, "GPIO_S58"),
550 PINCTRL_PIN(9, "GPIO_S59"),
551 PINCTRL_PIN(10, "GPIO_S510"),
552 PINCTRL_PIN(11, "PMC_SUSPWRDNACK"),
553 PINCTRL_PIN(12, "PMC_SUSCLK0"),
554 PINCTRL_PIN(13, "GPIO_S513"),
555 PINCTRL_PIN(14, "USB_ULPI_RST"),
556 PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"),
557 PINCTRL_PIN(16, "PMC_PWRBTN"),
558 PINCTRL_PIN(17, "GPIO_S517"),
559 PINCTRL_PIN(18, "PMC_SUS_STAT"),
560 PINCTRL_PIN(19, "USB_OC0"),
561 PINCTRL_PIN(20, "USB_OC1"),
562 PINCTRL_PIN(21, "PCU_SPI_CS1"),
563 PINCTRL_PIN(22, "GPIO_S522"),
564 PINCTRL_PIN(23, "GPIO_S523"),
565 PINCTRL_PIN(24, "GPIO_S524"),
566 PINCTRL_PIN(25, "GPIO_S525"),
567 PINCTRL_PIN(26, "GPIO_S526"),
568 PINCTRL_PIN(27, "GPIO_S527"),
569 PINCTRL_PIN(28, "GPIO_S528"),
570 PINCTRL_PIN(29, "GPIO_S529"),
571 PINCTRL_PIN(30, "GPIO_S530"),
572 PINCTRL_PIN(31, "USB_ULPI_CLK"),
573 PINCTRL_PIN(32, "USB_ULPI_DATA0"),
574 PINCTRL_PIN(33, "USB_ULPI_DATA1"),
575 PINCTRL_PIN(34, "USB_ULPI_DATA2"),
576 PINCTRL_PIN(35, "USB_ULPI_DATA3"),
577 PINCTRL_PIN(36, "USB_ULPI_DATA4"),
578 PINCTRL_PIN(37, "USB_ULPI_DATA5"),
579 PINCTRL_PIN(38, "USB_ULPI_DATA6"),
580 PINCTRL_PIN(39, "USB_ULPI_DATA7"),
581 PINCTRL_PIN(40, "USB_ULPI_DIR"),
582 PINCTRL_PIN(41, "USB_ULPI_NXT"),
583 PINCTRL_PIN(42, "USB_ULPI_STP"),
584 PINCTRL_PIN(43, "USB_ULPI_REFCLK"),
585};
586
c8f5c4c7 587static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = {
a5d811bb
MN		 588 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
589 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
590 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
591 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
592 52, 53, 59, 40,
593};
594
c8f5c4c7
CC		 595static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 };
596static const struct byt_simple_func_mux byt_sus_usb_oc_mux[] = {
597 SIMPLE_FUNC("usb", 0),
598 SIMPLE_FUNC("gpio", 1),
599};
600
601static const unsigned int byt_sus_usb_ulpi_pins[] = {
602 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
603};
604static const unsigned short byt_sus_usb_ulpi_mode_values[] = {
605 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
606};
607static const unsigned short byt_sus_usb_ulpi_gpio_mode_values[] = {
608 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
609};
610static const struct byt_mixed_func_mux byt_sus_usb_ulpi_mux[] = {
611 MIXED_FUNC("usb", byt_sus_usb_ulpi_mode_values),
612 MIXED_FUNC("gpio", byt_sus_usb_ulpi_gpio_mode_values),
613};
614
615static const unsigned int byt_sus_pcu_spi_pins[] = { 21 };
616static const struct byt_simple_func_mux byt_sus_pcu_spi_mux[] = {
617 SIMPLE_FUNC("spi", 0),
618 SIMPLE_FUNC("gpio", 1),
619};
620
621static const struct byt_pingroup byt_sus_groups[] = {
622 PIN_GROUP_SIMPLE("usb_oc_grp",
623 byt_sus_usb_over_current_pins, byt_sus_usb_oc_mux),
624 PIN_GROUP_MIXED("usb_ulpi_grp",
625 byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mux),
626 PIN_GROUP_SIMPLE("pcu_spi_grp",
627 byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mux),
628};
629
630static const char * const byt_sus_usb_groups[] = {
631 "usb_oc_grp", "usb_ulpi_grp",
632};
633static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" };
634static const char * const byt_sus_gpio_groups[] = {
635 "usb_oc_grp", "usb_ulpi_grp", "pcu_spi_grp",
636};
637
638static const struct byt_function byt_sus_functions[] = {
639 FUNCTION("usb", byt_sus_usb_groups),
640 FUNCTION("spi", byt_sus_spi_groups),
641 FUNCTION("gpio", byt_sus_gpio_groups),
642};
643
644static const struct byt_community byt_sus_communities[] = {
645 COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
646};
647
648static const struct byt_pinctrl_soc_data byt_sus_soc_data = {
649 .uid = BYT_SUS_ACPI_UID,
650 .pins = byt_sus_pins,
651 .npins = ARRAY_SIZE(byt_sus_pins),
652 .groups = byt_sus_groups,
653 .ngroups = ARRAY_SIZE(byt_sus_groups),
654 .functions = byt_sus_functions,
655 .nfunctions = ARRAY_SIZE(byt_sus_functions),
656 .communities = byt_sus_communities,
657 .ncommunities = ARRAY_SIZE(byt_sus_communities),
658};
659
660static const struct pinctrl_pin_desc byt_ncore_pins[] = {
661 PINCTRL_PIN(0, "GPIO_NCORE0"),
662 PINCTRL_PIN(1, "GPIO_NCORE1"),
663 PINCTRL_PIN(2, "GPIO_NCORE2"),
664 PINCTRL_PIN(3, "GPIO_NCORE3"),
665 PINCTRL_PIN(4, "GPIO_NCORE4"),
666 PINCTRL_PIN(5, "GPIO_NCORE5"),
667 PINCTRL_PIN(6, "GPIO_NCORE6"),
668 PINCTRL_PIN(7, "GPIO_NCORE7"),
669 PINCTRL_PIN(8, "GPIO_NCORE8"),
670 PINCTRL_PIN(9, "GPIO_NCORE9"),
671 PINCTRL_PIN(10, "GPIO_NCORE10"),
672 PINCTRL_PIN(11, "GPIO_NCORE11"),
673 PINCTRL_PIN(12, "GPIO_NCORE12"),
674 PINCTRL_PIN(13, "GPIO_NCORE13"),
675 PINCTRL_PIN(14, "GPIO_NCORE14"),
676 PINCTRL_PIN(15, "GPIO_NCORE15"),
677 PINCTRL_PIN(16, "GPIO_NCORE16"),
678 PINCTRL_PIN(17, "GPIO_NCORE17"),
679 PINCTRL_PIN(18, "GPIO_NCORE18"),
680 PINCTRL_PIN(19, "GPIO_NCORE19"),
681 PINCTRL_PIN(20, "GPIO_NCORE20"),
682 PINCTRL_PIN(21, "GPIO_NCORE21"),
683 PINCTRL_PIN(22, "GPIO_NCORE22"),
684 PINCTRL_PIN(23, "GPIO_NCORE23"),
685 PINCTRL_PIN(24, "GPIO_NCORE24"),
686 PINCTRL_PIN(25, "GPIO_NCORE25"),
687 PINCTRL_PIN(26, "GPIO_NCORE26"),
688 PINCTRL_PIN(27, "GPIO_NCORE27"),
689};
690
691static unsigned const byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
692 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
693 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
694 3, 6, 10, 13, 2, 5, 9, 7,
695};
696
697static const struct byt_community byt_ncore_communities[] = {
698 COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
699};
700
701static const struct byt_pinctrl_soc_data byt_ncore_soc_data = {
702 .uid = BYT_NCORE_ACPI_UID,
703 .pins = byt_ncore_pins,
704 .npins = ARRAY_SIZE(byt_ncore_pins),
705 .communities = byt_ncore_communities,
706 .ncommunities = ARRAY_SIZE(byt_ncore_communities),
707};
708
c8f5c4c7
CC		 709static const struct byt_pinctrl_soc_data *byt_soc_data[] = {
710 &byt_score_soc_data,
711 &byt_sus_soc_data,
712 &byt_ncore_soc_data,
713 NULL,
714};
715
c501d0b1
CC		 716static struct byt_community *byt_get_community(struct byt_gpio *vg,
717 unsigned int pin)
a5d811bb 718{
c501d0b1
CC		 719 struct byt_community *comm;
720 int i;
721
722 for (i = 0; i < vg->soc_data->ncommunities; i++) {
723 comm = vg->communities_copy + i;
724 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)
725 return comm;
726 }
a5d811bb 727
c501d0b1
CC		 728 return NULL;
729}
730
731static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset,
732 int reg)
733{
734 struct byt_community *comm = byt_get_community(vg, offset);
735 u32 reg_offset = 0;
736
737 if (!comm)
738 return NULL;
739
740 offset -= comm->pin_base;
a5d811bb
MN		 741 if (reg == BYT_INT_STAT_REG)
742 reg_offset = (offset / 32) * 4;
743 else
c501d0b1
CC		 744 reg_offset = comm->pad_map[offset] * 16;
745
746 return comm->reg_base + reg_offset + reg;
747}
748
749static int byt_get_groups_count(struct pinctrl_dev *pctldev)
750{
751 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
752
753 return vg->soc_data->ngroups;
754}
755
756static const char *byt_get_group_name(struct pinctrl_dev *pctldev,
757 unsigned int selector)
758{
759 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
760
761 return vg->soc_data->groups[selector].name;
762}
763
764static int byt_get_group_pins(struct pinctrl_dev *pctldev,
765 unsigned int selector,
766 const unsigned int **pins,
767 unsigned int *num_pins)
768{
769 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
770
771 *pins = vg->soc_data->groups[selector].pins;
772 *num_pins = vg->soc_data->groups[selector].npins;
773
774 return 0;
775}
776
777static const struct pinctrl_ops byt_pinctrl_ops = {
778 .get_groups_count = byt_get_groups_count,
779 .get_group_name = byt_get_group_name,
780 .get_group_pins = byt_get_group_pins,
781};
782
783static int byt_get_functions_count(struct pinctrl_dev *pctldev)
784{
785 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
786
787 return vg->soc_data->nfunctions;
788}
789
790static const char *byt_get_function_name(struct pinctrl_dev *pctldev,
791 unsigned int selector)
792{
793 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
794
795 return vg->soc_data->functions[selector].name;
796}
797
798static int byt_get_function_groups(struct pinctrl_dev *pctldev,
799 unsigned int selector,
800 const char * const **groups,
801 unsigned int *num_groups)
802{
803 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
804
805 *groups = vg->soc_data->functions[selector].groups;
806 *num_groups = vg->soc_data->functions[selector].ngroups;
807
808 return 0;
809}
810
811static int byt_get_group_simple_mux(const struct byt_pingroup group,
812 const char *func_name,
813 unsigned short *func)
814{
815 int i;
816
817 for (i = 0; i < group.nfuncs; i++) {
818 if (!strcmp(group.simple_funcs[i].name, func_name)) {
819 *func = group.simple_funcs[i].func;
820 return 0;
821 }
822 }
823
824 return 1;
825}
826
827static int byt_get_group_mixed_mux(const struct byt_pingroup group,
828 const char *func_name,
829 const unsigned short **func)
830{
831 int i;
832
833 for (i = 0; i < group.nfuncs; i++) {
834 if (!strcmp(group.mixed_funcs[i].name, func_name)) {
835 *func = group.mixed_funcs[i].func_values;
836 return 0;
837 }
838 }
a5d811bb 839
c501d0b1 840 return 1;
a5d811bb
MN		 841}
842
c501d0b1
CC		 843static void byt_set_group_simple_mux(struct byt_gpio *vg,
844 const struct byt_pingroup group,
845 unsigned short func)
95f0972c 846{
95f0972c 847 unsigned long flags;
c501d0b1 848 int i;
95f0972c 849
78e1c896 850 raw_spin_lock_irqsave(&vg->lock, flags);
c501d0b1
CC		 851
852 for (i = 0; i < group.npins; i++) {
853 void __iomem *padcfg0;
854 u32 value;
855
856 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
857 if (!padcfg0) {
858 dev_warn(&vg->pdev->dev,
859 "Group %s, pin %i not muxed (no padcfg0)\n",
860 group.name, i);
861 continue;
862 }
863
864 value = readl(padcfg0);
865 value &= ~BYT_PIN_MUX;
866 value |= func;
867 writel(value, padcfg0);
868 }
869
78e1c896 870 raw_spin_unlock_irqrestore(&vg->lock, flags);
95f0972c
MW		 871}
872
c501d0b1
CC		 873static void byt_set_group_mixed_mux(struct byt_gpio *vg,
874 const struct byt_pingroup group,
875 const unsigned short *func)
876{
877 unsigned long flags;
878 int i;
879
880 raw_spin_lock_irqsave(&vg->lock, flags);
881
882 for (i = 0; i < group.npins; i++) {
883 void __iomem *padcfg0;
884 u32 value;
885
886 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
887 if (!padcfg0) {
888 dev_warn(&vg->pdev->dev,
889 "Group %s, pin %i not muxed (no padcfg0)\n",
890 group.name, i);
891 continue;
892 }
893
894 value = readl(padcfg0);
895 value &= ~BYT_PIN_MUX;
896 value |= func[i];
897 writel(value, padcfg0);
898 }
899
900 raw_spin_unlock_irqrestore(&vg->lock, flags);
901}
902
903static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
904 unsigned int group_selector)
905{
906 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
907 const struct byt_function func = vg->soc_data->functions[func_selector];
908 const struct byt_pingroup group = vg->soc_data->groups[group_selector];
909 const unsigned short *mixed_func;
910 unsigned short simple_func;
911 int ret = 1;
912
913 if (group.has_simple_funcs)
914 ret = byt_get_group_simple_mux(group, func.name, &simple_func);
915 else
916 ret = byt_get_group_mixed_mux(group, func.name, &mixed_func);
917
918 if (ret)
919 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
920 else if (group.has_simple_funcs)
921 byt_set_group_simple_mux(vg, group, simple_func);
922 else
923 byt_set_group_mixed_mux(vg, group, mixed_func);
924
925 return 0;
926}
927
f8323b6b 928static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned offset)
42bd0070
CKH		 929{
930 /* SCORE pin 92-93 */
c501d0b1
CC		 931 if (!strcmp(vg->soc_data->uid, BYT_SCORE_ACPI_UID) &&
932 offset >= 92 && offset <= 93)
f8323b6b 933 return 1;
42bd0070
CKH		 934
935 /* SUS pin 11-21 */
c501d0b1
CC		 936 if (!strcmp(vg->soc_data->uid, BYT_SUS_ACPI_UID) &&
937 offset >= 11 && offset <= 21)
f8323b6b 938 return 1;
42bd0070 939
f8323b6b 940 return 0;
42bd0070
CKH		 941}
942
c501d0b1 943static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset)
a5d811bb 944{
c501d0b1
CC		 945 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
946 unsigned long flags;
947 u32 value;
948
949 raw_spin_lock_irqsave(&vg->lock, flags);
950 value = readl(reg);
951 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
952 writel(value, reg);
953 raw_spin_unlock_irqrestore(&vg->lock, flags);
954}
955
956static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
957 struct pinctrl_gpio_range *range,
958 unsigned int offset)
959{
960 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
961 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
f8323b6b 962 u32 value, gpio_mux;
39ce8150
MW		 963 unsigned long flags;
964
78e1c896 965 raw_spin_lock_irqsave(&vg->lock, flags);
42bd0070
CKH		 966
967 /*
968 * In most cases, func pin mux 000 means GPIO function.
969 * But, some pins may have func pin mux 001 represents
f8323b6b
MW		 970 * GPIO function.
971 *
972 * Because there are devices out there where some pins were not
973 * configured correctly we allow changing the mux value from
974 * request (but print out warning about that).
42bd0070
CKH		 975 */
976 value = readl(reg) & BYT_PIN_MUX;
f8323b6b
MW		 977 gpio_mux = byt_get_gpio_mux(vg, offset);
978 if (WARN_ON(gpio_mux != value)) {
f8323b6b
MW		 979 value = readl(reg) & ~BYT_PIN_MUX;
980 value |= gpio_mux;
981 writel(value, reg);
f8323b6b
MW		 982
983 dev_warn(&vg->pdev->dev,
984 "pin %u forcibly re-configured as GPIO\n", offset);
42bd0070 985 }
a5d811bb 986
78e1c896 987 raw_spin_unlock_irqrestore(&vg->lock, flags);
39ce8150 988
a5d811bb
MN		 989 pm_runtime_get(&vg->pdev->dev);
990
991 return 0;
992}
993
c501d0b1
CC		 994static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev,
995 struct pinctrl_gpio_range *range,
996 unsigned int offset)
997{
998 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
999
1000 byt_gpio_clear_triggering(vg, offset);
1001 pm_runtime_put(&vg->pdev->dev);
1002}
1003
1004static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
1005 struct pinctrl_gpio_range *range,
1006 unsigned int offset,
1007 bool input)
1008{
1009 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1010 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1011 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1012 unsigned long flags;
1013 u32 value;
1014
1015 raw_spin_lock_irqsave(&vg->lock, flags);
1016
1017 value = readl(val_reg);
1018 value &= ~BYT_DIR_MASK;
1019 if (input)
1020 value |= BYT_OUTPUT_EN;
1021 else
1022 /*
1023 * Before making any direction modifications, do a check if gpio
1024 * is set for direct IRQ. On baytrail, setting GPIO to output
1025 * does not make sense, so let's at least warn the caller before
1026 * they shoot themselves in the foot.
1027 */
1028 WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,
1029 "Potential Error: Setting GPIO with direct_irq_en to output");
1030 writel(value, val_reg);
1031
1032 raw_spin_unlock_irqrestore(&vg->lock, flags);
1033
1034 return 0;
1035}
1036
1037static const struct pinmux_ops byt_pinmux_ops = {
1038 .get_functions_count = byt_get_functions_count,
1039 .get_function_name = byt_get_function_name,
1040 .get_function_groups = byt_get_function_groups,
1041 .set_mux = byt_set_mux,
1042 .gpio_request_enable = byt_gpio_request_enable,
1043 .gpio_disable_free = byt_gpio_disable_free,
1044 .gpio_set_direction = byt_gpio_set_direction,
1045};
1046
c501d0b1
CC		 1047static void byt_get_pull_strength(u32 reg, u16 *strength)
1048{
1049 switch (reg & BYT_PULL_STR_MASK) {
1050 case BYT_PULL_STR_2K:
1051 *strength = 2000;
1052 break;
1053 case BYT_PULL_STR_10K:
1054 *strength = 10000;
1055 break;
1056 case BYT_PULL_STR_20K:
1057 *strength = 20000;
1058 break;
1059 case BYT_PULL_STR_40K:
1060 *strength = 40000;
1061 break;
1062 }
1063}
1064
1065static int byt_set_pull_strength(u32 *reg, u16 strength)
1066{
1067 *reg &= ~BYT_PULL_STR_MASK;
1068
1069 switch (strength) {
1070 case 2000:
1071 *reg |= BYT_PULL_STR_2K;
1072 break;
1073 case 10000:
1074 *reg |= BYT_PULL_STR_10K;
1075 break;
1076 case 20000:
1077 *reg |= BYT_PULL_STR_20K;
1078 break;
1079 case 40000:
1080 *reg |= BYT_PULL_STR_40K;
1081 break;
1082 default:
1083 return -EINVAL;
1084 }
1085
1086 return 0;
1087}
1088
1089static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
1090 unsigned long *config)
1091{
1092 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1093 enum pin_config_param param = pinconf_to_config_param(*config);
1094 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1095 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1096 unsigned long flags;
658b476c 1097 u32 conf, pull, val, debounce;
c501d0b1
CC		 1098 u16 arg = 0;
1099
1100 raw_spin_lock_irqsave(&vg->lock, flags);
1101 conf = readl(conf_reg);
1102 pull = conf & BYT_PULL_ASSIGN_MASK;
1103 val = readl(val_reg);
1104 raw_spin_unlock_irqrestore(&vg->lock, flags);
1105
1106 switch (param) {
1107 case PIN_CONFIG_BIAS_DISABLE:
1108 if (pull)
1109 return -EINVAL;
1110 break;
1111 case PIN_CONFIG_BIAS_PULL_DOWN:
1112 /* Pull assignment is only applicable in input mode */
1113 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN)
1114 return -EINVAL;
1115
1116 byt_get_pull_strength(conf, &arg);
1117
1118 break;
1119 case PIN_CONFIG_BIAS_PULL_UP:
1120 /* Pull assignment is only applicable in input mode */
1121 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP)
1122 return -EINVAL;
1123
1124 byt_get_pull_strength(conf, &arg);
1125
658b476c
CC		 1126 break;
1127 case PIN_CONFIG_INPUT_DEBOUNCE:
1128 if (!(conf & BYT_DEBOUNCE_EN))
1129 return -EINVAL;
1130
1131 raw_spin_lock_irqsave(&vg->lock, flags);
1132 debounce = readl(byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG));
1133 raw_spin_unlock_irqrestore(&vg->lock, flags);
1134
1135 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
1136 case BYT_DEBOUNCE_PULSE_375US:
1137 arg = 375;
1138 break;
1139 case BYT_DEBOUNCE_PULSE_750US:
1140 arg = 750;
1141 break;
1142 case BYT_DEBOUNCE_PULSE_1500US:
1143 arg = 1500;
1144 break;
1145 case BYT_DEBOUNCE_PULSE_3MS:
1146 arg = 3000;
1147 break;
1148 case BYT_DEBOUNCE_PULSE_6MS:
1149 arg = 6000;
1150 break;
1151 case BYT_DEBOUNCE_PULSE_12MS:
1152 arg = 12000;
1153 break;
1154 case BYT_DEBOUNCE_PULSE_24MS:
1155 arg = 24000;
1156 break;
1157 default:
1158 return -EINVAL;
1159 }
1160
c501d0b1
CC		 1161 break;
1162 default:
1163 return -ENOTSUPP;
1164 }
1165
1166 *config = pinconf_to_config_packed(param, arg);
1167
1168 return 0;
1169}
1170
1171static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
1172 unsigned int offset,
1173 unsigned long *configs,
1174 unsigned int num_configs)
1175{
1176 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1177 unsigned int param, arg;
1178 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1179 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1180 unsigned long flags;
658b476c 1181 u32 conf, val, debounce;
c501d0b1
CC		 1182 int i, ret = 0;
1183
1184 raw_spin_lock_irqsave(&vg->lock, flags);
1185
1186 conf = readl(conf_reg);
1187 val = readl(val_reg);
1188
1189 for (i = 0; i < num_configs; i++) {
1190 param = pinconf_to_config_param(configs[i]);
1191 arg = pinconf_to_config_argument(configs[i]);
1192
1193 switch (param) {
1194 case PIN_CONFIG_BIAS_DISABLE:
1195 conf &= ~BYT_PULL_ASSIGN_MASK;
1196 break;
1197 case PIN_CONFIG_BIAS_PULL_DOWN:
1198 /* Set default strength value in case none is given */
1199 if (arg == 1)
1200 arg = 2000;
1201
1202 /*
1203 * Pull assignment is only applicable in input mode. If
1204 * chip is not in input mode, set it and warn about it.
1205 */
1206 if (val & BYT_INPUT_EN) {
1207 val &= ~BYT_INPUT_EN;
1208 writel(val, val_reg);
1209 dev_warn(&vg->pdev->dev,
1210 "pin %u forcibly set to input mode\n",
1211 offset);
1212 }
1213
1214 conf &= ~BYT_PULL_ASSIGN_MASK;
1215 conf |= BYT_PULL_ASSIGN_DOWN;
1216 ret = byt_set_pull_strength(&conf, arg);
1217
1218 break;
1219 case PIN_CONFIG_BIAS_PULL_UP:
1220 /* Set default strength value in case none is given */
1221 if (arg == 1)
1222 arg = 2000;
1223
1224 /*
1225 * Pull assignment is only applicable in input mode. If
1226 * chip is not in input mode, set it and warn about it.
1227 */
1228 if (val & BYT_INPUT_EN) {
1229 val &= ~BYT_INPUT_EN;
1230 writel(val, val_reg);
1231 dev_warn(&vg->pdev->dev,
1232 "pin %u forcibly set to input mode\n",
1233 offset);
1234 }
1235
1236 conf &= ~BYT_PULL_ASSIGN_MASK;
1237 conf |= BYT_PULL_ASSIGN_UP;
1238 ret = byt_set_pull_strength(&conf, arg);
1239
658b476c
CC		 1240 break;
1241 case PIN_CONFIG_INPUT_DEBOUNCE:
1242 debounce = readl(byt_gpio_reg(vg, offset,
1243 BYT_DEBOUNCE_REG));
1244 conf &= ~BYT_DEBOUNCE_PULSE_MASK;
1245
1246 switch (arg) {
1247 case 375:
1248 conf |= BYT_DEBOUNCE_PULSE_375US;
1249 break;
1250 case 750:
1251 conf |= BYT_DEBOUNCE_PULSE_750US;
1252 break;
1253 case 1500:
1254 conf |= BYT_DEBOUNCE_PULSE_1500US;
1255 break;
1256 case 3000:
1257 conf |= BYT_DEBOUNCE_PULSE_3MS;
1258 break;
1259 case 6000:
1260 conf |= BYT_DEBOUNCE_PULSE_6MS;
1261 break;
1262 case 12000:
1263 conf |= BYT_DEBOUNCE_PULSE_12MS;
1264 break;
1265 case 24000:
1266 conf |= BYT_DEBOUNCE_PULSE_24MS;
1267 break;
1268 default:
1269 ret = -EINVAL;
1270 }
1271
c501d0b1
CC		 1272 break;
1273 default:
1274 ret = -ENOTSUPP;
1275 }
1276
1277 if (ret)
1278 break;
1279 }
1280
1281 if (!ret)
1282 writel(conf, conf_reg);
1283
1284 raw_spin_unlock_irqrestore(&vg->lock, flags);
1285
1286 return ret;
1287}
1288
1289static const struct pinconf_ops byt_pinconf_ops = {
1290 .is_generic = true,
1291 .pin_config_get = byt_pin_config_get,
1292 .pin_config_set = byt_pin_config_set,
1293};
1294
1295static const struct pinctrl_desc byt_pinctrl_desc = {
1296 .pctlops = &byt_pinctrl_ops,
1297 .pmxops = &byt_pinmux_ops,
1298 .confops = &byt_pinconf_ops,
1299 .owner = THIS_MODULE,
1300};
1301
a5d811bb
MN		 1302static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
1303{
bf9a5c96 1304 struct byt_gpio *vg = gpiochip_get_data(chip);
c501d0b1 1305 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
39ce8150
MW		 1306 unsigned long flags;
1307 u32 val;
1308
78e1c896 1309 raw_spin_lock_irqsave(&vg->lock, flags);
39ce8150 1310 val = readl(reg);
78e1c896 1311 raw_spin_unlock_irqrestore(&vg->lock, flags);
39ce8150 1312
3bde8771 1313 return !!(val & BYT_LEVEL);
a5d811bb
MN		 1314}
1315
1316static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1317{
bf9a5c96 1318 struct byt_gpio *vg = gpiochip_get_data(chip);
c501d0b1 1319 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
a5d811bb
MN		 1320 unsigned long flags;
1321 u32 old_val;
1322
86e3ef81
CC		 1323 if (!reg)
1324 return;
a5d811bb 1325
86e3ef81 1326 raw_spin_lock_irqsave(&vg->lock, flags);
a5d811bb 1327 old_val = readl(reg);
a5d811bb
MN		 1328 if (value)
1329 writel(old_val | BYT_LEVEL, reg);
1330 else
1331 writel(old_val & ~BYT_LEVEL, reg);
78e1c896 1332 raw_spin_unlock_irqrestore(&vg->lock, flags);
a5d811bb
MN		 1333}
1334
86e3ef81 1335static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
a5d811bb 1336{
bf9a5c96 1337 struct byt_gpio *vg = gpiochip_get_data(chip);
c501d0b1 1338 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
a5d811bb
MN		 1339 unsigned long flags;
1340 u32 value;
1341
86e3ef81
CC		 1342 if (!reg)
1343 return -EINVAL;
a5d811bb 1344
86e3ef81
CC		 1345 raw_spin_lock_irqsave(&vg->lock, flags);
1346 value = readl(reg);
78e1c896 1347 raw_spin_unlock_irqrestore(&vg->lock, flags);
a5d811bb 1348
86e3ef81
CC		 1349 if (!(value & BYT_OUTPUT_EN))
1350 return GPIOF_DIR_OUT;
1351 if (!(value & BYT_INPUT_EN))
1352 return GPIOF_DIR_IN;
1353
1354 return -EINVAL;
a5d811bb
MN		 1355}
1356
86e3ef81 1357static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
a5d811bb 1358{
86e3ef81
CC		 1359 return pinctrl_gpio_direction_input(chip->base + offset);
1360}
1361
1362static int byt_gpio_direction_output(struct gpio_chip *chip,
1363 unsigned int offset, int value)
1364{
1365 int ret = pinctrl_gpio_direction_output(chip->base + offset);
496940c1 1366
86e3ef81
CC		 1367 if (ret)
1368 return ret;
a5d811bb 1369
86e3ef81 1370 byt_gpio_set(chip, offset, value);
a5d811bb
MN		 1371
1372 return 0;
1373}
1374
1375static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1376{
bf9a5c96 1377 struct byt_gpio *vg = gpiochip_get_data(chip);
a5d811bb 1378 int i;
86e3ef81 1379 u32 conf0, val;
a5d811bb 1380
86e3ef81
CC		 1381 for (i = 0; i < vg->soc_data->npins; i++) {
1382 const struct byt_community *comm;
3ff95885
MW		 1383 const char *pull_str = NULL;
1384 const char *pull = NULL;
86e3ef81 1385 void __iomem *reg;
78e1c896 1386 unsigned long flags;
a4d8d6da 1387 const char *label;
86e3ef81 1388 unsigned int pin;
78e1c896
MW		 1389
1390 raw_spin_lock_irqsave(&vg->lock, flags);
86e3ef81
CC		 1391 pin = vg->soc_data->pins[i].number;
1392 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1393 if (!reg) {
1394 seq_printf(s,
1395 "Could not retrieve pin %i conf0 reg\n",
1396 pin);
22bbd21b 1397 raw_spin_unlock_irqrestore(&vg->lock, flags);
86e3ef81
CC		 1398 continue;
1399 }
1400 conf0 = readl(reg);
1401
1402 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1403 if (!reg) {
1404 seq_printf(s,
1405 "Could not retrieve pin %i val reg\n", pin);
22bbd21b
DC		 1406 raw_spin_unlock_irqrestore(&vg->lock, flags);
1407 continue;
86e3ef81
CC		 1408 }
1409 val = readl(reg);
78e1c896 1410 raw_spin_unlock_irqrestore(&vg->lock, flags);
a5d811bb 1411
86e3ef81
CC		 1412 comm = byt_get_community(vg, pin);
1413 if (!comm) {
1414 seq_printf(s,
1415 "Could not get community for pin %i\n", pin);
1416 continue;
1417 }
a4d8d6da
MN		 1418 label = gpiochip_is_requested(chip, i);
1419 if (!label)
1420 label = "Unrequested";
1421
3ff95885
MW		 1422 switch (conf0 & BYT_PULL_ASSIGN_MASK) {
1423 case BYT_PULL_ASSIGN_UP:
1424 pull = "up";
1425 break;
1426 case BYT_PULL_ASSIGN_DOWN:
1427 pull = "down";
1428 break;
1429 }
1430
1431 switch (conf0 & BYT_PULL_STR_MASK) {
1432 case BYT_PULL_STR_2K:
1433 pull_str = "2k";
1434 break;
1435 case BYT_PULL_STR_10K:
1436 pull_str = "10k";
1437 break;
1438 case BYT_PULL_STR_20K:
1439 pull_str = "20k";
1440 break;
1441 case BYT_PULL_STR_40K:
1442 pull_str = "40k";
1443 break;
1444 }
1445
a5d811bb 1446 seq_printf(s,
3ff95885 1447 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
86e3ef81 1448 pin,
a4d8d6da 1449 label,
a5d811bb
MN		 1450 val & BYT_INPUT_EN ? " " : "in",
1451 val & BYT_OUTPUT_EN ? " " : "out",
1452 val & BYT_LEVEL ? "hi" : "lo",
86e3ef81 1453 comm->pad_map[i], comm->pad_map[i] * 32,
a5d811bb 1454 conf0 & 0x7,
3ff95885
MW		 1455 conf0 & BYT_TRIG_NEG ? " fall" : " ",
1456 conf0 & BYT_TRIG_POS ? " rise" : " ",
1457 conf0 & BYT_TRIG_LVL ? " level" : " ");
1458
1459 if (pull && pull_str)
1460 seq_printf(s, " %-4s %-3s", pull, pull_str);
1461 else
1462 seq_puts(s, " ");
1463
1464 if (conf0 & BYT_IODEN)
1465 seq_puts(s, " open-drain");
1466
1467 seq_puts(s, "\n");
a5d811bb 1468 }
a5d811bb
MN		 1469}
1470
86e3ef81
CC		 1471static const struct gpio_chip byt_gpio_chip = {
1472 .owner = THIS_MODULE,
1473 .request = gpiochip_generic_request,
1474 .free = gpiochip_generic_free,
1475 .get_direction = byt_gpio_get_direction,
1476 .direction_input = byt_gpio_direction_input,
1477 .direction_output = byt_gpio_direction_output,
1478 .get = byt_gpio_get,
1479 .set = byt_gpio_set,
1480 .dbg_show = byt_gpio_dbg_show,
1481};
1482
31e4329f
MW		 1483static void byt_irq_ack(struct irq_data *d)
1484{
1485 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
bf9a5c96 1486 struct byt_gpio *vg = gpiochip_get_data(gc);
31e4329f
MW		 1487 unsigned offset = irqd_to_hwirq(d);
1488 void __iomem *reg;
1489
c501d0b1 1490 reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG);
9f573b98
CC		 1491 if (!reg)
1492 return;
1493
1494 raw_spin_lock(&vg->lock);
31e4329f 1495 writel(BIT(offset % 32), reg);
78e1c896 1496 raw_spin_unlock(&vg->lock);
31e4329f
MW		 1497}
1498
9f573b98
CC		 1499static void byt_irq_mask(struct irq_data *d)
1500{
1501 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1502 struct byt_gpio *vg = gpiochip_get_data(gc);
1503
1504 byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
1505}
1506
a5d811bb
MN		 1507static void byt_irq_unmask(struct irq_data *d)
1508{
31e4329f 1509 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
bf9a5c96 1510 struct byt_gpio *vg = gpiochip_get_data(gc);
31e4329f
MW		 1511 unsigned offset = irqd_to_hwirq(d);
1512 unsigned long flags;
1513 void __iomem *reg;
1514 u32 value;
1515
c501d0b1 1516 reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
9f573b98
CC		 1517 if (!reg)
1518 return;
78e1c896
MW		 1519
1520 raw_spin_lock_irqsave(&vg->lock, flags);
31e4329f
MW		 1521 value = readl(reg);
1522
1523 switch (irqd_get_trigger_type(d)) {
1524 case IRQ_TYPE_LEVEL_HIGH:
1525 value |= BYT_TRIG_LVL;
1526 case IRQ_TYPE_EDGE_RISING:
1527 value |= BYT_TRIG_POS;
1528 break;
1529 case IRQ_TYPE_LEVEL_LOW:
1530 value |= BYT_TRIG_LVL;
1531 case IRQ_TYPE_EDGE_FALLING:
1532 value |= BYT_TRIG_NEG;
1533 break;
1534 case IRQ_TYPE_EDGE_BOTH:
1535 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
1536 break;
1537 }
1538
1539 writel(value, reg);
1540
78e1c896 1541 raw_spin_unlock_irqrestore(&vg->lock, flags);
a5d811bb
MN		 1542}
1543
9f573b98 1544static int byt_irq_type(struct irq_data *d, unsigned int type)
a5d811bb 1545{
9f573b98
CC		 1546 struct byt_gpio *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
1547 u32 offset = irqd_to_hwirq(d);
1548 u32 value;
1549 unsigned long flags;
1550 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
31e4329f 1551
9f573b98
CC		 1552 if (!reg || offset >= vg->chip.ngpio)
1553 return -EINVAL;
1554
1555 raw_spin_lock_irqsave(&vg->lock, flags);
1556 value = readl(reg);
1557
1558 WARN(value & BYT_DIRECT_IRQ_EN,
1559 "Bad pad config for io mode, force direct_irq_en bit clearing");
1560
1561 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
1562 * are used to indicate high and low level triggering
1563 */
1564 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
1565 BYT_TRIG_LVL);
1566
1567 writel(value, reg);
1568
1569 if (type & IRQ_TYPE_EDGE_BOTH)
1570 irq_set_handler_locked(d, handle_edge_irq);
1571 else if (type & IRQ_TYPE_LEVEL_MASK)
1572 irq_set_handler_locked(d, handle_level_irq);
1573
1574 raw_spin_unlock_irqrestore(&vg->lock, flags);
1575
1576 return 0;
a5d811bb
MN		 1577}
1578
1579static struct irq_chip byt_irqchip = {
9f573b98
CC		 1580 .name = "BYT-GPIO",
1581 .irq_ack = byt_irq_ack,
1582 .irq_mask = byt_irq_mask,
1583 .irq_unmask = byt_irq_unmask,
1584 .irq_set_type = byt_irq_type,
1585 .flags = IRQCHIP_SKIP_SET_WAKE,
a5d811bb
MN		 1586};
1587
71e6ca61
CC		 1588static void byt_gpio_irq_handler(struct irq_desc *desc)
1589{
1590 struct irq_data *data = irq_desc_get_irq_data(desc);
1591 struct byt_gpio *vg = gpiochip_get_data(
1592 irq_desc_get_handler_data(desc));
1593 struct irq_chip *chip = irq_data_get_irq_chip(data);
1594 u32 base, pin;
1595 void __iomem *reg;
1596 unsigned long pending;
1597 unsigned int virq;
1598
1599 /* check from GPIO controller which pin triggered the interrupt */
1600 for (base = 0; base < vg->chip.ngpio; base += 32) {
1601 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1602
1603 if (!reg) {
1604 dev_warn(&vg->pdev->dev,
1605 "Pin %i: could not retrieve interrupt status register\n",
1606 base);
1607 continue;
1608 }
1609
1610 pending = readl(reg);
1611 for_each_set_bit(pin, &pending, 32) {
1612 virq = irq_find_mapping(vg->chip.irqdomain, base + pin);
1613 generic_handle_irq(virq);
1614 }
1615 }
1616 chip->irq_eoi(data);
1617}
1618
a5d811bb
MN		 1619static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
1620{
1621 void __iomem *reg;
1622 u32 base, value;
95f0972c
MW		 1623 int i;
1624
1625 /*
1626 * Clear interrupt triggers for all pins that are GPIOs and
1627 * do not use direct IRQ mode. This will prevent spurious
1628 * interrupts from misconfigured pins.
1629 */
71e6ca61
CC		 1630 for (i = 0; i < vg->soc_data->npins; i++) {
1631 unsigned int pin = vg->soc_data->pins[i].number;
1632
1633 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1634 if (!reg) {
1635 dev_warn(&vg->pdev->dev,
1636 "Pin %i: could not retrieve conf0 register\n",
1637 i);
1638 continue;
1639 }
1640
1641 value = readl(reg);
95f0972c
MW		 1642 if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i) &&
1643 !(value & BYT_DIRECT_IRQ_EN)) {
1644 byt_gpio_clear_triggering(vg, i);
1645 dev_dbg(&vg->pdev->dev, "disabling GPIO %d\n", i);
1646 }
1647 }
a5d811bb
MN		 1648
1649 /* clear interrupt status trigger registers */
71e6ca61 1650 for (base = 0; base < vg->soc_data->npins; base += 32) {
c501d0b1 1651 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
71e6ca61
CC		 1652
1653 if (!reg) {
1654 dev_warn(&vg->pdev->dev,
1655 "Pin %i: could not retrieve irq status reg\n",
1656 base);
1657 continue;
1658 }
1659
a5d811bb
MN		 1660 writel(0xffffffff, reg);
1661 /* make sure trigger bits are cleared, if not then a pin
1662 might be misconfigured in bios */
1663 value = readl(reg);
1664 if (value)
1665 dev_err(&vg->pdev->dev,
1666 "GPIO interrupt error, pins misconfigured\n");
1667 }
1668}
1669
71e6ca61 1670static int byt_gpio_probe(struct byt_gpio *vg)
a5d811bb 1671{
a5d811bb 1672 struct gpio_chip *gc;
71e6ca61 1673 struct resource *irq_rc;
a5d811bb
MN		 1674 int ret;
1675
71e6ca61
CC		 1676 /* Set up gpio chip */
1677 vg->chip = byt_gpio_chip;
1678 gc = &vg->chip;
1679 gc->label = dev_name(&vg->pdev->dev);
1680 gc->base = -1;
1681 gc->can_sleep = false;
1682 gc->parent = &vg->pdev->dev;
1683 gc->ngpio = vg->soc_data->npins;
a5d811bb 1684
fcc18deb 1685#ifdef CONFIG_PM_SLEEP
71e6ca61 1686 vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio,
fcc18deb
MW		 1687 sizeof(*vg->saved_context), GFP_KERNEL);
1688#endif
bf9a5c96 1689 ret = gpiochip_add_data(gc, vg);
e1ee5c57 1690 if (ret) {
71e6ca61 1691 dev_err(&vg->pdev->dev, "failed adding byt-gpio chip\n");
e1ee5c57
MW		 1692 return ret;
1693 }
1694
71e6ca61
CC		 1695 ret = gpiochip_add_pin_range(&vg->chip, dev_name(&vg->pdev->dev),
1696 0, 0, vg->soc_data->npins);
1697 if (ret) {
1698 dev_err(&vg->pdev->dev, "failed to add GPIO pin range\n");
1699 goto fail;
1700 }
1701
a5d811bb 1702 /* set up interrupts */
71e6ca61 1703 irq_rc = platform_get_resource(vg->pdev, IORESOURCE_IRQ, 0);
a5d811bb 1704 if (irq_rc && irq_rc->start) {
a5d811bb 1705 byt_gpio_irq_init_hw(vg);
e1ee5c57
MW		 1706 ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0,
1707 handle_simple_irq, IRQ_TYPE_NONE);
1708 if (ret) {
71e6ca61
CC		 1709 dev_err(&vg->pdev->dev, "failed to add irqchip\n");
1710 goto fail;
e1ee5c57 1711 }
a5d811bb 1712
e1ee5c57
MW		 1713 gpiochip_set_chained_irqchip(gc, &byt_irqchip,
1714 (unsigned)irq_rc->start,
1715 byt_gpio_irq_handler);
605a7bca
JY		 1716 }
1717
71e6ca61
CC		 1718 return ret;
1719
1720fail:
1721 gpiochip_remove(&vg->chip);
1722
1723 return ret;
1724}
1725
1726static int byt_set_soc_data(struct byt_gpio *vg,
1727 const struct byt_pinctrl_soc_data *soc_data)
1728{
1729 int i;
1730
1731 vg->soc_data = soc_data;
1732 vg->communities_copy = devm_kcalloc(&vg->pdev->dev,
1733 soc_data->ncommunities,
1734 sizeof(*vg->communities_copy),
1735 GFP_KERNEL);
1736 if (!vg->communities_copy)
1737 return -ENOMEM;
1738
1739 for (i = 0; i < soc_data->ncommunities; i++) {
1740 struct byt_community *comm = vg->communities_copy + i;
1741 struct resource *mem_rc;
1742
1743 *comm = vg->soc_data->communities[i];
1744
1745 mem_rc = platform_get_resource(vg->pdev, IORESOURCE_MEM, 0);
1746 comm->reg_base = devm_ioremap_resource(&vg->pdev->dev, mem_rc);
1747 if (IS_ERR(comm->reg_base))
1748 return PTR_ERR(comm->reg_base);
1749 }
1750
1751 return 0;
1752}
1753
1754static const struct acpi_device_id byt_gpio_acpi_match[] = {
1755 { "INT33B2", (kernel_ulong_t)byt_soc_data },
1756 { "INT33FC", (kernel_ulong_t)byt_soc_data },
1757 { }
1758};
1759MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
1760
1761static int byt_pinctrl_probe(struct platform_device *pdev)
1762{
1763 const struct byt_pinctrl_soc_data *soc_data = NULL;
1764 const struct byt_pinctrl_soc_data **soc_table;
1765 const struct acpi_device_id *acpi_id;
1766 struct acpi_device *acpi_dev;
1767 struct byt_gpio *vg;
1768 int i, ret;
1769
1770 acpi_dev = ACPI_COMPANION(&pdev->dev);
1771 if (!acpi_dev)
1772 return -ENODEV;
1773
1774 acpi_id = acpi_match_device(byt_gpio_acpi_match, &pdev->dev);
1775 if (!acpi_id)
1776 return -ENODEV;
1777
1778 soc_table = (const struct byt_pinctrl_soc_data **)acpi_id->driver_data;
1779
1780 for (i = 0; soc_table[i]; i++) {
1781 if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) {
1782 soc_data = soc_table[i];
1783 break;
1784 }
1785 }
1786
1787 if (!soc_data)
1788 return -ENODEV;
1789
1790 vg = devm_kzalloc(&pdev->dev, sizeof(*vg), GFP_KERNEL);
1791 if (!vg)
1792 return -ENOMEM;
1793
1794 vg->pdev = pdev;
1795 ret = byt_set_soc_data(vg, soc_data);
1796 if (ret) {
1797 dev_err(&pdev->dev, "failed to set soc data\n");
1798 return ret;
1799 }
1800
1801 vg->pctl_desc = byt_pinctrl_desc;
1802 vg->pctl_desc.name = dev_name(&pdev->dev);
1803 vg->pctl_desc.pins = vg->soc_data->pins;
1804 vg->pctl_desc.npins = vg->soc_data->npins;
1805
1806 vg->pctl_dev = pinctrl_register(&vg->pctl_desc, &pdev->dev, vg);
1807 if (IS_ERR(vg->pctl_dev)) {
1808 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1809 return PTR_ERR(vg->pctl_dev);
1810 }
1811
1812 ret = byt_gpio_probe(vg);
1813 if (ret) {
1814 pinctrl_unregister(vg->pctl_dev);
1815 return ret;
1816 }
1817
1818 platform_set_drvdata(pdev, vg);
1819 raw_spin_lock_init(&vg->lock);
1820 pm_runtime_enable(&pdev->dev);
1821
1822 return 0;
1823}
1824
1825static int byt_pinctrl_remove(struct platform_device *pdev)
1826{
1827 struct byt_gpio *vg = platform_get_drvdata(pdev);
1828
1829 pm_runtime_disable(&pdev->dev);
1830 gpiochip_remove(&vg->chip);
1831 pinctrl_unregister(vg->pctl_dev);
a5d811bb
MN		 1832
1833 return 0;
1834}
1835
fcc18deb
MW		 1836#ifdef CONFIG_PM_SLEEP
1837static int byt_gpio_suspend(struct device *dev)
1838{
1839 struct platform_device *pdev = to_platform_device(dev);
1840 struct byt_gpio *vg = platform_get_drvdata(pdev);
1841 int i;
1842
71e6ca61 1843 for (i = 0; i < vg->soc_data->npins; i++) {
fcc18deb
MW		 1844 void __iomem *reg;
1845 u32 value;
71e6ca61 1846 unsigned int pin = vg->soc_data->pins[i].number;
fcc18deb 1847
71e6ca61
CC		 1848 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1849 if (!reg) {
1850 dev_warn(&vg->pdev->dev,
1851 "Pin %i: could not retrieve conf0 register\n",
1852 i);
1853 continue;
1854 }
fcc18deb
MW		 1855 value = readl(reg) & BYT_CONF0_RESTORE_MASK;
1856 vg->saved_context[i].conf0 = value;
1857
71e6ca61 1858 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
fcc18deb
MW		 1859 value = readl(reg) & BYT_VAL_RESTORE_MASK;
1860 vg->saved_context[i].val = value;
1861 }
1862
1863 return 0;
1864}
1865
1866static int byt_gpio_resume(struct device *dev)
1867{
1868 struct platform_device *pdev = to_platform_device(dev);
1869 struct byt_gpio *vg = platform_get_drvdata(pdev);
1870 int i;
1871
71e6ca61 1872 for (i = 0; i < vg->soc_data->npins; i++) {
fcc18deb
MW		 1873 void __iomem *reg;
1874 u32 value;
71e6ca61 1875 unsigned int pin = vg->soc_data->pins[i].number;
fcc18deb 1876
71e6ca61
CC		 1877 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1878 if (!reg) {
1879 dev_warn(&vg->pdev->dev,
1880 "Pin %i: could not retrieve conf0 register\n",
1881 i);
1882 continue;
1883 }
fcc18deb
MW		 1884 value = readl(reg);
1885 if ((value & BYT_CONF0_RESTORE_MASK) !=
1886 vg->saved_context[i].conf0) {
1887 value &= ~BYT_CONF0_RESTORE_MASK;
1888 value |= vg->saved_context[i].conf0;
1889 writel(value, reg);
1890 dev_info(dev, "restored pin %d conf0 %#08x", i, value);
1891 }
1892
71e6ca61 1893 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
fcc18deb
MW		 1894 value = readl(reg);
1895 if ((value & BYT_VAL_RESTORE_MASK) !=
1896 vg->saved_context[i].val) {
1897 u32 v;
1898
1899 v = value & ~BYT_VAL_RESTORE_MASK;
1900 v |= vg->saved_context[i].val;
1901 if (v != value) {
1902 writel(v, reg);
1903 dev_dbg(dev, "restored pin %d val %#08x\n",
1904 i, v);
1905 }
1906 }
1907 }
1908
1909 return 0;
1910}
1911#endif
1912
ec879f12 1913#ifdef CONFIG_PM
a5d811bb
MN		 1914static int byt_gpio_runtime_suspend(struct device *dev)
1915{
1916 return 0;
1917}
1918
1919static int byt_gpio_runtime_resume(struct device *dev)
1920{
1921 return 0;
1922}
ec879f12 1923#endif
a5d811bb
MN		 1924
1925static const struct dev_pm_ops byt_gpio_pm_ops = {
fcc18deb
MW		 1926 SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
1927 SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume,
1928 NULL)
a5d811bb
MN		 1929};
1930
a5d811bb 1931static struct platform_driver byt_gpio_driver = {
71e6ca61
CC		 1932 .probe = byt_pinctrl_probe,
1933 .remove = byt_pinctrl_remove,
a5d811bb
MN		 1934 .driver = {
1935 .name = "byt_gpio",
a5d811bb
MN		 1936 .pm = &byt_gpio_pm_ops,
1937 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
1938 },
1939};
1940
1941static int __init byt_gpio_init(void)
1942{
1943 return platform_driver_register(&byt_gpio_driver);
1944}
a5d811bb 1945subsys_initcall(byt_gpio_init);
9067bbe5
FB		 1946
1947static void __exit byt_gpio_exit(void)
1948{
1949 platform_driver_unregister(&byt_gpio_driver);
1950}
1951module_exit(byt_gpio_exit);
Linux kernel - Deliverables
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