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4e80c8f5 AS |
1 | /* |
2 | * Intel Merrifield SoC pinctrl driver | |
3 | * | |
4 | * Copyright (C) 2016, Intel Corporation | |
5 | * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/bitops.h> | |
13 | #include <linux/err.h> | |
e95d0dfb | 14 | #include <linux/io.h> |
4e80c8f5 AS |
15 | #include <linux/module.h> |
16 | #include <linux/platform_device.h> | |
17 | #include <linux/pinctrl/pinconf.h> | |
18 | #include <linux/pinctrl/pinconf-generic.h> | |
19 | #include <linux/pinctrl/pinctrl.h> | |
20 | #include <linux/pinctrl/pinmux.h> | |
21 | ||
22 | #include "pinctrl-intel.h" | |
23 | ||
24 | #define MRFLD_FAMILY_NR 64 | |
25 | #define MRFLD_FAMILY_LEN 0x400 | |
26 | ||
27 | #define SLEW_OFFSET 0x000 | |
28 | #define BUFCFG_OFFSET 0x100 | |
29 | #define MISC_OFFSET 0x300 | |
30 | ||
31 | #define BUFCFG_PINMODE_SHIFT 0 | |
32 | #define BUFCFG_PINMODE_MASK GENMASK(2, 0) | |
33 | #define BUFCFG_PINMODE_GPIO 0 | |
34 | #define BUFCFG_PUPD_VAL_SHIFT 4 | |
35 | #define BUFCFG_PUPD_VAL_MASK GENMASK(5, 4) | |
36 | #define BUFCFG_PUPD_VAL_2K 0 | |
37 | #define BUFCFG_PUPD_VAL_20K 1 | |
38 | #define BUFCFG_PUPD_VAL_50K 2 | |
39 | #define BUFCFG_PUPD_VAL_910 3 | |
40 | #define BUFCFG_PU_EN BIT(8) | |
41 | #define BUFCFG_PD_EN BIT(9) | |
42 | #define BUFCFG_Px_EN_MASK GENMASK(9, 8) | |
43 | #define BUFCFG_SLEWSEL BIT(10) | |
44 | #define BUFCFG_OVINEN BIT(12) | |
45 | #define BUFCFG_OVINEN_EN BIT(13) | |
46 | #define BUFCFG_OVINEN_MASK GENMASK(13, 12) | |
47 | #define BUFCFG_OVOUTEN BIT(14) | |
48 | #define BUFCFG_OVOUTEN_EN BIT(15) | |
49 | #define BUFCFG_OVOUTEN_MASK GENMASK(15, 14) | |
50 | #define BUFCFG_INDATAOV_VAL BIT(16) | |
51 | #define BUFCFG_INDATAOV_EN BIT(17) | |
52 | #define BUFCFG_INDATAOV_MASK GENMASK(17, 16) | |
53 | #define BUFCFG_OUTDATAOV_VAL BIT(18) | |
54 | #define BUFCFG_OUTDATAOV_EN BIT(19) | |
55 | #define BUFCFG_OUTDATAOV_MASK GENMASK(19, 18) | |
56 | #define BUFCFG_OD_EN BIT(21) | |
57 | ||
58 | /** | |
59 | * struct mrfld_family - Intel pin family description | |
60 | * @barno: MMIO BAR number where registers for this family reside | |
61 | * @pin_base: Starting pin of pins in this family | |
62 | * @npins: Number of pins in this family | |
63 | * @protected: True if family is protected by access | |
64 | * @regs: family specific common registers | |
65 | */ | |
66 | struct mrfld_family { | |
67 | unsigned int barno; | |
68 | unsigned int pin_base; | |
69 | size_t npins; | |
70 | bool protected; | |
71 | void __iomem *regs; | |
72 | }; | |
73 | ||
74 | #define MRFLD_FAMILY(b, s, e) \ | |
75 | { \ | |
76 | .barno = (b), \ | |
77 | .pin_base = (s), \ | |
78 | .npins = (e) - (s) + 1, \ | |
79 | } | |
80 | ||
81 | #define MRFLD_FAMILY_PROTECTED(b, s, e) \ | |
82 | { \ | |
83 | .barno = (b), \ | |
84 | .pin_base = (s), \ | |
85 | .npins = (e) - (s) + 1, \ | |
86 | .protected = true, \ | |
87 | } | |
88 | ||
89 | static const struct pinctrl_pin_desc mrfld_pins[] = { | |
90 | /* Family 0: OCP2SSC (0 pins) */ | |
91 | /* Family 1: ULPI (13 pins) */ | |
92 | PINCTRL_PIN(0, "ULPI_CLK"), | |
93 | PINCTRL_PIN(1, "ULPI_D0"), | |
94 | PINCTRL_PIN(2, "ULPI_D1"), | |
95 | PINCTRL_PIN(3, "ULPI_D2"), | |
96 | PINCTRL_PIN(4, "ULPI_D3"), | |
97 | PINCTRL_PIN(5, "ULPI_D4"), | |
98 | PINCTRL_PIN(6, "ULPI_D5"), | |
99 | PINCTRL_PIN(7, "ULPI_D6"), | |
100 | PINCTRL_PIN(8, "ULPI_D7"), | |
101 | PINCTRL_PIN(9, "ULPI_DIR"), | |
102 | PINCTRL_PIN(10, "ULPI_NXT"), | |
103 | PINCTRL_PIN(11, "ULPI_REFCLK"), | |
104 | PINCTRL_PIN(12, "ULPI_STP"), | |
105 | /* Family 2: eMMC (24 pins) */ | |
106 | PINCTRL_PIN(13, "EMMC_CLK"), | |
107 | PINCTRL_PIN(14, "EMMC_CMD"), | |
108 | PINCTRL_PIN(15, "EMMC_D0"), | |
109 | PINCTRL_PIN(16, "EMMC_D1"), | |
110 | PINCTRL_PIN(17, "EMMC_D2"), | |
111 | PINCTRL_PIN(18, "EMMC_D3"), | |
112 | PINCTRL_PIN(19, "EMMC_D4"), | |
113 | PINCTRL_PIN(20, "EMMC_D5"), | |
114 | PINCTRL_PIN(21, "EMMC_D6"), | |
115 | PINCTRL_PIN(22, "EMMC_D7"), | |
116 | PINCTRL_PIN(23, "EMMC_RST_N"), | |
117 | PINCTRL_PIN(24, "GP154"), | |
118 | PINCTRL_PIN(25, "GP155"), | |
119 | PINCTRL_PIN(26, "GP156"), | |
120 | PINCTRL_PIN(27, "GP157"), | |
121 | PINCTRL_PIN(28, "GP158"), | |
122 | PINCTRL_PIN(29, "GP159"), | |
123 | PINCTRL_PIN(30, "GP160"), | |
124 | PINCTRL_PIN(31, "GP161"), | |
125 | PINCTRL_PIN(32, "GP162"), | |
126 | PINCTRL_PIN(33, "GP163"), | |
127 | PINCTRL_PIN(34, "GP97"), | |
128 | PINCTRL_PIN(35, "GP14"), | |
129 | PINCTRL_PIN(36, "GP15"), | |
130 | /* Family 3: SDIO (20 pins) */ | |
131 | PINCTRL_PIN(37, "GP77_SD_CD"), | |
132 | PINCTRL_PIN(38, "GP78_SD_CLK"), | |
133 | PINCTRL_PIN(39, "GP79_SD_CMD"), | |
134 | PINCTRL_PIN(40, "GP80_SD_D0"), | |
135 | PINCTRL_PIN(41, "GP81_SD_D1"), | |
136 | PINCTRL_PIN(42, "GP82_SD_D2"), | |
137 | PINCTRL_PIN(43, "GP83_SD_D3"), | |
138 | PINCTRL_PIN(44, "GP84_SD_LS_CLK_FB"), | |
139 | PINCTRL_PIN(45, "GP85_SD_LS_CMD_DIR"), | |
140 | PINCTRL_PIN(46, "GP86_SD_LVL_D_DIR"), | |
141 | PINCTRL_PIN(47, "GP88_SD_LS_SEL"), | |
142 | PINCTRL_PIN(48, "GP87_SD_PD"), | |
143 | PINCTRL_PIN(49, "GP89_SD_WP"), | |
144 | PINCTRL_PIN(50, "GP90_SDIO_CLK"), | |
145 | PINCTRL_PIN(51, "GP91_SDIO_CMD"), | |
146 | PINCTRL_PIN(52, "GP92_SDIO_D0"), | |
147 | PINCTRL_PIN(53, "GP93_SDIO_D1"), | |
148 | PINCTRL_PIN(54, "GP94_SDIO_D2"), | |
149 | PINCTRL_PIN(55, "GP95_SDIO_D3"), | |
150 | PINCTRL_PIN(56, "GP96_SDIO_PD"), | |
151 | /* Family 4: HSI (8 pins) */ | |
152 | PINCTRL_PIN(57, "HSI_ACDATA"), | |
153 | PINCTRL_PIN(58, "HSI_ACFLAG"), | |
154 | PINCTRL_PIN(59, "HSI_ACREADY"), | |
155 | PINCTRL_PIN(60, "HSI_ACWAKE"), | |
156 | PINCTRL_PIN(61, "HSI_CADATA"), | |
157 | PINCTRL_PIN(62, "HSI_CAFLAG"), | |
158 | PINCTRL_PIN(63, "HSI_CAREADY"), | |
159 | PINCTRL_PIN(64, "HSI_CAWAKE"), | |
160 | /* Family 5: SSP Audio (14 pins) */ | |
161 | PINCTRL_PIN(65, "GP70"), | |
162 | PINCTRL_PIN(66, "GP71"), | |
163 | PINCTRL_PIN(67, "GP32_I2S_0_CLK"), | |
164 | PINCTRL_PIN(68, "GP33_I2S_0_FS"), | |
165 | PINCTRL_PIN(69, "GP34_I2S_0_RXD"), | |
166 | PINCTRL_PIN(70, "GP35_I2S_0_TXD"), | |
167 | PINCTRL_PIN(71, "GP36_I2S_1_CLK"), | |
168 | PINCTRL_PIN(72, "GP37_I2S_1_FS"), | |
169 | PINCTRL_PIN(73, "GP38_I2S_1_RXD"), | |
170 | PINCTRL_PIN(74, "GP39_I2S_1_TXD"), | |
171 | PINCTRL_PIN(75, "GP40_I2S_2_CLK"), | |
172 | PINCTRL_PIN(76, "GP41_I2S_2_FS"), | |
173 | PINCTRL_PIN(77, "GP42_I2S_2_RXD"), | |
174 | PINCTRL_PIN(78, "GP43_I2S_2_TXD"), | |
175 | /* Family 6: GP SSP (22 pins) */ | |
176 | PINCTRL_PIN(79, "GP120_SPI_3_CLK"), | |
177 | PINCTRL_PIN(80, "GP121_SPI_3_SS"), | |
178 | PINCTRL_PIN(81, "GP122_SPI_3_RXD"), | |
179 | PINCTRL_PIN(82, "GP123_SPI_3_TXD"), | |
180 | PINCTRL_PIN(83, "GP102_SPI_4_CLK"), | |
181 | PINCTRL_PIN(84, "GP103_SPI_4_SS_0"), | |
182 | PINCTRL_PIN(85, "GP104_SPI_4_SS_1"), | |
183 | PINCTRL_PIN(86, "GP105_SPI_4_SS_2"), | |
184 | PINCTRL_PIN(87, "GP106_SPI_4_SS_3"), | |
185 | PINCTRL_PIN(88, "GP107_SPI_4_RXD"), | |
186 | PINCTRL_PIN(89, "GP108_SPI_4_TXD"), | |
187 | PINCTRL_PIN(90, "GP109_SPI_5_CLK"), | |
188 | PINCTRL_PIN(91, "GP110_SPI_5_SS_0"), | |
189 | PINCTRL_PIN(92, "GP111_SPI_5_SS_1"), | |
190 | PINCTRL_PIN(93, "GP112_SPI_5_SS_2"), | |
191 | PINCTRL_PIN(94, "GP113_SPI_5_SS_3"), | |
192 | PINCTRL_PIN(95, "GP114_SPI_5_RXD"), | |
193 | PINCTRL_PIN(96, "GP115_SPI_5_TXD"), | |
194 | PINCTRL_PIN(97, "GP116_SPI_6_CLK"), | |
195 | PINCTRL_PIN(98, "GP117_SPI_6_SS"), | |
196 | PINCTRL_PIN(99, "GP118_SPI_6_RXD"), | |
197 | PINCTRL_PIN(100, "GP119_SPI_6_TXD"), | |
198 | /* Family 7: I2C (14 pins) */ | |
199 | PINCTRL_PIN(101, "GP19_I2C_1_SCL"), | |
200 | PINCTRL_PIN(102, "GP20_I2C_1_SDA"), | |
201 | PINCTRL_PIN(103, "GP21_I2C_2_SCL"), | |
202 | PINCTRL_PIN(104, "GP22_I2C_2_SDA"), | |
203 | PINCTRL_PIN(105, "GP17_I2C_3_SCL_HDMI"), | |
204 | PINCTRL_PIN(106, "GP18_I2C_3_SDA_HDMI"), | |
205 | PINCTRL_PIN(107, "GP23_I2C_4_SCL"), | |
206 | PINCTRL_PIN(108, "GP24_I2C_4_SDA"), | |
207 | PINCTRL_PIN(109, "GP25_I2C_5_SCL"), | |
208 | PINCTRL_PIN(110, "GP26_I2C_5_SDA"), | |
209 | PINCTRL_PIN(111, "GP27_I2C_6_SCL"), | |
210 | PINCTRL_PIN(112, "GP28_I2C_6_SDA"), | |
211 | PINCTRL_PIN(113, "GP29_I2C_7_SCL"), | |
212 | PINCTRL_PIN(114, "GP30_I2C_7_SDA"), | |
213 | /* Family 8: UART (12 pins) */ | |
214 | PINCTRL_PIN(115, "GP124_UART_0_CTS"), | |
215 | PINCTRL_PIN(116, "GP125_UART_0_RTS"), | |
216 | PINCTRL_PIN(117, "GP126_UART_0_RX"), | |
217 | PINCTRL_PIN(118, "GP127_UART_0_TX"), | |
218 | PINCTRL_PIN(119, "GP128_UART_1_CTS"), | |
219 | PINCTRL_PIN(120, "GP129_UART_1_RTS"), | |
220 | PINCTRL_PIN(121, "GP130_UART_1_RX"), | |
221 | PINCTRL_PIN(122, "GP131_UART_1_TX"), | |
222 | PINCTRL_PIN(123, "GP132_UART_2_CTS"), | |
223 | PINCTRL_PIN(124, "GP133_UART_2_RTS"), | |
224 | PINCTRL_PIN(125, "GP134_UART_2_RX"), | |
225 | PINCTRL_PIN(126, "GP135_UART_2_TX"), | |
226 | /* Family 9: GPIO South (19 pins) */ | |
227 | PINCTRL_PIN(127, "GP177"), | |
228 | PINCTRL_PIN(128, "GP178"), | |
229 | PINCTRL_PIN(129, "GP179"), | |
230 | PINCTRL_PIN(130, "GP180"), | |
231 | PINCTRL_PIN(131, "GP181"), | |
232 | PINCTRL_PIN(132, "GP182_PWM2"), | |
233 | PINCTRL_PIN(133, "GP183_PWM3"), | |
234 | PINCTRL_PIN(134, "GP184"), | |
235 | PINCTRL_PIN(135, "GP185"), | |
236 | PINCTRL_PIN(136, "GP186"), | |
237 | PINCTRL_PIN(137, "GP187"), | |
238 | PINCTRL_PIN(138, "GP188"), | |
239 | PINCTRL_PIN(139, "GP189"), | |
240 | PINCTRL_PIN(140, "GP64_FAST_INT0"), | |
241 | PINCTRL_PIN(141, "GP65_FAST_INT1"), | |
242 | PINCTRL_PIN(142, "GP66_FAST_INT2"), | |
243 | PINCTRL_PIN(143, "GP67_FAST_INT3"), | |
244 | PINCTRL_PIN(144, "GP12_PWM0"), | |
245 | PINCTRL_PIN(145, "GP13_PWM1"), | |
246 | /* Family 10: Camera Sideband (12 pins) */ | |
247 | PINCTRL_PIN(146, "GP0"), | |
248 | PINCTRL_PIN(147, "GP1"), | |
249 | PINCTRL_PIN(148, "GP2"), | |
250 | PINCTRL_PIN(149, "GP3"), | |
251 | PINCTRL_PIN(150, "GP4"), | |
252 | PINCTRL_PIN(151, "GP5"), | |
253 | PINCTRL_PIN(152, "GP6"), | |
254 | PINCTRL_PIN(153, "GP7"), | |
255 | PINCTRL_PIN(154, "GP8"), | |
256 | PINCTRL_PIN(155, "GP9"), | |
257 | PINCTRL_PIN(156, "GP10"), | |
258 | PINCTRL_PIN(157, "GP11"), | |
259 | /* Family 11: Clock (22 pins) */ | |
260 | PINCTRL_PIN(158, "GP137"), | |
261 | PINCTRL_PIN(159, "GP138"), | |
262 | PINCTRL_PIN(160, "GP139"), | |
263 | PINCTRL_PIN(161, "GP140"), | |
264 | PINCTRL_PIN(162, "GP141"), | |
265 | PINCTRL_PIN(163, "GP142"), | |
266 | PINCTRL_PIN(164, "GP16_HDMI_HPD"), | |
267 | PINCTRL_PIN(165, "GP68_DSI_A_TE"), | |
268 | PINCTRL_PIN(166, "GP69_DSI_C_TE"), | |
269 | PINCTRL_PIN(167, "OSC_CLK_CTRL0"), | |
270 | PINCTRL_PIN(168, "OSC_CLK_CTRL1"), | |
271 | PINCTRL_PIN(169, "OSC_CLK0"), | |
272 | PINCTRL_PIN(170, "OSC_CLK1"), | |
273 | PINCTRL_PIN(171, "OSC_CLK2"), | |
274 | PINCTRL_PIN(172, "OSC_CLK3"), | |
275 | PINCTRL_PIN(173, "OSC_CLK4"), | |
276 | PINCTRL_PIN(174, "RESETOUT"), | |
277 | PINCTRL_PIN(175, "PMODE"), | |
278 | PINCTRL_PIN(176, "PRDY"), | |
279 | PINCTRL_PIN(177, "PREQ"), | |
280 | PINCTRL_PIN(178, "GP190"), | |
281 | PINCTRL_PIN(179, "GP191"), | |
282 | /* Family 12: MSIC (15 pins) */ | |
283 | PINCTRL_PIN(180, "I2C_0_SCL"), | |
284 | PINCTRL_PIN(181, "I2C_0_SDA"), | |
285 | PINCTRL_PIN(182, "IERR"), | |
286 | PINCTRL_PIN(183, "JTAG_TCK"), | |
287 | PINCTRL_PIN(184, "JTAG_TDI"), | |
288 | PINCTRL_PIN(185, "JTAG_TDO"), | |
289 | PINCTRL_PIN(186, "JTAG_TMS"), | |
290 | PINCTRL_PIN(187, "JTAG_TRST"), | |
291 | PINCTRL_PIN(188, "PROCHOT"), | |
292 | PINCTRL_PIN(189, "RTC_CLK"), | |
293 | PINCTRL_PIN(190, "SVID_ALERT"), | |
294 | PINCTRL_PIN(191, "SVID_CLK"), | |
295 | PINCTRL_PIN(192, "SVID_D"), | |
296 | PINCTRL_PIN(193, "THERMTRIP"), | |
297 | PINCTRL_PIN(194, "STANDBY"), | |
298 | /* Family 13: Keyboard (20 pins) */ | |
299 | PINCTRL_PIN(195, "GP44"), | |
300 | PINCTRL_PIN(196, "GP45"), | |
301 | PINCTRL_PIN(197, "GP46"), | |
302 | PINCTRL_PIN(198, "GP47"), | |
303 | PINCTRL_PIN(199, "GP48"), | |
304 | PINCTRL_PIN(200, "GP49"), | |
305 | PINCTRL_PIN(201, "GP50"), | |
306 | PINCTRL_PIN(202, "GP51"), | |
307 | PINCTRL_PIN(203, "GP52"), | |
308 | PINCTRL_PIN(204, "GP53"), | |
309 | PINCTRL_PIN(205, "GP54"), | |
310 | PINCTRL_PIN(206, "GP55"), | |
311 | PINCTRL_PIN(207, "GP56"), | |
312 | PINCTRL_PIN(208, "GP57"), | |
313 | PINCTRL_PIN(209, "GP58"), | |
314 | PINCTRL_PIN(210, "GP59"), | |
315 | PINCTRL_PIN(211, "GP60"), | |
316 | PINCTRL_PIN(212, "GP61"), | |
317 | PINCTRL_PIN(213, "GP62"), | |
318 | PINCTRL_PIN(214, "GP63"), | |
319 | /* Family 14: GPIO North (13 pins) */ | |
320 | PINCTRL_PIN(215, "GP164"), | |
321 | PINCTRL_PIN(216, "GP165"), | |
322 | PINCTRL_PIN(217, "GP166"), | |
323 | PINCTRL_PIN(218, "GP167"), | |
324 | PINCTRL_PIN(219, "GP168_MJTAG_TCK"), | |
325 | PINCTRL_PIN(220, "GP169_MJTAG_TDI"), | |
326 | PINCTRL_PIN(221, "GP170_MJTAG_TDO"), | |
327 | PINCTRL_PIN(222, "GP171_MJTAG_TMS"), | |
328 | PINCTRL_PIN(223, "GP172_MJTAG_TRST"), | |
329 | PINCTRL_PIN(224, "GP173"), | |
330 | PINCTRL_PIN(225, "GP174"), | |
331 | PINCTRL_PIN(226, "GP175"), | |
332 | PINCTRL_PIN(227, "GP176"), | |
333 | /* Family 15: PTI (5 pins) */ | |
334 | PINCTRL_PIN(228, "GP72_PTI_CLK"), | |
335 | PINCTRL_PIN(229, "GP73_PTI_D0"), | |
336 | PINCTRL_PIN(230, "GP74_PTI_D1"), | |
337 | PINCTRL_PIN(231, "GP75_PTI_D2"), | |
338 | PINCTRL_PIN(232, "GP76_PTI_D3"), | |
339 | /* Family 16: USB3 (0 pins) */ | |
340 | /* Family 17: HSIC (0 pins) */ | |
341 | /* Family 18: Broadcast (0 pins) */ | |
342 | }; | |
343 | ||
344 | static const unsigned int mrfld_sdio_pins[] = { 50, 51, 52, 53, 54, 55, 56 }; | |
345 | static const unsigned int mrfld_spi5_pins[] = { 90, 91, 92, 93, 94, 95, 96 }; | |
346 | static const unsigned int mrfld_uart0_pins[] = { 124, 125, 126, 127 }; | |
347 | static const unsigned int mrfld_uart1_pins[] = { 128, 129, 130, 131 }; | |
348 | static const unsigned int mrfld_uart2_pins[] = { 132, 133, 134, 135 }; | |
349 | static const unsigned int mrfld_pwm0_pins[] = { 144 }; | |
350 | static const unsigned int mrfld_pwm1_pins[] = { 145 }; | |
351 | static const unsigned int mrfld_pwm2_pins[] = { 132 }; | |
352 | static const unsigned int mrfld_pwm3_pins[] = { 133 }; | |
353 | ||
354 | static const struct intel_pingroup mrfld_groups[] = { | |
355 | PIN_GROUP("sdio_grp", mrfld_sdio_pins, 1), | |
356 | PIN_GROUP("spi5_grp", mrfld_spi5_pins, 1), | |
357 | PIN_GROUP("uart0_grp", mrfld_uart0_pins, 1), | |
358 | PIN_GROUP("uart1_grp", mrfld_uart1_pins, 1), | |
359 | PIN_GROUP("uart2_grp", mrfld_uart2_pins, 1), | |
360 | PIN_GROUP("pwm0_grp", mrfld_pwm0_pins, 1), | |
361 | PIN_GROUP("pwm1_grp", mrfld_pwm1_pins, 1), | |
362 | PIN_GROUP("pwm2_grp", mrfld_pwm2_pins, 1), | |
363 | PIN_GROUP("pwm3_grp", mrfld_pwm3_pins, 1), | |
364 | }; | |
365 | ||
366 | static const char * const mrfld_sdio_groups[] = { "sdio_grp" }; | |
367 | static const char * const mrfld_spi5_groups[] = { "spi5_grp" }; | |
368 | static const char * const mrfld_uart0_groups[] = { "uart0_grp" }; | |
369 | static const char * const mrfld_uart1_groups[] = { "uart1_grp" }; | |
370 | static const char * const mrfld_uart2_groups[] = { "uart2_grp" }; | |
371 | static const char * const mrfld_pwm0_groups[] = { "pwm0_grp" }; | |
372 | static const char * const mrfld_pwm1_groups[] = { "pwm1_grp" }; | |
373 | static const char * const mrfld_pwm2_groups[] = { "pwm2_grp" }; | |
374 | static const char * const mrfld_pwm3_groups[] = { "pwm3_grp" }; | |
375 | ||
376 | static const struct intel_function mrfld_functions[] = { | |
377 | FUNCTION("sdio", mrfld_sdio_groups), | |
378 | FUNCTION("spi5", mrfld_spi5_groups), | |
379 | FUNCTION("uart0", mrfld_uart0_groups), | |
380 | FUNCTION("uart1", mrfld_uart1_groups), | |
381 | FUNCTION("uart2", mrfld_uart2_groups), | |
382 | FUNCTION("pwm0", mrfld_pwm0_groups), | |
383 | FUNCTION("pwm1", mrfld_pwm1_groups), | |
384 | FUNCTION("pwm2", mrfld_pwm2_groups), | |
385 | FUNCTION("pwm3", mrfld_pwm3_groups), | |
386 | }; | |
387 | ||
388 | static const struct mrfld_family mrfld_families[] = { | |
389 | MRFLD_FAMILY(1, 0, 12), | |
390 | MRFLD_FAMILY(2, 13, 36), | |
391 | MRFLD_FAMILY(3, 37, 56), | |
392 | MRFLD_FAMILY(4, 57, 64), | |
393 | MRFLD_FAMILY(5, 65, 78), | |
394 | MRFLD_FAMILY(6, 79, 100), | |
395 | MRFLD_FAMILY_PROTECTED(7, 101, 114), | |
396 | MRFLD_FAMILY(8, 115, 126), | |
397 | MRFLD_FAMILY(9, 127, 145), | |
398 | MRFLD_FAMILY(10, 146, 157), | |
399 | MRFLD_FAMILY(11, 158, 179), | |
400 | MRFLD_FAMILY_PROTECTED(12, 180, 194), | |
401 | MRFLD_FAMILY(13, 195, 214), | |
402 | MRFLD_FAMILY(14, 215, 227), | |
403 | MRFLD_FAMILY(15, 228, 232), | |
404 | }; | |
405 | ||
406 | /** | |
407 | * struct mrfld_pinctrl - Intel Merrifield pinctrl private structure | |
408 | * @dev: Pointer to the device structure | |
409 | * @lock: Lock to serialize register access | |
410 | * @pctldesc: Pin controller description | |
411 | * @pctldev: Pointer to the pin controller device | |
412 | * @families: Array of families this pinctrl handles | |
413 | * @nfamilies: Number of families in the array | |
414 | * @functions: Array of functions | |
415 | * @nfunctions: Number of functions in the array | |
416 | * @groups: Array of pin groups | |
417 | * @ngroups: Number of groups in the array | |
418 | * @pins: Array of pins this pinctrl controls | |
419 | * @npins: Number of pins in the array | |
420 | */ | |
421 | struct mrfld_pinctrl { | |
422 | struct device *dev; | |
423 | raw_spinlock_t lock; | |
424 | struct pinctrl_desc pctldesc; | |
425 | struct pinctrl_dev *pctldev; | |
426 | ||
427 | /* Pin controller configuration */ | |
428 | const struct mrfld_family *families; | |
429 | size_t nfamilies; | |
430 | const struct intel_function *functions; | |
431 | size_t nfunctions; | |
432 | const struct intel_pingroup *groups; | |
433 | size_t ngroups; | |
434 | const struct pinctrl_pin_desc *pins; | |
435 | size_t npins; | |
436 | }; | |
437 | ||
438 | #define pin_to_bufno(f, p) ((p) - (f)->pin_base) | |
439 | ||
440 | static const struct mrfld_family *mrfld_get_family(struct mrfld_pinctrl *mp, | |
441 | unsigned int pin) | |
442 | { | |
443 | const struct mrfld_family *family; | |
444 | unsigned int i; | |
445 | ||
446 | for (i = 0; i < mp->nfamilies; i++) { | |
447 | family = &mp->families[i]; | |
448 | if (pin >= family->pin_base && | |
449 | pin < family->pin_base + family->npins) | |
450 | return family; | |
451 | } | |
452 | ||
453 | dev_warn(mp->dev, "failed to find family for pin %u\n", pin); | |
454 | return NULL; | |
455 | } | |
456 | ||
457 | static bool mrfld_buf_available(struct mrfld_pinctrl *mp, unsigned int pin) | |
458 | { | |
459 | const struct mrfld_family *family; | |
460 | ||
461 | family = mrfld_get_family(mp, pin); | |
462 | if (!family) | |
463 | return false; | |
464 | ||
465 | return !family->protected; | |
466 | } | |
467 | ||
468 | static void __iomem *mrfld_get_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin) | |
469 | { | |
470 | const struct mrfld_family *family; | |
471 | unsigned int bufno; | |
472 | ||
473 | family = mrfld_get_family(mp, pin); | |
474 | if (!family) | |
475 | return NULL; | |
476 | ||
477 | bufno = pin_to_bufno(family, pin); | |
478 | return family->regs + BUFCFG_OFFSET + bufno * 4; | |
479 | } | |
480 | ||
481 | static int mrfld_get_groups_count(struct pinctrl_dev *pctldev) | |
482 | { | |
483 | struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); | |
484 | ||
485 | return mp->ngroups; | |
486 | } | |
487 | ||
488 | static const char *mrfld_get_group_name(struct pinctrl_dev *pctldev, | |
489 | unsigned int group) | |
490 | { | |
491 | struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); | |
492 | ||
493 | return mp->groups[group].name; | |
494 | } | |
495 | ||
496 | static int mrfld_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, | |
497 | const unsigned int **pins, unsigned int *npins) | |
498 | { | |
499 | struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); | |
500 | ||
501 | *pins = mp->groups[group].pins; | |
502 | *npins = mp->groups[group].npins; | |
503 | return 0; | |
504 | } | |
505 | ||
506 | static void mrfld_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, | |
507 | unsigned int pin) | |
508 | { | |
509 | struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); | |
510 | void __iomem *bufcfg; | |
511 | u32 value, mode; | |
512 | ||
513 | if (!mrfld_buf_available(mp, pin)) { | |
514 | seq_puts(s, "not available"); | |
515 | return; | |
516 | } | |
517 | ||
518 | bufcfg = mrfld_get_bufcfg(mp, pin); | |
519 | value = readl(bufcfg); | |
520 | ||
521 | mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT; | |
522 | if (!mode) | |
523 | seq_puts(s, "GPIO "); | |
524 | else | |
525 | seq_printf(s, "mode %d ", mode); | |
526 | ||
527 | seq_printf(s, "0x%08x", value); | |
528 | } | |
529 | ||
530 | static const struct pinctrl_ops mrfld_pinctrl_ops = { | |
531 | .get_groups_count = mrfld_get_groups_count, | |
532 | .get_group_name = mrfld_get_group_name, | |
533 | .get_group_pins = mrfld_get_group_pins, | |
534 | .pin_dbg_show = mrfld_pin_dbg_show, | |
535 | }; | |
536 | ||
537 | static int mrfld_get_functions_count(struct pinctrl_dev *pctldev) | |
538 | { | |
539 | struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); | |
540 | ||
541 | return mp->nfunctions; | |
542 | } | |
543 | ||
544 | static const char *mrfld_get_function_name(struct pinctrl_dev *pctldev, | |
545 | unsigned int function) | |
546 | { | |
547 | struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); | |
548 | ||
549 | return mp->functions[function].name; | |
550 | } | |
551 | ||
552 | static int mrfld_get_function_groups(struct pinctrl_dev *pctldev, | |
553 | unsigned int function, | |
554 | const char * const **groups, | |
555 | unsigned int * const ngroups) | |
556 | { | |
557 | struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); | |
558 | ||
559 | *groups = mp->functions[function].groups; | |
560 | *ngroups = mp->functions[function].ngroups; | |
561 | return 0; | |
562 | } | |
563 | ||
564 | static void mrfld_update_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin, | |
565 | u32 bits, u32 mask) | |
566 | { | |
567 | void __iomem *bufcfg; | |
568 | u32 value; | |
569 | ||
570 | bufcfg = mrfld_get_bufcfg(mp, pin); | |
571 | value = readl(bufcfg); | |
572 | ||
573 | value &= ~mask; | |
574 | value |= bits & mask; | |
575 | ||
576 | writel(value, bufcfg); | |
577 | } | |
578 | ||
579 | static int mrfld_pinmux_set_mux(struct pinctrl_dev *pctldev, | |
580 | unsigned int function, | |
581 | unsigned int group) | |
582 | { | |
583 | struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); | |
584 | const struct intel_pingroup *grp = &mp->groups[group]; | |
585 | u32 bits = grp->mode << BUFCFG_PINMODE_SHIFT; | |
586 | u32 mask = BUFCFG_PINMODE_MASK; | |
587 | unsigned long flags; | |
588 | unsigned int i; | |
589 | ||
590 | /* | |
591 | * All pins in the groups needs to be accessible and writable | |
592 | * before we can enable the mux for this group. | |
593 | */ | |
594 | for (i = 0; i < grp->npins; i++) { | |
595 | if (!mrfld_buf_available(mp, grp->pins[i])) | |
596 | return -EBUSY; | |
597 | } | |
598 | ||
599 | /* Now enable the mux setting for each pin in the group */ | |
600 | raw_spin_lock_irqsave(&mp->lock, flags); | |
601 | for (i = 0; i < grp->npins; i++) | |
602 | mrfld_update_bufcfg(mp, grp->pins[i], bits, mask); | |
603 | raw_spin_unlock_irqrestore(&mp->lock, flags); | |
604 | ||
605 | return 0; | |
606 | } | |
607 | ||
608 | static int mrfld_gpio_request_enable(struct pinctrl_dev *pctldev, | |
609 | struct pinctrl_gpio_range *range, | |
610 | unsigned int pin) | |
611 | { | |
612 | struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); | |
613 | u32 bits = BUFCFG_PINMODE_GPIO << BUFCFG_PINMODE_SHIFT; | |
614 | u32 mask = BUFCFG_PINMODE_MASK; | |
615 | unsigned long flags; | |
616 | ||
617 | if (!mrfld_buf_available(mp, pin)) | |
618 | return -EBUSY; | |
619 | ||
620 | raw_spin_lock_irqsave(&mp->lock, flags); | |
621 | mrfld_update_bufcfg(mp, pin, bits, mask); | |
622 | raw_spin_unlock_irqrestore(&mp->lock, flags); | |
623 | ||
624 | return 0; | |
625 | } | |
626 | ||
627 | static const struct pinmux_ops mrfld_pinmux_ops = { | |
628 | .get_functions_count = mrfld_get_functions_count, | |
629 | .get_function_name = mrfld_get_function_name, | |
630 | .get_function_groups = mrfld_get_function_groups, | |
631 | .set_mux = mrfld_pinmux_set_mux, | |
632 | .gpio_request_enable = mrfld_gpio_request_enable, | |
633 | }; | |
634 | ||
635 | static int mrfld_config_get(struct pinctrl_dev *pctldev, unsigned int pin, | |
636 | unsigned long *config) | |
637 | { | |
638 | struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); | |
639 | enum pin_config_param param = pinconf_to_config_param(*config); | |
640 | u32 value, term; | |
641 | u16 arg = 0; | |
642 | ||
643 | if (!mrfld_buf_available(mp, pin)) | |
644 | return -ENOTSUPP; | |
645 | ||
646 | value = readl(mrfld_get_bufcfg(mp, pin)); | |
647 | term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT; | |
648 | ||
649 | switch (param) { | |
650 | case PIN_CONFIG_BIAS_DISABLE: | |
651 | if (value & BUFCFG_Px_EN_MASK) | |
652 | return -EINVAL; | |
653 | break; | |
654 | ||
655 | case PIN_CONFIG_BIAS_PULL_UP: | |
656 | if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PU_EN) | |
657 | return -EINVAL; | |
658 | ||
659 | switch (term) { | |
660 | case BUFCFG_PUPD_VAL_910: | |
661 | arg = 910; | |
662 | break; | |
663 | case BUFCFG_PUPD_VAL_2K: | |
664 | arg = 2000; | |
665 | break; | |
666 | case BUFCFG_PUPD_VAL_20K: | |
667 | arg = 20000; | |
668 | break; | |
669 | case BUFCFG_PUPD_VAL_50K: | |
670 | arg = 50000; | |
671 | break; | |
672 | } | |
673 | ||
674 | break; | |
675 | ||
676 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
677 | if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PD_EN) | |
678 | return -EINVAL; | |
679 | ||
680 | switch (term) { | |
681 | case BUFCFG_PUPD_VAL_910: | |
682 | arg = 910; | |
683 | break; | |
684 | case BUFCFG_PUPD_VAL_2K: | |
685 | arg = 2000; | |
686 | break; | |
687 | case BUFCFG_PUPD_VAL_20K: | |
688 | arg = 20000; | |
689 | break; | |
690 | case BUFCFG_PUPD_VAL_50K: | |
691 | arg = 50000; | |
692 | break; | |
693 | } | |
694 | ||
695 | break; | |
696 | ||
697 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
698 | if (!(value & BUFCFG_OD_EN)) | |
699 | return -EINVAL; | |
700 | break; | |
701 | ||
702 | case PIN_CONFIG_SLEW_RATE: | |
703 | if (!(value & BUFCFG_SLEWSEL)) | |
704 | arg = 0; | |
705 | else | |
706 | arg = 1; | |
707 | break; | |
708 | ||
709 | default: | |
710 | return -ENOTSUPP; | |
711 | } | |
712 | ||
713 | *config = pinconf_to_config_packed(param, arg); | |
714 | return 0; | |
715 | } | |
716 | ||
717 | static int mrfld_config_set_pin(struct mrfld_pinctrl *mp, unsigned int pin, | |
718 | unsigned long config) | |
719 | { | |
720 | unsigned int param = pinconf_to_config_param(config); | |
721 | unsigned int arg = pinconf_to_config_argument(config); | |
722 | u32 bits = 0, mask = 0; | |
723 | unsigned long flags; | |
724 | ||
725 | switch (param) { | |
726 | case PIN_CONFIG_BIAS_DISABLE: | |
727 | mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; | |
728 | break; | |
729 | ||
730 | case PIN_CONFIG_BIAS_PULL_UP: | |
731 | mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; | |
732 | bits |= BUFCFG_PU_EN; | |
733 | ||
734 | switch (arg) { | |
735 | case 50000: | |
736 | bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT; | |
737 | break; | |
738 | case 20000: | |
739 | bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT; | |
740 | break; | |
741 | case 2000: | |
742 | bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT; | |
743 | break; | |
744 | default: | |
745 | return -EINVAL; | |
746 | } | |
747 | ||
748 | break; | |
749 | ||
750 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
751 | mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK; | |
752 | bits |= BUFCFG_PD_EN; | |
753 | ||
754 | switch (arg) { | |
755 | case 50000: | |
756 | bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT; | |
757 | break; | |
758 | case 20000: | |
759 | bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT; | |
760 | break; | |
761 | case 2000: | |
762 | bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT; | |
763 | break; | |
764 | default: | |
765 | return -EINVAL; | |
766 | } | |
767 | ||
768 | break; | |
769 | ||
770 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
771 | mask |= BUFCFG_OD_EN; | |
772 | if (arg) | |
773 | bits |= BUFCFG_OD_EN; | |
774 | break; | |
775 | ||
776 | case PIN_CONFIG_SLEW_RATE: | |
777 | mask |= BUFCFG_SLEWSEL; | |
778 | if (arg) | |
779 | bits |= BUFCFG_SLEWSEL; | |
780 | break; | |
781 | } | |
782 | ||
783 | raw_spin_lock_irqsave(&mp->lock, flags); | |
784 | mrfld_update_bufcfg(mp, pin, bits, mask); | |
785 | raw_spin_unlock_irqrestore(&mp->lock, flags); | |
786 | ||
787 | return 0; | |
788 | } | |
789 | ||
790 | static int mrfld_config_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
791 | unsigned long *configs, unsigned int nconfigs) | |
792 | { | |
793 | struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev); | |
794 | unsigned int i; | |
795 | int ret; | |
796 | ||
797 | for (i = 0; i < nconfigs; i++) { | |
798 | switch (pinconf_to_config_param(configs[i])) { | |
799 | case PIN_CONFIG_BIAS_DISABLE: | |
800 | case PIN_CONFIG_BIAS_PULL_UP: | |
801 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
802 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
803 | case PIN_CONFIG_SLEW_RATE: | |
804 | ret = mrfld_config_set_pin(mp, pin, configs[i]); | |
805 | if (ret) | |
806 | return ret; | |
807 | break; | |
808 | ||
809 | default: | |
810 | return -ENOTSUPP; | |
811 | } | |
812 | } | |
813 | ||
814 | return 0; | |
815 | } | |
816 | ||
817 | static const struct pinconf_ops mrfld_pinconf_ops = { | |
818 | .is_generic = true, | |
819 | .pin_config_get = mrfld_config_get, | |
820 | .pin_config_set = mrfld_config_set, | |
821 | }; | |
822 | ||
823 | static const struct pinctrl_desc mrfld_pinctrl_desc = { | |
824 | .pctlops = &mrfld_pinctrl_ops, | |
825 | .pmxops = &mrfld_pinmux_ops, | |
826 | .confops = &mrfld_pinconf_ops, | |
827 | .owner = THIS_MODULE, | |
828 | }; | |
829 | ||
830 | static int mrfld_pinctrl_probe(struct platform_device *pdev) | |
831 | { | |
832 | struct mrfld_family *families; | |
833 | struct mrfld_pinctrl *mp; | |
834 | struct resource *mem; | |
835 | void __iomem *regs; | |
836 | size_t nfamilies; | |
837 | unsigned int i; | |
838 | ||
839 | mp = devm_kzalloc(&pdev->dev, sizeof(*mp), GFP_KERNEL); | |
840 | if (!mp) | |
841 | return -ENOMEM; | |
842 | ||
843 | mp->dev = &pdev->dev; | |
844 | raw_spin_lock_init(&mp->lock); | |
845 | ||
846 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
847 | regs = devm_ioremap_resource(&pdev->dev, mem); | |
848 | if (IS_ERR(regs)) | |
849 | return PTR_ERR(regs); | |
850 | ||
851 | /* | |
852 | * Make a copy of the families which we can use to hold pointers | |
853 | * to the registers. | |
854 | */ | |
855 | nfamilies = ARRAY_SIZE(mrfld_families), | |
856 | families = devm_kmemdup(&pdev->dev, mrfld_families, | |
857 | nfamilies * sizeof(mrfld_families), | |
858 | GFP_KERNEL); | |
859 | if (!families) | |
860 | return -ENOMEM; | |
861 | ||
862 | /* Splice memory resource by chunk per family */ | |
863 | for (i = 0; i < nfamilies; i++) { | |
864 | struct mrfld_family *family = &families[i]; | |
865 | ||
866 | family->regs = regs + family->barno * MRFLD_FAMILY_LEN; | |
867 | } | |
868 | ||
869 | mp->families = families; | |
870 | mp->nfamilies = nfamilies; | |
871 | mp->functions = mrfld_functions; | |
872 | mp->nfunctions = ARRAY_SIZE(mrfld_functions); | |
873 | mp->groups = mrfld_groups; | |
874 | mp->ngroups = ARRAY_SIZE(mrfld_groups); | |
875 | mp->pctldesc = mrfld_pinctrl_desc; | |
876 | mp->pctldesc.name = dev_name(&pdev->dev); | |
877 | mp->pctldesc.pins = mrfld_pins; | |
878 | mp->pctldesc.npins = ARRAY_SIZE(mrfld_pins); | |
879 | ||
880 | mp->pctldev = devm_pinctrl_register(&pdev->dev, &mp->pctldesc, mp); | |
881 | if (IS_ERR(mp->pctldev)) { | |
882 | dev_err(&pdev->dev, "failed to register pinctrl driver\n"); | |
883 | return PTR_ERR(mp->pctldev); | |
884 | } | |
885 | ||
886 | platform_set_drvdata(pdev, mp); | |
887 | return 0; | |
888 | } | |
889 | ||
890 | static struct platform_driver mrfld_pinctrl_driver = { | |
891 | .probe = mrfld_pinctrl_probe, | |
892 | .driver = { | |
893 | .name = "pinctrl-merrifield", | |
894 | }, | |
895 | }; | |
896 | ||
897 | static int __init mrfld_pinctrl_init(void) | |
898 | { | |
899 | return platform_driver_register(&mrfld_pinctrl_driver); | |
900 | } | |
901 | subsys_initcall(mrfld_pinctrl_init); | |
902 | ||
903 | static void __exit mrfld_pinctrl_exit(void) | |
904 | { | |
905 | platform_driver_unregister(&mrfld_pinctrl_driver); | |
906 | } | |
907 | module_exit(mrfld_pinctrl_exit); | |
908 | ||
909 | MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); | |
910 | MODULE_DESCRIPTION("Intel Merrifield SoC pinctrl driver"); | |
911 | MODULE_LICENSE("GPL v2"); | |
912 | MODULE_ALIAS("platform:pinctrl-merrifield"); |