projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 2ba384e6 JH |
1 | /* |
| 2 | * PIC32 pinctrl driver | |
| 3 | * | |
| 4 | * Joshua Henderson, <joshua.henderson@microchip.com> | |
| 5 | * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. | |
| 6 | * | |
| 7 | * This program is free software; you can distribute it and/or modify it | |
| 8 | * under the terms of the GNU General Public License (Version 2) as | |
| 9 | * published by the Free Software Foundation. | |
| 10 | * | |
| 11 | * This program is distributed in the hope it will be useful, but WITHOUT | |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
| 14 | * for more details. | |
| 15 | */ | |
| 16 | #ifndef PINCTRL_PINCTRL_PIC32_H | |
| 17 | #define PINCTRL_PINCTRL_PIC32_H | |
| 18 | ||
| 19 | /* PORT Registers */ | |
| 20 | #define ANSEL_REG 0x00 | |
| 21 | #define TRIS_REG 0x10 | |
| 22 | #define PORT_REG 0x20 | |
| 23 | #define LAT_REG 0x30 | |
| 24 | #define ODCU_REG 0x40 | |
| 25 | #define CNPU_REG 0x50 | |
| 26 | #define CNPD_REG 0x60 | |
| 27 | #define CNCON_REG 0x70 | |
| 28 | #define CNEN_REG 0x80 | |
| 29 | #define CNSTAT_REG 0x90 | |
| 30 | #define CNNE_REG 0xA0 | |
| 31 | #define CNF_REG 0xB0 | |
| 32 | ||
| 33 | /* Input PPS Registers */ | |
| 34 | #define INT1R 0x04 | |
| 35 | #define INT2R 0x08 | |
| 36 | #define INT3R 0x0C | |
| 37 | #define INT4R 0x10 | |
| 38 | #define T2CKR 0x18 | |
| 39 | #define T3CKR 0x1C | |
| 40 | #define T4CKR 0x20 | |
| 41 | #define T5CKR 0x24 | |
| 42 | #define T6CKR 0x28 | |
| 43 | #define T7CKR 0x2C | |
| 44 | #define T8CKR 0x30 | |
| 45 | #define T9CKR 0x34 | |
| 46 | #define IC1R 0x38 | |
| 47 | #define IC2R 0x3C | |
| 48 | #define IC3R 0x40 | |
| 49 | #define IC4R 0x44 | |
| 50 | #define IC5R 0x48 | |
| 51 | #define IC6R 0x4C | |
| 52 | #define IC7R 0x50 | |
| 53 | #define IC8R 0x54 | |
| 54 | #define IC9R 0x58 | |
| 55 | #define OCFAR 0x60 | |
| 56 | #define U1RXR 0x68 | |
| 57 | #define U1CTSR 0x6C | |
| 58 | #define U2RXR 0x70 | |
| 59 | #define U2CTSR 0x74 | |
| 60 | #define U3RXR 0x78 | |
| 61 | #define U3CTSR 0x7C | |
| 62 | #define U4RXR 0x80 | |
| 63 | #define U4CTSR 0x84 | |
| 64 | #define U5RXR 0x88 | |
| 65 | #define U5CTSR 0x8C | |
| 66 | #define U6RXR 0x90 | |
| 67 | #define U6CTSR 0x94 | |
| 68 | #define SDI1R 0x9C | |
| 69 | #define SS1INR 0xA0 | |
| 70 | #define SDI2R 0xA8 | |
| 71 | #define SS2INR 0xAC | |
| 72 | #define SDI3R 0xB4 | |
| 73 | #define SS3INR 0xB8 | |
| 74 | #define SDI4R 0xC0 | |
| 75 | #define SS4INR 0xC4 | |
| 76 | #define SDI5R 0xCC | |
| 77 | #define SS5INR 0xD0 | |
| 78 | #define SDI6R 0xD8 | |
| 79 | #define SS6INR 0xDC | |
| 80 | #define C1RXR 0xE0 | |
| 81 | #define C2RXR 0xE4 | |
| 82 | #define REFCLKI1R 0xE8 | |
| 83 | #define REFCLKI3R 0xF0 | |
| 84 | #define REFCLKI4R 0xF4 | |
| 85 | ||
| 86 | /* Output PPS Registers */ | |
| 87 | #define RPA14R 0x138 | |
| 88 | #define RPA15R 0x13C | |
| 89 | #define RPB0R 0x140 | |
| 90 | #define RPB1R 0x144 | |
| 91 | #define RPB2R 0x148 | |
| 92 | #define RPB3R 0x14C | |
| 93 | #define RPB5R 0x154 | |
| 94 | #define RPB6R 0x158 | |
| 95 | #define RPB7R 0x15C | |
| 96 | #define RPB8R 0x160 | |
| 97 | #define RPB9R 0x164 | |
| 98 | #define RPB10R 0x168 | |
| 99 | #define RPB14R 0x178 | |
| 100 | #define RPB15R 0x17C | |
| 101 | #define RPC1R 0x184 | |
| 102 | #define RPC2R 0x188 | |
| 103 | #define RPC3R 0x18C | |
| 104 | #define RPC4R 0x190 | |
| 105 | #define RPC13R 0x1B4 | |
| 106 | #define RPC14R 0x1B8 | |
| 107 | #define RPD0R 0x1C0 | |
| 108 | #define RPD1R 0x1C4 | |
| 109 | #define RPD2R 0x1C8 | |
| 110 | #define RPD3R 0x1CC | |
| 111 | #define RPD4R 0x1D0 | |
| 112 | #define RPD5R 0x1D4 | |
| 113 | #define RPD6R 0x1D8 | |
| 114 | #define RPD7R 0x1DC | |
| 115 | #define RPD9R 0x1E4 | |
| 116 | #define RPD10R 0x1E8 | |
| 117 | #define RPD11R 0x1EC | |
| 118 | #define RPD12R 0x1F0 | |
| 119 | #define RPD14R 0x1F8 | |
| 120 | #define RPD15R 0x1FC | |
| 121 | #define RPE3R 0x20C | |
| 122 | #define RPE5R 0x214 | |
| 123 | #define RPE8R 0x220 | |
| 124 | #define RPE9R 0x224 | |
| 125 | #define RPF0R 0x240 | |
| 126 | #define RPF1R 0x244 | |
| 127 | #define RPF2R 0x248 | |
| 128 | #define RPF3R 0x24C | |
| 129 | #define RPF4R 0x250 | |
| 130 | #define RPF5R 0x254 | |
| 131 | #define RPF8R 0x260 | |
| 132 | #define RPF12R 0x270 | |
| 133 | #define RPF13R 0x274 | |
| 134 | #define RPG0R 0x280 | |
| 135 | #define RPG1R 0x284 | |
| 136 | #define RPG6R 0x298 | |
| 137 | #define RPG7R 0x29C | |
| 138 | #define RPG8R 0x2A0 | |
| 139 | #define RPG9R 0x2A4 | |
| 140 | ||
| 141 | #endif /* PINCTRL_PINCTRL_PIC32_H */ |