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Merge remote-tracking branch 'pinctrl/for-next'
[deliverable/linux.git] / drivers / pinctrl / samsung / pinctrl-exynos.c
CommitLineData
43b169db
TA		 1/*
2 * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2012 Linaro Ltd
7 * http://www.linaro.org
8 *
9 * Author: Thomas Abraham <thomas.ab@samsung.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This file contains the Samsung Exynos specific information required by the
17 * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
18 * external gpio and wakeup interrupt support.
19 */
20
21#include <linux/module.h>
22#include <linux/device.h>
23#include <linux/interrupt.h>
24#include <linux/irqdomain.h>
25#include <linux/irq.h>
de88cbb7 26#include <linux/irqchip/chained_irq.h>
43b169db
TA		 27#include <linux/of_irq.h>
28#include <linux/io.h>
29#include <linux/slab.h>
19846950 30#include <linux/spinlock.h>
43b169db
TA		 31#include <linux/err.h>
32
43b169db
TA		 33#include "pinctrl-samsung.h"
34#include "pinctrl-exynos.h"
35
2e4a4fda
TF		 36struct exynos_irq_chip {
37 struct irq_chip chip;
38
39 u32 eint_con;
40 u32 eint_mask;
41 u32 eint_pend;
42};
43
44static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip)
45{
46 return container_of(chip, struct exynos_irq_chip, chip);
47}
499147c9 48
94ce944b 49static const struct samsung_pin_bank_type bank_type_off = {
499147c9 50 .fld_width = { 4, 1, 2, 2, 2, 2, },
43fc9e7f 51 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
499147c9
TF		 52};
53
94ce944b 54static const struct samsung_pin_bank_type bank_type_alive = {
499147c9 55 .fld_width = { 4, 1, 2, 2, },
43fc9e7f 56 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
499147c9
TF		 57};
58
2e4a4fda 59static void exynos_irq_mask(struct irq_data *irqd)
43b169db 60{
2e4a4fda
TF		 61 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
62 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
595be726
TF		 63 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
64 struct samsung_pinctrl_drv_data *d = bank->drvdata;
2e4a4fda 65 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
43b169db 66 unsigned long mask;
5ae8cf79
DA		 67 unsigned long flags;
68
69 spin_lock_irqsave(&bank->slock, flags);
43b169db
TA		 70
71 mask = readl(d->virt_base + reg_mask);
5ace03fb 72 mask |= 1 << irqd->hwirq;
43b169db 73 writel(mask, d->virt_base + reg_mask);
5ae8cf79
DA		 74
75 spin_unlock_irqrestore(&bank->slock, flags);
43b169db
TA		 76}
77
2e4a4fda 78static void exynos_irq_ack(struct irq_data *irqd)
43b169db 79{
2e4a4fda
TF		 80 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
81 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
595be726
TF		 82 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
83 struct samsung_pinctrl_drv_data *d = bank->drvdata;
2e4a4fda 84 unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset;
43b169db 85
5ace03fb 86 writel(1 << irqd->hwirq, d->virt_base + reg_pend);
43b169db
TA		 87}
88
2e4a4fda 89static void exynos_irq_unmask(struct irq_data *irqd)
43b169db 90{
2e4a4fda
TF		 91 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
92 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
595be726
TF		 93 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
94 struct samsung_pinctrl_drv_data *d = bank->drvdata;
2e4a4fda 95 unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset;
43b169db 96 unsigned long mask;
5ae8cf79 97 unsigned long flags;
43b169db 98
5a68e7a7
DA		 99 /*
100 * Ack level interrupts right before unmask
101 *
102 * If we don't do this we'll get a double-interrupt. Level triggered
103 * interrupts must not fire an interrupt if the level is not
104 * _currently_ active, even if it was active while the interrupt was
105 * masked.
106 */
107 if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
2e4a4fda 108 exynos_irq_ack(irqd);
5a68e7a7 109
5ae8cf79 110 spin_lock_irqsave(&bank->slock, flags);
43b169db
TA		 111
112 mask = readl(d->virt_base + reg_mask);
5ace03fb 113 mask &= ~(1 << irqd->hwirq);
43b169db 114 writel(mask, d->virt_base + reg_mask);
5ae8cf79
DA		 115
116 spin_unlock_irqrestore(&bank->slock, flags);
43b169db
TA		 117}
118
2e4a4fda 119static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
43b169db 120{
2e4a4fda
TF		 121 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
122 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
595be726
TF		 123 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
124 struct samsung_pinctrl_drv_data *d = bank->drvdata;
f6a8249f 125 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
43b169db 126 unsigned int con, trig_type;
2e4a4fda 127 unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
43b169db
TA		 128
129 switch (type) {
130 case IRQ_TYPE_EDGE_RISING:
131 trig_type = EXYNOS_EINT_EDGE_RISING;
132 break;
133 case IRQ_TYPE_EDGE_FALLING:
134 trig_type = EXYNOS_EINT_EDGE_FALLING;
135 break;
136 case IRQ_TYPE_EDGE_BOTH:
137 trig_type = EXYNOS_EINT_EDGE_BOTH;
138 break;
139 case IRQ_TYPE_LEVEL_HIGH:
140 trig_type = EXYNOS_EINT_LEVEL_HIGH;
141 break;
142 case IRQ_TYPE_LEVEL_LOW:
143 trig_type = EXYNOS_EINT_LEVEL_LOW;
144 break;
145 default:
146 pr_err("unsupported external interrupt type\n");
147 return -EINVAL;
148 }
149
150 if (type & IRQ_TYPE_EDGE_BOTH)
40ec168a 151 irq_set_handler_locked(irqd, handle_edge_irq);
43b169db 152 else
40ec168a 153 irq_set_handler_locked(irqd, handle_level_irq);
43b169db
TA		 154
155 con = readl(d->virt_base + reg_con);
156 con &= ~(EXYNOS_EINT_CON_MASK << shift);
157 con |= trig_type << shift;
158 writel(con, d->virt_base + reg_con);
ee2f573c 159
f6a8249f
TF		 160 return 0;
161}
162
163static int exynos_irq_request_resources(struct irq_data *irqd)
164{
165 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
166 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
167 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
94ce944b 168 const struct samsung_pin_bank_type *bank_type = bank->type;
f6a8249f
TF		 169 struct samsung_pinctrl_drv_data *d = bank->drvdata;
170 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
171 unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
172 unsigned long flags;
173 unsigned int mask;
174 unsigned int con;
175 int ret;
176
e3a2e878 177 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq);
f6a8249f 178 if (ret) {
58383c78
LW		 179 dev_err(bank->gpio_chip.parent,
180 "unable to lock pin %s-%lu IRQ\n",
f6a8249f
TF		 181 bank->name, irqd->hwirq);
182 return ret;
183 }
184
43fc9e7f 185 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
f6a8249f 186 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
499147c9 187 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
ee2f573c 188
19846950
TF		 189 spin_lock_irqsave(&bank->slock, flags);
190
ee2f573c
TF		 191 con = readl(d->virt_base + reg_con);
192 con &= ~(mask << shift);
193 con |= EXYNOS_EINT_FUNC << shift;
194 writel(con, d->virt_base + reg_con);
195
19846950
TF		 196 spin_unlock_irqrestore(&bank->slock, flags);
197
f6a8249f
TF		 198 exynos_irq_unmask(irqd);
199
43b169db
TA		 200 return 0;
201}
202
f6a8249f
TF		 203static void exynos_irq_release_resources(struct irq_data *irqd)
204{
205 struct irq_chip *chip = irq_data_get_irq_chip(irqd);
206 struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
207 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
94ce944b 208 const struct samsung_pin_bank_type *bank_type = bank->type;
f6a8249f
TF		 209 struct samsung_pinctrl_drv_data *d = bank->drvdata;
210 unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
211 unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
212 unsigned long flags;
213 unsigned int mask;
214 unsigned int con;
215
216 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
217 shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
218 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
219
220 exynos_irq_mask(irqd);
221
222 spin_lock_irqsave(&bank->slock, flags);
223
224 con = readl(d->virt_base + reg_con);
225 con &= ~(mask << shift);
226 con |= FUNC_INPUT << shift;
227 writel(con, d->virt_base + reg_con);
228
229 spin_unlock_irqrestore(&bank->slock, flags);
230
e3a2e878 231 gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq);
f6a8249f
TF		 232}
233
43b169db
TA		 234/*
235 * irq_chip for gpio interrupts.
236 */
2e4a4fda
TF		 237static struct exynos_irq_chip exynos_gpio_irq_chip = {
238 .chip = {
239 .name = "exynos_gpio_irq_chip",
240 .irq_unmask = exynos_irq_unmask,
241 .irq_mask = exynos_irq_mask,
242 .irq_ack = exynos_irq_ack,
243 .irq_set_type = exynos_irq_set_type,
f6a8249f
TF		 244 .irq_request_resources = exynos_irq_request_resources,
245 .irq_release_resources = exynos_irq_release_resources,
2e4a4fda
TF		 246 },
247 .eint_con = EXYNOS_GPIO_ECON_OFFSET,
248 .eint_mask = EXYNOS_GPIO_EMASK_OFFSET,
249 .eint_pend = EXYNOS_GPIO_EPEND_OFFSET,
43b169db
TA		 250};
251
6f5e41bd 252static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq,
43b169db
TA		 253 irq_hw_number_t hw)
254{
595be726 255 struct samsung_pin_bank *b = h->host_data;
43b169db 256
595be726 257 irq_set_chip_data(virq, b);
0d3d30db 258 irq_set_chip_and_handler(virq, &b->irq_chip->chip,
43b169db 259 handle_level_irq);
43b169db
TA		 260 return 0;
261}
262
43b169db 263/*
6f5e41bd 264 * irq domain callbacks for external gpio and wakeup interrupt controllers.
43b169db 265 */
6f5e41bd
AK		 266static const struct irq_domain_ops exynos_eint_irqd_ops = {
267 .map = exynos_eint_irq_map,
43b169db
TA		 268 .xlate = irq_domain_xlate_twocell,
269};
270
271static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
272{
273 struct samsung_pinctrl_drv_data *d = data;
1bf00d7a 274 struct samsung_pin_bank *bank = d->pin_banks;
43b169db
TA		 275 unsigned int svc, group, pin, virq;
276
2e4a4fda 277 svc = readl(d->virt_base + EXYNOS_SVC_OFFSET);
43b169db
TA		 278 group = EXYNOS_SVC_GROUP(svc);
279 pin = svc & EXYNOS_SVC_NUM_MASK;
280
281 if (!group)
282 return IRQ_HANDLED;
283 bank += (group - 1);
284
595be726 285 virq = irq_linear_revmap(bank->irq_domain, pin);
43b169db
TA		 286 if (!virq)
287 return IRQ_NONE;
288 generic_handle_irq(virq);
289 return IRQ_HANDLED;
290}
291
7ccbc60c
TF		 292struct exynos_eint_gpio_save {
293 u32 eint_con;
294 u32 eint_fltcon0;
295 u32 eint_fltcon1;
296};
297
43b169db
TA		 298/*
299 * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
300 * @d: driver data of samsung pinctrl driver.
301 */
302static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
303{
595be726 304 struct samsung_pin_bank *bank;
43b169db 305 struct device *dev = d->dev;
7ccbc60c
TF		 306 int ret;
307 int i;
43b169db
TA		 308
309 if (!d->irq) {
310 dev_err(dev, "irq number not available\n");
311 return -EINVAL;
312 }
313
314 ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq,
315 0, dev_name(dev), d);
316 if (ret) {
317 dev_err(dev, "irq request failed\n");
318 return -ENXIO;
319 }
320
1bf00d7a
TF		 321 bank = d->pin_banks;
322 for (i = 0; i < d->nr_banks; ++i, ++bank) {
595be726
TF		 323 if (bank->eint_type != EINT_TYPE_GPIO)
324 continue;
325 bank->irq_domain = irq_domain_add_linear(bank->of_node,
6f5e41bd 326 bank->nr_pins, &exynos_eint_irqd_ops, bank);
595be726
TF		 327 if (!bank->irq_domain) {
328 dev_err(dev, "gpio irq domain add failed\n");
7ccbc60c
TF		 329 ret = -ENXIO;
330 goto err_domains;
331 }
332
333 bank->soc_priv = devm_kzalloc(d->dev,
334 sizeof(struct exynos_eint_gpio_save), GFP_KERNEL);
335 if (!bank->soc_priv) {
336 irq_domain_remove(bank->irq_domain);
337 ret = -ENOMEM;
338 goto err_domains;
595be726 339 }
0d3d30db
AK		 340
341 bank->irq_chip = &exynos_gpio_irq_chip;
43b169db
TA		 342 }
343
344 return 0;
7ccbc60c
TF		 345
346err_domains:
347 for (--i, --bank; i >= 0; --i, --bank) {
348 if (bank->eint_type != EINT_TYPE_GPIO)
349 continue;
350 irq_domain_remove(bank->irq_domain);
351 }
352
353 return ret;
43b169db
TA		 354}
355
ad350cd9
TF		 356static u32 exynos_eint_wake_mask = 0xffffffff;
357
358u32 exynos_get_eint_wake_mask(void)
359{
360 return exynos_eint_wake_mask;
361}
362
363static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
364{
365 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
366 unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq);
367
368 pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq);
369
370 if (!on)
371 exynos_eint_wake_mask |= bit;
372 else
373 exynos_eint_wake_mask &= ~bit;
374
375 return 0;
376}
377
43b169db
TA		 378/*
379 * irq_chip for wakeup interrupts
380 */
14c255d3 381static struct exynos_irq_chip exynos4210_wkup_irq_chip __initdata = {
2e4a4fda 382 .chip = {
14c255d3 383 .name = "exynos4210_wkup_irq_chip",
2e4a4fda
TF		 384 .irq_unmask = exynos_irq_unmask,
385 .irq_mask = exynos_irq_mask,
386 .irq_ack = exynos_irq_ack,
387 .irq_set_type = exynos_irq_set_type,
388 .irq_set_wake = exynos_wkup_irq_set_wake,
f6a8249f
TF		 389 .irq_request_resources = exynos_irq_request_resources,
390 .irq_release_resources = exynos_irq_release_resources,
2e4a4fda
TF		 391 },
392 .eint_con = EXYNOS_WKUP_ECON_OFFSET,
393 .eint_mask = EXYNOS_WKUP_EMASK_OFFSET,
394 .eint_pend = EXYNOS_WKUP_EPEND_OFFSET,
43b169db
TA		 395};
396
14c255d3
AK		 397static struct exynos_irq_chip exynos7_wkup_irq_chip __initdata = {
398 .chip = {
399 .name = "exynos7_wkup_irq_chip",
400 .irq_unmask = exynos_irq_unmask,
401 .irq_mask = exynos_irq_mask,
402 .irq_ack = exynos_irq_ack,
403 .irq_set_type = exynos_irq_set_type,
404 .irq_set_wake = exynos_wkup_irq_set_wake,
405 .irq_request_resources = exynos_irq_request_resources,
406 .irq_release_resources = exynos_irq_release_resources,
407 },
408 .eint_con = EXYNOS7_WKUP_ECON_OFFSET,
409 .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET,
410 .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET,
411};
412
413/* list of external wakeup controllers supported */
414static const struct of_device_id exynos_wkup_irq_ids[] = {
415 { .compatible = "samsung,exynos4210-wakeup-eint",
416 .data = &exynos4210_wkup_irq_chip },
417 { .compatible = "samsung,exynos7-wakeup-eint",
418 .data = &exynos7_wkup_irq_chip },
419 { }
420};
421
43b169db 422/* interrupt handler for wakeup interrupts 0..15 */
bd0b9ac4 423static void exynos_irq_eint0_15(struct irq_desc *desc)
43b169db 424{
5663bb27 425 struct exynos_weint_data *eintd = irq_desc_get_handler_data(desc);
a04b07c0 426 struct samsung_pin_bank *bank = eintd->bank;
5663bb27 427 struct irq_chip *chip = irq_desc_get_chip(desc);
43b169db
TA		 428 int eint_irq;
429
430 chained_irq_enter(chip, desc);
43b169db 431
a04b07c0 432 eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq);
43b169db 433 generic_handle_irq(eint_irq);
26fecf0b 434
43b169db
TA		 435 chained_irq_exit(chip, desc);
436}
437
a04b07c0
TF		 438static inline void exynos_irq_demux_eint(unsigned long pend,
439 struct irq_domain *domain)
43b169db
TA		 440{
441 unsigned int irq;
442
443 while (pend) {
444 irq = fls(pend) - 1;
a04b07c0 445 generic_handle_irq(irq_find_mapping(domain, irq));
43b169db
TA		 446 pend &= ~(1 << irq);
447 }
448}
449
450/* interrupt handler for wakeup interrupt 16 */
bd0b9ac4 451static void exynos_irq_demux_eint16_31(struct irq_desc *desc)
43b169db 452{
5663bb27
JL		 453 struct irq_chip *chip = irq_desc_get_chip(desc);
454 struct exynos_muxed_weint_data *eintd = irq_desc_get_handler_data(desc);
a04b07c0 455 struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata;
43b169db 456 unsigned long pend;
de59049b 457 unsigned long mask;
a04b07c0 458 int i;
43b169db
TA		 459
460 chained_irq_enter(chip, desc);
a04b07c0
TF		 461
462 for (i = 0; i < eintd->nr_banks; ++i) {
463 struct samsung_pin_bank *b = eintd->banks[i];
0d3d30db 464 pend = readl(d->virt_base + b->irq_chip->eint_pend
2e4a4fda 465 + b->eint_offset);
0d3d30db 466 mask = readl(d->virt_base + b->irq_chip->eint_mask
2e4a4fda 467 + b->eint_offset);
a04b07c0
TF		 468 exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
469 }
470
43b169db
TA		 471 chained_irq_exit(chip, desc);
472}
473
43b169db
TA		 474/*
475 * exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
476 * @d: driver data of samsung pinctrl driver.
477 */
478static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
479{
480 struct device *dev = d->dev;
c3ad056b
TF		 481 struct device_node *wkup_np = NULL;
482 struct device_node *np;
a04b07c0 483 struct samsung_pin_bank *bank;
43b169db 484 struct exynos_weint_data *weint_data;
a04b07c0 485 struct exynos_muxed_weint_data *muxed_data;
14c255d3 486 struct exynos_irq_chip *irq_chip;
a04b07c0
TF		 487 unsigned int muxed_banks = 0;
488 unsigned int i;
43b169db
TA		 489 int idx, irq;
490
c3ad056b 491 for_each_child_of_node(dev->of_node, np) {
14c255d3
AK		 492 const struct of_device_id *match;
493
494 match = of_match_node(exynos_wkup_irq_ids, np);
495 if (match) {
496 irq_chip = kmemdup(match->data,
497 sizeof(*irq_chip), GFP_KERNEL);
c3ad056b
TF		 498 wkup_np = np;
499 break;
500 }
43b169db 501 }
c3ad056b
TF		 502 if (!wkup_np)
503 return -ENODEV;
43b169db 504
1bf00d7a
TF		 505 bank = d->pin_banks;
506 for (i = 0; i < d->nr_banks; ++i, ++bank) {
a04b07c0
TF		 507 if (bank->eint_type != EINT_TYPE_WKUP)
508 continue;
43b169db 509
a04b07c0 510 bank->irq_domain = irq_domain_add_linear(bank->of_node,
6f5e41bd 511 bank->nr_pins, &exynos_eint_irqd_ops, bank);
a04b07c0
TF		 512 if (!bank->irq_domain) {
513 dev_err(dev, "wkup irq domain add failed\n");
514 return -ENXIO;
515 }
43b169db 516
14c255d3 517 bank->irq_chip = irq_chip;
0d3d30db 518
a04b07c0
TF		 519 if (!of_find_property(bank->of_node, "interrupts", NULL)) {
520 bank->eint_type = EINT_TYPE_WKUP_MUX;
521 ++muxed_banks;
522 continue;
523 }
43b169db 524
a04b07c0
TF		 525 weint_data = devm_kzalloc(dev, bank->nr_pins
526 * sizeof(*weint_data), GFP_KERNEL);
527 if (!weint_data) {
528 dev_err(dev, "could not allocate memory for weint_data\n");
529 return -ENOMEM;
530 }
43b169db 531
a04b07c0
TF		 532 for (idx = 0; idx < bank->nr_pins; ++idx) {
533 irq = irq_of_parse_and_map(bank->of_node, idx);
534 if (!irq) {
535 dev_err(dev, "irq number for eint-%s-%d not found\n",
536 bank->name, idx);
537 continue;
538 }
539 weint_data[idx].irq = idx;
540 weint_data[idx].bank = bank;
c21f7849
TG		 541 irq_set_chained_handler_and_data(irq,
542 exynos_irq_eint0_15,
543 &weint_data[idx]);
43b169db
TA		 544 }
545 }
a04b07c0
TF		 546
547 if (!muxed_banks)
548 return 0;
549
550 irq = irq_of_parse_and_map(wkup_np, 0);
551 if (!irq) {
552 dev_err(dev, "irq number for muxed EINTs not found\n");
553 return 0;
554 }
555
556 muxed_data = devm_kzalloc(dev, sizeof(*muxed_data)
557 + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL);
558 if (!muxed_data) {
559 dev_err(dev, "could not allocate memory for muxed_data\n");
560 return -ENOMEM;
561 }
562
bb56fc35
TG		 563 irq_set_chained_handler_and_data(irq, exynos_irq_demux_eint16_31,
564 muxed_data);
a04b07c0 565
1bf00d7a 566 bank = d->pin_banks;
a04b07c0 567 idx = 0;
1bf00d7a 568 for (i = 0; i < d->nr_banks; ++i, ++bank) {
a04b07c0
TF		 569 if (bank->eint_type != EINT_TYPE_WKUP_MUX)
570 continue;
571
572 muxed_data->banks[idx++] = bank;
573 }
574 muxed_data->nr_banks = muxed_banks;
575
43b169db
TA		 576 return 0;
577}
578
7ccbc60c
TF		 579static void exynos_pinctrl_suspend_bank(
580 struct samsung_pinctrl_drv_data *drvdata,
581 struct samsung_pin_bank *bank)
582{
583 struct exynos_eint_gpio_save *save = bank->soc_priv;
584 void __iomem *regs = drvdata->virt_base;
585
586 save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
587 + bank->eint_offset);
588 save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
589 + 2 * bank->eint_offset);
590 save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
591 + 2 * bank->eint_offset + 4);
592
593 pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
594 pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
595 pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
596}
597
598static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
599{
1bf00d7a 600 struct samsung_pin_bank *bank = drvdata->pin_banks;
7ccbc60c
TF		 601 int i;
602
1bf00d7a 603 for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
7ccbc60c
TF		 604 if (bank->eint_type == EINT_TYPE_GPIO)
605 exynos_pinctrl_suspend_bank(drvdata, bank);
606}
607
608static void exynos_pinctrl_resume_bank(
609 struct samsung_pinctrl_drv_data *drvdata,
610 struct samsung_pin_bank *bank)
611{
612 struct exynos_eint_gpio_save *save = bank->soc_priv;
613 void __iomem *regs = drvdata->virt_base;
614
615 pr_debug("%s: con %#010x => %#010x\n", bank->name,
616 readl(regs + EXYNOS_GPIO_ECON_OFFSET
617 + bank->eint_offset), save->eint_con);
618 pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
619 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
620 + 2 * bank->eint_offset), save->eint_fltcon0);
621 pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
622 readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
623 + 2 * bank->eint_offset + 4), save->eint_fltcon1);
624
625 writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
626 + bank->eint_offset);
627 writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
628 + 2 * bank->eint_offset);
629 writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
630 + 2 * bank->eint_offset + 4);
631}
632
633static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
634{
1bf00d7a 635 struct samsung_pin_bank *bank = drvdata->pin_banks;
7ccbc60c
TF		 636 int i;
637
1bf00d7a 638 for (i = 0; i < drvdata->nr_banks; ++i, ++bank)
7ccbc60c
TF		 639 if (bank->eint_type == EINT_TYPE_GPIO)
640 exynos_pinctrl_resume_bank(drvdata, bank);
641}
642
608a26a7 643/* pin banks of s5pv210 pin-controller */
8100cf47 644static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = {
608a26a7 645 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
48802925 646 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
608a26a7
MK		 647 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
648 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
649 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
650 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
48802925
MK		 651 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
652 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c),
653 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20),
654 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24),
608a26a7
MK		 655 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28),
656 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c),
48802925 657 EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30),
608a26a7
MK		 658 EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34),
659 EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38),
660 EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c),
661 EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40),
662 EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),
663 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44),
664 EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48),
665 EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c),
666 EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50),
667 EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54),
668 EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"),
669 EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"),
670 EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"),
671 EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"),
672 EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"),
673 EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"),
674 EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"),
675 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00),
676 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04),
677 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08),
678 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c),
679};
680
1bf00d7a 681const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = {
608a26a7
MK		 682 {
683 /* pin-controller instance 0 data */
684 .pin_banks = s5pv210_pin_bank,
685 .nr_banks = ARRAY_SIZE(s5pv210_pin_bank),
608a26a7
MK		 686 .eint_gpio_init = exynos_eint_gpio_init,
687 .eint_wkup_init = exynos_eint_wkup_init,
688 .suspend = exynos_pinctrl_suspend,
689 .resume = exynos_pinctrl_resume,
608a26a7
MK		 690 },
691};
692
d97f5b98 693/* pin banks of exynos3250 pin-controller 0 */
8100cf47 694static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = {
d97f5b98
TF		 695 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
696 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
697 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
698 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
699 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
700 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
701 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18),
702};
703
704/* pin banks of exynos3250 pin-controller 1 */
8100cf47 705static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = {
d97f5b98
TF		 706 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"),
707 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"),
708 EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"),
709 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),
710 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
711 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
712 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18),
713 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
714 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
715 EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c),
716 EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30),
717 EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34),
718 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
719 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
720 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
721 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
722};
723
724/*
725 * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes
726 * two gpio/pin-mux/pinconfig controllers.
727 */
1bf00d7a 728const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = {
d97f5b98
TF		 729 {
730 /* pin-controller instance 0 data */
731 .pin_banks = exynos3250_pin_banks0,
732 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0),
d97f5b98
TF		 733 .eint_gpio_init = exynos_eint_gpio_init,
734 .suspend = exynos_pinctrl_suspend,
735 .resume = exynos_pinctrl_resume,
d97f5b98
TF		 736 }, {
737 /* pin-controller instance 1 data */
738 .pin_banks = exynos3250_pin_banks1,
739 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1),
d97f5b98
TF		 740 .eint_gpio_init = exynos_eint_gpio_init,
741 .eint_wkup_init = exynos_eint_wkup_init,
742 .suspend = exynos_pinctrl_suspend,
743 .resume = exynos_pinctrl_resume,
d97f5b98
TF		 744 },
745};
746
43b169db 747/* pin banks of exynos4210 pin-controller 0 */
8100cf47 748static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = {
1b6056d6
TF		 749 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
750 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
751 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
752 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
753 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
754 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
755 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
756 EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c),
757 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
758 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24),
759 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28),
760 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c),
761 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
762 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
763 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
764 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
43b169db
TA		 765};
766
767/* pin banks of exynos4210 pin-controller 1 */
8100cf47 768static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = {
1b6056d6
TF		 769 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
770 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
771 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
772 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
773 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
774 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
775 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18),
776 EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c),
777 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
40ba6227
TF		 778 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
779 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
780 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
781 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
782 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
783 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
784 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
a04b07c0
TF		 785 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
786 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
787 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
788 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
43b169db
TA		 789};
790
791/* pin banks of exynos4210 pin-controller 2 */
8100cf47 792static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = {
40ba6227 793 EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
43b169db
TA		 794};
795
796/*
797 * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
798 * three gpio/pin-mux/pinconfig controllers.
799 */
1bf00d7a 800const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = {
43b169db
TA		 801 {
802 /* pin-controller instance 0 data */
803 .pin_banks = exynos4210_pin_banks0,
804 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0),
43b169db 805 .eint_gpio_init = exynos_eint_gpio_init,
7ccbc60c
TF		 806 .suspend = exynos_pinctrl_suspend,
807 .resume = exynos_pinctrl_resume,
43b169db
TA		 808 }, {
809 /* pin-controller instance 1 data */
810 .pin_banks = exynos4210_pin_banks1,
811 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1),
43b169db
TA		 812 .eint_gpio_init = exynos_eint_gpio_init,
813 .eint_wkup_init = exynos_eint_wkup_init,
7ccbc60c
TF		 814 .suspend = exynos_pinctrl_suspend,
815 .resume = exynos_pinctrl_resume,
43b169db
TA		 816 }, {
817 /* pin-controller instance 2 data */
818 .pin_banks = exynos4210_pin_banks2,
819 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2),
43b169db
TA		 820 },
821};
6edc794a
TF		 822
823/* pin banks of exynos4x12 pin-controller 0 */
8100cf47 824static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = {
6edc794a
TF		 825 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
826 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
827 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
828 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
829 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
830 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
831 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
832 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
833 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
834 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
835 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
836 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),
837 EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),
838};
839
840/* pin banks of exynos4x12 pin-controller 1 */
8100cf47 841static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = {
6edc794a
TF		 842 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
843 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
844 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
845 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
846 EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),
847 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),
848 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
849 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
850 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
851 EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
852 EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
853 EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
854 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
855 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
856 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
857 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
858 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
859 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
860 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
861 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
862 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
863 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
864 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
865};
866
867/* pin banks of exynos4x12 pin-controller 2 */
8100cf47 868static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = {
6edc794a
TF		 869 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
870};
871
872/* pin banks of exynos4x12 pin-controller 3 */
8100cf47 873static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = {
6edc794a
TF		 874 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
875 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
876 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
877 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),
878 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),
879};
880
881/*
882 * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes
883 * four gpio/pin-mux/pinconfig controllers.
884 */
1bf00d7a 885const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = {
6edc794a
TF		 886 {
887 /* pin-controller instance 0 data */
888 .pin_banks = exynos4x12_pin_banks0,
889 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0),
6edc794a 890 .eint_gpio_init = exynos_eint_gpio_init,
7ccbc60c
TF		 891 .suspend = exynos_pinctrl_suspend,
892 .resume = exynos_pinctrl_resume,
6edc794a
TF		 893 }, {
894 /* pin-controller instance 1 data */
895 .pin_banks = exynos4x12_pin_banks1,
896 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1),
6edc794a
TF		 897 .eint_gpio_init = exynos_eint_gpio_init,
898 .eint_wkup_init = exynos_eint_wkup_init,
7ccbc60c
TF		 899 .suspend = exynos_pinctrl_suspend,
900 .resume = exynos_pinctrl_resume,
6edc794a
TF		 901 }, {
902 /* pin-controller instance 2 data */
903 .pin_banks = exynos4x12_pin_banks2,
904 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2),
6edc794a 905 .eint_gpio_init = exynos_eint_gpio_init,
7ccbc60c
TF		 906 .suspend = exynos_pinctrl_suspend,
907 .resume = exynos_pinctrl_resume,
6edc794a
TF		 908 }, {
909 /* pin-controller instance 3 data */
910 .pin_banks = exynos4x12_pin_banks3,
911 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3),
6edc794a 912 .eint_gpio_init = exynos_eint_gpio_init,
7ccbc60c
TF		 913 .suspend = exynos_pinctrl_suspend,
914 .resume = exynos_pinctrl_resume,
6edc794a
TF		 915 },
916};
f67faf48 917
2891ba29
TF		 918/* pin banks of exynos4415 pin-controller 0 */
919static const struct samsung_pin_bank_data exynos4415_pin_banks0[] = {
920 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
921 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
922 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
923 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
924 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
925 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
926 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
927 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
928 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
929 EXYNOS_PIN_BANK_EINTG(1, 0x1C0, "gpf2", 0x38),
930};
931
932/* pin banks of exynos4415 pin-controller 1 */
933static const struct samsung_pin_bank_data exynos4415_pin_banks1[] = {
934 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),
935 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
936 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
937 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
938 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpl0", 0x18),
939 EXYNOS_PIN_BANK_EINTN(6, 0x120, "mp00"),
940 EXYNOS_PIN_BANK_EINTN(4, 0x140, "mp01"),
941 EXYNOS_PIN_BANK_EINTN(6, 0x160, "mp02"),
942 EXYNOS_PIN_BANK_EINTN(8, 0x180, "mp03"),
943 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "mp04"),
944 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "mp05"),
945 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "mp06"),
946 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
947 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
948 EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
949 EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
950 EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
951 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
952 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
953 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
954 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
955};
956
957/* pin banks of exynos4415 pin-controller 2 */
958static const struct samsung_pin_bank_data exynos4415_pin_banks2[] = {
959 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
960 EXYNOS_PIN_BANK_EINTN(2, 0x000, "etc1"),
961};
962
963/*
964 * Samsung pinctrl driver data for Exynos4415 SoC. Exynos4415 SoC includes
965 * three gpio/pin-mux/pinconfig controllers.
966 */
967const struct samsung_pin_ctrl exynos4415_pin_ctrl[] = {
968 {
969 /* pin-controller instance 0 data */
970 .pin_banks = exynos4415_pin_banks0,
971 .nr_banks = ARRAY_SIZE(exynos4415_pin_banks0),
972 .eint_gpio_init = exynos_eint_gpio_init,
973 .suspend = exynos_pinctrl_suspend,
974 .resume = exynos_pinctrl_resume,
975 }, {
976 /* pin-controller instance 1 data */
977 .pin_banks = exynos4415_pin_banks1,
978 .nr_banks = ARRAY_SIZE(exynos4415_pin_banks1),
979 .eint_gpio_init = exynos_eint_gpio_init,
980 .eint_wkup_init = exynos_eint_wkup_init,
981 .suspend = exynos_pinctrl_suspend,
982 .resume = exynos_pinctrl_resume,
983 }, {
984 /* pin-controller instance 2 data */
985 .pin_banks = exynos4415_pin_banks2,
986 .nr_banks = ARRAY_SIZE(exynos4415_pin_banks2),
987 .eint_gpio_init = exynos_eint_gpio_init,
988 .suspend = exynos_pinctrl_suspend,
989 .resume = exynos_pinctrl_resume,
990 },
991};
992
f67faf48 993/* pin banks of exynos5250 pin-controller 0 */
8100cf47 994static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = {
f67faf48
TA		 995 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
996 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
997 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
998 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
999 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
1000 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
1001 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
1002 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
1003 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
1004 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
1005 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
1006 EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
1007 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
1008 EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
1009 EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
1010 EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
1011 EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
1012 EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
1013 EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
1014 EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
1015 EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
1016 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
1017 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
1018 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
1019 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
1020};
1021
1022/* pin banks of exynos5250 pin-controller 1 */
8100cf47 1023static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = {
f67faf48
TA		 1024 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
1025 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
1026 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
1027 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
1028 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
1029 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
1030 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
1031 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
1032 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
1033};
1034
1035/* pin banks of exynos5250 pin-controller 2 */
8100cf47 1036static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = {
f67faf48
TA		 1037 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
1038 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
1039 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
1040 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
1041 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
1042};
1043
1044/* pin banks of exynos5250 pin-controller 3 */
8100cf47 1045static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = {
f67faf48
TA		 1046 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
1047};
1048
1049/*
1050 * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
1051 * four gpio/pin-mux/pinconfig controllers.
1052 */
1bf00d7a 1053const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = {
f67faf48
TA		 1054 {
1055 /* pin-controller instance 0 data */
1056 .pin_banks = exynos5250_pin_banks0,
1057 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0),
f67faf48
TA		 1058 .eint_gpio_init = exynos_eint_gpio_init,
1059 .eint_wkup_init = exynos_eint_wkup_init,
7ccbc60c
TF		 1060 .suspend = exynos_pinctrl_suspend,
1061 .resume = exynos_pinctrl_resume,
f67faf48
TA		 1062 }, {
1063 /* pin-controller instance 1 data */
1064 .pin_banks = exynos5250_pin_banks1,
1065 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1),
f67faf48 1066 .eint_gpio_init = exynos_eint_gpio_init,
7ccbc60c
TF		 1067 .suspend = exynos_pinctrl_suspend,
1068 .resume = exynos_pinctrl_resume,
f67faf48
TA		 1069 }, {
1070 /* pin-controller instance 2 data */
1071 .pin_banks = exynos5250_pin_banks2,
1072 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2),
f67faf48 1073 .eint_gpio_init = exynos_eint_gpio_init,
7ccbc60c
TF		 1074 .suspend = exynos_pinctrl_suspend,
1075 .resume = exynos_pinctrl_resume,
f67faf48
TA		 1076 }, {
1077 /* pin-controller instance 3 data */
1078 .pin_banks = exynos5250_pin_banks3,
1079 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3),
f67faf48 1080 .eint_gpio_init = exynos_eint_gpio_init,
7ccbc60c
TF		 1081 .suspend = exynos_pinctrl_suspend,
1082 .resume = exynos_pinctrl_resume,
f67faf48
TA		 1083 },
1084};
983dbeb3 1085
9a8b6079 1086/* pin banks of exynos5260 pin-controller 0 */
8100cf47 1087static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = {
9a8b6079
YGJ		 1088 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
1089 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
1090 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
1091 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
1092 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),
1093 EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14),
1094 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18),
1095 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c),
1096 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20),
1097 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24),
1098 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28),
1099 EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
1100 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30),
1101 EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34),
1102 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38),
1103 EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c),
1104 EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40),
1105 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
1106 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
1107 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
1108 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
1109};
1110
1111/* pin banks of exynos5260 pin-controller 1 */
8100cf47 1112static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = {
9a8b6079
YGJ		 1113 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
1114 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
1115 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
1116 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
1117 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10),
1118};
1119
1120/* pin banks of exynos5260 pin-controller 2 */
8100cf47 1121static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = {
9a8b6079
YGJ		 1122 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
1123 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
1124};
1125
1126/*
1127 * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes
1128 * three gpio/pin-mux/pinconfig controllers.
1129 */
1bf00d7a 1130const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = {
9a8b6079
YGJ		 1131 {
1132 /* pin-controller instance 0 data */
1133 .pin_banks = exynos5260_pin_banks0,
1134 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0),
9a8b6079
YGJ		 1135 .eint_gpio_init = exynos_eint_gpio_init,
1136 .eint_wkup_init = exynos_eint_wkup_init,
9a8b6079
YGJ		 1137 }, {
1138 /* pin-controller instance 1 data */
1139 .pin_banks = exynos5260_pin_banks1,
1140 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1),
9a8b6079 1141 .eint_gpio_init = exynos_eint_gpio_init,
9a8b6079
YGJ		 1142 }, {
1143 /* pin-controller instance 2 data */
1144 .pin_banks = exynos5260_pin_banks2,
1145 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2),
9a8b6079 1146 .eint_gpio_init = exynos_eint_gpio_init,
9a8b6079
YGJ		 1147 },
1148};
1149
023e06df
HK		 1150/* pin banks of exynos5410 pin-controller 0 */
1151static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = {
1152 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
1153 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
1154 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
1155 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
1156 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
1157 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
1158 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
1159 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
1160 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20),
1161 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24),
1162 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28),
1163 EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"),
1164 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c),
1165 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30),
1166 EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34),
1167 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38),
1168 EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c),
1169 EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40),
1170 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44),
1171 EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48),
1172 EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c),
1173 EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50),
1174 EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"),
1175 EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"),
1176 EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"),
1177 EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"),
1178 EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"),
1179 EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"),
1180 EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"),
1181 EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"),
1182 EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"),
1183 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
1184 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
1185 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
1186 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
1187};
1188
1189/* pin banks of exynos5410 pin-controller 1 */
1190static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = {
1191 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00),
1192 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04),
1193 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08),
1194 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c),
1195 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10),
1196 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14),
1197 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18),
1198 EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c),
1199 EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20),
1200};
1201
1202/* pin banks of exynos5410 pin-controller 2 */
1203static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = {
1204 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
1205 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
1206 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
1207 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
1208 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
1209};
1210
1211/* pin banks of exynos5410 pin-controller 3 */
1212static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = {
1213 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
1214};
1215
1216/*
1217 * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes
1218 * four gpio/pin-mux/pinconfig controllers.
1219 */
1220const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = {
1221 {
1222 /* pin-controller instance 0 data */
1223 .pin_banks = exynos5410_pin_banks0,
1224 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks0),
1225 .eint_gpio_init = exynos_eint_gpio_init,
1226 .eint_wkup_init = exynos_eint_wkup_init,
1227 .suspend = exynos_pinctrl_suspend,
1228 .resume = exynos_pinctrl_resume,
1229 }, {
1230 /* pin-controller instance 1 data */
1231 .pin_banks = exynos5410_pin_banks1,
1232 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks1),
1233 .eint_gpio_init = exynos_eint_gpio_init,
1234 .suspend = exynos_pinctrl_suspend,
1235 .resume = exynos_pinctrl_resume,
1236 }, {
1237 /* pin-controller instance 2 data */
1238 .pin_banks = exynos5410_pin_banks2,
1239 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks2),
1240 .eint_gpio_init = exynos_eint_gpio_init,
1241 .suspend = exynos_pinctrl_suspend,
1242 .resume = exynos_pinctrl_resume,
1243 }, {
1244 /* pin-controller instance 3 data */
1245 .pin_banks = exynos5410_pin_banks3,
1246 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks3),
1247 .eint_gpio_init = exynos_eint_gpio_init,
1248 .suspend = exynos_pinctrl_suspend,
1249 .resume = exynos_pinctrl_resume,
1250 },
1251};
1252
983dbeb3 1253/* pin banks of exynos5420 pin-controller 0 */
8100cf47 1254static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = {
983dbeb3
LKA		 1255 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
1256 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
1257 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
1258 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
1259 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
1260};
1261
1262/* pin banks of exynos5420 pin-controller 1 */
8100cf47 1263static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = {
983dbeb3
LKA		 1264 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00),
1265 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04),
1266 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
1267 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
1268 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10),
1269 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14),
1270 EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"),
1271 EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"),
1272 EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"),
1273 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"),
1274 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"),
1275 EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"),
1276 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"),
1277};
1278
1279/* pin banks of exynos5420 pin-controller 2 */
8100cf47 1280static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = {
983dbeb3
LKA		 1281 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
1282 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
1283 EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08),
1284 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c),
1285 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
1286 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
1287 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
1288 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c),
1289};
1290
1291/* pin banks of exynos5420 pin-controller 3 */
8100cf47 1292static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = {
983dbeb3
LKA		 1293 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
1294 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
1295 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
1296 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
1297 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
1298 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
1299 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),
1300 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c),
1301 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20),
1302};
1303
1304/* pin banks of exynos5420 pin-controller 4 */
8100cf47 1305static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = {
983dbeb3
LKA		 1306 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
1307};
1308
1309/*
1310 * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes
1311 * four gpio/pin-mux/pinconfig controllers.
1312 */
1bf00d7a 1313const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = {
983dbeb3
LKA		 1314 {
1315 /* pin-controller instance 0 data */
1316 .pin_banks = exynos5420_pin_banks0,
1317 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0),
983dbeb3
LKA		 1318 .eint_gpio_init = exynos_eint_gpio_init,
1319 .eint_wkup_init = exynos_eint_wkup_init,
983dbeb3
LKA		 1320 }, {
1321 /* pin-controller instance 1 data */
1322 .pin_banks = exynos5420_pin_banks1,
1323 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1),
983dbeb3 1324 .eint_gpio_init = exynos_eint_gpio_init,
983dbeb3
LKA		 1325 }, {
1326 /* pin-controller instance 2 data */
1327 .pin_banks = exynos5420_pin_banks2,
1328 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2),
983dbeb3 1329 .eint_gpio_init = exynos_eint_gpio_init,
983dbeb3
LKA		 1330 }, {
1331 /* pin-controller instance 3 data */
1332 .pin_banks = exynos5420_pin_banks3,
1333 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3),
983dbeb3 1334 .eint_gpio_init = exynos_eint_gpio_init,
983dbeb3
LKA		 1335 }, {
1336 /* pin-controller instance 4 data */
1337 .pin_banks = exynos5420_pin_banks4,
1338 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4),
983dbeb3 1339 .eint_gpio_init = exynos_eint_gpio_init,
983dbeb3
LKA		 1340 },
1341};
50cea0cf 1342
3c5ecc9e
CC		 1343/* pin banks of exynos5433 pin-controller - ALIVE */
1344static const struct samsung_pin_bank_data exynos5433_pin_banks0[] = {
1345 EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
1346 EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
1347 EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
1348 EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
1349};
1350
1351/* pin banks of exynos5433 pin-controller - AUD */
1352static const struct samsung_pin_bank_data exynos5433_pin_banks1[] = {
1353 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
1354 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
1355};
1356
1357/* pin banks of exynos5433 pin-controller - CPIF */
1358static const struct samsung_pin_bank_data exynos5433_pin_banks2[] = {
1359 EXYNOS_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00),
1360};
1361
1362/* pin banks of exynos5433 pin-controller - eSE */
1363static const struct samsung_pin_bank_data exynos5433_pin_banks3[] = {
1364 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00),
1365};
1366
1367/* pin banks of exynos5433 pin-controller - FINGER */
1368static const struct samsung_pin_bank_data exynos5433_pin_banks4[] = {
1369 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00),
1370};
1371
1372/* pin banks of exynos5433 pin-controller - FSYS */
1373static const struct samsung_pin_bank_data exynos5433_pin_banks5[] = {
1374 EXYNOS_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00),
1375 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04),
1376 EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08),
1377 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c),
1378 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10),
1379 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14),
1380};
1381
1382/* pin banks of exynos5433 pin-controller - IMEM */
1383static const struct samsung_pin_bank_data exynos5433_pin_banks6[] = {
1384 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00),
1385};
1386
1387/* pin banks of exynos5433 pin-controller - NFC */
1388static const struct samsung_pin_bank_data exynos5433_pin_banks7[] = {
1389 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
1390};
1391
1392/* pin banks of exynos5433 pin-controller - PERIC */
1393static const struct samsung_pin_bank_data exynos5433_pin_banks8[] = {
1394 EXYNOS_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00),
1395 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04),
1396 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08),
1397 EXYNOS_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c),
1398 EXYNOS_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10),
1399 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14),
1400 EXYNOS_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18),
1401 EXYNOS_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c),
1402 EXYNOS_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20),
1403 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24),
1404 EXYNOS_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28),
1405 EXYNOS_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c),
1406 EXYNOS_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30),
1407 EXYNOS_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34),
1408 EXYNOS_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38),
1409 EXYNOS_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c),
1410 EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),
1411};
1412
1413/* pin banks of exynos5433 pin-controller - TOUCH */
1414static const struct samsung_pin_bank_data exynos5433_pin_banks9[] = {
1415 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
1416};
1417
1418/*
1419 * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
1420 * ten gpio/pin-mux/pinconfig controllers.
1421 */
1422const struct samsung_pin_ctrl exynos5433_pin_ctrl[] = {
1423 {
1424 /* pin-controller instance 0 data */
1425 .pin_banks = exynos5433_pin_banks0,
1426 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks0),
1427 .eint_wkup_init = exynos_eint_wkup_init,
1428 .suspend = exynos_pinctrl_suspend,
1429 .resume = exynos_pinctrl_resume,
1430 }, {
1431 /* pin-controller instance 1 data */
1432 .pin_banks = exynos5433_pin_banks1,
1433 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks1),
1434 .eint_gpio_init = exynos_eint_gpio_init,
1435 .suspend = exynos_pinctrl_suspend,
1436 .resume = exynos_pinctrl_resume,
1437 }, {
1438 /* pin-controller instance 2 data */
1439 .pin_banks = exynos5433_pin_banks2,
1440 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks2),
1441 .eint_gpio_init = exynos_eint_gpio_init,
1442 .suspend = exynos_pinctrl_suspend,
1443 .resume = exynos_pinctrl_resume,
1444 }, {
1445 /* pin-controller instance 3 data */
1446 .pin_banks = exynos5433_pin_banks3,
1447 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks3),
1448 .eint_gpio_init = exynos_eint_gpio_init,
1449 .suspend = exynos_pinctrl_suspend,
1450 .resume = exynos_pinctrl_resume,
1451 }, {
1452 /* pin-controller instance 4 data */
1453 .pin_banks = exynos5433_pin_banks4,
1454 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks4),
1455 .eint_gpio_init = exynos_eint_gpio_init,
1456 .suspend = exynos_pinctrl_suspend,
1457 .resume = exynos_pinctrl_resume,
1458 }, {
1459 /* pin-controller instance 5 data */
1460 .pin_banks = exynos5433_pin_banks5,
1461 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks5),
1462 .eint_gpio_init = exynos_eint_gpio_init,
1463 .suspend = exynos_pinctrl_suspend,
1464 .resume = exynos_pinctrl_resume,
1465 }, {
1466 /* pin-controller instance 6 data */
1467 .pin_banks = exynos5433_pin_banks6,
1468 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks6),
1469 .eint_gpio_init = exynos_eint_gpio_init,
1470 .suspend = exynos_pinctrl_suspend,
1471 .resume = exynos_pinctrl_resume,
1472 }, {
1473 /* pin-controller instance 7 data */
1474 .pin_banks = exynos5433_pin_banks7,
1475 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks7),
1476 .eint_gpio_init = exynos_eint_gpio_init,
1477 .suspend = exynos_pinctrl_suspend,
1478 .resume = exynos_pinctrl_resume,
1479 }, {
1480 /* pin-controller instance 8 data */
1481 .pin_banks = exynos5433_pin_banks8,
1482 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks8),
1483 .eint_gpio_init = exynos_eint_gpio_init,
1484 .suspend = exynos_pinctrl_suspend,
1485 .resume = exynos_pinctrl_resume,
1486 }, {
1487 /* pin-controller instance 9 data */
1488 .pin_banks = exynos5433_pin_banks9,
1489 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks9),
1490 .eint_gpio_init = exynos_eint_gpio_init,
1491 .suspend = exynos_pinctrl_suspend,
1492 .resume = exynos_pinctrl_resume,
1493 },
1494};
1495
50cea0cf
NKC		 1496/* pin banks of exynos7 pin-controller - ALIVE */
1497static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = {
1498 EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
1499 EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
1500 EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
1501 EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
1502};
1503
1504/* pin banks of exynos7 pin-controller - BUS0 */
1505static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = {
1506 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
1507 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04),
1508 EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08),
1509 EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c),
1510 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10),
1511 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
1512 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
1513 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c),
1514 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20),
1515 EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24),
1516 EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28),
1517 EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c),
1518 EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30),
1519 EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34),
1520 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38),
1521};
1522
1523/* pin banks of exynos7 pin-controller - NFC */
1524static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = {
1525 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
1526};
1527
1528/* pin banks of exynos7 pin-controller - TOUCH */
1529static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = {
1530 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
1531};
1532
1533/* pin banks of exynos7 pin-controller - FF */
1534static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = {
1535 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00),
1536};
1537
1538/* pin banks of exynos7 pin-controller - ESE */
1539static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = {
1540 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00),
1541};
1542
1543/* pin banks of exynos7 pin-controller - FSYS0 */
1544static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = {
1545 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00),
1546};
1547
1548/* pin banks of exynos7 pin-controller - FSYS1 */
1549static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
1550 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00),
1551 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04),
1552 EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08),
1553 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
1554};
1555
d171cd02
VG		 1556/* pin banks of exynos7 pin-controller - BUS1 */
1557static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
1558 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
1559 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04),
1560 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08),
1561 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c),
1562 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),
1563 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14),
1564 EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18),
1565 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c),
1566 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),
1567 EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24),
1568};
1569
ac5a186e
PV		 1570static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = {
1571 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
1572 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
1573};
1574
50cea0cf
NKC		 1575const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
1576 {
1577 /* pin-controller instance 0 Alive data */
1578 .pin_banks = exynos7_pin_banks0,
1579 .nr_banks = ARRAY_SIZE(exynos7_pin_banks0),
50cea0cf
NKC		 1580 .eint_wkup_init = exynos_eint_wkup_init,
1581 }, {
1582 /* pin-controller instance 1 BUS0 data */
1583 .pin_banks = exynos7_pin_banks1,
1584 .nr_banks = ARRAY_SIZE(exynos7_pin_banks1),
1585 .eint_gpio_init = exynos_eint_gpio_init,
1586 }, {
1587 /* pin-controller instance 2 NFC data */
1588 .pin_banks = exynos7_pin_banks2,
1589 .nr_banks = ARRAY_SIZE(exynos7_pin_banks2),
1590 .eint_gpio_init = exynos_eint_gpio_init,
1591 }, {
1592 /* pin-controller instance 3 TOUCH data */
1593 .pin_banks = exynos7_pin_banks3,
1594 .nr_banks = ARRAY_SIZE(exynos7_pin_banks3),
1595 .eint_gpio_init = exynos_eint_gpio_init,
1596 }, {
1597 /* pin-controller instance 4 FF data */
1598 .pin_banks = exynos7_pin_banks4,
1599 .nr_banks = ARRAY_SIZE(exynos7_pin_banks4),
1600 .eint_gpio_init = exynos_eint_gpio_init,
1601 }, {
1602 /* pin-controller instance 5 ESE data */
1603 .pin_banks = exynos7_pin_banks5,
1604 .nr_banks = ARRAY_SIZE(exynos7_pin_banks5),
1605 .eint_gpio_init = exynos_eint_gpio_init,
1606 }, {
1607 /* pin-controller instance 6 FSYS0 data */
1608 .pin_banks = exynos7_pin_banks6,
1609 .nr_banks = ARRAY_SIZE(exynos7_pin_banks6),
1610 .eint_gpio_init = exynos_eint_gpio_init,
1611 }, {
1612 /* pin-controller instance 7 FSYS1 data */
1613 .pin_banks = exynos7_pin_banks7,
1614 .nr_banks = ARRAY_SIZE(exynos7_pin_banks7),
1615 .eint_gpio_init = exynos_eint_gpio_init,
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VG		 1616 }, {
1617 /* pin-controller instance 8 BUS1 data */
1618 .pin_banks = exynos7_pin_banks8,
1619 .nr_banks = ARRAY_SIZE(exynos7_pin_banks8),
1620 .eint_gpio_init = exynos_eint_gpio_init,
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PV		 1621 }, {
1622 /* pin-controller instance 9 AUD data */
1623 .pin_banks = exynos7_pin_banks9,
1624 .nr_banks = ARRAY_SIZE(exynos7_pin_banks9),
1625 .eint_gpio_init = exynos_eint_gpio_init,
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NKC		 1626 },
1627};
Linux kernel - Deliverables
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