Commit | Line | Data |
---|---|---|
2967dab1 | 1 | /* |
b3c185a7 | 2 | * SuperH Pin Function Controller support. |
2967dab1 MD |
3 | * |
4 | * Copyright (C) 2008 Magnus Damm | |
b3c185a7 | 5 | * Copyright (C) 2009 - 2012 Paul Mundt |
2967dab1 MD |
6 | * |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
c6193eac LP |
11 | |
12 | #define DRV_NAME "sh-pfc" | |
f9492fda | 13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
b72421d8 | 14 | |
90efde22 | 15 | #include <linux/bitops.h> |
2967dab1 | 16 | #include <linux/err.h> |
90efde22 | 17 | #include <linux/errno.h> |
2967dab1 | 18 | #include <linux/io.h> |
b0e10211 | 19 | #include <linux/ioport.h> |
90efde22 LP |
20 | #include <linux/kernel.h> |
21 | #include <linux/module.h> | |
ca5481c6 | 22 | #include <linux/pinctrl/machine.h> |
c6193eac | 23 | #include <linux/platform_device.h> |
90efde22 | 24 | #include <linux/slab.h> |
b0e10211 | 25 | |
f9165132 LP |
26 | #include "core.h" |
27 | ||
973931ae | 28 | static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev) |
b0e10211 MD |
29 | { |
30 | struct resource *res; | |
31 | int k; | |
32 | ||
56dc04af | 33 | if (pdev->num_resources == 0) { |
973931ae | 34 | pfc->num_windows = 0; |
b0e10211 | 35 | return 0; |
973931ae | 36 | } |
b0e10211 | 37 | |
56dc04af | 38 | pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources * |
1724acfd | 39 | sizeof(*pfc->window), GFP_NOWAIT); |
b3c185a7 | 40 | if (!pfc->window) |
1724acfd | 41 | return -ENOMEM; |
b0e10211 | 42 | |
56dc04af | 43 | pfc->num_windows = pdev->num_resources; |
973931ae | 44 | |
56dc04af | 45 | for (k = 0, res = pdev->resource; k < pdev->num_resources; k++, res++) { |
b0e10211 | 46 | WARN_ON(resource_type(res) != IORESOURCE_MEM); |
b3c185a7 PM |
47 | pfc->window[k].phys = res->start; |
48 | pfc->window[k].size = resource_size(res); | |
c9fa88e2 LP |
49 | pfc->window[k].virt = devm_ioremap_nocache(pfc->dev, res->start, |
50 | resource_size(res)); | |
51 | if (!pfc->window[k].virt) | |
1724acfd | 52 | return -ENOMEM; |
b0e10211 MD |
53 | } |
54 | ||
55 | return 0; | |
b0e10211 MD |
56 | } |
57 | ||
4aeacd5b LP |
58 | static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, |
59 | unsigned long address) | |
b0e10211 | 60 | { |
4aeacd5b | 61 | struct sh_pfc_window *window; |
b0e10211 MD |
62 | int k; |
63 | ||
64 | /* scan through physical windows and convert address */ | |
973931ae | 65 | for (k = 0; k < pfc->num_windows; k++) { |
b3c185a7 | 66 | window = pfc->window + k; |
b0e10211 MD |
67 | |
68 | if (address < window->phys) | |
69 | continue; | |
70 | ||
71 | if (address >= (window->phys + window->size)) | |
72 | continue; | |
73 | ||
74 | return window->virt + (address - window->phys); | |
75 | } | |
76 | ||
77 | /* no windows defined, register must be 1:1 mapped virt:phys */ | |
78 | return (void __iomem *)address; | |
79 | } | |
2967dab1 | 80 | |
934cb02b LP |
81 | struct sh_pfc_pin *sh_pfc_get_pin(struct sh_pfc *pfc, unsigned int pin) |
82 | { | |
83 | return &pfc->info->pins[pin]; | |
84 | } | |
85 | ||
4aeacd5b | 86 | static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r) |
2967dab1 MD |
87 | { |
88 | if (enum_id < r->begin) | |
89 | return 0; | |
90 | ||
91 | if (enum_id > r->end) | |
92 | return 0; | |
93 | ||
94 | return 1; | |
95 | } | |
96 | ||
4aeacd5b LP |
97 | static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, |
98 | unsigned long reg_width) | |
3292094e MD |
99 | { |
100 | switch (reg_width) { | |
101 | case 8: | |
b0e10211 | 102 | return ioread8(mapped_reg); |
3292094e | 103 | case 16: |
b0e10211 | 104 | return ioread16(mapped_reg); |
3292094e | 105 | case 32: |
b0e10211 | 106 | return ioread32(mapped_reg); |
3292094e MD |
107 | } |
108 | ||
109 | BUG(); | |
110 | return 0; | |
111 | } | |
112 | ||
4aeacd5b LP |
113 | static void sh_pfc_write_raw_reg(void __iomem *mapped_reg, |
114 | unsigned long reg_width, unsigned long data) | |
3292094e MD |
115 | { |
116 | switch (reg_width) { | |
117 | case 8: | |
b0e10211 | 118 | iowrite8(data, mapped_reg); |
3292094e MD |
119 | return; |
120 | case 16: | |
b0e10211 | 121 | iowrite16(data, mapped_reg); |
3292094e MD |
122 | return; |
123 | case 32: | |
b0e10211 | 124 | iowrite32(data, mapped_reg); |
3292094e MD |
125 | return; |
126 | } | |
127 | ||
128 | BUG(); | |
129 | } | |
130 | ||
b3c185a7 | 131 | int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos) |
92554d97 MD |
132 | { |
133 | unsigned long pos; | |
134 | ||
135 | pos = dr->reg_width - (in_pos + 1); | |
136 | ||
137 | pr_debug("read_bit: addr = %lx, pos = %ld, " | |
138 | "r_width = %ld\n", dr->reg, pos, dr->reg_width); | |
139 | ||
4aeacd5b | 140 | return (sh_pfc_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1; |
92554d97 MD |
141 | } |
142 | ||
b3c185a7 PM |
143 | void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos, |
144 | unsigned long value) | |
3292094e MD |
145 | { |
146 | unsigned long pos; | |
147 | ||
148 | pos = dr->reg_width - (in_pos + 1); | |
149 | ||
ca6f2d7f | 150 | pr_debug("write_bit addr = %lx, value = %d, pos = %ld, " |
fd2cb0ce PM |
151 | "r_width = %ld\n", |
152 | dr->reg, !!value, pos, dr->reg_width); | |
3292094e MD |
153 | |
154 | if (value) | |
155 | set_bit(pos, &dr->reg_shadow); | |
156 | else | |
157 | clear_bit(pos, &dr->reg_shadow); | |
158 | ||
4aeacd5b | 159 | sh_pfc_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow); |
3292094e MD |
160 | } |
161 | ||
4aeacd5b LP |
162 | static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, |
163 | struct pinmux_cfg_reg *crp, | |
164 | unsigned long in_pos, | |
165 | void __iomem **mapped_regp, | |
166 | unsigned long *maskp, | |
167 | unsigned long *posp) | |
2967dab1 | 168 | { |
f78a26f5 MD |
169 | int k; |
170 | ||
4aeacd5b | 171 | *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg); |
2967dab1 | 172 | |
f78a26f5 MD |
173 | if (crp->field_width) { |
174 | *maskp = (1 << crp->field_width) - 1; | |
175 | *posp = crp->reg_width - ((in_pos + 1) * crp->field_width); | |
176 | } else { | |
177 | *maskp = (1 << crp->var_field_width[in_pos]) - 1; | |
178 | *posp = crp->reg_width; | |
179 | for (k = 0; k <= in_pos; k++) | |
180 | *posp -= crp->var_field_width[k]; | |
181 | } | |
18925e11 MD |
182 | } |
183 | ||
4aeacd5b LP |
184 | static int sh_pfc_read_config_reg(struct sh_pfc *pfc, |
185 | struct pinmux_cfg_reg *crp, | |
186 | unsigned long field) | |
18925e11 MD |
187 | { |
188 | void __iomem *mapped_reg; | |
189 | unsigned long mask, pos; | |
190 | ||
4aeacd5b | 191 | sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); |
2967dab1 | 192 | |
18925e11 | 193 | pr_debug("read_reg: addr = %lx, field = %ld, " |
fd2cb0ce | 194 | "r_width = %ld, f_width = %ld\n", |
18925e11 | 195 | crp->reg, field, crp->reg_width, crp->field_width); |
2967dab1 | 196 | |
4aeacd5b | 197 | return (sh_pfc_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask; |
0fc64cc0 MD |
198 | } |
199 | ||
4aeacd5b LP |
200 | static void sh_pfc_write_config_reg(struct sh_pfc *pfc, |
201 | struct pinmux_cfg_reg *crp, | |
202 | unsigned long field, unsigned long value) | |
0fc64cc0 | 203 | { |
18925e11 | 204 | void __iomem *mapped_reg; |
e499ada8 | 205 | unsigned long mask, pos, data; |
0fc64cc0 | 206 | |
4aeacd5b | 207 | sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); |
2967dab1 | 208 | |
18925e11 | 209 | pr_debug("write_reg addr = %lx, value = %ld, field = %ld, " |
fd2cb0ce | 210 | "r_width = %ld, f_width = %ld\n", |
18925e11 | 211 | crp->reg, value, field, crp->reg_width, crp->field_width); |
0fc64cc0 MD |
212 | |
213 | mask = ~(mask << pos); | |
214 | value = value << pos; | |
2967dab1 | 215 | |
4aeacd5b | 216 | data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width); |
e499ada8 MD |
217 | data &= mask; |
218 | data |= value; | |
219 | ||
19bb7fe3 | 220 | if (pfc->info->unlock_reg) |
4aeacd5b | 221 | sh_pfc_write_raw_reg( |
19bb7fe3 | 222 | sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32, |
4aeacd5b | 223 | ~data); |
e499ada8 | 224 | |
4aeacd5b | 225 | sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data); |
2967dab1 MD |
226 | } |
227 | ||
0b73ee5d | 228 | static void sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio) |
2967dab1 | 229 | { |
a3db40a6 | 230 | struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio]; |
2967dab1 MD |
231 | struct pinmux_data_reg *data_reg; |
232 | int k, n; | |
233 | ||
2967dab1 MD |
234 | k = 0; |
235 | while (1) { | |
19bb7fe3 | 236 | data_reg = pfc->info->data_regs + k; |
2967dab1 MD |
237 | |
238 | if (!data_reg->reg_width) | |
239 | break; | |
240 | ||
4aeacd5b | 241 | data_reg->mapped_reg = sh_pfc_phys_to_virt(pfc, data_reg->reg); |
b0e10211 | 242 | |
2967dab1 | 243 | for (n = 0; n < data_reg->reg_width; n++) { |
18801be7 MD |
244 | if (data_reg->enum_ids[n] == gpiop->enum_id) { |
245 | gpiop->flags &= ~PINMUX_FLAG_DREG; | |
246 | gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT); | |
247 | gpiop->flags &= ~PINMUX_FLAG_DBIT; | |
248 | gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT); | |
0b73ee5d | 249 | return; |
2967dab1 MD |
250 | } |
251 | } | |
252 | k++; | |
253 | } | |
254 | ||
18801be7 | 255 | BUG(); |
2967dab1 MD |
256 | } |
257 | ||
4aeacd5b | 258 | static void sh_pfc_setup_data_regs(struct sh_pfc *pfc) |
3292094e MD |
259 | { |
260 | struct pinmux_data_reg *drp; | |
261 | int k; | |
262 | ||
0b73ee5d LP |
263 | for (k = 0; k < pfc->info->nr_pins; k++) { |
264 | if (pfc->info->pins[k].enum_id == 0) | |
265 | continue; | |
266 | ||
4aeacd5b | 267 | sh_pfc_setup_data_reg(pfc, k); |
0b73ee5d | 268 | } |
3292094e MD |
269 | |
270 | k = 0; | |
271 | while (1) { | |
19bb7fe3 | 272 | drp = pfc->info->data_regs + k; |
3292094e MD |
273 | |
274 | if (!drp->reg_width) | |
275 | break; | |
276 | ||
4aeacd5b LP |
277 | drp->reg_shadow = sh_pfc_read_raw_reg(drp->mapped_reg, |
278 | drp->reg_width); | |
3292094e MD |
279 | k++; |
280 | } | |
281 | } | |
282 | ||
0b73ee5d LP |
283 | void sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio, |
284 | struct pinmux_data_reg **drp, int *bitp) | |
18801be7 | 285 | { |
934cb02b | 286 | struct sh_pfc_pin *gpiop = sh_pfc_get_pin(pfc, gpio); |
18801be7 MD |
287 | int k, n; |
288 | ||
18801be7 MD |
289 | k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT; |
290 | n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT; | |
19bb7fe3 | 291 | *drp = pfc->info->data_regs + k; |
18801be7 | 292 | *bitp = n; |
18801be7 MD |
293 | } |
294 | ||
4aeacd5b LP |
295 | static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id, |
296 | struct pinmux_cfg_reg **crp, int *fieldp, | |
297 | int *valuep, unsigned long **cntp) | |
2967dab1 MD |
298 | { |
299 | struct pinmux_cfg_reg *config_reg; | |
f78a26f5 MD |
300 | unsigned long r_width, f_width, curr_width, ncomb; |
301 | int k, m, n, pos, bit_pos; | |
2967dab1 MD |
302 | |
303 | k = 0; | |
304 | while (1) { | |
19bb7fe3 | 305 | config_reg = pfc->info->cfg_regs + k; |
2967dab1 MD |
306 | |
307 | r_width = config_reg->reg_width; | |
308 | f_width = config_reg->field_width; | |
309 | ||
310 | if (!r_width) | |
311 | break; | |
f78a26f5 MD |
312 | |
313 | pos = 0; | |
314 | m = 0; | |
315 | for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) { | |
316 | if (f_width) | |
317 | curr_width = f_width; | |
318 | else | |
319 | curr_width = config_reg->var_field_width[m]; | |
320 | ||
321 | ncomb = 1 << curr_width; | |
322 | for (n = 0; n < ncomb; n++) { | |
323 | if (config_reg->enum_ids[pos + n] == enum_id) { | |
324 | *crp = config_reg; | |
325 | *fieldp = m; | |
326 | *valuep = n; | |
327 | *cntp = &config_reg->cnt[m]; | |
328 | return 0; | |
329 | } | |
2967dab1 | 330 | } |
f78a26f5 MD |
331 | pos += ncomb; |
332 | m++; | |
2967dab1 MD |
333 | } |
334 | k++; | |
335 | } | |
336 | ||
337 | return -1; | |
338 | } | |
339 | ||
a68fdca9 LP |
340 | static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos, |
341 | pinmux_enum_t *enum_idp) | |
2967dab1 | 342 | { |
19bb7fe3 | 343 | pinmux_enum_t *data = pfc->info->gpio_data; |
2967dab1 MD |
344 | int k; |
345 | ||
2967dab1 MD |
346 | if (pos) { |
347 | *enum_idp = data[pos + 1]; | |
348 | return pos + 1; | |
349 | } | |
350 | ||
19bb7fe3 | 351 | for (k = 0; k < pfc->info->gpio_data_size; k++) { |
a68fdca9 | 352 | if (data[k] == mark) { |
2967dab1 MD |
353 | *enum_idp = data[k + 1]; |
354 | return k + 1; | |
355 | } | |
356 | } | |
357 | ||
a68fdca9 | 358 | pr_err("cannot locate data/mark enum_id for mark %d\n", mark); |
2967dab1 MD |
359 | return -1; |
360 | } | |
361 | ||
a68fdca9 LP |
362 | int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type, |
363 | int cfg_mode) | |
2967dab1 MD |
364 | { |
365 | struct pinmux_cfg_reg *cr = NULL; | |
366 | pinmux_enum_t enum_id; | |
367 | struct pinmux_range *range; | |
ad4a07ff | 368 | int in_range, pos, field, value; |
2967dab1 MD |
369 | unsigned long *cntp; |
370 | ||
371 | switch (pinmux_type) { | |
372 | ||
373 | case PINMUX_TYPE_FUNCTION: | |
374 | range = NULL; | |
375 | break; | |
376 | ||
377 | case PINMUX_TYPE_OUTPUT: | |
19bb7fe3 | 378 | range = &pfc->info->output; |
2967dab1 MD |
379 | break; |
380 | ||
381 | case PINMUX_TYPE_INPUT: | |
19bb7fe3 | 382 | range = &pfc->info->input; |
2967dab1 MD |
383 | break; |
384 | ||
385 | case PINMUX_TYPE_INPUT_PULLUP: | |
19bb7fe3 | 386 | range = &pfc->info->input_pu; |
2967dab1 MD |
387 | break; |
388 | ||
389 | case PINMUX_TYPE_INPUT_PULLDOWN: | |
19bb7fe3 | 390 | range = &pfc->info->input_pd; |
2967dab1 MD |
391 | break; |
392 | ||
393 | default: | |
394 | goto out_err; | |
395 | } | |
396 | ||
397 | pos = 0; | |
398 | enum_id = 0; | |
ad4a07ff MD |
399 | field = 0; |
400 | value = 0; | |
2967dab1 | 401 | while (1) { |
a68fdca9 | 402 | pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id); |
2967dab1 MD |
403 | if (pos <= 0) |
404 | goto out_err; | |
405 | ||
406 | if (!enum_id) | |
407 | break; | |
408 | ||
50dd3145 | 409 | /* first check if this is a function enum */ |
19bb7fe3 | 410 | in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function); |
50dd3145 MD |
411 | if (!in_range) { |
412 | /* not a function enum */ | |
413 | if (range) { | |
414 | /* | |
415 | * other range exists, so this pin is | |
416 | * a regular GPIO pin that now is being | |
417 | * bound to a specific direction. | |
418 | * | |
419 | * for this case we only allow function enums | |
420 | * and the enums that match the other range. | |
421 | */ | |
4aeacd5b | 422 | in_range = sh_pfc_enum_in_range(enum_id, range); |
50dd3145 MD |
423 | |
424 | /* | |
425 | * special case pass through for fixed | |
426 | * input-only or output-only pins without | |
427 | * function enum register association. | |
428 | */ | |
429 | if (in_range && enum_id == range->force) | |
430 | continue; | |
431 | } else { | |
432 | /* | |
433 | * no other range exists, so this pin | |
434 | * must then be of the function type. | |
435 | * | |
436 | * allow function type pins to select | |
437 | * any combination of function/in/out | |
438 | * in their MARK lists. | |
439 | */ | |
440 | in_range = 1; | |
441 | } | |
42eed42b MD |
442 | } |
443 | ||
2967dab1 MD |
444 | if (!in_range) |
445 | continue; | |
446 | ||
4aeacd5b LP |
447 | if (sh_pfc_get_config_reg(pfc, enum_id, &cr, |
448 | &field, &value, &cntp) != 0) | |
2967dab1 MD |
449 | goto out_err; |
450 | ||
451 | switch (cfg_mode) { | |
452 | case GPIO_CFG_DRYRUN: | |
18925e11 | 453 | if (!*cntp || |
4aeacd5b | 454 | (sh_pfc_read_config_reg(pfc, cr, field) != value)) |
2967dab1 MD |
455 | continue; |
456 | break; | |
457 | ||
458 | case GPIO_CFG_REQ: | |
4aeacd5b | 459 | sh_pfc_write_config_reg(pfc, cr, field, value); |
2967dab1 MD |
460 | *cntp = *cntp + 1; |
461 | break; | |
462 | ||
463 | case GPIO_CFG_FREE: | |
464 | *cntp = *cntp - 1; | |
465 | break; | |
466 | } | |
467 | } | |
468 | ||
469 | return 0; | |
470 | out_err: | |
471 | return -1; | |
472 | } | |
473 | ||
c6193eac | 474 | static int sh_pfc_probe(struct platform_device *pdev) |
2967dab1 | 475 | { |
19bb7fe3 | 476 | struct sh_pfc_soc_info *info; |
c6193eac | 477 | struct sh_pfc *pfc; |
0fc64cc0 | 478 | int ret; |
2967dab1 | 479 | |
06d5631f PM |
480 | /* |
481 | * Ensure that the type encoding fits | |
482 | */ | |
483 | BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1)); | |
484 | ||
19bb7fe3 LP |
485 | info = pdev->id_entry->driver_data |
486 | ? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data; | |
487 | if (info == NULL) | |
c6193eac | 488 | return -ENODEV; |
2967dab1 | 489 | |
8c43fcc7 | 490 | pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL); |
c6193eac LP |
491 | if (pfc == NULL) |
492 | return -ENOMEM; | |
d4e62d00 | 493 | |
19bb7fe3 | 494 | pfc->info = info; |
c6193eac LP |
495 | pfc->dev = &pdev->dev; |
496 | ||
973931ae | 497 | ret = sh_pfc_ioremap(pfc, pdev); |
c6193eac | 498 | if (unlikely(ret < 0)) |
b0e10211 MD |
499 | return ret; |
500 | ||
c6193eac | 501 | spin_lock_init(&pfc->lock); |
69edbba0 | 502 | |
ca5481c6 | 503 | pinctrl_provide_dummies(); |
4aeacd5b | 504 | sh_pfc_setup_data_regs(pfc); |
b0e10211 | 505 | |
ca5481c6 PM |
506 | /* |
507 | * Initialize pinctrl bindings first | |
508 | */ | |
c6193eac | 509 | ret = sh_pfc_register_pinctrl(pfc); |
f9492fda | 510 | if (unlikely(ret != 0)) |
c9fa88e2 | 511 | return ret; |
ca5481c6 | 512 | |
6f6a4a68 | 513 | #ifdef CONFIG_GPIO_SH_PFC |
ca5481c6 PM |
514 | /* |
515 | * Then the GPIO chip | |
516 | */ | |
c6193eac | 517 | ret = sh_pfc_register_gpiochip(pfc); |
6f6a4a68 | 518 | if (unlikely(ret != 0)) { |
ca5481c6 PM |
519 | /* |
520 | * If the GPIO chip fails to come up we still leave the | |
521 | * PFC state as it is, given that there are already | |
522 | * extant users of it that have succeeded by this point. | |
523 | */ | |
6f6a4a68 | 524 | pr_notice("failed to init GPIO chip, ignoring...\n"); |
b3c185a7 | 525 | } |
6f6a4a68 | 526 | #endif |
b72421d8 | 527 | |
c6193eac LP |
528 | platform_set_drvdata(pdev, pfc); |
529 | ||
19bb7fe3 | 530 | pr_info("%s support registered\n", info->name); |
ca5481c6 | 531 | |
b3c185a7 | 532 | return 0; |
b72421d8 | 533 | } |
6f6a4a68 | 534 | |
c6193eac LP |
535 | static int sh_pfc_remove(struct platform_device *pdev) |
536 | { | |
537 | struct sh_pfc *pfc = platform_get_drvdata(pdev); | |
538 | ||
539 | #ifdef CONFIG_GPIO_SH_PFC | |
540 | sh_pfc_unregister_gpiochip(pfc); | |
541 | #endif | |
542 | sh_pfc_unregister_pinctrl(pfc); | |
543 | ||
c6193eac LP |
544 | platform_set_drvdata(pdev, NULL); |
545 | ||
546 | return 0; | |
547 | } | |
548 | ||
549 | static const struct platform_device_id sh_pfc_id_table[] = { | |
d5b1521a LP |
550 | #ifdef CONFIG_PINCTRL_PFC_R8A7740 |
551 | { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info }, | |
881023d2 LP |
552 | #endif |
553 | #ifdef CONFIG_PINCTRL_PFC_R8A7779 | |
554 | { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info }, | |
6e5469a6 | 555 | #endif |
ccda552e LP |
556 | #ifdef CONFIG_PINCTRL_PFC_SH7203 |
557 | { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info }, | |
558 | #endif | |
a8d42fc4 LP |
559 | #ifdef CONFIG_PINCTRL_PFC_SH7264 |
560 | { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info }, | |
561 | #endif | |
f5e811f2 LP |
562 | #ifdef CONFIG_PINCTRL_PFC_SH7269 |
563 | { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info }, | |
564 | #endif | |
6e5469a6 LP |
565 | #ifdef CONFIG_PINCTRL_PFC_SH7372 |
566 | { "pfc-sh7372", (kernel_ulong_t)&sh7372_pinmux_info }, | |
5d5166dc LP |
567 | #endif |
568 | #ifdef CONFIG_PINCTRL_PFC_SH73A0 | |
569 | { "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info }, | |
74cad605 LP |
570 | #endif |
571 | #ifdef CONFIG_PINCTRL_PFC_SH7720 | |
572 | { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info }, | |
f5e25ae5 LP |
573 | #endif |
574 | #ifdef CONFIG_PINCTRL_PFC_SH7722 | |
575 | { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info }, | |
d05afa0a LP |
576 | #endif |
577 | #ifdef CONFIG_PINCTRL_PFC_SH7723 | |
578 | { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info }, | |
0ff25bab LP |
579 | #endif |
580 | #ifdef CONFIG_PINCTRL_PFC_SH7724 | |
581 | { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info }, | |
ac1ebc21 LP |
582 | #endif |
583 | #ifdef CONFIG_PINCTRL_PFC_SH7734 | |
584 | { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info }, | |
0bb92677 LP |
585 | #endif |
586 | #ifdef CONFIG_PINCTRL_PFC_SH7757 | |
587 | { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info }, | |
a56398e9 LP |
588 | #endif |
589 | #ifdef CONFIG_PINCTRL_PFC_SH7785 | |
590 | { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info }, | |
d2a31bdd LP |
591 | #endif |
592 | #ifdef CONFIG_PINCTRL_PFC_SH7786 | |
593 | { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info }, | |
d5d9a818 LP |
594 | #endif |
595 | #ifdef CONFIG_PINCTRL_PFC_SHX3 | |
596 | { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info }, | |
d5b1521a | 597 | #endif |
c6193eac LP |
598 | { "sh-pfc", 0 }, |
599 | { }, | |
600 | }; | |
601 | MODULE_DEVICE_TABLE(platform, sh_pfc_id_table); | |
602 | ||
603 | static struct platform_driver sh_pfc_driver = { | |
604 | .probe = sh_pfc_probe, | |
605 | .remove = sh_pfc_remove, | |
606 | .id_table = sh_pfc_id_table, | |
607 | .driver = { | |
608 | .name = DRV_NAME, | |
609 | .owner = THIS_MODULE, | |
610 | }, | |
611 | }; | |
612 | ||
40ee6fce LP |
613 | static int __init sh_pfc_init(void) |
614 | { | |
615 | return platform_driver_register(&sh_pfc_driver); | |
c6193eac | 616 | } |
40ee6fce | 617 | postcore_initcall(sh_pfc_init); |
c6193eac LP |
618 | |
619 | static void __exit sh_pfc_exit(void) | |
620 | { | |
621 | platform_driver_unregister(&sh_pfc_driver); | |
622 | } | |
623 | module_exit(sh_pfc_exit); | |
624 | ||
6f6a4a68 LP |
625 | MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart"); |
626 | MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller"); | |
627 | MODULE_LICENSE("GPL v2"); |