[deliverable/linux.git] / drivers / pinctrl / sh-pfc / core.c

/*
 * SuperH Pin Function Controller support.
 *
 * Copyright (C) 2008 Magnus Damm
 * Copyright (C) 2009 - 2012 Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#define DRV_NAME "sh-pfc"
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/bitops.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pinctrl/machine.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include "core.h"

static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev)
{
	struct resource *res;
	int k;

	if (pdev->num_resources == 0)
		return -EINVAL;

	pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources *
				   sizeof(*pfc->window), GFP_NOWAIT);
	if (!pfc->window)
		return -ENOMEM;

	pfc->num_windows = pdev->num_resources;

	for (k = 0, res = pdev->resource; k < pdev->num_resources; k++, res++) {
		WARN_ON(resource_type(res) != IORESOURCE_MEM);
		pfc->window[k].phys = res->start;
		pfc->window[k].size = resource_size(res);
		pfc->window[k].virt = devm_ioremap_nocache(pfc->dev, res->start,
							   resource_size(res));
		if (!pfc->window[k].virt)
			return -ENOMEM;
	}

	return 0;
}

static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
					 unsigned long address)
{
	struct sh_pfc_window *window;
	unsigned int i;

	/* scan through physical windows and convert address */
	for (i = 0; i < pfc->num_windows; i++) {
		window = pfc->window + i;

		if (address < window->phys)
			continue;

		if (address >= (window->phys + window->size))
			continue;

		return window->virt + (address - window->phys);
	}

	BUG();
}

int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
{
	unsigned int offset;
	unsigned int i;

	if (pfc->info->ranges == NULL)
		return pin;

	for (i = 0, offset = 0; i < pfc->info->nr_ranges; ++i) {
		const struct pinmux_range *range = &pfc->info->ranges[i];

		if (pin <= range->end)
			return pin >= range->begin
			     ? offset + pin - range->begin : -1;

		offset += range->end - range->begin + 1;
	}

	return -1;
}

static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
{
	if (enum_id < r->begin)
		return 0;

	if (enum_id > r->end)
		return 0;

	return 1;
}

unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
				  unsigned long reg_width)
{
	switch (reg_width) {
	case 8:
		return ioread8(mapped_reg);
	case 16:
		return ioread16(mapped_reg);
	case 32:
		return ioread32(mapped_reg);
	}

	BUG();
	return 0;
}

void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
			  unsigned long data)
{
	switch (reg_width) {
	case 8:
		iowrite8(data, mapped_reg);
		return;
	case 16:
		iowrite16(data, mapped_reg);
		return;
	case 32:
		iowrite32(data, mapped_reg);
		return;
	}

	BUG();
}

static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
				     struct pinmux_cfg_reg *crp,
				     unsigned long in_pos,
				     void __iomem **mapped_regp,
				     unsigned long *maskp,
				     unsigned long *posp)
{
	int k;

	*mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);

	if (crp->field_width) {
		*maskp = (1 << crp->field_width) - 1;
		*posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
	} else {
		*maskp = (1 << crp->var_field_width[in_pos]) - 1;
		*posp = crp->reg_width;
		for (k = 0; k <= in_pos; k++)
			*posp -= crp->var_field_width[k];
	}
}

static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
				    struct pinmux_cfg_reg *crp,
				    unsigned long field, unsigned long value)
{
	void __iomem *mapped_reg;
	unsigned long mask, pos, data;

	sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);

	pr_debug("write_reg addr = %lx, value = %ld, field = %ld, "
		 "r_width = %ld, f_width = %ld\n",
		 crp->reg, value, field, crp->reg_width, crp->field_width);

	mask = ~(mask << pos);
	value = value << pos;

	data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
	data &= mask;
	data |= value;

	if (pfc->info->unlock_reg)
		sh_pfc_write_raw_reg(
			sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
			~data);

	sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
}

static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
				 struct pinmux_cfg_reg **crp, int *fieldp,
				 int *valuep)
{
	struct pinmux_cfg_reg *config_reg;
	unsigned long r_width, f_width, curr_width, ncomb;
	int k, m, n, pos, bit_pos;

	k = 0;
	while (1) {
		config_reg = pfc->info->cfg_regs + k;

		r_width = config_reg->reg_width;
		f_width = config_reg->field_width;

		if (!r_width)
			break;

		pos = 0;
		m = 0;
		for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
			if (f_width)
				curr_width = f_width;
			else
				curr_width = config_reg->var_field_width[m];

			ncomb = 1 << curr_width;
			for (n = 0; n < ncomb; n++) {
				if (config_reg->enum_ids[pos + n] == enum_id) {
					*crp = config_reg;
					*fieldp = m;
					*valuep = n;
					return 0;
				}
			}
			pos += ncomb;
			m++;
		}
		k++;
	}

	return -1;
}

static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos,
			      pinmux_enum_t *enum_idp)
{
	pinmux_enum_t *data = pfc->info->gpio_data;
	int k;

	if (pos) {
		*enum_idp = data[pos + 1];
		return pos + 1;
	}

	for (k = 0; k < pfc->info->gpio_data_size; k++) {
		if (data[k] == mark) {
			*enum_idp = data[k + 1];
			return k + 1;
		}
	}

	pr_err("cannot locate data/mark enum_id for mark %d\n", mark);
	return -1;
}

int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
{
	struct pinmux_cfg_reg *cr = NULL;
	pinmux_enum_t enum_id;
	struct pinmux_range *range;
	int in_range, pos, field, value;

	switch (pinmux_type) {

	case PINMUX_TYPE_FUNCTION:
		range = NULL;
		break;

	case PINMUX_TYPE_OUTPUT:
		range = &pfc->info->output;
		break;

	case PINMUX_TYPE_INPUT:
		range = &pfc->info->input;
		break;

	case PINMUX_TYPE_INPUT_PULLUP:
		range = &pfc->info->input_pu;
		break;

	case PINMUX_TYPE_INPUT_PULLDOWN:
		range = &pfc->info->input_pd;
		break;

	default:
		return -1;
	}

	pos = 0;
	enum_id = 0;
	field = 0;
	value = 0;
	while (1) {
		pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
		if (pos <= 0)
			return -1;

		if (!enum_id)
			break;

		/* first check if this is a function enum */
		in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
		if (!in_range) {
			/* not a function enum */
			if (range) {
				/*
				 * other range exists, so this pin is
				 * a regular GPIO pin that now is being
				 * bound to a specific direction.
				 *
				 * for this case we only allow function enums
				 * and the enums that match the other range.
				 */
				in_range = sh_pfc_enum_in_range(enum_id, range);

				/*
				 * special case pass through for fixed
				 * input-only or output-only pins without
				 * function enum register association.
				 */
				if (in_range && enum_id == range->force)
					continue;
			} else {
				/*
				 * no other range exists, so this pin
				 * must then be of the function type.
				 *
				 * allow function type pins to select
				 * any combination of function/in/out
				 * in their MARK lists.
				 */
				in_range = 1;
			}
		}

		if (!in_range)
			continue;

		if (sh_pfc_get_config_reg(pfc, enum_id, &cr,
					  &field, &value) != 0)
			return -1;

		sh_pfc_write_config_reg(pfc, cr, field, value);
	}

	return 0;
}

static int sh_pfc_probe(struct platform_device *pdev)
{
	struct sh_pfc_soc_info *info;
	struct sh_pfc *pfc;
	int ret;

	info = pdev->id_entry->driver_data
	      ? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data;
	if (info == NULL)
		return -ENODEV;

	pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
	if (pfc == NULL)
		return -ENOMEM;

	pfc->info = info;
	pfc->dev = &pdev->dev;

	ret = sh_pfc_ioremap(pfc, pdev);
	if (unlikely(ret < 0))
		return ret;

	spin_lock_init(&pfc->lock);

	pinctrl_provide_dummies();

	/*
	 * Initialize pinctrl bindings first
	 */
	ret = sh_pfc_register_pinctrl(pfc);
	if (unlikely(ret != 0))
		return ret;

#ifdef CONFIG_GPIO_SH_PFC
	/*
	 * Then the GPIO chip
	 */
	ret = sh_pfc_register_gpiochip(pfc);
	if (unlikely(ret != 0)) {
		/*
		 * If the GPIO chip fails to come up we still leave the
		 * PFC state as it is, given that there are already
		 * extant users of it that have succeeded by this point.
		 */
		pr_notice("failed to init GPIO chip, ignoring...\n");
	}
#endif

	platform_set_drvdata(pdev, pfc);

	pr_info("%s support registered\n", info->name);

	return 0;
}

static int sh_pfc_remove(struct platform_device *pdev)
{
	struct sh_pfc *pfc = platform_get_drvdata(pdev);

#ifdef CONFIG_GPIO_SH_PFC
	sh_pfc_unregister_gpiochip(pfc);
#endif
	sh_pfc_unregister_pinctrl(pfc);

	platform_set_drvdata(pdev, NULL);

	return 0;
}

static const struct platform_device_id sh_pfc_id_table[] = {
#ifdef CONFIG_PINCTRL_PFC_R8A7740
	{ "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7779
	{ "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7203
	{ "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7264
	{ "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7269
	{ "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7372
	{ "pfc-sh7372", (kernel_ulong_t)&sh7372_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH73A0
	{ "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7720
	{ "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7722
	{ "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7723
	{ "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7724
	{ "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7734
	{ "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7757
	{ "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7785
	{ "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SH7786
	{ "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_SHX3
	{ "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
#endif
	{ "sh-pfc", 0 },
	{ },
};
MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);

static struct platform_driver sh_pfc_driver = {
	.probe		= sh_pfc_probe,
	.remove		= sh_pfc_remove,
	.id_table	= sh_pfc_id_table,
	.driver		= {
		.name	= DRV_NAME,
		.owner	= THIS_MODULE,
	},
};

static int __init sh_pfc_init(void)
{
	return platform_driver_register(&sh_pfc_driver);
}
postcore_initcall(sh_pfc_init);

static void __exit sh_pfc_exit(void)
{
	platform_driver_unregister(&sh_pfc_driver);
}
module_exit(sh_pfc_exit);

MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
2967dab1	1	/*
b3c185a7	2	* SuperH Pin Function Controller support.
2967dab1 MD	3	*
2967dab1 MD	4	* Copyright (C) 2008 Magnus Damm
b3c185a7	5	* Copyright (C) 2009 - 2012 Paul Mundt
2967dab1 MD	6	*
	7	* This file is subject to the terms and conditions of the GNU General Public
	8	* License. See the file "COPYING" in the main directory of this archive
	9	* for more details.
	10	*/
c6193eac LP	11
c6193eac LP	12	#define DRV_NAME "sh-pfc"
f9492fda	13	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
b72421d8	14
90efde22	15	#include <linux/bitops.h>
2967dab1	16	#include <linux/err.h>
90efde22	17	#include <linux/errno.h>
2967dab1	18	#include <linux/io.h>
b0e10211	19	#include <linux/ioport.h>
90efde22 LP	20	#include <linux/kernel.h>
90efde22 LP	21	#include <linux/module.h>
ca5481c6	22	#include <linux/pinctrl/machine.h>
c6193eac	23	#include <linux/platform_device.h>
90efde22	24	#include <linux/slab.h>
b0e10211	25
f9165132 LP	26	#include "core.h"
f9165132 LP	27
973931ae	28	static int sh_pfc_ioremap(struct sh_pfc pfc, struct platform_device pdev)
b0e10211 MD	29	{
	30	struct resource *res;
	31	int k;
	32
bee9f22b LP	33	if (pdev->num_resources == 0)
bee9f22b LP	34	return -EINVAL;
b0e10211	35
56dc04af	36	pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources *
1724acfd	37	sizeof(*pfc->window), GFP_NOWAIT);
b3c185a7	38	if (!pfc->window)
1724acfd	39	return -ENOMEM;
b0e10211	40
56dc04af	41	pfc->num_windows = pdev->num_resources;
973931ae	42
56dc04af	43	for (k = 0, res = pdev->resource; k < pdev->num_resources; k++, res++) {
b0e10211	44	WARN_ON(resource_type(res) != IORESOURCE_MEM);
b3c185a7 PM	45	pfc->window[k].phys = res->start;
b3c185a7 PM	46	pfc->window[k].size = resource_size(res);
c9fa88e2 LP	47	pfc->window[k].virt = devm_ioremap_nocache(pfc->dev, res->start,
	48	resource_size(res));
	49	if (!pfc->window[k].virt)
1724acfd	50	return -ENOMEM;
b0e10211 MD	51	}
	52
	53	return 0;
b0e10211 MD	54	}
b0e10211 MD	55
e51d5343 LP	56	static void __iomem sh_pfc_phys_to_virt(struct sh_pfc pfc,
e51d5343 LP	57	unsigned long address)
b0e10211	58	{
4aeacd5b	59	struct sh_pfc_window *window;
bee9f22b	60	unsigned int i;
b0e10211 MD	61
b0e10211 MD	62	/* scan through physical windows and convert address */
bee9f22b LP	63	for (i = 0; i < pfc->num_windows; i++) {
bee9f22b LP	64	window = pfc->window + i;
b0e10211 MD	65
	66	if (address < window->phys)
	67	continue;
	68
	69	if (address >= (window->phys + window->size))
	70	continue;
	71
	72	return window->virt + (address - window->phys);
	73	}
	74
bee9f22b	75	BUG();
b0e10211	76	}
2967dab1	77
1a0039dc	78	int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
934cb02b	79	{
63d57383 LP	80	unsigned int offset;
	81	unsigned int i;
	82
	83	if (pfc->info->ranges == NULL)
1a0039dc	84	return pin;
63d57383 LP	85
	86	for (i = 0, offset = 0; i < pfc->info->nr_ranges; ++i) {
	87	const struct pinmux_range *range = &pfc->info->ranges[i];
	88
	89	if (pin <= range->end)
	90	return pin >= range->begin
1a0039dc	91	? offset + pin - range->begin : -1;
63d57383 LP	92
	93	offset += range->end - range->begin + 1;
	94	}
	95
1a0039dc	96	return -1;
934cb02b LP	97	}
934cb02b LP	98
4aeacd5b	99	static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
2967dab1 MD	100	{
	101	if (enum_id < r->begin)
	102	return 0;
	103
	104	if (enum_id > r->end)
	105	return 0;
	106
	107	return 1;
	108	}
	109
41f1219f LP	110	unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
41f1219f LP	111	unsigned long reg_width)
3292094e MD	112	{
	113	switch (reg_width) {
	114	case 8:
b0e10211	115	return ioread8(mapped_reg);
3292094e	116	case 16:
b0e10211	117	return ioread16(mapped_reg);
3292094e	118	case 32:
b0e10211	119	return ioread32(mapped_reg);
3292094e MD	120	}
	121
	122	BUG();
	123	return 0;
	124	}
	125
41f1219f LP	126	void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
41f1219f LP	127	unsigned long data)
3292094e MD	128	{
	129	switch (reg_width) {
	130	case 8:
b0e10211	131	iowrite8(data, mapped_reg);
3292094e MD	132	return;
3292094e MD	133	case 16:
b0e10211	134	iowrite16(data, mapped_reg);
3292094e MD	135	return;
3292094e MD	136	case 32:
b0e10211	137	iowrite32(data, mapped_reg);
3292094e MD	138	return;
	139	}
	140
	141	BUG();
	142	}
	143
4aeacd5b LP	144	static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
	145	struct pinmux_cfg_reg *crp,
	146	unsigned long in_pos,
	147	void __iomem **mapped_regp,
	148	unsigned long *maskp,
	149	unsigned long *posp)
2967dab1	150	{
f78a26f5 MD	151	int k;
f78a26f5 MD	152
4aeacd5b	153	*mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
2967dab1	154
f78a26f5 MD	155	if (crp->field_width) {
	156	*maskp = (1 << crp->field_width) - 1;
	157	posp = crp->reg_width - ((in_pos + 1) crp->field_width);
	158	} else {
	159	*maskp = (1 << crp->var_field_width[in_pos]) - 1;
	160	*posp = crp->reg_width;
	161	for (k = 0; k <= in_pos; k++)
	162	*posp -= crp->var_field_width[k];
	163	}
18925e11 MD	164	}
18925e11 MD	165
4aeacd5b LP	166	static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
	167	struct pinmux_cfg_reg *crp,
	168	unsigned long field, unsigned long value)
0fc64cc0	169	{
18925e11	170	void __iomem *mapped_reg;
e499ada8	171	unsigned long mask, pos, data;
0fc64cc0	172
4aeacd5b	173	sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
2967dab1	174
18925e11	175	pr_debug("write_reg addr = %lx, value = %ld, field = %ld, "
fd2cb0ce	176	"r_width = %ld, f_width = %ld\n",
18925e11	177	crp->reg, value, field, crp->reg_width, crp->field_width);
0fc64cc0 MD	178
	179	mask = ~(mask << pos);
	180	value = value << pos;
2967dab1	181
4aeacd5b	182	data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
e499ada8 MD	183	data &= mask;
	184	data \|= value;
	185
19bb7fe3	186	if (pfc->info->unlock_reg)
4aeacd5b	187	sh_pfc_write_raw_reg(
19bb7fe3	188	sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
4aeacd5b	189	~data);
e499ada8	190
4aeacd5b	191	sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
2967dab1 MD	192	}
2967dab1 MD	193
4aeacd5b LP	194	static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
4aeacd5b LP	195	struct pinmux_cfg_reg *crp, int fieldp,
861601de	196	int *valuep)
2967dab1 MD	197	{
2967dab1 MD	198	struct pinmux_cfg_reg *config_reg;
f78a26f5 MD	199	unsigned long r_width, f_width, curr_width, ncomb;
f78a26f5 MD	200	int k, m, n, pos, bit_pos;
2967dab1 MD	201
	202	k = 0;
	203	while (1) {
19bb7fe3	204	config_reg = pfc->info->cfg_regs + k;
2967dab1 MD	205
	206	r_width = config_reg->reg_width;
	207	f_width = config_reg->field_width;
	208
	209	if (!r_width)
	210	break;
f78a26f5 MD	211
	212	pos = 0;
	213	m = 0;
	214	for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
	215	if (f_width)
	216	curr_width = f_width;
	217	else
	218	curr_width = config_reg->var_field_width[m];
	219
	220	ncomb = 1 << curr_width;
	221	for (n = 0; n < ncomb; n++) {
	222	if (config_reg->enum_ids[pos + n] == enum_id) {
	223	*crp = config_reg;
	224	*fieldp = m;
	225	*valuep = n;
f78a26f5 MD	226	return 0;
f78a26f5 MD	227	}
2967dab1	228	}
f78a26f5 MD	229	pos += ncomb;
f78a26f5 MD	230	m++;
2967dab1 MD	231	}
	232	k++;
	233	}
	234
	235	return -1;
	236	}
	237
a68fdca9 LP	238	static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos,
a68fdca9 LP	239	pinmux_enum_t *enum_idp)
2967dab1	240	{
19bb7fe3	241	pinmux_enum_t *data = pfc->info->gpio_data;
2967dab1 MD	242	int k;
2967dab1 MD	243
2967dab1 MD	244	if (pos) {
	245	*enum_idp = data[pos + 1];
	246	return pos + 1;
	247	}
	248
19bb7fe3	249	for (k = 0; k < pfc->info->gpio_data_size; k++) {
a68fdca9	250	if (data[k] == mark) {
2967dab1 MD	251	*enum_idp = data[k + 1];
	252	return k + 1;
	253	}
	254	}
	255
a68fdca9	256	pr_err("cannot locate data/mark enum_id for mark %d\n", mark);
2967dab1 MD	257	return -1;
	258	}
	259
861601de	260	int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
2967dab1 MD	261	{
	262	struct pinmux_cfg_reg *cr = NULL;
	263	pinmux_enum_t enum_id;
	264	struct pinmux_range *range;
ad4a07ff	265	int in_range, pos, field, value;
2967dab1 MD	266
	267	switch (pinmux_type) {
	268
	269	case PINMUX_TYPE_FUNCTION:
	270	range = NULL;
	271	break;
	272
	273	case PINMUX_TYPE_OUTPUT:
19bb7fe3	274	range = &pfc->info->output;
2967dab1 MD	275	break;
	276
	277	case PINMUX_TYPE_INPUT:
19bb7fe3	278	range = &pfc->info->input;
2967dab1 MD	279	break;
	280
	281	case PINMUX_TYPE_INPUT_PULLUP:
19bb7fe3	282	range = &pfc->info->input_pu;
2967dab1 MD	283	break;
	284
	285	case PINMUX_TYPE_INPUT_PULLDOWN:
19bb7fe3	286	range = &pfc->info->input_pd;
2967dab1 MD	287	break;
	288
	289	default:
861601de	290	return -1;
2967dab1 MD	291	}
	292
	293	pos = 0;
	294	enum_id = 0;
ad4a07ff MD	295	field = 0;
ad4a07ff MD	296	value = 0;
2967dab1	297	while (1) {
a68fdca9	298	pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
2967dab1	299	if (pos <= 0)
861601de	300	return -1;
2967dab1 MD	301
	302	if (!enum_id)
	303	break;
	304
50dd3145	305	/* first check if this is a function enum */
19bb7fe3	306	in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
50dd3145 MD	307	if (!in_range) {
	308	/* not a function enum */
	309	if (range) {
	310	/*
	311	* other range exists, so this pin is
	312	* a regular GPIO pin that now is being
	313	* bound to a specific direction.
	314	*
	315	* for this case we only allow function enums
	316	* and the enums that match the other range.
	317	*/
4aeacd5b	318	in_range = sh_pfc_enum_in_range(enum_id, range);
50dd3145 MD	319
	320	/*
	321	* special case pass through for fixed
	322	* input-only or output-only pins without
	323	* function enum register association.
	324	*/
	325	if (in_range && enum_id == range->force)
	326	continue;
	327	} else {
	328	/*
	329	* no other range exists, so this pin
	330	* must then be of the function type.
	331	*
	332	* allow function type pins to select
	333	* any combination of function/in/out
	334	* in their MARK lists.
	335	*/
	336	in_range = 1;
	337	}
42eed42b MD	338	}
42eed42b MD	339
2967dab1 MD	340	if (!in_range)
	341	continue;
	342
4aeacd5b	343	if (sh_pfc_get_config_reg(pfc, enum_id, &cr,
861601de LP	344	&field, &value) != 0)
861601de LP	345	return -1;
2967dab1	346
861601de	347	sh_pfc_write_config_reg(pfc, cr, field, value);
2967dab1 MD	348	}
	349
	350	return 0;
2967dab1 MD	351	}
2967dab1 MD	352
c6193eac	353	static int sh_pfc_probe(struct platform_device *pdev)
2967dab1	354	{
19bb7fe3	355	struct sh_pfc_soc_info *info;
c6193eac	356	struct sh_pfc *pfc;
0fc64cc0	357	int ret;
2967dab1	358
19bb7fe3 LP	359	info = pdev->id_entry->driver_data
	360	? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data;
	361	if (info == NULL)
c6193eac	362	return -ENODEV;
2967dab1	363
8c43fcc7	364	pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
c6193eac LP	365	if (pfc == NULL)
c6193eac LP	366	return -ENOMEM;
d4e62d00	367
19bb7fe3	368	pfc->info = info;
c6193eac LP	369	pfc->dev = &pdev->dev;
c6193eac LP	370
973931ae	371	ret = sh_pfc_ioremap(pfc, pdev);
c6193eac	372	if (unlikely(ret < 0))
b0e10211 MD	373	return ret;
b0e10211 MD	374
c6193eac	375	spin_lock_init(&pfc->lock);
69edbba0	376
ca5481c6	377	pinctrl_provide_dummies();
b0e10211	378
ca5481c6 PM	379	/*
	380	* Initialize pinctrl bindings first
	381	*/
c6193eac	382	ret = sh_pfc_register_pinctrl(pfc);
f9492fda	383	if (unlikely(ret != 0))
c9fa88e2	384	return ret;
ca5481c6	385
6f6a4a68	386	#ifdef CONFIG_GPIO_SH_PFC
ca5481c6 PM	387	/*
	388	* Then the GPIO chip
	389	*/
c6193eac	390	ret = sh_pfc_register_gpiochip(pfc);
6f6a4a68	391	if (unlikely(ret != 0)) {
ca5481c6 PM	392	/*
	393	* If the GPIO chip fails to come up we still leave the
	394	* PFC state as it is, given that there are already
	395	* extant users of it that have succeeded by this point.
	396	*/
6f6a4a68	397	pr_notice("failed to init GPIO chip, ignoring...\n");
b3c185a7	398	}
6f6a4a68	399	#endif
b72421d8	400
c6193eac LP	401	platform_set_drvdata(pdev, pfc);
c6193eac LP	402
19bb7fe3	403	pr_info("%s support registered\n", info->name);
ca5481c6	404
b3c185a7	405	return 0;
b72421d8	406	}
6f6a4a68	407
c6193eac LP	408	static int sh_pfc_remove(struct platform_device *pdev)
	409	{
	410	struct sh_pfc *pfc = platform_get_drvdata(pdev);
	411
	412	#ifdef CONFIG_GPIO_SH_PFC
	413	sh_pfc_unregister_gpiochip(pfc);
	414	#endif
	415	sh_pfc_unregister_pinctrl(pfc);
	416
c6193eac LP	417	platform_set_drvdata(pdev, NULL);
	418
	419	return 0;
	420	}
	421
	422	static const struct platform_device_id sh_pfc_id_table[] = {
d5b1521a LP	423	#ifdef CONFIG_PINCTRL_PFC_R8A7740
d5b1521a LP	424	{ "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
881023d2 LP	425	#endif
	426	#ifdef CONFIG_PINCTRL_PFC_R8A7779
	427	{ "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
6e5469a6	428	#endif
ccda552e LP	429	#ifdef CONFIG_PINCTRL_PFC_SH7203
	430	{ "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
	431	#endif
a8d42fc4 LP	432	#ifdef CONFIG_PINCTRL_PFC_SH7264
	433	{ "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
	434	#endif
f5e811f2 LP	435	#ifdef CONFIG_PINCTRL_PFC_SH7269
	436	{ "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
	437	#endif
6e5469a6 LP	438	#ifdef CONFIG_PINCTRL_PFC_SH7372
6e5469a6 LP	439	{ "pfc-sh7372", (kernel_ulong_t)&sh7372_pinmux_info },
5d5166dc LP	440	#endif
	441	#ifdef CONFIG_PINCTRL_PFC_SH73A0
	442	{ "pfc-sh73a0", (kernel_ulong_t)&sh73a0_pinmux_info },
74cad605 LP	443	#endif
	444	#ifdef CONFIG_PINCTRL_PFC_SH7720
	445	{ "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
f5e25ae5 LP	446	#endif
	447	#ifdef CONFIG_PINCTRL_PFC_SH7722
	448	{ "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
d05afa0a LP	449	#endif
	450	#ifdef CONFIG_PINCTRL_PFC_SH7723
	451	{ "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
0ff25bab LP	452	#endif
	453	#ifdef CONFIG_PINCTRL_PFC_SH7724
	454	{ "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
ac1ebc21 LP	455	#endif
	456	#ifdef CONFIG_PINCTRL_PFC_SH7734
	457	{ "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
0bb92677 LP	458	#endif
	459	#ifdef CONFIG_PINCTRL_PFC_SH7757
	460	{ "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
a56398e9 LP	461	#endif
	462	#ifdef CONFIG_PINCTRL_PFC_SH7785
	463	{ "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
d2a31bdd LP	464	#endif
	465	#ifdef CONFIG_PINCTRL_PFC_SH7786
	466	{ "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
d5d9a818 LP	467	#endif
	468	#ifdef CONFIG_PINCTRL_PFC_SHX3
	469	{ "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
d5b1521a	470	#endif
c6193eac LP	471	{ "sh-pfc", 0 },
	472	{ },
	473	};
	474	MODULE_DEVICE_TABLE(platform, sh_pfc_id_table);
	475
	476	static struct platform_driver sh_pfc_driver = {
	477	.probe = sh_pfc_probe,
	478	.remove = sh_pfc_remove,
	479	.id_table = sh_pfc_id_table,
	480	.driver = {
	481	.name = DRV_NAME,
	482	.owner = THIS_MODULE,
	483	},
	484	};
	485
40ee6fce LP	486	static int __init sh_pfc_init(void)
	487	{
	488	return platform_driver_register(&sh_pfc_driver);
c6193eac	489	}
40ee6fce	490	postcore_initcall(sh_pfc_init);
c6193eac LP	491
	492	static void __exit sh_pfc_exit(void)
	493	{
	494	platform_driver_unregister(&sh_pfc_driver);
	495	}
	496	module_exit(sh_pfc_exit);
	497
6f6a4a68 LP	498	MODULE_AUTHOR("Magnus Damm, Paul Mundt, Laurent Pinchart");
	499	MODULE_DESCRIPTION("Pin Control and GPIO driver for SuperH pin function controller");
	500	MODULE_LICENSE("GPL v2");