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87f8c988 KM |
1 | /* |
2 | * r8a7778 processor support - PFC hardware block | |
3 | * | |
4 | * Copyright (C) 2013 Renesas Solutions Corp. | |
5 | * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | |
2d7cd398 | 6 | * Copyright (C) 2013 Cogent Embedded, Inc. |
ae7465a0 | 7 | * Copyright (C) 2015 Ulrich Hecht |
87f8c988 KM |
8 | * |
9 | * based on | |
10 | * Copyright (C) 2011 Renesas Solutions Corp. | |
11 | * Copyright (C) 2011 Magnus Damm | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License as published by | |
15 | * the Free Software Foundation; version 2 of the License. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | */ | |
22 | ||
ae7465a0 | 23 | #include <linux/io.h> |
87f8c988 | 24 | #include <linux/kernel.h> |
ae7465a0 | 25 | #include <linux/pinctrl/pinconf-generic.h> |
ae7465a0 | 26 | #include "core.h" |
87f8c988 KM |
27 | #include "sh_pfc.h" |
28 | ||
ae7465a0 UH |
29 | #define PORT_GP_PUP_1(bank, pin, fn, sfx) \ |
30 | PORT_GP_CFG_1(bank, pin, fn, sfx, SH_PFC_PIN_CFG_PULL_UP) | |
31 | ||
32 | #define PORT_GP_PUP_27(bank, fn, sfx) \ | |
33 | PORT_GP_PUP_1(bank, 0, fn, sfx), PORT_GP_PUP_1(bank, 1, fn, sfx), \ | |
34 | PORT_GP_PUP_1(bank, 2, fn, sfx), PORT_GP_PUP_1(bank, 3, fn, sfx), \ | |
35 | PORT_GP_PUP_1(bank, 4, fn, sfx), PORT_GP_PUP_1(bank, 5, fn, sfx), \ | |
36 | PORT_GP_PUP_1(bank, 6, fn, sfx), PORT_GP_PUP_1(bank, 7, fn, sfx), \ | |
37 | PORT_GP_PUP_1(bank, 8, fn, sfx), PORT_GP_PUP_1(bank, 9, fn, sfx), \ | |
38 | PORT_GP_PUP_1(bank, 10, fn, sfx), PORT_GP_PUP_1(bank, 11, fn, sfx), \ | |
39 | PORT_GP_PUP_1(bank, 12, fn, sfx), PORT_GP_PUP_1(bank, 13, fn, sfx), \ | |
40 | PORT_GP_PUP_1(bank, 14, fn, sfx), PORT_GP_PUP_1(bank, 15, fn, sfx), \ | |
41 | PORT_GP_PUP_1(bank, 16, fn, sfx), PORT_GP_PUP_1(bank, 17, fn, sfx), \ | |
42 | PORT_GP_PUP_1(bank, 18, fn, sfx), PORT_GP_PUP_1(bank, 19, fn, sfx), \ | |
43 | PORT_GP_PUP_1(bank, 20, fn, sfx), PORT_GP_PUP_1(bank, 21, fn, sfx), \ | |
44 | PORT_GP_PUP_1(bank, 22, fn, sfx), PORT_GP_PUP_1(bank, 23, fn, sfx), \ | |
45 | PORT_GP_PUP_1(bank, 24, fn, sfx), PORT_GP_PUP_1(bank, 25, fn, sfx), \ | |
46 | PORT_GP_PUP_1(bank, 26, fn, sfx) | |
87f8c988 KM |
47 | |
48 | #define CPU_ALL_PORT(fn, sfx) \ | |
ae7465a0 UH |
49 | PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ |
50 | PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ | |
51 | PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ | |
52 | PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ | |
53 | PORT_GP_PUP_27(4, fn, sfx) | |
87f8c988 | 54 | |
87f8c988 KM |
55 | enum { |
56 | PINMUX_RESERVED = 0, | |
57 | ||
58 | PINMUX_DATA_BEGIN, | |
59 | GP_ALL(DATA), /* GP_0_0_DATA -> GP_4_26_DATA */ | |
60 | PINMUX_DATA_END, | |
61 | ||
62 | PINMUX_FUNCTION_BEGIN, | |
63 | GP_ALL(FN), /* GP_0_0_FN -> GP_4_26_FN */ | |
64 | ||
65 | /* GPSR0 */ | |
66 | FN_IP0_1_0, FN_PENC0, FN_PENC1, FN_IP0_4_2, | |
67 | FN_IP0_7_5, FN_IP0_11_8, FN_IP0_14_12, FN_A1, | |
68 | FN_A2, FN_A3, FN_IP0_15, FN_IP0_16, | |
69 | FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20, | |
70 | FN_IP0_21, FN_IP0_22, FN_IP0_23, FN_IP0_24, | |
71 | FN_IP0_25, FN_IP0_26, FN_IP0_27, FN_IP0_28, | |
72 | FN_IP0_29, FN_IP0_30, FN_IP1_0, FN_IP1_1, | |
73 | FN_IP1_4_2, FN_IP1_7_5, FN_IP1_10_8, FN_IP1_14_11, | |
74 | ||
75 | /* GPSR1 */ | |
76 | FN_IP1_23_21, FN_WE0, FN_IP1_24, FN_IP1_27_25, | |
77 | FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, | |
78 | FN_IP2_11_9, FN_IP2_13_12, FN_IP2_16_14, FN_IP2_17, | |
79 | FN_IP2_30, FN_IP2_31, FN_IP3_1_0, FN_IP3_4_2, | |
80 | FN_IP3_7_5, FN_IP3_9_8, FN_IP3_12_10, FN_IP3_15_13, | |
81 | FN_IP3_18_16, FN_IP3_20_19, FN_IP3_23_21, FN_IP3_26_24, | |
82 | FN_IP3_27, FN_IP3_28, FN_IP3_29, FN_IP3_30, | |
83 | FN_IP3_31, FN_IP4_0, FN_IP4_3_1, FN_IP4_6_4, | |
84 | ||
85 | /* GPSR2 */ | |
86 | FN_IP4_7, FN_IP4_8, FN_IP4_10_9, FN_IP4_12_11, | |
87 | FN_IP4_14_13, FN_IP4_16_15, FN_IP4_20_17, FN_IP4_24_21, | |
88 | FN_IP4_26_25, FN_IP4_28_27, FN_IP4_30_29, FN_IP5_1_0, | |
89 | FN_IP5_3_2, FN_IP5_5_4, FN_IP5_6, FN_IP5_7, | |
90 | FN_IP5_9_8, FN_IP5_11_10, FN_IP5_12, FN_IP5_14_13, | |
91 | FN_IP5_17_15, FN_IP5_20_18, FN_AUDIO_CLKA, FN_AUDIO_CLKB, | |
92 | FN_IP5_22_21, FN_IP5_25_23, FN_IP5_28_26, FN_IP5_30_29, | |
93 | FN_IP6_1_0, FN_IP6_4_2, FN_IP6_6_5, FN_IP6_7, | |
94 | ||
95 | /* GPSR3 */ | |
96 | FN_IP6_8, FN_IP6_9, FN_SSI_SCK34, FN_IP6_10, | |
97 | FN_IP6_12_11, FN_IP6_13, FN_IP6_15_14, FN_IP6_16, | |
98 | FN_IP6_18_17, FN_IP6_20_19, FN_IP6_21, FN_IP6_23_22, | |
99 | FN_IP6_25_24, FN_IP6_27_26, FN_IP6_29_28, FN_IP6_31_30, | |
100 | FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_8_6, | |
101 | FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18, | |
102 | FN_IP7_21, FN_IP7_24_22, FN_IP7_28_25, FN_IP7_31_29, | |
103 | FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_10_9, | |
104 | ||
105 | /* GPSR4 */ | |
106 | FN_IP8_13_11, FN_IP8_15_14, FN_IP8_18_16, FN_IP8_21_19, | |
107 | FN_IP8_23_22, FN_IP8_26_24, FN_IP8_29_27, FN_IP9_2_0, | |
108 | FN_IP9_5_3, FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, | |
109 | FN_IP9_17_15, FN_IP9_20_18, FN_IP9_23_21, FN_IP9_26_24, | |
110 | FN_IP9_29_27, FN_IP10_2_0, FN_IP10_5_3, FN_IP10_8_6, | |
111 | FN_IP10_12_9, FN_IP10_15_13, FN_IP10_18_16, FN_IP10_21_19, | |
112 | FN_IP10_24_22, FN_AVS1, FN_AVS2, | |
113 | ||
114 | /* IPSR0 */ | |
115 | FN_PRESETOUT, FN_PWM1, FN_AUDATA0, FN_ARM_TRACEDATA_0, | |
116 | FN_GPSCLK_C, FN_USB_OVC0, FN_TX2_E, FN_SDA2_B, | |
117 | FN_AUDATA1, FN_ARM_TRACEDATA_1, FN_GPSIN_C, | |
118 | FN_USB_OVC1, FN_RX2_E, FN_SCL2_B, FN_SD1_DAT2_A, | |
119 | FN_MMC_D2, FN_BS, FN_ATADIR0_A, FN_SDSELF_A, | |
120 | FN_PWM4_B, FN_SD1_DAT3_A, FN_MMC_D3, FN_A0, | |
121 | FN_ATAG0_A, FN_REMOCON_B, FN_A4, FN_A5, | |
122 | FN_A6, FN_A7, FN_A8, FN_A9, | |
123 | FN_A10, FN_A11, FN_A12, FN_A13, | |
124 | FN_A14, FN_A15, FN_A16, FN_A17, | |
125 | FN_A18, FN_A19, | |
126 | ||
127 | /* IPSR1 */ | |
128 | FN_A20, FN_HSPI_CS1_B, FN_A21, FN_HSPI_CLK1_B, | |
129 | FN_A22, FN_HRTS0_B, FN_RX2_B, FN_DREQ2_A, | |
130 | FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A, | |
131 | FN_TS_SDEN0_A, FN_SD1_CD_A, FN_MMC_D6, FN_A24, | |
132 | FN_DREQ1_A, FN_HRX0_B, FN_TS_SPSYNC0_A, | |
133 | FN_SD1_WP_A, FN_MMC_D7, FN_A25, FN_DACK1_A, | |
134 | FN_HCTS0_B, FN_RX3_C, FN_TS_SDAT0_A, FN_CLKOUT, | |
135 | FN_HSPI_TX1_B, FN_PWM0_B, FN_CS0, FN_HSPI_RX1_B, | |
136 | FN_SSI_SCK1_B, FN_ATAG0_B, FN_CS1_A26, FN_SDA2_A, | |
137 | FN_SCK2_B, FN_MMC_D5, FN_ATADIR0_B, FN_RD_WR, | |
138 | FN_WE1, FN_ATAWR0_B, FN_SSI_WS1_B, FN_EX_CS0, | |
139 | FN_SCL2_A, FN_TX3_C, FN_TS_SCK0_A, FN_EX_CS1, | |
140 | FN_MMC_D4, | |
141 | ||
142 | /* IPSR2 */ | |
143 | FN_SD1_CLK_A, FN_MMC_CLK, FN_ATACS00, FN_EX_CS2, | |
144 | FN_SD1_CMD_A, FN_MMC_CMD, FN_ATACS10, FN_EX_CS3, | |
145 | FN_SD1_DAT0_A, FN_MMC_D0, FN_ATARD0, FN_EX_CS4, | |
146 | FN_EX_WAIT1_A, FN_SD1_DAT1_A, FN_MMC_D1, FN_ATAWR0_A, | |
147 | FN_EX_CS5, FN_EX_WAIT2_A, FN_DREQ0_A, FN_RX3_A, | |
148 | FN_DACK0, FN_TX3_A, FN_DRACK0, FN_EX_WAIT0, | |
149 | FN_PWM0_C, FN_D0, FN_D1, FN_D2, | |
150 | FN_D3, FN_D4, FN_D5, FN_D6, | |
151 | FN_D7, FN_D8, FN_D9, FN_D10, | |
152 | FN_D11, FN_RD_WR_B, FN_IRQ0, FN_MLB_CLK, | |
153 | FN_IRQ1_A, | |
154 | ||
155 | /* IPSR3 */ | |
156 | FN_MLB_SIG, FN_RX5_B, FN_SDA3_A, FN_IRQ2_A, | |
157 | FN_MLB_DAT, FN_TX5_B, FN_SCL3_A, FN_IRQ3_A, | |
158 | FN_SDSELF_B, FN_SD1_CMD_B, FN_SCIF_CLK, FN_AUDIO_CLKOUT_B, | |
159 | FN_CAN_CLK_B, FN_SDA3_B, FN_SD1_CLK_B, FN_HTX0_A, | |
160 | FN_TX0_A, FN_SD1_DAT0_B, FN_HRX0_A, FN_RX0_A, | |
161 | FN_SD1_DAT1_B, FN_HSCK0, FN_SCK0, FN_SCL3_B, | |
162 | FN_SD1_DAT2_B, FN_HCTS0_A, FN_CTS0, FN_SD1_DAT3_B, | |
163 | FN_HRTS0_A, FN_RTS0, FN_SSI_SCK4, FN_DU0_DR0, | |
164 | FN_LCDOUT0, FN_AUDATA2, FN_ARM_TRACEDATA_2, | |
165 | FN_SDA3_C, FN_ADICHS1, FN_TS_SDEN0_B, FN_SSI_WS4, | |
166 | FN_DU0_DR1, FN_LCDOUT1, FN_AUDATA3, FN_ARM_TRACEDATA_3, | |
167 | FN_SCL3_C, FN_ADICHS2, FN_TS_SPSYNC0_B, | |
168 | FN_DU0_DR2, FN_LCDOUT2, FN_DU0_DR3, FN_LCDOUT3, | |
169 | FN_DU0_DR4, FN_LCDOUT4, FN_DU0_DR5, FN_LCDOUT5, | |
170 | FN_DU0_DR6, FN_LCDOUT6, | |
171 | ||
172 | /* IPSR4 */ | |
173 | FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8, | |
174 | FN_AUDATA4, FN_ARM_TRACEDATA_4, FN_TX1_D, | |
175 | FN_CAN0_TX_A, FN_ADICHS0, FN_DU0_DG1, FN_LCDOUT9, | |
176 | FN_AUDATA5, FN_ARM_TRACEDATA_5, FN_RX1_D, | |
177 | FN_CAN0_RX_A, FN_ADIDATA, FN_DU0_DG2, FN_LCDOUT10, | |
178 | FN_DU0_DG3, FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12, | |
179 | FN_RX0_B, FN_DU0_DG5, FN_LCDOUT13, FN_TX0_B, | |
180 | FN_DU0_DG6, FN_LCDOUT14, FN_RX4_A, FN_DU0_DG7, | |
181 | FN_LCDOUT15, FN_TX4_A, FN_SSI_SCK2_B, FN_VI0_R0_B, | |
182 | FN_DU0_DB0, FN_LCDOUT16, FN_AUDATA6, FN_ARM_TRACEDATA_6, | |
183 | FN_GPSCLK_A, FN_PWM0_A, FN_ADICLK, FN_TS_SDAT0_B, | |
184 | FN_AUDIO_CLKC, FN_VI0_R1_B, FN_DU0_DB1, FN_LCDOUT17, | |
185 | FN_AUDATA7, FN_ARM_TRACEDATA_7, FN_GPSIN_A, | |
186 | FN_ADICS_SAMP, FN_TS_SCK0_B, FN_VI0_R2_B, FN_DU0_DB2, | |
187 | FN_LCDOUT18, FN_VI0_R3_B, FN_DU0_DB3, FN_LCDOUT19, | |
188 | FN_VI0_R4_B, FN_DU0_DB4, FN_LCDOUT20, | |
189 | ||
190 | /* IPSR5 */ | |
191 | FN_VI0_R5_B, FN_DU0_DB5, FN_LCDOUT21, FN_VI1_DATA10_B, | |
192 | FN_DU0_DB6, FN_LCDOUT22, FN_VI1_DATA11_B, | |
193 | FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN, | |
194 | FN_QSTVA_QVS, FN_DU0_DOTCLKO_UT0, FN_QCLK, | |
195 | FN_DU0_DOTCLKO_UT1, FN_QSTVB_QVE, FN_AUDIO_CLKOUT_A, | |
196 | FN_REMOCON_C, FN_SSI_WS2_B, FN_DU0_EXHSYNC_DU0_HSYNC, | |
197 | FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, | |
198 | FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, | |
199 | FN_QCPV_QDE, FN_FMCLK_D, FN_SSI_SCK1_A, FN_DU0_DISP, | |
200 | FN_QPOLA, FN_AUDCK, FN_ARM_TRACECLK, | |
201 | FN_BPFCLK_D, FN_SSI_WS1_A, FN_DU0_CDE, FN_QPOLB, | |
202 | FN_AUDSYNC, FN_ARM_TRACECTL, FN_FMIN_D, | |
203 | FN_SD1_CD_B, FN_SSI_SCK78, FN_HSPI_RX0_B, FN_TX1_B, | |
204 | FN_SD1_WP_B, FN_SSI_WS78, FN_HSPI_CLK0_B, FN_RX1_B, | |
205 | FN_CAN_CLK_D, FN_SSI_SDATA8, FN_SSI_SCK2_A, FN_HSPI_CS0_B, | |
206 | FN_TX2_A, FN_CAN0_TX_B, FN_SSI_SDATA7, FN_HSPI_TX0_B, | |
207 | FN_RX2_A, FN_CAN0_RX_B, | |
208 | ||
209 | /* IPSR6 */ | |
210 | FN_SSI_SCK6, FN_HSPI_RX2_A, FN_FMCLK_B, FN_CAN1_TX_B, | |
211 | FN_SSI_WS6, FN_HSPI_CLK2_A, FN_BPFCLK_B, FN_CAN1_RX_B, | |
212 | FN_SSI_SDATA6, FN_HSPI_TX2_A, FN_FMIN_B, FN_SSI_SCK5, | |
213 | FN_RX4_C, FN_SSI_WS5, FN_TX4_C, FN_SSI_SDATA5, | |
214 | FN_RX0_D, FN_SSI_WS34, FN_ARM_TRACEDATA_8, | |
215 | FN_SSI_SDATA4, FN_SSI_WS2_A, FN_ARM_TRACEDATA_9, | |
216 | FN_SSI_SDATA3, FN_ARM_TRACEDATA_10, | |
217 | FN_SSI_SCK012, FN_ARM_TRACEDATA_11, | |
218 | FN_TX0_D, FN_SSI_WS012, FN_ARM_TRACEDATA_12, | |
219 | FN_SSI_SDATA2, FN_HSPI_CS2_A, FN_ARM_TRACEDATA_13, | |
220 | FN_SDA1_A, FN_SSI_SDATA1, FN_ARM_TRACEDATA_14, | |
221 | FN_SCL1_A, FN_SCK2_A, FN_SSI_SDATA0, | |
222 | FN_ARM_TRACEDATA_15, | |
223 | FN_SD0_CLK, FN_SUB_TDO, FN_SD0_CMD, FN_SUB_TRST, | |
224 | FN_SD0_DAT0, FN_SUB_TMS, FN_SD0_DAT1, FN_SUB_TCK, | |
225 | FN_SD0_DAT2, FN_SUB_TDI, | |
226 | ||
227 | /* IPSR7 */ | |
228 | FN_SD0_DAT3, FN_IRQ1_B, FN_SD0_CD, FN_TX5_A, | |
229 | FN_SD0_WP, FN_RX5_A, FN_VI1_CLKENB, FN_HSPI_CLK0_A, | |
230 | FN_HTX1_A, FN_RTS1_C, FN_VI1_FIELD, FN_HSPI_CS0_A, | |
231 | FN_HRX1_A, FN_SCK1_C, FN_VI1_HSYNC, FN_HSPI_RX0_A, | |
232 | FN_HRTS1_A, FN_FMCLK_A, FN_RX1_C, FN_VI1_VSYNC, | |
233 | FN_HSPI_TX0, FN_HCTS1_A, FN_BPFCLK_A, FN_TX1_C, | |
234 | FN_TCLK0, FN_HSCK1_A, FN_FMIN_A, FN_IRQ2_C, | |
235 | FN_CTS1_C, FN_SPEEDIN, FN_VI0_CLK, FN_CAN_CLK_A, | |
236 | FN_VI0_CLKENB, FN_SD2_DAT2_B, FN_VI1_DATA0, FN_DU1_DG6, | |
237 | FN_HSPI_RX1_A, FN_RX4_B, FN_VI0_FIELD, FN_SD2_DAT3_B, | |
238 | FN_VI0_R3_C, FN_VI1_DATA1, FN_DU1_DG7, FN_HSPI_CLK1_A, | |
239 | FN_TX4_B, FN_VI0_HSYNC, FN_SD2_CD_B, FN_VI1_DATA2, | |
240 | FN_DU1_DR2, FN_HSPI_CS1_A, FN_RX3_B, | |
241 | ||
242 | /* IPSR8 */ | |
243 | FN_VI0_VSYNC, FN_SD2_WP_B, FN_VI1_DATA3, FN_DU1_DR3, | |
244 | FN_HSPI_TX1_A, FN_TX3_B, FN_VI0_DATA0_VI0_B0, | |
245 | FN_DU1_DG2, FN_IRQ2_B, FN_RX3_D, FN_VI0_DATA1_VI0_B1, | |
246 | FN_DU1_DG3, FN_IRQ3_B, FN_TX3_D, FN_VI0_DATA2_VI0_B2, | |
247 | FN_DU1_DG4, FN_RX0_C, FN_VI0_DATA3_VI0_B3, | |
248 | FN_DU1_DG5, FN_TX1_A, FN_TX0_C, FN_VI0_DATA4_VI0_B4, | |
249 | FN_DU1_DB2, FN_RX1_A, FN_VI0_DATA5_VI0_B5, | |
250 | FN_DU1_DB3, FN_SCK1_A, FN_PWM4, FN_HSCK1_B, | |
251 | FN_VI0_DATA6_VI0_G0, FN_DU1_DB4, FN_CTS1_A, | |
252 | FN_PWM5, FN_VI0_DATA7_VI0_G1, FN_DU1_DB5, | |
253 | FN_RTS1_A, FN_VI0_G2, FN_SD2_CLK_B, FN_VI1_DATA4, | |
254 | FN_DU1_DR4, FN_HTX1_B, FN_VI0_G3, FN_SD2_CMD_B, | |
255 | FN_VI1_DATA5, FN_DU1_DR5, FN_HRX1_B, | |
256 | ||
257 | /* IPSR9 */ | |
258 | FN_VI0_G4, FN_SD2_DAT0_B, FN_VI1_DATA6, FN_DU1_DR6, | |
259 | FN_HRTS1_B, FN_VI0_G5, FN_SD2_DAT1_B, FN_VI1_DATA7, | |
260 | FN_DU1_DR7, FN_HCTS1_B, FN_VI0_R0_A, FN_VI1_CLK, | |
261 | FN_ETH_REF_CLK, FN_DU1_DOTCLKIN, FN_VI0_R1_A, | |
262 | FN_VI1_DATA8, FN_DU1_DB6, FN_ETH_TXD0, FN_PWM2, | |
263 | FN_TCLK1, FN_VI0_R2_A, FN_VI1_DATA9, FN_DU1_DB7, | |
264 | FN_ETH_TXD1, FN_PWM3, FN_VI0_R3_A, FN_ETH_CRS_DV, | |
265 | FN_IECLK, FN_SCK2_C, FN_VI0_R4_A, FN_ETH_TX_EN, | |
266 | FN_IETX, FN_TX2_C, FN_VI0_R5_A, FN_ETH_RX_ER, | |
267 | FN_FMCLK_C, FN_IERX, FN_RX2_C, FN_VI1_DATA10_A, | |
268 | FN_DU1_DOTCLKOUT, FN_ETH_RXD0, FN_BPFCLK_C, | |
269 | FN_TX2_D, FN_SDA2_C, FN_VI1_DATA11_A, | |
270 | FN_DU1_EXHSYNC_DU1_HSYNC, FN_ETH_RXD1, FN_FMIN_C, | |
271 | FN_RX2_D, FN_SCL2_C, | |
272 | ||
273 | /* IPSR10 */ | |
274 | FN_SD2_CLK_A, FN_DU1_EXVSYNC_DU1_VSYNC, FN_ATARD1, | |
275 | FN_ETH_MDC, FN_SDA1_B, FN_SD2_CMD_A, | |
276 | FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_ATAWR1, | |
277 | FN_ETH_MDIO, FN_SCL1_B, FN_SD2_DAT0_A, FN_DU1_DISP, | |
278 | FN_ATACS01, FN_DREQ1_B, FN_ETH_LINK, FN_CAN1_RX_A, | |
279 | FN_SD2_DAT1_A, FN_DU1_CDE, FN_ATACS11, FN_DACK1_B, | |
280 | FN_ETH_MAGIC, FN_CAN1_TX_A, FN_PWM6, FN_SD2_DAT2_A, | |
281 | FN_VI1_DATA12, FN_DREQ2_B, FN_ATADIR1, FN_HSPI_CLK2_B, | |
282 | FN_GPSCLK_B, FN_SD2_DAT3_A, FN_VI1_DATA13, FN_DACK2_B, | |
283 | FN_ATAG1, FN_HSPI_CS2_B, FN_GPSIN_B, FN_SD2_CD_A, | |
284 | FN_VI1_DATA14, FN_EX_WAIT1_B, FN_DREQ0_B, FN_HSPI_RX2_B, | |
285 | FN_REMOCON_A, FN_SD2_WP_A, FN_VI1_DATA15, FN_EX_WAIT2_B, | |
286 | FN_DACK0_B, FN_HSPI_TX2_B, FN_CAN_CLK_C, | |
287 | ||
288 | /* SEL */ | |
289 | FN_SEL_SCIF5_A, FN_SEL_SCIF5_B, | |
290 | FN_SEL_SCIF4_A, FN_SEL_SCIF4_B, FN_SEL_SCIF4_C, | |
291 | FN_SEL_SCIF3_A, FN_SEL_SCIF3_B, FN_SEL_SCIF3_C, FN_SEL_SCIF3_D, | |
292 | FN_SEL_SCIF2_A, FN_SEL_SCIF2_B, FN_SEL_SCIF2_C, FN_SEL_SCIF2_D, FN_SEL_SCIF2_E, | |
293 | FN_SEL_SCIF1_A, FN_SEL_SCIF1_B, FN_SEL_SCIF1_C, FN_SEL_SCIF1_D, | |
294 | FN_SEL_SCIF0_A, FN_SEL_SCIF0_B, FN_SEL_SCIF0_C, FN_SEL_SCIF0_D, | |
295 | FN_SEL_SSI2_A, FN_SEL_SSI2_B, | |
296 | FN_SEL_SSI1_A, FN_SEL_SSI1_B, | |
297 | FN_SEL_VI1_A, FN_SEL_VI1_B, | |
298 | FN_SEL_VI0_A, FN_SEL_VI0_B, FN_SEL_VI0_C, FN_SEL_VI0_D, | |
299 | FN_SEL_SD2_A, FN_SEL_SD2_B, | |
300 | FN_SEL_SD1_A, FN_SEL_SD1_B, | |
301 | FN_SEL_IRQ3_A, FN_SEL_IRQ3_B, | |
302 | FN_SEL_IRQ2_A, FN_SEL_IRQ2_B, FN_SEL_IRQ2_C, | |
303 | FN_SEL_IRQ1_A, FN_SEL_IRQ1_B, | |
304 | FN_SEL_DREQ2_A, FN_SEL_DREQ2_B, | |
305 | FN_SEL_DREQ1_A, FN_SEL_DREQ1_B, | |
306 | FN_SEL_DREQ0_A, FN_SEL_DREQ0_B, | |
307 | FN_SEL_WAIT2_A, FN_SEL_WAIT2_B, | |
308 | FN_SEL_WAIT1_A, FN_SEL_WAIT1_B, | |
309 | FN_SEL_CAN1_A, FN_SEL_CAN1_B, | |
310 | FN_SEL_CAN0_A, FN_SEL_CAN0_B, | |
311 | FN_SEL_CANCLK_A, FN_SEL_CANCLK_B, | |
312 | FN_SEL_CANCLK_C, FN_SEL_CANCLK_D, | |
313 | FN_SEL_HSCIF1_A, FN_SEL_HSCIF1_B, | |
314 | FN_SEL_HSCIF0_A, FN_SEL_HSCIF0_B, | |
315 | FN_SEL_REMOCON_A, FN_SEL_REMOCON_B, FN_SEL_REMOCON_C, | |
316 | FN_SEL_FM_A, FN_SEL_FM_B, FN_SEL_FM_C, FN_SEL_FM_D, | |
317 | FN_SEL_GPS_A, FN_SEL_GPS_B, FN_SEL_GPS_C, | |
318 | FN_SEL_TSIF0_A, FN_SEL_TSIF0_B, | |
319 | FN_SEL_HSPI2_A, FN_SEL_HSPI2_B, | |
320 | FN_SEL_HSPI1_A, FN_SEL_HSPI1_B, | |
321 | FN_SEL_HSPI0_A, FN_SEL_HSPI0_B, | |
322 | FN_SEL_I2C3_A, FN_SEL_I2C3_B, FN_SEL_I2C3_C, | |
323 | FN_SEL_I2C2_A, FN_SEL_I2C2_B, FN_SEL_I2C2_C, | |
324 | FN_SEL_I2C1_A, FN_SEL_I2C1_B, | |
325 | PINMUX_FUNCTION_END, | |
326 | ||
327 | PINMUX_MARK_BEGIN, | |
328 | ||
329 | /* GPSR0 */ | |
330 | PENC0_MARK, PENC1_MARK, A1_MARK, A2_MARK, A3_MARK, | |
331 | ||
332 | /* GPSR1 */ | |
333 | WE0_MARK, | |
334 | ||
335 | /* GPSR2 */ | |
336 | AUDIO_CLKA_MARK, | |
337 | AUDIO_CLKB_MARK, | |
338 | ||
339 | /* GPSR3 */ | |
340 | SSI_SCK34_MARK, | |
341 | ||
342 | /* GPSR4 */ | |
343 | AVS1_MARK, | |
344 | AVS2_MARK, | |
345 | ||
0eef12d7 LP |
346 | VI0_R0_C_MARK, /* see sel_vi0 */ |
347 | VI0_R1_C_MARK, /* see sel_vi0 */ | |
348 | VI0_R2_C_MARK, /* see sel_vi0 */ | |
349 | /* VI0_R3_C_MARK, */ | |
350 | VI0_R4_C_MARK, /* see sel_vi0 */ | |
351 | VI0_R5_C_MARK, /* see sel_vi0 */ | |
352 | ||
353 | VI0_R0_D_MARK, /* see sel_vi0 */ | |
354 | VI0_R1_D_MARK, /* see sel_vi0 */ | |
355 | VI0_R2_D_MARK, /* see sel_vi0 */ | |
356 | VI0_R3_D_MARK, /* see sel_vi0 */ | |
357 | VI0_R4_D_MARK, /* see sel_vi0 */ | |
358 | VI0_R5_D_MARK, /* see sel_vi0 */ | |
87f8c988 KM |
359 | |
360 | /* IPSR0 */ | |
361 | PRESETOUT_MARK, PWM1_MARK, AUDATA0_MARK, | |
362 | ARM_TRACEDATA_0_MARK, GPSCLK_C_MARK, USB_OVC0_MARK, | |
363 | TX2_E_MARK, SDA2_B_MARK, AUDATA1_MARK, ARM_TRACEDATA_1_MARK, | |
364 | GPSIN_C_MARK, USB_OVC1_MARK, RX2_E_MARK, SCL2_B_MARK, | |
365 | SD1_DAT2_A_MARK, MMC_D2_MARK, BS_MARK, | |
366 | ATADIR0_A_MARK, SDSELF_A_MARK, PWM4_B_MARK, SD1_DAT3_A_MARK, | |
367 | MMC_D3_MARK, A0_MARK, ATAG0_A_MARK, REMOCON_B_MARK, | |
368 | A4_MARK, A5_MARK, A6_MARK, A7_MARK, | |
369 | A8_MARK, A9_MARK, A10_MARK, A11_MARK, | |
370 | A12_MARK, A13_MARK, A14_MARK, A15_MARK, | |
371 | A16_MARK, A17_MARK, A18_MARK, A19_MARK, | |
372 | ||
373 | /* IPSR1 */ | |
374 | A20_MARK, HSPI_CS1_B_MARK, A21_MARK, | |
375 | HSPI_CLK1_B_MARK, A22_MARK, HRTS0_B_MARK, | |
376 | RX2_B_MARK, DREQ2_A_MARK, A23_MARK, HTX0_B_MARK, | |
377 | TX2_B_MARK, DACK2_A_MARK, TS_SDEN0_A_MARK, | |
378 | SD1_CD_A_MARK, MMC_D6_MARK, A24_MARK, DREQ1_A_MARK, | |
379 | HRX0_B_MARK, TS_SPSYNC0_A_MARK, SD1_WP_A_MARK, | |
380 | MMC_D7_MARK, A25_MARK, DACK1_A_MARK, HCTS0_B_MARK, | |
381 | RX3_C_MARK, TS_SDAT0_A_MARK, CLKOUT_MARK, | |
382 | HSPI_TX1_B_MARK, PWM0_B_MARK, CS0_MARK, | |
383 | HSPI_RX1_B_MARK, SSI_SCK1_B_MARK, | |
384 | ATAG0_B_MARK, CS1_A26_MARK, SDA2_A_MARK, SCK2_B_MARK, | |
385 | MMC_D5_MARK, ATADIR0_B_MARK, RD_WR_MARK, WE1_MARK, | |
386 | ATAWR0_B_MARK, SSI_WS1_B_MARK, EX_CS0_MARK, SCL2_A_MARK, | |
387 | TX3_C_MARK, TS_SCK0_A_MARK, EX_CS1_MARK, MMC_D4_MARK, | |
388 | ||
389 | /* IPSR2 */ | |
390 | SD1_CLK_A_MARK, MMC_CLK_MARK, ATACS00_MARK, EX_CS2_MARK, | |
391 | SD1_CMD_A_MARK, MMC_CMD_MARK, ATACS10_MARK, EX_CS3_MARK, | |
392 | SD1_DAT0_A_MARK, MMC_D0_MARK, ATARD0_MARK, | |
393 | EX_CS4_MARK, EX_WAIT1_A_MARK, SD1_DAT1_A_MARK, | |
394 | MMC_D1_MARK, ATAWR0_A_MARK, EX_CS5_MARK, EX_WAIT2_A_MARK, | |
395 | DREQ0_A_MARK, RX3_A_MARK, DACK0_MARK, TX3_A_MARK, | |
396 | DRACK0_MARK, EX_WAIT0_MARK, PWM0_C_MARK, D0_MARK, | |
397 | D1_MARK, D2_MARK, D3_MARK, D4_MARK, | |
398 | D5_MARK, D6_MARK, D7_MARK, D8_MARK, | |
399 | D9_MARK, D10_MARK, D11_MARK, RD_WR_B_MARK, | |
400 | IRQ0_MARK, MLB_CLK_MARK, IRQ1_A_MARK, | |
401 | ||
402 | /* IPSR3 */ | |
403 | MLB_SIG_MARK, RX5_B_MARK, SDA3_A_MARK, IRQ2_A_MARK, | |
404 | MLB_DAT_MARK, TX5_B_MARK, SCL3_A_MARK, IRQ3_A_MARK, | |
405 | SDSELF_B_MARK, SD1_CMD_B_MARK, SCIF_CLK_MARK, AUDIO_CLKOUT_B_MARK, | |
406 | CAN_CLK_B_MARK, SDA3_B_MARK, SD1_CLK_B_MARK, HTX0_A_MARK, | |
407 | TX0_A_MARK, SD1_DAT0_B_MARK, HRX0_A_MARK, | |
408 | RX0_A_MARK, SD1_DAT1_B_MARK, HSCK0_MARK, | |
409 | SCK0_MARK, SCL3_B_MARK, SD1_DAT2_B_MARK, | |
410 | HCTS0_A_MARK, CTS0_MARK, SD1_DAT3_B_MARK, | |
411 | HRTS0_A_MARK, RTS0_MARK, SSI_SCK4_MARK, | |
412 | DU0_DR0_MARK, LCDOUT0_MARK, AUDATA2_MARK, ARM_TRACEDATA_2_MARK, | |
413 | SDA3_C_MARK, ADICHS1_MARK, TS_SDEN0_B_MARK, | |
414 | SSI_WS4_MARK, DU0_DR1_MARK, LCDOUT1_MARK, AUDATA3_MARK, | |
415 | ARM_TRACEDATA_3_MARK, SCL3_C_MARK, ADICHS2_MARK, | |
416 | TS_SPSYNC0_B_MARK, DU0_DR2_MARK, LCDOUT2_MARK, | |
417 | DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK, | |
418 | DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK, | |
419 | ||
420 | /* IPSR4 */ | |
421 | DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK, | |
422 | AUDATA4_MARK, ARM_TRACEDATA_4_MARK, | |
423 | TX1_D_MARK, CAN0_TX_A_MARK, ADICHS0_MARK, DU0_DG1_MARK, | |
424 | LCDOUT9_MARK, AUDATA5_MARK, ARM_TRACEDATA_5_MARK, | |
425 | RX1_D_MARK, CAN0_RX_A_MARK, ADIDATA_MARK, DU0_DG2_MARK, | |
426 | LCDOUT10_MARK, DU0_DG3_MARK, LCDOUT11_MARK, DU0_DG4_MARK, | |
427 | LCDOUT12_MARK, RX0_B_MARK, DU0_DG5_MARK, LCDOUT13_MARK, | |
428 | TX0_B_MARK, DU0_DG6_MARK, LCDOUT14_MARK, RX4_A_MARK, | |
429 | DU0_DG7_MARK, LCDOUT15_MARK, TX4_A_MARK, SSI_SCK2_B_MARK, | |
430 | VI0_R0_B_MARK, DU0_DB0_MARK, LCDOUT16_MARK, AUDATA6_MARK, | |
431 | ARM_TRACEDATA_6_MARK, GPSCLK_A_MARK, PWM0_A_MARK, | |
432 | ADICLK_MARK, TS_SDAT0_B_MARK, AUDIO_CLKC_MARK, | |
433 | VI0_R1_B_MARK, DU0_DB1_MARK, LCDOUT17_MARK, AUDATA7_MARK, | |
434 | ARM_TRACEDATA_7_MARK, GPSIN_A_MARK, ADICS_SAMP_MARK, | |
435 | TS_SCK0_B_MARK, VI0_R2_B_MARK, DU0_DB2_MARK, LCDOUT18_MARK, | |
436 | VI0_R3_B_MARK, DU0_DB3_MARK, LCDOUT19_MARK, VI0_R4_B_MARK, | |
437 | DU0_DB4_MARK, LCDOUT20_MARK, | |
438 | ||
439 | /* IPSR5 */ | |
440 | VI0_R5_B_MARK, DU0_DB5_MARK, LCDOUT21_MARK, VI1_DATA10_B_MARK, | |
441 | DU0_DB6_MARK, LCDOUT22_MARK, VI1_DATA11_B_MARK, | |
442 | DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK, | |
443 | QSTVA_QVS_MARK, DU0_DOTCLKO_UT0_MARK, | |
444 | QCLK_MARK, DU0_DOTCLKO_UT1_MARK, QSTVB_QVE_MARK, | |
445 | AUDIO_CLKOUT_A_MARK, REMOCON_C_MARK, SSI_WS2_B_MARK, | |
446 | DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK, | |
447 | DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, | |
448 | DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, | |
449 | QCPV_QDE_MARK, FMCLK_D_MARK, SSI_SCK1_A_MARK, | |
450 | DU0_DISP_MARK, QPOLA_MARK, AUDCK_MARK, ARM_TRACECLK_MARK, | |
451 | BPFCLK_D_MARK, SSI_WS1_A_MARK, DU0_CDE_MARK, QPOLB_MARK, | |
452 | AUDSYNC_MARK, ARM_TRACECTL_MARK, FMIN_D_MARK, | |
453 | SD1_CD_B_MARK, SSI_SCK78_MARK, HSPI_RX0_B_MARK, | |
454 | TX1_B_MARK, SD1_WP_B_MARK, SSI_WS78_MARK, HSPI_CLK0_B_MARK, | |
455 | RX1_B_MARK, CAN_CLK_D_MARK, SSI_SDATA8_MARK, | |
456 | SSI_SCK2_A_MARK, HSPI_CS0_B_MARK, | |
457 | TX2_A_MARK, CAN0_TX_B_MARK, SSI_SDATA7_MARK, | |
458 | HSPI_TX0_B_MARK, RX2_A_MARK, CAN0_RX_B_MARK, | |
459 | ||
460 | /* IPSR6 */ | |
461 | SSI_SCK6_MARK, HSPI_RX2_A_MARK, FMCLK_B_MARK, | |
462 | CAN1_TX_B_MARK, SSI_WS6_MARK, HSPI_CLK2_A_MARK, | |
463 | BPFCLK_B_MARK, CAN1_RX_B_MARK, SSI_SDATA6_MARK, | |
464 | HSPI_TX2_A_MARK, FMIN_B_MARK, SSI_SCK5_MARK, | |
465 | RX4_C_MARK, SSI_WS5_MARK, TX4_C_MARK, SSI_SDATA5_MARK, | |
466 | RX0_D_MARK, SSI_WS34_MARK, ARM_TRACEDATA_8_MARK, | |
467 | SSI_SDATA4_MARK, SSI_WS2_A_MARK, ARM_TRACEDATA_9_MARK, | |
468 | SSI_SDATA3_MARK, ARM_TRACEDATA_10_MARK, | |
469 | SSI_SCK012_MARK, ARM_TRACEDATA_11_MARK, | |
470 | TX0_D_MARK, SSI_WS012_MARK, ARM_TRACEDATA_12_MARK, | |
471 | SSI_SDATA2_MARK, HSPI_CS2_A_MARK, | |
472 | ARM_TRACEDATA_13_MARK, SDA1_A_MARK, SSI_SDATA1_MARK, | |
473 | ARM_TRACEDATA_14_MARK, SCL1_A_MARK, SCK2_A_MARK, | |
474 | SSI_SDATA0_MARK, ARM_TRACEDATA_15_MARK, | |
475 | SD0_CLK_MARK, SUB_TDO_MARK, SD0_CMD_MARK, SUB_TRST_MARK, | |
476 | SD0_DAT0_MARK, SUB_TMS_MARK, SD0_DAT1_MARK, SUB_TCK_MARK, | |
477 | SD0_DAT2_MARK, SUB_TDI_MARK, | |
478 | ||
479 | /* IPSR7 */ | |
480 | SD0_DAT3_MARK, IRQ1_B_MARK, SD0_CD_MARK, TX5_A_MARK, | |
481 | SD0_WP_MARK, RX5_A_MARK, VI1_CLKENB_MARK, | |
482 | HSPI_CLK0_A_MARK, HTX1_A_MARK, RTS1_C_MARK, VI1_FIELD_MARK, | |
483 | HSPI_CS0_A_MARK, HRX1_A_MARK, SCK1_C_MARK, VI1_HSYNC_MARK, | |
484 | HSPI_RX0_A_MARK, HRTS1_A_MARK, FMCLK_A_MARK, RX1_C_MARK, | |
485 | VI1_VSYNC_MARK, HSPI_TX0_MARK, HCTS1_A_MARK, BPFCLK_A_MARK, | |
486 | TX1_C_MARK, TCLK0_MARK, HSCK1_A_MARK, FMIN_A_MARK, | |
487 | IRQ2_C_MARK, CTS1_C_MARK, SPEEDIN_MARK, VI0_CLK_MARK, | |
488 | CAN_CLK_A_MARK, VI0_CLKENB_MARK, SD2_DAT2_B_MARK, | |
489 | VI1_DATA0_MARK, DU1_DG6_MARK, HSPI_RX1_A_MARK, | |
490 | RX4_B_MARK, VI0_FIELD_MARK, SD2_DAT3_B_MARK, | |
491 | VI0_R3_C_MARK, VI1_DATA1_MARK, DU1_DG7_MARK, HSPI_CLK1_A_MARK, | |
492 | TX4_B_MARK, VI0_HSYNC_MARK, SD2_CD_B_MARK, VI1_DATA2_MARK, | |
493 | DU1_DR2_MARK, HSPI_CS1_A_MARK, RX3_B_MARK, | |
494 | ||
495 | /* IPSR8 */ | |
496 | VI0_VSYNC_MARK, SD2_WP_B_MARK, VI1_DATA3_MARK, DU1_DR3_MARK, | |
497 | HSPI_TX1_A_MARK, TX3_B_MARK, VI0_DATA0_VI0_B0_MARK, | |
498 | DU1_DG2_MARK, IRQ2_B_MARK, RX3_D_MARK, VI0_DATA1_VI0_B1_MARK, | |
499 | DU1_DG3_MARK, IRQ3_B_MARK, TX3_D_MARK, VI0_DATA2_VI0_B2_MARK, | |
500 | DU1_DG4_MARK, RX0_C_MARK, VI0_DATA3_VI0_B3_MARK, | |
501 | DU1_DG5_MARK, TX1_A_MARK, TX0_C_MARK, VI0_DATA4_VI0_B4_MARK, | |
502 | DU1_DB2_MARK, RX1_A_MARK, VI0_DATA5_VI0_B5_MARK, | |
503 | DU1_DB3_MARK, SCK1_A_MARK, PWM4_MARK, HSCK1_B_MARK, | |
504 | VI0_DATA6_VI0_G0_MARK, DU1_DB4_MARK, CTS1_A_MARK, | |
505 | PWM5_MARK, VI0_DATA7_VI0_G1_MARK, DU1_DB5_MARK, | |
506 | RTS1_A_MARK, VI0_G2_MARK, SD2_CLK_B_MARK, VI1_DATA4_MARK, | |
507 | DU1_DR4_MARK, HTX1_B_MARK, VI0_G3_MARK, SD2_CMD_B_MARK, | |
508 | VI1_DATA5_MARK, DU1_DR5_MARK, HRX1_B_MARK, | |
509 | ||
510 | /* IPSR9 */ | |
511 | VI0_G4_MARK, SD2_DAT0_B_MARK, VI1_DATA6_MARK, | |
512 | DU1_DR6_MARK, HRTS1_B_MARK, VI0_G5_MARK, SD2_DAT1_B_MARK, | |
513 | VI1_DATA7_MARK, DU1_DR7_MARK, HCTS1_B_MARK, VI0_R0_A_MARK, | |
514 | VI1_CLK_MARK, ETH_REF_CLK_MARK, DU1_DOTCLKIN_MARK, | |
515 | VI0_R1_A_MARK, VI1_DATA8_MARK, DU1_DB6_MARK, ETH_TXD0_MARK, | |
516 | PWM2_MARK, TCLK1_MARK, VI0_R2_A_MARK, VI1_DATA9_MARK, | |
517 | DU1_DB7_MARK, ETH_TXD1_MARK, PWM3_MARK, VI0_R3_A_MARK, | |
518 | ETH_CRS_DV_MARK, IECLK_MARK, SCK2_C_MARK, | |
519 | VI0_R4_A_MARK, ETH_TX_EN_MARK, IETX_MARK, | |
520 | TX2_C_MARK, VI0_R5_A_MARK, ETH_RX_ER_MARK, FMCLK_C_MARK, | |
521 | IERX_MARK, RX2_C_MARK, VI1_DATA10_A_MARK, | |
522 | DU1_DOTCLKOUT_MARK, ETH_RXD0_MARK, | |
523 | BPFCLK_C_MARK, TX2_D_MARK, SDA2_C_MARK, VI1_DATA11_A_MARK, | |
524 | DU1_EXHSYNC_DU1_HSYNC_MARK, ETH_RXD1_MARK, FMIN_C_MARK, | |
525 | RX2_D_MARK, SCL2_C_MARK, | |
526 | ||
527 | /* IPSR10 */ | |
528 | SD2_CLK_A_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, ATARD1_MARK, | |
529 | ETH_MDC_MARK, SDA1_B_MARK, SD2_CMD_A_MARK, | |
530 | DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, ATAWR1_MARK, | |
531 | ETH_MDIO_MARK, SCL1_B_MARK, SD2_DAT0_A_MARK, | |
532 | DU1_DISP_MARK, ATACS01_MARK, DREQ1_B_MARK, ETH_LINK_MARK, | |
533 | CAN1_RX_A_MARK, SD2_DAT1_A_MARK, DU1_CDE_MARK, | |
534 | ATACS11_MARK, DACK1_B_MARK, ETH_MAGIC_MARK, CAN1_TX_A_MARK, | |
535 | PWM6_MARK, SD2_DAT2_A_MARK, VI1_DATA12_MARK, | |
536 | DREQ2_B_MARK, ATADIR1_MARK, HSPI_CLK2_B_MARK, | |
537 | GPSCLK_B_MARK, SD2_DAT3_A_MARK, VI1_DATA13_MARK, | |
538 | DACK2_B_MARK, ATAG1_MARK, HSPI_CS2_B_MARK, | |
539 | GPSIN_B_MARK, SD2_CD_A_MARK, VI1_DATA14_MARK, | |
540 | EX_WAIT1_B_MARK, DREQ0_B_MARK, HSPI_RX2_B_MARK, | |
541 | REMOCON_A_MARK, SD2_WP_A_MARK, VI1_DATA15_MARK, | |
542 | EX_WAIT2_B_MARK, DACK0_B_MARK, | |
543 | HSPI_TX2_B_MARK, CAN_CLK_C_MARK, | |
544 | ||
545 | PINMUX_MARK_END, | |
546 | }; | |
547 | ||
533743dc | 548 | static const u16 pinmux_data[] = { |
87f8c988 KM |
549 | PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ |
550 | ||
79e72c53 GU |
551 | PINMUX_SINGLE(PENC0), |
552 | PINMUX_SINGLE(PENC1), | |
553 | PINMUX_SINGLE(A1), | |
554 | PINMUX_SINGLE(A2), | |
555 | PINMUX_SINGLE(A3), | |
556 | PINMUX_SINGLE(WE0), | |
557 | PINMUX_SINGLE(AUDIO_CLKA), | |
558 | PINMUX_SINGLE(AUDIO_CLKB), | |
559 | PINMUX_SINGLE(SSI_SCK34), | |
560 | PINMUX_SINGLE(AVS1), | |
561 | PINMUX_SINGLE(AVS2), | |
87f8c988 KM |
562 | |
563 | /* IPSR0 */ | |
e01678e3 GU |
564 | PINMUX_IPSR_GPSR(IP0_1_0, PRESETOUT), |
565 | PINMUX_IPSR_GPSR(IP0_1_0, PWM1), | |
87f8c988 | 566 | |
e01678e3 GU |
567 | PINMUX_IPSR_GPSR(IP0_4_2, AUDATA0), |
568 | PINMUX_IPSR_GPSR(IP0_4_2, ARM_TRACEDATA_0), | |
87f8c988 | 569 | PINMUX_IPSR_MSEL(IP0_4_2, GPSCLK_C, SEL_GPS_C), |
e01678e3 GU |
570 | PINMUX_IPSR_GPSR(IP0_4_2, USB_OVC0), |
571 | PINMUX_IPSR_GPSR(IP0_4_2, TX2_E), | |
87f8c988 KM |
572 | PINMUX_IPSR_MSEL(IP0_4_2, SDA2_B, SEL_I2C2_B), |
573 | ||
e01678e3 GU |
574 | PINMUX_IPSR_GPSR(IP0_7_5, AUDATA1), |
575 | PINMUX_IPSR_GPSR(IP0_7_5, ARM_TRACEDATA_1), | |
87f8c988 | 576 | PINMUX_IPSR_MSEL(IP0_7_5, GPSIN_C, SEL_GPS_C), |
e01678e3 | 577 | PINMUX_IPSR_GPSR(IP0_7_5, USB_OVC1), |
87f8c988 KM |
578 | PINMUX_IPSR_MSEL(IP0_7_5, RX2_E, SEL_SCIF2_E), |
579 | PINMUX_IPSR_MSEL(IP0_7_5, SCL2_B, SEL_I2C2_B), | |
580 | ||
581 | PINMUX_IPSR_MSEL(IP0_11_8, SD1_DAT2_A, SEL_SD1_A), | |
e01678e3 GU |
582 | PINMUX_IPSR_GPSR(IP0_11_8, MMC_D2), |
583 | PINMUX_IPSR_GPSR(IP0_11_8, BS), | |
584 | PINMUX_IPSR_GPSR(IP0_11_8, ATADIR0_A), | |
585 | PINMUX_IPSR_GPSR(IP0_11_8, SDSELF_A), | |
586 | PINMUX_IPSR_GPSR(IP0_11_8, PWM4_B), | |
87f8c988 KM |
587 | |
588 | PINMUX_IPSR_MSEL(IP0_14_12, SD1_DAT3_A, SEL_SD1_A), | |
e01678e3 GU |
589 | PINMUX_IPSR_GPSR(IP0_14_12, MMC_D3), |
590 | PINMUX_IPSR_GPSR(IP0_14_12, A0), | |
591 | PINMUX_IPSR_GPSR(IP0_14_12, ATAG0_A), | |
87f8c988 KM |
592 | PINMUX_IPSR_MSEL(IP0_14_12, REMOCON_B, SEL_REMOCON_B), |
593 | ||
e01678e3 GU |
594 | PINMUX_IPSR_GPSR(IP0_15, A4), |
595 | PINMUX_IPSR_GPSR(IP0_16, A5), | |
596 | PINMUX_IPSR_GPSR(IP0_17, A6), | |
597 | PINMUX_IPSR_GPSR(IP0_18, A7), | |
598 | PINMUX_IPSR_GPSR(IP0_19, A8), | |
599 | PINMUX_IPSR_GPSR(IP0_20, A9), | |
600 | PINMUX_IPSR_GPSR(IP0_21, A10), | |
601 | PINMUX_IPSR_GPSR(IP0_22, A11), | |
602 | PINMUX_IPSR_GPSR(IP0_23, A12), | |
603 | PINMUX_IPSR_GPSR(IP0_24, A13), | |
604 | PINMUX_IPSR_GPSR(IP0_25, A14), | |
605 | PINMUX_IPSR_GPSR(IP0_26, A15), | |
606 | PINMUX_IPSR_GPSR(IP0_27, A16), | |
607 | PINMUX_IPSR_GPSR(IP0_28, A17), | |
608 | PINMUX_IPSR_GPSR(IP0_29, A18), | |
609 | PINMUX_IPSR_GPSR(IP0_30, A19), | |
87f8c988 KM |
610 | |
611 | /* IPSR1 */ | |
e01678e3 | 612 | PINMUX_IPSR_GPSR(IP1_0, A20), |
87f8c988 KM |
613 | PINMUX_IPSR_MSEL(IP1_0, HSPI_CS1_B, SEL_HSPI1_B), |
614 | ||
e01678e3 | 615 | PINMUX_IPSR_GPSR(IP1_1, A21), |
87f8c988 KM |
616 | PINMUX_IPSR_MSEL(IP1_1, HSPI_CLK1_B, SEL_HSPI1_B), |
617 | ||
e01678e3 | 618 | PINMUX_IPSR_GPSR(IP1_4_2, A22), |
87f8c988 KM |
619 | PINMUX_IPSR_MSEL(IP1_4_2, HRTS0_B, SEL_HSCIF0_B), |
620 | PINMUX_IPSR_MSEL(IP1_4_2, RX2_B, SEL_SCIF2_B), | |
621 | PINMUX_IPSR_MSEL(IP1_4_2, DREQ2_A, SEL_DREQ2_A), | |
622 | ||
e01678e3 GU |
623 | PINMUX_IPSR_GPSR(IP1_7_5, A23), |
624 | PINMUX_IPSR_GPSR(IP1_7_5, HTX0_B), | |
625 | PINMUX_IPSR_GPSR(IP1_7_5, TX2_B), | |
626 | PINMUX_IPSR_GPSR(IP1_7_5, DACK2_A), | |
87f8c988 KM |
627 | PINMUX_IPSR_MSEL(IP1_7_5, TS_SDEN0_A, SEL_TSIF0_A), |
628 | ||
629 | PINMUX_IPSR_MSEL(IP1_10_8, SD1_CD_A, SEL_SD1_A), | |
e01678e3 GU |
630 | PINMUX_IPSR_GPSR(IP1_10_8, MMC_D6), |
631 | PINMUX_IPSR_GPSR(IP1_10_8, A24), | |
87f8c988 KM |
632 | PINMUX_IPSR_MSEL(IP1_10_8, DREQ1_A, SEL_DREQ1_A), |
633 | PINMUX_IPSR_MSEL(IP1_10_8, HRX0_B, SEL_HSCIF0_B), | |
634 | PINMUX_IPSR_MSEL(IP1_10_8, TS_SPSYNC0_A, SEL_TSIF0_A), | |
635 | ||
636 | PINMUX_IPSR_MSEL(IP1_14_11, SD1_WP_A, SEL_SD1_A), | |
e01678e3 GU |
637 | PINMUX_IPSR_GPSR(IP1_14_11, MMC_D7), |
638 | PINMUX_IPSR_GPSR(IP1_14_11, A25), | |
639 | PINMUX_IPSR_GPSR(IP1_14_11, DACK1_A), | |
87f8c988 KM |
640 | PINMUX_IPSR_MSEL(IP1_14_11, HCTS0_B, SEL_HSCIF0_B), |
641 | PINMUX_IPSR_MSEL(IP1_14_11, RX3_C, SEL_SCIF3_C), | |
642 | PINMUX_IPSR_MSEL(IP1_14_11, TS_SDAT0_A, SEL_TSIF0_A), | |
643 | ||
644 | PINMUX_IPSR_NOGP(IP1_16_15, CLKOUT), | |
645 | PINMUX_IPSR_NOGP(IP1_16_15, HSPI_TX1_B), | |
646 | PINMUX_IPSR_NOGP(IP1_16_15, PWM0_B), | |
647 | ||
648 | PINMUX_IPSR_NOGP(IP1_17, CS0), | |
649 | PINMUX_IPSR_NOGM(IP1_17, HSPI_RX1_B, SEL_HSPI1_B), | |
650 | ||
651 | PINMUX_IPSR_NOGM(IP1_20_18, SSI_SCK1_B, SEL_SSI1_B), | |
652 | PINMUX_IPSR_NOGP(IP1_20_18, ATAG0_B), | |
653 | PINMUX_IPSR_NOGP(IP1_20_18, CS1_A26), | |
654 | PINMUX_IPSR_NOGM(IP1_20_18, SDA2_A, SEL_I2C2_A), | |
655 | PINMUX_IPSR_NOGM(IP1_20_18, SCK2_B, SEL_SCIF2_B), | |
656 | ||
e01678e3 GU |
657 | PINMUX_IPSR_GPSR(IP1_23_21, MMC_D5), |
658 | PINMUX_IPSR_GPSR(IP1_23_21, ATADIR0_B), | |
659 | PINMUX_IPSR_GPSR(IP1_23_21, RD_WR), | |
87f8c988 | 660 | |
e01678e3 GU |
661 | PINMUX_IPSR_GPSR(IP1_24, WE1), |
662 | PINMUX_IPSR_GPSR(IP1_24, ATAWR0_B), | |
87f8c988 KM |
663 | |
664 | PINMUX_IPSR_MSEL(IP1_27_25, SSI_WS1_B, SEL_SSI1_B), | |
e01678e3 | 665 | PINMUX_IPSR_GPSR(IP1_27_25, EX_CS0), |
87f8c988 | 666 | PINMUX_IPSR_MSEL(IP1_27_25, SCL2_A, SEL_I2C2_A), |
e01678e3 | 667 | PINMUX_IPSR_GPSR(IP1_27_25, TX3_C), |
87f8c988 KM |
668 | PINMUX_IPSR_MSEL(IP1_27_25, TS_SCK0_A, SEL_TSIF0_A), |
669 | ||
e01678e3 GU |
670 | PINMUX_IPSR_GPSR(IP1_29_28, EX_CS1), |
671 | PINMUX_IPSR_GPSR(IP1_29_28, MMC_D4), | |
87f8c988 KM |
672 | |
673 | /* IPSR2 */ | |
e01678e3 GU |
674 | PINMUX_IPSR_GPSR(IP2_2_0, SD1_CLK_A), |
675 | PINMUX_IPSR_GPSR(IP2_2_0, MMC_CLK), | |
676 | PINMUX_IPSR_GPSR(IP2_2_0, ATACS00), | |
677 | PINMUX_IPSR_GPSR(IP2_2_0, EX_CS2), | |
87f8c988 KM |
678 | |
679 | PINMUX_IPSR_MSEL(IP2_5_3, SD1_CMD_A, SEL_SD1_A), | |
e01678e3 GU |
680 | PINMUX_IPSR_GPSR(IP2_5_3, MMC_CMD), |
681 | PINMUX_IPSR_GPSR(IP2_5_3, ATACS10), | |
682 | PINMUX_IPSR_GPSR(IP2_5_3, EX_CS3), | |
87f8c988 KM |
683 | |
684 | PINMUX_IPSR_MSEL(IP2_8_6, SD1_DAT0_A, SEL_SD1_A), | |
e01678e3 GU |
685 | PINMUX_IPSR_GPSR(IP2_8_6, MMC_D0), |
686 | PINMUX_IPSR_GPSR(IP2_8_6, ATARD0), | |
687 | PINMUX_IPSR_GPSR(IP2_8_6, EX_CS4), | |
87f8c988 KM |
688 | PINMUX_IPSR_MSEL(IP2_8_6, EX_WAIT1_A, SEL_WAIT1_A), |
689 | ||
690 | PINMUX_IPSR_MSEL(IP2_11_9, SD1_DAT1_A, SEL_SD1_A), | |
e01678e3 GU |
691 | PINMUX_IPSR_GPSR(IP2_11_9, MMC_D1), |
692 | PINMUX_IPSR_GPSR(IP2_11_9, ATAWR0_A), | |
693 | PINMUX_IPSR_GPSR(IP2_11_9, EX_CS5), | |
87f8c988 KM |
694 | PINMUX_IPSR_MSEL(IP2_11_9, EX_WAIT2_A, SEL_WAIT2_A), |
695 | ||
696 | PINMUX_IPSR_MSEL(IP2_13_12, DREQ0_A, SEL_DREQ0_A), | |
697 | PINMUX_IPSR_MSEL(IP2_13_12, RX3_A, SEL_SCIF3_A), | |
698 | ||
e01678e3 GU |
699 | PINMUX_IPSR_GPSR(IP2_16_14, DACK0), |
700 | PINMUX_IPSR_GPSR(IP2_16_14, TX3_A), | |
701 | PINMUX_IPSR_GPSR(IP2_16_14, DRACK0), | |
87f8c988 | 702 | |
e01678e3 GU |
703 | PINMUX_IPSR_GPSR(IP2_17, EX_WAIT0), |
704 | PINMUX_IPSR_GPSR(IP2_17, PWM0_C), | |
87f8c988 KM |
705 | |
706 | PINMUX_IPSR_NOGP(IP2_18, D0), | |
707 | PINMUX_IPSR_NOGP(IP2_19, D1), | |
708 | PINMUX_IPSR_NOGP(IP2_20, D2), | |
709 | PINMUX_IPSR_NOGP(IP2_21, D3), | |
710 | PINMUX_IPSR_NOGP(IP2_22, D4), | |
711 | PINMUX_IPSR_NOGP(IP2_23, D5), | |
712 | PINMUX_IPSR_NOGP(IP2_24, D6), | |
713 | PINMUX_IPSR_NOGP(IP2_25, D7), | |
714 | PINMUX_IPSR_NOGP(IP2_26, D8), | |
715 | PINMUX_IPSR_NOGP(IP2_27, D9), | |
716 | PINMUX_IPSR_NOGP(IP2_28, D10), | |
717 | PINMUX_IPSR_NOGP(IP2_29, D11), | |
718 | ||
e01678e3 GU |
719 | PINMUX_IPSR_GPSR(IP2_30, RD_WR_B), |
720 | PINMUX_IPSR_GPSR(IP2_30, IRQ0), | |
87f8c988 | 721 | |
e01678e3 | 722 | PINMUX_IPSR_GPSR(IP2_31, MLB_CLK), |
87f8c988 KM |
723 | PINMUX_IPSR_MSEL(IP2_31, IRQ1_A, SEL_IRQ1_A), |
724 | ||
725 | /* IPSR3 */ | |
e01678e3 | 726 | PINMUX_IPSR_GPSR(IP3_1_0, MLB_SIG), |
87f8c988 KM |
727 | PINMUX_IPSR_MSEL(IP3_1_0, RX5_B, SEL_SCIF5_B), |
728 | PINMUX_IPSR_MSEL(IP3_1_0, SDA3_A, SEL_I2C3_A), | |
729 | PINMUX_IPSR_MSEL(IP3_1_0, IRQ2_A, SEL_IRQ2_A), | |
730 | ||
e01678e3 GU |
731 | PINMUX_IPSR_GPSR(IP3_4_2, MLB_DAT), |
732 | PINMUX_IPSR_GPSR(IP3_4_2, TX5_B), | |
87f8c988 KM |
733 | PINMUX_IPSR_MSEL(IP3_4_2, SCL3_A, SEL_I2C3_A), |
734 | PINMUX_IPSR_MSEL(IP3_4_2, IRQ3_A, SEL_IRQ3_A), | |
e01678e3 | 735 | PINMUX_IPSR_GPSR(IP3_4_2, SDSELF_B), |
87f8c988 KM |
736 | |
737 | PINMUX_IPSR_MSEL(IP3_7_5, SD1_CMD_B, SEL_SD1_B), | |
e01678e3 GU |
738 | PINMUX_IPSR_GPSR(IP3_7_5, SCIF_CLK), |
739 | PINMUX_IPSR_GPSR(IP3_7_5, AUDIO_CLKOUT_B), | |
87f8c988 KM |
740 | PINMUX_IPSR_MSEL(IP3_7_5, CAN_CLK_B, SEL_CANCLK_B), |
741 | PINMUX_IPSR_MSEL(IP3_7_5, SDA3_B, SEL_I2C3_B), | |
742 | ||
e01678e3 GU |
743 | PINMUX_IPSR_GPSR(IP3_9_8, SD1_CLK_B), |
744 | PINMUX_IPSR_GPSR(IP3_9_8, HTX0_A), | |
745 | PINMUX_IPSR_GPSR(IP3_9_8, TX0_A), | |
87f8c988 KM |
746 | |
747 | PINMUX_IPSR_MSEL(IP3_12_10, SD1_DAT0_B, SEL_SD1_B), | |
748 | PINMUX_IPSR_MSEL(IP3_12_10, HRX0_A, SEL_HSCIF0_A), | |
749 | PINMUX_IPSR_MSEL(IP3_12_10, RX0_A, SEL_SCIF0_A), | |
750 | ||
751 | PINMUX_IPSR_MSEL(IP3_15_13, SD1_DAT1_B, SEL_SD1_B), | |
752 | PINMUX_IPSR_MSEL(IP3_15_13, HSCK0, SEL_HSCIF0_A), | |
e01678e3 | 753 | PINMUX_IPSR_GPSR(IP3_15_13, SCK0), |
87f8c988 KM |
754 | PINMUX_IPSR_MSEL(IP3_15_13, SCL3_B, SEL_I2C3_B), |
755 | ||
756 | PINMUX_IPSR_MSEL(IP3_18_16, SD1_DAT2_B, SEL_SD1_B), | |
757 | PINMUX_IPSR_MSEL(IP3_18_16, HCTS0_A, SEL_HSCIF0_A), | |
e01678e3 | 758 | PINMUX_IPSR_GPSR(IP3_18_16, CTS0), |
87f8c988 KM |
759 | |
760 | PINMUX_IPSR_MSEL(IP3_20_19, SD1_DAT3_B, SEL_SD1_B), | |
761 | PINMUX_IPSR_MSEL(IP3_20_19, HRTS0_A, SEL_HSCIF0_A), | |
e01678e3 | 762 | PINMUX_IPSR_GPSR(IP3_20_19, RTS0), |
87f8c988 | 763 | |
e01678e3 GU |
764 | PINMUX_IPSR_GPSR(IP3_23_21, SSI_SCK4), |
765 | PINMUX_IPSR_GPSR(IP3_23_21, DU0_DR0), | |
766 | PINMUX_IPSR_GPSR(IP3_23_21, LCDOUT0), | |
767 | PINMUX_IPSR_GPSR(IP3_23_21, AUDATA2), | |
768 | PINMUX_IPSR_GPSR(IP3_23_21, ARM_TRACEDATA_2), | |
87f8c988 | 769 | PINMUX_IPSR_MSEL(IP3_23_21, SDA3_C, SEL_I2C3_C), |
e01678e3 | 770 | PINMUX_IPSR_GPSR(IP3_23_21, ADICHS1), |
87f8c988 KM |
771 | PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN0_B, SEL_TSIF0_B), |
772 | ||
e01678e3 GU |
773 | PINMUX_IPSR_GPSR(IP3_26_24, SSI_WS4), |
774 | PINMUX_IPSR_GPSR(IP3_26_24, DU0_DR1), | |
775 | PINMUX_IPSR_GPSR(IP3_26_24, LCDOUT1), | |
776 | PINMUX_IPSR_GPSR(IP3_26_24, AUDATA3), | |
777 | PINMUX_IPSR_GPSR(IP3_26_24, ARM_TRACEDATA_3), | |
87f8c988 | 778 | PINMUX_IPSR_MSEL(IP3_26_24, SCL3_C, SEL_I2C3_C), |
e01678e3 | 779 | PINMUX_IPSR_GPSR(IP3_26_24, ADICHS2), |
87f8c988 KM |
780 | PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC0_B, SEL_TSIF0_B), |
781 | ||
e01678e3 GU |
782 | PINMUX_IPSR_GPSR(IP3_27, DU0_DR2), |
783 | PINMUX_IPSR_GPSR(IP3_27, LCDOUT2), | |
87f8c988 | 784 | |
e01678e3 GU |
785 | PINMUX_IPSR_GPSR(IP3_28, DU0_DR3), |
786 | PINMUX_IPSR_GPSR(IP3_28, LCDOUT3), | |
87f8c988 | 787 | |
e01678e3 GU |
788 | PINMUX_IPSR_GPSR(IP3_29, DU0_DR4), |
789 | PINMUX_IPSR_GPSR(IP3_29, LCDOUT4), | |
87f8c988 | 790 | |
e01678e3 GU |
791 | PINMUX_IPSR_GPSR(IP3_30, DU0_DR5), |
792 | PINMUX_IPSR_GPSR(IP3_30, LCDOUT5), | |
87f8c988 | 793 | |
e01678e3 GU |
794 | PINMUX_IPSR_GPSR(IP3_31, DU0_DR6), |
795 | PINMUX_IPSR_GPSR(IP3_31, LCDOUT6), | |
87f8c988 KM |
796 | |
797 | /* IPSR4 */ | |
e01678e3 GU |
798 | PINMUX_IPSR_GPSR(IP4_0, DU0_DR7), |
799 | PINMUX_IPSR_GPSR(IP4_0, LCDOUT7), | |
800 | ||
801 | PINMUX_IPSR_GPSR(IP4_3_1, DU0_DG0), | |
802 | PINMUX_IPSR_GPSR(IP4_3_1, LCDOUT8), | |
803 | PINMUX_IPSR_GPSR(IP4_3_1, AUDATA4), | |
804 | PINMUX_IPSR_GPSR(IP4_3_1, ARM_TRACEDATA_4), | |
805 | PINMUX_IPSR_GPSR(IP4_3_1, TX1_D), | |
806 | PINMUX_IPSR_GPSR(IP4_3_1, CAN0_TX_A), | |
807 | PINMUX_IPSR_GPSR(IP4_3_1, ADICHS0), | |
808 | ||
809 | PINMUX_IPSR_GPSR(IP4_6_4, DU0_DG1), | |
810 | PINMUX_IPSR_GPSR(IP4_6_4, LCDOUT9), | |
811 | PINMUX_IPSR_GPSR(IP4_6_4, AUDATA5), | |
812 | PINMUX_IPSR_GPSR(IP4_6_4, ARM_TRACEDATA_5), | |
87f8c988 KM |
813 | PINMUX_IPSR_MSEL(IP4_6_4, RX1_D, SEL_SCIF1_D), |
814 | PINMUX_IPSR_MSEL(IP4_6_4, CAN0_RX_A, SEL_CAN0_A), | |
e01678e3 | 815 | PINMUX_IPSR_GPSR(IP4_6_4, ADIDATA), |
87f8c988 | 816 | |
e01678e3 GU |
817 | PINMUX_IPSR_GPSR(IP4_7, DU0_DG2), |
818 | PINMUX_IPSR_GPSR(IP4_7, LCDOUT10), | |
87f8c988 | 819 | |
e01678e3 GU |
820 | PINMUX_IPSR_GPSR(IP4_8, DU0_DG3), |
821 | PINMUX_IPSR_GPSR(IP4_8, LCDOUT11), | |
87f8c988 | 822 | |
e01678e3 GU |
823 | PINMUX_IPSR_GPSR(IP4_10_9, DU0_DG4), |
824 | PINMUX_IPSR_GPSR(IP4_10_9, LCDOUT12), | |
87f8c988 KM |
825 | PINMUX_IPSR_MSEL(IP4_10_9, RX0_B, SEL_SCIF0_B), |
826 | ||
e01678e3 GU |
827 | PINMUX_IPSR_GPSR(IP4_12_11, DU0_DG5), |
828 | PINMUX_IPSR_GPSR(IP4_12_11, LCDOUT13), | |
829 | PINMUX_IPSR_GPSR(IP4_12_11, TX0_B), | |
87f8c988 | 830 | |
e01678e3 GU |
831 | PINMUX_IPSR_GPSR(IP4_14_13, DU0_DG6), |
832 | PINMUX_IPSR_GPSR(IP4_14_13, LCDOUT14), | |
87f8c988 KM |
833 | PINMUX_IPSR_MSEL(IP4_14_13, RX4_A, SEL_SCIF4_A), |
834 | ||
e01678e3 GU |
835 | PINMUX_IPSR_GPSR(IP4_16_15, DU0_DG7), |
836 | PINMUX_IPSR_GPSR(IP4_16_15, LCDOUT15), | |
837 | PINMUX_IPSR_GPSR(IP4_16_15, TX4_A), | |
87f8c988 KM |
838 | |
839 | PINMUX_IPSR_MSEL(IP4_20_17, SSI_SCK2_B, SEL_SSI2_B), | |
840 | PINMUX_DATA(VI0_R0_B_MARK, FN_IP4_20_17, FN_VI0_R0_B, FN_SEL_VI0_B), /* see sel_vi0 */ | |
841 | PINMUX_DATA(VI0_R0_D_MARK, FN_IP4_20_17, FN_VI0_R0_B, FN_SEL_VI0_D), /* see sel_vi0 */ | |
e01678e3 GU |
842 | PINMUX_IPSR_GPSR(IP4_20_17, DU0_DB0), |
843 | PINMUX_IPSR_GPSR(IP4_20_17, LCDOUT16), | |
844 | PINMUX_IPSR_GPSR(IP4_20_17, AUDATA6), | |
845 | PINMUX_IPSR_GPSR(IP4_20_17, ARM_TRACEDATA_6), | |
87f8c988 | 846 | PINMUX_IPSR_MSEL(IP4_20_17, GPSCLK_A, SEL_GPS_A), |
e01678e3 GU |
847 | PINMUX_IPSR_GPSR(IP4_20_17, PWM0_A), |
848 | PINMUX_IPSR_GPSR(IP4_20_17, ADICLK), | |
87f8c988 KM |
849 | PINMUX_IPSR_MSEL(IP4_20_17, TS_SDAT0_B, SEL_TSIF0_B), |
850 | ||
e01678e3 | 851 | PINMUX_IPSR_GPSR(IP4_24_21, AUDIO_CLKC), |
87f8c988 KM |
852 | PINMUX_DATA(VI0_R1_B_MARK, FN_IP4_24_21, FN_VI0_R1_B, FN_SEL_VI0_B), /* see sel_vi0 */ |
853 | PINMUX_DATA(VI0_R1_D_MARK, FN_IP4_24_21, FN_VI0_R1_B, FN_SEL_VI0_D), /* see sel_vi0 */ | |
e01678e3 GU |
854 | PINMUX_IPSR_GPSR(IP4_24_21, DU0_DB1), |
855 | PINMUX_IPSR_GPSR(IP4_24_21, LCDOUT17), | |
856 | PINMUX_IPSR_GPSR(IP4_24_21, AUDATA7), | |
857 | PINMUX_IPSR_GPSR(IP4_24_21, ARM_TRACEDATA_7), | |
87f8c988 | 858 | PINMUX_IPSR_MSEL(IP4_24_21, GPSIN_A, SEL_GPS_A), |
e01678e3 | 859 | PINMUX_IPSR_GPSR(IP4_24_21, ADICS_SAMP), |
87f8c988 KM |
860 | PINMUX_IPSR_MSEL(IP4_24_21, TS_SCK0_B, SEL_TSIF0_B), |
861 | ||
862 | PINMUX_DATA(VI0_R2_B_MARK, FN_IP4_26_25, FN_VI0_R2_B, FN_SEL_VI0_B), /* see sel_vi0 */ | |
863 | PINMUX_DATA(VI0_R2_D_MARK, FN_IP4_26_25, FN_VI0_R2_B, FN_SEL_VI0_D), /* see sel_vi0 */ | |
e01678e3 GU |
864 | PINMUX_IPSR_GPSR(IP4_26_25, DU0_DB2), |
865 | PINMUX_IPSR_GPSR(IP4_26_25, LCDOUT18), | |
87f8c988 KM |
866 | |
867 | PINMUX_IPSR_MSEL(IP4_28_27, VI0_R3_B, SEL_VI0_B), | |
e01678e3 GU |
868 | PINMUX_IPSR_GPSR(IP4_28_27, DU0_DB3), |
869 | PINMUX_IPSR_GPSR(IP4_28_27, LCDOUT19), | |
87f8c988 KM |
870 | |
871 | PINMUX_DATA(VI0_R4_B_MARK, FN_IP4_30_29, FN_VI0_R4_B, FN_SEL_VI0_B), /* see sel_vi0 */ | |
872 | PINMUX_DATA(VI0_R4_D_MARK, FN_IP4_30_29, FN_VI0_R4_B, FN_SEL_VI0_D), /* see sel_vi0 */ | |
e01678e3 GU |
873 | PINMUX_IPSR_GPSR(IP4_30_29, DU0_DB4), |
874 | PINMUX_IPSR_GPSR(IP4_30_29, LCDOUT20), | |
87f8c988 KM |
875 | |
876 | /* IPSR5 */ | |
877 | PINMUX_DATA(VI0_R5_B_MARK, FN_IP5_1_0, FN_VI0_R5_B, FN_SEL_VI0_B), /* see sel_vi0 */ | |
878 | PINMUX_DATA(VI0_R5_D_MARK, FN_IP5_1_0, FN_VI0_R5_B, FN_SEL_VI0_D), /* see sel_vi0 */ | |
e01678e3 GU |
879 | PINMUX_IPSR_GPSR(IP5_1_0, DU0_DB5), |
880 | PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT21), | |
87f8c988 KM |
881 | |
882 | PINMUX_IPSR_MSEL(IP5_3_2, VI1_DATA10_B, SEL_VI1_B), | |
e01678e3 GU |
883 | PINMUX_IPSR_GPSR(IP5_3_2, DU0_DB6), |
884 | PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT22), | |
87f8c988 KM |
885 | |
886 | PINMUX_IPSR_MSEL(IP5_5_4, VI1_DATA11_B, SEL_VI1_B), | |
e01678e3 GU |
887 | PINMUX_IPSR_GPSR(IP5_5_4, DU0_DB7), |
888 | PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT23), | |
87f8c988 | 889 | |
e01678e3 GU |
890 | PINMUX_IPSR_GPSR(IP5_6, DU0_DOTCLKIN), |
891 | PINMUX_IPSR_GPSR(IP5_6, QSTVA_QVS), | |
87f8c988 | 892 | |
e01678e3 GU |
893 | PINMUX_IPSR_GPSR(IP5_7, DU0_DOTCLKO_UT0), |
894 | PINMUX_IPSR_GPSR(IP5_7, QCLK), | |
87f8c988 | 895 | |
e01678e3 GU |
896 | PINMUX_IPSR_GPSR(IP5_9_8, DU0_DOTCLKO_UT1), |
897 | PINMUX_IPSR_GPSR(IP5_9_8, QSTVB_QVE), | |
898 | PINMUX_IPSR_GPSR(IP5_9_8, AUDIO_CLKOUT_A), | |
87f8c988 KM |
899 | PINMUX_IPSR_MSEL(IP5_9_8, REMOCON_C, SEL_REMOCON_C), |
900 | ||
901 | PINMUX_IPSR_MSEL(IP5_11_10, SSI_WS2_B, SEL_SSI2_B), | |
e01678e3 GU |
902 | PINMUX_IPSR_GPSR(IP5_11_10, DU0_EXHSYNC_DU0_HSYNC), |
903 | PINMUX_IPSR_GPSR(IP5_11_10, QSTH_QHS), | |
87f8c988 | 904 | |
e01678e3 GU |
905 | PINMUX_IPSR_GPSR(IP5_12, DU0_EXVSYNC_DU0_VSYNC), |
906 | PINMUX_IPSR_GPSR(IP5_12, QSTB_QHE), | |
87f8c988 | 907 | |
e01678e3 GU |
908 | PINMUX_IPSR_GPSR(IP5_14_13, DU0_EXODDF_DU0_ODDF_DISP_CDE), |
909 | PINMUX_IPSR_GPSR(IP5_14_13, QCPV_QDE), | |
87f8c988 KM |
910 | PINMUX_IPSR_MSEL(IP5_14_13, FMCLK_D, SEL_FM_D), |
911 | ||
912 | PINMUX_IPSR_MSEL(IP5_17_15, SSI_SCK1_A, SEL_SSI1_A), | |
e01678e3 GU |
913 | PINMUX_IPSR_GPSR(IP5_17_15, DU0_DISP), |
914 | PINMUX_IPSR_GPSR(IP5_17_15, QPOLA), | |
915 | PINMUX_IPSR_GPSR(IP5_17_15, AUDCK), | |
916 | PINMUX_IPSR_GPSR(IP5_17_15, ARM_TRACECLK), | |
917 | PINMUX_IPSR_GPSR(IP5_17_15, BPFCLK_D), | |
87f8c988 KM |
918 | |
919 | PINMUX_IPSR_MSEL(IP5_20_18, SSI_WS1_A, SEL_SSI1_A), | |
e01678e3 GU |
920 | PINMUX_IPSR_GPSR(IP5_20_18, DU0_CDE), |
921 | PINMUX_IPSR_GPSR(IP5_20_18, QPOLB), | |
922 | PINMUX_IPSR_GPSR(IP5_20_18, AUDSYNC), | |
923 | PINMUX_IPSR_GPSR(IP5_20_18, ARM_TRACECTL), | |
87f8c988 KM |
924 | PINMUX_IPSR_MSEL(IP5_20_18, FMIN_D, SEL_FM_D), |
925 | ||
926 | PINMUX_IPSR_MSEL(IP5_22_21, SD1_CD_B, SEL_SD1_B), | |
e01678e3 | 927 | PINMUX_IPSR_GPSR(IP5_22_21, SSI_SCK78), |
87f8c988 | 928 | PINMUX_IPSR_MSEL(IP5_22_21, HSPI_RX0_B, SEL_HSPI0_B), |
e01678e3 | 929 | PINMUX_IPSR_GPSR(IP5_22_21, TX1_B), |
87f8c988 KM |
930 | |
931 | PINMUX_IPSR_MSEL(IP5_25_23, SD1_WP_B, SEL_SD1_B), | |
e01678e3 | 932 | PINMUX_IPSR_GPSR(IP5_25_23, SSI_WS78), |
87f8c988 KM |
933 | PINMUX_IPSR_MSEL(IP5_25_23, HSPI_CLK0_B, SEL_HSPI0_B), |
934 | PINMUX_IPSR_MSEL(IP5_25_23, RX1_B, SEL_SCIF1_B), | |
935 | PINMUX_IPSR_MSEL(IP5_25_23, CAN_CLK_D, SEL_CANCLK_D), | |
936 | ||
e01678e3 | 937 | PINMUX_IPSR_GPSR(IP5_28_26, SSI_SDATA8), |
87f8c988 KM |
938 | PINMUX_IPSR_MSEL(IP5_28_26, SSI_SCK2_A, SEL_SSI2_A), |
939 | PINMUX_IPSR_MSEL(IP5_28_26, HSPI_CS0_B, SEL_HSPI0_B), | |
e01678e3 GU |
940 | PINMUX_IPSR_GPSR(IP5_28_26, TX2_A), |
941 | PINMUX_IPSR_GPSR(IP5_28_26, CAN0_TX_B), | |
87f8c988 | 942 | |
e01678e3 GU |
943 | PINMUX_IPSR_GPSR(IP5_30_29, SSI_SDATA7), |
944 | PINMUX_IPSR_GPSR(IP5_30_29, HSPI_TX0_B), | |
87f8c988 KM |
945 | PINMUX_IPSR_MSEL(IP5_30_29, RX2_A, SEL_SCIF2_A), |
946 | PINMUX_IPSR_MSEL(IP5_30_29, CAN0_RX_B, SEL_CAN0_B), | |
947 | ||
948 | /* IPSR6 */ | |
e01678e3 | 949 | PINMUX_IPSR_GPSR(IP6_1_0, SSI_SCK6), |
87f8c988 KM |
950 | PINMUX_IPSR_MSEL(IP6_1_0, HSPI_RX2_A, SEL_HSPI2_A), |
951 | PINMUX_IPSR_MSEL(IP6_1_0, FMCLK_B, SEL_FM_B), | |
e01678e3 | 952 | PINMUX_IPSR_GPSR(IP6_1_0, CAN1_TX_B), |
87f8c988 | 953 | |
e01678e3 | 954 | PINMUX_IPSR_GPSR(IP6_4_2, SSI_WS6), |
87f8c988 | 955 | PINMUX_IPSR_MSEL(IP6_4_2, HSPI_CLK2_A, SEL_HSPI2_A), |
e01678e3 | 956 | PINMUX_IPSR_GPSR(IP6_4_2, BPFCLK_B), |
87f8c988 KM |
957 | PINMUX_IPSR_MSEL(IP6_4_2, CAN1_RX_B, SEL_CAN1_B), |
958 | ||
e01678e3 GU |
959 | PINMUX_IPSR_GPSR(IP6_6_5, SSI_SDATA6), |
960 | PINMUX_IPSR_GPSR(IP6_6_5, HSPI_TX2_A), | |
87f8c988 KM |
961 | PINMUX_IPSR_MSEL(IP6_6_5, FMIN_B, SEL_FM_B), |
962 | ||
e01678e3 | 963 | PINMUX_IPSR_GPSR(IP6_7, SSI_SCK5), |
87f8c988 KM |
964 | PINMUX_IPSR_MSEL(IP6_7, RX4_C, SEL_SCIF4_C), |
965 | ||
e01678e3 GU |
966 | PINMUX_IPSR_GPSR(IP6_8, SSI_WS5), |
967 | PINMUX_IPSR_GPSR(IP6_8, TX4_C), | |
87f8c988 | 968 | |
e01678e3 | 969 | PINMUX_IPSR_GPSR(IP6_9, SSI_SDATA5), |
87f8c988 KM |
970 | PINMUX_IPSR_MSEL(IP6_9, RX0_D, SEL_SCIF0_D), |
971 | ||
e01678e3 GU |
972 | PINMUX_IPSR_GPSR(IP6_10, SSI_WS34), |
973 | PINMUX_IPSR_GPSR(IP6_10, ARM_TRACEDATA_8), | |
87f8c988 | 974 | |
e01678e3 | 975 | PINMUX_IPSR_GPSR(IP6_12_11, SSI_SDATA4), |
87f8c988 | 976 | PINMUX_IPSR_MSEL(IP6_12_11, SSI_WS2_A, SEL_SSI2_A), |
e01678e3 | 977 | PINMUX_IPSR_GPSR(IP6_12_11, ARM_TRACEDATA_9), |
87f8c988 | 978 | |
e01678e3 GU |
979 | PINMUX_IPSR_GPSR(IP6_13, SSI_SDATA3), |
980 | PINMUX_IPSR_GPSR(IP6_13, ARM_TRACEDATA_10), | |
87f8c988 | 981 | |
e01678e3 GU |
982 | PINMUX_IPSR_GPSR(IP6_15_14, SSI_SCK012), |
983 | PINMUX_IPSR_GPSR(IP6_15_14, ARM_TRACEDATA_11), | |
984 | PINMUX_IPSR_GPSR(IP6_15_14, TX0_D), | |
87f8c988 | 985 | |
e01678e3 GU |
986 | PINMUX_IPSR_GPSR(IP6_16, SSI_WS012), |
987 | PINMUX_IPSR_GPSR(IP6_16, ARM_TRACEDATA_12), | |
87f8c988 | 988 | |
e01678e3 | 989 | PINMUX_IPSR_GPSR(IP6_18_17, SSI_SDATA2), |
87f8c988 | 990 | PINMUX_IPSR_MSEL(IP6_18_17, HSPI_CS2_A, SEL_HSPI2_A), |
e01678e3 | 991 | PINMUX_IPSR_GPSR(IP6_18_17, ARM_TRACEDATA_13), |
87f8c988 KM |
992 | PINMUX_IPSR_MSEL(IP6_18_17, SDA1_A, SEL_I2C1_A), |
993 | ||
e01678e3 GU |
994 | PINMUX_IPSR_GPSR(IP6_20_19, SSI_SDATA1), |
995 | PINMUX_IPSR_GPSR(IP6_20_19, ARM_TRACEDATA_14), | |
87f8c988 KM |
996 | PINMUX_IPSR_MSEL(IP6_20_19, SCL1_A, SEL_I2C1_A), |
997 | PINMUX_IPSR_MSEL(IP6_20_19, SCK2_A, SEL_SCIF2_A), | |
998 | ||
e01678e3 GU |
999 | PINMUX_IPSR_GPSR(IP6_21, SSI_SDATA0), |
1000 | PINMUX_IPSR_GPSR(IP6_21, ARM_TRACEDATA_15), | |
87f8c988 | 1001 | |
e01678e3 GU |
1002 | PINMUX_IPSR_GPSR(IP6_23_22, SD0_CLK), |
1003 | PINMUX_IPSR_GPSR(IP6_23_22, SUB_TDO), | |
87f8c988 | 1004 | |
e01678e3 GU |
1005 | PINMUX_IPSR_GPSR(IP6_25_24, SD0_CMD), |
1006 | PINMUX_IPSR_GPSR(IP6_25_24, SUB_TRST), | |
87f8c988 | 1007 | |
e01678e3 GU |
1008 | PINMUX_IPSR_GPSR(IP6_27_26, SD0_DAT0), |
1009 | PINMUX_IPSR_GPSR(IP6_27_26, SUB_TMS), | |
87f8c988 | 1010 | |
e01678e3 GU |
1011 | PINMUX_IPSR_GPSR(IP6_29_28, SD0_DAT1), |
1012 | PINMUX_IPSR_GPSR(IP6_29_28, SUB_TCK), | |
87f8c988 | 1013 | |
e01678e3 GU |
1014 | PINMUX_IPSR_GPSR(IP6_31_30, SD0_DAT2), |
1015 | PINMUX_IPSR_GPSR(IP6_31_30, SUB_TDI), | |
87f8c988 KM |
1016 | |
1017 | /* IPSR7 */ | |
e01678e3 | 1018 | PINMUX_IPSR_GPSR(IP7_1_0, SD0_DAT3), |
87f8c988 KM |
1019 | PINMUX_IPSR_MSEL(IP7_1_0, IRQ1_B, SEL_IRQ1_B), |
1020 | ||
e01678e3 GU |
1021 | PINMUX_IPSR_GPSR(IP7_3_2, SD0_CD), |
1022 | PINMUX_IPSR_GPSR(IP7_3_2, TX5_A), | |
87f8c988 | 1023 | |
e01678e3 | 1024 | PINMUX_IPSR_GPSR(IP7_5_4, SD0_WP), |
87f8c988 KM |
1025 | PINMUX_IPSR_MSEL(IP7_5_4, RX5_A, SEL_SCIF5_A), |
1026 | ||
e01678e3 | 1027 | PINMUX_IPSR_GPSR(IP7_8_6, VI1_CLKENB), |
87f8c988 | 1028 | PINMUX_IPSR_MSEL(IP7_8_6, HSPI_CLK0_A, SEL_HSPI0_A), |
e01678e3 | 1029 | PINMUX_IPSR_GPSR(IP7_8_6, HTX1_A), |
87f8c988 KM |
1030 | PINMUX_IPSR_MSEL(IP7_8_6, RTS1_C, SEL_SCIF1_C), |
1031 | ||
e01678e3 | 1032 | PINMUX_IPSR_GPSR(IP7_11_9, VI1_FIELD), |
87f8c988 KM |
1033 | PINMUX_IPSR_MSEL(IP7_11_9, HSPI_CS0_A, SEL_HSPI0_A), |
1034 | PINMUX_IPSR_MSEL(IP7_11_9, HRX1_A, SEL_HSCIF1_A), | |
1035 | PINMUX_IPSR_MSEL(IP7_11_9, SCK1_C, SEL_SCIF1_C), | |
1036 | ||
e01678e3 | 1037 | PINMUX_IPSR_GPSR(IP7_14_12, VI1_HSYNC), |
87f8c988 KM |
1038 | PINMUX_IPSR_MSEL(IP7_14_12, HSPI_RX0_A, SEL_HSPI0_A), |
1039 | PINMUX_IPSR_MSEL(IP7_14_12, HRTS1_A, SEL_HSCIF1_A), | |
1040 | PINMUX_IPSR_MSEL(IP7_14_12, FMCLK_A, SEL_FM_A), | |
1041 | PINMUX_IPSR_MSEL(IP7_14_12, RX1_C, SEL_SCIF1_C), | |
1042 | ||
e01678e3 GU |
1043 | PINMUX_IPSR_GPSR(IP7_17_15, VI1_VSYNC), |
1044 | PINMUX_IPSR_GPSR(IP7_17_15, HSPI_TX0), | |
87f8c988 | 1045 | PINMUX_IPSR_MSEL(IP7_17_15, HCTS1_A, SEL_HSCIF1_A), |
e01678e3 GU |
1046 | PINMUX_IPSR_GPSR(IP7_17_15, BPFCLK_A), |
1047 | PINMUX_IPSR_GPSR(IP7_17_15, TX1_C), | |
87f8c988 | 1048 | |
e01678e3 | 1049 | PINMUX_IPSR_GPSR(IP7_20_18, TCLK0), |
87f8c988 KM |
1050 | PINMUX_IPSR_MSEL(IP7_20_18, HSCK1_A, SEL_HSCIF1_A), |
1051 | PINMUX_IPSR_MSEL(IP7_20_18, FMIN_A, SEL_FM_A), | |
1052 | PINMUX_IPSR_MSEL(IP7_20_18, IRQ2_C, SEL_IRQ2_C), | |
1053 | PINMUX_IPSR_MSEL(IP7_20_18, CTS1_C, SEL_SCIF1_C), | |
e01678e3 | 1054 | PINMUX_IPSR_GPSR(IP7_20_18, SPEEDIN), |
87f8c988 | 1055 | |
e01678e3 | 1056 | PINMUX_IPSR_GPSR(IP7_21, VI0_CLK), |
87f8c988 KM |
1057 | PINMUX_IPSR_MSEL(IP7_21, CAN_CLK_A, SEL_CANCLK_A), |
1058 | ||
e01678e3 | 1059 | PINMUX_IPSR_GPSR(IP7_24_22, VI0_CLKENB), |
87f8c988 | 1060 | PINMUX_IPSR_MSEL(IP7_24_22, SD2_DAT2_B, SEL_SD2_B), |
e01678e3 GU |
1061 | PINMUX_IPSR_GPSR(IP7_24_22, VI1_DATA0), |
1062 | PINMUX_IPSR_GPSR(IP7_24_22, DU1_DG6), | |
87f8c988 KM |
1063 | PINMUX_IPSR_MSEL(IP7_24_22, HSPI_RX1_A, SEL_HSPI1_A), |
1064 | PINMUX_IPSR_MSEL(IP7_24_22, RX4_B, SEL_SCIF4_B), | |
1065 | ||
e01678e3 | 1066 | PINMUX_IPSR_GPSR(IP7_28_25, VI0_FIELD), |
87f8c988 KM |
1067 | PINMUX_IPSR_MSEL(IP7_28_25, SD2_DAT3_B, SEL_SD2_B), |
1068 | PINMUX_DATA(VI0_R3_C_MARK, FN_IP7_28_25, FN_VI0_R3_C, FN_SEL_VI0_C), /* see sel_vi0 */ | |
1069 | PINMUX_DATA(VI0_R3_D_MARK, FN_IP7_28_25, FN_VI0_R3_C, FN_SEL_VI0_D), /* see sel_vi0 */ | |
e01678e3 GU |
1070 | PINMUX_IPSR_GPSR(IP7_28_25, VI1_DATA1), |
1071 | PINMUX_IPSR_GPSR(IP7_28_25, DU1_DG7), | |
87f8c988 | 1072 | PINMUX_IPSR_MSEL(IP7_28_25, HSPI_CLK1_A, SEL_HSPI1_A), |
e01678e3 | 1073 | PINMUX_IPSR_GPSR(IP7_28_25, TX4_B), |
87f8c988 | 1074 | |
e01678e3 | 1075 | PINMUX_IPSR_GPSR(IP7_31_29, VI0_HSYNC), |
87f8c988 | 1076 | PINMUX_IPSR_MSEL(IP7_31_29, SD2_CD_B, SEL_SD2_B), |
e01678e3 GU |
1077 | PINMUX_IPSR_GPSR(IP7_31_29, VI1_DATA2), |
1078 | PINMUX_IPSR_GPSR(IP7_31_29, DU1_DR2), | |
87f8c988 KM |
1079 | PINMUX_IPSR_MSEL(IP7_31_29, HSPI_CS1_A, SEL_HSPI1_A), |
1080 | PINMUX_IPSR_MSEL(IP7_31_29, RX3_B, SEL_SCIF3_B), | |
1081 | ||
1082 | /* IPSR8 */ | |
e01678e3 | 1083 | PINMUX_IPSR_GPSR(IP8_2_0, VI0_VSYNC), |
87f8c988 | 1084 | PINMUX_IPSR_MSEL(IP8_2_0, SD2_WP_B, SEL_SD2_B), |
e01678e3 GU |
1085 | PINMUX_IPSR_GPSR(IP8_2_0, VI1_DATA3), |
1086 | PINMUX_IPSR_GPSR(IP8_2_0, DU1_DR3), | |
1087 | PINMUX_IPSR_GPSR(IP8_2_0, HSPI_TX1_A), | |
1088 | PINMUX_IPSR_GPSR(IP8_2_0, TX3_B), | |
87f8c988 | 1089 | |
e01678e3 GU |
1090 | PINMUX_IPSR_GPSR(IP8_5_3, VI0_DATA0_VI0_B0), |
1091 | PINMUX_IPSR_GPSR(IP8_5_3, DU1_DG2), | |
87f8c988 KM |
1092 | PINMUX_IPSR_MSEL(IP8_5_3, IRQ2_B, SEL_IRQ2_B), |
1093 | PINMUX_IPSR_MSEL(IP8_5_3, RX3_D, SEL_SCIF3_D), | |
1094 | ||
e01678e3 GU |
1095 | PINMUX_IPSR_GPSR(IP8_8_6, VI0_DATA1_VI0_B1), |
1096 | PINMUX_IPSR_GPSR(IP8_8_6, DU1_DG3), | |
87f8c988 | 1097 | PINMUX_IPSR_MSEL(IP8_8_6, IRQ3_B, SEL_IRQ3_B), |
e01678e3 | 1098 | PINMUX_IPSR_GPSR(IP8_8_6, TX3_D), |
87f8c988 | 1099 | |
e01678e3 GU |
1100 | PINMUX_IPSR_GPSR(IP8_10_9, VI0_DATA2_VI0_B2), |
1101 | PINMUX_IPSR_GPSR(IP8_10_9, DU1_DG4), | |
87f8c988 KM |
1102 | PINMUX_IPSR_MSEL(IP8_10_9, RX0_C, SEL_SCIF0_C), |
1103 | ||
e01678e3 GU |
1104 | PINMUX_IPSR_GPSR(IP8_13_11, VI0_DATA3_VI0_B3), |
1105 | PINMUX_IPSR_GPSR(IP8_13_11, DU1_DG5), | |
1106 | PINMUX_IPSR_GPSR(IP8_13_11, TX1_A), | |
1107 | PINMUX_IPSR_GPSR(IP8_13_11, TX0_C), | |
87f8c988 | 1108 | |
e01678e3 GU |
1109 | PINMUX_IPSR_GPSR(IP8_15_14, VI0_DATA4_VI0_B4), |
1110 | PINMUX_IPSR_GPSR(IP8_15_14, DU1_DB2), | |
87f8c988 KM |
1111 | PINMUX_IPSR_MSEL(IP8_15_14, RX1_A, SEL_SCIF1_A), |
1112 | ||
e01678e3 GU |
1113 | PINMUX_IPSR_GPSR(IP8_18_16, VI0_DATA5_VI0_B5), |
1114 | PINMUX_IPSR_GPSR(IP8_18_16, DU1_DB3), | |
87f8c988 | 1115 | PINMUX_IPSR_MSEL(IP8_18_16, SCK1_A, SEL_SCIF1_A), |
e01678e3 | 1116 | PINMUX_IPSR_GPSR(IP8_18_16, PWM4), |
87f8c988 KM |
1117 | PINMUX_IPSR_MSEL(IP8_18_16, HSCK1_B, SEL_HSCIF1_B), |
1118 | ||
e01678e3 GU |
1119 | PINMUX_IPSR_GPSR(IP8_21_19, VI0_DATA6_VI0_G0), |
1120 | PINMUX_IPSR_GPSR(IP8_21_19, DU1_DB4), | |
87f8c988 | 1121 | PINMUX_IPSR_MSEL(IP8_21_19, CTS1_A, SEL_SCIF1_A), |
e01678e3 | 1122 | PINMUX_IPSR_GPSR(IP8_21_19, PWM5), |
87f8c988 | 1123 | |
e01678e3 GU |
1124 | PINMUX_IPSR_GPSR(IP8_23_22, VI0_DATA7_VI0_G1), |
1125 | PINMUX_IPSR_GPSR(IP8_23_22, DU1_DB5), | |
87f8c988 KM |
1126 | PINMUX_IPSR_MSEL(IP8_23_22, RTS1_A, SEL_SCIF1_A), |
1127 | ||
e01678e3 GU |
1128 | PINMUX_IPSR_GPSR(IP8_26_24, VI0_G2), |
1129 | PINMUX_IPSR_GPSR(IP8_26_24, SD2_CLK_B), | |
1130 | PINMUX_IPSR_GPSR(IP8_26_24, VI1_DATA4), | |
1131 | PINMUX_IPSR_GPSR(IP8_26_24, DU1_DR4), | |
1132 | PINMUX_IPSR_GPSR(IP8_26_24, HTX1_B), | |
87f8c988 | 1133 | |
e01678e3 | 1134 | PINMUX_IPSR_GPSR(IP8_29_27, VI0_G3), |
87f8c988 | 1135 | PINMUX_IPSR_MSEL(IP8_29_27, SD2_CMD_B, SEL_SD2_B), |
e01678e3 GU |
1136 | PINMUX_IPSR_GPSR(IP8_29_27, VI1_DATA5), |
1137 | PINMUX_IPSR_GPSR(IP8_29_27, DU1_DR5), | |
87f8c988 KM |
1138 | PINMUX_IPSR_MSEL(IP8_29_27, HRX1_B, SEL_HSCIF1_B), |
1139 | ||
1140 | /* IPSR9 */ | |
e01678e3 | 1141 | PINMUX_IPSR_GPSR(IP9_2_0, VI0_G4), |
87f8c988 | 1142 | PINMUX_IPSR_MSEL(IP9_2_0, SD2_DAT0_B, SEL_SD2_B), |
e01678e3 GU |
1143 | PINMUX_IPSR_GPSR(IP9_2_0, VI1_DATA6), |
1144 | PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR6), | |
87f8c988 KM |
1145 | PINMUX_IPSR_MSEL(IP9_2_0, HRTS1_B, SEL_HSCIF1_B), |
1146 | ||
e01678e3 | 1147 | PINMUX_IPSR_GPSR(IP9_5_3, VI0_G5), |
87f8c988 | 1148 | PINMUX_IPSR_MSEL(IP9_5_3, SD2_DAT1_B, SEL_SD2_B), |
e01678e3 GU |
1149 | PINMUX_IPSR_GPSR(IP9_5_3, VI1_DATA7), |
1150 | PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR7), | |
87f8c988 KM |
1151 | PINMUX_IPSR_MSEL(IP9_5_3, HCTS1_B, SEL_HSCIF1_B), |
1152 | ||
1153 | PINMUX_DATA(VI0_R0_A_MARK, FN_IP9_8_6, FN_VI0_R0_A, FN_SEL_VI0_A), /* see sel_vi0 */ | |
1154 | PINMUX_DATA(VI0_R0_C_MARK, FN_IP9_8_6, FN_VI0_R0_A, FN_SEL_VI0_C), /* see sel_vi0 */ | |
e01678e3 GU |
1155 | PINMUX_IPSR_GPSR(IP9_8_6, VI1_CLK), |
1156 | PINMUX_IPSR_GPSR(IP9_8_6, ETH_REF_CLK), | |
1157 | PINMUX_IPSR_GPSR(IP9_8_6, DU1_DOTCLKIN), | |
87f8c988 KM |
1158 | |
1159 | PINMUX_DATA(VI0_R1_A_MARK, FN_IP9_11_9, FN_VI0_R1_A, FN_SEL_VI0_A), /* see sel_vi0 */ | |
1160 | PINMUX_DATA(VI0_R1_C_MARK, FN_IP9_11_9, FN_VI0_R1_A, FN_SEL_VI0_C), /* see sel_vi0 */ | |
e01678e3 GU |
1161 | PINMUX_IPSR_GPSR(IP9_11_9, VI1_DATA8), |
1162 | PINMUX_IPSR_GPSR(IP9_11_9, DU1_DB6), | |
1163 | PINMUX_IPSR_GPSR(IP9_11_9, ETH_TXD0), | |
1164 | PINMUX_IPSR_GPSR(IP9_11_9, PWM2), | |
1165 | PINMUX_IPSR_GPSR(IP9_11_9, TCLK1), | |
87f8c988 KM |
1166 | |
1167 | PINMUX_DATA(VI0_R2_A_MARK, FN_IP9_14_12, FN_VI0_R2_A, FN_SEL_VI0_A), /* see sel_vi0 */ | |
1168 | PINMUX_DATA(VI0_R2_C_MARK, FN_IP9_14_12, FN_VI0_R2_A, FN_SEL_VI0_C), /* see sel_vi0 */ | |
e01678e3 GU |
1169 | PINMUX_IPSR_GPSR(IP9_14_12, VI1_DATA9), |
1170 | PINMUX_IPSR_GPSR(IP9_14_12, DU1_DB7), | |
1171 | PINMUX_IPSR_GPSR(IP9_14_12, ETH_TXD1), | |
1172 | PINMUX_IPSR_GPSR(IP9_14_12, PWM3), | |
87f8c988 KM |
1173 | |
1174 | PINMUX_IPSR_MSEL(IP9_17_15, VI0_R3_A, SEL_VI0_A), | |
e01678e3 GU |
1175 | PINMUX_IPSR_GPSR(IP9_17_15, ETH_CRS_DV), |
1176 | PINMUX_IPSR_GPSR(IP9_17_15, IECLK), | |
87f8c988 KM |
1177 | PINMUX_IPSR_MSEL(IP9_17_15, SCK2_C, SEL_SCIF2_C), |
1178 | ||
1179 | PINMUX_DATA(VI0_R4_A_MARK, FN_IP9_20_18, FN_VI0_R4_A, FN_SEL_VI0_A), /* see sel_vi0 */ | |
1180 | PINMUX_DATA(VI0_R3_C_MARK, FN_IP9_20_18, FN_VI0_R4_A, FN_SEL_VI0_C), /* see sel_vi0 */ | |
e01678e3 GU |
1181 | PINMUX_IPSR_GPSR(IP9_20_18, ETH_TX_EN), |
1182 | PINMUX_IPSR_GPSR(IP9_20_18, IETX), | |
1183 | PINMUX_IPSR_GPSR(IP9_20_18, TX2_C), | |
87f8c988 KM |
1184 | |
1185 | PINMUX_DATA(VI0_R5_A_MARK, FN_IP9_23_21, FN_VI0_R5_A, FN_SEL_VI0_A), /* see sel_vi0 */ | |
1186 | PINMUX_DATA(VI0_R5_C_MARK, FN_IP9_23_21, FN_VI0_R5_A, FN_SEL_VI0_C), /* see sel_vi0 */ | |
e01678e3 | 1187 | PINMUX_IPSR_GPSR(IP9_23_21, ETH_RX_ER), |
87f8c988 | 1188 | PINMUX_IPSR_MSEL(IP9_23_21, FMCLK_C, SEL_FM_C), |
e01678e3 | 1189 | PINMUX_IPSR_GPSR(IP9_23_21, IERX), |
87f8c988 KM |
1190 | PINMUX_IPSR_MSEL(IP9_23_21, RX2_C, SEL_SCIF2_C), |
1191 | ||
1192 | PINMUX_IPSR_MSEL(IP9_26_24, VI1_DATA10_A, SEL_VI1_A), | |
e01678e3 GU |
1193 | PINMUX_IPSR_GPSR(IP9_26_24, DU1_DOTCLKOUT), |
1194 | PINMUX_IPSR_GPSR(IP9_26_24, ETH_RXD0), | |
1195 | PINMUX_IPSR_GPSR(IP9_26_24, BPFCLK_C), | |
1196 | PINMUX_IPSR_GPSR(IP9_26_24, TX2_D), | |
87f8c988 KM |
1197 | PINMUX_IPSR_MSEL(IP9_26_24, SDA2_C, SEL_I2C2_C), |
1198 | ||
1199 | PINMUX_IPSR_MSEL(IP9_29_27, VI1_DATA11_A, SEL_VI1_A), | |
e01678e3 GU |
1200 | PINMUX_IPSR_GPSR(IP9_29_27, DU1_EXHSYNC_DU1_HSYNC), |
1201 | PINMUX_IPSR_GPSR(IP9_29_27, ETH_RXD1), | |
87f8c988 KM |
1202 | PINMUX_IPSR_MSEL(IP9_29_27, FMIN_C, SEL_FM_C), |
1203 | PINMUX_IPSR_MSEL(IP9_29_27, RX2_D, SEL_SCIF2_D), | |
1204 | PINMUX_IPSR_MSEL(IP9_29_27, SCL2_C, SEL_I2C2_C), | |
1205 | ||
1206 | /* IPSR10 */ | |
e01678e3 GU |
1207 | PINMUX_IPSR_GPSR(IP10_2_0, SD2_CLK_A), |
1208 | PINMUX_IPSR_GPSR(IP10_2_0, DU1_EXVSYNC_DU1_VSYNC), | |
1209 | PINMUX_IPSR_GPSR(IP10_2_0, ATARD1), | |
1210 | PINMUX_IPSR_GPSR(IP10_2_0, ETH_MDC), | |
87f8c988 KM |
1211 | PINMUX_IPSR_MSEL(IP10_2_0, SDA1_B, SEL_I2C1_B), |
1212 | ||
1213 | PINMUX_IPSR_MSEL(IP10_5_3, SD2_CMD_A, SEL_SD2_A), | |
e01678e3 GU |
1214 | PINMUX_IPSR_GPSR(IP10_5_3, DU1_EXODDF_DU1_ODDF_DISP_CDE), |
1215 | PINMUX_IPSR_GPSR(IP10_5_3, ATAWR1), | |
1216 | PINMUX_IPSR_GPSR(IP10_5_3, ETH_MDIO), | |
87f8c988 KM |
1217 | PINMUX_IPSR_MSEL(IP10_5_3, SCL1_B, SEL_I2C1_B), |
1218 | ||
1219 | PINMUX_IPSR_MSEL(IP10_8_6, SD2_DAT0_A, SEL_SD2_A), | |
e01678e3 GU |
1220 | PINMUX_IPSR_GPSR(IP10_8_6, DU1_DISP), |
1221 | PINMUX_IPSR_GPSR(IP10_8_6, ATACS01), | |
87f8c988 | 1222 | PINMUX_IPSR_MSEL(IP10_8_6, DREQ1_B, SEL_DREQ1_B), |
e01678e3 | 1223 | PINMUX_IPSR_GPSR(IP10_8_6, ETH_LINK), |
87f8c988 KM |
1224 | PINMUX_IPSR_MSEL(IP10_8_6, CAN1_RX_A, SEL_CAN1_A), |
1225 | ||
1226 | PINMUX_IPSR_MSEL(IP10_12_9, SD2_DAT1_A, SEL_SD2_A), | |
e01678e3 GU |
1227 | PINMUX_IPSR_GPSR(IP10_12_9, DU1_CDE), |
1228 | PINMUX_IPSR_GPSR(IP10_12_9, ATACS11), | |
1229 | PINMUX_IPSR_GPSR(IP10_12_9, DACK1_B), | |
1230 | PINMUX_IPSR_GPSR(IP10_12_9, ETH_MAGIC), | |
1231 | PINMUX_IPSR_GPSR(IP10_12_9, CAN1_TX_A), | |
1232 | PINMUX_IPSR_GPSR(IP10_12_9, PWM6), | |
87f8c988 KM |
1233 | |
1234 | PINMUX_IPSR_MSEL(IP10_15_13, SD2_DAT2_A, SEL_SD2_A), | |
e01678e3 | 1235 | PINMUX_IPSR_GPSR(IP10_15_13, VI1_DATA12), |
87f8c988 | 1236 | PINMUX_IPSR_MSEL(IP10_15_13, DREQ2_B, SEL_DREQ2_B), |
e01678e3 | 1237 | PINMUX_IPSR_GPSR(IP10_15_13, ATADIR1), |
87f8c988 KM |
1238 | PINMUX_IPSR_MSEL(IP10_15_13, HSPI_CLK2_B, SEL_HSPI2_B), |
1239 | PINMUX_IPSR_MSEL(IP10_15_13, GPSCLK_B, SEL_GPS_B), | |
1240 | ||
1241 | PINMUX_IPSR_MSEL(IP10_18_16, SD2_DAT3_A, SEL_SD2_A), | |
e01678e3 GU |
1242 | PINMUX_IPSR_GPSR(IP10_18_16, VI1_DATA13), |
1243 | PINMUX_IPSR_GPSR(IP10_18_16, DACK2_B), | |
1244 | PINMUX_IPSR_GPSR(IP10_18_16, ATAG1), | |
87f8c988 KM |
1245 | PINMUX_IPSR_MSEL(IP10_18_16, HSPI_CS2_B, SEL_HSPI2_B), |
1246 | PINMUX_IPSR_MSEL(IP10_18_16, GPSIN_B, SEL_GPS_B), | |
1247 | ||
1248 | PINMUX_IPSR_MSEL(IP10_21_19, SD2_CD_A, SEL_SD2_A), | |
e01678e3 | 1249 | PINMUX_IPSR_GPSR(IP10_21_19, VI1_DATA14), |
87f8c988 KM |
1250 | PINMUX_IPSR_MSEL(IP10_21_19, EX_WAIT1_B, SEL_WAIT1_B), |
1251 | PINMUX_IPSR_MSEL(IP10_21_19, DREQ0_B, SEL_DREQ0_B), | |
1252 | PINMUX_IPSR_MSEL(IP10_21_19, HSPI_RX2_B, SEL_HSPI2_B), | |
1253 | PINMUX_IPSR_MSEL(IP10_21_19, REMOCON_A, SEL_REMOCON_A), | |
1254 | ||
1255 | PINMUX_IPSR_MSEL(IP10_24_22, SD2_WP_A, SEL_SD2_A), | |
e01678e3 | 1256 | PINMUX_IPSR_GPSR(IP10_24_22, VI1_DATA15), |
87f8c988 | 1257 | PINMUX_IPSR_MSEL(IP10_24_22, EX_WAIT2_B, SEL_WAIT2_B), |
e01678e3 GU |
1258 | PINMUX_IPSR_GPSR(IP10_24_22, DACK0_B), |
1259 | PINMUX_IPSR_GPSR(IP10_24_22, HSPI_TX2_B), | |
87f8c988 KM |
1260 | PINMUX_IPSR_MSEL(IP10_24_22, CAN_CLK_C, SEL_CANCLK_C), |
1261 | }; | |
1262 | ||
87f8c988 KM |
1263 | /* Pin numbers for pins without a corresponding GPIO port number are computed |
1264 | * from the row and column numbers with a 1000 offset to avoid collisions with | |
1265 | * GPIO port numbers. | |
1266 | */ | |
1267 | #define PIN_NUMBER(row, col) (1000+((row)-1)*25+(col)-1) | |
1268 | ||
44a45b55 | 1269 | static const struct sh_pfc_pin pinmux_pins[] = { |
4f82e3ee LP |
1270 | PINMUX_GPIO_GP_ALL(), |
1271 | ||
1272 | /* Pins not associated with a GPIO port */ | |
1273 | SH_PFC_PIN_NAMED(3, 20, C20), | |
1274 | SH_PFC_PIN_NAMED(20, 1, T1), | |
1275 | SH_PFC_PIN_NAMED(25, 2, Y2), | |
1276 | }; | |
1277 | ||
a10cd30e KM |
1278 | /* - macro */ |
1279 | #define SH_PFC_PINS(name, args...) \ | |
87f8c988 | 1280 | static const unsigned int name ##_pins[] = { args } |
a10cd30e KM |
1281 | #define SH_PFC_MUX1(name, arg1) \ |
1282 | static const unsigned int name ##_mux[] = { arg1##_MARK } | |
1283 | #define SH_PFC_MUX2(name, arg1, arg2) \ | |
1284 | static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, } | |
1285 | #define SH_PFC_MUX3(name, arg1, arg2, arg3) \ | |
1286 | static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \ | |
1287 | arg3##_MARK } | |
1288 | #define SH_PFC_MUX4(name, arg1, arg2, arg3, arg4) \ | |
1289 | static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \ | |
1290 | arg3##_MARK, arg4##_MARK } | |
2d7cd398 VB |
1291 | #define SH_PFC_MUX8(name, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8) \ |
1292 | static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \ | |
1293 | arg3##_MARK, arg4##_MARK, \ | |
1294 | arg5##_MARK, arg6##_MARK, \ | |
1295 | arg7##_MARK, arg8##_MARK, } | |
a10cd30e | 1296 | |
3ad8219a KM |
1297 | /* - AUDIO macro -------------------------------------------------------------*/ |
1298 | #define AUDIO_PFC_PIN(name, pin) SH_PFC_PINS(name, pin) | |
1299 | #define AUDIO_PFC_DAT(name, pin) SH_PFC_MUX1(name, pin) | |
1300 | ||
1301 | /* - AUDIO clock -------------------------------------------------------------*/ | |
1302 | AUDIO_PFC_PIN(audio_clk_a, RCAR_GP_PIN(2, 22)); | |
1303 | AUDIO_PFC_DAT(audio_clk_a, AUDIO_CLKA); | |
1304 | AUDIO_PFC_PIN(audio_clk_b, RCAR_GP_PIN(2, 23)); | |
1305 | AUDIO_PFC_DAT(audio_clk_b, AUDIO_CLKB); | |
1306 | AUDIO_PFC_PIN(audio_clk_c, RCAR_GP_PIN(2, 7)); | |
1307 | AUDIO_PFC_DAT(audio_clk_c, AUDIO_CLKC); | |
1308 | AUDIO_PFC_PIN(audio_clkout_a, RCAR_GP_PIN(2, 16)); | |
1309 | AUDIO_PFC_DAT(audio_clkout_a, AUDIO_CLKOUT_A); | |
1310 | AUDIO_PFC_PIN(audio_clkout_b, RCAR_GP_PIN(1, 16)); | |
1311 | AUDIO_PFC_DAT(audio_clkout_b, AUDIO_CLKOUT_B); | |
1312 | ||
24799c22 SS |
1313 | /* - CAN macro --------_----------------------------------------------------- */ |
1314 | #define CAN_PFC_PINS(name, args...) SH_PFC_PINS(name, args) | |
1315 | #define CAN_PFC_DATA(name, tx, rx) SH_PFC_MUX2(name, tx, rx) | |
1316 | #define CAN_PFC_CLK(name, clk) SH_PFC_MUX1(name, clk) | |
1317 | ||
1318 | /* - CAN0 ------------------------------------------------------------------- */ | |
1319 | CAN_PFC_PINS(can0_data_a, RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31)); | |
1320 | CAN_PFC_DATA(can0_data_a, CAN0_TX_A, CAN0_RX_A); | |
1321 | CAN_PFC_PINS(can0_data_b, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27)); | |
1322 | CAN_PFC_DATA(can0_data_b, CAN0_TX_B, CAN0_RX_B); | |
1323 | ||
1324 | /* - CAN1 ------------------------------------------------------------------- */ | |
1325 | CAN_PFC_PINS(can1_data_a, RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19)); | |
1326 | CAN_PFC_DATA(can1_data_a, CAN1_TX_A, CAN1_RX_A); | |
1327 | CAN_PFC_PINS(can1_data_b, RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 29)); | |
1328 | CAN_PFC_DATA(can1_data_b, CAN1_TX_B, CAN1_RX_B); | |
1329 | ||
1330 | /* - CAN_CLK --------------------------------------------------------------- */ | |
1331 | CAN_PFC_PINS(can_clk_a, RCAR_GP_PIN(3, 24)); | |
1332 | CAN_PFC_CLK(can_clk_a, CAN_CLK_A); | |
1333 | CAN_PFC_PINS(can_clk_b, RCAR_GP_PIN(1, 16)); | |
1334 | CAN_PFC_CLK(can_clk_b, CAN_CLK_B); | |
1335 | CAN_PFC_PINS(can_clk_c, RCAR_GP_PIN(4, 24)); | |
1336 | CAN_PFC_CLK(can_clk_c, CAN_CLK_C); | |
1337 | CAN_PFC_PINS(can_clk_d, RCAR_GP_PIN(2, 25)); | |
1338 | CAN_PFC_CLK(can_clk_d, CAN_CLK_D); | |
1339 | ||
3c5886d1 SS |
1340 | /* - Ether ------------------------------------------------------------------ */ |
1341 | SH_PFC_PINS(ether_rmii, RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), | |
1342 | RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 9), | |
1343 | RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), | |
1344 | RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 14), | |
1345 | RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17)); | |
1346 | static const unsigned int ether_rmii_mux[] = { | |
1347 | ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK, | |
1348 | ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK, | |
1349 | ETH_MDIO_MARK, ETH_MDC_MARK, | |
1350 | }; | |
1351 | SH_PFC_PINS(ether_link, RCAR_GP_PIN(4, 19)); | |
1352 | SH_PFC_MUX1(ether_link, ETH_LINK); | |
1353 | SH_PFC_PINS(ether_magic, RCAR_GP_PIN(4, 20)); | |
1354 | SH_PFC_MUX1(ether_magic, ETH_MAGIC); | |
1355 | ||
a10cd30e KM |
1356 | /* - SCIF macro ------------------------------------------------------------- */ |
1357 | #define SCIF_PFC_PIN(name, args...) SH_PFC_PINS(name, args) | |
1358 | #define SCIF_PFC_DAT(name, tx, rx) SH_PFC_MUX2(name, tx, rx) | |
1359 | #define SCIF_PFC_CTR(name, cts, rts) SH_PFC_MUX2(name, cts, rts) | |
1360 | #define SCIF_PFC_CLK(name, sck) SH_PFC_MUX1(name, sck) | |
87f8c988 KM |
1361 | |
1362 | /* - HSCIF0 ----------------------------------------------------------------- */ | |
1363 | SCIF_PFC_PIN(hscif0_data_a, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18)); | |
1364 | SCIF_PFC_DAT(hscif0_data_a, HTX0_A, HRX0_A); | |
1365 | SCIF_PFC_PIN(hscif0_data_b, RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 30)); | |
1366 | SCIF_PFC_DAT(hscif0_data_b, HTX0_B, HRX0_B); | |
1367 | SCIF_PFC_PIN(hscif0_ctrl_a, RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21)); | |
1368 | SCIF_PFC_CTR(hscif0_ctrl_a, HCTS0_A, HRTS0_A); | |
1369 | SCIF_PFC_PIN(hscif0_ctrl_b, RCAR_GP_PIN(0, 31), RCAR_GP_PIN(0, 28)); | |
1370 | SCIF_PFC_CTR(hscif0_ctrl_b, HCTS0_B, HRTS0_B); | |
1371 | SCIF_PFC_PIN(hscif0_clk, RCAR_GP_PIN(1, 19)); | |
1372 | SCIF_PFC_CLK(hscif0_clk, HSCK0); | |
1373 | ||
1374 | /* - HSCIF1 ----------------------------------------------------------------- */ | |
1375 | SCIF_PFC_PIN(hscif1_data_a, RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20)); | |
1376 | SCIF_PFC_DAT(hscif1_data_a, HTX1_A, HRX1_A); | |
1377 | SCIF_PFC_PIN(hscif1_data_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6)); | |
1378 | SCIF_PFC_DAT(hscif1_data_b, HTX1_B, HRX1_B); | |
1379 | SCIF_PFC_PIN(hscif1_ctrl_a, RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21)); | |
1380 | SCIF_PFC_CTR(hscif1_ctrl_a, HCTS1_A, HRTS1_A); | |
1381 | SCIF_PFC_PIN(hscif1_ctrl_b, RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7)); | |
1382 | SCIF_PFC_CTR(hscif1_ctrl_b, HCTS1_B, HRTS1_B); | |
1383 | SCIF_PFC_PIN(hscif1_clk_a, RCAR_GP_PIN(3, 23)); | |
1384 | SCIF_PFC_CLK(hscif1_clk_a, HSCK1_A); | |
1385 | SCIF_PFC_PIN(hscif1_clk_b, RCAR_GP_PIN(4, 2)); | |
1386 | SCIF_PFC_CLK(hscif1_clk_b, HSCK1_B); | |
1387 | ||
09cc76a9 KM |
1388 | /* - HSPI macro --------------------------------------------------------------*/ |
1389 | #define HSPI_PFC_PIN(name, args...) SH_PFC_PINS(name, args) | |
1390 | #define HSPI_PFC_DAT(name, clk, cs, rx, tx) SH_PFC_MUX4(name, clk, cs, rx, tx) | |
1391 | ||
1392 | /* - HSPI0 -------------------------------------------------------------------*/ | |
1393 | HSPI_PFC_PIN(hspi0_a, RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), | |
1394 | RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22)); | |
1395 | HSPI_PFC_DAT(hspi0_a, HSPI_CLK0_A, HSPI_CS0_A, | |
1396 | HSPI_RX0_A, HSPI_TX0); | |
1397 | ||
1398 | HSPI_PFC_PIN(hspi0_b, RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26), | |
1399 | RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 27)); | |
1400 | HSPI_PFC_DAT(hspi0_b, HSPI_CLK0_B, HSPI_CS0_B, | |
1401 | HSPI_RX0_B, HSPI_TX0_B); | |
1402 | ||
1403 | /* - HSPI1 -------------------------------------------------------------------*/ | |
1404 | HSPI_PFC_PIN(hspi1_a, RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), | |
1405 | RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 28)); | |
1406 | HSPI_PFC_DAT(hspi1_a, HSPI_CLK1_A, HSPI_CS1_A, | |
1407 | HSPI_RX1_A, HSPI_TX1_A); | |
1408 | ||
1409 | HSPI_PFC_PIN(hspi1_b, RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 26), | |
1410 | PIN_NUMBER(20, 1), PIN_NUMBER(25, 2)); | |
1411 | HSPI_PFC_DAT(hspi1_b, HSPI_CLK1_B, HSPI_CS1_B, | |
1412 | HSPI_RX1_B, HSPI_TX1_B); | |
1413 | ||
1414 | /* - HSPI2 -------------------------------------------------------------------*/ | |
1415 | HSPI_PFC_PIN(hspi2_a, RCAR_GP_PIN(2, 29), RCAR_GP_PIN(3, 8), | |
1416 | RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 30)); | |
1417 | HSPI_PFC_DAT(hspi2_a, HSPI_CLK2_A, HSPI_CS2_A, | |
1418 | HSPI_RX2_A, HSPI_TX2_A); | |
1419 | ||
1420 | HSPI_PFC_PIN(hspi2_b, RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22), | |
1421 | RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24)); | |
1422 | HSPI_PFC_DAT(hspi2_b, HSPI_CLK2_B, HSPI_CS2_B, | |
1423 | HSPI_RX2_B, HSPI_TX2_B); | |
1424 | ||
0dcbc69e KM |
1425 | /* - I2C macro ------------------------------------------------------------- */ |
1426 | #define I2C_PFC_PIN(name, args...) SH_PFC_PINS(name, args) | |
1427 | #define I2C_PFC_MUX(name, sda, scl) SH_PFC_MUX2(name, sda, scl) | |
1428 | ||
1429 | /* - I2C1 ------------------------------------------------------------------ */ | |
1430 | I2C_PFC_PIN(i2c1_a, RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9)); | |
1431 | I2C_PFC_MUX(i2c1_a, SDA1_A, SCL1_A); | |
1432 | I2C_PFC_PIN(i2c1_b, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18)); | |
1433 | I2C_PFC_MUX(i2c1_b, SDA1_B, SCL1_B); | |
1434 | ||
1435 | /* - I2C2 ------------------------------------------------------------------ */ | |
1436 | I2C_PFC_PIN(i2c2_a, PIN_NUMBER(3, 20), RCAR_GP_PIN(1, 3)); | |
1437 | I2C_PFC_MUX(i2c2_a, SDA2_A, SCL2_A); | |
1438 | I2C_PFC_PIN(i2c2_b, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4)); | |
1439 | I2C_PFC_MUX(i2c2_b, SDA2_B, SCL2_B); | |
1440 | I2C_PFC_PIN(i2c2_c, RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16)); | |
1441 | I2C_PFC_MUX(i2c2_c, SDA2_C, SCL2_C); | |
1442 | ||
1443 | /* - I2C3 ------------------------------------------------------------------ */ | |
1444 | I2C_PFC_PIN(i2c3_a, RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15)); | |
1445 | I2C_PFC_MUX(i2c3_a, SDA3_A, SCL3_A); | |
1446 | I2C_PFC_PIN(i2c3_b, RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 19)); | |
1447 | I2C_PFC_MUX(i2c3_b, SDA3_B, SCL3_B); | |
1448 | I2C_PFC_PIN(i2c3_c, RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23)); | |
1449 | I2C_PFC_MUX(i2c3_c, SDA3_C, SCL3_C); | |
1450 | ||
3ef2a776 KM |
1451 | /* - MMC macro -------------------------------------------------------------- */ |
1452 | #define MMC_PFC_PINS(name, args...) SH_PFC_PINS(name, args) | |
1453 | #define MMC_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd) | |
1454 | #define MMC_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0) | |
1455 | #define MMC_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3) | |
1456 | #define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \ | |
1457 | SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7) | |
1458 | ||
1459 | /* - MMC -------------------------------------------------------------------- */ | |
1460 | MMC_PFC_PINS(mmc_ctrl, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6)); | |
1461 | MMC_PFC_CTRL(mmc_ctrl, MMC_CLK, MMC_CMD); | |
1462 | MMC_PFC_PINS(mmc_data1, RCAR_GP_PIN(1, 7)); | |
1463 | MMC_PFC_DAT1(mmc_data1, MMC_D0); | |
cd622017 | 1464 | MMC_PFC_PINS(mmc_data4, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), |
3ef2a776 KM |
1465 | RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6)); |
1466 | MMC_PFC_DAT4(mmc_data4, MMC_D0, MMC_D1, | |
1467 | MMC_D2, MMC_D3); | |
cd622017 | 1468 | MMC_PFC_PINS(mmc_data8, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), |
3ef2a776 KM |
1469 | RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), |
1470 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0), | |
1471 | RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31)); | |
1472 | MMC_PFC_DAT8(mmc_data8, MMC_D0, MMC_D1, | |
1473 | MMC_D2, MMC_D3, | |
1474 | MMC_D4, MMC_D5, | |
1475 | MMC_D6, MMC_D7); | |
1476 | ||
87f8c988 KM |
1477 | /* - SCIF CLOCK ------------------------------------------------------------- */ |
1478 | SCIF_PFC_PIN(scif_clk, RCAR_GP_PIN(1, 16)); | |
1479 | SCIF_PFC_CLK(scif_clk, SCIF_CLK); | |
1480 | ||
1481 | /* - SCIF0 ------------------------------------------------------------------ */ | |
1482 | SCIF_PFC_PIN(scif0_data_a, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18)); | |
1483 | SCIF_PFC_DAT(scif0_data_a, TX0_A, RX0_A); | |
1484 | SCIF_PFC_PIN(scif0_data_b, RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2)); | |
1485 | SCIF_PFC_DAT(scif0_data_b, TX0_B, RX0_B); | |
1486 | SCIF_PFC_PIN(scif0_data_c, RCAR_GP_PIN(4, 0), RCAR_GP_PIN(3, 31)); | |
1487 | SCIF_PFC_DAT(scif0_data_c, TX0_C, RX0_C); | |
1488 | SCIF_PFC_PIN(scif0_data_d, RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 1)); | |
1489 | SCIF_PFC_DAT(scif0_data_d, TX0_D, RX0_D); | |
1490 | SCIF_PFC_PIN(scif0_ctrl, RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21)); | |
1491 | SCIF_PFC_CTR(scif0_ctrl, CTS0, RTS0); | |
1492 | SCIF_PFC_PIN(scif0_clk, RCAR_GP_PIN(1, 19)); | |
1493 | SCIF_PFC_CLK(scif0_clk, SCK0); | |
1494 | ||
1495 | /* - SCIF1 ------------------------------------------------------------------ */ | |
1496 | SCIF_PFC_PIN(scif1_data_a, RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1)); | |
1497 | SCIF_PFC_DAT(scif1_data_a, TX1_A, RX1_A); | |
1498 | SCIF_PFC_PIN(scif1_data_b, RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25)); | |
1499 | SCIF_PFC_DAT(scif1_data_b, TX1_B, RX1_B); | |
1500 | SCIF_PFC_PIN(scif1_data_c, RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21)); | |
1501 | SCIF_PFC_DAT(scif1_data_c, TX1_C, RX1_C); | |
1502 | SCIF_PFC_PIN(scif1_data_d, RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31)); | |
1503 | SCIF_PFC_DAT(scif1_data_d, TX1_D, RX1_D); | |
1504 | SCIF_PFC_PIN(scif1_ctrl_a, RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4)); | |
1505 | SCIF_PFC_CTR(scif1_ctrl_a, CTS1_A, RTS1_A); | |
1506 | SCIF_PFC_PIN(scif1_ctrl_c, RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 19)); | |
1507 | SCIF_PFC_CTR(scif1_ctrl_c, CTS1_C, RTS1_C); | |
1508 | SCIF_PFC_PIN(scif1_clk_a, RCAR_GP_PIN(4, 2)); | |
1509 | SCIF_PFC_CLK(scif1_clk_a, SCK1_A); | |
1510 | SCIF_PFC_PIN(scif1_clk_c, RCAR_GP_PIN(3, 20)); | |
1511 | SCIF_PFC_CLK(scif1_clk_c, SCK1_C); | |
1512 | ||
1513 | /* - SCIF2 ------------------------------------------------------------------ */ | |
1514 | SCIF_PFC_PIN(scif2_data_a, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27)); | |
1515 | SCIF_PFC_DAT(scif2_data_a, TX2_A, RX2_A); | |
1516 | SCIF_PFC_PIN(scif2_data_b, RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 28)); | |
1517 | SCIF_PFC_DAT(scif2_data_b, TX2_B, RX2_B); | |
1518 | SCIF_PFC_PIN(scif2_data_c, RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14)); | |
1519 | SCIF_PFC_DAT(scif2_data_c, TX2_C, RX2_C); | |
1520 | SCIF_PFC_PIN(scif2_data_d, RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16)); | |
1521 | SCIF_PFC_DAT(scif2_data_d, TX2_D, RX2_D); | |
1522 | SCIF_PFC_PIN(scif2_data_e, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4)); | |
1523 | SCIF_PFC_DAT(scif2_data_e, TX2_E, RX2_E); | |
1524 | SCIF_PFC_PIN(scif2_clk_a, RCAR_GP_PIN(3, 9)); | |
1525 | SCIF_PFC_CLK(scif2_clk_a, SCK2_A); | |
1526 | SCIF_PFC_PIN(scif2_clk_b, PIN_NUMBER(3, 20)); | |
1527 | SCIF_PFC_CLK(scif2_clk_b, SCK2_B); | |
1528 | SCIF_PFC_PIN(scif2_clk_c, RCAR_GP_PIN(4, 12)); | |
1529 | SCIF_PFC_CLK(scif2_clk_c, SCK2_C); | |
1530 | ||
1531 | /* - SCIF3 ------------------------------------------------------------------ */ | |
1532 | SCIF_PFC_PIN(scif3_data_a, RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9)); | |
1533 | SCIF_PFC_DAT(scif3_data_a, TX3_A, RX3_A); | |
1534 | SCIF_PFC_PIN(scif3_data_b, RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27)); | |
1535 | SCIF_PFC_DAT(scif3_data_b, TX3_B, RX3_B); | |
1536 | SCIF_PFC_PIN(scif3_data_c, RCAR_GP_PIN(1, 3), RCAR_GP_PIN(0, 31)); | |
1537 | SCIF_PFC_DAT(scif3_data_c, TX3_C, RX3_C); | |
1538 | SCIF_PFC_PIN(scif3_data_d, RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 29)); | |
1539 | SCIF_PFC_DAT(scif3_data_d, TX3_D, RX3_D); | |
1540 | ||
1541 | /* - SCIF4 ------------------------------------------------------------------ */ | |
1542 | SCIF_PFC_PIN(scif4_data_a, RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4)); | |
1543 | SCIF_PFC_DAT(scif4_data_a, TX4_A, RX4_A); | |
1544 | SCIF_PFC_PIN(scif4_data_b, RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 25)); | |
1545 | SCIF_PFC_DAT(scif4_data_b, TX4_B, RX4_B); | |
1546 | SCIF_PFC_PIN(scif4_data_c, RCAR_GP_PIN(3, 0), RCAR_GP_PIN(2, 31)); | |
1547 | SCIF_PFC_DAT(scif4_data_c, TX4_C, RX4_C); | |
1548 | ||
1549 | /* - SCIF5 ------------------------------------------------------------------ */ | |
1550 | SCIF_PFC_PIN(scif5_data_a, RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18)); | |
1551 | SCIF_PFC_DAT(scif5_data_a, TX5_A, RX5_A); | |
1552 | SCIF_PFC_PIN(scif5_data_b, RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14)); | |
1553 | SCIF_PFC_DAT(scif5_data_b, TX5_B, RX5_B); | |
1554 | ||
564617d2 KM |
1555 | /* - SDHI macro ------------------------------------------------------------- */ |
1556 | #define SDHI_PFC_PINS(name, args...) SH_PFC_PINS(name, args) | |
1557 | #define SDHI_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0) | |
1558 | #define SDHI_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3) | |
1559 | #define SDHI_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd) | |
1560 | #define SDHI_PFC_CDPN(name, cd) SH_PFC_MUX1(name, cd) | |
1561 | #define SDHI_PFC_WPPN(name, wp) SH_PFC_MUX1(name, wp) | |
1562 | ||
1563 | /* - SDHI0 ------------------------------------------------------------------ */ | |
1564 | SDHI_PFC_PINS(sdhi0_cd, RCAR_GP_PIN(3, 17)); | |
1565 | SDHI_PFC_CDPN(sdhi0_cd, SD0_CD); | |
1566 | SDHI_PFC_PINS(sdhi0_ctrl, RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12)); | |
1567 | SDHI_PFC_CTRL(sdhi0_ctrl, SD0_CLK, SD0_CMD); | |
1568 | SDHI_PFC_PINS(sdhi0_data1, RCAR_GP_PIN(3, 13)); | |
1569 | SDHI_PFC_DAT1(sdhi0_data1, SD0_DAT0); | |
1570 | SDHI_PFC_PINS(sdhi0_data4, RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14), | |
1571 | RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16)); | |
1572 | SDHI_PFC_DAT4(sdhi0_data4, SD0_DAT0, SD0_DAT1, | |
1573 | SD0_DAT2, SD0_DAT3); | |
1574 | SDHI_PFC_PINS(sdhi0_wp, RCAR_GP_PIN(3, 18)); | |
1575 | SDHI_PFC_WPPN(sdhi0_wp, SD0_WP); | |
1576 | ||
1577 | /* - SDHI1 ------------------------------------------------------------------ */ | |
0290df2d KM |
1578 | SDHI_PFC_PINS(sdhi1_cd_a, RCAR_GP_PIN(0, 30)); |
1579 | SDHI_PFC_CDPN(sdhi1_cd_a, SD1_CD_A); | |
1580 | SDHI_PFC_PINS(sdhi1_cd_b, RCAR_GP_PIN(2, 24)); | |
1581 | SDHI_PFC_CDPN(sdhi1_cd_b, SD1_CD_B); | |
1582 | SDHI_PFC_PINS(sdhi1_ctrl_a, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6)); | |
1583 | SDHI_PFC_CTRL(sdhi1_ctrl_a, SD1_CLK_A, SD1_CMD_A); | |
1584 | SDHI_PFC_PINS(sdhi1_ctrl_b, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16)); | |
1585 | SDHI_PFC_CTRL(sdhi1_ctrl_b, SD1_CLK_B, SD1_CMD_B); | |
1586 | SDHI_PFC_PINS(sdhi1_data1_a, RCAR_GP_PIN(1, 7)); | |
1587 | SDHI_PFC_DAT1(sdhi1_data1_a, SD1_DAT0_A); | |
1588 | SDHI_PFC_PINS(sdhi1_data1_b, RCAR_GP_PIN(1, 18)); | |
1589 | SDHI_PFC_DAT1(sdhi1_data1_b, SD1_DAT0_B); | |
1590 | SDHI_PFC_PINS(sdhi1_data4_a, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8), | |
564617d2 | 1591 | RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6)); |
0290df2d | 1592 | SDHI_PFC_DAT4(sdhi1_data4_a, SD1_DAT0_A, SD1_DAT1_A, |
564617d2 | 1593 | SD1_DAT2_A, SD1_DAT3_A); |
0290df2d | 1594 | SDHI_PFC_PINS(sdhi1_data4_b, RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), |
564617d2 | 1595 | RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21)); |
0290df2d | 1596 | SDHI_PFC_DAT4(sdhi1_data4_b, SD1_DAT0_B, SD1_DAT1_B, |
564617d2 | 1597 | SD1_DAT2_B, SD1_DAT3_B); |
0290df2d KM |
1598 | SDHI_PFC_PINS(sdhi1_wp_a, RCAR_GP_PIN(0, 31)); |
1599 | SDHI_PFC_WPPN(sdhi1_wp_a, SD1_WP_A); | |
1600 | SDHI_PFC_PINS(sdhi1_wp_b, RCAR_GP_PIN(2, 25)); | |
1601 | SDHI_PFC_WPPN(sdhi1_wp_b, SD1_WP_B); | |
564617d2 KM |
1602 | |
1603 | /* - SDH2 ------------------------------------------------------------------- */ | |
0290df2d KM |
1604 | SDHI_PFC_PINS(sdhi2_cd_a, RCAR_GP_PIN(4, 23)); |
1605 | SDHI_PFC_CDPN(sdhi2_cd_a, SD2_CD_A); | |
1606 | SDHI_PFC_PINS(sdhi2_cd_b, RCAR_GP_PIN(3, 27)); | |
1607 | SDHI_PFC_CDPN(sdhi2_cd_b, SD2_CD_B); | |
1608 | SDHI_PFC_PINS(sdhi2_ctrl_a, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18)); | |
1609 | SDHI_PFC_CTRL(sdhi2_ctrl_a, SD2_CLK_A, SD2_CMD_A); | |
1610 | SDHI_PFC_PINS(sdhi2_ctrl_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6)); | |
1611 | SDHI_PFC_CTRL(sdhi2_ctrl_b, SD2_CLK_B, SD2_CMD_B); | |
1612 | SDHI_PFC_PINS(sdhi2_data1_a, RCAR_GP_PIN(4, 19)); | |
1613 | SDHI_PFC_DAT1(sdhi2_data1_a, SD2_DAT0_A); | |
1614 | SDHI_PFC_PINS(sdhi2_data1_b, RCAR_GP_PIN(4, 7)); | |
1615 | SDHI_PFC_DAT1(sdhi2_data1_b, SD2_DAT0_B); | |
1616 | SDHI_PFC_PINS(sdhi2_data4_a, RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20), | |
564617d2 | 1617 | RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22)); |
0290df2d | 1618 | SDHI_PFC_DAT4(sdhi2_data4_a, SD2_DAT0_A, SD2_DAT1_A, |
564617d2 | 1619 | SD2_DAT2_A, SD2_DAT3_A); |
0290df2d | 1620 | SDHI_PFC_PINS(sdhi2_data4_b, RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8), |
564617d2 | 1621 | RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26)); |
0290df2d | 1622 | SDHI_PFC_DAT4(sdhi2_data4_b, SD2_DAT0_B, SD2_DAT1_B, |
564617d2 | 1623 | SD2_DAT2_B, SD2_DAT3_B); |
0290df2d KM |
1624 | SDHI_PFC_PINS(sdhi2_wp_a, RCAR_GP_PIN(4, 24)); |
1625 | SDHI_PFC_WPPN(sdhi2_wp_a, SD2_WP_A); | |
1626 | SDHI_PFC_PINS(sdhi2_wp_b, RCAR_GP_PIN(3, 28)); | |
1627 | SDHI_PFC_WPPN(sdhi2_wp_b, SD2_WP_B); | |
564617d2 | 1628 | |
3ad8219a KM |
1629 | /* - SSI macro -------------------------------------------------------------- */ |
1630 | #define SSI_PFC_PINS(name, args...) SH_PFC_PINS(name, args) | |
1631 | #define SSI_PFC_CTRL(name, sck, ws) SH_PFC_MUX2(name, sck, ws) | |
1632 | #define SSI_PFC_DATA(name, d) SH_PFC_MUX1(name, d) | |
1633 | ||
1634 | /* - SSI 0/1/2 -------------------------------------------------------------- */ | |
1635 | SSI_PFC_PINS(ssi012_ctrl, RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7)); | |
1636 | SSI_PFC_CTRL(ssi012_ctrl, SSI_SCK012, SSI_WS012); | |
1637 | SSI_PFC_PINS(ssi0_data, RCAR_GP_PIN(3, 10)); | |
1638 | SSI_PFC_DATA(ssi0_data, SSI_SDATA0); | |
1639 | SSI_PFC_PINS(ssi1_a_ctrl, RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21)); | |
1640 | SSI_PFC_CTRL(ssi1_a_ctrl, SSI_SCK1_A, SSI_WS1_A); | |
1641 | SSI_PFC_PINS(ssi1_b_ctrl, PIN_NUMBER(3, 20), RCAR_GP_PIN(1, 3)); | |
1642 | SSI_PFC_CTRL(ssi1_b_ctrl, SSI_SCK1_B, SSI_WS1_B); | |
1643 | SSI_PFC_PINS(ssi1_data, RCAR_GP_PIN(3, 9)); | |
1644 | SSI_PFC_DATA(ssi1_data, SSI_SDATA1); | |
1645 | SSI_PFC_PINS(ssi2_a_ctrl, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(3, 4)); | |
1646 | SSI_PFC_CTRL(ssi2_a_ctrl, SSI_SCK2_A, SSI_WS2_A); | |
1647 | SSI_PFC_PINS(ssi2_b_ctrl, RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 17)); | |
1648 | SSI_PFC_CTRL(ssi2_b_ctrl, SSI_SCK2_B, SSI_WS2_B); | |
1649 | SSI_PFC_PINS(ssi2_data, RCAR_GP_PIN(3, 8)); | |
1650 | SSI_PFC_DATA(ssi2_data, SSI_SDATA2); | |
1651 | ||
1652 | /* - SSI 3/4 ---------------------------------------------------------------- */ | |
1653 | SSI_PFC_PINS(ssi34_ctrl, RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3)); | |
1654 | SSI_PFC_CTRL(ssi34_ctrl, SSI_SCK34, SSI_WS34); | |
1655 | SSI_PFC_PINS(ssi3_data, RCAR_GP_PIN(3, 5)); | |
1656 | SSI_PFC_DATA(ssi3_data, SSI_SDATA3); | |
1657 | SSI_PFC_PINS(ssi4_ctrl, RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23)); | |
1658 | SSI_PFC_CTRL(ssi4_ctrl, SSI_SCK4, SSI_WS4); | |
1659 | SSI_PFC_PINS(ssi4_data, RCAR_GP_PIN(3, 4)); | |
1660 | SSI_PFC_DATA(ssi4_data, SSI_SDATA4); | |
1661 | ||
1662 | /* - SSI 5 ------------------------------------------------------------------ */ | |
1663 | SSI_PFC_PINS(ssi5_ctrl, RCAR_GP_PIN(2, 31), RCAR_GP_PIN(3, 0)); | |
1664 | SSI_PFC_CTRL(ssi5_ctrl, SSI_SCK5, SSI_WS5); | |
1665 | SSI_PFC_PINS(ssi5_data, RCAR_GP_PIN(3, 1)); | |
1666 | SSI_PFC_DATA(ssi5_data, SSI_SDATA5); | |
1667 | ||
1668 | /* - SSI 6 ------------------------------------------------------------------ */ | |
1669 | SSI_PFC_PINS(ssi6_ctrl, RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 29)); | |
1670 | SSI_PFC_CTRL(ssi6_ctrl, SSI_SCK6, SSI_WS6); | |
1671 | SSI_PFC_PINS(ssi6_data, RCAR_GP_PIN(2, 30)); | |
1672 | SSI_PFC_DATA(ssi6_data, SSI_SDATA6); | |
1673 | ||
1674 | /* - SSI 7/8 --------------------------------------------------------------- */ | |
1675 | SSI_PFC_PINS(ssi78_ctrl, RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25)); | |
1676 | SSI_PFC_CTRL(ssi78_ctrl, SSI_SCK78, SSI_WS78); | |
1677 | SSI_PFC_PINS(ssi7_data, RCAR_GP_PIN(2, 27)); | |
1678 | SSI_PFC_DATA(ssi7_data, SSI_SDATA7); | |
1679 | SSI_PFC_PINS(ssi8_data, RCAR_GP_PIN(2, 26)); | |
1680 | SSI_PFC_DATA(ssi8_data, SSI_SDATA8); | |
1681 | ||
5cee53b6 SS |
1682 | /* - USB0 ------------------------------------------------------------------- */ |
1683 | SH_PFC_PINS(usb0, RCAR_GP_PIN(0, 1)); | |
1684 | SH_PFC_MUX1(usb0, PENC0); | |
1685 | SH_PFC_PINS(usb0_ovc, RCAR_GP_PIN(0, 3)); | |
1686 | SH_PFC_MUX1(usb0_ovc, USB_OVC0); | |
1687 | ||
1688 | /* - USB1 ------------------------------------------------------------------- */ | |
1689 | SH_PFC_PINS(usb1, RCAR_GP_PIN(0, 2)); | |
1690 | SH_PFC_MUX1(usb1, PENC1); | |
1691 | SH_PFC_PINS(usb1_ovc, RCAR_GP_PIN(0, 4)); | |
1692 | SH_PFC_MUX1(usb1_ovc, USB_OVC1); | |
1693 | ||
2d7cd398 VB |
1694 | /* - VIN macros ------------------------------------------------------------- */ |
1695 | #define VIN_PFC_PINS(name, args...) SH_PFC_PINS(name, args) | |
1696 | #define VIN_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \ | |
1697 | SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7) | |
1698 | #define VIN_PFC_CLK(name, clk) SH_PFC_MUX1(name, clk) | |
1699 | #define VIN_PFC_SYNC(name, hsync, vsync) SH_PFC_MUX2(name, hsync, vsync) | |
1700 | ||
1701 | /* - VIN0 ------------------------------------------------------------------- */ | |
1702 | VIN_PFC_PINS(vin0_data8, RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 30), | |
1703 | RCAR_GP_PIN(3, 31), RCAR_GP_PIN(4, 0), | |
1704 | RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), | |
1705 | RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4)); | |
1706 | VIN_PFC_DAT8(vin0_data8, VI0_DATA0_VI0_B0, VI0_DATA1_VI0_B1, | |
1707 | VI0_DATA2_VI0_B2, VI0_DATA3_VI0_B3, | |
1708 | VI0_DATA4_VI0_B4, VI0_DATA5_VI0_B5, | |
1709 | VI0_DATA6_VI0_G0, VI0_DATA7_VI0_G1); | |
1710 | VIN_PFC_PINS(vin0_clk, RCAR_GP_PIN(3, 24)); | |
1711 | VIN_PFC_CLK(vin0_clk, VI0_CLK); | |
1712 | VIN_PFC_PINS(vin0_sync, RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28)); | |
1713 | VIN_PFC_SYNC(vin0_sync, VI0_HSYNC, VI0_VSYNC); | |
1714 | /* - VIN1 ------------------------------------------------------------------- */ | |
1715 | VIN_PFC_PINS(vin1_data8, RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26), | |
1716 | RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), | |
1717 | RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6), | |
1718 | RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8)); | |
1719 | VIN_PFC_DAT8(vin1_data8, VI1_DATA0, VI1_DATA1, | |
1720 | VI1_DATA2, VI1_DATA3, | |
1721 | VI1_DATA4, VI1_DATA5, | |
1722 | VI1_DATA6, VI1_DATA7); | |
1723 | VIN_PFC_PINS(vin1_clk, RCAR_GP_PIN(4, 9)); | |
1724 | VIN_PFC_CLK(vin1_clk, VI1_CLK); | |
1725 | VIN_PFC_PINS(vin1_sync, RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22)); | |
1726 | VIN_PFC_SYNC(vin1_sync, VI1_HSYNC, VI1_VSYNC); | |
1727 | ||
87f8c988 | 1728 | static const struct sh_pfc_pin_group pinmux_groups[] = { |
3ad8219a KM |
1729 | SH_PFC_PIN_GROUP(audio_clk_a), |
1730 | SH_PFC_PIN_GROUP(audio_clk_b), | |
1731 | SH_PFC_PIN_GROUP(audio_clk_c), | |
1732 | SH_PFC_PIN_GROUP(audio_clkout_a), | |
1733 | SH_PFC_PIN_GROUP(audio_clkout_b), | |
24799c22 SS |
1734 | SH_PFC_PIN_GROUP(can0_data_a), |
1735 | SH_PFC_PIN_GROUP(can0_data_b), | |
1736 | SH_PFC_PIN_GROUP(can1_data_a), | |
1737 | SH_PFC_PIN_GROUP(can1_data_b), | |
1738 | SH_PFC_PIN_GROUP(can_clk_a), | |
1739 | SH_PFC_PIN_GROUP(can_clk_b), | |
1740 | SH_PFC_PIN_GROUP(can_clk_c), | |
1741 | SH_PFC_PIN_GROUP(can_clk_d), | |
3c5886d1 SS |
1742 | SH_PFC_PIN_GROUP(ether_rmii), |
1743 | SH_PFC_PIN_GROUP(ether_link), | |
1744 | SH_PFC_PIN_GROUP(ether_magic), | |
87f8c988 KM |
1745 | SH_PFC_PIN_GROUP(hscif0_data_a), |
1746 | SH_PFC_PIN_GROUP(hscif0_data_b), | |
1747 | SH_PFC_PIN_GROUP(hscif0_ctrl_a), | |
1748 | SH_PFC_PIN_GROUP(hscif0_ctrl_b), | |
1749 | SH_PFC_PIN_GROUP(hscif0_clk), | |
1750 | SH_PFC_PIN_GROUP(hscif1_data_a), | |
1751 | SH_PFC_PIN_GROUP(hscif1_data_b), | |
1752 | SH_PFC_PIN_GROUP(hscif1_ctrl_a), | |
1753 | SH_PFC_PIN_GROUP(hscif1_ctrl_b), | |
1754 | SH_PFC_PIN_GROUP(hscif1_clk_a), | |
1755 | SH_PFC_PIN_GROUP(hscif1_clk_b), | |
09cc76a9 KM |
1756 | SH_PFC_PIN_GROUP(hspi0_a), |
1757 | SH_PFC_PIN_GROUP(hspi0_b), | |
1758 | SH_PFC_PIN_GROUP(hspi1_a), | |
1759 | SH_PFC_PIN_GROUP(hspi1_b), | |
1760 | SH_PFC_PIN_GROUP(hspi2_a), | |
1761 | SH_PFC_PIN_GROUP(hspi2_b), | |
0dcbc69e KM |
1762 | SH_PFC_PIN_GROUP(i2c1_a), |
1763 | SH_PFC_PIN_GROUP(i2c1_b), | |
1764 | SH_PFC_PIN_GROUP(i2c2_a), | |
1765 | SH_PFC_PIN_GROUP(i2c2_b), | |
1766 | SH_PFC_PIN_GROUP(i2c2_c), | |
1767 | SH_PFC_PIN_GROUP(i2c3_a), | |
1768 | SH_PFC_PIN_GROUP(i2c3_b), | |
1769 | SH_PFC_PIN_GROUP(i2c3_c), | |
3ef2a776 KM |
1770 | SH_PFC_PIN_GROUP(mmc_ctrl), |
1771 | SH_PFC_PIN_GROUP(mmc_data1), | |
1772 | SH_PFC_PIN_GROUP(mmc_data4), | |
1773 | SH_PFC_PIN_GROUP(mmc_data8), | |
87f8c988 KM |
1774 | SH_PFC_PIN_GROUP(scif_clk), |
1775 | SH_PFC_PIN_GROUP(scif0_data_a), | |
1776 | SH_PFC_PIN_GROUP(scif0_data_b), | |
1777 | SH_PFC_PIN_GROUP(scif0_data_c), | |
1778 | SH_PFC_PIN_GROUP(scif0_data_d), | |
1779 | SH_PFC_PIN_GROUP(scif0_ctrl), | |
1780 | SH_PFC_PIN_GROUP(scif0_clk), | |
1781 | SH_PFC_PIN_GROUP(scif1_data_a), | |
1782 | SH_PFC_PIN_GROUP(scif1_data_b), | |
1783 | SH_PFC_PIN_GROUP(scif1_data_c), | |
1784 | SH_PFC_PIN_GROUP(scif1_data_d), | |
1785 | SH_PFC_PIN_GROUP(scif1_ctrl_a), | |
1786 | SH_PFC_PIN_GROUP(scif1_ctrl_c), | |
1787 | SH_PFC_PIN_GROUP(scif1_clk_a), | |
1788 | SH_PFC_PIN_GROUP(scif1_clk_c), | |
1789 | SH_PFC_PIN_GROUP(scif2_data_a), | |
1790 | SH_PFC_PIN_GROUP(scif2_data_b), | |
1791 | SH_PFC_PIN_GROUP(scif2_data_c), | |
1792 | SH_PFC_PIN_GROUP(scif2_data_d), | |
1793 | SH_PFC_PIN_GROUP(scif2_data_e), | |
1794 | SH_PFC_PIN_GROUP(scif2_clk_a), | |
1795 | SH_PFC_PIN_GROUP(scif2_clk_b), | |
1796 | SH_PFC_PIN_GROUP(scif2_clk_c), | |
1797 | SH_PFC_PIN_GROUP(scif3_data_a), | |
1798 | SH_PFC_PIN_GROUP(scif3_data_b), | |
1799 | SH_PFC_PIN_GROUP(scif3_data_c), | |
1800 | SH_PFC_PIN_GROUP(scif3_data_d), | |
1801 | SH_PFC_PIN_GROUP(scif4_data_a), | |
1802 | SH_PFC_PIN_GROUP(scif4_data_b), | |
1803 | SH_PFC_PIN_GROUP(scif4_data_c), | |
1804 | SH_PFC_PIN_GROUP(scif5_data_a), | |
1805 | SH_PFC_PIN_GROUP(scif5_data_b), | |
564617d2 KM |
1806 | SH_PFC_PIN_GROUP(sdhi0_cd), |
1807 | SH_PFC_PIN_GROUP(sdhi0_ctrl), | |
1808 | SH_PFC_PIN_GROUP(sdhi0_data1), | |
1809 | SH_PFC_PIN_GROUP(sdhi0_data4), | |
1810 | SH_PFC_PIN_GROUP(sdhi0_wp), | |
0290df2d KM |
1811 | SH_PFC_PIN_GROUP(sdhi1_cd_a), |
1812 | SH_PFC_PIN_GROUP(sdhi1_cd_b), | |
1813 | SH_PFC_PIN_GROUP(sdhi1_ctrl_a), | |
1814 | SH_PFC_PIN_GROUP(sdhi1_ctrl_b), | |
1815 | SH_PFC_PIN_GROUP(sdhi1_data1_a), | |
1816 | SH_PFC_PIN_GROUP(sdhi1_data1_b), | |
1817 | SH_PFC_PIN_GROUP(sdhi1_data4_a), | |
1818 | SH_PFC_PIN_GROUP(sdhi1_data4_b), | |
1819 | SH_PFC_PIN_GROUP(sdhi1_wp_a), | |
1820 | SH_PFC_PIN_GROUP(sdhi1_wp_b), | |
1821 | SH_PFC_PIN_GROUP(sdhi2_cd_a), | |
1822 | SH_PFC_PIN_GROUP(sdhi2_cd_b), | |
1823 | SH_PFC_PIN_GROUP(sdhi2_ctrl_a), | |
1824 | SH_PFC_PIN_GROUP(sdhi2_ctrl_b), | |
1825 | SH_PFC_PIN_GROUP(sdhi2_data1_a), | |
1826 | SH_PFC_PIN_GROUP(sdhi2_data1_b), | |
1827 | SH_PFC_PIN_GROUP(sdhi2_data4_a), | |
1828 | SH_PFC_PIN_GROUP(sdhi2_data4_b), | |
1829 | SH_PFC_PIN_GROUP(sdhi2_wp_a), | |
1830 | SH_PFC_PIN_GROUP(sdhi2_wp_b), | |
3ad8219a KM |
1831 | SH_PFC_PIN_GROUP(ssi012_ctrl), |
1832 | SH_PFC_PIN_GROUP(ssi0_data), | |
1833 | SH_PFC_PIN_GROUP(ssi1_a_ctrl), | |
1834 | SH_PFC_PIN_GROUP(ssi1_b_ctrl), | |
1835 | SH_PFC_PIN_GROUP(ssi1_data), | |
1836 | SH_PFC_PIN_GROUP(ssi2_a_ctrl), | |
1837 | SH_PFC_PIN_GROUP(ssi2_b_ctrl), | |
1838 | SH_PFC_PIN_GROUP(ssi2_data), | |
1839 | SH_PFC_PIN_GROUP(ssi34_ctrl), | |
1840 | SH_PFC_PIN_GROUP(ssi3_data), | |
1841 | SH_PFC_PIN_GROUP(ssi4_ctrl), | |
1842 | SH_PFC_PIN_GROUP(ssi4_data), | |
1843 | SH_PFC_PIN_GROUP(ssi5_ctrl), | |
1844 | SH_PFC_PIN_GROUP(ssi5_data), | |
1845 | SH_PFC_PIN_GROUP(ssi6_ctrl), | |
1846 | SH_PFC_PIN_GROUP(ssi6_data), | |
1847 | SH_PFC_PIN_GROUP(ssi78_ctrl), | |
1848 | SH_PFC_PIN_GROUP(ssi7_data), | |
1849 | SH_PFC_PIN_GROUP(ssi8_data), | |
5cee53b6 SS |
1850 | SH_PFC_PIN_GROUP(usb0), |
1851 | SH_PFC_PIN_GROUP(usb0_ovc), | |
1852 | SH_PFC_PIN_GROUP(usb1), | |
1853 | SH_PFC_PIN_GROUP(usb1_ovc), | |
2d7cd398 VB |
1854 | SH_PFC_PIN_GROUP(vin0_data8), |
1855 | SH_PFC_PIN_GROUP(vin0_clk), | |
1856 | SH_PFC_PIN_GROUP(vin0_sync), | |
1857 | SH_PFC_PIN_GROUP(vin1_data8), | |
1858 | SH_PFC_PIN_GROUP(vin1_clk), | |
1859 | SH_PFC_PIN_GROUP(vin1_sync), | |
87f8c988 KM |
1860 | }; |
1861 | ||
3ad8219a KM |
1862 | static const char * const audio_clk_groups[] = { |
1863 | "audio_clk_a", | |
1864 | "audio_clk_b", | |
1865 | "audio_clk_c", | |
1866 | "audio_clkout_a", | |
1867 | "audio_clkout_b", | |
1868 | }; | |
1869 | ||
24799c22 SS |
1870 | static const char * const can0_groups[] = { |
1871 | "can0_data_a", | |
1872 | "can0_data_b", | |
1873 | "can_clk_a", | |
1874 | "can_clk_b", | |
1875 | "can_clk_c", | |
1876 | "can_clk_d", | |
1877 | }; | |
1878 | ||
1879 | static const char * const can1_groups[] = { | |
1880 | "can1_data_a", | |
1881 | "can1_data_b", | |
1882 | "can_clk_a", | |
1883 | "can_clk_b", | |
1884 | "can_clk_c", | |
1885 | "can_clk_d", | |
1886 | }; | |
1887 | ||
3c5886d1 SS |
1888 | static const char * const ether_groups[] = { |
1889 | "ether_rmii", | |
1890 | "ether_link", | |
1891 | "ether_magic", | |
1892 | }; | |
1893 | ||
87f8c988 KM |
1894 | static const char * const hscif0_groups[] = { |
1895 | "hscif0_data_a", | |
1896 | "hscif0_data_b", | |
1897 | "hscif0_ctrl_a", | |
1898 | "hscif0_ctrl_b", | |
1899 | "hscif0_clk", | |
1900 | }; | |
1901 | ||
1902 | static const char * const hscif1_groups[] = { | |
1903 | "hscif1_data_a", | |
1904 | "hscif1_data_b", | |
1905 | "hscif1_ctrl_a", | |
1906 | "hscif1_ctrl_b", | |
1907 | "hscif1_clk_a", | |
1908 | "hscif1_clk_b", | |
1909 | }; | |
1910 | ||
09cc76a9 KM |
1911 | static const char * const hspi0_groups[] = { |
1912 | "hspi0_a", | |
1913 | "hspi0_b", | |
1914 | }; | |
1915 | ||
1916 | static const char * const hspi1_groups[] = { | |
1917 | "hspi1_a", | |
1918 | "hspi1_b", | |
1919 | }; | |
1920 | ||
1921 | static const char * const hspi2_groups[] = { | |
1922 | "hspi2_a", | |
1923 | "hspi2_b", | |
1924 | }; | |
1925 | ||
0dcbc69e KM |
1926 | static const char * const i2c1_groups[] = { |
1927 | "i2c1_a", | |
1928 | "i2c1_b", | |
1929 | }; | |
1930 | ||
1931 | static const char * const i2c2_groups[] = { | |
1932 | "i2c2_a", | |
1933 | "i2c2_b", | |
1934 | "i2c2_c", | |
1935 | }; | |
1936 | ||
1937 | static const char * const i2c3_groups[] = { | |
1938 | "i2c3_a", | |
1939 | "i2c3_b", | |
1940 | "i2c3_c", | |
1941 | }; | |
1942 | ||
3ef2a776 KM |
1943 | static const char * const mmc_groups[] = { |
1944 | "mmc_ctrl", | |
1945 | "mmc_data1", | |
1946 | "mmc_data4", | |
1947 | "mmc_data8", | |
1948 | }; | |
1949 | ||
87f8c988 KM |
1950 | static const char * const scif_clk_groups[] = { |
1951 | "scif_clk", | |
1952 | }; | |
1953 | ||
1954 | static const char * const scif0_groups[] = { | |
1955 | "scif0_data_a", | |
1956 | "scif0_data_b", | |
1957 | "scif0_data_c", | |
1958 | "scif0_data_d", | |
1959 | "scif0_ctrl", | |
1960 | "scif0_clk", | |
1961 | }; | |
1962 | ||
1963 | static const char * const scif1_groups[] = { | |
1964 | "scif1_data_a", | |
1965 | "scif1_data_b", | |
1966 | "scif1_data_c", | |
1967 | "scif1_data_d", | |
1968 | "scif1_ctrl_a", | |
1969 | "scif1_ctrl_c", | |
1970 | "scif1_clk_a", | |
1971 | "scif1_clk_c", | |
1972 | }; | |
1973 | ||
1974 | static const char * const scif2_groups[] = { | |
1975 | "scif2_data_a", | |
1976 | "scif2_data_b", | |
1977 | "scif2_data_c", | |
1978 | "scif2_data_d", | |
1979 | "scif2_data_e", | |
1980 | "scif2_clk_a", | |
1981 | "scif2_clk_b", | |
1982 | "scif2_clk_c", | |
1983 | }; | |
1984 | ||
1985 | static const char * const scif3_groups[] = { | |
1986 | "scif3_data_a", | |
1987 | "scif3_data_b", | |
1988 | "scif3_data_c", | |
1989 | "scif3_data_d", | |
1990 | }; | |
1991 | ||
1992 | static const char * const scif4_groups[] = { | |
1993 | "scif4_data_a", | |
1994 | "scif4_data_b", | |
1995 | "scif4_data_c", | |
1996 | }; | |
1997 | ||
1998 | static const char * const scif5_groups[] = { | |
1999 | "scif5_data_a", | |
2000 | "scif5_data_b", | |
2001 | }; | |
2002 | ||
564617d2 KM |
2003 | |
2004 | static const char * const sdhi0_groups[] = { | |
2005 | "sdhi0_cd", | |
2006 | "sdhi0_ctrl", | |
2007 | "sdhi0_data1", | |
2008 | "sdhi0_data4", | |
2009 | "sdhi0_wp", | |
2010 | }; | |
2011 | ||
2012 | static const char * const sdhi1_groups[] = { | |
0290df2d KM |
2013 | "sdhi1_cd_a", |
2014 | "sdhi1_cd_b", | |
2015 | "sdhi1_ctrl_a", | |
2016 | "sdhi1_ctrl_b", | |
2017 | "sdhi1_data1_a", | |
2018 | "sdhi1_data1_b", | |
2019 | "sdhi1_data4_a", | |
2020 | "sdhi1_data4_b", | |
2021 | "sdhi1_wp_a", | |
2022 | "sdhi1_wp_b", | |
564617d2 KM |
2023 | }; |
2024 | ||
2025 | static const char * const sdhi2_groups[] = { | |
0290df2d KM |
2026 | "sdhi2_cd_a", |
2027 | "sdhi2_cd_b", | |
2028 | "sdhi2_ctrl_a", | |
2029 | "sdhi2_ctrl_b", | |
2030 | "sdhi2_data1_a", | |
2031 | "sdhi2_data1_b", | |
2032 | "sdhi2_data4_a", | |
2033 | "sdhi2_data4_b", | |
2034 | "sdhi2_wp_a", | |
2035 | "sdhi2_wp_b", | |
564617d2 KM |
2036 | }; |
2037 | ||
3ad8219a KM |
2038 | static const char * const ssi_groups[] = { |
2039 | "ssi012_ctrl", | |
2040 | "ssi0_data", | |
2041 | "ssi1_a_ctrl", | |
2042 | "ssi1_b_ctrl", | |
2043 | "ssi1_data", | |
2044 | "ssi2_a_ctrl", | |
2045 | "ssi2_b_ctrl", | |
2046 | "ssi2_data", | |
2047 | "ssi34_ctrl", | |
2048 | "ssi3_data", | |
2049 | "ssi4_ctrl", | |
2050 | "ssi4_data", | |
2051 | "ssi5_ctrl", | |
2052 | "ssi5_data", | |
2053 | "ssi6_ctrl", | |
2054 | "ssi6_data", | |
2055 | "ssi78_ctrl", | |
2056 | "ssi7_data", | |
2057 | "ssi8_data", | |
2058 | }; | |
2059 | ||
5cee53b6 SS |
2060 | static const char * const usb0_groups[] = { |
2061 | "usb0", | |
2062 | "usb0_ovc", | |
2063 | }; | |
2064 | ||
2065 | static const char * const usb1_groups[] = { | |
2066 | "usb1", | |
2067 | "usb1_ovc", | |
2068 | }; | |
2069 | ||
2d7cd398 VB |
2070 | static const char * const vin0_groups[] = { |
2071 | "vin0_data8", | |
2072 | "vin0_clk", | |
2073 | "vin0_sync", | |
2074 | }; | |
2075 | ||
2076 | static const char * const vin1_groups[] = { | |
2077 | "vin1_data8", | |
2078 | "vin1_clk", | |
2079 | "vin1_sync", | |
2080 | }; | |
2081 | ||
87f8c988 | 2082 | static const struct sh_pfc_function pinmux_functions[] = { |
3ad8219a | 2083 | SH_PFC_FUNCTION(audio_clk), |
24799c22 SS |
2084 | SH_PFC_FUNCTION(can0), |
2085 | SH_PFC_FUNCTION(can1), | |
3c5886d1 | 2086 | SH_PFC_FUNCTION(ether), |
87f8c988 KM |
2087 | SH_PFC_FUNCTION(hscif0), |
2088 | SH_PFC_FUNCTION(hscif1), | |
09cc76a9 KM |
2089 | SH_PFC_FUNCTION(hspi0), |
2090 | SH_PFC_FUNCTION(hspi1), | |
2091 | SH_PFC_FUNCTION(hspi2), | |
0dcbc69e KM |
2092 | SH_PFC_FUNCTION(i2c1), |
2093 | SH_PFC_FUNCTION(i2c2), | |
2094 | SH_PFC_FUNCTION(i2c3), | |
3ef2a776 | 2095 | SH_PFC_FUNCTION(mmc), |
87f8c988 KM |
2096 | SH_PFC_FUNCTION(scif_clk), |
2097 | SH_PFC_FUNCTION(scif0), | |
2098 | SH_PFC_FUNCTION(scif1), | |
2099 | SH_PFC_FUNCTION(scif2), | |
2100 | SH_PFC_FUNCTION(scif3), | |
2101 | SH_PFC_FUNCTION(scif4), | |
2102 | SH_PFC_FUNCTION(scif5), | |
564617d2 KM |
2103 | SH_PFC_FUNCTION(sdhi0), |
2104 | SH_PFC_FUNCTION(sdhi1), | |
2105 | SH_PFC_FUNCTION(sdhi2), | |
3ad8219a | 2106 | SH_PFC_FUNCTION(ssi), |
5cee53b6 SS |
2107 | SH_PFC_FUNCTION(usb0), |
2108 | SH_PFC_FUNCTION(usb1), | |
2d7cd398 VB |
2109 | SH_PFC_FUNCTION(vin0), |
2110 | SH_PFC_FUNCTION(vin1), | |
87f8c988 KM |
2111 | }; |
2112 | ||
44a45b55 | 2113 | static const struct pinmux_cfg_reg pinmux_config_regs[] = { |
87f8c988 KM |
2114 | { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) { |
2115 | GP_0_31_FN, FN_IP1_14_11, | |
2116 | GP_0_30_FN, FN_IP1_10_8, | |
2117 | GP_0_29_FN, FN_IP1_7_5, | |
2118 | GP_0_28_FN, FN_IP1_4_2, | |
2119 | GP_0_27_FN, FN_IP1_1, | |
2120 | GP_0_26_FN, FN_IP1_0, | |
2121 | GP_0_25_FN, FN_IP0_30, | |
2122 | GP_0_24_FN, FN_IP0_29, | |
2123 | GP_0_23_FN, FN_IP0_28, | |
2124 | GP_0_22_FN, FN_IP0_27, | |
2125 | GP_0_21_FN, FN_IP0_26, | |
2126 | GP_0_20_FN, FN_IP0_25, | |
2127 | GP_0_19_FN, FN_IP0_24, | |
2128 | GP_0_18_FN, FN_IP0_23, | |
2129 | GP_0_17_FN, FN_IP0_22, | |
2130 | GP_0_16_FN, FN_IP0_21, | |
2131 | GP_0_15_FN, FN_IP0_20, | |
2132 | GP_0_14_FN, FN_IP0_19, | |
2133 | GP_0_13_FN, FN_IP0_18, | |
2134 | GP_0_12_FN, FN_IP0_17, | |
2135 | GP_0_11_FN, FN_IP0_16, | |
2136 | GP_0_10_FN, FN_IP0_15, | |
2137 | GP_0_9_FN, FN_A3, | |
2138 | GP_0_8_FN, FN_A2, | |
2139 | GP_0_7_FN, FN_A1, | |
2140 | GP_0_6_FN, FN_IP0_14_12, | |
2141 | GP_0_5_FN, FN_IP0_11_8, | |
2142 | GP_0_4_FN, FN_IP0_7_5, | |
2143 | GP_0_3_FN, FN_IP0_4_2, | |
2144 | GP_0_2_FN, FN_PENC1, | |
2145 | GP_0_1_FN, FN_PENC0, | |
2146 | GP_0_0_FN, FN_IP0_1_0 } | |
2147 | }, | |
2148 | { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) { | |
2149 | GP_1_31_FN, FN_IP4_6_4, | |
2150 | GP_1_30_FN, FN_IP4_3_1, | |
2151 | GP_1_29_FN, FN_IP4_0, | |
2152 | GP_1_28_FN, FN_IP3_31, | |
2153 | GP_1_27_FN, FN_IP3_30, | |
2154 | GP_1_26_FN, FN_IP3_29, | |
2155 | GP_1_25_FN, FN_IP3_28, | |
2156 | GP_1_24_FN, FN_IP3_27, | |
2157 | GP_1_23_FN, FN_IP3_26_24, | |
2158 | GP_1_22_FN, FN_IP3_23_21, | |
2159 | GP_1_21_FN, FN_IP3_20_19, | |
2160 | GP_1_20_FN, FN_IP3_18_16, | |
2161 | GP_1_19_FN, FN_IP3_15_13, | |
2162 | GP_1_18_FN, FN_IP3_12_10, | |
2163 | GP_1_17_FN, FN_IP3_9_8, | |
2164 | GP_1_16_FN, FN_IP3_7_5, | |
2165 | GP_1_15_FN, FN_IP3_4_2, | |
2166 | GP_1_14_FN, FN_IP3_1_0, | |
2167 | GP_1_13_FN, FN_IP2_31, | |
2168 | GP_1_12_FN, FN_IP2_30, | |
2169 | GP_1_11_FN, FN_IP2_17, | |
2170 | GP_1_10_FN, FN_IP2_16_14, | |
2171 | GP_1_9_FN, FN_IP2_13_12, | |
2172 | GP_1_8_FN, FN_IP2_11_9, | |
2173 | GP_1_7_FN, FN_IP2_8_6, | |
2174 | GP_1_6_FN, FN_IP2_5_3, | |
2175 | GP_1_5_FN, FN_IP2_2_0, | |
2176 | GP_1_4_FN, FN_IP1_29_28, | |
2177 | GP_1_3_FN, FN_IP1_27_25, | |
2178 | GP_1_2_FN, FN_IP1_24, | |
2179 | GP_1_1_FN, FN_WE0, | |
2180 | GP_1_0_FN, FN_IP1_23_21 } | |
2181 | }, | |
2182 | { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) { | |
2183 | GP_2_31_FN, FN_IP6_7, | |
2184 | GP_2_30_FN, FN_IP6_6_5, | |
2185 | GP_2_29_FN, FN_IP6_4_2, | |
2186 | GP_2_28_FN, FN_IP6_1_0, | |
2187 | GP_2_27_FN, FN_IP5_30_29, | |
2188 | GP_2_26_FN, FN_IP5_28_26, | |
2189 | GP_2_25_FN, FN_IP5_25_23, | |
2190 | GP_2_24_FN, FN_IP5_22_21, | |
2191 | GP_2_23_FN, FN_AUDIO_CLKB, | |
2192 | GP_2_22_FN, FN_AUDIO_CLKA, | |
2193 | GP_2_21_FN, FN_IP5_20_18, | |
2194 | GP_2_20_FN, FN_IP5_17_15, | |
2195 | GP_2_19_FN, FN_IP5_14_13, | |
2196 | GP_2_18_FN, FN_IP5_12, | |
2197 | GP_2_17_FN, FN_IP5_11_10, | |
2198 | GP_2_16_FN, FN_IP5_9_8, | |
2199 | GP_2_15_FN, FN_IP5_7, | |
2200 | GP_2_14_FN, FN_IP5_6, | |
2201 | GP_2_13_FN, FN_IP5_5_4, | |
2202 | GP_2_12_FN, FN_IP5_3_2, | |
2203 | GP_2_11_FN, FN_IP5_1_0, | |
2204 | GP_2_10_FN, FN_IP4_30_29, | |
2205 | GP_2_9_FN, FN_IP4_28_27, | |
2206 | GP_2_8_FN, FN_IP4_26_25, | |
2207 | GP_2_7_FN, FN_IP4_24_21, | |
2208 | GP_2_6_FN, FN_IP4_20_17, | |
2209 | GP_2_5_FN, FN_IP4_16_15, | |
2210 | GP_2_4_FN, FN_IP4_14_13, | |
2211 | GP_2_3_FN, FN_IP4_12_11, | |
2212 | GP_2_2_FN, FN_IP4_10_9, | |
2213 | GP_2_1_FN, FN_IP4_8, | |
2214 | GP_2_0_FN, FN_IP4_7 } | |
2215 | }, | |
2216 | { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) { | |
2217 | GP_3_31_FN, FN_IP8_10_9, | |
2218 | GP_3_30_FN, FN_IP8_8_6, | |
2219 | GP_3_29_FN, FN_IP8_5_3, | |
2220 | GP_3_28_FN, FN_IP8_2_0, | |
2221 | GP_3_27_FN, FN_IP7_31_29, | |
2222 | GP_3_26_FN, FN_IP7_28_25, | |
2223 | GP_3_25_FN, FN_IP7_24_22, | |
2224 | GP_3_24_FN, FN_IP7_21, | |
2225 | GP_3_23_FN, FN_IP7_20_18, | |
2226 | GP_3_22_FN, FN_IP7_17_15, | |
2227 | GP_3_21_FN, FN_IP7_14_12, | |
2228 | GP_3_20_FN, FN_IP7_11_9, | |
2229 | GP_3_19_FN, FN_IP7_8_6, | |
2230 | GP_3_18_FN, FN_IP7_5_4, | |
2231 | GP_3_17_FN, FN_IP7_3_2, | |
2232 | GP_3_16_FN, FN_IP7_1_0, | |
2233 | GP_3_15_FN, FN_IP6_31_30, | |
2234 | GP_3_14_FN, FN_IP6_29_28, | |
2235 | GP_3_13_FN, FN_IP6_27_26, | |
2236 | GP_3_12_FN, FN_IP6_25_24, | |
2237 | GP_3_11_FN, FN_IP6_23_22, | |
2238 | GP_3_10_FN, FN_IP6_21, | |
2239 | GP_3_9_FN, FN_IP6_20_19, | |
2240 | GP_3_8_FN, FN_IP6_18_17, | |
2241 | GP_3_7_FN, FN_IP6_16, | |
2242 | GP_3_6_FN, FN_IP6_15_14, | |
2243 | GP_3_5_FN, FN_IP6_13, | |
2244 | GP_3_4_FN, FN_IP6_12_11, | |
2245 | GP_3_3_FN, FN_IP6_10, | |
2246 | GP_3_2_FN, FN_SSI_SCK34, | |
2247 | GP_3_1_FN, FN_IP6_9, | |
2248 | GP_3_0_FN, FN_IP6_8 } | |
2249 | }, | |
2250 | { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) { | |
2251 | 0, 0, | |
2252 | 0, 0, | |
2253 | 0, 0, | |
2254 | 0, 0, | |
2255 | 0, 0, | |
2256 | GP_4_26_FN, FN_AVS2, | |
2257 | GP_4_25_FN, FN_AVS1, | |
2258 | GP_4_24_FN, FN_IP10_24_22, | |
2259 | GP_4_23_FN, FN_IP10_21_19, | |
2260 | GP_4_22_FN, FN_IP10_18_16, | |
2261 | GP_4_21_FN, FN_IP10_15_13, | |
2262 | GP_4_20_FN, FN_IP10_12_9, | |
2263 | GP_4_19_FN, FN_IP10_8_6, | |
2264 | GP_4_18_FN, FN_IP10_5_3, | |
2265 | GP_4_17_FN, FN_IP10_2_0, | |
2266 | GP_4_16_FN, FN_IP9_29_27, | |
2267 | GP_4_15_FN, FN_IP9_26_24, | |
2268 | GP_4_14_FN, FN_IP9_23_21, | |
2269 | GP_4_13_FN, FN_IP9_20_18, | |
2270 | GP_4_12_FN, FN_IP9_17_15, | |
2271 | GP_4_11_FN, FN_IP9_14_12, | |
2272 | GP_4_10_FN, FN_IP9_11_9, | |
2273 | GP_4_9_FN, FN_IP9_8_6, | |
2274 | GP_4_8_FN, FN_IP9_5_3, | |
2275 | GP_4_7_FN, FN_IP9_2_0, | |
2276 | GP_4_6_FN, FN_IP8_29_27, | |
2277 | GP_4_5_FN, FN_IP8_26_24, | |
2278 | GP_4_4_FN, FN_IP8_23_22, | |
2279 | GP_4_3_FN, FN_IP8_21_19, | |
2280 | GP_4_2_FN, FN_IP8_18_16, | |
2281 | GP_4_1_FN, FN_IP8_15_14, | |
2282 | GP_4_0_FN, FN_IP8_13_11 } | |
2283 | }, | |
2284 | ||
2285 | { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32, | |
2286 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, | |
2287 | 1, 1, 1, 1, 1, 1, 3, 4, 3, 3, 2) { | |
2288 | /* IP0_31 [1] */ | |
2289 | 0, 0, | |
2290 | /* IP0_30 [1] */ | |
2291 | FN_A19, 0, | |
2292 | /* IP0_29 [1] */ | |
2293 | FN_A18, 0, | |
2294 | /* IP0_28 [1] */ | |
2295 | FN_A17, 0, | |
2296 | /* IP0_27 [1] */ | |
2297 | FN_A16, 0, | |
2298 | /* IP0_26 [1] */ | |
2299 | FN_A15, 0, | |
2300 | /* IP0_25 [1] */ | |
2301 | FN_A14, 0, | |
2302 | /* IP0_24 [1] */ | |
2303 | FN_A13, 0, | |
2304 | /* IP0_23 [1] */ | |
2305 | FN_A12, 0, | |
2306 | /* IP0_22 [1] */ | |
2307 | FN_A11, 0, | |
2308 | /* IP0_21 [1] */ | |
2309 | FN_A10, 0, | |
2310 | /* IP0_20 [1] */ | |
2311 | FN_A9, 0, | |
2312 | /* IP0_19 [1] */ | |
2313 | FN_A8, 0, | |
2314 | /* IP0_18 [1] */ | |
2315 | FN_A7, 0, | |
2316 | /* IP0_17 [1] */ | |
2317 | FN_A6, 0, | |
2318 | /* IP0_16 [1] */ | |
2319 | FN_A5, 0, | |
2320 | /* IP0_15 [1] */ | |
2321 | FN_A4, 0, | |
2322 | /* IP0_14_12 [3] */ | |
2323 | FN_SD1_DAT3_A, FN_MMC_D3, 0, FN_A0, | |
2324 | FN_ATAG0_A, 0, FN_REMOCON_B, 0, | |
2325 | /* IP0_11_8 [4] */ | |
2326 | FN_SD1_DAT2_A, FN_MMC_D2, 0, FN_BS, | |
2327 | FN_ATADIR0_A, 0, FN_SDSELF_B, 0, | |
2328 | FN_PWM4_B, 0, 0, 0, | |
2329 | 0, 0, 0, 0, | |
2330 | /* IP0_7_5 [3] */ | |
2331 | FN_AUDATA1, FN_ARM_TRACEDATA_1, FN_GPSIN_C, FN_USB_OVC1, | |
2332 | FN_RX2_E, FN_SCL2_B, 0, 0, | |
2333 | /* IP0_4_2 [3] */ | |
2334 | FN_AUDATA0, FN_ARM_TRACEDATA_0, FN_GPSCLK_C, FN_USB_OVC0, | |
2335 | FN_TX2_E, FN_SDA2_B, 0, 0, | |
2336 | /* IP0_1_0 [2] */ | |
2337 | FN_PRESETOUT, 0, FN_PWM1, 0, | |
2338 | } | |
2339 | }, | |
2340 | { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32, | |
2341 | 1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3, 3, 1, 1) { | |
2342 | /* IP1_31 [1] */ | |
2343 | 0, 0, | |
2344 | /* IP1_30 [1] */ | |
2345 | 0, 0, | |
2346 | /* IP1_29_28 [2] */ | |
2347 | FN_EX_CS1, FN_MMC_D4, 0, 0, | |
2348 | /* IP1_27_25 [3] */ | |
2349 | FN_SSI_WS1_B, FN_EX_CS0, FN_SCL2_A, FN_TX3_C, | |
2350 | FN_TS_SCK0_A, 0, 0, 0, | |
2351 | /* IP1_24 [1] */ | |
2352 | FN_WE1, FN_ATAWR0_B, | |
2353 | /* IP1_23_21 [3] */ | |
2354 | FN_MMC_D5, FN_ATADIR0_B, 0, FN_RD_WR, | |
2355 | 0, 0, 0, 0, | |
2356 | /* IP1_20_18 [3] */ | |
2357 | FN_SSI_SCK1_B, FN_ATAG0_B, FN_CS1_A26, FN_SDA2_A, | |
2358 | FN_SCK2_B, 0, 0, 0, | |
2359 | /* IP1_17 [1] */ | |
2360 | FN_CS0, FN_HSPI_RX1_B, | |
2361 | /* IP1_16_15 [2] */ | |
2362 | FN_CLKOUT, FN_HSPI_TX1_B, FN_PWM0_B, 0, | |
2363 | /* IP1_14_11 [4] */ | |
2364 | FN_SD1_WP_A, FN_MMC_D7, 0, FN_A25, | |
2365 | FN_DACK1_A, 0, FN_HCTS0_B, FN_RX3_C, | |
2366 | FN_TS_SDAT0_A, 0, 0, 0, | |
2367 | 0, 0, 0, 0, | |
2368 | /* IP1_10_8 [3] */ | |
2369 | FN_SD1_CLK_B, FN_MMC_D6, 0, FN_A24, | |
2370 | FN_DREQ1_A, 0, FN_HRX0_B, FN_TS_SPSYNC0_A, | |
2371 | /* IP1_7_5 [3] */ | |
2372 | FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A, | |
2373 | FN_TS_SDEN0_A, 0, 0, 0, | |
2374 | /* IP1_4_2 [3] */ | |
2375 | FN_A22, FN_HRTS0_B, FN_RX2_B, FN_DREQ2_A, | |
2376 | 0, 0, 0, 0, | |
2377 | /* IP1_1 [1] */ | |
2378 | FN_A21, FN_HSPI_CLK1_B, | |
2379 | /* IP1_0 [1] */ | |
2380 | FN_A20, FN_HSPI_CS1_B, | |
2381 | } | |
2382 | }, | |
2383 | { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32, | |
2384 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, | |
2385 | 1, 1, 1, 1, 3, 2, 3, 3, 3, 3) { | |
2386 | /* IP2_31 [1] */ | |
d64d0050 | 2387 | FN_MLB_CLK, FN_IRQ1_A, |
87f8c988 KM |
2388 | /* IP2_30 [1] */ |
2389 | FN_RD_WR_B, FN_IRQ0, | |
2390 | /* IP2_29 [1] */ | |
2391 | FN_D11, 0, | |
2392 | /* IP2_28 [1] */ | |
2393 | FN_D10, 0, | |
2394 | /* IP2_27 [1] */ | |
2395 | FN_D9, 0, | |
2396 | /* IP2_26 [1] */ | |
2397 | FN_D8, 0, | |
2398 | /* IP2_25 [1] */ | |
2399 | FN_D7, 0, | |
2400 | /* IP2_24 [1] */ | |
2401 | FN_D6, 0, | |
2402 | /* IP2_23 [1] */ | |
2403 | FN_D5, 0, | |
2404 | /* IP2_22 [1] */ | |
2405 | FN_D4, 0, | |
2406 | /* IP2_21 [1] */ | |
2407 | FN_D3, 0, | |
2408 | /* IP2_20 [1] */ | |
2409 | FN_D2, 0, | |
2410 | /* IP2_19 [1] */ | |
2411 | FN_D1, 0, | |
2412 | /* IP2_18 [1] */ | |
2413 | FN_D0, 0, | |
2414 | /* IP2_17 [1] */ | |
2415 | FN_EX_WAIT0, FN_PWM0_C, | |
2416 | /* IP2_16_14 [3] */ | |
2417 | FN_DACK0, 0, 0, FN_TX3_A, | |
2418 | FN_DRACK0, 0, 0, 0, | |
2419 | /* IP2_13_12 [2] */ | |
2420 | FN_DREQ0_A, 0, 0, FN_RX3_A, | |
2421 | /* IP2_11_9 [3] */ | |
2422 | FN_SD1_DAT1_A, FN_MMC_D1, 0, FN_ATAWR0_A, | |
2423 | FN_EX_CS5, FN_EX_WAIT2_A, 0, 0, | |
2424 | /* IP2_8_6 [3] */ | |
2425 | FN_SD1_DAT0_A, FN_MMC_D0, 0, FN_ATARD0, | |
2426 | FN_EX_CS4, FN_EX_WAIT1_A, 0, 0, | |
2427 | /* IP2_5_3 [3] */ | |
2428 | FN_SD1_CMD_A, FN_MMC_CMD, 0, FN_ATACS10, | |
2429 | FN_EX_CS3, 0, 0, 0, | |
2430 | /* IP2_2_0 [3] */ | |
2431 | FN_SD1_CLK_A, FN_MMC_CLK, 0, FN_ATACS00, | |
2432 | FN_EX_CS2, 0, 0, 0, | |
2433 | } | |
2434 | }, | |
2435 | { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32, | |
2436 | 1, 1, 1, 1, 1, 3, 3, 2, | |
2437 | 3, 3, 3, 2, 3, 3, 2) { | |
2438 | /* IP3_31 [1] */ | |
2439 | FN_DU0_DR6, FN_LCDOUT6, | |
2440 | /* IP3_30 [1] */ | |
2441 | FN_DU0_DR5, FN_LCDOUT5, | |
2442 | /* IP3_29 [1] */ | |
2443 | FN_DU0_DR4, FN_LCDOUT4, | |
2444 | /* IP3_28 [1] */ | |
2445 | FN_DU0_DR3, FN_LCDOUT3, | |
2446 | /* IP3_27 [1] */ | |
2447 | FN_DU0_DR2, FN_LCDOUT2, | |
2448 | /* IP3_26_24 [3] */ | |
2449 | FN_SSI_WS4, FN_DU0_DR1, FN_LCDOUT1, FN_AUDATA3, | |
2450 | FN_ARM_TRACEDATA_3, FN_SCL3_C, FN_ADICHS2, FN_TS_SPSYNC0_B, | |
2451 | /* IP3_23_21 [3] */ | |
2452 | FN_SSI_SCK4, FN_DU0_DR0, FN_LCDOUT0, FN_AUDATA2, | |
2453 | FN_ARM_TRACEDATA_2, FN_SDA3_C, FN_ADICHS1, FN_TS_SDEN0_B, | |
2454 | /* IP3_20_19 [2] */ | |
2455 | FN_SD1_DAT3_B, FN_HRTS0_A, FN_RTS0, 0, | |
2456 | /* IP3_18_16 [3] */ | |
2457 | FN_SD1_DAT2_B, FN_HCTS0_A, FN_CTS0, 0, | |
2458 | 0, 0, 0, 0, | |
2459 | /* IP3_15_13 [3] */ | |
2460 | FN_SD1_DAT1_B, FN_HSCK0, FN_SCK0, FN_SCL3_B, | |
2461 | 0, 0, 0, 0, | |
2462 | /* IP3_12_10 [3] */ | |
2463 | FN_SD1_DAT0_B, FN_HRX0_A, FN_RX0_A, 0, | |
2464 | 0, 0, 0, 0, | |
2465 | /* IP3_9_8 [2] */ | |
2466 | FN_SD1_CLK_B, FN_HTX0_A, FN_TX0_A, 0, | |
2467 | /* IP3_7_5 [3] */ | |
2468 | FN_SD1_CMD_B, FN_SCIF_CLK, FN_AUDIO_CLKOUT_B, FN_CAN_CLK_B, | |
2469 | FN_SDA3_B, 0, 0, 0, | |
2470 | /* IP3_4_2 [3] */ | |
2471 | FN_MLB_DAT, FN_TX5_B, FN_SCL3_A, FN_IRQ3_A, | |
2472 | FN_SDSELF_B, 0, 0, 0, | |
2473 | /* IP3_1_0 [2] */ | |
2474 | FN_MLB_SIG, FN_RX5_B, FN_SDA3_A, FN_IRQ2_A, | |
2475 | } | |
2476 | }, | |
2477 | { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32, | |
2478 | 1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1, 3, 3, 1) { | |
2479 | /* IP4_31 [1] */ | |
2480 | 0, 0, | |
2481 | /* IP4_30_29 [2] */ | |
2482 | FN_VI0_R4_B, FN_DU0_DB4, FN_LCDOUT20, 0, | |
2483 | /* IP4_28_27 [2] */ | |
2484 | FN_VI0_R3_B, FN_DU0_DB3, FN_LCDOUT19, 0, | |
2485 | /* IP4_26_25 [2] */ | |
2486 | FN_VI0_R2_B, FN_DU0_DB2, FN_LCDOUT18, 0, | |
2487 | /* IP4_24_21 [4] */ | |
2488 | FN_AUDIO_CLKC, FN_VI0_R1_B, FN_DU0_DB1, FN_LCDOUT17, | |
2489 | FN_AUDATA7, FN_ARM_TRACEDATA_7, FN_GPSIN_A, 0, | |
2490 | FN_ADICS_SAMP, FN_TS_SCK0_B, 0, 0, | |
2491 | 0, 0, 0, 0, | |
2492 | /* IP4_20_17 [4] */ | |
2493 | FN_SSI_SCK2_B, FN_VI0_R0_B, FN_DU0_DB0, FN_LCDOUT16, | |
2494 | FN_AUDATA6, FN_ARM_TRACEDATA_6, FN_GPSCLK_A, FN_PWM0_A, | |
2495 | FN_ADICLK, FN_TS_SDAT0_B, 0, 0, | |
2496 | 0, 0, 0, 0, | |
2497 | /* IP4_16_15 [2] */ | |
2498 | FN_DU0_DG7, FN_LCDOUT15, FN_TX4_A, 0, | |
2499 | /* IP4_14_13 [2] */ | |
2500 | FN_DU0_DG6, FN_LCDOUT14, FN_RX4_A, 0, | |
2501 | /* IP4_12_11 [2] */ | |
2502 | FN_DU0_DG5, FN_LCDOUT13, FN_TX0_B, 0, | |
2503 | /* IP4_10_9 [2] */ | |
2504 | FN_DU0_DG4, FN_LCDOUT12, FN_RX0_B, 0, | |
2505 | /* IP4_8 [1] */ | |
2506 | FN_DU0_DG3, FN_LCDOUT11, | |
2507 | /* IP4_7 [1] */ | |
2508 | FN_DU0_DG2, FN_LCDOUT10, | |
2509 | /* IP4_6_4 [3] */ | |
2510 | FN_DU0_DG1, FN_LCDOUT9, FN_AUDATA5, FN_ARM_TRACEDATA_5, | |
2511 | FN_RX1_D, FN_CAN0_RX_A, FN_ADIDATA, 0, | |
2512 | /* IP4_3_1 [3] */ | |
2513 | FN_DU0_DG0, FN_LCDOUT8, FN_AUDATA4, FN_ARM_TRACEDATA_4, | |
2514 | FN_TX1_D, FN_CAN0_TX_A, FN_ADICHS0, 0, | |
2515 | /* IP4_0 [1] */ | |
2516 | FN_DU0_DR7, FN_LCDOUT7, | |
2517 | } | |
2518 | }, | |
2519 | { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32, | |
2520 | 1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1, 1, 2, 2, 2) { | |
2521 | ||
2522 | /* IP5_31 [1] */ | |
2523 | 0, 0, | |
2524 | /* IP5_30_29 [2] */ | |
2525 | FN_SSI_SDATA7, FN_HSPI_TX0_B, FN_RX2_A, FN_CAN0_RX_B, | |
2526 | /* IP5_28_26 [3] */ | |
2527 | FN_SSI_SDATA8, FN_SSI_SCK2_A, FN_HSPI_CS0_B, FN_TX2_A, | |
2528 | FN_CAN0_TX_B, 0, 0, 0, | |
2529 | /* IP5_25_23 [3] */ | |
2530 | FN_SD1_WP_B, FN_SSI_WS78, FN_HSPI_CLK0_B, FN_RX1_B, | |
2531 | FN_CAN_CLK_D, 0, 0, 0, | |
2532 | /* IP5_22_21 [2] */ | |
2533 | FN_SD1_CD_B, FN_SSI_SCK78, FN_HSPI_RX0_B, FN_TX1_B, | |
2534 | /* IP5_20_18 [3] */ | |
2535 | FN_SSI_WS1_A, FN_DU0_CDE, FN_QPOLB, FN_AUDSYNC, | |
2536 | FN_ARM_TRACECTL, FN_FMIN_D, 0, 0, | |
2537 | /* IP5_17_15 [3] */ | |
2538 | FN_SSI_SCK1_A, FN_DU0_DISP, FN_QPOLA, FN_AUDCK, | |
2539 | FN_ARM_TRACECLK, FN_BPFCLK_D, 0, 0, | |
2540 | /* IP5_14_13 [2] */ | |
2541 | FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, | |
2542 | FN_FMCLK_D, 0, | |
2543 | /* IP5_12 [1] */ | |
2544 | FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, | |
2545 | /* IP5_11_10 [2] */ | |
2546 | FN_SSI_WS2_B, FN_DU0_EXHSYNC_DU0_HSYNC, | |
2547 | FN_QSTH_QHS, 0, | |
2548 | /* IP5_9_8 [2] */ | |
2549 | FN_DU0_DOTCLKO_UT1, FN_QSTVB_QVE, | |
2550 | FN_AUDIO_CLKOUT_A, FN_REMOCON_C, | |
2551 | /* IP5_7 [1] */ | |
2552 | FN_DU0_DOTCLKO_UT0, FN_QCLK, | |
2553 | /* IP5_6 [1] */ | |
2554 | FN_DU0_DOTCLKIN, FN_QSTVA_QVS, | |
2555 | /* IP5_5_4 [2] */ | |
2556 | FN_VI1_DATA11_B, FN_DU0_DB7, FN_LCDOUT23, 0, | |
2557 | /* IP5_3_2 [2] */ | |
2558 | FN_VI1_DATA10_B, FN_DU0_DB6, FN_LCDOUT22, 0, | |
2559 | /* IP5_1_0 [2] */ | |
2560 | FN_VI0_R5_B, FN_DU0_DB5, FN_LCDOUT21, 0, | |
2561 | } | |
2562 | }, | |
2563 | { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32, | |
2564 | 2, 2, 2, 2, 2, 1, 2, 2, 1, 2, | |
2565 | 1, 2, 1, 1, 1, 1, 2, 3, 2) { | |
2566 | /* IP6_31_30 [2] */ | |
2567 | FN_SD0_DAT2, 0, FN_SUB_TDI, 0, | |
2568 | /* IP6_29_28 [2] */ | |
2569 | FN_SD0_DAT1, 0, FN_SUB_TCK, 0, | |
2570 | /* IP6_27_26 [2] */ | |
2571 | FN_SD0_DAT0, 0, FN_SUB_TMS, 0, | |
2572 | /* IP6_25_24 [2] */ | |
2573 | FN_SD0_CMD, 0, FN_SUB_TRST, 0, | |
2574 | /* IP6_23_22 [2] */ | |
2575 | FN_SD0_CLK, 0, FN_SUB_TDO, 0, | |
2576 | /* IP6_21 [1] */ | |
2577 | FN_SSI_SDATA0, FN_ARM_TRACEDATA_15, | |
2578 | /* IP6_20_19 [2] */ | |
2579 | FN_SSI_SDATA1, FN_ARM_TRACEDATA_14, | |
2580 | FN_SCL1_A, FN_SCK2_A, | |
2581 | /* IP6_18_17 [2] */ | |
2582 | FN_SSI_SDATA2, FN_HSPI_CS2_A, | |
2583 | FN_ARM_TRACEDATA_13, FN_SDA1_A, | |
2584 | /* IP6_16 [1] */ | |
2585 | FN_SSI_WS012, FN_ARM_TRACEDATA_12, | |
2586 | /* IP6_15_14 [2] */ | |
2587 | FN_SSI_SCK012, FN_ARM_TRACEDATA_11, | |
2588 | FN_TX0_D, 0, | |
2589 | /* IP6_13 [1] */ | |
2590 | FN_SSI_SDATA3, FN_ARM_TRACEDATA_10, | |
2591 | /* IP6_12_11 [2] */ | |
2592 | FN_SSI_SDATA4, FN_SSI_WS2_A, | |
2593 | FN_ARM_TRACEDATA_9, 0, | |
2594 | /* IP6_10 [1] */ | |
2595 | FN_SSI_WS34, FN_ARM_TRACEDATA_8, | |
2596 | /* IP6_9 [1] */ | |
2597 | FN_SSI_SDATA5, FN_RX0_D, | |
2598 | /* IP6_8 [1] */ | |
2599 | FN_SSI_WS5, FN_TX4_C, | |
2600 | /* IP6_7 [1] */ | |
2601 | FN_SSI_SCK5, FN_RX4_C, | |
2602 | /* IP6_6_5 [2] */ | |
2603 | FN_SSI_SDATA6, FN_HSPI_TX2_A, | |
2604 | FN_FMIN_B, 0, | |
2605 | /* IP6_4_2 [3] */ | |
2606 | FN_SSI_WS6, FN_HSPI_CLK2_A, | |
2607 | FN_BPFCLK_B, FN_CAN1_RX_B, | |
2608 | 0, 0, 0, 0, | |
2609 | /* IP6_1_0 [2] */ | |
2610 | FN_SSI_SCK6, FN_HSPI_RX2_A, | |
2611 | FN_FMCLK_B, FN_CAN1_TX_B, | |
2612 | } | |
2613 | }, | |
2614 | { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32, | |
2615 | 3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2) { | |
2616 | ||
2617 | /* IP7_31_29 [3] */ | |
2618 | FN_VI0_HSYNC, FN_SD2_CD_B, FN_VI1_DATA2, FN_DU1_DR2, | |
2619 | 0, FN_HSPI_CS1_A, FN_RX3_B, 0, | |
2620 | /* IP7_28_25 [4] */ | |
2621 | FN_VI0_FIELD, FN_SD2_DAT3_B, FN_VI0_R3_C, FN_VI1_DATA1, | |
2622 | FN_DU1_DG7, 0, FN_HSPI_CLK1_A, FN_TX4_B, | |
2623 | 0, 0, 0, 0, | |
2624 | 0, 0, 0, 0, | |
2625 | /* IP7_24_22 [3] */ | |
2626 | FN_VI0_CLKENB, FN_SD2_DAT2_B, FN_VI1_DATA0, FN_DU1_DG6, | |
2627 | 0, FN_HSPI_RX1_A, FN_RX4_B, 0, | |
2628 | /* IP7_21 [1] */ | |
2629 | FN_VI0_CLK, FN_CAN_CLK_A, | |
2630 | /* IP7_20_18 [3] */ | |
2631 | FN_TCLK0, FN_HSCK1_A, FN_FMIN_A, 0, | |
2632 | FN_IRQ2_C, FN_CTS1_C, FN_SPEEDIN, 0, | |
2633 | /* IP7_17_15 [3] */ | |
2634 | FN_VI1_VSYNC, FN_HSPI_TX0, FN_HCTS1_A, FN_BPFCLK_A, | |
2635 | 0, FN_TX1_C, 0, 0, | |
2636 | /* IP7_14_12 [3] */ | |
2637 | FN_VI1_HSYNC, FN_HSPI_RX0_A, FN_HRTS1_A, FN_FMCLK_A, | |
2638 | 0, FN_RX1_C, 0, 0, | |
2639 | /* IP7_11_9 [3] */ | |
2640 | FN_VI1_FIELD, FN_HSPI_CS0_A, FN_HRX1_A, 0, | |
2641 | FN_SCK1_C, 0, 0, 0, | |
2642 | /* IP7_8_6 [3] */ | |
2643 | FN_VI1_CLKENB, FN_HSPI_CLK0_A, FN_HTX1_A, 0, | |
2644 | FN_RTS1_C, 0, 0, 0, | |
2645 | /* IP7_5_4 [2] */ | |
2646 | FN_SD0_WP, 0, FN_RX5_A, 0, | |
2647 | /* IP7_3_2 [2] */ | |
2648 | FN_SD0_CD, 0, FN_TX5_A, 0, | |
2649 | /* IP7_1_0 [2] */ | |
2650 | FN_SD0_DAT3, 0, FN_IRQ1_B, 0, | |
2651 | } | |
2652 | }, | |
2653 | { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32, | |
2654 | 1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3) { | |
2655 | /* IP8_31 [1] */ | |
2656 | 0, 0, | |
2657 | /* IP8_30 [1] */ | |
2658 | 0, 0, | |
2659 | /* IP8_29_27 [3] */ | |
2660 | FN_VI0_G3, FN_SD2_CMD_B, FN_VI1_DATA5, FN_DU1_DR5, | |
2661 | 0, FN_HRX1_B, 0, 0, | |
2662 | /* IP8_26_24 [3] */ | |
2663 | FN_VI0_G2, FN_SD2_CLK_B, FN_VI1_DATA4, FN_DU1_DR4, | |
2664 | 0, FN_HTX1_B, 0, 0, | |
2665 | /* IP8_23_22 [2] */ | |
2666 | FN_VI0_DATA7_VI0_G1, FN_DU1_DB5, | |
2667 | FN_RTS1_A, 0, | |
2668 | /* IP8_21_19 [3] */ | |
2669 | FN_VI0_DATA6_VI0_G0, FN_DU1_DB4, | |
2670 | FN_CTS1_A, FN_PWM5, | |
2671 | 0, 0, 0, 0, | |
2672 | /* IP8_18_16 [3] */ | |
2673 | FN_VI0_DATA5_VI0_B5, FN_DU1_DB3, FN_SCK1_A, FN_PWM4, | |
2674 | 0, FN_HSCK1_B, 0, 0, | |
2675 | /* IP8_15_14 [2] */ | |
2676 | FN_VI0_DATA4_VI0_B4, FN_DU1_DB2, FN_RX1_A, 0, | |
2677 | /* IP8_13_11 [3] */ | |
2678 | FN_VI0_DATA3_VI0_B3, FN_DU1_DG5, FN_TX1_A, FN_TX0_C, | |
2679 | 0, 0, 0, 0, | |
2680 | /* IP8_10_9 [2] */ | |
2681 | FN_VI0_DATA2_VI0_B2, FN_DU1_DG4, FN_RX0_C, 0, | |
2682 | /* IP8_8_6 [3] */ | |
2683 | FN_VI0_DATA1_VI0_B1, FN_DU1_DG3, FN_IRQ3_B, FN_TX3_D, | |
2684 | 0, 0, 0, 0, | |
2685 | /* IP8_5_3 [3] */ | |
2686 | FN_VI0_DATA0_VI0_B0, FN_DU1_DG2, FN_IRQ2_B, FN_RX3_D, | |
2687 | 0, 0, 0, 0, | |
2688 | /* IP8_2_0 [3] */ | |
2689 | FN_VI0_VSYNC, FN_SD2_WP_B, FN_VI1_DATA3, FN_DU1_DR3, | |
2690 | 0, FN_HSPI_TX1_A, FN_TX3_B, 0, | |
2691 | } | |
2692 | }, | |
2693 | { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32, | |
2694 | 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { | |
2695 | /* IP9_31 [1] */ | |
2696 | 0, 0, | |
2697 | /* IP9_30 [1] */ | |
2698 | 0, 0, | |
2699 | /* IP9_29_27 [3] */ | |
2700 | FN_VI1_DATA11_A, FN_DU1_EXHSYNC_DU1_HSYNC, | |
2701 | FN_ETH_RXD1, FN_FMIN_C, | |
2702 | 0, FN_RX2_D, | |
2703 | FN_SCL2_C, 0, | |
2704 | /* IP9_26_24 [3] */ | |
2705 | FN_VI1_DATA10_A, FN_DU1_DOTCLKOUT, | |
2706 | FN_ETH_RXD0, FN_BPFCLK_C, | |
2707 | 0, FN_TX2_D, | |
2708 | FN_SDA2_C, 0, | |
2709 | /* IP9_23_21 [3] */ | |
2710 | FN_VI0_R5_A, 0, FN_ETH_RX_ER, FN_FMCLK_C, | |
2711 | FN_IERX, FN_RX2_C, 0, 0, | |
2712 | /* IP9_20_18 [3] */ | |
2713 | FN_VI0_R4_A, FN_ETH_TX_EN, 0, 0, | |
2714 | FN_IETX, FN_TX2_C, 0, 0, | |
2715 | /* IP9_17_15 [3] */ | |
2716 | FN_VI0_R3_A, FN_ETH_CRS_DV, 0, FN_IECLK, | |
2717 | FN_SCK2_C, 0, 0, 0, | |
2718 | /* IP9_14_12 [3] */ | |
2719 | FN_VI0_R2_A, FN_VI1_DATA9, FN_DU1_DB7, FN_ETH_TXD1, | |
2720 | 0, FN_PWM3, 0, 0, | |
2721 | /* IP9_11_9 [3] */ | |
2722 | FN_VI0_R1_A, FN_VI1_DATA8, FN_DU1_DB6, FN_ETH_TXD0, | |
2723 | 0, FN_PWM2, FN_TCLK1, 0, | |
2724 | /* IP9_8_6 [3] */ | |
2725 | FN_VI0_R0_A, FN_VI1_CLK, FN_ETH_REF_CLK, FN_DU1_DOTCLKIN, | |
2726 | 0, 0, 0, 0, | |
2727 | /* IP9_5_3 [3] */ | |
2728 | FN_VI0_G5, FN_SD2_DAT1_B, FN_VI1_DATA7, FN_DU1_DR7, | |
2729 | 0, FN_HCTS1_B, 0, 0, | |
2730 | /* IP9_2_0 [3] */ | |
2731 | FN_VI0_G4, FN_SD2_DAT0_B, FN_VI1_DATA6, FN_DU1_DR6, | |
2732 | 0, FN_HRTS1_B, 0, 0, | |
2733 | } | |
2734 | }, | |
2735 | { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32, | |
2736 | 1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4, 3, 3, 3) { | |
2737 | ||
2738 | /* IP10_31 [1] */ | |
2739 | 0, 0, | |
2740 | /* IP10_30 [1] */ | |
2741 | 0, 0, | |
2742 | /* IP10_29 [1] */ | |
2743 | 0, 0, | |
2744 | /* IP10_28 [1] */ | |
2745 | 0, 0, | |
2746 | /* IP10_27 [1] */ | |
2747 | 0, 0, | |
2748 | /* IP10_26 [1] */ | |
2749 | 0, 0, | |
2750 | /* IP10_25 [1] */ | |
2751 | 0, 0, | |
2752 | /* IP10_24_22 [3] */ | |
2753 | FN_SD2_WP_A, FN_VI1_DATA15, FN_EX_WAIT2_B, FN_DACK0_B, | |
2754 | FN_HSPI_TX2_B, FN_CAN_CLK_C, 0, 0, | |
2755 | /* IP10_21_19 [3] */ | |
2756 | FN_SD2_CD_A, FN_VI1_DATA14, FN_EX_WAIT1_B, FN_DREQ0_B, | |
2757 | FN_HSPI_RX2_B, FN_REMOCON_A, 0, 0, | |
2758 | /* IP10_18_16 [3] */ | |
2759 | FN_SD2_DAT3_A, FN_VI1_DATA13, FN_DACK2_B, FN_ATAG1, | |
2760 | FN_HSPI_CS2_B, FN_GPSIN_B, 0, 0, | |
2761 | /* IP10_15_13 [3] */ | |
2762 | FN_SD2_DAT2_A, FN_VI1_DATA12, FN_DREQ2_B, FN_ATADIR1, | |
2763 | FN_HSPI_CLK2_B, FN_GPSCLK_B, 0, 0, | |
2764 | /* IP10_12_9 [4] */ | |
2765 | FN_SD2_DAT1_A, FN_DU1_CDE, FN_ATACS11, FN_DACK1_B, | |
2766 | FN_ETH_MAGIC, FN_CAN1_TX_A, 0, FN_PWM6, | |
2767 | 0, 0, 0, 0, | |
2768 | 0, 0, 0, 0, | |
2769 | /* IP10_8_6 [3] */ | |
2770 | FN_SD2_DAT0_A, FN_DU1_DISP, FN_ATACS01, FN_DREQ1_B, | |
2771 | FN_ETH_LINK, FN_CAN1_RX_A, 0, 0, | |
2772 | /* IP10_5_3 [3] */ | |
2773 | FN_SD2_CMD_A, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, | |
2774 | FN_ATAWR1, FN_ETH_MDIO, | |
2775 | FN_SCL1_B, 0, | |
2776 | 0, 0, | |
2777 | /* IP10_2_0 [3] */ | |
2778 | FN_SD2_CLK_A, FN_DU1_EXVSYNC_DU1_VSYNC, | |
2779 | FN_ATARD1, FN_ETH_MDC, | |
2780 | FN_SDA1_B, 0, | |
2781 | 0, 0, | |
2782 | } | |
2783 | }, | |
2784 | { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32, | |
2785 | 1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2, | |
2786 | 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) { | |
2787 | ||
2788 | /* SEL 31 [1] */ | |
2789 | 0, 0, | |
2790 | /* SEL_30 (SCIF5) [1] */ | |
2791 | FN_SEL_SCIF5_A, FN_SEL_SCIF5_B, | |
2792 | /* SEL_29_28 (SCIF4) [2] */ | |
2793 | FN_SEL_SCIF4_A, FN_SEL_SCIF4_B, | |
2794 | FN_SEL_SCIF4_C, 0, | |
2795 | /* SEL_27_26 (SCIF3) [2] */ | |
2796 | FN_SEL_SCIF3_A, FN_SEL_SCIF3_B, | |
2797 | FN_SEL_SCIF3_C, FN_SEL_SCIF3_D, | |
2798 | /* SEL_25_23 (SCIF2) [3] */ | |
2799 | FN_SEL_SCIF2_A, FN_SEL_SCIF2_B, | |
2800 | FN_SEL_SCIF2_C, FN_SEL_SCIF2_D, | |
2801 | FN_SEL_SCIF2_E, 0, | |
2802 | 0, 0, | |
2803 | /* SEL_22_21 (SCIF1) [2] */ | |
2804 | FN_SEL_SCIF1_A, FN_SEL_SCIF1_B, | |
2805 | FN_SEL_SCIF1_C, FN_SEL_SCIF1_D, | |
2806 | /* SEL_20_19 (SCIF0) [2] */ | |
2807 | FN_SEL_SCIF0_A, FN_SEL_SCIF0_B, | |
2808 | FN_SEL_SCIF0_C, FN_SEL_SCIF0_D, | |
2809 | /* SEL_18 [1] */ | |
2810 | 0, 0, | |
2811 | /* SEL_17 (SSI2) [1] */ | |
2812 | FN_SEL_SSI2_A, FN_SEL_SSI2_B, | |
2813 | /* SEL_16 (SSI1) [1] */ | |
2814 | FN_SEL_SSI1_A, FN_SEL_SSI1_B, | |
2815 | /* SEL_15 (VI1) [1] */ | |
2816 | FN_SEL_VI1_A, FN_SEL_VI1_B, | |
2817 | /* SEL_14_13 (VI0) [2] */ | |
2818 | FN_SEL_VI0_A, FN_SEL_VI0_B, | |
2819 | FN_SEL_VI0_C, FN_SEL_VI0_D, | |
2820 | /* SEL_12 [1] */ | |
2821 | 0, 0, | |
2822 | /* SEL_11 (SD2) [1] */ | |
2823 | FN_SEL_SD2_A, FN_SEL_SD2_B, | |
2824 | /* SEL_10 (SD1) [1] */ | |
2825 | FN_SEL_SD1_A, FN_SEL_SD1_B, | |
2826 | /* SEL_9 (IRQ3) [1] */ | |
2827 | FN_SEL_IRQ3_A, FN_SEL_IRQ3_B, | |
2828 | /* SEL_8_7 (IRQ2) [2] */ | |
2829 | FN_SEL_IRQ2_A, FN_SEL_IRQ2_B, | |
2830 | FN_SEL_IRQ2_C, 0, | |
2831 | /* SEL_6 (IRQ1) [1] */ | |
2832 | FN_SEL_IRQ1_A, FN_SEL_IRQ1_B, | |
2833 | /* SEL_5 [1] */ | |
2834 | 0, 0, | |
2835 | /* SEL_4 (DREQ2) [1] */ | |
2836 | FN_SEL_DREQ2_A, FN_SEL_DREQ2_B, | |
2837 | /* SEL_3 (DREQ1) [1] */ | |
2838 | FN_SEL_DREQ1_A, FN_SEL_DREQ1_B, | |
2839 | /* SEL_2 (DREQ0) [1] */ | |
2840 | FN_SEL_DREQ0_A, FN_SEL_DREQ0_B, | |
2841 | /* SEL_1 (WAIT2) [1] */ | |
2842 | FN_SEL_WAIT2_A, FN_SEL_WAIT2_B, | |
2843 | /* SEL_0 (WAIT1) [1] */ | |
2844 | FN_SEL_WAIT1_A, FN_SEL_WAIT1_B, | |
2845 | } | |
2846 | }, | |
2847 | { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32, | |
2848 | 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, | |
2849 | 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1) { | |
2850 | ||
2851 | /* SEL_31 [1] */ | |
2852 | 0, 0, | |
2853 | /* SEL_30 [1] */ | |
2854 | 0, 0, | |
2855 | /* SEL_29 [1] */ | |
2856 | 0, 0, | |
2857 | /* SEL_28 [1] */ | |
2858 | 0, 0, | |
2859 | /* SEL_27 (CAN1) [1] */ | |
2860 | FN_SEL_CAN1_A, FN_SEL_CAN1_B, | |
2861 | /* SEL_26 (CAN0) [1] */ | |
2862 | FN_SEL_CAN0_A, FN_SEL_CAN0_B, | |
2863 | /* SEL_25_24 (CANCLK) [2] */ | |
2864 | FN_SEL_CANCLK_A, FN_SEL_CANCLK_B, | |
2865 | FN_SEL_CANCLK_C, FN_SEL_CANCLK_D, | |
2866 | /* SEL_23 (HSCIF1) [1] */ | |
2867 | FN_SEL_HSCIF1_A, FN_SEL_HSCIF1_B, | |
2868 | /* SEL_22 (HSCIF0) [1] */ | |
2869 | FN_SEL_HSCIF0_A, FN_SEL_HSCIF0_B, | |
2870 | /* SEL_21 [1] */ | |
2871 | 0, 0, | |
2872 | /* SEL_20 [1] */ | |
2873 | 0, 0, | |
2874 | /* SEL_19 [1] */ | |
2875 | 0, 0, | |
2876 | /* SEL_18 [1] */ | |
2877 | 0, 0, | |
2878 | /* SEL_17 [1] */ | |
2879 | 0, 0, | |
2880 | /* SEL_16 [1] */ | |
2881 | 0, 0, | |
2882 | /* SEL_15 [1] */ | |
2883 | 0, 0, | |
2884 | /* SEL_14_13 (REMOCON) [2] */ | |
2885 | FN_SEL_REMOCON_A, FN_SEL_REMOCON_B, | |
2886 | FN_SEL_REMOCON_C, 0, | |
2887 | /* SEL_12_11 (FM) [2] */ | |
2888 | FN_SEL_FM_A, FN_SEL_FM_B, | |
2889 | FN_SEL_FM_C, FN_SEL_FM_D, | |
2890 | /* SEL_10_9 (GPS) [2] */ | |
2891 | FN_SEL_GPS_A, FN_SEL_GPS_B, | |
2892 | FN_SEL_GPS_C, 0, | |
2893 | /* SEL_8 (TSIF0) [1] */ | |
2894 | FN_SEL_TSIF0_A, FN_SEL_TSIF0_B, | |
2895 | /* SEL_7 (HSPI2) [1] */ | |
2896 | FN_SEL_HSPI2_A, FN_SEL_HSPI2_B, | |
2897 | /* SEL_6 (HSPI1) [1] */ | |
2898 | FN_SEL_HSPI1_A, FN_SEL_HSPI1_B, | |
2899 | /* SEL_5 (HSPI0) [1] */ | |
2900 | FN_SEL_HSPI0_A, FN_SEL_HSPI0_B, | |
2901 | /* SEL_4_3 (I2C3) [2] */ | |
2902 | FN_SEL_I2C3_A, FN_SEL_I2C3_B, | |
2903 | FN_SEL_I2C3_C, 0, | |
2904 | /* SEL_2_1 (I2C2) [2] */ | |
2905 | FN_SEL_I2C2_A, FN_SEL_I2C2_B, | |
2906 | FN_SEL_I2C2_C, 0, | |
2907 | /* SEL_0 (I2C1) [1] */ | |
2908 | FN_SEL_I2C1_A, FN_SEL_I2C1_B, | |
2909 | } | |
2910 | }, | |
2911 | { }, | |
2912 | }; | |
2913 | ||
ae7465a0 UH |
2914 | #define PUPR0 0x100 |
2915 | #define PUPR1 0x104 | |
2916 | #define PUPR2 0x108 | |
2917 | #define PUPR3 0x10c | |
2918 | #define PUPR4 0x110 | |
2919 | #define PUPR5 0x114 | |
2920 | ||
2921 | static const struct { | |
2922 | u16 reg : 11; | |
2923 | u16 bit : 5; | |
2924 | } pullups[] = { | |
2925 | [RCAR_GP_PIN(0, 6)] = { PUPR0, 0 }, /* A0 */ | |
2926 | [RCAR_GP_PIN(0, 7)] = { PUPR0, 1 }, /* A1 */ | |
2927 | [RCAR_GP_PIN(0, 8)] = { PUPR0, 2 }, /* A2 */ | |
2928 | [RCAR_GP_PIN(0, 9)] = { PUPR0, 3 }, /* A3 */ | |
2929 | [RCAR_GP_PIN(0, 10)] = { PUPR0, 4 }, /* A4 */ | |
2930 | [RCAR_GP_PIN(0, 11)] = { PUPR0, 5 }, /* A5 */ | |
2931 | [RCAR_GP_PIN(0, 12)] = { PUPR0, 6 }, /* A6 */ | |
2932 | [RCAR_GP_PIN(0, 13)] = { PUPR0, 7 }, /* A7 */ | |
2933 | [RCAR_GP_PIN(0, 14)] = { PUPR0, 8 }, /* A8 */ | |
2934 | [RCAR_GP_PIN(0, 15)] = { PUPR0, 9 }, /* A9 */ | |
2935 | [RCAR_GP_PIN(0, 16)] = { PUPR0, 10 }, /* A10 */ | |
2936 | [RCAR_GP_PIN(0, 17)] = { PUPR0, 11 }, /* A11 */ | |
2937 | [RCAR_GP_PIN(0, 18)] = { PUPR0, 12 }, /* A12 */ | |
2938 | [RCAR_GP_PIN(0, 19)] = { PUPR0, 13 }, /* A13 */ | |
2939 | [RCAR_GP_PIN(0, 20)] = { PUPR0, 14 }, /* A14 */ | |
2940 | [RCAR_GP_PIN(0, 21)] = { PUPR0, 15 }, /* A15 */ | |
2941 | [RCAR_GP_PIN(0, 22)] = { PUPR0, 16 }, /* A16 */ | |
2942 | [RCAR_GP_PIN(0, 23)] = { PUPR0, 17 }, /* A17 */ | |
2943 | [RCAR_GP_PIN(0, 24)] = { PUPR0, 18 }, /* A18 */ | |
2944 | [RCAR_GP_PIN(0, 25)] = { PUPR0, 19 }, /* A19 */ | |
2945 | [RCAR_GP_PIN(0, 26)] = { PUPR0, 20 }, /* A20 */ | |
2946 | [RCAR_GP_PIN(0, 27)] = { PUPR0, 21 }, /* A21 */ | |
2947 | [RCAR_GP_PIN(0, 28)] = { PUPR0, 22 }, /* A22 */ | |
2948 | [RCAR_GP_PIN(0, 29)] = { PUPR0, 23 }, /* A23 */ | |
2949 | [RCAR_GP_PIN(0, 30)] = { PUPR0, 24 }, /* A24 */ | |
2950 | [RCAR_GP_PIN(0, 31)] = { PUPR0, 25 }, /* A25 */ | |
2951 | [RCAR_GP_PIN(1, 3)] = { PUPR0, 26 }, /* /EX_CS0 */ | |
2952 | [RCAR_GP_PIN(1, 4)] = { PUPR0, 27 }, /* /EX_CS1 */ | |
2953 | [RCAR_GP_PIN(1, 5)] = { PUPR0, 28 }, /* /EX_CS2 */ | |
2954 | [RCAR_GP_PIN(1, 6)] = { PUPR0, 29 }, /* /EX_CS3 */ | |
2955 | [RCAR_GP_PIN(1, 7)] = { PUPR0, 30 }, /* /EX_CS4 */ | |
2956 | [RCAR_GP_PIN(1, 8)] = { PUPR0, 31 }, /* /EX_CS5 */ | |
2957 | ||
2958 | [RCAR_GP_PIN(0, 0)] = { PUPR1, 0 }, /* /PRESETOUT */ | |
2959 | [RCAR_GP_PIN(0, 5)] = { PUPR1, 1 }, /* /BS */ | |
2960 | [RCAR_GP_PIN(1, 0)] = { PUPR1, 2 }, /* RD//WR */ | |
2961 | [RCAR_GP_PIN(1, 1)] = { PUPR1, 3 }, /* /WE0 */ | |
2962 | [RCAR_GP_PIN(1, 2)] = { PUPR1, 4 }, /* /WE1 */ | |
2963 | [RCAR_GP_PIN(1, 11)] = { PUPR1, 5 }, /* EX_WAIT0 */ | |
2964 | [RCAR_GP_PIN(1, 9)] = { PUPR1, 6 }, /* DREQ0 */ | |
2965 | [RCAR_GP_PIN(1, 10)] = { PUPR1, 7 }, /* DACK0 */ | |
2966 | [RCAR_GP_PIN(1, 12)] = { PUPR1, 8 }, /* IRQ0 */ | |
2967 | [RCAR_GP_PIN(1, 13)] = { PUPR1, 9 }, /* IRQ1 */ | |
2968 | ||
2969 | [RCAR_GP_PIN(1, 22)] = { PUPR2, 0 }, /* DU0_DR0 */ | |
2970 | [RCAR_GP_PIN(1, 23)] = { PUPR2, 1 }, /* DU0_DR1 */ | |
2971 | [RCAR_GP_PIN(1, 24)] = { PUPR2, 2 }, /* DU0_DR2 */ | |
2972 | [RCAR_GP_PIN(1, 25)] = { PUPR2, 3 }, /* DU0_DR3 */ | |
2973 | [RCAR_GP_PIN(1, 26)] = { PUPR2, 4 }, /* DU0_DR4 */ | |
2974 | [RCAR_GP_PIN(1, 27)] = { PUPR2, 5 }, /* DU0_DR5 */ | |
2975 | [RCAR_GP_PIN(1, 28)] = { PUPR2, 6 }, /* DU0_DR6 */ | |
2976 | [RCAR_GP_PIN(1, 29)] = { PUPR2, 7 }, /* DU0_DR7 */ | |
2977 | [RCAR_GP_PIN(1, 30)] = { PUPR2, 8 }, /* DU0_DG0 */ | |
2978 | [RCAR_GP_PIN(1, 31)] = { PUPR2, 9 }, /* DU0_DG1 */ | |
2979 | [RCAR_GP_PIN(2, 0)] = { PUPR2, 10 }, /* DU0_DG2 */ | |
2980 | [RCAR_GP_PIN(2, 1)] = { PUPR2, 11 }, /* DU0_DG3 */ | |
2981 | [RCAR_GP_PIN(2, 2)] = { PUPR2, 12 }, /* DU0_DG4 */ | |
2982 | [RCAR_GP_PIN(2, 3)] = { PUPR2, 13 }, /* DU0_DG5 */ | |
2983 | [RCAR_GP_PIN(2, 4)] = { PUPR2, 14 }, /* DU0_DG6 */ | |
2984 | [RCAR_GP_PIN(2, 5)] = { PUPR2, 15 }, /* DU0_DG7 */ | |
2985 | [RCAR_GP_PIN(2, 6)] = { PUPR2, 16 }, /* DU0_DB0 */ | |
2986 | [RCAR_GP_PIN(2, 7)] = { PUPR2, 17 }, /* DU0_DB1 */ | |
2987 | [RCAR_GP_PIN(2, 8)] = { PUPR2, 18 }, /* DU0_DB2 */ | |
2988 | [RCAR_GP_PIN(2, 9)] = { PUPR2, 19 }, /* DU0_DB3 */ | |
2989 | [RCAR_GP_PIN(2, 10)] = { PUPR2, 20 }, /* DU0_DB4 */ | |
2990 | [RCAR_GP_PIN(2, 11)] = { PUPR2, 21 }, /* DU0_DB5 */ | |
2991 | [RCAR_GP_PIN(2, 12)] = { PUPR2, 22 }, /* DU0_DB6 */ | |
2992 | [RCAR_GP_PIN(2, 13)] = { PUPR2, 23 }, /* DU0_DB7 */ | |
2993 | [RCAR_GP_PIN(2, 14)] = { PUPR2, 24 }, /* DU0_DOTCLKIN */ | |
2994 | [RCAR_GP_PIN(2, 15)] = { PUPR2, 25 }, /* DU0_DOTCLKOUT0 */ | |
2995 | [RCAR_GP_PIN(2, 17)] = { PUPR2, 26 }, /* DU0_HSYNC */ | |
2996 | [RCAR_GP_PIN(2, 18)] = { PUPR2, 27 }, /* DU0_VSYNC */ | |
2997 | [RCAR_GP_PIN(2, 19)] = { PUPR2, 28 }, /* DU0_EXODDF */ | |
2998 | [RCAR_GP_PIN(2, 20)] = { PUPR2, 29 }, /* DU0_DISP */ | |
2999 | [RCAR_GP_PIN(2, 21)] = { PUPR2, 30 }, /* DU0_CDE */ | |
3000 | [RCAR_GP_PIN(2, 16)] = { PUPR2, 31 }, /* DU0_DOTCLKOUT1 */ | |
3001 | ||
3002 | [RCAR_GP_PIN(3, 24)] = { PUPR3, 0 }, /* VI0_CLK */ | |
3003 | [RCAR_GP_PIN(3, 25)] = { PUPR3, 1 }, /* VI0_CLKENB */ | |
3004 | [RCAR_GP_PIN(3, 26)] = { PUPR3, 2 }, /* VI0_FIELD */ | |
3005 | [RCAR_GP_PIN(3, 27)] = { PUPR3, 3 }, /* /VI0_HSYNC */ | |
3006 | [RCAR_GP_PIN(3, 28)] = { PUPR3, 4 }, /* /VI0_VSYNC */ | |
3007 | [RCAR_GP_PIN(3, 29)] = { PUPR3, 5 }, /* VI0_DATA0 */ | |
3008 | [RCAR_GP_PIN(3, 30)] = { PUPR3, 6 }, /* VI0_DATA1 */ | |
3009 | [RCAR_GP_PIN(3, 31)] = { PUPR3, 7 }, /* VI0_DATA2 */ | |
3010 | [RCAR_GP_PIN(4, 0)] = { PUPR3, 8 }, /* VI0_DATA3 */ | |
3011 | [RCAR_GP_PIN(4, 1)] = { PUPR3, 9 }, /* VI0_DATA4 */ | |
3012 | [RCAR_GP_PIN(4, 2)] = { PUPR3, 10 }, /* VI0_DATA5 */ | |
3013 | [RCAR_GP_PIN(4, 3)] = { PUPR3, 11 }, /* VI0_DATA6 */ | |
3014 | [RCAR_GP_PIN(4, 4)] = { PUPR3, 12 }, /* VI0_DATA7 */ | |
3015 | [RCAR_GP_PIN(4, 5)] = { PUPR3, 13 }, /* VI0_G2 */ | |
3016 | [RCAR_GP_PIN(4, 6)] = { PUPR3, 14 }, /* VI0_G3 */ | |
3017 | [RCAR_GP_PIN(4, 7)] = { PUPR3, 15 }, /* VI0_G4 */ | |
3018 | [RCAR_GP_PIN(4, 8)] = { PUPR3, 16 }, /* VI0_G5 */ | |
3019 | [RCAR_GP_PIN(4, 21)] = { PUPR3, 17 }, /* VI1_DATA12 */ | |
3020 | [RCAR_GP_PIN(4, 22)] = { PUPR3, 18 }, /* VI1_DATA13 */ | |
3021 | [RCAR_GP_PIN(4, 23)] = { PUPR3, 19 }, /* VI1_DATA14 */ | |
3022 | [RCAR_GP_PIN(4, 24)] = { PUPR3, 20 }, /* VI1_DATA15 */ | |
3023 | [RCAR_GP_PIN(4, 9)] = { PUPR3, 21 }, /* ETH_REF_CLK */ | |
3024 | [RCAR_GP_PIN(4, 10)] = { PUPR3, 22 }, /* ETH_TXD0 */ | |
3025 | [RCAR_GP_PIN(4, 11)] = { PUPR3, 23 }, /* ETH_TXD1 */ | |
3026 | [RCAR_GP_PIN(4, 12)] = { PUPR3, 24 }, /* ETH_CRS_DV */ | |
3027 | [RCAR_GP_PIN(4, 13)] = { PUPR3, 25 }, /* ETH_TX_EN */ | |
3028 | [RCAR_GP_PIN(4, 14)] = { PUPR3, 26 }, /* ETH_RX_ER */ | |
3029 | [RCAR_GP_PIN(4, 15)] = { PUPR3, 27 }, /* ETH_RXD0 */ | |
3030 | [RCAR_GP_PIN(4, 16)] = { PUPR3, 28 }, /* ETH_RXD1 */ | |
3031 | [RCAR_GP_PIN(4, 17)] = { PUPR3, 29 }, /* ETH_MDC */ | |
3032 | [RCAR_GP_PIN(4, 18)] = { PUPR3, 30 }, /* ETH_MDIO */ | |
3033 | [RCAR_GP_PIN(4, 19)] = { PUPR3, 31 }, /* ETH_LINK */ | |
3034 | ||
3035 | [RCAR_GP_PIN(3, 6)] = { PUPR4, 0 }, /* SSI_SCK012 */ | |
3036 | [RCAR_GP_PIN(3, 7)] = { PUPR4, 1 }, /* SSI_WS012 */ | |
3037 | [RCAR_GP_PIN(3, 10)] = { PUPR4, 2 }, /* SSI_SDATA0 */ | |
3038 | [RCAR_GP_PIN(3, 9)] = { PUPR4, 3 }, /* SSI_SDATA1 */ | |
3039 | [RCAR_GP_PIN(3, 8)] = { PUPR4, 4 }, /* SSI_SDATA2 */ | |
3040 | [RCAR_GP_PIN(3, 2)] = { PUPR4, 5 }, /* SSI_SCK34 */ | |
3041 | [RCAR_GP_PIN(3, 3)] = { PUPR4, 6 }, /* SSI_WS34 */ | |
3042 | [RCAR_GP_PIN(3, 5)] = { PUPR4, 7 }, /* SSI_SDATA3 */ | |
3043 | [RCAR_GP_PIN(3, 4)] = { PUPR4, 8 }, /* SSI_SDATA4 */ | |
3044 | [RCAR_GP_PIN(2, 31)] = { PUPR4, 9 }, /* SSI_SCK5 */ | |
3045 | [RCAR_GP_PIN(3, 0)] = { PUPR4, 10 }, /* SSI_WS5 */ | |
3046 | [RCAR_GP_PIN(3, 1)] = { PUPR4, 11 }, /* SSI_SDATA5 */ | |
3047 | [RCAR_GP_PIN(2, 28)] = { PUPR4, 12 }, /* SSI_SCK6 */ | |
3048 | [RCAR_GP_PIN(2, 29)] = { PUPR4, 13 }, /* SSI_WS6 */ | |
3049 | [RCAR_GP_PIN(2, 30)] = { PUPR4, 14 }, /* SSI_SDATA6 */ | |
3050 | [RCAR_GP_PIN(2, 24)] = { PUPR4, 15 }, /* SSI_SCK78 */ | |
3051 | [RCAR_GP_PIN(2, 25)] = { PUPR4, 16 }, /* SSI_WS78 */ | |
3052 | [RCAR_GP_PIN(2, 27)] = { PUPR4, 17 }, /* SSI_SDATA7 */ | |
3053 | [RCAR_GP_PIN(2, 26)] = { PUPR4, 18 }, /* SSI_SDATA8 */ | |
3054 | [RCAR_GP_PIN(3, 23)] = { PUPR4, 19 }, /* TCLK0 */ | |
3055 | [RCAR_GP_PIN(3, 11)] = { PUPR4, 20 }, /* SD0_CLK */ | |
3056 | [RCAR_GP_PIN(3, 12)] = { PUPR4, 21 }, /* SD0_CMD */ | |
3057 | [RCAR_GP_PIN(3, 13)] = { PUPR4, 22 }, /* SD0_DAT0 */ | |
3058 | [RCAR_GP_PIN(3, 14)] = { PUPR4, 23 }, /* SD0_DAT1 */ | |
3059 | [RCAR_GP_PIN(3, 15)] = { PUPR4, 24 }, /* SD0_DAT2 */ | |
3060 | [RCAR_GP_PIN(3, 16)] = { PUPR4, 25 }, /* SD0_DAT3 */ | |
3061 | [RCAR_GP_PIN(3, 17)] = { PUPR4, 26 }, /* SD0_CD */ | |
3062 | [RCAR_GP_PIN(3, 18)] = { PUPR4, 27 }, /* SD0_WP */ | |
3063 | [RCAR_GP_PIN(2, 22)] = { PUPR4, 28 }, /* AUDIO_CLKA */ | |
3064 | [RCAR_GP_PIN(2, 23)] = { PUPR4, 29 }, /* AUDIO_CLKB */ | |
3065 | [RCAR_GP_PIN(1, 14)] = { PUPR4, 30 }, /* IRQ2 */ | |
3066 | [RCAR_GP_PIN(1, 15)] = { PUPR4, 31 }, /* IRQ3 */ | |
3067 | ||
3068 | [RCAR_GP_PIN(0, 1)] = { PUPR5, 0 }, /* PENC0 */ | |
3069 | [RCAR_GP_PIN(0, 2)] = { PUPR5, 1 }, /* PENC1 */ | |
3070 | [RCAR_GP_PIN(0, 3)] = { PUPR5, 2 }, /* USB_OVC0 */ | |
3071 | [RCAR_GP_PIN(0, 4)] = { PUPR5, 3 }, /* USB_OVC1 */ | |
3072 | [RCAR_GP_PIN(1, 16)] = { PUPR5, 4 }, /* SCIF_CLK */ | |
3073 | [RCAR_GP_PIN(1, 17)] = { PUPR5, 5 }, /* TX0 */ | |
3074 | [RCAR_GP_PIN(1, 18)] = { PUPR5, 6 }, /* RX0 */ | |
3075 | [RCAR_GP_PIN(1, 19)] = { PUPR5, 7 }, /* SCK0 */ | |
3076 | [RCAR_GP_PIN(1, 20)] = { PUPR5, 8 }, /* /CTS0 */ | |
3077 | [RCAR_GP_PIN(1, 21)] = { PUPR5, 9 }, /* /RTS0 */ | |
3078 | [RCAR_GP_PIN(3, 19)] = { PUPR5, 10 }, /* HSPI_CLK0 */ | |
3079 | [RCAR_GP_PIN(3, 20)] = { PUPR5, 11 }, /* /HSPI_CS0 */ | |
3080 | [RCAR_GP_PIN(3, 21)] = { PUPR5, 12 }, /* HSPI_RX0 */ | |
3081 | [RCAR_GP_PIN(3, 22)] = { PUPR5, 13 }, /* HSPI_TX0 */ | |
3082 | [RCAR_GP_PIN(4, 20)] = { PUPR5, 14 }, /* ETH_MAGIC */ | |
3083 | [RCAR_GP_PIN(4, 25)] = { PUPR5, 15 }, /* AVS1 */ | |
3084 | [RCAR_GP_PIN(4, 26)] = { PUPR5, 16 }, /* AVS2 */ | |
3085 | }; | |
3086 | ||
3087 | static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc, | |
3088 | unsigned int pin) | |
3089 | { | |
3090 | void __iomem *addr; | |
3091 | ||
3092 | if (WARN_ON_ONCE(!pullups[pin].reg)) | |
3093 | return PIN_CONFIG_BIAS_DISABLE; | |
3094 | ||
3095 | addr = pfc->windows->virt + pullups[pin].reg; | |
3096 | ||
3097 | if (ioread32(addr) & BIT(pullups[pin].bit)) | |
3098 | return PIN_CONFIG_BIAS_PULL_UP; | |
3099 | else | |
3100 | return PIN_CONFIG_BIAS_DISABLE; | |
3101 | } | |
3102 | ||
3103 | static void r8a7778_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, | |
3104 | unsigned int bias) | |
3105 | { | |
3106 | void __iomem *addr; | |
3107 | u32 value; | |
3108 | u32 bit; | |
3109 | ||
3110 | if (WARN_ON_ONCE(!pullups[pin].reg)) | |
3111 | return; | |
3112 | ||
3113 | addr = pfc->windows->virt + pullups[pin].reg; | |
3114 | bit = BIT(pullups[pin].bit); | |
3115 | ||
3116 | value = ioread32(addr) & ~bit; | |
3117 | if (bias == PIN_CONFIG_BIAS_PULL_UP) | |
3118 | value |= bit; | |
3119 | iowrite32(value, addr); | |
3120 | } | |
3121 | ||
3122 | static const struct sh_pfc_soc_operations r8a7778_pfc_ops = { | |
3123 | .get_bias = r8a7778_pinmux_get_bias, | |
3124 | .set_bias = r8a7778_pinmux_set_bias, | |
3125 | }; | |
3126 | ||
87f8c988 KM |
3127 | const struct sh_pfc_soc_info r8a7778_pinmux_info = { |
3128 | .name = "r8a7778_pfc", | |
ae7465a0 | 3129 | .ops = &r8a7778_pfc_ops, |
87f8c988 KM |
3130 | |
3131 | .unlock_reg = 0xfffc0000, /* PMMR */ | |
3132 | ||
3133 | .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, | |
3134 | ||
3135 | .pins = pinmux_pins, | |
3136 | .nr_pins = ARRAY_SIZE(pinmux_pins), | |
3137 | ||
3138 | .groups = pinmux_groups, | |
3139 | .nr_groups = ARRAY_SIZE(pinmux_groups), | |
3140 | ||
3141 | .functions = pinmux_functions, | |
3142 | .nr_functions = ARRAY_SIZE(pinmux_functions), | |
3143 | ||
3144 | .cfg_regs = pinmux_config_regs, | |
3145 | ||
b8b47d67 GU |
3146 | .pinmux_data = pinmux_data, |
3147 | .pinmux_data_size = ARRAY_SIZE(pinmux_data), | |
87f8c988 | 3148 | }; |