[deliverable/linux.git] / drivers / pinctrl / sh-pfc / sh_pfc.h

/*
 * SuperH Pin Function Controller Support
 *
 * Copyright (c) 2008 Magnus Damm
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#ifndef __SH_PFC_H
#define __SH_PFC_H

#include <linux/bug.h>
#include <linux/stringify.h>

enum {
	PINMUX_TYPE_NONE,
	PINMUX_TYPE_FUNCTION,
	PINMUX_TYPE_GPIO,
	PINMUX_TYPE_OUTPUT,
	PINMUX_TYPE_INPUT,
};

#define SH_PFC_PIN_CFG_INPUT		(1 << 0)
#define SH_PFC_PIN_CFG_OUTPUT		(1 << 1)
#define SH_PFC_PIN_CFG_PULL_UP		(1 << 2)
#define SH_PFC_PIN_CFG_PULL_DOWN	(1 << 3)
#define SH_PFC_PIN_CFG_NO_GPIO		(1 << 31)

struct sh_pfc_pin {
	u16 pin;
	u16 enum_id;
	const char *name;
	unsigned int configs;
};

#define SH_PFC_PIN_GROUP(n)				\
	{						\
		.name = #n,				\
		.pins = n##_pins,			\
		.mux = n##_mux,				\
		.nr_pins = ARRAY_SIZE(n##_pins),	\
	}

struct sh_pfc_pin_group {
	const char *name;
	const unsigned int *pins;
	const unsigned int *mux;
	unsigned int nr_pins;
};

#define SH_PFC_FUNCTION(n)				\
	{						\
		.name = #n,				\
		.groups = n##_groups,			\
		.nr_groups = ARRAY_SIZE(n##_groups),	\
	}

struct sh_pfc_function {
	const char *name;
	const char * const *groups;
	unsigned int nr_groups;
};

struct pinmux_func {
	u16 enum_id;
	const char *name;
};

struct pinmux_cfg_reg {
	u32 reg;
	u8 reg_width, field_width;
	const u16 *enum_ids;
	const u8 *var_field_width;
};

#define PINMUX_CFG_REG(name, r, r_width, f_width) \
	.reg = r, .reg_width = r_width, .field_width = f_width,		\
	.enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])

#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
	.reg = r, .reg_width = r_width,	\
	.var_field_width = (const u8 [r_width]) \
		{ var_fw0, var_fwn, 0 }, \
	.enum_ids = (const u16 [])

struct pinmux_data_reg {
	u32 reg;
	u8 reg_width;
	const u16 *enum_ids;
};

#define PINMUX_DATA_REG(name, r, r_width) \
	.reg = r, .reg_width = r_width,	\
	.enum_ids = (const u16 [r_width]) \

struct pinmux_irq {
	int irq;
	const short *gpios;
};

#ifdef CONFIG_ARCH_MULTIPLATFORM
#define PINMUX_IRQ(irq_nr, ids...)			   \
	{ .gpios = (const short []) { ids, -1 } }
#else
#define PINMUX_IRQ(irq_nr, ids...)			   \
	{ .irq = irq_nr, .gpios = (const short []) { ids, -1 } }
#endif

struct pinmux_range {
	u16 begin;
	u16 end;
	u16 force;
};

struct sh_pfc;

struct sh_pfc_soc_operations {
	int (*init)(struct sh_pfc *pfc);
	unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
	void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
			 unsigned int bias);
};

struct sh_pfc_soc_info {
	const char *name;
	const struct sh_pfc_soc_operations *ops;

	struct pinmux_range input;
	struct pinmux_range output;
	struct pinmux_range function;

	const struct sh_pfc_pin *pins;
	unsigned int nr_pins;
	const struct sh_pfc_pin_group *groups;
	unsigned int nr_groups;
	const struct sh_pfc_function *functions;
	unsigned int nr_functions;

	const struct pinmux_func *func_gpios;
	unsigned int nr_func_gpios;

	const struct pinmux_cfg_reg *cfg_regs;
	const struct pinmux_data_reg *data_regs;

	const u16 *gpio_data;
	unsigned int gpio_data_size;

	const struct pinmux_irq *gpio_irq;
	unsigned int gpio_irq_size;

	u32 unlock_reg;
};

/* -----------------------------------------------------------------------------
 * Helper macros to create pin and port lists
 */

/*
 * sh_pfc_soc_info gpio_data array macros
 */

#define PINMUX_DATA(data_or_mark, ids...)	data_or_mark, ids, 0

#define PINMUX_IPSR_NOGP(ispr, fn)					\
	PINMUX_DATA(fn##_MARK, FN_##fn)
#define PINMUX_IPSR_DATA(ipsr, fn)					\
	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
#define PINMUX_IPSR_NOGM(ispr, fn, ms)					\
	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms)
#define PINMUX_IPSR_NOFN(ipsr, fn, ms)					\
	PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##ms)
#define PINMUX_IPSR_MSEL(ipsr, fn, ms)					\
	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms)
#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms)				\
	PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn)

/*
 * GP port style (32 ports banks)
 */

#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)

#define PORT_GP_32(bank, fn, sfx)					\
	PORT_GP_1(bank, 0,  fn, sfx), PORT_GP_1(bank, 1,  fn, sfx),	\
	PORT_GP_1(bank, 2,  fn, sfx), PORT_GP_1(bank, 3,  fn, sfx),	\
	PORT_GP_1(bank, 4,  fn, sfx), PORT_GP_1(bank, 5,  fn, sfx),	\
	PORT_GP_1(bank, 6,  fn, sfx), PORT_GP_1(bank, 7,  fn, sfx),	\
	PORT_GP_1(bank, 8,  fn, sfx), PORT_GP_1(bank, 9,  fn, sfx),	\
	PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx),	\
	PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx),	\
	PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx),	\
	PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx),	\
	PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx),	\
	PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx),	\
	PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx),	\
	PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx),	\
	PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx),	\
	PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx),	\
	PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)

#define PORT_GP_32_REV(bank, fn, sfx)					\
	PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx),	\
	PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx),	\
	PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx),	\
	PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx),	\
	PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx),	\
	PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx),	\
	PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx),	\
	PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx),	\
	PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx),	\
	PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx),	\
	PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx),	\
	PORT_GP_1(bank, 9,  fn, sfx), PORT_GP_1(bank, 8,  fn, sfx),	\
	PORT_GP_1(bank, 7,  fn, sfx), PORT_GP_1(bank, 6,  fn, sfx),	\
	PORT_GP_1(bank, 5,  fn, sfx), PORT_GP_1(bank, 4,  fn, sfx),	\
	PORT_GP_1(bank, 3,  fn, sfx), PORT_GP_1(bank, 2,  fn, sfx),	\
	PORT_GP_1(bank, 1,  fn, sfx), PORT_GP_1(bank, 0,  fn, sfx)

/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
#define _GP_ALL(bank, pin, name, sfx)	name##_##sfx
#define GP_ALL(str)			CPU_ALL_PORT(_GP_ALL, str)

/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
#define _GP_GPIO(bank, _pin, _name, sfx)				\
	[(bank * 32) + _pin] = {					\
		.pin = (bank * 32) + _pin,				\
		.name = __stringify(_name),				\
		.enum_id = _name##_DATA,				\
	}
#define PINMUX_GPIO_GP_ALL()		CPU_ALL_PORT(_GP_GPIO, unused)

/* PINMUX_DATA_GP_ALL -  Expand to a list of name_DATA, name_FN marks */
#define _GP_DATA(bank, pin, name, sfx)	PINMUX_DATA(name##_DATA, name##_FN)
#define PINMUX_DATA_GP_ALL()		CPU_ALL_PORT(_GP_DATA, unused)

/*
 * PORT style (linear pin space)
 */

#define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)

#define PORT_10(pn, fn, pfx, sfx)					  \
	PORT_1(pn,   fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx),	  \
	PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx),	  \
	PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx),	  \
	PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx),	  \
	PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)

#define PORT_90(pn, fn, pfx, sfx)					  \
	PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
	PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
	PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
	PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
	PORT_10(pn+90, fn, pfx##9, sfx)

/* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
#define _PORT_ALL(pn, pfx, sfx)		pfx##_##sfx
#define PORT_ALL(str)			CPU_ALL_PORT(_PORT_ALL, PORT, str)

/* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
#define PINMUX_GPIO(_pin)						\
	[GPIO_##_pin] = {						\
		.pin = (u16)-1,						\
		.name = __stringify(GPIO_##_pin),			\
		.enum_id = _pin##_DATA,					\
	}

/* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
#define SH_PFC_PIN_CFG(_pin, cfgs)					\
	{								\
		.pin = _pin,						\
		.name = __stringify(PORT##_pin),			\
		.enum_id = PORT##_pin##_DATA,				\
		.configs = cfgs,					\
	}

/* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */
#define SH_PFC_PIN_NAMED(row, col, _name)				\
	{								\
		.pin = PIN_NUMBER(row, col),				\
		.name = __stringify(PIN_##_name),			\
		.configs = SH_PFC_PIN_CFG_NO_GPIO,			\
	}

/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
 *		     PORT_name_OUT, PORT_name_IN marks
 */
#define _PORT_DATA(pn, pfx, sfx)					\
	PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0,			\
		    PORT##pfx##_OUT, PORT##pfx##_IN)
#define PINMUX_DATA_ALL()		CPU_ALL_PORT(_PORT_DATA, , unused)

/* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
#define PINMUX_GPIO_FN(gpio, base, data_or_mark)			\
	[gpio - (base)] = {						\
		.name = __stringify(gpio),				\
		.enum_id = data_or_mark,				\
	}
#define GPIO_FN(str)							\
	PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)

/*
 * PORTnCR macro
 */
#define PORTCR(nr, reg)							\
	{								\
		PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
			/* PULMD[1:0], handled by .set_bias() */	\
			0, 0, 0, 0,					\
			/* IE and OE */					\
			0, PORT##nr##_OUT, PORT##nr##_IN, 0,		\
			/* SEC, not supported */			\
			0, 0,						\
			/* PTMD[2:0] */					\
			PORT##nr##_FN0, PORT##nr##_FN1,			\
			PORT##nr##_FN2, PORT##nr##_FN3,			\
			PORT##nr##_FN4, PORT##nr##_FN5,			\
			PORT##nr##_FN6, PORT##nr##_FN7			\
		}							\
	}

#endif /* __SH_PFC_H */
Commit	Line	Data
fae43399 MD	1	/*
	2	* SuperH Pin Function Controller Support
	3	*
	4	* Copyright (c) 2008 Magnus Damm
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10
	11	#ifndef __SH_PFC_H
	12	#define __SH_PFC_H
	13
bf9f0674	14	#include <linux/bug.h>
72c7afa1	15	#include <linux/stringify.h>
fae43399	16
06d5631f PM	17	enum {
06d5631f PM	18	PINMUX_TYPE_NONE,
06d5631f PM	19	PINMUX_TYPE_FUNCTION,
	20	PINMUX_TYPE_GPIO,
	21	PINMUX_TYPE_OUTPUT,
	22	PINMUX_TYPE_INPUT,
06d5631f	23	};
fae43399	24
c58d9c1b LP	25	#define SH_PFC_PIN_CFG_INPUT (1 << 0)
	26	#define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
	27	#define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
	28	#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
4f82e3ee	29	#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
c58d9c1b	30
a3db40a6	31	struct sh_pfc_pin {
9689896c	32	u16 pin;
533743dc	33	u16 enum_id;
72c7afa1	34	const char *name;
c58d9c1b	35	unsigned int configs;
fae43399 MD	36	};
fae43399 MD	37
3d8d9f1d LP	38	#define SH_PFC_PIN_GROUP(n) \
	39	{ \
	40	.name = #n, \
	41	.pins = n##_pins, \
	42	.mux = n##_mux, \
	43	.nr_pins = ARRAY_SIZE(n##_pins), \
	44	}
	45
	46	struct sh_pfc_pin_group {
	47	const char *name;
	48	const unsigned int *pins;
	49	const unsigned int *mux;
	50	unsigned int nr_pins;
	51	};
	52
	53	#define SH_PFC_FUNCTION(n) \
	54	{ \
	55	.name = #n, \
	56	.groups = n##_groups, \
	57	.nr_groups = ARRAY_SIZE(n##_groups), \
	58	}
	59
	60	struct sh_pfc_function {
	61	const char *name;
	62	const char * const *groups;
	63	unsigned int nr_groups;
	64	};
	65
a373ed0a	66	struct pinmux_func {
533743dc	67	u16 enum_id;
a373ed0a LP	68	const char *name;
	69	};
	70
fae43399	71	struct pinmux_cfg_reg {
1f34de05	72	u32 reg;
dc700715	73	u8 reg_width, field_width;
533743dc	74	const u16 *enum_ids;
dc700715	75	const u8 *var_field_width;
fae43399 MD	76	};
	77
	78	#define PINMUX_CFG_REG(name, r, r_width, f_width) \
	79	.reg = r, .reg_width = r_width, .field_width = f_width, \
9aecff58	80	.enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
f78a26f5 MD	81
	82	#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
	83	.reg = r, .reg_width = r_width, \
dc700715	84	.var_field_width = (const u8 [r_width]) \
9aecff58 LP	85	{ var_fw0, var_fwn, 0 }, \
9aecff58 LP	86	.enum_ids = (const u16 [])
fae43399 MD	87
fae43399 MD	88	struct pinmux_data_reg {
1f34de05	89	u32 reg;
dc700715	90	u8 reg_width;
533743dc	91	const u16 *enum_ids;
fae43399 MD	92	};
	93
	94	#define PINMUX_DATA_REG(name, r, r_width) \
	95	.reg = r, .reg_width = r_width, \
9aecff58	96	.enum_ids = (const u16 [r_width]) \
fae43399	97
ad2a8e7e MD	98	struct pinmux_irq {
ad2a8e7e MD	99	int irq;
6d5bddd5	100	const short *gpios;
ad2a8e7e MD	101	};
ad2a8e7e MD	102
0e26e8df LP	103	#ifdef CONFIG_ARCH_MULTIPLATFORM
	104	#define PINMUX_IRQ(irq_nr, ids...) \
	105	{ .gpios = (const short []) { ids, -1 } }
	106	#else
ad2a8e7e	107	#define PINMUX_IRQ(irq_nr, ids...) \
6d5bddd5	108	{ .irq = irq_nr, .gpios = (const short []) { ids, -1 } }
0e26e8df	109	#endif
ad2a8e7e	110
fae43399	111	struct pinmux_range {
533743dc LP	112	u16 begin;
	113	u16 end;
	114	u16 force;
fae43399 MD	115	};
fae43399 MD	116
c58d9c1b LP	117	struct sh_pfc;
	118
	119	struct sh_pfc_soc_operations {
0c151062	120	int (init)(struct sh_pfc pfc);
c58d9c1b LP	121	unsigned int (get_bias)(struct sh_pfc pfc, unsigned int pin);
	122	void (set_bias)(struct sh_pfc pfc, unsigned int pin,
	123	unsigned int bias);
	124	};
	125
19bb7fe3	126	struct sh_pfc_soc_info {
cd3c1bee	127	const char *name;
c58d9c1b LP	128	const struct sh_pfc_soc_operations *ops;
c58d9c1b LP	129
fae43399	130	struct pinmux_range input;
fae43399	131	struct pinmux_range output;
fae43399 MD	132	struct pinmux_range function;
fae43399 MD	133
cd3c1bee	134	const struct sh_pfc_pin *pins;
caa5bac3	135	unsigned int nr_pins;
3d8d9f1d LP	136	const struct sh_pfc_pin_group *groups;
	137	unsigned int nr_groups;
	138	const struct sh_pfc_function *functions;
	139	unsigned int nr_functions;
	140
cd3c1bee	141	const struct pinmux_func *func_gpios;
a373ed0a	142	unsigned int nr_func_gpios;
d7a7ca57	143
cd3c1bee LP	144	const struct pinmux_cfg_reg *cfg_regs;
cd3c1bee LP	145	const struct pinmux_data_reg *data_regs;
fae43399	146
533743dc	147	const u16 *gpio_data;
fae43399 MD	148	unsigned int gpio_data_size;
fae43399 MD	149
cd3c1bee	150	const struct pinmux_irq *gpio_irq;
ad2a8e7e MD	151	unsigned int gpio_irq_size;
ad2a8e7e MD	152
1f34de05	153	u32 unlock_reg;
fae43399 MD	154	};
fae43399 MD	155
e3d93b46 LP	156	/* -----------------------------------------------------------------------------
	157	* Helper macros to create pin and port lists
	158	*/
	159
	160	/*
	161	* sh_pfc_soc_info gpio_data array macros
	162	*/
	163
	164	#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
	165
	166	#define PINMUX_IPSR_NOGP(ispr, fn) \
	167	PINMUX_DATA(fn##_MARK, FN_##fn)
	168	#define PINMUX_IPSR_DATA(ipsr, fn) \
	169	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
	170	#define PINMUX_IPSR_NOGM(ispr, fn, ms) \
	171	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms)
4c9e4735 NS	172	#define PINMUX_IPSR_NOFN(ipsr, fn, ms) \
4c9e4735 NS	173	PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##ms)
e3d93b46 LP	174	#define PINMUX_IPSR_MSEL(ipsr, fn, ms) \
	175	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms)
	176	#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) \
	177	PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn)
	178
	179	/*
	180	* GP port style (32 ports banks)
	181	*/
	182
	183	#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
	184
	185	#define PORT_GP_32(bank, fn, sfx) \
	186	PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
	187	PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
	188	PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
	189	PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
	190	PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
	191	PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
	192	PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
	193	PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
	194	PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
	195	PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
	196	PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
	197	PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
	198	PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
	199	PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \
	200	PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \
	201	PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
	202
	203	#define PORT_GP_32_REV(bank, fn, sfx) \
	204	PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
	205	PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
	206	PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
	207	PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
	208	PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
	209	PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
	210	PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
	211	PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
	212	PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
	213	PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
	214	PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
	215	PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
	216	PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
	217	PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
	218	PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
	219	PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
	220
	221	/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
	222	#define _GP_ALL(bank, pin, name, sfx) name##_##sfx
	223	#define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str)
	224
	225	/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
9689896c LP	226	#define _GP_GPIO(bank, _pin, _name, sfx) \
	227	[(bank * 32) + _pin] = { \
	228	.pin = (bank * 32) + _pin, \
e3d93b46 LP	229	.name = __stringify(_name), \
	230	.enum_id = _name##_DATA, \
	231	}
	232	#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
	233
	234	/* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
	235	#define _GP_DATA(bank, pin, name, sfx) PINMUX_DATA(name##_DATA, name##_FN)
	236	#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
	237
	238	/*
	239	* PORT style (linear pin space)
	240	*/
	241
3ce0d7eb	242	#define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
16b915e4 LP	243
	244	#define PORT_10(pn, fn, pfx, sfx) \
	245	PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \
	246	PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \
	247	PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \
	248	PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \
	249	PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
	250
	251	#define PORT_90(pn, fn, pfx, sfx) \
	252	PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
	253	PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
	254	PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
	255	PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
	256	PORT_10(pn+90, fn, pfx##9, sfx)
972c3fb6	257
e3d93b46	258	/* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
3ce0d7eb	259	#define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx
e3d93b46	260	#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
972c3fb6	261
e3d93b46	262	/* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
9689896c LP	263	#define PINMUX_GPIO(_pin) \
	264	[GPIO_##_pin] = { \
	265	.pin = (u16)-1, \
8620f394	266	.name = __stringify(GPIO_##_pin), \
9689896c	267	.enum_id = _pin##_DATA, \
e3d93b46 LP	268	}
e3d93b46 LP	269
df020272	270	/* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
9689896c	271	#define SH_PFC_PIN_CFG(_pin, cfgs) \
df020272	272	{ \
9689896c LP	273	.pin = _pin, \
	274	.name = __stringify(PORT##_pin), \
	275	.enum_id = PORT##_pin##_DATA, \
df020272 LP	276	.configs = cfgs, \
	277	}
	278
4f82e3ee LP	279	/* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */
	280	#define SH_PFC_PIN_NAMED(row, col, _name) \
	281	{ \
	282	.pin = PIN_NUMBER(row, col), \
	283	.name = __stringify(PIN_##_name), \
	284	.configs = SH_PFC_PIN_CFG_NO_GPIO, \
	285	}
	286
e3d93b46 LP	287	/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
	288	* PORT_name_OUT, PORT_name_IN marks
	289	*/
3ce0d7eb	290	#define _PORT_DATA(pn, pfx, sfx) \
e3d93b46 LP	291	PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
	292	PORT##pfx##_OUT, PORT##pfx##_IN)
	293	#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
	294
	295	/* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
	296	#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
	297	[gpio - (base)] = { \
	298	.name = __stringify(gpio), \
	299	.enum_id = data_or_mark, \
	300	}
	301	#define GPIO_FN(str) \
	302	PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
bd8d0cba	303
e3d93b46 LP	304	/*
	305	* PORTnCR macro
	306	*/
9b49139b KM	307	#define PORTCR(nr, reg) \
9b49139b KM	308	{ \
05c5f265 GU	309	PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
	310	/* PULMD[1:0], handled by .set_bias() */ \
	311	0, 0, 0, 0, \
	312	/* IE and OE */ \
	313	0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
	314	/* SEC, not supported */ \
	315	0, 0, \
	316	/* PTMD[2:0] */ \
	317	PORT##nr##_FN0, PORT##nr##_FN1, \
	318	PORT##nr##_FN2, PORT##nr##_FN3, \
	319	PORT##nr##_FN4, PORT##nr##_FN5, \
	320	PORT##nr##_FN6, PORT##nr##_FN7 \
	321	} \
9b49139b	322	}
bd8d0cba	323
fae43399	324	#endif /* __SH_PFC_H */