[deliverable/linux.git] / drivers / pinctrl / sh-pfc / sh_pfc.h

/*
 * SuperH Pin Function Controller Support
 *
 * Copyright (c) 2008 Magnus Damm
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#ifndef __SH_PFC_H
#define __SH_PFC_H

#include <linux/stringify.h>
#include <asm-generic/gpio.h>

typedef unsigned short pinmux_enum_t;
typedef unsigned short pinmux_flag_t;

enum {
	PINMUX_TYPE_NONE,

	PINMUX_TYPE_FUNCTION,
	PINMUX_TYPE_GPIO,
	PINMUX_TYPE_OUTPUT,
	PINMUX_TYPE_INPUT,
	PINMUX_TYPE_INPUT_PULLUP,
	PINMUX_TYPE_INPUT_PULLDOWN,

	PINMUX_FLAG_TYPE,	/* must be last */
};

#define PINMUX_FLAG_DBIT_SHIFT      5
#define PINMUX_FLAG_DBIT            (0x1f << PINMUX_FLAG_DBIT_SHIFT)
#define PINMUX_FLAG_DREG_SHIFT      10
#define PINMUX_FLAG_DREG            (0x3f << PINMUX_FLAG_DREG_SHIFT)

struct pinmux_gpio {
	const pinmux_enum_t enum_id;
	pinmux_flag_t flags;
	const char *name;
};

#define PINMUX_GPIO(gpio, data_or_mark)			\
	[gpio] = {					\
		.name = __stringify(gpio),		\
		.enum_id = data_or_mark,		\
		.flags = PINMUX_TYPE_GPIO		\
	}
#define PINMUX_GPIO_FN(gpio, data_or_mark)		\
	[gpio] = {					\
		.name = __stringify(gpio),		\
		.enum_id = data_or_mark,		\
		.flags = PINMUX_TYPE_FUNCTION		\
	}

#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0

struct pinmux_cfg_reg {
	unsigned long reg, reg_width, field_width;
	unsigned long *cnt;
	pinmux_enum_t *enum_ids;
	unsigned long *var_field_width;
};

#define PINMUX_CFG_REG(name, r, r_width, f_width) \
	.reg = r, .reg_width = r_width, .field_width = f_width,		\
	.cnt = (unsigned long [r_width / f_width]) {}, \
	.enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)])

#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
	.reg = r, .reg_width = r_width,	\
	.cnt = (unsigned long [r_width]) {}, \
	.var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \
	.enum_ids = (pinmux_enum_t [])

struct pinmux_data_reg {
	unsigned long reg, reg_width, reg_shadow;
	pinmux_enum_t *enum_ids;
	void __iomem *mapped_reg;
};

#define PINMUX_DATA_REG(name, r, r_width) \
	.reg = r, .reg_width = r_width,	\
	.enum_ids = (pinmux_enum_t [r_width]) \

struct pinmux_irq {
	int irq;
	pinmux_enum_t *enum_ids;
};

#define PINMUX_IRQ(irq_nr, ids...)			   \
	{ .irq = irq_nr, .enum_ids = (pinmux_enum_t []) { ids, 0 } }	\

struct pinmux_range {
	pinmux_enum_t begin;
	pinmux_enum_t end;
	pinmux_enum_t force;
};

struct sh_pfc_soc_info {
	char *name;
	struct pinmux_range input;
	struct pinmux_range input_pd;
	struct pinmux_range input_pu;
	struct pinmux_range output;
	struct pinmux_range function;

	struct pinmux_gpio *gpios;
	unsigned int nr_pins;
	unsigned int nr_gpios;

	struct pinmux_cfg_reg *cfg_regs;
	struct pinmux_data_reg *data_regs;

	pinmux_enum_t *gpio_data;
	unsigned int gpio_data_size;

	struct pinmux_irq *gpio_irq;
	unsigned int gpio_irq_size;

	unsigned long unlock_reg;
};

enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };

/* helper macro for port */
#define PORT_1(fn, pfx, sfx) fn(pfx, sfx)

#define PORT_10(fn, pfx, sfx) \
	PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx),	\
	PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx),	\
	PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx),	\
	PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx),	\
	PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx)

#define PORT_90(fn, pfx, sfx) \
	PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx),	\
	PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx),	\
	PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx),	\
	PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx),	\
	PORT_10(fn, pfx##9, sfx)

#define _PORT_ALL(pfx, sfx) pfx##_##sfx
#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
#define PORT_ALL(str)	CPU_ALL_PORT(_PORT_ALL, PORT, str)
#define GPIO_PORT_ALL()	CPU_ALL_PORT(_GPIO_PORT, , unused)
#define GPIO_FN(str) PINMUX_GPIO_FN(GPIO_FN_##str, str##_MARK)

/* helper macro for pinmux_enum_t */
#define PORT_DATA_I(nr)	\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)

#define PORT_DATA_I_PD(nr)	\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,	\
		    PORT##nr##_IN, PORT##nr##_IN_PD)

#define PORT_DATA_I_PU(nr)	\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,	\
		    PORT##nr##_IN, PORT##nr##_IN_PU)

#define PORT_DATA_I_PU_PD(nr)	\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0,			\
		    PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)

#define PORT_DATA_O(nr)		\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT)

#define PORT_DATA_IO(nr)	\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT,	\
		    PORT##nr##_IN)

#define PORT_DATA_IO_PD(nr)	\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT,	\
		    PORT##nr##_IN, PORT##nr##_IN_PD)

#define PORT_DATA_IO_PU(nr)	\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT,	\
		    PORT##nr##_IN, PORT##nr##_IN_PU)

#define PORT_DATA_IO_PU_PD(nr)	\
	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT,	\
		    PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)

/* helper macro for top 4 bits in PORTnCR */
#define _PCRH(in, in_pd, in_pu, out)	\
	0, (out), (in), 0,		\
	0, 0, 0, 0,			\
	0, 0, (in_pd), 0,		\
	0, 0, (in_pu), 0

#define PORTCR(nr, reg)							\
	{								\
		PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) {		\
			_PCRH(PORT##nr##_IN, PORT##nr##_IN_PD,		\
			      PORT##nr##_IN_PU, PORT##nr##_OUT),	\
				PORT##nr##_FN0, PORT##nr##_FN1,		\
				PORT##nr##_FN2, PORT##nr##_FN3,		\
				PORT##nr##_FN4, PORT##nr##_FN5,		\
				PORT##nr##_FN6, PORT##nr##_FN7 }	\
	}

#endif /* __SH_PFC_H */
Commit	Line	Data
fae43399 MD	1	/*
	2	* SuperH Pin Function Controller Support
	3	*
	4	* Copyright (c) 2008 Magnus Damm
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10
	11	#ifndef __SH_PFC_H
	12	#define __SH_PFC_H
	13
72c7afa1	14	#include <linux/stringify.h>
fae43399 MD	15	#include <asm-generic/gpio.h>
	16
	17	typedef unsigned short pinmux_enum_t;
	18	typedef unsigned short pinmux_flag_t;
	19
06d5631f PM	20	enum {
06d5631f PM	21	PINMUX_TYPE_NONE,
fae43399	22
06d5631f PM	23	PINMUX_TYPE_FUNCTION,
	24	PINMUX_TYPE_GPIO,
	25	PINMUX_TYPE_OUTPUT,
	26	PINMUX_TYPE_INPUT,
	27	PINMUX_TYPE_INPUT_PULLUP,
	28	PINMUX_TYPE_INPUT_PULLDOWN,
	29
	30	PINMUX_FLAG_TYPE, /* must be last */
	31	};
fae43399 MD	32
	33	#define PINMUX_FLAG_DBIT_SHIFT 5
	34	#define PINMUX_FLAG_DBIT (0x1f << PINMUX_FLAG_DBIT_SHIFT)
	35	#define PINMUX_FLAG_DREG_SHIFT 10
	36	#define PINMUX_FLAG_DREG (0x3f << PINMUX_FLAG_DREG_SHIFT)
	37
	38	struct pinmux_gpio {
051fae4b	39	const pinmux_enum_t enum_id;
fae43399	40	pinmux_flag_t flags;
72c7afa1	41	const char *name;
fae43399 MD	42	};
fae43399 MD	43
380c2ed9 LP	44	#define PINMUX_GPIO(gpio, data_or_mark) \
	45	[gpio] = { \
	46	.name = __stringify(gpio), \
	47	.enum_id = data_or_mark, \
	48	.flags = PINMUX_TYPE_GPIO \
	49	}
	50	#define PINMUX_GPIO_FN(gpio, data_or_mark) \
	51	[gpio] = { \
	52	.name = __stringify(gpio), \
	53	.enum_id = data_or_mark, \
	54	.flags = PINMUX_TYPE_FUNCTION \
	55	}
06d5631f	56
fae43399 MD	57	#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
	58
	59	struct pinmux_cfg_reg {
	60	unsigned long reg, reg_width, field_width;
	61	unsigned long *cnt;
	62	pinmux_enum_t *enum_ids;
f78a26f5	63	unsigned long *var_field_width;
fae43399 MD	64	};
	65
	66	#define PINMUX_CFG_REG(name, r, r_width, f_width) \
	67	.reg = r, .reg_width = r_width, .field_width = f_width, \
	68	.cnt = (unsigned long [r_width / f_width]) {}, \
f78a26f5 MD	69	.enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)])
	70
	71	#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
	72	.reg = r, .reg_width = r_width, \
	73	.cnt = (unsigned long [r_width]) {}, \
	74	.var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \
	75	.enum_ids = (pinmux_enum_t [])
fae43399 MD	76
	77	struct pinmux_data_reg {
	78	unsigned long reg, reg_width, reg_shadow;
	79	pinmux_enum_t *enum_ids;
b0e10211	80	void __iomem *mapped_reg;
fae43399 MD	81	};
	82
	83	#define PINMUX_DATA_REG(name, r, r_width) \
	84	.reg = r, .reg_width = r_width, \
	85	.enum_ids = (pinmux_enum_t [r_width]) \
	86
ad2a8e7e MD	87	struct pinmux_irq {
	88	int irq;
	89	pinmux_enum_t *enum_ids;
	90	};
	91
	92	#define PINMUX_IRQ(irq_nr, ids...) \
	93	{ .irq = irq_nr, .enum_ids = (pinmux_enum_t []) { ids, 0 } } \
	94
fae43399 MD	95	struct pinmux_range {
	96	pinmux_enum_t begin;
	97	pinmux_enum_t end;
	98	pinmux_enum_t force;
	99	};
	100
19bb7fe3	101	struct sh_pfc_soc_info {
fae43399	102	char *name;
fae43399 MD	103	struct pinmux_range input;
	104	struct pinmux_range input_pd;
	105	struct pinmux_range input_pu;
	106	struct pinmux_range output;
fae43399 MD	107	struct pinmux_range function;
fae43399 MD	108
fae43399	109	struct pinmux_gpio *gpios;
caa5bac3	110	unsigned int nr_pins;
d7a7ca57 LP	111	unsigned int nr_gpios;
d7a7ca57 LP	112
fae43399 MD	113	struct pinmux_cfg_reg *cfg_regs;
	114	struct pinmux_data_reg *data_regs;
	115
	116	pinmux_enum_t *gpio_data;
	117	unsigned int gpio_data_size;
	118
ad2a8e7e MD	119	struct pinmux_irq *gpio_irq;
	120	unsigned int gpio_irq_size;
	121
e499ada8	122	unsigned long unlock_reg;
fae43399 MD	123	};
fae43399 MD	124
b3c185a7	125	enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
fae43399	126
972c3fb6 KM	127	/* helper macro for port */
	128	#define PORT_1(fn, pfx, sfx) fn(pfx, sfx)
	129
	130	#define PORT_10(fn, pfx, sfx) \
	131	PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \
	132	PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \
	133	PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \
	134	PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \
	135	PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx)
	136
	137	#define PORT_90(fn, pfx, sfx) \
	138	PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \
	139	PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \
	140	PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx), \
	141	PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx), \
	142	PORT_10(fn, pfx##9, sfx)
	143
	144	#define _PORT_ALL(pfx, sfx) pfx##_##sfx
	145	#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
	146	#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
	147	#define GPIO_PORT_ALL() CPU_ALL_PORT(_GPIO_PORT, , unused)
380c2ed9	148	#define GPIO_FN(str) PINMUX_GPIO_FN(GPIO_FN_##str, str##_MARK)
972c3fb6	149
bd8d0cba KM	150	/* helper macro for pinmux_enum_t */
	151	#define PORT_DATA_I(nr) \
	152	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
	153
	154	#define PORT_DATA_I_PD(nr) \
	155	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
	156	PORT##nr##_IN, PORT##nr##_IN_PD)
	157
	158	#define PORT_DATA_I_PU(nr) \
	159	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
	160	PORT##nr##_IN, PORT##nr##_IN_PU)
	161
	162	#define PORT_DATA_I_PU_PD(nr) \
	163	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
	164	PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
	165
	166	#define PORT_DATA_O(nr) \
	167	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT)
	168
	169	#define PORT_DATA_IO(nr) \
	170	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
	171	PORT##nr##_IN)
	172
	173	#define PORT_DATA_IO_PD(nr) \
	174	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
	175	PORT##nr##_IN, PORT##nr##_IN_PD)
	176
	177	#define PORT_DATA_IO_PU(nr) \
	178	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
	179	PORT##nr##_IN, PORT##nr##_IN_PU)
	180
	181	#define PORT_DATA_IO_PU_PD(nr) \
	182	PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
	183	PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
	184
9b49139b KM	185	/* helper macro for top 4 bits in PORTnCR */
	186	#define _PCRH(in, in_pd, in_pu, out) \
	187	0, (out), (in), 0, \
	188	0, 0, 0, 0, \
	189	0, 0, (in_pd), 0, \
	190	0, 0, (in_pu), 0
	191
	192	#define PORTCR(nr, reg) \
	193	{ \
	194	PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
	195	_PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \
	196	PORT##nr##_IN_PU, PORT##nr##_OUT), \
	197	PORT##nr##_FN0, PORT##nr##_FN1, \
	198	PORT##nr##_FN2, PORT##nr##_FN3, \
	199	PORT##nr##_FN4, PORT##nr##_FN5, \
	200	PORT##nr##_FN6, PORT##nr##_FN7 } \
	201	}
bd8d0cba	202
fae43399	203	#endif /* __SH_PFC_H */