[deliverable/linux.git] / drivers / pinctrl / sh-pfc / sh_pfc.h

/*
 * SuperH Pin Function Controller Support
 *
 * Copyright (c) 2008 Magnus Damm
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#ifndef __SH_PFC_H
#define __SH_PFC_H

#include <linux/bug.h>
#include <linux/stringify.h>

enum {
	PINMUX_TYPE_NONE,
	PINMUX_TYPE_FUNCTION,
	PINMUX_TYPE_GPIO,
	PINMUX_TYPE_OUTPUT,
	PINMUX_TYPE_INPUT,
};

#define SH_PFC_PIN_CFG_INPUT		(1 << 0)
#define SH_PFC_PIN_CFG_OUTPUT		(1 << 1)
#define SH_PFC_PIN_CFG_PULL_UP		(1 << 2)
#define SH_PFC_PIN_CFG_PULL_DOWN	(1 << 3)

struct sh_pfc_pin {
	u16 enum_id;
	const char *name;
	unsigned int configs;
};

#define SH_PFC_PIN_GROUP(n)				\
	{						\
		.name = #n,				\
		.pins = n##_pins,			\
		.mux = n##_mux,				\
		.nr_pins = ARRAY_SIZE(n##_pins),	\
	}

struct sh_pfc_pin_group {
	const char *name;
	const unsigned int *pins;
	const unsigned int *mux;
	unsigned int nr_pins;
};

#define SH_PFC_FUNCTION(n)				\
	{						\
		.name = #n,				\
		.groups = n##_groups,			\
		.nr_groups = ARRAY_SIZE(n##_groups),	\
	}

struct sh_pfc_function {
	const char *name;
	const char * const *groups;
	unsigned int nr_groups;
};

struct pinmux_func {
	u16 enum_id;
	const char *name;
};

struct pinmux_cfg_reg {
	unsigned long reg, reg_width, field_width;
	const u16 *enum_ids;
	const unsigned long *var_field_width;
};

#define PINMUX_CFG_REG(name, r, r_width, f_width) \
	.reg = r, .reg_width = r_width, .field_width = f_width,		\
	.enum_ids = (u16 [(r_width / f_width) * (1 << f_width)])

#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
	.reg = r, .reg_width = r_width,	\
	.var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \
	.enum_ids = (u16 [])

struct pinmux_data_reg {
	unsigned long reg, reg_width;
	const u16 *enum_ids;
};

#define PINMUX_DATA_REG(name, r, r_width) \
	.reg = r, .reg_width = r_width,	\
	.enum_ids = (u16 [r_width]) \

struct pinmux_irq {
	int irq;
	unsigned short *gpios;
};

#define PINMUX_IRQ(irq_nr, ids...)			   \
	{ .irq = irq_nr, .gpios = (unsigned short []) { ids, 0 } }	\

struct pinmux_range {
	u16 begin;
	u16 end;
	u16 force;
};

struct sh_pfc;

struct sh_pfc_soc_operations {
	int (*init)(struct sh_pfc *pfc);
	void (*exit)(struct sh_pfc *pfc);
	unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
	void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
			 unsigned int bias);
};

struct sh_pfc_soc_info {
	const char *name;
	const struct sh_pfc_soc_operations *ops;

	struct pinmux_range input;
	struct pinmux_range output;
	struct pinmux_range function;

	const struct sh_pfc_pin *pins;
	unsigned int nr_pins;
	const struct pinmux_range *ranges;
	unsigned int nr_ranges;
	const struct sh_pfc_pin_group *groups;
	unsigned int nr_groups;
	const struct sh_pfc_function *functions;
	unsigned int nr_functions;

	const struct pinmux_func *func_gpios;
	unsigned int nr_func_gpios;

	const struct pinmux_cfg_reg *cfg_regs;
	const struct pinmux_data_reg *data_regs;

	const u16 *gpio_data;
	unsigned int gpio_data_size;

	const struct pinmux_irq *gpio_irq;
	unsigned int gpio_irq_size;

	unsigned long unlock_reg;
};

/* -----------------------------------------------------------------------------
 * Helper macros to create pin and port lists
 */

/*
 * sh_pfc_soc_info gpio_data array macros
 */

#define PINMUX_DATA(data_or_mark, ids...)	data_or_mark, ids, 0

#define PINMUX_IPSR_NOGP(ispr, fn)					\
	PINMUX_DATA(fn##_MARK, FN_##fn)
#define PINMUX_IPSR_DATA(ipsr, fn)					\
	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
#define PINMUX_IPSR_NOGM(ispr, fn, ms)					\
	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms)
#define PINMUX_IPSR_MSEL(ipsr, fn, ms)					\
	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms)
#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms)				\
	PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn)

/*
 * GP port style (32 ports banks)
 */

#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)

#define PORT_GP_32(bank, fn, sfx)					\
	PORT_GP_1(bank, 0,  fn, sfx), PORT_GP_1(bank, 1,  fn, sfx),	\
	PORT_GP_1(bank, 2,  fn, sfx), PORT_GP_1(bank, 3,  fn, sfx),	\
	PORT_GP_1(bank, 4,  fn, sfx), PORT_GP_1(bank, 5,  fn, sfx),	\
	PORT_GP_1(bank, 6,  fn, sfx), PORT_GP_1(bank, 7,  fn, sfx),	\
	PORT_GP_1(bank, 8,  fn, sfx), PORT_GP_1(bank, 9,  fn, sfx),	\
	PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx),	\
	PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx),	\
	PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx),	\
	PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx),	\
	PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx),	\
	PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx),	\
	PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx),	\
	PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx),	\
	PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx),	\
	PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx),	\
	PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)

#define PORT_GP_32_REV(bank, fn, sfx)					\
	PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx),	\
	PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx),	\
	PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx),	\
	PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx),	\
	PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx),	\
	PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx),	\
	PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx),	\
	PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx),	\
	PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx),	\
	PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx),	\
	PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx),	\
	PORT_GP_1(bank, 9,  fn, sfx), PORT_GP_1(bank, 8,  fn, sfx),	\
	PORT_GP_1(bank, 7,  fn, sfx), PORT_GP_1(bank, 6,  fn, sfx),	\
	PORT_GP_1(bank, 5,  fn, sfx), PORT_GP_1(bank, 4,  fn, sfx),	\
	PORT_GP_1(bank, 3,  fn, sfx), PORT_GP_1(bank, 2,  fn, sfx),	\
	PORT_GP_1(bank, 1,  fn, sfx), PORT_GP_1(bank, 0,  fn, sfx)

/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
#define _GP_ALL(bank, pin, name, sfx)	name##_##sfx
#define GP_ALL(str)			CPU_ALL_PORT(_GP_ALL, str)

/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
#define _GP_GPIO(bank, pin, _name, sfx)					\
	[(bank * 32) + pin] = {						\
		.name = __stringify(_name),				\
		.enum_id = _name##_DATA,				\
	}
#define PINMUX_GPIO_GP_ALL()		CPU_ALL_PORT(_GP_GPIO, unused)

/* PINMUX_DATA_GP_ALL -  Expand to a list of name_DATA, name_FN marks */
#define _GP_DATA(bank, pin, name, sfx)	PINMUX_DATA(name##_DATA, name##_FN)
#define PINMUX_DATA_GP_ALL()		CPU_ALL_PORT(_GP_DATA, unused)

/*
 * PORT style (linear pin space)
 */

#define PORT_1(fn, pfx, sfx) fn(pfx, sfx)

#define PORT_10(fn, pfx, sfx)						\
	PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx),		\
	PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx),		\
	PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx),		\
	PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx),		\
	PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx)

#define PORT_90(fn, pfx, sfx) \
	PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx),		\
	PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx),		\
	PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx),		\
	PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx),		\
	PORT_10(fn, pfx##9, sfx)

/* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
#define _PORT_ALL(pfx, sfx)		pfx##_##sfx
#define PORT_ALL(str)			CPU_ALL_PORT(_PORT_ALL, PORT, str)

/* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
#define PINMUX_GPIO(pin)						\
	[GPIO_##pin] = {						\
		.name = __stringify(name),				\
		.enum_id = pin##_DATA,					\
	}

/* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
#define SH_PFC_PIN_CFG(pin, cfgs)					\
	{								\
		.name = __stringify(PORT##pin),				\
		.enum_id = PORT##pin##_DATA,				\
		.configs = cfgs,					\
	}

/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
 *		     PORT_name_OUT, PORT_name_IN marks
 */
#define _PORT_DATA(pfx, sfx)						\
	PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0,			\
		    PORT##pfx##_OUT, PORT##pfx##_IN)
#define PINMUX_DATA_ALL()		CPU_ALL_PORT(_PORT_DATA, , unused)

/* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
#define PINMUX_GPIO_FN(gpio, base, data_or_mark)			\
	[gpio - (base)] = {						\
		.name = __stringify(gpio),				\
		.enum_id = data_or_mark,				\
	}
#define GPIO_FN(str)							\
	PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)

/*
 * PORTnCR macro
 */
#define _PCRH(in, in_pd, in_pu, out)	\
	0, (out), (in), 0,		\
	0, 0, 0, 0,			\
	0, 0, (in_pd), 0,		\
	0, 0, (in_pu), 0

#define PORTCR(nr, reg)							\
	{								\
		PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) {		\
			_PCRH(PORT##nr##_IN, PORT##nr##_IN_PD,		\
			      PORT##nr##_IN_PU, PORT##nr##_OUT),	\
				PORT##nr##_FN0, PORT##nr##_FN1,		\
				PORT##nr##_FN2, PORT##nr##_FN3,		\
				PORT##nr##_FN4, PORT##nr##_FN5,		\
				PORT##nr##_FN6, PORT##nr##_FN7 }	\
	}

#endif /* __SH_PFC_H */
Commit	Line	Data
fae43399 MD	1	/*
	2	* SuperH Pin Function Controller Support
	3	*
	4	* Copyright (c) 2008 Magnus Damm
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10
	11	#ifndef __SH_PFC_H
	12	#define __SH_PFC_H
	13
bf9f0674	14	#include <linux/bug.h>
72c7afa1	15	#include <linux/stringify.h>
fae43399	16
06d5631f PM	17	enum {
06d5631f PM	18	PINMUX_TYPE_NONE,
06d5631f PM	19	PINMUX_TYPE_FUNCTION,
	20	PINMUX_TYPE_GPIO,
	21	PINMUX_TYPE_OUTPUT,
	22	PINMUX_TYPE_INPUT,
06d5631f	23	};
fae43399	24
c58d9c1b LP	25	#define SH_PFC_PIN_CFG_INPUT (1 << 0)
	26	#define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
	27	#define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
	28	#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
	29
a3db40a6	30	struct sh_pfc_pin {
533743dc	31	u16 enum_id;
72c7afa1	32	const char *name;
c58d9c1b	33	unsigned int configs;
fae43399 MD	34	};
fae43399 MD	35
3d8d9f1d LP	36	#define SH_PFC_PIN_GROUP(n) \
	37	{ \
	38	.name = #n, \
	39	.pins = n##_pins, \
	40	.mux = n##_mux, \
	41	.nr_pins = ARRAY_SIZE(n##_pins), \
	42	}
	43
	44	struct sh_pfc_pin_group {
	45	const char *name;
	46	const unsigned int *pins;
	47	const unsigned int *mux;
	48	unsigned int nr_pins;
	49	};
	50
	51	#define SH_PFC_FUNCTION(n) \
	52	{ \
	53	.name = #n, \
	54	.groups = n##_groups, \
	55	.nr_groups = ARRAY_SIZE(n##_groups), \
	56	}
	57
	58	struct sh_pfc_function {
	59	const char *name;
	60	const char * const *groups;
	61	unsigned int nr_groups;
	62	};
	63
a373ed0a	64	struct pinmux_func {
533743dc	65	u16 enum_id;
a373ed0a LP	66	const char *name;
	67	};
	68
fae43399 MD	69	struct pinmux_cfg_reg {
fae43399 MD	70	unsigned long reg, reg_width, field_width;
533743dc	71	const u16 *enum_ids;
cd3c1bee	72	const unsigned long *var_field_width;
fae43399 MD	73	};
	74
	75	#define PINMUX_CFG_REG(name, r, r_width, f_width) \
	76	.reg = r, .reg_width = r_width, .field_width = f_width, \
533743dc	77	.enum_ids = (u16 [(r_width / f_width) * (1 << f_width)])
f78a26f5 MD	78
	79	#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
	80	.reg = r, .reg_width = r_width, \
f78a26f5	81	.var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \
533743dc	82	.enum_ids = (u16 [])
fae43399 MD	83
fae43399 MD	84	struct pinmux_data_reg {
51cb226b	85	unsigned long reg, reg_width;
533743dc	86	const u16 *enum_ids;
fae43399 MD	87	};
	88
	89	#define PINMUX_DATA_REG(name, r, r_width) \
	90	.reg = r, .reg_width = r_width, \
533743dc	91	.enum_ids = (u16 [r_width]) \
fae43399	92
ad2a8e7e MD	93	struct pinmux_irq {
ad2a8e7e MD	94	int irq;
c07f54f6	95	unsigned short *gpios;
ad2a8e7e MD	96	};
	97
	98	#define PINMUX_IRQ(irq_nr, ids...) \
c07f54f6	99	{ .irq = irq_nr, .gpios = (unsigned short []) { ids, 0 } } \
ad2a8e7e	100
fae43399	101	struct pinmux_range {
533743dc LP	102	u16 begin;
	103	u16 end;
	104	u16 force;
fae43399 MD	105	};
fae43399 MD	106
c58d9c1b LP	107	struct sh_pfc;
	108
	109	struct sh_pfc_soc_operations {
0c151062 LP	110	int (init)(struct sh_pfc pfc);
0c151062 LP	111	void (exit)(struct sh_pfc pfc);
c58d9c1b LP	112	unsigned int (get_bias)(struct sh_pfc pfc, unsigned int pin);
	113	void (set_bias)(struct sh_pfc pfc, unsigned int pin,
	114	unsigned int bias);
	115	};
	116
19bb7fe3	117	struct sh_pfc_soc_info {
cd3c1bee	118	const char *name;
c58d9c1b LP	119	const struct sh_pfc_soc_operations *ops;
c58d9c1b LP	120
fae43399	121	struct pinmux_range input;
fae43399	122	struct pinmux_range output;
fae43399 MD	123	struct pinmux_range function;
fae43399 MD	124
cd3c1bee	125	const struct sh_pfc_pin *pins;
caa5bac3	126	unsigned int nr_pins;
63d57383 LP	127	const struct pinmux_range *ranges;
63d57383 LP	128	unsigned int nr_ranges;
3d8d9f1d LP	129	const struct sh_pfc_pin_group *groups;
	130	unsigned int nr_groups;
	131	const struct sh_pfc_function *functions;
	132	unsigned int nr_functions;
	133
cd3c1bee	134	const struct pinmux_func *func_gpios;
a373ed0a	135	unsigned int nr_func_gpios;
d7a7ca57	136
cd3c1bee LP	137	const struct pinmux_cfg_reg *cfg_regs;
cd3c1bee LP	138	const struct pinmux_data_reg *data_regs;
fae43399	139
533743dc	140	const u16 *gpio_data;
fae43399 MD	141	unsigned int gpio_data_size;
fae43399 MD	142
cd3c1bee	143	const struct pinmux_irq *gpio_irq;
ad2a8e7e MD	144	unsigned int gpio_irq_size;
ad2a8e7e MD	145
e499ada8	146	unsigned long unlock_reg;
fae43399 MD	147	};
fae43399 MD	148
e3d93b46 LP	149	/* -----------------------------------------------------------------------------
	150	* Helper macros to create pin and port lists
	151	*/
	152
	153	/*
	154	* sh_pfc_soc_info gpio_data array macros
	155	*/
	156
	157	#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
	158
	159	#define PINMUX_IPSR_NOGP(ispr, fn) \
	160	PINMUX_DATA(fn##_MARK, FN_##fn)
	161	#define PINMUX_IPSR_DATA(ipsr, fn) \
	162	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
	163	#define PINMUX_IPSR_NOGM(ispr, fn, ms) \
	164	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms)
	165	#define PINMUX_IPSR_MSEL(ipsr, fn, ms) \
	166	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms)
	167	#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) \
	168	PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn)
	169
	170	/*
	171	* GP port style (32 ports banks)
	172	*/
	173
	174	#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
	175
	176	#define PORT_GP_32(bank, fn, sfx) \
	177	PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
	178	PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
	179	PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
	180	PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
	181	PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
	182	PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
	183	PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
	184	PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
	185	PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
	186	PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
	187	PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
	188	PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
	189	PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
	190	PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \
	191	PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \
	192	PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
	193
	194	#define PORT_GP_32_REV(bank, fn, sfx) \
	195	PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
	196	PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
	197	PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
	198	PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
	199	PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
	200	PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
	201	PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
	202	PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
	203	PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
	204	PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
	205	PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
	206	PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
	207	PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
	208	PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
	209	PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
	210	PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
	211
	212	/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
213	#define _GP_ALL(bank, pin, name, sfx) name##_##sfx
214	#define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str)
215
216	/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
217	#define _GP_GPIO(bank, pin, _name, sfx) \
218	[(bank * 32) + pin] = { \
219	.name = __stringify(_name), \
220	.enum_id = _name##_DATA, \
221	}
222	#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
223
224	/* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
225	#define _GP_DATA(bank, pin, name, sfx) PINMUX_DATA(name##_DATA, name##_FN)
226	#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
227
228	/*
229	* PORT style (linear pin space)
230	*/
231
972c3fb6 KM	232	#define PORT_1(fn, pfx, sfx) fn(pfx, sfx)
972c3fb6 KM	233
e3d93b46 LP	234	#define PORT_10(fn, pfx, sfx) \
	235	PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \
	236	PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \
	237	PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \
	238	PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \
972c3fb6 KM	239	PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx)
	240
	241	#define PORT_90(fn, pfx, sfx) \
e3d93b46 LP	242	PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \
	243	PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \
	244	PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx), \
	245	PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx), \
972c3fb6 KM	246	PORT_10(fn, pfx##9, sfx)
972c3fb6 KM	247
e3d93b46 LP	248	/* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
	249	#define _PORT_ALL(pfx, sfx) pfx##_##sfx
	250	#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
972c3fb6	251
e3d93b46	252	/* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
7cbb0e55 LP	253	#define PINMUX_GPIO(pin) \
	254	[GPIO_##pin] = { \
	255	.name = __stringify(name), \
	256	.enum_id = pin##_DATA, \
e3d93b46 LP	257	}
e3d93b46 LP	258
df020272 LP	259	/* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
	260	#define SH_PFC_PIN_CFG(pin, cfgs) \
	261	{ \
	262	.name = __stringify(PORT##pin), \
	263	.enum_id = PORT##pin##_DATA, \
	264	.configs = cfgs, \
	265	}
	266
e3d93b46 LP	267	/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
	268	* PORT_name_OUT, PORT_name_IN marks
	269	*/
	270	#define _PORT_DATA(pfx, sfx) \
	271	PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
	272	PORT##pfx##_OUT, PORT##pfx##_IN)
	273	#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
	274
	275	/* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
	276	#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
	277	[gpio - (base)] = { \
	278	.name = __stringify(gpio), \
	279	.enum_id = data_or_mark, \
	280	}
	281	#define GPIO_FN(str) \
	282	PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
bd8d0cba	283
e3d93b46 LP	284	/*
	285	* PORTnCR macro
	286	*/
9b49139b KM	287	#define _PCRH(in, in_pd, in_pu, out) \
	288	0, (out), (in), 0, \
	289	0, 0, 0, 0, \
	290	0, 0, (in_pd), 0, \
	291	0, 0, (in_pu), 0
	292
	293	#define PORTCR(nr, reg) \
	294	{ \
	295	PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
	296	_PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \
	297	PORT##nr##_IN_PU, PORT##nr##_OUT), \
	298	PORT##nr##_FN0, PORT##nr##_FN1, \
	299	PORT##nr##_FN2, PORT##nr##_FN3, \
	300	PORT##nr##_FN4, PORT##nr##_FN5, \
	301	PORT##nr##_FN6, PORT##nr##_FN7 } \
	302	}
bd8d0cba	303
fae43399	304	#endif /* __SH_PFC_H */