projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
x86, powercap, rapl: Reorder CPU detection table
[deliverable/linux.git] / drivers / powercap / intel_rapl.c
CommitLineData
2d281d81
JP		 1/*
2 * Intel Running Average Power Limit (RAPL) Driver
3 * Copyright (c) 2013, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.
16 *
17 */
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/list.h>
23#include <linux/types.h>
24#include <linux/device.h>
25#include <linux/slab.h>
26#include <linux/log2.h>
27#include <linux/bitmap.h>
28#include <linux/delay.h>
29#include <linux/sysfs.h>
30#include <linux/cpu.h>
31#include <linux/powercap.h>
3c2c0845 32#include <asm/iosf_mbi.h>
2d281d81
JP		 33
34#include <asm/processor.h>
35#include <asm/cpu_device_id.h>
62d16733 36#include <asm/intel-family.h>
2d281d81 37
3521ba1c
SP		 38/* Local defines */
39#define MSR_PLATFORM_POWER_LIMIT 0x0000065C
40
2d281d81
JP		 41/* bitmasks for RAPL MSRs, used by primitive access functions */
42#define ENERGY_STATUS_MASK 0xffffffff
43
44#define POWER_LIMIT1_MASK 0x7FFF
45#define POWER_LIMIT1_ENABLE BIT(15)
46#define POWER_LIMIT1_CLAMP BIT(16)
47
48#define POWER_LIMIT2_MASK (0x7FFFULL<<32)
49#define POWER_LIMIT2_ENABLE BIT_ULL(47)
50#define POWER_LIMIT2_CLAMP BIT_ULL(48)
51#define POWER_PACKAGE_LOCK BIT_ULL(63)
52#define POWER_PP_LOCK BIT(31)
53
54#define TIME_WINDOW1_MASK (0x7FULL<<17)
55#define TIME_WINDOW2_MASK (0x7FULL<<49)
56
57#define POWER_UNIT_OFFSET 0
58#define POWER_UNIT_MASK 0x0F
59
60#define ENERGY_UNIT_OFFSET 0x08
61#define ENERGY_UNIT_MASK 0x1F00
62
63#define TIME_UNIT_OFFSET 0x10
64#define TIME_UNIT_MASK 0xF0000
65
66#define POWER_INFO_MAX_MASK (0x7fffULL<<32)
67#define POWER_INFO_MIN_MASK (0x7fffULL<<16)
68#define POWER_INFO_MAX_TIME_WIN_MASK (0x3fULL<<48)
69#define POWER_INFO_THERMAL_SPEC_MASK 0x7fff
70
71#define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff
72#define PP_POLICY_MASK 0x1F
73
74/* Non HW constants */
75#define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */
76#define RAPL_PRIMITIVE_DUMMY BIT(2)
77
2d281d81
JP		 78#define TIME_WINDOW_MAX_MSEC 40000
79#define TIME_WINDOW_MIN_MSEC 250
d474a4d3 80#define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit */
2d281d81
JP		 81enum unit_type {
82 ARBITRARY_UNIT, /* no translation */
83 POWER_UNIT,
84 ENERGY_UNIT,
85 TIME_UNIT,
86};
87
88enum rapl_domain_type {
89 RAPL_DOMAIN_PACKAGE, /* entire package/socket */
90 RAPL_DOMAIN_PP0, /* core power plane */
91 RAPL_DOMAIN_PP1, /* graphics uncore */
92 RAPL_DOMAIN_DRAM,/* DRAM control_type */
3521ba1c 93 RAPL_DOMAIN_PLATFORM, /* PSys control_type */
2d281d81
JP		 94 RAPL_DOMAIN_MAX,
95};
96
97enum rapl_domain_msr_id {
98 RAPL_DOMAIN_MSR_LIMIT,
99 RAPL_DOMAIN_MSR_STATUS,
100 RAPL_DOMAIN_MSR_PERF,
101 RAPL_DOMAIN_MSR_POLICY,
102 RAPL_DOMAIN_MSR_INFO,
103 RAPL_DOMAIN_MSR_MAX,
104};
105
106/* per domain data, some are optional */
107enum rapl_primitives {
108 ENERGY_COUNTER,
109 POWER_LIMIT1,
110 POWER_LIMIT2,
111 FW_LOCK,
112
113 PL1_ENABLE, /* power limit 1, aka long term */
114 PL1_CLAMP, /* allow frequency to go below OS request */
115 PL2_ENABLE, /* power limit 2, aka short term, instantaneous */
116 PL2_CLAMP,
117
118 TIME_WINDOW1, /* long term */
119 TIME_WINDOW2, /* short term */
120 THERMAL_SPEC_POWER,
121 MAX_POWER,
122
123 MIN_POWER,
124 MAX_TIME_WINDOW,
125 THROTTLED_TIME,
126 PRIORITY_LEVEL,
127
128 /* below are not raw primitive data */
129 AVERAGE_POWER,
130 NR_RAPL_PRIMITIVES,
131};
132
133#define NR_RAW_PRIMITIVES (NR_RAPL_PRIMITIVES - 2)
134
135/* Can be expanded to include events, etc.*/
136struct rapl_domain_data {
137 u64 primitives[NR_RAPL_PRIMITIVES];
138 unsigned long timestamp;
139};
140
f14a1396
JP		 141struct msrl_action {
142 u32 msr_no;
143 u64 clear_mask;
144 u64 set_mask;
145 int err;
146};
2d281d81
JP		 147
148#define DOMAIN_STATE_INACTIVE BIT(0)
149#define DOMAIN_STATE_POWER_LIMIT_SET BIT(1)
150#define DOMAIN_STATE_BIOS_LOCKED BIT(2)
151
152#define NR_POWER_LIMITS (2)
153struct rapl_power_limit {
154 struct powercap_zone_constraint *constraint;
155 int prim_id; /* primitive ID used to enable */
156 struct rapl_domain *domain;
157 const char *name;
158};
159
160static const char pl1_name[] = "long_term";
161static const char pl2_name[] = "short_term";
162
309557f5 163struct rapl_package;
2d281d81
JP		 164struct rapl_domain {
165 const char *name;
166 enum rapl_domain_type id;
167 int msrs[RAPL_DOMAIN_MSR_MAX];
168 struct powercap_zone power_zone;
169 struct rapl_domain_data rdd;
170 struct rapl_power_limit rpl[NR_POWER_LIMITS];
171 u64 attr_map; /* track capabilities */
172 unsigned int state;
d474a4d3 173 unsigned int domain_energy_unit;
309557f5 174 struct rapl_package *rp;
2d281d81
JP		 175};
176#define power_zone_to_rapl_domain(_zone) \
177 container_of(_zone, struct rapl_domain, power_zone)
178
179
180/* Each physical package contains multiple domains, these are the common
181 * data across RAPL domains within a package.
182 */
183struct rapl_package {
184 unsigned int id; /* physical package/socket id */
185 unsigned int nr_domains;
186 unsigned long domain_map; /* bit map of active domains */
3c2c0845
JP		 187 unsigned int power_unit;
188 unsigned int energy_unit;
189 unsigned int time_unit;
2d281d81
JP		 190 struct rapl_domain *domains; /* array of domains, sized at runtime */
191 struct powercap_zone *power_zone; /* keep track of parent zone */
192 int nr_cpus; /* active cpus on the package, topology info is lost during
193 * cpu hotplug. so we have to track ourselves.
194 */
195 unsigned long power_limit_irq; /* keep track of package power limit
196 * notify interrupt enable status.
197 */
198 struct list_head plist;
323ee64a 199 int lead_cpu; /* one active cpu per package for access */
2d281d81 200};
087e9cba
JP		 201
202struct rapl_defaults {
51b63409 203 u8 floor_freq_reg_addr;
087e9cba
JP		 204 int (*check_unit)(struct rapl_package *rp, int cpu);
205 void (*set_floor_freq)(struct rapl_domain *rd, bool mode);
206 u64 (*compute_time_window)(struct rapl_package *rp, u64 val,
207 bool to_raw);
d474a4d3 208 unsigned int dram_domain_energy_unit;
087e9cba
JP		 209};
210static struct rapl_defaults *rapl_defaults;
211
3c2c0845 212/* Sideband MBI registers */
51b63409
AT		 213#define IOSF_CPU_POWER_BUDGET_CTL_BYT (0x2)
214#define IOSF_CPU_POWER_BUDGET_CTL_TNG (0xdf)
3c2c0845 215
2d281d81
JP		 216#define PACKAGE_PLN_INT_SAVED BIT(0)
217#define MAX_PRIM_NAME (32)
218
219/* per domain data. used to describe individual knobs such that access function
220 * can be consolidated into one instead of many inline functions.
221 */
222struct rapl_primitive_info {
223 const char *name;
224 u64 mask;
225 int shift;
226 enum rapl_domain_msr_id id;
227 enum unit_type unit;
228 u32 flag;
229};
230
231#define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \
232 .name = #p, \
233 .mask = m, \
234 .shift = s, \
235 .id = i, \
236 .unit = u, \
237 .flag = f \
238 }
239
240static void rapl_init_domains(struct rapl_package *rp);
241static int rapl_read_data_raw(struct rapl_domain *rd,
242 enum rapl_primitives prim,
243 bool xlate, u64 *data);
244static int rapl_write_data_raw(struct rapl_domain *rd,
245 enum rapl_primitives prim,
246 unsigned long long value);
309557f5 247static u64 rapl_unit_xlate(struct rapl_domain *rd,
d474a4d3 248 enum unit_type type, u64 value,
2d281d81 249 int to_raw);
309557f5 250static void package_power_limit_irq_save(struct rapl_package *rp);
2d281d81
JP		 251
252static LIST_HEAD(rapl_packages); /* guarded by CPU hotplug lock */
253
254static const char * const rapl_domain_names[] = {
255 "package",
256 "core",
257 "uncore",
258 "dram",
3521ba1c 259 "psys",
2d281d81
JP		 260};
261
262static struct powercap_control_type *control_type; /* PowerCap Controller */
3521ba1c 263static struct rapl_domain *platform_rapl_domain; /* Platform (PSys) domain */
2d281d81
JP		 264
265/* caller to ensure CPU hotplug lock is held */
266static struct rapl_package *find_package_by_id(int id)
267{
268 struct rapl_package *rp;
269
270 list_for_each_entry(rp, &rapl_packages, plist) {
271 if (rp->id == id)
272 return rp;
273 }
274
275 return NULL;
276}
277
2d281d81
JP		 278/* caller must hold cpu hotplug lock */
279static void rapl_cleanup_data(void)
280{
281 struct rapl_package *p, *tmp;
282
283 list_for_each_entry_safe(p, tmp, &rapl_packages, plist) {
284 kfree(p->domains);
285 list_del(&p->plist);
286 kfree(p);
287 }
288}
289
290static int get_energy_counter(struct powercap_zone *power_zone, u64 *energy_raw)
291{
292 struct rapl_domain *rd;
293 u64 energy_now;
294
295 /* prevent CPU hotplug, make sure the RAPL domain does not go
296 * away while reading the counter.
297 */
298 get_online_cpus();
299 rd = power_zone_to_rapl_domain(power_zone);
300
301 if (!rapl_read_data_raw(rd, ENERGY_COUNTER, true, &energy_now)) {
302 *energy_raw = energy_now;
303 put_online_cpus();
304
305 return 0;
306 }
307 put_online_cpus();
308
309 return -EIO;
310}
311
312static int get_max_energy_counter(struct powercap_zone *pcd_dev, u64 *energy)
313{
d474a4d3
JP		 314 struct rapl_domain *rd = power_zone_to_rapl_domain(pcd_dev);
315
309557f5 316 *energy = rapl_unit_xlate(rd, ENERGY_UNIT, ENERGY_STATUS_MASK, 0);
2d281d81
JP		 317 return 0;
318}
319
320static int release_zone(struct powercap_zone *power_zone)
321{
322 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
309557f5 323 struct rapl_package *rp = rd->rp;
2d281d81
JP		 324
325 /* package zone is the last zone of a package, we can free
326 * memory here since all children has been unregistered.
327 */
328 if (rd->id == RAPL_DOMAIN_PACKAGE) {
2d281d81
JP		 329 kfree(rd);
330 rp->domains = NULL;
331 }
332
333 return 0;
334
335}
336
337static int find_nr_power_limit(struct rapl_domain *rd)
338{
339 int i;
340
341 for (i = 0; i < NR_POWER_LIMITS; i++) {
342 if (rd->rpl[i].name == NULL)
343 break;
344 }
345
346 return i;
347}
348
349static int set_domain_enable(struct powercap_zone *power_zone, bool mode)
350{
351 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
2d281d81
JP		 352
353 if (rd->state & DOMAIN_STATE_BIOS_LOCKED)
354 return -EACCES;
3c2c0845 355
2d281d81 356 get_online_cpus();
2d281d81 357 rapl_write_data_raw(rd, PL1_ENABLE, mode);
51b63409
AT		 358 if (rapl_defaults->set_floor_freq)
359 rapl_defaults->set_floor_freq(rd, mode);
2d281d81
JP		 360 put_online_cpus();
361
362 return 0;
363}
364
365static int get_domain_enable(struct powercap_zone *power_zone, bool *mode)
366{
367 struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
368 u64 val;
369
370 if (rd->state & DOMAIN_STATE_BIOS_LOCKED) {
371 *mode = false;
372 return 0;
373 }
374 get_online_cpus();
375 if (rapl_read_data_raw(rd, PL1_ENABLE, true, &val)) {
376 put_online_cpus();
377 return -EIO;
378 }
379 *mode = val;
380 put_online_cpus();
381
382 return 0;
383}
384
385/* per RAPL domain ops, in the order of rapl_domain_type */
600c395b 386static const struct powercap_zone_ops zone_ops[] = {
2d281d81
JP		 387 /* RAPL_DOMAIN_PACKAGE */
388 {
389 .get_energy_uj = get_energy_counter,
390 .get_max_energy_range_uj = get_max_energy_counter,
391 .release = release_zone,
392 .set_enable = set_domain_enable,
393 .get_enable = get_domain_enable,
394 },
395 /* RAPL_DOMAIN_PP0 */
396 {
397 .get_energy_uj = get_energy_counter,
398 .get_max_energy_range_uj = get_max_energy_counter,
399 .release = release_zone,
400 .set_enable = set_domain_enable,
401 .get_enable = get_domain_enable,
402 },
403 /* RAPL_DOMAIN_PP1 */
404 {
405 .get_energy_uj = get_energy_counter,
406 .get_max_energy_range_uj = get_max_energy_counter,
407 .release = release_zone,
408 .set_enable = set_domain_enable,
409 .get_enable = get_domain_enable,
410 },
411 /* RAPL_DOMAIN_DRAM */
412 {
413 .get_energy_uj = get_energy_counter,
414 .get_max_energy_range_uj = get_max_energy_counter,
415 .release = release_zone,
416 .set_enable = set_domain_enable,
417 .get_enable = get_domain_enable,
418 },
3521ba1c
SP		 419 /* RAPL_DOMAIN_PLATFORM */
420 {
421 .get_energy_uj = get_energy_counter,
422 .get_max_energy_range_uj = get_max_energy_counter,
423 .release = release_zone,
424 .set_enable = set_domain_enable,
425 .get_enable = get_domain_enable,
426 },
2d281d81
JP		 427};
428
429static int set_power_limit(struct powercap_zone *power_zone, int id,
430 u64 power_limit)
431{
432 struct rapl_domain *rd;
433 struct rapl_package *rp;
434 int ret = 0;
435
436 get_online_cpus();
437 rd = power_zone_to_rapl_domain(power_zone);
309557f5 438 rp = rd->rp;
2d281d81
JP		 439
440 if (rd->state & DOMAIN_STATE_BIOS_LOCKED) {
441 dev_warn(&power_zone->dev, "%s locked by BIOS, monitoring only\n",
442 rd->name);
443 ret = -EACCES;
444 goto set_exit;
445 }
446
447 switch (rd->rpl[id].prim_id) {
448 case PL1_ENABLE:
449 rapl_write_data_raw(rd, POWER_LIMIT1, power_limit);
450 break;
451 case PL2_ENABLE:
452 rapl_write_data_raw(rd, POWER_LIMIT2, power_limit);
453 break;
454 default:
455 ret = -EINVAL;
456 }
457 if (!ret)
309557f5 458 package_power_limit_irq_save(rp);
2d281d81
JP		 459set_exit:
460 put_online_cpus();
461 return ret;
462}
463
464static int get_current_power_limit(struct powercap_zone *power_zone, int id,
465 u64 *data)
466{
467 struct rapl_domain *rd;
468 u64 val;
469 int prim;
470 int ret = 0;
471
472 get_online_cpus();
473 rd = power_zone_to_rapl_domain(power_zone);
474 switch (rd->rpl[id].prim_id) {
475 case PL1_ENABLE:
476 prim = POWER_LIMIT1;
477 break;
478 case PL2_ENABLE:
479 prim = POWER_LIMIT2;
480 break;
481 default:
482 put_online_cpus();
483 return -EINVAL;
484 }
485 if (rapl_read_data_raw(rd, prim, true, &val))
486 ret = -EIO;
487 else
488 *data = val;
489
490 put_online_cpus();
491
492 return ret;
493}
494
495static int set_time_window(struct powercap_zone *power_zone, int id,
496 u64 window)
497{
498 struct rapl_domain *rd;
499 int ret = 0;
500
501 get_online_cpus();
502 rd = power_zone_to_rapl_domain(power_zone);
503 switch (rd->rpl[id].prim_id) {
504 case PL1_ENABLE:
505 rapl_write_data_raw(rd, TIME_WINDOW1, window);
506 break;
507 case PL2_ENABLE:
508 rapl_write_data_raw(rd, TIME_WINDOW2, window);
509 break;
510 default:
511 ret = -EINVAL;
512 }
513 put_online_cpus();
514 return ret;
515}
516
517static int get_time_window(struct powercap_zone *power_zone, int id, u64 *data)
518{
519 struct rapl_domain *rd;
520 u64 val;
521 int ret = 0;
522
523 get_online_cpus();
524 rd = power_zone_to_rapl_domain(power_zone);
525 switch (rd->rpl[id].prim_id) {
526 case PL1_ENABLE:
527 ret = rapl_read_data_raw(rd, TIME_WINDOW1, true, &val);
528 break;
529 case PL2_ENABLE:
530 ret = rapl_read_data_raw(rd, TIME_WINDOW2, true, &val);
531 break;
532 default:
533 put_online_cpus();
534 return -EINVAL;
535 }
536 if (!ret)
537 *data = val;
538 put_online_cpus();
539
540 return ret;
541}
542
543static const char *get_constraint_name(struct powercap_zone *power_zone, int id)
544{
545 struct rapl_power_limit *rpl;
546 struct rapl_domain *rd;
547
548 rd = power_zone_to_rapl_domain(power_zone);
549 rpl = (struct rapl_power_limit *) &rd->rpl[id];
550
551 return rpl->name;
552}
553
554
555static int get_max_power(struct powercap_zone *power_zone, int id,
556 u64 *data)
557{
558 struct rapl_domain *rd;
559 u64 val;
560 int prim;
561 int ret = 0;
562
563 get_online_cpus();
564 rd = power_zone_to_rapl_domain(power_zone);
565 switch (rd->rpl[id].prim_id) {
566 case PL1_ENABLE:
567 prim = THERMAL_SPEC_POWER;
568 break;
569 case PL2_ENABLE:
570 prim = MAX_POWER;
571 break;
572 default:
573 put_online_cpus();
574 return -EINVAL;
575 }
576 if (rapl_read_data_raw(rd, prim, true, &val))
577 ret = -EIO;
578 else
579 *data = val;
580
581 put_online_cpus();
582
583 return ret;
584}
585
600c395b 586static const struct powercap_zone_constraint_ops constraint_ops = {
2d281d81
JP		 587 .set_power_limit_uw = set_power_limit,
588 .get_power_limit_uw = get_current_power_limit,
589 .set_time_window_us = set_time_window,
590 .get_time_window_us = get_time_window,
591 .get_max_power_uw = get_max_power,
592 .get_name = get_constraint_name,
593};
594
595/* called after domain detection and package level data are set */
596static void rapl_init_domains(struct rapl_package *rp)
597{
598 int i;
599 struct rapl_domain *rd = rp->domains;
600
601 for (i = 0; i < RAPL_DOMAIN_MAX; i++) {
602 unsigned int mask = rp->domain_map & (1 << i);
603 switch (mask) {
604 case BIT(RAPL_DOMAIN_PACKAGE):
605 rd->name = rapl_domain_names[RAPL_DOMAIN_PACKAGE];
606 rd->id = RAPL_DOMAIN_PACKAGE;
607 rd->msrs[0] = MSR_PKG_POWER_LIMIT;
608 rd->msrs[1] = MSR_PKG_ENERGY_STATUS;
609 rd->msrs[2] = MSR_PKG_PERF_STATUS;
610 rd->msrs[3] = 0;
611 rd->msrs[4] = MSR_PKG_POWER_INFO;
612 rd->rpl[0].prim_id = PL1_ENABLE;
613 rd->rpl[0].name = pl1_name;
614 rd->rpl[1].prim_id = PL2_ENABLE;
615 rd->rpl[1].name = pl2_name;
616 break;
617 case BIT(RAPL_DOMAIN_PP0):
618 rd->name = rapl_domain_names[RAPL_DOMAIN_PP0];
619 rd->id = RAPL_DOMAIN_PP0;
620 rd->msrs[0] = MSR_PP0_POWER_LIMIT;
621 rd->msrs[1] = MSR_PP0_ENERGY_STATUS;
622 rd->msrs[2] = 0;
623 rd->msrs[3] = MSR_PP0_POLICY;
624 rd->msrs[4] = 0;
625 rd->rpl[0].prim_id = PL1_ENABLE;
626 rd->rpl[0].name = pl1_name;
627 break;
628 case BIT(RAPL_DOMAIN_PP1):
629 rd->name = rapl_domain_names[RAPL_DOMAIN_PP1];
630 rd->id = RAPL_DOMAIN_PP1;
631 rd->msrs[0] = MSR_PP1_POWER_LIMIT;
632 rd->msrs[1] = MSR_PP1_ENERGY_STATUS;
633 rd->msrs[2] = 0;
634 rd->msrs[3] = MSR_PP1_POLICY;
635 rd->msrs[4] = 0;
636 rd->rpl[0].prim_id = PL1_ENABLE;
637 rd->rpl[0].name = pl1_name;
638 break;
639 case BIT(RAPL_DOMAIN_DRAM):
640 rd->name = rapl_domain_names[RAPL_DOMAIN_DRAM];
641 rd->id = RAPL_DOMAIN_DRAM;
642 rd->msrs[0] = MSR_DRAM_POWER_LIMIT;
643 rd->msrs[1] = MSR_DRAM_ENERGY_STATUS;
644 rd->msrs[2] = MSR_DRAM_PERF_STATUS;
645 rd->msrs[3] = 0;
646 rd->msrs[4] = MSR_DRAM_POWER_INFO;
647 rd->rpl[0].prim_id = PL1_ENABLE;
648 rd->rpl[0].name = pl1_name;
d474a4d3
JP		 649 rd->domain_energy_unit =
650 rapl_defaults->dram_domain_energy_unit;
651 if (rd->domain_energy_unit)
652 pr_info("DRAM domain energy unit %dpj\n",
653 rd->domain_energy_unit);
2d281d81
JP		 654 break;
655 }
656 if (mask) {
309557f5 657 rd->rp = rp;
2d281d81
JP		 658 rd++;
659 }
660 }
661}
662
309557f5
JP		 663static u64 rapl_unit_xlate(struct rapl_domain *rd, enum unit_type type,
664 u64 value, int to_raw)
2d281d81 665{
3c2c0845 666 u64 units = 1;
309557f5 667 struct rapl_package *rp = rd->rp;
d474a4d3 668 u64 scale = 1;
2d281d81 669
2d281d81
JP		 670 switch (type) {
671 case POWER_UNIT:
3c2c0845 672 units = rp->power_unit;
2d281d81
JP		 673 break;
674 case ENERGY_UNIT:
d474a4d3
JP		 675 scale = ENERGY_UNIT_SCALE;
676 /* per domain unit takes precedence */
677 if (rd && rd->domain_energy_unit)
678 units = rd->domain_energy_unit;
679 else
680 units = rp->energy_unit;
2d281d81
JP		 681 break;
682 case TIME_UNIT:
3c2c0845 683 return rapl_defaults->compute_time_window(rp, value, to_raw);
2d281d81
JP		 684 case ARBITRARY_UNIT:
685 default:
686 return value;
687 };
688
689 if (to_raw)
d474a4d3 690 return div64_u64(value, units) * scale;
3c2c0845
JP		 691
692 value *= units;
693
d474a4d3 694 return div64_u64(value, scale);
2d281d81
JP		 695}
696
697/* in the order of enum rapl_primitives */
698static struct rapl_primitive_info rpi[] = {
699 /* name, mask, shift, msr index, unit divisor */
700 PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0,
701 RAPL_DOMAIN_MSR_STATUS, ENERGY_UNIT, 0),
702 PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0,
703 RAPL_DOMAIN_MSR_LIMIT, POWER_UNIT, 0),
704 PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32,
705 RAPL_DOMAIN_MSR_LIMIT, POWER_UNIT, 0),
706 PRIMITIVE_INFO_INIT(FW_LOCK, POWER_PP_LOCK, 31,
707 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
708 PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15,
709 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
710 PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16,
711 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
712 PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47,
713 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
714 PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48,
715 RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
716 PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17,
717 RAPL_DOMAIN_MSR_LIMIT, TIME_UNIT, 0),
718 PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49,
719 RAPL_DOMAIN_MSR_LIMIT, TIME_UNIT, 0),
720 PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, POWER_INFO_THERMAL_SPEC_MASK,
721 0, RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0),
722 PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32,
723 RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0),
724 PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16,
725 RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0),
726 PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, POWER_INFO_MAX_TIME_WIN_MASK, 48,
727 RAPL_DOMAIN_MSR_INFO, TIME_UNIT, 0),
728 PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0,
729 RAPL_DOMAIN_MSR_PERF, TIME_UNIT, 0),
730 PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0,
731 RAPL_DOMAIN_MSR_POLICY, ARBITRARY_UNIT, 0),
732 /* non-hardware */
733 PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UNIT,
734 RAPL_PRIMITIVE_DERIVED),
735 {NULL, 0, 0, 0},
736};
737
738/* Read primitive data based on its related struct rapl_primitive_info.
739 * if xlate flag is set, return translated data based on data units, i.e.
740 * time, energy, and power.
741 * RAPL MSRs are non-architectual and are laid out not consistently across
742 * domains. Here we use primitive info to allow writing consolidated access
743 * functions.
744 * For a given primitive, it is processed by MSR mask and shift. Unit conversion
745 * is pre-assigned based on RAPL unit MSRs read at init time.
746 * 63-------------------------- 31--------------------------- 0
747 * | xxxxx (mask) |
748 * | |<- shift ----------------|
749 * 63-------------------------- 31--------------------------- 0
750 */
751static int rapl_read_data_raw(struct rapl_domain *rd,
752 enum rapl_primitives prim,
753 bool xlate, u64 *data)
754{
755 u64 value, final;
756 u32 msr;
757 struct rapl_primitive_info *rp = &rpi[prim];
758 int cpu;
759
760 if (!rp->name || rp->flag & RAPL_PRIMITIVE_DUMMY)
761 return -EINVAL;
762
763 msr = rd->msrs[rp->id];
764 if (!msr)
765 return -EINVAL;
323ee64a
JP		 766
767 cpu = rd->rp->lead_cpu;
2d281d81
JP		 768
769 /* special-case package domain, which uses a different bit*/
770 if (prim == FW_LOCK && rd->id == RAPL_DOMAIN_PACKAGE) {
771 rp->mask = POWER_PACKAGE_LOCK;
772 rp->shift = 63;
773 }
774 /* non-hardware data are collected by the polling thread */
775 if (rp->flag & RAPL_PRIMITIVE_DERIVED) {
776 *data = rd->rdd.primitives[prim];
777 return 0;
778 }
779
780 if (rdmsrl_safe_on_cpu(cpu, msr, &value)) {
781 pr_debug("failed to read msr 0x%x on cpu %d\n", msr, cpu);
782 return -EIO;
783 }
784
785 final = value & rp->mask;
786 final = final >> rp->shift;
787 if (xlate)
309557f5 788 *data = rapl_unit_xlate(rd, rp->unit, final, 0);
2d281d81
JP		 789 else
790 *data = final;
791
792 return 0;
793}
794
f14a1396
JP		 795
796static int msrl_update_safe(u32 msr_no, u64 clear_mask, u64 set_mask)
797{
798 int err;
799 u64 val;
800
801 err = rdmsrl_safe(msr_no, &val);
802 if (err)
803 goto out;
804
805 val &= ~clear_mask;
806 val |= set_mask;
807
808 err = wrmsrl_safe(msr_no, val);
809
810out:
811 return err;
812}
813
814static void msrl_update_func(void *info)
815{
816 struct msrl_action *ma = info;
817
818 ma->err = msrl_update_safe(ma->msr_no, ma->clear_mask, ma->set_mask);
819}
820
2d281d81
JP		 821/* Similar use of primitive info in the read counterpart */
822static int rapl_write_data_raw(struct rapl_domain *rd,
823 enum rapl_primitives prim,
824 unsigned long long value)
825{
2d281d81
JP		 826 struct rapl_primitive_info *rp = &rpi[prim];
827 int cpu;
f14a1396
JP		 828 u64 bits;
829 struct msrl_action ma;
830 int ret;
2d281d81 831
323ee64a 832 cpu = rd->rp->lead_cpu;
309557f5 833 bits = rapl_unit_xlate(rd, rp->unit, value, 1);
f14a1396
JP		 834 bits |= bits << rp->shift;
835 memset(&ma, 0, sizeof(ma));
836
837 ma.msr_no = rd->msrs[rp->id];
838 ma.clear_mask = rp->mask;
839 ma.set_mask = bits;
840
841 ret = smp_call_function_single(cpu, msrl_update_func, &ma, 1);
842 if (ret)
843 WARN_ON_ONCE(ret);
844 else
845 ret = ma.err;
846
847 return ret;
2d281d81
JP		 848}
849
3c2c0845
JP		 850/*
851 * Raw RAPL data stored in MSRs are in certain scales. We need to
852 * convert them into standard units based on the units reported in
853 * the RAPL unit MSRs. This is specific to CPUs as the method to
854 * calculate units differ on different CPUs.
855 * We convert the units to below format based on CPUs.
856 * i.e.
d474a4d3 857 * energy unit: picoJoules : Represented in picoJoules by default
3c2c0845
JP		 858 * power unit : microWatts : Represented in milliWatts by default
859 * time unit : microseconds: Represented in seconds by default
860 */
861static int rapl_check_unit_core(struct rapl_package *rp, int cpu)
2d281d81
JP		 862{
863 u64 msr_val;
864 u32 value;
865
866 if (rdmsrl_safe_on_cpu(cpu, MSR_RAPL_POWER_UNIT, &msr_val)) {
867 pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n",
868 MSR_RAPL_POWER_UNIT, cpu);
869 return -ENODEV;
870 }
871
2d281d81 872 value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
d474a4d3 873 rp->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value);
2d281d81
JP		 874
875 value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
3c2c0845 876 rp->power_unit = 1000000 / (1 << value);
2d281d81
JP		 877
878 value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
3c2c0845 879 rp->time_unit = 1000000 / (1 << value);
2d281d81 880
d474a4d3 881 pr_debug("Core CPU package %d energy=%dpJ, time=%dus, power=%duW\n",
3c2c0845 882 rp->id, rp->energy_unit, rp->time_unit, rp->power_unit);
2d281d81
JP		 883
884 return 0;
885}
886
3c2c0845
JP		 887static int rapl_check_unit_atom(struct rapl_package *rp, int cpu)
888{
889 u64 msr_val;
890 u32 value;
891
892 if (rdmsrl_safe_on_cpu(cpu, MSR_RAPL_POWER_UNIT, &msr_val)) {
893 pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n",
894 MSR_RAPL_POWER_UNIT, cpu);
895 return -ENODEV;
896 }
897 value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
d474a4d3 898 rp->energy_unit = ENERGY_UNIT_SCALE * 1 << value;
3c2c0845
JP		 899
900 value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
901 rp->power_unit = (1 << value) * 1000;
902
903 value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
904 rp->time_unit = 1000000 / (1 << value);
905
d474a4d3 906 pr_debug("Atom package %d energy=%dpJ, time=%dus, power=%duW\n",
3c2c0845
JP		 907 rp->id, rp->energy_unit, rp->time_unit, rp->power_unit);
908
909 return 0;
910}
911
f14a1396
JP		 912static void power_limit_irq_save_cpu(void *info)
913{
914 u32 l, h = 0;
915 struct rapl_package *rp = (struct rapl_package *)info;
916
917 /* save the state of PLN irq mask bit before disabling it */
918 rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h);
919 if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED)) {
920 rp->power_limit_irq = l & PACKAGE_THERM_INT_PLN_ENABLE;
921 rp->power_limit_irq |= PACKAGE_PLN_INT_SAVED;
922 }
923 l &= ~PACKAGE_THERM_INT_PLN_ENABLE;
924 wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
925}
926
3c2c0845 927
2d281d81
JP		 928/* REVISIT:
929 * When package power limit is set artificially low by RAPL, LVT
930 * thermal interrupt for package power limit should be ignored
931 * since we are not really exceeding the real limit. The intention
932 * is to avoid excessive interrupts while we are trying to save power.
933 * A useful feature might be routing the package_power_limit interrupt
934 * to userspace via eventfd. once we have a usecase, this is simple
935 * to do by adding an atomic notifier.
936 */
937
309557f5 938static void package_power_limit_irq_save(struct rapl_package *rp)
2d281d81 939{
f14a1396
JP		 940 if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN))
941 return;
942
323ee64a 943 smp_call_function_single(rp->lead_cpu, power_limit_irq_save_cpu, rp, 1);
f14a1396
JP		 944}
945
946static void power_limit_irq_restore_cpu(void *info)
947{
948 u32 l, h = 0;
949 struct rapl_package *rp = (struct rapl_package *)info;
950
951 rdmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h);
952
953 if (rp->power_limit_irq & PACKAGE_THERM_INT_PLN_ENABLE)
954 l |= PACKAGE_THERM_INT_PLN_ENABLE;
955 else
956 l &= ~PACKAGE_THERM_INT_PLN_ENABLE;
957
958 wrmsr_safe(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
2d281d81
JP		 959}
960
961/* restore per package power limit interrupt enable state */
309557f5 962static void package_power_limit_irq_restore(struct rapl_package *rp)
2d281d81 963{
2d281d81
JP		 964 if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN))
965 return;
966
2d281d81
JP		 967 /* irq enable state not saved, nothing to restore */
968 if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED))
969 return;
2d281d81 970
323ee64a 971 smp_call_function_single(rp->lead_cpu, power_limit_irq_restore_cpu, rp, 1);
2d281d81
JP		 972}
973
3c2c0845
JP		 974static void set_floor_freq_default(struct rapl_domain *rd, bool mode)
975{
976 int nr_powerlimit = find_nr_power_limit(rd);
977
978 /* always enable clamp such that p-state can go below OS requested
979 * range. power capping priority over guranteed frequency.
980 */
981 rapl_write_data_raw(rd, PL1_CLAMP, mode);
982
983 /* some domains have pl2 */
984 if (nr_powerlimit > 1) {
985 rapl_write_data_raw(rd, PL2_ENABLE, mode);
986 rapl_write_data_raw(rd, PL2_CLAMP, mode);
987 }
988}
989
990static void set_floor_freq_atom(struct rapl_domain *rd, bool enable)
991{
992 static u32 power_ctrl_orig_val;
993 u32 mdata;
994
51b63409
AT		 995 if (!rapl_defaults->floor_freq_reg_addr) {
996 pr_err("Invalid floor frequency config register\n");
997 return;
998 }
999
3c2c0845 1000 if (!power_ctrl_orig_val)
4077a387
AS		 1001 iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_CR_READ,
1002 rapl_defaults->floor_freq_reg_addr,
1003 &power_ctrl_orig_val);
3c2c0845
JP		 1004 mdata = power_ctrl_orig_val;
1005 if (enable) {
1006 mdata &= ~(0x7f << 8);
1007 mdata |= 1 << 8;
1008 }
4077a387
AS		 1009 iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE,
1010 rapl_defaults->floor_freq_reg_addr, mdata);
3c2c0845
JP		 1011}
1012
1013static u64 rapl_compute_time_window_core(struct rapl_package *rp, u64 value,
1014 bool to_raw)
1015{
1016 u64 f, y; /* fraction and exp. used for time unit */
1017
1018 /*
1019 * Special processing based on 2^Y*(1+F/4), refer
1020 * to Intel Software Developer's manual Vol.3B: CH 14.9.3.
1021 */
1022 if (!to_raw) {
1023 f = (value & 0x60) >> 5;
1024 y = value & 0x1f;
1025 value = (1 << y) * (4 + f) * rp->time_unit / 4;
1026 } else {
1027 do_div(value, rp->time_unit);
1028 y = ilog2(value);
1029 f = div64_u64(4 * (value - (1 << y)), 1 << y);
1030 value = (y & 0x1f) | ((f & 0x3) << 5);
1031 }
1032 return value;
1033}
1034
1035static u64 rapl_compute_time_window_atom(struct rapl_package *rp, u64 value,
1036 bool to_raw)
1037{
1038 /*
1039 * Atom time unit encoding is straight forward val * time_unit,
1040 * where time_unit is default to 1 sec. Never 0.
1041 */
1042 if (!to_raw)
1043 return (value) ? value *= rp->time_unit : rp->time_unit;
1044 else
1045 value = div64_u64(value, rp->time_unit);
1046
1047 return value;
1048}
1049
087e9cba 1050static const struct rapl_defaults rapl_defaults_core = {
51b63409 1051 .floor_freq_reg_addr = 0,
3c2c0845
JP		 1052 .check_unit = rapl_check_unit_core,
1053 .set_floor_freq = set_floor_freq_default,
1054 .compute_time_window = rapl_compute_time_window_core,
087e9cba
JP		 1055};
1056
d474a4d3
JP		 1057static const struct rapl_defaults rapl_defaults_hsw_server = {
1058 .check_unit = rapl_check_unit_core,
1059 .set_floor_freq = set_floor_freq_default,
1060 .compute_time_window = rapl_compute_time_window_core,
1061 .dram_domain_energy_unit = 15300,
1062};
1063
51b63409
AT		 1064static const struct rapl_defaults rapl_defaults_byt = {
1065 .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT,
1066 .check_unit = rapl_check_unit_atom,
1067 .set_floor_freq = set_floor_freq_atom,
1068 .compute_time_window = rapl_compute_time_window_atom,
1069};
1070
1071static const struct rapl_defaults rapl_defaults_tng = {
1072 .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG,
3c2c0845
JP		 1073 .check_unit = rapl_check_unit_atom,
1074 .set_floor_freq = set_floor_freq_atom,
1075 .compute_time_window = rapl_compute_time_window_atom,
087e9cba
JP		 1076};
1077
51b63409
AT		 1078static const struct rapl_defaults rapl_defaults_ann = {
1079 .floor_freq_reg_addr = 0,
1080 .check_unit = rapl_check_unit_atom,
1081 .set_floor_freq = NULL,
1082 .compute_time_window = rapl_compute_time_window_atom,
1083};
1084
1085static const struct rapl_defaults rapl_defaults_cht = {
1086 .floor_freq_reg_addr = 0,
1087 .check_unit = rapl_check_unit_atom,
1088 .set_floor_freq = NULL,
1089 .compute_time_window = rapl_compute_time_window_atom,
1090};
1091
087e9cba
JP		 1092#define RAPL_CPU(_model, _ops) { \
1093 .vendor = X86_VENDOR_INTEL, \
1094 .family = 6, \
1095 .model = _model, \
1096 .driver_data = (kernel_ulong_t)&_ops, \
1097 }
1098
ea85dbca 1099static const struct x86_cpu_id rapl_ids[] __initconst = {
62d16733
DH		 1100 RAPL_CPU(INTEL_FAM6_SANDYBRIDGE, rapl_defaults_core),
1101 RAPL_CPU(INTEL_FAM6_SANDYBRIDGE_X, rapl_defaults_core),
0bb04b5f 1102
62d16733 1103 RAPL_CPU(INTEL_FAM6_IVYBRIDGE, rapl_defaults_core),
0bb04b5f 1104
62d16733 1105 RAPL_CPU(INTEL_FAM6_HASWELL_CORE, rapl_defaults_core),
62d16733
DH		 1106 RAPL_CPU(INTEL_FAM6_HASWELL_ULT, rapl_defaults_core),
1107 RAPL_CPU(INTEL_FAM6_HASWELL_GT3E, rapl_defaults_core),
0bb04b5f
DH		 1108 RAPL_CPU(INTEL_FAM6_HASWELL_X, rapl_defaults_hsw_server),
1109
1110 RAPL_CPU(INTEL_FAM6_BROADWELL_CORE, rapl_defaults_core),
62d16733 1111 RAPL_CPU(INTEL_FAM6_BROADWELL_GT3E, rapl_defaults_core),
0bb04b5f
DH		 1112 RAPL_CPU(INTEL_FAM6_BROADWELL_XEON_D, rapl_defaults_core),
1113 RAPL_CPU(INTEL_FAM6_BROADWELL_X, rapl_defaults_hsw_server),
1114
1115 RAPL_CPU(INTEL_FAM6_SKYLAKE_DESKTOP, rapl_defaults_core),
62d16733 1116 RAPL_CPU(INTEL_FAM6_SKYLAKE_MOBILE, rapl_defaults_core),
0bb04b5f
DH		 1117 RAPL_CPU(INTEL_FAM6_KABYLAKE_MOBILE, rapl_defaults_core),
1118 RAPL_CPU(INTEL_FAM6_KABYLAKE_DESKTOP, rapl_defaults_core),
1119
1120 RAPL_CPU(INTEL_FAM6_ATOM_SILVERMONT1, rapl_defaults_byt),
62d16733
DH		 1121 RAPL_CPU(INTEL_FAM6_ATOM_AIRMONT, rapl_defaults_cht),
1122 RAPL_CPU(INTEL_FAM6_ATOM_MERRIFIELD1, rapl_defaults_tng),
62d16733
DH		 1123 RAPL_CPU(INTEL_FAM6_ATOM_MERRIFIELD2, rapl_defaults_ann),
1124 RAPL_CPU(INTEL_FAM6_ATOM_GOLDMONT, rapl_defaults_core),
0bb04b5f 1125
62d16733 1126 RAPL_CPU(INTEL_FAM6_XEON_PHI_KNL, rapl_defaults_hsw_server),
2d281d81
JP		 1127 {}
1128};
1129MODULE_DEVICE_TABLE(x86cpu, rapl_ids);
1130
1131/* read once for all raw primitive data for all packages, domains */
1132static void rapl_update_domain_data(void)
1133{
1134 int dmn, prim;
1135 u64 val;
1136 struct rapl_package *rp;
1137
1138 list_for_each_entry(rp, &rapl_packages, plist) {
1139 for (dmn = 0; dmn < rp->nr_domains; dmn++) {
1140 pr_debug("update package %d domain %s data\n", rp->id,
1141 rp->domains[dmn].name);
1142 /* exclude non-raw primitives */
1143 for (prim = 0; prim < NR_RAW_PRIMITIVES; prim++)
1144 if (!rapl_read_data_raw(&rp->domains[dmn], prim,
1145 rpi[prim].unit,
1146 &val))
1147 rp->domains[dmn].rdd.primitives[prim] =
1148 val;
1149 }
1150 }
1151
1152}
1153
1154static int rapl_unregister_powercap(void)
1155{
1156 struct rapl_package *rp;
1157 struct rapl_domain *rd, *rd_package = NULL;
1158
1159 /* unregister all active rapl packages from the powercap layer,
1160 * hotplug lock held
1161 */
1162 list_for_each_entry(rp, &rapl_packages, plist) {
309557f5 1163 package_power_limit_irq_restore(rp);
2d281d81
JP		 1164
1165 for (rd = rp->domains; rd < rp->domains + rp->nr_domains;
1166 rd++) {
1167 pr_debug("remove package, undo power limit on %d: %s\n",
1168 rp->id, rd->name);
1169 rapl_write_data_raw(rd, PL1_ENABLE, 0);
2d281d81 1170 rapl_write_data_raw(rd, PL1_CLAMP, 0);
5021282c
SI		 1171 if (find_nr_power_limit(rd) > 1) {
1172 rapl_write_data_raw(rd, PL2_ENABLE, 0);
1173 rapl_write_data_raw(rd, PL2_CLAMP, 0);
1174 }
2d281d81
JP		 1175 if (rd->id == RAPL_DOMAIN_PACKAGE) {
1176 rd_package = rd;
1177 continue;
1178 }
1179 powercap_unregister_zone(control_type, &rd->power_zone);
1180 }
1181 /* do the package zone last */
1182 if (rd_package)
1183 powercap_unregister_zone(control_type,
1184 &rd_package->power_zone);
1185 }
3521ba1c
SP		 1186
1187 if (platform_rapl_domain) {
1188 powercap_unregister_zone(control_type,
1189 &platform_rapl_domain->power_zone);
1190 kfree(platform_rapl_domain);
1191 }
1192
2d281d81
JP		 1193 powercap_unregister_control_type(control_type);
1194
1195 return 0;
1196}
1197
1198static int rapl_package_register_powercap(struct rapl_package *rp)
1199{
1200 struct rapl_domain *rd;
1201 int ret = 0;
1202 char dev_name[17]; /* max domain name = 7 + 1 + 8 for int + 1 for null*/
1203 struct powercap_zone *power_zone = NULL;
1204 int nr_pl;
1205
1206 /* first we register package domain as the parent zone*/
1207 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1208 if (rd->id == RAPL_DOMAIN_PACKAGE) {
1209 nr_pl = find_nr_power_limit(rd);
1210 pr_debug("register socket %d package domain %s\n",
1211 rp->id, rd->name);
1212 memset(dev_name, 0, sizeof(dev_name));
1213 snprintf(dev_name, sizeof(dev_name), "%s-%d",
1214 rd->name, rp->id);
1215 power_zone = powercap_register_zone(&rd->power_zone,
1216 control_type,
1217 dev_name, NULL,
1218 &zone_ops[rd->id],
1219 nr_pl,
1220 &constraint_ops);
1221 if (IS_ERR(power_zone)) {
1222 pr_debug("failed to register package, %d\n",
1223 rp->id);
1224 ret = PTR_ERR(power_zone);
1225 goto exit_package;
1226 }
1227 /* track parent zone in per package/socket data */
1228 rp->power_zone = power_zone;
1229 /* done, only one package domain per socket */
1230 break;
1231 }
1232 }
1233 if (!power_zone) {
1234 pr_err("no package domain found, unknown topology!\n");
1235 ret = -ENODEV;
1236 goto exit_package;
1237 }
1238 /* now register domains as children of the socket/package*/
1239 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1240 if (rd->id == RAPL_DOMAIN_PACKAGE)
1241 continue;
1242 /* number of power limits per domain varies */
1243 nr_pl = find_nr_power_limit(rd);
1244 power_zone = powercap_register_zone(&rd->power_zone,
1245 control_type, rd->name,
1246 rp->power_zone,
1247 &zone_ops[rd->id], nr_pl,
1248 &constraint_ops);
1249
1250 if (IS_ERR(power_zone)) {
1251 pr_debug("failed to register power_zone, %d:%s:%s\n",
1252 rp->id, rd->name, dev_name);
1253 ret = PTR_ERR(power_zone);
1254 goto err_cleanup;
1255 }
1256 }
1257
1258exit_package:
1259 return ret;
1260err_cleanup:
1261 /* clean up previously initialized domains within the package if we
1262 * failed after the first domain setup.
1263 */
1264 while (--rd >= rp->domains) {
1265 pr_debug("unregister package %d domain %s\n", rp->id, rd->name);
1266 powercap_unregister_zone(control_type, &rd->power_zone);
1267 }
1268
1269 return ret;
1270}
1271
3521ba1c
SP		 1272static int rapl_register_psys(void)
1273{
1274 struct rapl_domain *rd;
1275 struct powercap_zone *power_zone;
1276 u64 val;
1277
1278 if (rdmsrl_safe_on_cpu(0, MSR_PLATFORM_ENERGY_STATUS, &val) || !val)
1279 return -ENODEV;
1280
1281 if (rdmsrl_safe_on_cpu(0, MSR_PLATFORM_POWER_LIMIT, &val) || !val)
1282 return -ENODEV;
1283
1284 rd = kzalloc(sizeof(*rd), GFP_KERNEL);
1285 if (!rd)
1286 return -ENOMEM;
1287
1288 rd->name = rapl_domain_names[RAPL_DOMAIN_PLATFORM];
1289 rd->id = RAPL_DOMAIN_PLATFORM;
1290 rd->msrs[0] = MSR_PLATFORM_POWER_LIMIT;
1291 rd->msrs[1] = MSR_PLATFORM_ENERGY_STATUS;
1292 rd->rpl[0].prim_id = PL1_ENABLE;
1293 rd->rpl[0].name = pl1_name;
1294 rd->rpl[1].prim_id = PL2_ENABLE;
1295 rd->rpl[1].name = pl2_name;
1296 rd->rp = find_package_by_id(0);
1297
1298 power_zone = powercap_register_zone(&rd->power_zone, control_type,
1299 "psys", NULL,
1300 &zone_ops[RAPL_DOMAIN_PLATFORM],
1301 2, &constraint_ops);
1302
1303 if (IS_ERR(power_zone)) {
1304 kfree(rd);
1305 return PTR_ERR(power_zone);
1306 }
1307
1308 platform_rapl_domain = rd;
1309
1310 return 0;
1311}
1312
2d281d81
JP		 1313static int rapl_register_powercap(void)
1314{
1315 struct rapl_domain *rd;
1316 struct rapl_package *rp;
1317 int ret = 0;
1318
1319 control_type = powercap_register_control_type(NULL, "intel-rapl", NULL);
1320 if (IS_ERR(control_type)) {
1321 pr_debug("failed to register powercap control_type.\n");
1322 return PTR_ERR(control_type);
1323 }
1324 /* read the initial data */
1325 rapl_update_domain_data();
1326 list_for_each_entry(rp, &rapl_packages, plist)
1327 if (rapl_package_register_powercap(rp))
1328 goto err_cleanup_package;
3521ba1c
SP		 1329
1330 /* Don't bail out if PSys is not supported */
1331 rapl_register_psys();
1332
2d281d81
JP		 1333 return ret;
1334
1335err_cleanup_package:
1336 /* clean up previously initialized packages */
1337 list_for_each_entry_continue_reverse(rp, &rapl_packages, plist) {
1338 for (rd = rp->domains; rd < rp->domains + rp->nr_domains;
1339 rd++) {
1340 pr_debug("unregister zone/package %d, %s domain\n",
1341 rp->id, rd->name);
1342 powercap_unregister_zone(control_type, &rd->power_zone);
1343 }
1344 }
1345
1346 return ret;
1347}
1348
1349static int rapl_check_domain(int cpu, int domain)
1350{
1351 unsigned msr;
9d31c676 1352 u64 val = 0;
2d281d81
JP		 1353
1354 switch (domain) {
1355 case RAPL_DOMAIN_PACKAGE:
1356 msr = MSR_PKG_ENERGY_STATUS;
1357 break;
1358 case RAPL_DOMAIN_PP0:
1359 msr = MSR_PP0_ENERGY_STATUS;
1360 break;
1361 case RAPL_DOMAIN_PP1:
1362 msr = MSR_PP1_ENERGY_STATUS;
1363 break;
1364 case RAPL_DOMAIN_DRAM:
1365 msr = MSR_DRAM_ENERGY_STATUS;
1366 break;
3521ba1c
SP		 1367 case RAPL_DOMAIN_PLATFORM:
1368 /* PSYS(PLATFORM) is not a CPU domain, so avoid printng error */
1369 return -EINVAL;
2d281d81
JP		 1370 default:
1371 pr_err("invalid domain id %d\n", domain);
1372 return -EINVAL;
1373 }
9d31c676
JP		 1374 /* make sure domain counters are available and contains non-zero
1375 * values, otherwise skip it.
7b874772 1376 */
9d31c676
JP		 1377 if (rdmsrl_safe_on_cpu(cpu, msr, &val) || !val)
1378 return -ENODEV;
2d281d81 1379
9d31c676 1380 return 0;
2d281d81
JP		 1381}
1382
1383/* Detect active and valid domains for the given CPU, caller must
1384 * ensure the CPU belongs to the targeted package and CPU hotlug is disabled.
1385 */
1386static int rapl_detect_domains(struct rapl_package *rp, int cpu)
1387{
1388 int i;
1389 int ret = 0;
1390 struct rapl_domain *rd;
1391 u64 locked;
1392
1393 for (i = 0; i < RAPL_DOMAIN_MAX; i++) {
1394 /* use physical package id to read counters */
fcdf1797 1395 if (!rapl_check_domain(cpu, i)) {
2d281d81 1396 rp->domain_map |= 1 << i;
fcdf1797
JP		 1397 pr_info("Found RAPL domain %s\n", rapl_domain_names[i]);
1398 }
2d281d81
JP		 1399 }
1400 rp->nr_domains = bitmap_weight(&rp->domain_map, RAPL_DOMAIN_MAX);
1401 if (!rp->nr_domains) {
1402 pr_err("no valid rapl domains found in package %d\n", rp->id);
1403 ret = -ENODEV;
1404 goto done;
1405 }
1406 pr_debug("found %d domains on package %d\n", rp->nr_domains, rp->id);
1407
1408 rp->domains = kcalloc(rp->nr_domains + 1, sizeof(struct rapl_domain),
1409 GFP_KERNEL);
1410 if (!rp->domains) {
1411 ret = -ENOMEM;
1412 goto done;
1413 }
1414 rapl_init_domains(rp);
1415
1416 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1417 /* check if the domain is locked by BIOS */
79a21dbf
PB		 1418 ret = rapl_read_data_raw(rd, FW_LOCK, false, &locked);
1419 if (ret)
1420 return ret;
1421 if (locked) {
2d281d81
JP		 1422 pr_info("RAPL package %d domain %s locked by BIOS\n",
1423 rp->id, rd->name);
79a21dbf 1424 rd->state |= DOMAIN_STATE_BIOS_LOCKED;
2d281d81
JP		 1425 }
1426 }
1427
1428
1429done:
1430 return ret;
1431}
1432
1433static bool is_package_new(int package)
1434{
1435 struct rapl_package *rp;
1436
1437 /* caller prevents cpu hotplug, there will be no new packages added
1438 * or deleted while traversing the package list, no need for locking.
1439 */
1440 list_for_each_entry(rp, &rapl_packages, plist)
1441 if (package == rp->id)
1442 return false;
1443
1444 return true;
1445}
1446
1447/* RAPL interface can be made of a two-level hierarchy: package level and domain
1448 * level. We first detect the number of packages then domains of each package.
1449 * We have to consider the possiblity of CPU online/offline due to hotplug and
1450 * other scenarios.
1451 */
1452static int rapl_detect_topology(void)
1453{
1454 int i;
1455 int phy_package_id;
1456 struct rapl_package *new_package, *rp;
1457
1458 for_each_online_cpu(i) {
1459 phy_package_id = topology_physical_package_id(i);
1460 if (is_package_new(phy_package_id)) {
1461 new_package = kzalloc(sizeof(*rp), GFP_KERNEL);
1462 if (!new_package) {
1463 rapl_cleanup_data();
1464 return -ENOMEM;
1465 }
1466 /* add the new package to the list */
1467 new_package->id = phy_package_id;
1468 new_package->nr_cpus = 1;
323ee64a
JP		 1469 /* use the first active cpu of the package to access */
1470 new_package->lead_cpu = i;
2d281d81
JP		 1471 /* check if the package contains valid domains */
1472 if (rapl_detect_domains(new_package, i) ||
3c2c0845 1473 rapl_defaults->check_unit(new_package, i)) {
2d281d81
JP		 1474 kfree(new_package->domains);
1475 kfree(new_package);
1476 /* free up the packages already initialized */
1477 rapl_cleanup_data();
1478 return -ENODEV;
1479 }
1480 INIT_LIST_HEAD(&new_package->plist);
1481 list_add(&new_package->plist, &rapl_packages);
1482 } else {
1483 rp = find_package_by_id(phy_package_id);
1484 if (rp)
1485 ++rp->nr_cpus;
1486 }
1487 }
1488
1489 return 0;
1490}
1491
1492/* called from CPU hotplug notifier, hotplug lock held */
1493static void rapl_remove_package(struct rapl_package *rp)
1494{
1495 struct rapl_domain *rd, *rd_package = NULL;
1496
1497 for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
1498 if (rd->id == RAPL_DOMAIN_PACKAGE) {
1499 rd_package = rd;
1500 continue;
1501 }
1502 pr_debug("remove package %d, %s domain\n", rp->id, rd->name);
1503 powercap_unregister_zone(control_type, &rd->power_zone);
1504 }
1505 /* do parent zone last */
1506 powercap_unregister_zone(control_type, &rd_package->power_zone);
1507 list_del(&rp->plist);
1508 kfree(rp);
1509}
1510
1511/* called from CPU hotplug notifier, hotplug lock held */
1512static int rapl_add_package(int cpu)
1513{
1514 int ret = 0;
1515 int phy_package_id;
1516 struct rapl_package *rp;
1517
1518 phy_package_id = topology_physical_package_id(cpu);
1519 rp = kzalloc(sizeof(struct rapl_package), GFP_KERNEL);
1520 if (!rp)
1521 return -ENOMEM;
1522
1523 /* add the new package to the list */
1524 rp->id = phy_package_id;
1525 rp->nr_cpus = 1;
323ee64a
JP		 1526 rp->lead_cpu = cpu;
1527
2d281d81
JP		 1528 /* check if the package contains valid domains */
1529 if (rapl_detect_domains(rp, cpu) ||
3c2c0845 1530 rapl_defaults->check_unit(rp, cpu)) {
2d281d81
JP		 1531 ret = -ENODEV;
1532 goto err_free_package;
1533 }
1534 if (!rapl_package_register_powercap(rp)) {
1535 INIT_LIST_HEAD(&rp->plist);
1536 list_add(&rp->plist, &rapl_packages);
1537 return ret;
1538 }
1539
1540err_free_package:
1541 kfree(rp->domains);
1542 kfree(rp);
1543
1544 return ret;
1545}
1546
1547/* Handles CPU hotplug on multi-socket systems.
1548 * If a CPU goes online as the first CPU of the physical package
1549 * we add the RAPL package to the system. Similarly, when the last
1550 * CPU of the package is removed, we remove the RAPL package and its
1551 * associated domains. Cooling devices are handled accordingly at
1552 * per-domain level.
1553 */
1554static int rapl_cpu_callback(struct notifier_block *nfb,
1555 unsigned long action, void *hcpu)
1556{
1557 unsigned long cpu = (unsigned long)hcpu;
1558 int phy_package_id;
1559 struct rapl_package *rp;
323ee64a 1560 int lead_cpu;
2d281d81
JP		 1561
1562 phy_package_id = topology_physical_package_id(cpu);
1563 switch (action) {
1564 case CPU_ONLINE:
1565 case CPU_ONLINE_FROZEN:
1566 case CPU_DOWN_FAILED:
1567 case CPU_DOWN_FAILED_FROZEN:
1568 rp = find_package_by_id(phy_package_id);
1569 if (rp)
1570 ++rp->nr_cpus;
1571 else
1572 rapl_add_package(cpu);
1573 break;
1574 case CPU_DOWN_PREPARE:
1575 case CPU_DOWN_PREPARE_FROZEN:
1576 rp = find_package_by_id(phy_package_id);
1577 if (!rp)
1578 break;
1579 if (--rp->nr_cpus == 0)
1580 rapl_remove_package(rp);
323ee64a
JP		 1581 else if (cpu == rp->lead_cpu) {
1582 /* choose another active cpu in the package */
1583 lead_cpu = cpumask_any_but(topology_core_cpumask(cpu), cpu);
1584 if (lead_cpu < nr_cpu_ids)
1585 rp->lead_cpu = lead_cpu;
1586 else /* should never go here */
1587 pr_err("no active cpu available for package %d\n",
1588 phy_package_id);
1589 }
2d281d81
JP		 1590 }
1591
1592 return NOTIFY_OK;
1593}
1594
1595static struct notifier_block rapl_cpu_notifier = {
1596 .notifier_call = rapl_cpu_callback,
1597};
1598
1599static int __init rapl_init(void)
1600{
1601 int ret = 0;
087e9cba 1602 const struct x86_cpu_id *id;
2d281d81 1603
087e9cba
JP		 1604 id = x86_match_cpu(rapl_ids);
1605 if (!id) {
2d281d81
JP		 1606 pr_err("driver does not support CPU family %d model %d\n",
1607 boot_cpu_data.x86, boot_cpu_data.x86_model);
1608
1609 return -ENODEV;
1610 }
009f225e 1611
087e9cba
JP		 1612 rapl_defaults = (struct rapl_defaults *)id->driver_data;
1613
009f225e
SB		 1614 cpu_notifier_register_begin();
1615
2d281d81
JP		 1616 /* prevent CPU hotplug during detection */
1617 get_online_cpus();
1618 ret = rapl_detect_topology();
1619 if (ret)
1620 goto done;
1621
1622 if (rapl_register_powercap()) {
1623 rapl_cleanup_data();
1624 ret = -ENODEV;
1625 goto done;
1626 }
009f225e 1627 __register_hotcpu_notifier(&rapl_cpu_notifier);
2d281d81
JP		 1628done:
1629 put_online_cpus();
009f225e 1630 cpu_notifier_register_done();
2d281d81
JP		 1631
1632 return ret;
1633}
1634
1635static void __exit rapl_exit(void)
1636{
009f225e 1637 cpu_notifier_register_begin();
2d281d81 1638 get_online_cpus();
009f225e 1639 __unregister_hotcpu_notifier(&rapl_cpu_notifier);
2d281d81
JP		 1640 rapl_unregister_powercap();
1641 rapl_cleanup_data();
1642 put_online_cpus();
009f225e 1643 cpu_notifier_register_done();
2d281d81
JP		 1644}
1645
1646module_init(rapl_init);
1647module_exit(rapl_exit);
1648
1649MODULE_DESCRIPTION("Driver for Intel RAPL (Running Average Power Limit)");
1650MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>");
1651MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
This page took 0.18503 seconds and 5 git commands to generate.