[deliverable/linux.git] / drivers / rtc / rtc-pcf2123.c

/*
 * An SPI driver for the Philips PCF2123 RTC
 * Copyright 2009 Cyber Switching, Inc.
 *
 * Author: Chris Verges <chrisv@cyberswitching.com>
 * Maintainers: http://www.cyberswitching.com
 *
 * based on the RS5C348 driver in this same directory.
 *
 * Thanks to Christian Pellegrin <chripell@fsfe.org> for
 * the sysfs contributions to this driver.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Please note that the CS is active high, so platform data
 * should look something like:
 *
 * static struct spi_board_info ek_spi_devices[] = {
 *	...
 *	{
 *		.modalias		= "rtc-pcf2123",
 *		.chip_select		= 1,
 *		.controller_data	= (void *)AT91_PIN_PA10,
 *		.max_speed_hz		= 1000 * 1000,
 *		.mode			= SPI_CS_HIGH,
 *		.bus_num		= 0,
 *	},
 *	...
 *};
 *
 */

#include <linux/bcd.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/rtc.h>
#include <linux/spi/spi.h>
#include <linux/module.h>
#include <linux/sysfs.h>

#define DRV_VERSION "0.6"

/* REGISTERS */
#define PCF2123_REG_CTRL1	(0x00)	/* Control Register 1 */
#define PCF2123_REG_CTRL2	(0x01)	/* Control Register 2 */
#define PCF2123_REG_SC		(0x02)	/* datetime */
#define PCF2123_REG_MN		(0x03)
#define PCF2123_REG_HR		(0x04)
#define PCF2123_REG_DM		(0x05)
#define PCF2123_REG_DW		(0x06)
#define PCF2123_REG_MO		(0x07)
#define PCF2123_REG_YR		(0x08)
#define PCF2123_REG_ALRM_MN	(0x09)	/* Alarm Registers */
#define PCF2123_REG_ALRM_HR	(0x0a)
#define PCF2123_REG_ALRM_DM	(0x0b)
#define PCF2123_REG_ALRM_DW	(0x0c)
#define PCF2123_REG_OFFSET	(0x0d)	/* Clock Rate Offset Register */
#define PCF2123_REG_TMR_CLKOUT	(0x0e)	/* Timer Registers */
#define PCF2123_REG_CTDWN_TMR	(0x0f)

/* PCF2123_REG_CTRL1 BITS */
#define CTRL1_CLEAR		(0)	/* Clear */
#define CTRL1_CORR_INT		BIT(1)	/* Correction irq enable */
#define CTRL1_12_HOUR		BIT(2)	/* 12 hour time */
#define CTRL1_SW_RESET	(BIT(3) | BIT(4) | BIT(6))	/* Software reset */
#define CTRL1_STOP		BIT(5)	/* Stop the clock */
#define CTRL1_EXT_TEST		BIT(7)	/* External clock test mode */

/* PCF2123_REG_CTRL2 BITS */
#define CTRL2_TIE		BIT(0)	/* Countdown timer irq enable */
#define CTRL2_AIE		BIT(1)	/* Alarm irq enable */
#define CTRL2_TF		BIT(2)	/* Countdown timer flag */
#define CTRL2_AF		BIT(3)	/* Alarm flag */
#define CTRL2_TI_TP		BIT(4)	/* Irq pin generates pulse */
#define CTRL2_MSF		BIT(5)	/* Minute or second irq flag */
#define CTRL2_SI		BIT(6)	/* Second irq enable */
#define CTRL2_MI		BIT(7)	/* Minute irq enable */

/* PCF2123_REG_SC BITS */
#define OSC_HAS_STOPPED		BIT(7)	/* Clock has been stopped */

/* PCF2123_REG_ALRM_XX BITS */
#define ALRM_ENABLE		BIT(7)	/* MN, HR, DM, or DW alarm enable */

/* PCF2123_REG_TMR_CLKOUT BITS */
#define CD_TMR_4096KHZ		(0)	/* 4096 KHz countdown timer */
#define CD_TMR_64HZ		(1)	/* 64 Hz countdown timer */
#define CD_TMR_1HZ		(2)	/* 1 Hz countdown timer */
#define CD_TMR_60th_HZ		(3)	/* 60th Hz countdown timer */
#define CD_TMR_TE		BIT(3)	/* Countdown timer enable */

/* PCF2123_REG_OFFSET BITS */
#define OFFSET_SIGN_BIT		BIT(6)	/* 2's complement sign bit */
#define OFFSET_COARSE		BIT(7)	/* Coarse mode offset */
#define OFFSET_STEP		(2170)	/* Offset step in parts per billion */

/* READ/WRITE ADDRESS BITS */
#define PCF2123_WRITE		BIT(4)
#define PCF2123_READ		(BIT(4) | BIT(7))


static struct spi_driver pcf2123_driver;

struct pcf2123_sysfs_reg {
	struct device_attribute attr;
	char name[2];
};

struct pcf2123_plat_data {
	struct rtc_device *rtc;
	struct pcf2123_sysfs_reg regs[16];
};

/*
 * Causes a 30 nanosecond delay to ensure that the PCF2123 chip select
 * is released properly after an SPI write.  This function should be
 * called after EVERY read/write call over SPI.
 */
static inline void pcf2123_delay_trec(void)
{
	ndelay(30);
}

static int pcf2123_read(struct device *dev, u8 reg, u8 *rxbuf, size_t size)
{
	struct spi_device *spi = to_spi_device(dev);
	int ret;

	reg |= PCF2123_READ;
	ret = spi_write_then_read(spi, &reg, 1, rxbuf, size);
	pcf2123_delay_trec();

	return ret;
}

static int pcf2123_write(struct device *dev, u8 *txbuf, size_t size)
{
	struct spi_device *spi = to_spi_device(dev);
	int ret;

	txbuf[0] |= PCF2123_WRITE;
	ret = spi_write(spi, txbuf, size);
	pcf2123_delay_trec();

	return ret;
}

static int pcf2123_write_reg(struct device *dev, u8 reg, u8 val)
{
	u8 txbuf[2];

	txbuf[0] = reg;
	txbuf[1] = val;
	return pcf2123_write(dev, txbuf, sizeof(txbuf));
}

static ssize_t pcf2123_show(struct device *dev, struct device_attribute *attr,
			    char *buffer)
{
	struct pcf2123_sysfs_reg *r;
	u8 rxbuf[1];
	unsigned long reg;
	int ret;

	r = container_of(attr, struct pcf2123_sysfs_reg, attr);

	ret = kstrtoul(r->name, 16, &reg);
	if (ret)
		return ret;

	ret = pcf2123_read(dev, reg, rxbuf, 1);
	if (ret < 0)
		return -EIO;

	return sprintf(buffer, "0x%x\n", rxbuf[0]);
}

static ssize_t pcf2123_store(struct device *dev, struct device_attribute *attr,
			     const char *buffer, size_t count) {
	struct pcf2123_sysfs_reg *r;
	unsigned long reg;
	unsigned long val;

	int ret;

	r = container_of(attr, struct pcf2123_sysfs_reg, attr);

	ret = kstrtoul(r->name, 16, &reg);
	if (ret)
		return ret;

	ret = kstrtoul(buffer, 10, &val);
	if (ret)
		return ret;

	pcf2123_write_reg(dev, reg, val);
	if (ret < 0)
		return -EIO;
	return count;
}

static int pcf2123_read_offset(struct device *dev, long *offset)
{
	int ret;
	s8 reg;

	ret = pcf2123_read(dev, PCF2123_REG_OFFSET, &reg, 1);
	if (ret < 0)
		return ret;

	if (reg & OFFSET_COARSE)
		reg <<= 1; /* multiply by 2 and sign extend */
	else
		reg |= (reg & OFFSET_SIGN_BIT) << 1; /* sign extend only */

	*offset = ((long)reg) * OFFSET_STEP;

	return 0;
}

/*
 * The offset register is a 7 bit signed value with a coarse bit in bit 7.
 * The main difference between the two is normal offset adjusts the first
 * second of n minutes every other hour, with 61, 62 and 63 being shoved
 * into the 60th minute.
 * The coarse adjustment does the same, but every hour.
 * the two overlap, with every even normal offset value corresponding
 * to a coarse offset. Based on this algorithm, it seems that despite the
 * name, coarse offset is a better fit for overlapping values.
 */
static int pcf2123_set_offset(struct device *dev, long offset)
{
	s8 reg;

	if (offset > OFFSET_STEP * 127)
		reg = 127;
	else if (offset < OFFSET_STEP * -128)
		reg = -128;
	else
		reg = (s8)((offset + (OFFSET_STEP >> 1)) / OFFSET_STEP);

	/* choose fine offset only for odd values in the normal range */
	if (reg & 1 && reg <= 63 && reg >= -64) {
		/* Normal offset. Clear the coarse bit */
		reg &= ~OFFSET_COARSE;
	} else {
		/* Coarse offset. Divide by 2 and set the coarse bit */
		reg >>= 1;
		reg |= OFFSET_COARSE;
	}

	return pcf2123_write_reg(dev, PCF2123_REG_OFFSET, reg);
}

static int pcf2123_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	u8 rxbuf[7];
	int ret;

	ret = pcf2123_read(dev, PCF2123_REG_SC, rxbuf, sizeof(rxbuf));
	if (ret < 0)
		return ret;

	if (rxbuf[0] & OSC_HAS_STOPPED) {
		dev_info(dev, "clock was stopped. Time is not valid\n");
		return -EINVAL;
	}

	tm->tm_sec = bcd2bin(rxbuf[0] & 0x7F);
	tm->tm_min = bcd2bin(rxbuf[1] & 0x7F);
	tm->tm_hour = bcd2bin(rxbuf[2] & 0x3F); /* rtc hr 0-23 */
	tm->tm_mday = bcd2bin(rxbuf[3] & 0x3F);
	tm->tm_wday = rxbuf[4] & 0x07;
	tm->tm_mon = bcd2bin(rxbuf[5] & 0x1F) - 1; /* rtc mn 1-12 */
	tm->tm_year = bcd2bin(rxbuf[6]);
	if (tm->tm_year < 70)
		tm->tm_year += 100;	/* assume we are in 1970...2069 */

	dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
			"mday=%d, mon=%d, year=%d, wday=%d\n",
			__func__,
			tm->tm_sec, tm->tm_min, tm->tm_hour,
			tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);

	return rtc_valid_tm(tm);
}

static int pcf2123_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	u8 txbuf[8];
	int ret;

	dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
			"mday=%d, mon=%d, year=%d, wday=%d\n",
			__func__,
			tm->tm_sec, tm->tm_min, tm->tm_hour,
			tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);

	/* Stop the counter first */
	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP);
	if (ret < 0)
		return ret;

	/* Set the new time */
	txbuf[0] = PCF2123_REG_SC;
	txbuf[1] = bin2bcd(tm->tm_sec & 0x7F);
	txbuf[2] = bin2bcd(tm->tm_min & 0x7F);
	txbuf[3] = bin2bcd(tm->tm_hour & 0x3F);
	txbuf[4] = bin2bcd(tm->tm_mday & 0x3F);
	txbuf[5] = tm->tm_wday & 0x07;
	txbuf[6] = bin2bcd((tm->tm_mon + 1) & 0x1F); /* rtc mn 1-12 */
	txbuf[7] = bin2bcd(tm->tm_year < 100 ? tm->tm_year : tm->tm_year - 100);

	ret = pcf2123_write(dev, txbuf, sizeof(txbuf));
	if (ret < 0)
		return ret;

	/* Start the counter */
	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR);
	if (ret < 0)
		return ret;

	return 0;
}

static int pcf2123_reset(struct device *dev)
{
	int ret;
	u8  rxbuf[2];

	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_SW_RESET);
	if (ret < 0)
		return ret;

	/* Stop the counter */
	dev_dbg(dev, "stopping RTC\n");
	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP);
	if (ret < 0)
		return ret;

	/* See if the counter was actually stopped */
	dev_dbg(dev, "checking for presence of RTC\n");
	ret = pcf2123_read(dev, PCF2123_REG_CTRL1, rxbuf, sizeof(rxbuf));
	if (ret < 0)
		return ret;

	dev_dbg(dev, "received data from RTC (0x%02X 0x%02X)\n",
		rxbuf[0], rxbuf[1]);
	if (!(rxbuf[0] & CTRL1_STOP))
		return -ENODEV;

	/* Start the counter */
	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR);
	if (ret < 0)
		return ret;

	return 0;
}

static const struct rtc_class_ops pcf2123_rtc_ops = {
	.read_time	= pcf2123_rtc_read_time,
	.set_time	= pcf2123_rtc_set_time,
	.read_offset	= pcf2123_read_offset,
	.set_offset	= pcf2123_set_offset,

};

static int pcf2123_probe(struct spi_device *spi)
{
	struct rtc_device *rtc;
	struct rtc_time tm;
	struct pcf2123_plat_data *pdata;
	int ret, i;

	pdata = devm_kzalloc(&spi->dev, sizeof(struct pcf2123_plat_data),
				GFP_KERNEL);
	if (!pdata)
		return -ENOMEM;
	spi->dev.platform_data = pdata;

	ret = pcf2123_rtc_read_time(&spi->dev, &tm);
	if (ret < 0) {
		ret = pcf2123_reset(&spi->dev);
		if (ret < 0) {
			dev_err(&spi->dev, "chip not found\n");
			goto kfree_exit;
		}
	}

	dev_info(&spi->dev, "chip found, driver version " DRV_VERSION "\n");
	dev_info(&spi->dev, "spiclk %u KHz.\n",
			(spi->max_speed_hz + 500) / 1000);

	/* Finalize the initialization */
	rtc = devm_rtc_device_register(&spi->dev, pcf2123_driver.driver.name,
			&pcf2123_rtc_ops, THIS_MODULE);

	if (IS_ERR(rtc)) {
		dev_err(&spi->dev, "failed to register.\n");
		ret = PTR_ERR(rtc);
		goto kfree_exit;
	}

	pdata->rtc = rtc;

	for (i = 0; i < 16; i++) {
		sysfs_attr_init(&pdata->regs[i].attr.attr);
		sprintf(pdata->regs[i].name, "%1x", i);
		pdata->regs[i].attr.attr.mode = S_IRUGO | S_IWUSR;
		pdata->regs[i].attr.attr.name = pdata->regs[i].name;
		pdata->regs[i].attr.show = pcf2123_show;
		pdata->regs[i].attr.store = pcf2123_store;
		ret = device_create_file(&spi->dev, &pdata->regs[i].attr);
		if (ret) {
			dev_err(&spi->dev, "Unable to create sysfs %s\n",
				pdata->regs[i].name);
			goto sysfs_exit;
		}
	}

	return 0;

sysfs_exit:
	for (i--; i >= 0; i--)
		device_remove_file(&spi->dev, &pdata->regs[i].attr);

kfree_exit:
	spi->dev.platform_data = NULL;
	return ret;
}

static int pcf2123_remove(struct spi_device *spi)
{
	struct pcf2123_plat_data *pdata = dev_get_platdata(&spi->dev);
	int i;

	if (pdata) {
		for (i = 0; i < 16; i++)
			if (pdata->regs[i].name[0])
				device_remove_file(&spi->dev,
						   &pdata->regs[i].attr);
	}

	return 0;
}

#ifdef CONFIG_OF
static const struct of_device_id pcf2123_dt_ids[] = {
	{ .compatible = "nxp,rtc-pcf2123", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, pcf2123_dt_ids);
#endif

static struct spi_driver pcf2123_driver = {
	.driver	= {
			.name	= "rtc-pcf2123",
			.of_match_table = of_match_ptr(pcf2123_dt_ids),
	},
	.probe	= pcf2123_probe,
	.remove	= pcf2123_remove,
};

module_spi_driver(pcf2123_driver);

MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>");
MODULE_DESCRIPTION("NXP PCF2123 RTC driver");
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
7f3923a1 CV	1	/*
	2	* An SPI driver for the Philips PCF2123 RTC
	3	* Copyright 2009 Cyber Switching, Inc.
	4	*
	5	* Author: Chris Verges <chrisv@cyberswitching.com>
	6	* Maintainers: http://www.cyberswitching.com
	7	*
	8	* based on the RS5C348 driver in this same directory.
	9	*
	10	* Thanks to Christian Pellegrin <chripell@fsfe.org> for
	11	* the sysfs contributions to this driver.
	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License version 2 as
	15	* published by the Free Software Foundation.
	16	*
	17	* Please note that the CS is active high, so platform data
	18	* should look something like:
	19	*
	20	* static struct spi_board_info ek_spi_devices[] = {
369015fb SK	21	* ...
	22	* {
	23	* .modalias = "rtc-pcf2123",
	24	* .chip_select = 1,
	25	* .controller_data = (void *)AT91_PIN_PA10,
7f3923a1 CV	26	* .max_speed_hz = 1000 * 1000,
	27	* .mode = SPI_CS_HIGH,
	28	* .bus_num = 0,
	29	* },
	30	* ...
	31	*};
	32	*
	33	*/
	34
	35	#include <linux/bcd.h>
	36	#include <linux/delay.h>
	37	#include <linux/device.h>
	38	#include <linux/errno.h>
	39	#include <linux/init.h>
	40	#include <linux/kernel.h>
3fc70077	41	#include <linux/of.h>
7f3923a1	42	#include <linux/string.h>
5a0e3ad6	43	#include <linux/slab.h>
7f3923a1 CV	44	#include <linux/rtc.h>
7f3923a1 CV	45	#include <linux/spi/spi.h>
2113852b	46	#include <linux/module.h>
5ed12f12	47	#include <linux/sysfs.h>
7f3923a1	48
f3d2570a	49	#define DRV_VERSION "0.6"
7f3923a1	50
245cb74b	51	/* REGISTERS */
7f3923a1 CV	52	#define PCF2123_REG_CTRL1 (0x00) /* Control Register 1 */
	53	#define PCF2123_REG_CTRL2 (0x01) /* Control Register 2 */
	54	#define PCF2123_REG_SC (0x02) /* datetime */
	55	#define PCF2123_REG_MN (0x03)
	56	#define PCF2123_REG_HR (0x04)
	57	#define PCF2123_REG_DM (0x05)
	58	#define PCF2123_REG_DW (0x06)
	59	#define PCF2123_REG_MO (0x07)
	60	#define PCF2123_REG_YR (0x08)
245cb74b JC	61	#define PCF2123_REG_ALRM_MN (0x09) /* Alarm Registers */
	62	#define PCF2123_REG_ALRM_HR (0x0a)
	63	#define PCF2123_REG_ALRM_DM (0x0b)
	64	#define PCF2123_REG_ALRM_DW (0x0c)
	65	#define PCF2123_REG_OFFSET (0x0d) /* Clock Rate Offset Register */
	66	#define PCF2123_REG_TMR_CLKOUT (0x0e) /* Timer Registers */
	67	#define PCF2123_REG_CTDWN_TMR (0x0f)
	68
	69	/* PCF2123_REG_CTRL1 BITS */
	70	#define CTRL1_CLEAR (0) /* Clear */
	71	#define CTRL1_CORR_INT BIT(1) /* Correction irq enable */
	72	#define CTRL1_12_HOUR BIT(2) /* 12 hour time */
	73	#define CTRL1_SW_RESET (BIT(3) \| BIT(4) \| BIT(6)) /* Software reset */
	74	#define CTRL1_STOP BIT(5) /* Stop the clock */
	75	#define CTRL1_EXT_TEST BIT(7) /* External clock test mode */
	76
	77	/* PCF2123_REG_CTRL2 BITS */
	78	#define CTRL2_TIE BIT(0) /* Countdown timer irq enable */
	79	#define CTRL2_AIE BIT(1) /* Alarm irq enable */
	80	#define CTRL2_TF BIT(2) /* Countdown timer flag */
	81	#define CTRL2_AF BIT(3) /* Alarm flag */
	82	#define CTRL2_TI_TP BIT(4) /* Irq pin generates pulse */
	83	#define CTRL2_MSF BIT(5) /* Minute or second irq flag */
	84	#define CTRL2_SI BIT(6) /* Second irq enable */
	85	#define CTRL2_MI BIT(7) /* Minute irq enable */
	86
	87	/* PCF2123_REG_SC BITS */
	88	#define OSC_HAS_STOPPED BIT(7) /* Clock has been stopped */
	89
	90	/* PCF2123_REG_ALRM_XX BITS */
	91	#define ALRM_ENABLE BIT(7) /* MN, HR, DM, or DW alarm enable */
	92
	93	/* PCF2123_REG_TMR_CLKOUT BITS */
	94	#define CD_TMR_4096KHZ (0) /* 4096 KHz countdown timer */
	95	#define CD_TMR_64HZ (1) /* 64 Hz countdown timer */
	96	#define CD_TMR_1HZ (2) /* 1 Hz countdown timer */
	97	#define CD_TMR_60th_HZ (3) /* 60th Hz countdown timer */
	98	#define CD_TMR_TE BIT(3) /* Countdown timer enable */
	99
	100	/* PCF2123_REG_OFFSET BITS */
	101	#define OFFSET_SIGN_BIT BIT(6) /* 2's complement sign bit */
	102	#define OFFSET_COARSE BIT(7) /* Coarse mode offset */
bae2f647	103	#define OFFSET_STEP (2170) /* Offset step in parts per billion */
245cb74b JC	104
	105	/* READ/WRITE ADDRESS BITS */
	106	#define PCF2123_WRITE BIT(4)
	107	#define PCF2123_READ (BIT(4) \| BIT(7))
7f3923a1	108
7f3923a1 CV	109
	110	static struct spi_driver pcf2123_driver;
	111
	112	struct pcf2123_sysfs_reg {
f3d2570a	113	struct device_attribute attr;
7f3923a1 CV	114	char name[2];
	115	};
	116
	117	struct pcf2123_plat_data {
	118	struct rtc_device *rtc;
	119	struct pcf2123_sysfs_reg regs[16];
	120	};
	121
	122	/*
	123	* Causes a 30 nanosecond delay to ensure that the PCF2123 chip select
	124	* is released properly after an SPI write. This function should be
	125	* called after EVERY read/write call over SPI.
	126	*/
	127	static inline void pcf2123_delay_trec(void)
	128	{
	129	ndelay(30);
	130	}
	131
66c056d6 JC	132	static int pcf2123_read(struct device dev, u8 reg, u8 rxbuf, size_t size)
	133	{
	134	struct spi_device *spi = to_spi_device(dev);
	135	int ret;
	136
	137	reg \|= PCF2123_READ;
	138	ret = spi_write_then_read(spi, &reg, 1, rxbuf, size);
	139	pcf2123_delay_trec();
	140
	141	return ret;
	142	}
	143
809b453b JC	144	static int pcf2123_write(struct device dev, u8 txbuf, size_t size)
	145	{
	146	struct spi_device *spi = to_spi_device(dev);
	147	int ret;
	148
	149	txbuf[0] \|= PCF2123_WRITE;
	150	ret = spi_write(spi, txbuf, size);
	151	pcf2123_delay_trec();
	152
	153	return ret;
	154	}
	155
	156	static int pcf2123_write_reg(struct device *dev, u8 reg, u8 val)
	157	{
	158	u8 txbuf[2];
	159
	160	txbuf[0] = reg;
	161	txbuf[1] = val;
	162	return pcf2123_write(dev, txbuf, sizeof(txbuf));
	163	}
	164
7f3923a1 CV	165	static ssize_t pcf2123_show(struct device dev, struct device_attribute attr,
	166	char *buffer)
	167	{
f3d2570a	168	struct pcf2123_sysfs_reg *r;
66c056d6	169	u8 rxbuf[1];
f3d2570a	170	unsigned long reg;
7f3923a1 CV	171	int ret;
7f3923a1 CV	172
f3d2570a CV	173	r = container_of(attr, struct pcf2123_sysfs_reg, attr);
f3d2570a CV	174
4c5591c1 JH	175	ret = kstrtoul(r->name, 16, &reg);
	176	if (ret)
	177	return ret;
f3d2570a	178
66c056d6	179	ret = pcf2123_read(dev, reg, rxbuf, 1);
7f3923a1	180	if (ret < 0)
f3d2570a	181	return -EIO;
66c056d6	182
f3d2570a	183	return sprintf(buffer, "0x%x\n", rxbuf[0]);
7f3923a1 CV	184	}
	185
	186	static ssize_t pcf2123_store(struct device dev, struct device_attribute attr,
	187	const char *buffer, size_t count) {
f3d2570a	188	struct pcf2123_sysfs_reg *r;
f3d2570a CV	189	unsigned long reg;
	190	unsigned long val;
	191
7f3923a1 CV	192	int ret;
7f3923a1 CV	193
f3d2570a CV	194	r = container_of(attr, struct pcf2123_sysfs_reg, attr);
f3d2570a CV	195
4c5591c1 JH	196	ret = kstrtoul(r->name, 16, &reg);
	197	if (ret)
	198	return ret;
	199
	200	ret = kstrtoul(buffer, 10, &val);
	201	if (ret)
	202	return ret;
f3d2570a	203
809b453b	204	pcf2123_write_reg(dev, reg, val);
7f3923a1 CV	205	if (ret < 0)
7f3923a1 CV	206	return -EIO;
7f3923a1 CV	207	return count;
	208	}
	209
bae2f647 JC	210	static int pcf2123_read_offset(struct device dev, long offset)
	211	{
	212	int ret;
	213	s8 reg;
	214
	215	ret = pcf2123_read(dev, PCF2123_REG_OFFSET, &reg, 1);
	216	if (ret < 0)
	217	return ret;
	218
	219	if (reg & OFFSET_COARSE)
	220	reg <<= 1; /* multiply by 2 and sign extend */
	221	else
	222	reg \|= (reg & OFFSET_SIGN_BIT) << 1; /* sign extend only */
	223
	224	offset = ((long)reg) OFFSET_STEP;
	225
	226	return 0;
	227	}
	228
	229	/*
	230	* The offset register is a 7 bit signed value with a coarse bit in bit 7.
	231	* The main difference between the two is normal offset adjusts the first
	232	* second of n minutes every other hour, with 61, 62 and 63 being shoved
	233	* into the 60th minute.
	234	* The coarse adjustment does the same, but every hour.
	235	* the two overlap, with every even normal offset value corresponding
	236	* to a coarse offset. Based on this algorithm, it seems that despite the
	237	* name, coarse offset is a better fit for overlapping values.
	238	*/
	239	static int pcf2123_set_offset(struct device *dev, long offset)
	240	{
	241	s8 reg;
	242
	243	if (offset > OFFSET_STEP * 127)
	244	reg = 127;
	245	else if (offset < OFFSET_STEP * -128)
	246	reg = -128;
	247	else
	248	reg = (s8)((offset + (OFFSET_STEP >> 1)) / OFFSET_STEP);
	249
	250	/* choose fine offset only for odd values in the normal range */
	251	if (reg & 1 && reg <= 63 && reg >= -64) {
	252	/* Normal offset. Clear the coarse bit */
	253	reg &= ~OFFSET_COARSE;
	254	} else {
	255	/* Coarse offset. Divide by 2 and set the coarse bit */
	256	reg >>= 1;
	257	reg \|= OFFSET_COARSE;
	258	}
	259
	260	return pcf2123_write_reg(dev, PCF2123_REG_OFFSET, reg);
	261	}
	262
7f3923a1 CV	263	static int pcf2123_rtc_read_time(struct device dev, struct rtc_time tm)
7f3923a1 CV	264	{
66c056d6	265	u8 rxbuf[7];
7f3923a1 CV	266	int ret;
7f3923a1 CV	267
66c056d6	268	ret = pcf2123_read(dev, PCF2123_REG_SC, rxbuf, sizeof(rxbuf));
7f3923a1 CV	269	if (ret < 0)
7f3923a1 CV	270	return ret;
7f3923a1	271
f07fa924 JC	272	if (rxbuf[0] & OSC_HAS_STOPPED) {
	273	dev_info(dev, "clock was stopped. Time is not valid\n");
	274	return -EINVAL;
	275	}
	276
7f3923a1 CV	277	tm->tm_sec = bcd2bin(rxbuf[0] & 0x7F);
	278	tm->tm_min = bcd2bin(rxbuf[1] & 0x7F);
	279	tm->tm_hour = bcd2bin(rxbuf[2] & 0x3F); /* rtc hr 0-23 */
	280	tm->tm_mday = bcd2bin(rxbuf[3] & 0x3F);
	281	tm->tm_wday = rxbuf[4] & 0x07;
	282	tm->tm_mon = bcd2bin(rxbuf[5] & 0x1F) - 1; /* rtc mn 1-12 */
	283	tm->tm_year = bcd2bin(rxbuf[6]);
	284	if (tm->tm_year < 70)
	285	tm->tm_year += 100; /* assume we are in 1970...2069 */
	286
	287	dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
	288	"mday=%d, mon=%d, year=%d, wday=%d\n",
	289	__func__,
	290	tm->tm_sec, tm->tm_min, tm->tm_hour,
	291	tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
	292
821f51c4	293	return rtc_valid_tm(tm);
7f3923a1 CV	294	}
	295
	296	static int pcf2123_rtc_set_time(struct device dev, struct rtc_time tm)
	297	{
7f3923a1 CV	298	u8 txbuf[8];
	299	int ret;
	300
	301	dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
	302	"mday=%d, mon=%d, year=%d, wday=%d\n",
	303	__func__,
	304	tm->tm_sec, tm->tm_min, tm->tm_hour,
	305	tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
	306
	307	/* Stop the counter first */
809b453b	308	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP);
7f3923a1 CV	309	if (ret < 0)
7f3923a1 CV	310	return ret;
7f3923a1 CV	311
7f3923a1 CV	312	/* Set the new time */
809b453b	313	txbuf[0] = PCF2123_REG_SC;
7f3923a1 CV	314	txbuf[1] = bin2bcd(tm->tm_sec & 0x7F);
	315	txbuf[2] = bin2bcd(tm->tm_min & 0x7F);
	316	txbuf[3] = bin2bcd(tm->tm_hour & 0x3F);
	317	txbuf[4] = bin2bcd(tm->tm_mday & 0x3F);
	318	txbuf[5] = tm->tm_wday & 0x07;
	319	txbuf[6] = bin2bcd((tm->tm_mon + 1) & 0x1F); /* rtc mn 1-12 */
	320	txbuf[7] = bin2bcd(tm->tm_year < 100 ? tm->tm_year : tm->tm_year - 100);
	321
809b453b	322	ret = pcf2123_write(dev, txbuf, sizeof(txbuf));
7f3923a1 CV	323	if (ret < 0)
7f3923a1 CV	324	return ret;
7f3923a1 CV	325
7f3923a1 CV	326	/* Start the counter */
809b453b	327	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR);
7f3923a1 CV	328	if (ret < 0)
7f3923a1 CV	329	return ret;
7f3923a1 CV	330
	331	return 0;
	332	}
	333
1e094b94 JC	334	static int pcf2123_reset(struct device *dev)
	335	{
	336	int ret;
	337	u8 rxbuf[2];
	338
	339	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_SW_RESET);
	340	if (ret < 0)
	341	return ret;
	342
	343	/* Stop the counter */
	344	dev_dbg(dev, "stopping RTC\n");
	345	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_STOP);
	346	if (ret < 0)
	347	return ret;
	348
	349	/* See if the counter was actually stopped */
	350	dev_dbg(dev, "checking for presence of RTC\n");
	351	ret = pcf2123_read(dev, PCF2123_REG_CTRL1, rxbuf, sizeof(rxbuf));
	352	if (ret < 0)
	353	return ret;
	354
	355	dev_dbg(dev, "received data from RTC (0x%02X 0x%02X)\n",
	356	rxbuf[0], rxbuf[1]);
	357	if (!(rxbuf[0] & CTRL1_STOP))
	358	return -ENODEV;
	359
	360	/* Start the counter */
	361	ret = pcf2123_write_reg(dev, PCF2123_REG_CTRL1, CTRL1_CLEAR);
	362	if (ret < 0)
	363	return ret;
	364
	365	return 0;
	366	}
	367
7f3923a1 CV	368	static const struct rtc_class_ops pcf2123_rtc_ops = {
	369	.read_time = pcf2123_rtc_read_time,
	370	.set_time = pcf2123_rtc_set_time,
bae2f647 JC	371	.read_offset = pcf2123_read_offset,
	372	.set_offset = pcf2123_set_offset,
	373
7f3923a1 CV	374	};
7f3923a1 CV	375
5a167f45	376	static int pcf2123_probe(struct spi_device *spi)
7f3923a1 CV	377	{
7f3923a1 CV	378	struct rtc_device *rtc;
f07fa924	379	struct rtc_time tm;
7f3923a1	380	struct pcf2123_plat_data *pdata;
7f3923a1 CV	381	int ret, i;
7f3923a1 CV	382
dd48ccc4 JH	383	pdata = devm_kzalloc(&spi->dev, sizeof(struct pcf2123_plat_data),
dd48ccc4 JH	384	GFP_KERNEL);
7f3923a1 CV	385	if (!pdata)
	386	return -ENOMEM;
	387	spi->dev.platform_data = pdata;
	388
f07fa924	389	ret = pcf2123_rtc_read_time(&spi->dev, &tm);
1e094b94	390	if (ret < 0) {
f07fa924 JC	391	ret = pcf2123_reset(&spi->dev);
	392	if (ret < 0) {
	393	dev_err(&spi->dev, "chip not found\n");
	394	goto kfree_exit;
	395	}
7f3923a1 CV	396	}
	397
	398	dev_info(&spi->dev, "chip found, driver version " DRV_VERSION "\n");
	399	dev_info(&spi->dev, "spiclk %u KHz.\n",
	400	(spi->max_speed_hz + 500) / 1000);
	401
7f3923a1	402	/* Finalize the initialization */
dd48ccc4	403	rtc = devm_rtc_device_register(&spi->dev, pcf2123_driver.driver.name,
7f3923a1 CV	404	&pcf2123_rtc_ops, THIS_MODULE);
	405
	406	if (IS_ERR(rtc)) {
	407	dev_err(&spi->dev, "failed to register.\n");
	408	ret = PTR_ERR(rtc);
	409	goto kfree_exit;
	410	}
	411
	412	pdata->rtc = rtc;
	413
	414	for (i = 0; i < 16; i++) {
5ed12f12	415	sysfs_attr_init(&pdata->regs[i].attr.attr);
7f3923a1 CV	416	sprintf(pdata->regs[i].name, "%1x", i);
	417	pdata->regs[i].attr.attr.mode = S_IRUGO \| S_IWUSR;
	418	pdata->regs[i].attr.attr.name = pdata->regs[i].name;
	419	pdata->regs[i].attr.show = pcf2123_show;
	420	pdata->regs[i].attr.store = pcf2123_store;
	421	ret = device_create_file(&spi->dev, &pdata->regs[i].attr);
	422	if (ret) {
	423	dev_err(&spi->dev, "Unable to create sysfs %s\n",
	424	pdata->regs[i].name);
f3d2570a	425	goto sysfs_exit;
7f3923a1 CV	426	}
	427	}
	428
	429	return 0;
f3d2570a CV	430
	431	sysfs_exit:
	432	for (i--; i >= 0; i--)
	433	device_remove_file(&spi->dev, &pdata->regs[i].attr);
	434
7f3923a1	435	kfree_exit:
7f3923a1 CV	436	spi->dev.platform_data = NULL;
	437	return ret;
	438	}
	439
5a167f45	440	static int pcf2123_remove(struct spi_device *spi)
7f3923a1	441	{
ffc75bb8	442	struct pcf2123_plat_data *pdata = dev_get_platdata(&spi->dev);
7f3923a1 CV	443	int i;
	444
	445	if (pdata) {
7f3923a1 CV	446	for (i = 0; i < 16; i++)
	447	if (pdata->regs[i].name[0])
	448	device_remove_file(&spi->dev,
	449	&pdata->regs[i].attr);
7f3923a1 CV	450	}
	451
	452	return 0;
	453	}
	454
3fc70077 JC	455	#ifdef CONFIG_OF
	456	static const struct of_device_id pcf2123_dt_ids[] = {
	457	{ .compatible = "nxp,rtc-pcf2123", },
	458	{ /* sentinel */ }
	459	};
	460	MODULE_DEVICE_TABLE(of, pcf2123_dt_ids);
	461	#endif
	462
7f3923a1 CV	463	static struct spi_driver pcf2123_driver = {
	464	.driver = {
	465	.name = "rtc-pcf2123",
3fc70077	466	.of_match_table = of_match_ptr(pcf2123_dt_ids),
7f3923a1 CV	467	},
7f3923a1 CV	468	.probe = pcf2123_probe,
5a167f45	469	.remove = pcf2123_remove,
7f3923a1 CV	470	};
7f3923a1 CV	471
109e9418	472	module_spi_driver(pcf2123_driver);
7f3923a1 CV	473
	474	MODULE_AUTHOR("Chris Verges <chrisv@cyberswitching.com>");
	475	MODULE_DESCRIPTION("NXP PCF2123 RTC driver");
	476	MODULE_LICENSE("GPL");
	477	MODULE_VERSION(DRV_VERSION);