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6733b39a | 1 | /** |
65c5efa8 | 2 | * Copyright (C) 2005 - 2014 Emulex |
6733b39a JK |
3 | * All rights reserved. |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License version 2 | |
7 | * as published by the Free Software Foundation. The full GNU General | |
8 | * Public License is included in this distribution in the file called COPYING. | |
9 | * | |
255fa9a3 | 10 | * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com) |
6733b39a JK |
11 | * |
12 | * Contact Information: | |
255fa9a3 | 13 | * linux-drivers@emulex.com |
6733b39a | 14 | * |
255fa9a3 JK |
15 | * Emulex |
16 | * 3333 Susan Street | |
17 | * Costa Mesa, CA 92626 | |
6733b39a | 18 | */ |
255fa9a3 | 19 | |
6733b39a JK |
20 | #include <linux/reboot.h> |
21 | #include <linux/delay.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
6733b39a JK |
23 | #include <linux/interrupt.h> |
24 | #include <linux/blkdev.h> | |
25 | #include <linux/pci.h> | |
26 | #include <linux/string.h> | |
27 | #include <linux/kernel.h> | |
28 | #include <linux/semaphore.h> | |
c7acc5b8 | 29 | #include <linux/iscsi_boot_sysfs.h> |
acf3368f | 30 | #include <linux/module.h> |
ffce3e2e | 31 | #include <linux/bsg-lib.h> |
6733b39a JK |
32 | |
33 | #include <scsi/libiscsi.h> | |
ffce3e2e JK |
34 | #include <scsi/scsi_bsg_iscsi.h> |
35 | #include <scsi/scsi_netlink.h> | |
6733b39a JK |
36 | #include <scsi/scsi_transport_iscsi.h> |
37 | #include <scsi/scsi_transport.h> | |
38 | #include <scsi/scsi_cmnd.h> | |
39 | #include <scsi/scsi_device.h> | |
40 | #include <scsi/scsi_host.h> | |
41 | #include <scsi/scsi.h> | |
42 | #include "be_main.h" | |
43 | #include "be_iscsi.h" | |
44 | #include "be_mgmt.h" | |
0a513dd8 | 45 | #include "be_cmds.h" |
6733b39a JK |
46 | |
47 | static unsigned int be_iopoll_budget = 10; | |
48 | static unsigned int be_max_phys_size = 64; | |
bfead3b2 | 49 | static unsigned int enable_msix = 1; |
6733b39a | 50 | |
6733b39a | 51 | MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR); |
76d15dbd | 52 | MODULE_VERSION(BUILD_STR); |
2f635883 | 53 | MODULE_AUTHOR("Emulex Corporation"); |
6733b39a JK |
54 | MODULE_LICENSE("GPL"); |
55 | module_param(be_iopoll_budget, int, 0); | |
56 | module_param(enable_msix, int, 0); | |
57 | module_param(be_max_phys_size, uint, S_IRUGO); | |
99bc5d55 JSJ |
58 | MODULE_PARM_DESC(be_max_phys_size, |
59 | "Maximum Size (In Kilobytes) of physically contiguous " | |
60 | "memory that can be allocated. Range is 16 - 128"); | |
61 | ||
62 | #define beiscsi_disp_param(_name)\ | |
63 | ssize_t \ | |
64 | beiscsi_##_name##_disp(struct device *dev,\ | |
65 | struct device_attribute *attrib, char *buf) \ | |
66 | { \ | |
67 | struct Scsi_Host *shost = class_to_shost(dev);\ | |
68 | struct beiscsi_hba *phba = iscsi_host_priv(shost); \ | |
69 | uint32_t param_val = 0; \ | |
70 | param_val = phba->attr_##_name;\ | |
71 | return snprintf(buf, PAGE_SIZE, "%d\n",\ | |
72 | phba->attr_##_name);\ | |
73 | } | |
74 | ||
75 | #define beiscsi_change_param(_name, _minval, _maxval, _defaval)\ | |
76 | int \ | |
77 | beiscsi_##_name##_change(struct beiscsi_hba *phba, uint32_t val)\ | |
78 | {\ | |
79 | if (val >= _minval && val <= _maxval) {\ | |
80 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\ | |
81 | "BA_%d : beiscsi_"#_name" updated "\ | |
82 | "from 0x%x ==> 0x%x\n",\ | |
83 | phba->attr_##_name, val); \ | |
84 | phba->attr_##_name = val;\ | |
85 | return 0;\ | |
86 | } \ | |
87 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, \ | |
88 | "BA_%d beiscsi_"#_name" attribute "\ | |
89 | "cannot be updated to 0x%x, "\ | |
90 | "range allowed is ["#_minval" - "#_maxval"]\n", val);\ | |
91 | return -EINVAL;\ | |
92 | } | |
93 | ||
94 | #define beiscsi_store_param(_name) \ | |
95 | ssize_t \ | |
96 | beiscsi_##_name##_store(struct device *dev,\ | |
97 | struct device_attribute *attr, const char *buf,\ | |
98 | size_t count) \ | |
99 | { \ | |
100 | struct Scsi_Host *shost = class_to_shost(dev);\ | |
101 | struct beiscsi_hba *phba = iscsi_host_priv(shost);\ | |
102 | uint32_t param_val = 0;\ | |
103 | if (!isdigit(buf[0]))\ | |
104 | return -EINVAL;\ | |
105 | if (sscanf(buf, "%i", ¶m_val) != 1)\ | |
106 | return -EINVAL;\ | |
107 | if (beiscsi_##_name##_change(phba, param_val) == 0) \ | |
108 | return strlen(buf);\ | |
109 | else \ | |
110 | return -EINVAL;\ | |
111 | } | |
112 | ||
113 | #define beiscsi_init_param(_name, _minval, _maxval, _defval) \ | |
114 | int \ | |
115 | beiscsi_##_name##_init(struct beiscsi_hba *phba, uint32_t val) \ | |
116 | { \ | |
117 | if (val >= _minval && val <= _maxval) {\ | |
118 | phba->attr_##_name = val;\ | |
119 | return 0;\ | |
120 | } \ | |
121 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\ | |
122 | "BA_%d beiscsi_"#_name" attribute " \ | |
123 | "cannot be updated to 0x%x, "\ | |
124 | "range allowed is ["#_minval" - "#_maxval"]\n", val);\ | |
125 | phba->attr_##_name = _defval;\ | |
126 | return -EINVAL;\ | |
127 | } | |
128 | ||
129 | #define BEISCSI_RW_ATTR(_name, _minval, _maxval, _defval, _descp) \ | |
130 | static uint beiscsi_##_name = _defval;\ | |
131 | module_param(beiscsi_##_name, uint, S_IRUGO);\ | |
132 | MODULE_PARM_DESC(beiscsi_##_name, _descp);\ | |
133 | beiscsi_disp_param(_name)\ | |
134 | beiscsi_change_param(_name, _minval, _maxval, _defval)\ | |
135 | beiscsi_store_param(_name)\ | |
136 | beiscsi_init_param(_name, _minval, _maxval, _defval)\ | |
137 | DEVICE_ATTR(beiscsi_##_name, S_IRUGO | S_IWUSR,\ | |
138 | beiscsi_##_name##_disp, beiscsi_##_name##_store) | |
139 | ||
140 | /* | |
141 | * When new log level added update the | |
142 | * the MAX allowed value for log_enable | |
143 | */ | |
144 | BEISCSI_RW_ATTR(log_enable, 0x00, | |
145 | 0xFF, 0x00, "Enable logging Bit Mask\n" | |
146 | "\t\t\t\tInitialization Events : 0x01\n" | |
147 | "\t\t\t\tMailbox Events : 0x02\n" | |
148 | "\t\t\t\tMiscellaneous Events : 0x04\n" | |
149 | "\t\t\t\tError Handling : 0x08\n" | |
150 | "\t\t\t\tIO Path Events : 0x10\n" | |
afb96058 JK |
151 | "\t\t\t\tConfiguration Path : 0x20\n" |
152 | "\t\t\t\tiSCSI Protocol : 0x40\n"); | |
99bc5d55 | 153 | |
5cac7596 | 154 | DEVICE_ATTR(beiscsi_drvr_ver, S_IRUGO, beiscsi_drvr_ver_disp, NULL); |
26000db7 | 155 | DEVICE_ATTR(beiscsi_adapter_family, S_IRUGO, beiscsi_adap_family_disp, NULL); |
22661e25 | 156 | DEVICE_ATTR(beiscsi_fw_ver, S_IRUGO, beiscsi_fw_ver_disp, NULL); |
d3fea9af | 157 | DEVICE_ATTR(beiscsi_phys_port, S_IRUGO, beiscsi_phys_port_disp, NULL); |
6103c1f7 JK |
158 | DEVICE_ATTR(beiscsi_active_session_count, S_IRUGO, |
159 | beiscsi_active_session_disp, NULL); | |
160 | DEVICE_ATTR(beiscsi_free_session_count, S_IRUGO, | |
161 | beiscsi_free_session_disp, NULL); | |
99bc5d55 JSJ |
162 | struct device_attribute *beiscsi_attrs[] = { |
163 | &dev_attr_beiscsi_log_enable, | |
5cac7596 | 164 | &dev_attr_beiscsi_drvr_ver, |
26000db7 | 165 | &dev_attr_beiscsi_adapter_family, |
22661e25 | 166 | &dev_attr_beiscsi_fw_ver, |
6103c1f7 JK |
167 | &dev_attr_beiscsi_active_session_count, |
168 | &dev_attr_beiscsi_free_session_count, | |
d3fea9af | 169 | &dev_attr_beiscsi_phys_port, |
99bc5d55 JSJ |
170 | NULL, |
171 | }; | |
6733b39a | 172 | |
6763daae JSJ |
173 | static char const *cqe_desc[] = { |
174 | "RESERVED_DESC", | |
175 | "SOL_CMD_COMPLETE", | |
176 | "SOL_CMD_KILLED_DATA_DIGEST_ERR", | |
177 | "CXN_KILLED_PDU_SIZE_EXCEEDS_DSL", | |
178 | "CXN_KILLED_BURST_LEN_MISMATCH", | |
179 | "CXN_KILLED_AHS_RCVD", | |
180 | "CXN_KILLED_HDR_DIGEST_ERR", | |
181 | "CXN_KILLED_UNKNOWN_HDR", | |
182 | "CXN_KILLED_STALE_ITT_TTT_RCVD", | |
183 | "CXN_KILLED_INVALID_ITT_TTT_RCVD", | |
184 | "CXN_KILLED_RST_RCVD", | |
185 | "CXN_KILLED_TIMED_OUT", | |
186 | "CXN_KILLED_RST_SENT", | |
187 | "CXN_KILLED_FIN_RCVD", | |
188 | "CXN_KILLED_BAD_UNSOL_PDU_RCVD", | |
189 | "CXN_KILLED_BAD_WRB_INDEX_ERROR", | |
190 | "CXN_KILLED_OVER_RUN_RESIDUAL", | |
191 | "CXN_KILLED_UNDER_RUN_RESIDUAL", | |
192 | "CMD_KILLED_INVALID_STATSN_RCVD", | |
193 | "CMD_KILLED_INVALID_R2T_RCVD", | |
194 | "CMD_CXN_KILLED_LUN_INVALID", | |
195 | "CMD_CXN_KILLED_ICD_INVALID", | |
196 | "CMD_CXN_KILLED_ITT_INVALID", | |
197 | "CMD_CXN_KILLED_SEQ_OUTOFORDER", | |
198 | "CMD_CXN_KILLED_INVALID_DATASN_RCVD", | |
199 | "CXN_INVALIDATE_NOTIFY", | |
200 | "CXN_INVALIDATE_INDEX_NOTIFY", | |
201 | "CMD_INVALIDATED_NOTIFY", | |
202 | "UNSOL_HDR_NOTIFY", | |
203 | "UNSOL_DATA_NOTIFY", | |
204 | "UNSOL_DATA_DIGEST_ERROR_NOTIFY", | |
205 | "DRIVERMSG_NOTIFY", | |
206 | "CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN", | |
207 | "SOL_CMD_KILLED_DIF_ERR", | |
208 | "CXN_KILLED_SYN_RCVD", | |
209 | "CXN_KILLED_IMM_DATA_RCVD" | |
210 | }; | |
211 | ||
6733b39a JK |
212 | static int beiscsi_slave_configure(struct scsi_device *sdev) |
213 | { | |
214 | blk_queue_max_segment_size(sdev->request_queue, 65536); | |
215 | return 0; | |
216 | } | |
217 | ||
4183122d JK |
218 | static int beiscsi_eh_abort(struct scsi_cmnd *sc) |
219 | { | |
220 | struct iscsi_cls_session *cls_session; | |
221 | struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr; | |
222 | struct beiscsi_io_task *aborted_io_task; | |
223 | struct iscsi_conn *conn; | |
224 | struct beiscsi_conn *beiscsi_conn; | |
225 | struct beiscsi_hba *phba; | |
226 | struct iscsi_session *session; | |
227 | struct invalidate_command_table *inv_tbl; | |
3cbb7a74 | 228 | struct be_dma_mem nonemb_cmd; |
4183122d | 229 | unsigned int cid, tag, num_invalidate; |
1957aa7f | 230 | int rc; |
4183122d JK |
231 | |
232 | cls_session = starget_to_session(scsi_target(sc->device)); | |
233 | session = cls_session->dd_data; | |
234 | ||
659743b0 | 235 | spin_lock_bh(&session->frwd_lock); |
4183122d JK |
236 | if (!aborted_task || !aborted_task->sc) { |
237 | /* we raced */ | |
659743b0 | 238 | spin_unlock_bh(&session->frwd_lock); |
4183122d JK |
239 | return SUCCESS; |
240 | } | |
241 | ||
242 | aborted_io_task = aborted_task->dd_data; | |
243 | if (!aborted_io_task->scsi_cmnd) { | |
244 | /* raced or invalid command */ | |
659743b0 | 245 | spin_unlock_bh(&session->frwd_lock); |
4183122d JK |
246 | return SUCCESS; |
247 | } | |
659743b0 | 248 | spin_unlock_bh(&session->frwd_lock); |
7626c06b JK |
249 | /* Invalidate WRB Posted for this Task */ |
250 | AMAP_SET_BITS(struct amap_iscsi_wrb, invld, | |
251 | aborted_io_task->pwrb_handle->pwrb, | |
252 | 1); | |
253 | ||
4183122d JK |
254 | conn = aborted_task->conn; |
255 | beiscsi_conn = conn->dd_data; | |
256 | phba = beiscsi_conn->phba; | |
257 | ||
258 | /* invalidate iocb */ | |
259 | cid = beiscsi_conn->beiscsi_conn_cid; | |
260 | inv_tbl = phba->inv_tbl; | |
261 | memset(inv_tbl, 0x0, sizeof(*inv_tbl)); | |
262 | inv_tbl->cid = cid; | |
263 | inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index; | |
264 | num_invalidate = 1; | |
3cbb7a74 JK |
265 | nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev, |
266 | sizeof(struct invalidate_commands_params_in), | |
267 | &nonemb_cmd.dma); | |
268 | if (nonemb_cmd.va == NULL) { | |
99bc5d55 JSJ |
269 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH, |
270 | "BM_%d : Failed to allocate memory for" | |
271 | "mgmt_invalidate_icds\n"); | |
3cbb7a74 JK |
272 | return FAILED; |
273 | } | |
274 | nonemb_cmd.size = sizeof(struct invalidate_commands_params_in); | |
275 | ||
276 | tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate, | |
277 | cid, &nonemb_cmd); | |
4183122d | 278 | if (!tag) { |
99bc5d55 JSJ |
279 | beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH, |
280 | "BM_%d : mgmt_invalidate_icds could not be" | |
281 | "submitted\n"); | |
3cbb7a74 JK |
282 | pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, |
283 | nonemb_cmd.va, nonemb_cmd.dma); | |
284 | ||
4183122d | 285 | return FAILED; |
4183122d | 286 | } |
e175defe | 287 | |
1957aa7f JK |
288 | rc = beiscsi_mccq_compl(phba, tag, NULL, &nonemb_cmd); |
289 | if (rc != -EBUSY) | |
290 | pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, | |
291 | nonemb_cmd.va, nonemb_cmd.dma); | |
292 | ||
4183122d JK |
293 | return iscsi_eh_abort(sc); |
294 | } | |
295 | ||
296 | static int beiscsi_eh_device_reset(struct scsi_cmnd *sc) | |
297 | { | |
298 | struct iscsi_task *abrt_task; | |
299 | struct beiscsi_io_task *abrt_io_task; | |
300 | struct iscsi_conn *conn; | |
301 | struct beiscsi_conn *beiscsi_conn; | |
302 | struct beiscsi_hba *phba; | |
303 | struct iscsi_session *session; | |
304 | struct iscsi_cls_session *cls_session; | |
305 | struct invalidate_command_table *inv_tbl; | |
3cbb7a74 | 306 | struct be_dma_mem nonemb_cmd; |
4183122d | 307 | unsigned int cid, tag, i, num_invalidate; |
1957aa7f | 308 | int rc; |
4183122d JK |
309 | |
310 | /* invalidate iocbs */ | |
311 | cls_session = starget_to_session(scsi_target(sc->device)); | |
312 | session = cls_session->dd_data; | |
659743b0 | 313 | spin_lock_bh(&session->frwd_lock); |
db7f7709 | 314 | if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) { |
659743b0 | 315 | spin_unlock_bh(&session->frwd_lock); |
db7f7709 JK |
316 | return FAILED; |
317 | } | |
4183122d JK |
318 | conn = session->leadconn; |
319 | beiscsi_conn = conn->dd_data; | |
320 | phba = beiscsi_conn->phba; | |
321 | cid = beiscsi_conn->beiscsi_conn_cid; | |
322 | inv_tbl = phba->inv_tbl; | |
323 | memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN); | |
324 | num_invalidate = 0; | |
325 | for (i = 0; i < conn->session->cmds_max; i++) { | |
326 | abrt_task = conn->session->cmds[i]; | |
327 | abrt_io_task = abrt_task->dd_data; | |
328 | if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE) | |
329 | continue; | |
330 | ||
126e964a | 331 | if (sc->device->lun != abrt_task->sc->device->lun) |
4183122d JK |
332 | continue; |
333 | ||
7626c06b JK |
334 | /* Invalidate WRB Posted for this Task */ |
335 | AMAP_SET_BITS(struct amap_iscsi_wrb, invld, | |
336 | abrt_io_task->pwrb_handle->pwrb, | |
337 | 1); | |
338 | ||
4183122d JK |
339 | inv_tbl->cid = cid; |
340 | inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index; | |
341 | num_invalidate++; | |
342 | inv_tbl++; | |
343 | } | |
659743b0 | 344 | spin_unlock_bh(&session->frwd_lock); |
4183122d JK |
345 | inv_tbl = phba->inv_tbl; |
346 | ||
3cbb7a74 JK |
347 | nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev, |
348 | sizeof(struct invalidate_commands_params_in), | |
349 | &nonemb_cmd.dma); | |
350 | if (nonemb_cmd.va == NULL) { | |
99bc5d55 JSJ |
351 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH, |
352 | "BM_%d : Failed to allocate memory for" | |
353 | "mgmt_invalidate_icds\n"); | |
3cbb7a74 JK |
354 | return FAILED; |
355 | } | |
356 | nonemb_cmd.size = sizeof(struct invalidate_commands_params_in); | |
357 | memset(nonemb_cmd.va, 0, nonemb_cmd.size); | |
358 | tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate, | |
359 | cid, &nonemb_cmd); | |
4183122d | 360 | if (!tag) { |
99bc5d55 JSJ |
361 | beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH, |
362 | "BM_%d : mgmt_invalidate_icds could not be" | |
363 | " submitted\n"); | |
3cbb7a74 JK |
364 | pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, |
365 | nonemb_cmd.va, nonemb_cmd.dma); | |
4183122d | 366 | return FAILED; |
4183122d | 367 | } |
e175defe | 368 | |
1957aa7f JK |
369 | rc = beiscsi_mccq_compl(phba, tag, NULL, &nonemb_cmd); |
370 | if (rc != -EBUSY) | |
371 | pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, | |
372 | nonemb_cmd.va, nonemb_cmd.dma); | |
4183122d | 373 | return iscsi_eh_device_reset(sc); |
4183122d JK |
374 | } |
375 | ||
c7acc5b8 JK |
376 | static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf) |
377 | { | |
378 | struct beiscsi_hba *phba = data; | |
f457a46f MC |
379 | struct mgmt_session_info *boot_sess = &phba->boot_sess; |
380 | struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0]; | |
c7acc5b8 JK |
381 | char *str = buf; |
382 | int rc; | |
383 | ||
384 | switch (type) { | |
385 | case ISCSI_BOOT_TGT_NAME: | |
386 | rc = sprintf(buf, "%.*s\n", | |
f457a46f MC |
387 | (int)strlen(boot_sess->target_name), |
388 | (char *)&boot_sess->target_name); | |
c7acc5b8 JK |
389 | break; |
390 | case ISCSI_BOOT_TGT_IP_ADDR: | |
f457a46f | 391 | if (boot_conn->dest_ipaddr.ip_type == 0x1) |
c7acc5b8 | 392 | rc = sprintf(buf, "%pI4\n", |
0e43895e | 393 | (char *)&boot_conn->dest_ipaddr.addr); |
c7acc5b8 JK |
394 | else |
395 | rc = sprintf(str, "%pI6\n", | |
0e43895e | 396 | (char *)&boot_conn->dest_ipaddr.addr); |
c7acc5b8 JK |
397 | break; |
398 | case ISCSI_BOOT_TGT_PORT: | |
f457a46f | 399 | rc = sprintf(str, "%d\n", boot_conn->dest_port); |
c7acc5b8 JK |
400 | break; |
401 | ||
402 | case ISCSI_BOOT_TGT_CHAP_NAME: | |
403 | rc = sprintf(str, "%.*s\n", | |
f457a46f MC |
404 | boot_conn->negotiated_login_options.auth_data.chap. |
405 | target_chap_name_length, | |
406 | (char *)&boot_conn->negotiated_login_options. | |
407 | auth_data.chap.target_chap_name); | |
c7acc5b8 JK |
408 | break; |
409 | case ISCSI_BOOT_TGT_CHAP_SECRET: | |
410 | rc = sprintf(str, "%.*s\n", | |
f457a46f MC |
411 | boot_conn->negotiated_login_options.auth_data.chap. |
412 | target_secret_length, | |
413 | (char *)&boot_conn->negotiated_login_options. | |
414 | auth_data.chap.target_secret); | |
c7acc5b8 JK |
415 | break; |
416 | case ISCSI_BOOT_TGT_REV_CHAP_NAME: | |
417 | rc = sprintf(str, "%.*s\n", | |
f457a46f MC |
418 | boot_conn->negotiated_login_options.auth_data.chap. |
419 | intr_chap_name_length, | |
420 | (char *)&boot_conn->negotiated_login_options. | |
421 | auth_data.chap.intr_chap_name); | |
c7acc5b8 JK |
422 | break; |
423 | case ISCSI_BOOT_TGT_REV_CHAP_SECRET: | |
f457a46f MC |
424 | rc = sprintf(str, "%.*s\n", |
425 | boot_conn->negotiated_login_options.auth_data.chap. | |
426 | intr_secret_length, | |
427 | (char *)&boot_conn->negotiated_login_options. | |
428 | auth_data.chap.intr_secret); | |
c7acc5b8 JK |
429 | break; |
430 | case ISCSI_BOOT_TGT_FLAGS: | |
f457a46f | 431 | rc = sprintf(str, "2\n"); |
c7acc5b8 JK |
432 | break; |
433 | case ISCSI_BOOT_TGT_NIC_ASSOC: | |
f457a46f | 434 | rc = sprintf(str, "0\n"); |
c7acc5b8 JK |
435 | break; |
436 | default: | |
437 | rc = -ENOSYS; | |
438 | break; | |
439 | } | |
440 | return rc; | |
441 | } | |
442 | ||
443 | static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf) | |
444 | { | |
445 | struct beiscsi_hba *phba = data; | |
446 | char *str = buf; | |
447 | int rc; | |
448 | ||
449 | switch (type) { | |
450 | case ISCSI_BOOT_INI_INITIATOR_NAME: | |
451 | rc = sprintf(str, "%s\n", phba->boot_sess.initiator_iscsiname); | |
452 | break; | |
453 | default: | |
454 | rc = -ENOSYS; | |
455 | break; | |
456 | } | |
457 | return rc; | |
458 | } | |
459 | ||
460 | static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf) | |
461 | { | |
462 | struct beiscsi_hba *phba = data; | |
463 | char *str = buf; | |
464 | int rc; | |
465 | ||
466 | switch (type) { | |
467 | case ISCSI_BOOT_ETH_FLAGS: | |
f457a46f | 468 | rc = sprintf(str, "2\n"); |
c7acc5b8 JK |
469 | break; |
470 | case ISCSI_BOOT_ETH_INDEX: | |
f457a46f | 471 | rc = sprintf(str, "0\n"); |
c7acc5b8 JK |
472 | break; |
473 | case ISCSI_BOOT_ETH_MAC: | |
0e43895e MC |
474 | rc = beiscsi_get_macaddr(str, phba); |
475 | break; | |
c7acc5b8 JK |
476 | default: |
477 | rc = -ENOSYS; | |
478 | break; | |
479 | } | |
480 | return rc; | |
481 | } | |
482 | ||
483 | ||
587a1f16 | 484 | static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type) |
c7acc5b8 | 485 | { |
587a1f16 | 486 | umode_t rc; |
c7acc5b8 JK |
487 | |
488 | switch (type) { | |
489 | case ISCSI_BOOT_TGT_NAME: | |
490 | case ISCSI_BOOT_TGT_IP_ADDR: | |
491 | case ISCSI_BOOT_TGT_PORT: | |
492 | case ISCSI_BOOT_TGT_CHAP_NAME: | |
493 | case ISCSI_BOOT_TGT_CHAP_SECRET: | |
494 | case ISCSI_BOOT_TGT_REV_CHAP_NAME: | |
495 | case ISCSI_BOOT_TGT_REV_CHAP_SECRET: | |
496 | case ISCSI_BOOT_TGT_NIC_ASSOC: | |
497 | case ISCSI_BOOT_TGT_FLAGS: | |
498 | rc = S_IRUGO; | |
499 | break; | |
500 | default: | |
501 | rc = 0; | |
502 | break; | |
503 | } | |
504 | return rc; | |
505 | } | |
506 | ||
587a1f16 | 507 | static umode_t beiscsi_ini_get_attr_visibility(void *data, int type) |
c7acc5b8 | 508 | { |
587a1f16 | 509 | umode_t rc; |
c7acc5b8 JK |
510 | |
511 | switch (type) { | |
512 | case ISCSI_BOOT_INI_INITIATOR_NAME: | |
513 | rc = S_IRUGO; | |
514 | break; | |
515 | default: | |
516 | rc = 0; | |
517 | break; | |
518 | } | |
519 | return rc; | |
520 | } | |
521 | ||
522 | ||
587a1f16 | 523 | static umode_t beiscsi_eth_get_attr_visibility(void *data, int type) |
c7acc5b8 | 524 | { |
587a1f16 | 525 | umode_t rc; |
c7acc5b8 JK |
526 | |
527 | switch (type) { | |
528 | case ISCSI_BOOT_ETH_FLAGS: | |
529 | case ISCSI_BOOT_ETH_MAC: | |
530 | case ISCSI_BOOT_ETH_INDEX: | |
531 | rc = S_IRUGO; | |
532 | break; | |
533 | default: | |
534 | rc = 0; | |
535 | break; | |
536 | } | |
537 | return rc; | |
538 | } | |
539 | ||
bfead3b2 | 540 | /*------------------- PCI Driver operations and data ----------------- */ |
9baa3c34 | 541 | static const struct pci_device_id beiscsi_pci_id_table[] = { |
bfead3b2 | 542 | { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) }, |
f98c96b0 | 543 | { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) }, |
bfead3b2 JK |
544 | { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) }, |
545 | { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) }, | |
546 | { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) }, | |
139a1b1e | 547 | { PCI_DEVICE(ELX_VENDOR_ID, OC_SKH_ID1) }, |
bfead3b2 JK |
548 | { 0 } |
549 | }; | |
550 | MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table); | |
551 | ||
99bc5d55 | 552 | |
6733b39a JK |
553 | static struct scsi_host_template beiscsi_sht = { |
554 | .module = THIS_MODULE, | |
2f635883 | 555 | .name = "Emulex 10Gbe open-iscsi Initiator Driver", |
6733b39a JK |
556 | .proc_name = DRV_NAME, |
557 | .queuecommand = iscsi_queuecommand, | |
db5ed4df | 558 | .change_queue_depth = scsi_change_queue_depth, |
6733b39a JK |
559 | .slave_configure = beiscsi_slave_configure, |
560 | .target_alloc = iscsi_target_alloc, | |
4183122d JK |
561 | .eh_abort_handler = beiscsi_eh_abort, |
562 | .eh_device_reset_handler = beiscsi_eh_device_reset, | |
309ce156 | 563 | .eh_target_reset_handler = iscsi_eh_session_reset, |
99bc5d55 | 564 | .shost_attrs = beiscsi_attrs, |
6733b39a JK |
565 | .sg_tablesize = BEISCSI_SGLIST_ELEMENTS, |
566 | .can_queue = BE2_IO_DEPTH, | |
567 | .this_id = -1, | |
568 | .max_sectors = BEISCSI_MAX_SECTORS, | |
569 | .cmd_per_lun = BEISCSI_CMD_PER_LUN, | |
570 | .use_clustering = ENABLE_CLUSTERING, | |
ffce3e2e | 571 | .vendor_id = SCSI_NL_VID_TYPE_PCI | BE_VENDOR_ID, |
c40ecc12 | 572 | .track_queue_depth = 1, |
6733b39a | 573 | }; |
6733b39a | 574 | |
bfead3b2 | 575 | static struct scsi_transport_template *beiscsi_scsi_transport; |
6733b39a JK |
576 | |
577 | static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev) | |
578 | { | |
579 | struct beiscsi_hba *phba; | |
580 | struct Scsi_Host *shost; | |
581 | ||
582 | shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0); | |
583 | if (!shost) { | |
99bc5d55 JSJ |
584 | dev_err(&pcidev->dev, |
585 | "beiscsi_hba_alloc - iscsi_host_alloc failed\n"); | |
6733b39a JK |
586 | return NULL; |
587 | } | |
588 | shost->dma_boundary = pcidev->dma_mask; | |
589 | shost->max_id = BE2_MAX_SESSIONS; | |
590 | shost->max_channel = 0; | |
591 | shost->max_cmd_len = BEISCSI_MAX_CMD_LEN; | |
592 | shost->max_lun = BEISCSI_NUM_MAX_LUN; | |
593 | shost->transportt = beiscsi_scsi_transport; | |
6733b39a JK |
594 | phba = iscsi_host_priv(shost); |
595 | memset(phba, 0, sizeof(*phba)); | |
596 | phba->shost = shost; | |
597 | phba->pcidev = pci_dev_get(pcidev); | |
2807afb7 | 598 | pci_set_drvdata(pcidev, phba); |
0e43895e | 599 | phba->interface_handle = 0xFFFFFFFF; |
6733b39a | 600 | |
6733b39a | 601 | return phba; |
6733b39a JK |
602 | } |
603 | ||
604 | static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba) | |
605 | { | |
606 | if (phba->csr_va) { | |
607 | iounmap(phba->csr_va); | |
608 | phba->csr_va = NULL; | |
609 | } | |
610 | if (phba->db_va) { | |
611 | iounmap(phba->db_va); | |
612 | phba->db_va = NULL; | |
613 | } | |
614 | if (phba->pci_va) { | |
615 | iounmap(phba->pci_va); | |
616 | phba->pci_va = NULL; | |
617 | } | |
618 | } | |
619 | ||
620 | static int beiscsi_map_pci_bars(struct beiscsi_hba *phba, | |
621 | struct pci_dev *pcidev) | |
622 | { | |
623 | u8 __iomem *addr; | |
f98c96b0 | 624 | int pcicfg_reg; |
6733b39a JK |
625 | |
626 | addr = ioremap_nocache(pci_resource_start(pcidev, 2), | |
627 | pci_resource_len(pcidev, 2)); | |
628 | if (addr == NULL) | |
629 | return -ENOMEM; | |
630 | phba->ctrl.csr = addr; | |
631 | phba->csr_va = addr; | |
632 | phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2); | |
633 | ||
634 | addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024); | |
635 | if (addr == NULL) | |
636 | goto pci_map_err; | |
637 | phba->ctrl.db = addr; | |
638 | phba->db_va = addr; | |
639 | phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4); | |
640 | ||
f98c96b0 JK |
641 | if (phba->generation == BE_GEN2) |
642 | pcicfg_reg = 1; | |
643 | else | |
644 | pcicfg_reg = 0; | |
645 | ||
646 | addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg), | |
647 | pci_resource_len(pcidev, pcicfg_reg)); | |
648 | ||
6733b39a JK |
649 | if (addr == NULL) |
650 | goto pci_map_err; | |
651 | phba->ctrl.pcicfg = addr; | |
652 | phba->pci_va = addr; | |
f98c96b0 | 653 | phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg); |
6733b39a JK |
654 | return 0; |
655 | ||
656 | pci_map_err: | |
657 | beiscsi_unmap_pci_function(phba); | |
658 | return -ENOMEM; | |
659 | } | |
660 | ||
661 | static int beiscsi_enable_pci(struct pci_dev *pcidev) | |
662 | { | |
663 | int ret; | |
664 | ||
665 | ret = pci_enable_device(pcidev); | |
666 | if (ret) { | |
99bc5d55 JSJ |
667 | dev_err(&pcidev->dev, |
668 | "beiscsi_enable_pci - enable device failed\n"); | |
6733b39a JK |
669 | return ret; |
670 | } | |
671 | ||
bfead3b2 | 672 | pci_set_master(pcidev); |
6c57625b JK |
673 | ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(64)); |
674 | if (ret) { | |
675 | ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32)); | |
676 | if (ret) { | |
677 | dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n"); | |
678 | pci_disable_device(pcidev); | |
679 | return ret; | |
680 | } else { | |
681 | ret = pci_set_consistent_dma_mask(pcidev, | |
682 | DMA_BIT_MASK(32)); | |
683 | } | |
684 | } else { | |
685 | ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64)); | |
6733b39a JK |
686 | if (ret) { |
687 | dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n"); | |
688 | pci_disable_device(pcidev); | |
689 | return ret; | |
690 | } | |
691 | } | |
692 | return 0; | |
693 | } | |
694 | ||
695 | static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev) | |
696 | { | |
697 | struct be_ctrl_info *ctrl = &phba->ctrl; | |
698 | struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced; | |
699 | struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem; | |
700 | int status = 0; | |
701 | ||
702 | ctrl->pdev = pdev; | |
703 | status = beiscsi_map_pci_bars(phba, pdev); | |
704 | if (status) | |
705 | return status; | |
6733b39a JK |
706 | mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16; |
707 | mbox_mem_alloc->va = pci_alloc_consistent(pdev, | |
708 | mbox_mem_alloc->size, | |
709 | &mbox_mem_alloc->dma); | |
710 | if (!mbox_mem_alloc->va) { | |
711 | beiscsi_unmap_pci_function(phba); | |
a49e06d5 | 712 | return -ENOMEM; |
6733b39a JK |
713 | } |
714 | ||
715 | mbox_mem_align->size = sizeof(struct be_mcc_mailbox); | |
716 | mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16); | |
717 | mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16); | |
718 | memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox)); | |
719 | spin_lock_init(&ctrl->mbox_lock); | |
bfead3b2 JK |
720 | spin_lock_init(&phba->ctrl.mcc_lock); |
721 | spin_lock_init(&phba->ctrl.mcc_cq_lock); | |
722 | ||
6733b39a JK |
723 | return status; |
724 | } | |
725 | ||
843ae752 JK |
726 | /** |
727 | * beiscsi_get_params()- Set the config paramters | |
728 | * @phba: ptr device priv structure | |
729 | **/ | |
6733b39a JK |
730 | static void beiscsi_get_params(struct beiscsi_hba *phba) |
731 | { | |
843ae752 JK |
732 | uint32_t total_cid_count = 0; |
733 | uint32_t total_icd_count = 0; | |
734 | uint8_t ulp_num = 0; | |
735 | ||
736 | total_cid_count = BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP0) + | |
737 | BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP1); | |
738 | ||
cf987b79 JK |
739 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { |
740 | uint32_t align_mask = 0; | |
741 | uint32_t icd_post_per_page = 0; | |
742 | uint32_t icd_count_unavailable = 0; | |
743 | uint32_t icd_start = 0, icd_count = 0; | |
744 | uint32_t icd_start_align = 0, icd_count_align = 0; | |
745 | ||
843ae752 | 746 | if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { |
cf987b79 JK |
747 | icd_start = phba->fw_config.iscsi_icd_start[ulp_num]; |
748 | icd_count = phba->fw_config.iscsi_icd_count[ulp_num]; | |
749 | ||
750 | /* Get ICD count that can be posted on each page */ | |
751 | icd_post_per_page = (PAGE_SIZE / (BE2_SGE * | |
752 | sizeof(struct iscsi_sge))); | |
753 | align_mask = (icd_post_per_page - 1); | |
754 | ||
755 | /* Check if icd_start is aligned ICD per page posting */ | |
756 | if (icd_start % icd_post_per_page) { | |
757 | icd_start_align = ((icd_start + | |
758 | icd_post_per_page) & | |
759 | ~(align_mask)); | |
760 | phba->fw_config. | |
761 | iscsi_icd_start[ulp_num] = | |
762 | icd_start_align; | |
763 | } | |
764 | ||
765 | icd_count_align = (icd_count & ~align_mask); | |
766 | ||
767 | /* ICD discarded in the process of alignment */ | |
768 | if (icd_start_align) | |
769 | icd_count_unavailable = ((icd_start_align - | |
770 | icd_start) + | |
771 | (icd_count - | |
772 | icd_count_align)); | |
773 | ||
774 | /* Updated ICD count available */ | |
775 | phba->fw_config.iscsi_icd_count[ulp_num] = (icd_count - | |
776 | icd_count_unavailable); | |
777 | ||
778 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, | |
779 | "BM_%d : Aligned ICD values\n" | |
780 | "\t ICD Start : %d\n" | |
781 | "\t ICD Count : %d\n" | |
782 | "\t ICD Discarded : %d\n", | |
783 | phba->fw_config. | |
784 | iscsi_icd_start[ulp_num], | |
785 | phba->fw_config. | |
786 | iscsi_icd_count[ulp_num], | |
787 | icd_count_unavailable); | |
843ae752 JK |
788 | break; |
789 | } | |
cf987b79 | 790 | } |
843ae752 | 791 | |
cf987b79 | 792 | total_icd_count = phba->fw_config.iscsi_icd_count[ulp_num]; |
843ae752 JK |
793 | phba->params.ios_per_ctrl = (total_icd_count - |
794 | (total_cid_count + | |
795 | BE2_TMFS + BE2_NOPOUT_REQ)); | |
796 | phba->params.cxns_per_ctrl = total_cid_count; | |
797 | phba->params.asyncpdus_per_ctrl = total_cid_count; | |
798 | phba->params.icds_per_ctrl = total_icd_count; | |
6733b39a JK |
799 | phba->params.num_sge_per_io = BE2_SGE; |
800 | phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ; | |
801 | phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ; | |
802 | phba->params.eq_timer = 64; | |
843ae752 JK |
803 | phba->params.num_eq_entries = 1024; |
804 | phba->params.num_cq_entries = 1024; | |
6733b39a JK |
805 | phba->params.wrbs_per_cxn = 256; |
806 | } | |
807 | ||
808 | static void hwi_ring_eq_db(struct beiscsi_hba *phba, | |
809 | unsigned int id, unsigned int clr_interrupt, | |
810 | unsigned int num_processed, | |
811 | unsigned char rearm, unsigned char event) | |
812 | { | |
813 | u32 val = 0; | |
e08b3c8b | 814 | |
6733b39a JK |
815 | if (rearm) |
816 | val |= 1 << DB_EQ_REARM_SHIFT; | |
817 | if (clr_interrupt) | |
818 | val |= 1 << DB_EQ_CLR_SHIFT; | |
819 | if (event) | |
820 | val |= 1 << DB_EQ_EVNT_SHIFT; | |
e08b3c8b | 821 | |
6733b39a | 822 | val |= num_processed << DB_EQ_NUM_POPPED_SHIFT; |
e08b3c8b JK |
823 | /* Setting lower order EQ_ID Bits */ |
824 | val |= (id & DB_EQ_RING_ID_LOW_MASK); | |
825 | ||
826 | /* Setting Higher order EQ_ID Bits */ | |
827 | val |= (((id >> DB_EQ_HIGH_FEILD_SHIFT) & | |
828 | DB_EQ_RING_ID_HIGH_MASK) | |
829 | << DB_EQ_HIGH_SET_SHIFT); | |
830 | ||
6733b39a JK |
831 | iowrite32(val, phba->db_va + DB_EQ_OFFSET); |
832 | } | |
833 | ||
bfead3b2 JK |
834 | /** |
835 | * be_isr_mcc - The isr routine of the driver. | |
836 | * @irq: Not used | |
837 | * @dev_id: Pointer to host adapter structure | |
838 | */ | |
839 | static irqreturn_t be_isr_mcc(int irq, void *dev_id) | |
840 | { | |
841 | struct beiscsi_hba *phba; | |
842 | struct be_eq_entry *eqe = NULL; | |
843 | struct be_queue_info *eq; | |
844 | struct be_queue_info *mcc; | |
845 | unsigned int num_eq_processed; | |
846 | struct be_eq_obj *pbe_eq; | |
847 | unsigned long flags; | |
848 | ||
849 | pbe_eq = dev_id; | |
850 | eq = &pbe_eq->q; | |
851 | phba = pbe_eq->phba; | |
852 | mcc = &phba->ctrl.mcc_obj.cq; | |
853 | eqe = queue_tail_node(eq); | |
bfead3b2 JK |
854 | |
855 | num_eq_processed = 0; | |
856 | ||
857 | while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] | |
858 | & EQE_VALID_MASK) { | |
859 | if (((eqe->dw[offsetof(struct amap_eq_entry, | |
860 | resource_id) / 32] & | |
861 | EQE_RESID_MASK) >> 16) == mcc->id) { | |
862 | spin_lock_irqsave(&phba->isr_lock, flags); | |
72fb46a9 | 863 | pbe_eq->todo_mcc_cq = true; |
bfead3b2 JK |
864 | spin_unlock_irqrestore(&phba->isr_lock, flags); |
865 | } | |
866 | AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); | |
867 | queue_tail_inc(eq); | |
868 | eqe = queue_tail_node(eq); | |
869 | num_eq_processed++; | |
870 | } | |
72fb46a9 JSJ |
871 | if (pbe_eq->todo_mcc_cq) |
872 | queue_work(phba->wq, &pbe_eq->work_cqs); | |
bfead3b2 JK |
873 | if (num_eq_processed) |
874 | hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1); | |
875 | ||
876 | return IRQ_HANDLED; | |
877 | } | |
878 | ||
879 | /** | |
880 | * be_isr_msix - The isr routine of the driver. | |
881 | * @irq: Not used | |
882 | * @dev_id: Pointer to host adapter structure | |
883 | */ | |
884 | static irqreturn_t be_isr_msix(int irq, void *dev_id) | |
885 | { | |
886 | struct beiscsi_hba *phba; | |
887 | struct be_eq_entry *eqe = NULL; | |
888 | struct be_queue_info *eq; | |
889 | struct be_queue_info *cq; | |
890 | unsigned int num_eq_processed; | |
891 | struct be_eq_obj *pbe_eq; | |
bfead3b2 JK |
892 | |
893 | pbe_eq = dev_id; | |
894 | eq = &pbe_eq->q; | |
895 | cq = pbe_eq->cq; | |
896 | eqe = queue_tail_node(eq); | |
bfead3b2 JK |
897 | |
898 | phba = pbe_eq->phba; | |
899 | num_eq_processed = 0; | |
89f8b33c JA |
900 | while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] |
901 | & EQE_VALID_MASK) { | |
902 | if (!blk_iopoll_sched_prep(&pbe_eq->iopoll)) | |
903 | blk_iopoll_sched(&pbe_eq->iopoll); | |
bfead3b2 | 904 | |
89f8b33c JA |
905 | AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); |
906 | queue_tail_inc(eq); | |
907 | eqe = queue_tail_node(eq); | |
908 | num_eq_processed++; | |
bfead3b2 | 909 | } |
72fb46a9 JSJ |
910 | |
911 | if (num_eq_processed) | |
912 | hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 0, 1); | |
913 | ||
914 | return IRQ_HANDLED; | |
bfead3b2 JK |
915 | } |
916 | ||
6733b39a JK |
917 | /** |
918 | * be_isr - The isr routine of the driver. | |
919 | * @irq: Not used | |
920 | * @dev_id: Pointer to host adapter structure | |
921 | */ | |
922 | static irqreturn_t be_isr(int irq, void *dev_id) | |
923 | { | |
924 | struct beiscsi_hba *phba; | |
925 | struct hwi_controller *phwi_ctrlr; | |
926 | struct hwi_context_memory *phwi_context; | |
927 | struct be_eq_entry *eqe = NULL; | |
928 | struct be_queue_info *eq; | |
bfead3b2 | 929 | struct be_queue_info *mcc; |
6733b39a | 930 | unsigned long flags, index; |
bfead3b2 | 931 | unsigned int num_mcceq_processed, num_ioeq_processed; |
6733b39a | 932 | struct be_ctrl_info *ctrl; |
bfead3b2 | 933 | struct be_eq_obj *pbe_eq; |
6733b39a JK |
934 | int isr; |
935 | ||
936 | phba = dev_id; | |
6eab04a8 | 937 | ctrl = &phba->ctrl; |
bfead3b2 JK |
938 | isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET + |
939 | (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE)); | |
940 | if (!isr) | |
941 | return IRQ_NONE; | |
6733b39a JK |
942 | |
943 | phwi_ctrlr = phba->phwi_ctrlr; | |
944 | phwi_context = phwi_ctrlr->phwi_ctxt; | |
bfead3b2 JK |
945 | pbe_eq = &phwi_context->be_eq[0]; |
946 | ||
947 | eq = &phwi_context->be_eq[0].q; | |
948 | mcc = &phba->ctrl.mcc_obj.cq; | |
6733b39a JK |
949 | index = 0; |
950 | eqe = queue_tail_node(eq); | |
6733b39a | 951 | |
bfead3b2 JK |
952 | num_ioeq_processed = 0; |
953 | num_mcceq_processed = 0; | |
89f8b33c JA |
954 | while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] |
955 | & EQE_VALID_MASK) { | |
956 | if (((eqe->dw[offsetof(struct amap_eq_entry, | |
957 | resource_id) / 32] & | |
958 | EQE_RESID_MASK) >> 16) == mcc->id) { | |
959 | spin_lock_irqsave(&phba->isr_lock, flags); | |
960 | pbe_eq->todo_mcc_cq = true; | |
961 | spin_unlock_irqrestore(&phba->isr_lock, flags); | |
962 | num_mcceq_processed++; | |
963 | } else { | |
964 | if (!blk_iopoll_sched_prep(&pbe_eq->iopoll)) | |
965 | blk_iopoll_sched(&pbe_eq->iopoll); | |
bfead3b2 | 966 | num_ioeq_processed++; |
6733b39a | 967 | } |
89f8b33c JA |
968 | AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); |
969 | queue_tail_inc(eq); | |
970 | eqe = queue_tail_node(eq); | |
971 | } | |
972 | if (num_ioeq_processed || num_mcceq_processed) { | |
973 | if (pbe_eq->todo_mcc_cq) | |
72fb46a9 | 974 | queue_work(phba->wq, &pbe_eq->work_cqs); |
6733b39a | 975 | |
89f8b33c | 976 | if ((num_mcceq_processed) && (!num_ioeq_processed)) |
bfead3b2 | 977 | hwi_ring_eq_db(phba, eq->id, 0, |
89f8b33c JA |
978 | (num_ioeq_processed + |
979 | num_mcceq_processed) , 1, 1); | |
980 | else | |
981 | hwi_ring_eq_db(phba, eq->id, 0, | |
982 | (num_ioeq_processed + | |
983 | num_mcceq_processed), 0, 1); | |
984 | ||
985 | return IRQ_HANDLED; | |
986 | } else | |
987 | return IRQ_NONE; | |
6733b39a JK |
988 | } |
989 | ||
990 | static int beiscsi_init_irqs(struct beiscsi_hba *phba) | |
991 | { | |
992 | struct pci_dev *pcidev = phba->pcidev; | |
bfead3b2 JK |
993 | struct hwi_controller *phwi_ctrlr; |
994 | struct hwi_context_memory *phwi_context; | |
4f5af07e | 995 | int ret, msix_vec, i, j; |
6733b39a | 996 | |
bfead3b2 JK |
997 | phwi_ctrlr = phba->phwi_ctrlr; |
998 | phwi_context = phwi_ctrlr->phwi_ctxt; | |
999 | ||
1000 | if (phba->msix_enabled) { | |
1001 | for (i = 0; i < phba->num_cpus; i++) { | |
8fcfb210 JK |
1002 | phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, |
1003 | GFP_KERNEL); | |
1004 | if (!phba->msi_name[i]) { | |
1005 | ret = -ENOMEM; | |
1006 | goto free_msix_irqs; | |
1007 | } | |
1008 | ||
1009 | sprintf(phba->msi_name[i], "beiscsi_%02x_%02x", | |
1010 | phba->shost->host_no, i); | |
bfead3b2 | 1011 | msix_vec = phba->msix_entries[i].vector; |
8fcfb210 JK |
1012 | ret = request_irq(msix_vec, be_isr_msix, 0, |
1013 | phba->msi_name[i], | |
bfead3b2 | 1014 | &phwi_context->be_eq[i]); |
4f5af07e | 1015 | if (ret) { |
99bc5d55 JSJ |
1016 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
1017 | "BM_%d : beiscsi_init_irqs-Failed to" | |
1018 | "register msix for i = %d\n", | |
1019 | i); | |
8fcfb210 | 1020 | kfree(phba->msi_name[i]); |
4f5af07e JK |
1021 | goto free_msix_irqs; |
1022 | } | |
bfead3b2 | 1023 | } |
8fcfb210 JK |
1024 | phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL); |
1025 | if (!phba->msi_name[i]) { | |
1026 | ret = -ENOMEM; | |
1027 | goto free_msix_irqs; | |
1028 | } | |
1029 | sprintf(phba->msi_name[i], "beiscsi_mcc_%02x", | |
1030 | phba->shost->host_no); | |
bfead3b2 | 1031 | msix_vec = phba->msix_entries[i].vector; |
8fcfb210 | 1032 | ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i], |
bfead3b2 | 1033 | &phwi_context->be_eq[i]); |
4f5af07e | 1034 | if (ret) { |
99bc5d55 JSJ |
1035 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT , |
1036 | "BM_%d : beiscsi_init_irqs-" | |
1037 | "Failed to register beiscsi_msix_mcc\n"); | |
8fcfb210 | 1038 | kfree(phba->msi_name[i]); |
4f5af07e JK |
1039 | goto free_msix_irqs; |
1040 | } | |
1041 | ||
bfead3b2 JK |
1042 | } else { |
1043 | ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED, | |
1044 | "beiscsi", phba); | |
1045 | if (ret) { | |
99bc5d55 JSJ |
1046 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
1047 | "BM_%d : beiscsi_init_irqs-" | |
1048 | "Failed to register irq\\n"); | |
bfead3b2 JK |
1049 | return ret; |
1050 | } | |
6733b39a JK |
1051 | } |
1052 | return 0; | |
4f5af07e | 1053 | free_msix_irqs: |
8fcfb210 JK |
1054 | for (j = i - 1; j >= 0; j--) { |
1055 | kfree(phba->msi_name[j]); | |
1056 | msix_vec = phba->msix_entries[j].vector; | |
4f5af07e | 1057 | free_irq(msix_vec, &phwi_context->be_eq[j]); |
8fcfb210 | 1058 | } |
4f5af07e | 1059 | return ret; |
6733b39a JK |
1060 | } |
1061 | ||
e08b3c8b | 1062 | void hwi_ring_cq_db(struct beiscsi_hba *phba, |
6733b39a JK |
1063 | unsigned int id, unsigned int num_processed, |
1064 | unsigned char rearm, unsigned char event) | |
1065 | { | |
1066 | u32 val = 0; | |
e08b3c8b | 1067 | |
6733b39a JK |
1068 | if (rearm) |
1069 | val |= 1 << DB_CQ_REARM_SHIFT; | |
e08b3c8b | 1070 | |
6733b39a | 1071 | val |= num_processed << DB_CQ_NUM_POPPED_SHIFT; |
e08b3c8b JK |
1072 | |
1073 | /* Setting lower order CQ_ID Bits */ | |
1074 | val |= (id & DB_CQ_RING_ID_LOW_MASK); | |
1075 | ||
1076 | /* Setting Higher order CQ_ID Bits */ | |
1077 | val |= (((id >> DB_CQ_HIGH_FEILD_SHIFT) & | |
1078 | DB_CQ_RING_ID_HIGH_MASK) | |
1079 | << DB_CQ_HIGH_SET_SHIFT); | |
1080 | ||
6733b39a JK |
1081 | iowrite32(val, phba->db_va + DB_CQ_OFFSET); |
1082 | } | |
1083 | ||
6733b39a JK |
1084 | static unsigned int |
1085 | beiscsi_process_async_pdu(struct beiscsi_conn *beiscsi_conn, | |
1086 | struct beiscsi_hba *phba, | |
6733b39a JK |
1087 | struct pdu_base *ppdu, |
1088 | unsigned long pdu_len, | |
1089 | void *pbuffer, unsigned long buf_len) | |
1090 | { | |
1091 | struct iscsi_conn *conn = beiscsi_conn->conn; | |
1092 | struct iscsi_session *session = conn->session; | |
bfead3b2 JK |
1093 | struct iscsi_task *task; |
1094 | struct beiscsi_io_task *io_task; | |
1095 | struct iscsi_hdr *login_hdr; | |
6733b39a JK |
1096 | |
1097 | switch (ppdu->dw[offsetof(struct amap_pdu_base, opcode) / 32] & | |
1098 | PDUBASE_OPCODE_MASK) { | |
1099 | case ISCSI_OP_NOOP_IN: | |
1100 | pbuffer = NULL; | |
1101 | buf_len = 0; | |
1102 | break; | |
1103 | case ISCSI_OP_ASYNC_EVENT: | |
1104 | break; | |
1105 | case ISCSI_OP_REJECT: | |
1106 | WARN_ON(!pbuffer); | |
1107 | WARN_ON(!(buf_len == 48)); | |
99bc5d55 JSJ |
1108 | beiscsi_log(phba, KERN_ERR, |
1109 | BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, | |
1110 | "BM_%d : In ISCSI_OP_REJECT\n"); | |
6733b39a JK |
1111 | break; |
1112 | case ISCSI_OP_LOGIN_RSP: | |
7bd6e25c | 1113 | case ISCSI_OP_TEXT_RSP: |
bfead3b2 JK |
1114 | task = conn->login_task; |
1115 | io_task = task->dd_data; | |
1116 | login_hdr = (struct iscsi_hdr *)ppdu; | |
1117 | login_hdr->itt = io_task->libiscsi_itt; | |
6733b39a JK |
1118 | break; |
1119 | default: | |
99bc5d55 JSJ |
1120 | beiscsi_log(phba, KERN_WARNING, |
1121 | BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, | |
1122 | "BM_%d : Unrecognized opcode 0x%x in async msg\n", | |
1123 | (ppdu-> | |
6733b39a | 1124 | dw[offsetof(struct amap_pdu_base, opcode) / 32] |
99bc5d55 | 1125 | & PDUBASE_OPCODE_MASK)); |
6733b39a JK |
1126 | return 1; |
1127 | } | |
1128 | ||
659743b0 | 1129 | spin_lock_bh(&session->back_lock); |
6733b39a | 1130 | __iscsi_complete_pdu(conn, (struct iscsi_hdr *)ppdu, pbuffer, buf_len); |
659743b0 | 1131 | spin_unlock_bh(&session->back_lock); |
6733b39a JK |
1132 | return 0; |
1133 | } | |
1134 | ||
1135 | static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba) | |
1136 | { | |
1137 | struct sgl_handle *psgl_handle; | |
1138 | ||
1139 | if (phba->io_sgl_hndl_avbl) { | |
99bc5d55 JSJ |
1140 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO, |
1141 | "BM_%d : In alloc_io_sgl_handle," | |
1142 | " io_sgl_alloc_index=%d\n", | |
1143 | phba->io_sgl_alloc_index); | |
1144 | ||
6733b39a JK |
1145 | psgl_handle = phba->io_sgl_hndl_base[phba-> |
1146 | io_sgl_alloc_index]; | |
1147 | phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL; | |
1148 | phba->io_sgl_hndl_avbl--; | |
bfead3b2 JK |
1149 | if (phba->io_sgl_alloc_index == (phba->params. |
1150 | ios_per_ctrl - 1)) | |
6733b39a JK |
1151 | phba->io_sgl_alloc_index = 0; |
1152 | else | |
1153 | phba->io_sgl_alloc_index++; | |
1154 | } else | |
1155 | psgl_handle = NULL; | |
1156 | return psgl_handle; | |
1157 | } | |
1158 | ||
1159 | static void | |
1160 | free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle) | |
1161 | { | |
99bc5d55 JSJ |
1162 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO, |
1163 | "BM_%d : In free_,io_sgl_free_index=%d\n", | |
1164 | phba->io_sgl_free_index); | |
1165 | ||
6733b39a JK |
1166 | if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) { |
1167 | /* | |
1168 | * this can happen if clean_task is called on a task that | |
1169 | * failed in xmit_task or alloc_pdu. | |
1170 | */ | |
99bc5d55 JSJ |
1171 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO, |
1172 | "BM_%d : Double Free in IO SGL io_sgl_free_index=%d," | |
1173 | "value there=%p\n", phba->io_sgl_free_index, | |
1174 | phba->io_sgl_hndl_base | |
1175 | [phba->io_sgl_free_index]); | |
6733b39a JK |
1176 | return; |
1177 | } | |
1178 | phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle; | |
1179 | phba->io_sgl_hndl_avbl++; | |
1180 | if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1)) | |
1181 | phba->io_sgl_free_index = 0; | |
1182 | else | |
1183 | phba->io_sgl_free_index++; | |
1184 | } | |
1185 | ||
1186 | /** | |
1187 | * alloc_wrb_handle - To allocate a wrb handle | |
1188 | * @phba: The hba pointer | |
1189 | * @cid: The cid to use for allocation | |
6733b39a JK |
1190 | * |
1191 | * This happens under session_lock until submission to chip | |
1192 | */ | |
d5431488 | 1193 | struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid) |
6733b39a JK |
1194 | { |
1195 | struct hwi_wrb_context *pwrb_context; | |
1196 | struct hwi_controller *phwi_ctrlr; | |
d5431488 | 1197 | struct wrb_handle *pwrb_handle, *pwrb_handle_tmp; |
a7909b39 | 1198 | uint16_t cri_index = BE_GET_CRI_FROM_CID(cid); |
6733b39a JK |
1199 | |
1200 | phwi_ctrlr = phba->phwi_ctrlr; | |
a7909b39 | 1201 | pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; |
d5431488 | 1202 | if (pwrb_context->wrb_handles_available >= 2) { |
bfead3b2 JK |
1203 | pwrb_handle = pwrb_context->pwrb_handle_base[ |
1204 | pwrb_context->alloc_index]; | |
1205 | pwrb_context->wrb_handles_available--; | |
bfead3b2 JK |
1206 | if (pwrb_context->alloc_index == |
1207 | (phba->params.wrbs_per_cxn - 1)) | |
1208 | pwrb_context->alloc_index = 0; | |
1209 | else | |
1210 | pwrb_context->alloc_index++; | |
d5431488 JK |
1211 | pwrb_handle_tmp = pwrb_context->pwrb_handle_base[ |
1212 | pwrb_context->alloc_index]; | |
1213 | pwrb_handle->nxt_wrb_index = pwrb_handle_tmp->wrb_index; | |
bfead3b2 JK |
1214 | } else |
1215 | pwrb_handle = NULL; | |
6733b39a JK |
1216 | return pwrb_handle; |
1217 | } | |
1218 | ||
1219 | /** | |
1220 | * free_wrb_handle - To free the wrb handle back to pool | |
1221 | * @phba: The hba pointer | |
1222 | * @pwrb_context: The context to free from | |
1223 | * @pwrb_handle: The wrb_handle to free | |
1224 | * | |
1225 | * This happens under session_lock until submission to chip | |
1226 | */ | |
1227 | static void | |
1228 | free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context, | |
1229 | struct wrb_handle *pwrb_handle) | |
1230 | { | |
32951dd8 | 1231 | pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle; |
bfead3b2 JK |
1232 | pwrb_context->wrb_handles_available++; |
1233 | if (pwrb_context->free_index == (phba->params.wrbs_per_cxn - 1)) | |
1234 | pwrb_context->free_index = 0; | |
1235 | else | |
1236 | pwrb_context->free_index++; | |
1237 | ||
99bc5d55 JSJ |
1238 | beiscsi_log(phba, KERN_INFO, |
1239 | BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, | |
1240 | "BM_%d : FREE WRB: pwrb_handle=%p free_index=0x%x" | |
1241 | "wrb_handles_available=%d\n", | |
1242 | pwrb_handle, pwrb_context->free_index, | |
1243 | pwrb_context->wrb_handles_available); | |
6733b39a JK |
1244 | } |
1245 | ||
1246 | static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba) | |
1247 | { | |
1248 | struct sgl_handle *psgl_handle; | |
1249 | ||
1250 | if (phba->eh_sgl_hndl_avbl) { | |
1251 | psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index]; | |
1252 | phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL; | |
99bc5d55 JSJ |
1253 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG, |
1254 | "BM_%d : mgmt_sgl_alloc_index=%d=0x%x\n", | |
1255 | phba->eh_sgl_alloc_index, | |
1256 | phba->eh_sgl_alloc_index); | |
1257 | ||
6733b39a JK |
1258 | phba->eh_sgl_hndl_avbl--; |
1259 | if (phba->eh_sgl_alloc_index == | |
1260 | (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - | |
1261 | 1)) | |
1262 | phba->eh_sgl_alloc_index = 0; | |
1263 | else | |
1264 | phba->eh_sgl_alloc_index++; | |
1265 | } else | |
1266 | psgl_handle = NULL; | |
1267 | return psgl_handle; | |
1268 | } | |
1269 | ||
1270 | void | |
1271 | free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle) | |
1272 | { | |
1273 | ||
99bc5d55 JSJ |
1274 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG, |
1275 | "BM_%d : In free_mgmt_sgl_handle," | |
1276 | "eh_sgl_free_index=%d\n", | |
1277 | phba->eh_sgl_free_index); | |
1278 | ||
6733b39a JK |
1279 | if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) { |
1280 | /* | |
1281 | * this can happen if clean_task is called on a task that | |
1282 | * failed in xmit_task or alloc_pdu. | |
1283 | */ | |
99bc5d55 JSJ |
1284 | beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_CONFIG, |
1285 | "BM_%d : Double Free in eh SGL ," | |
1286 | "eh_sgl_free_index=%d\n", | |
1287 | phba->eh_sgl_free_index); | |
6733b39a JK |
1288 | return; |
1289 | } | |
1290 | phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle; | |
1291 | phba->eh_sgl_hndl_avbl++; | |
1292 | if (phba->eh_sgl_free_index == | |
1293 | (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1)) | |
1294 | phba->eh_sgl_free_index = 0; | |
1295 | else | |
1296 | phba->eh_sgl_free_index++; | |
1297 | } | |
1298 | ||
1299 | static void | |
1300 | be_complete_io(struct beiscsi_conn *beiscsi_conn, | |
73133261 JSJ |
1301 | struct iscsi_task *task, |
1302 | struct common_sol_cqe *csol_cqe) | |
6733b39a JK |
1303 | { |
1304 | struct beiscsi_io_task *io_task = task->dd_data; | |
1305 | struct be_status_bhs *sts_bhs = | |
1306 | (struct be_status_bhs *)io_task->cmd_bhs; | |
1307 | struct iscsi_conn *conn = beiscsi_conn->conn; | |
6733b39a JK |
1308 | unsigned char *sense; |
1309 | u32 resid = 0, exp_cmdsn, max_cmdsn; | |
1310 | u8 rsp, status, flags; | |
1311 | ||
73133261 JSJ |
1312 | exp_cmdsn = csol_cqe->exp_cmdsn; |
1313 | max_cmdsn = (csol_cqe->exp_cmdsn + | |
1314 | csol_cqe->cmd_wnd - 1); | |
1315 | rsp = csol_cqe->i_resp; | |
1316 | status = csol_cqe->i_sts; | |
1317 | flags = csol_cqe->i_flags; | |
1318 | resid = csol_cqe->res_cnt; | |
1319 | ||
bd535451 | 1320 | if (!task->sc) { |
da334977 | 1321 | if (io_task->scsi_cmnd) { |
bd535451 | 1322 | scsi_dma_unmap(io_task->scsi_cmnd); |
da334977 JK |
1323 | io_task->scsi_cmnd = NULL; |
1324 | } | |
6733b39a | 1325 | |
bd535451 JK |
1326 | return; |
1327 | } | |
6733b39a JK |
1328 | task->sc->result = (DID_OK << 16) | status; |
1329 | if (rsp != ISCSI_STATUS_CMD_COMPLETED) { | |
1330 | task->sc->result = DID_ERROR << 16; | |
1331 | goto unmap; | |
1332 | } | |
1333 | ||
1334 | /* bidi not initially supported */ | |
1335 | if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) { | |
6733b39a JK |
1336 | if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW)) |
1337 | task->sc->result = DID_ERROR << 16; | |
1338 | ||
1339 | if (flags & ISCSI_FLAG_CMD_UNDERFLOW) { | |
1340 | scsi_set_resid(task->sc, resid); | |
1341 | if (!status && (scsi_bufflen(task->sc) - resid < | |
1342 | task->sc->underflow)) | |
1343 | task->sc->result = DID_ERROR << 16; | |
1344 | } | |
1345 | } | |
1346 | ||
1347 | if (status == SAM_STAT_CHECK_CONDITION) { | |
4053a4be | 1348 | u16 sense_len; |
bfead3b2 | 1349 | unsigned short *slen = (unsigned short *)sts_bhs->sense_info; |
4053a4be | 1350 | |
6733b39a | 1351 | sense = sts_bhs->sense_info + sizeof(unsigned short); |
4053a4be | 1352 | sense_len = be16_to_cpu(*slen); |
6733b39a JK |
1353 | memcpy(task->sc->sense_buffer, sense, |
1354 | min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE)); | |
1355 | } | |
756d29c8 | 1356 | |
73133261 JSJ |
1357 | if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ) |
1358 | conn->rxdata_octets += resid; | |
6733b39a JK |
1359 | unmap: |
1360 | scsi_dma_unmap(io_task->scsi_cmnd); | |
da334977 | 1361 | io_task->scsi_cmnd = NULL; |
6733b39a JK |
1362 | iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn); |
1363 | } | |
1364 | ||
1365 | static void | |
1366 | be_complete_logout(struct beiscsi_conn *beiscsi_conn, | |
73133261 JSJ |
1367 | struct iscsi_task *task, |
1368 | struct common_sol_cqe *csol_cqe) | |
6733b39a JK |
1369 | { |
1370 | struct iscsi_logout_rsp *hdr; | |
bfead3b2 | 1371 | struct beiscsi_io_task *io_task = task->dd_data; |
6733b39a JK |
1372 | struct iscsi_conn *conn = beiscsi_conn->conn; |
1373 | ||
1374 | hdr = (struct iscsi_logout_rsp *)task->hdr; | |
7bd6e25c | 1375 | hdr->opcode = ISCSI_OP_LOGOUT_RSP; |
6733b39a JK |
1376 | hdr->t2wait = 5; |
1377 | hdr->t2retain = 0; | |
73133261 JSJ |
1378 | hdr->flags = csol_cqe->i_flags; |
1379 | hdr->response = csol_cqe->i_resp; | |
702dc5e8 JK |
1380 | hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn); |
1381 | hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn + | |
1382 | csol_cqe->cmd_wnd - 1); | |
73133261 | 1383 | |
7bd6e25c JK |
1384 | hdr->dlength[0] = 0; |
1385 | hdr->dlength[1] = 0; | |
1386 | hdr->dlength[2] = 0; | |
6733b39a | 1387 | hdr->hlength = 0; |
bfead3b2 | 1388 | hdr->itt = io_task->libiscsi_itt; |
6733b39a JK |
1389 | __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0); |
1390 | } | |
1391 | ||
1392 | static void | |
1393 | be_complete_tmf(struct beiscsi_conn *beiscsi_conn, | |
73133261 JSJ |
1394 | struct iscsi_task *task, |
1395 | struct common_sol_cqe *csol_cqe) | |
6733b39a JK |
1396 | { |
1397 | struct iscsi_tm_rsp *hdr; | |
1398 | struct iscsi_conn *conn = beiscsi_conn->conn; | |
bfead3b2 | 1399 | struct beiscsi_io_task *io_task = task->dd_data; |
6733b39a JK |
1400 | |
1401 | hdr = (struct iscsi_tm_rsp *)task->hdr; | |
7bd6e25c | 1402 | hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP; |
73133261 JSJ |
1403 | hdr->flags = csol_cqe->i_flags; |
1404 | hdr->response = csol_cqe->i_resp; | |
702dc5e8 JK |
1405 | hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn); |
1406 | hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn + | |
1407 | csol_cqe->cmd_wnd - 1); | |
73133261 | 1408 | |
bfead3b2 | 1409 | hdr->itt = io_task->libiscsi_itt; |
6733b39a JK |
1410 | __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0); |
1411 | } | |
1412 | ||
1413 | static void | |
1414 | hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn, | |
1415 | struct beiscsi_hba *phba, struct sol_cqe *psol) | |
1416 | { | |
1417 | struct hwi_wrb_context *pwrb_context; | |
bfead3b2 | 1418 | struct wrb_handle *pwrb_handle = NULL; |
6733b39a | 1419 | struct hwi_controller *phwi_ctrlr; |
bfead3b2 JK |
1420 | struct iscsi_task *task; |
1421 | struct beiscsi_io_task *io_task; | |
a7909b39 | 1422 | uint16_t wrb_index, cid, cri_index; |
6733b39a JK |
1423 | |
1424 | phwi_ctrlr = phba->phwi_ctrlr; | |
2c9dfd36 JK |
1425 | if (is_chip_be2_be3r(phba)) { |
1426 | wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe, | |
73133261 | 1427 | wrb_idx, psol); |
2c9dfd36 | 1428 | cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe, |
73133261 JSJ |
1429 | cid, psol); |
1430 | } else { | |
2c9dfd36 | 1431 | wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2, |
73133261 | 1432 | wrb_idx, psol); |
2c9dfd36 | 1433 | cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2, |
73133261 JSJ |
1434 | cid, psol); |
1435 | } | |
1436 | ||
a7909b39 JK |
1437 | cri_index = BE_GET_CRI_FROM_CID(cid); |
1438 | pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; | |
73133261 | 1439 | pwrb_handle = pwrb_context->pwrb_handle_basestd[wrb_index]; |
32951dd8 | 1440 | task = pwrb_handle->pio_handle; |
35e66019 | 1441 | |
bfead3b2 | 1442 | io_task = task->dd_data; |
4a4a11b9 JK |
1443 | memset(io_task->pwrb_handle->pwrb, 0, sizeof(struct iscsi_wrb)); |
1444 | iscsi_put_task(task); | |
6733b39a JK |
1445 | } |
1446 | ||
1447 | static void | |
1448 | be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn, | |
73133261 JSJ |
1449 | struct iscsi_task *task, |
1450 | struct common_sol_cqe *csol_cqe) | |
6733b39a JK |
1451 | { |
1452 | struct iscsi_nopin *hdr; | |
1453 | struct iscsi_conn *conn = beiscsi_conn->conn; | |
bfead3b2 | 1454 | struct beiscsi_io_task *io_task = task->dd_data; |
6733b39a JK |
1455 | |
1456 | hdr = (struct iscsi_nopin *)task->hdr; | |
73133261 JSJ |
1457 | hdr->flags = csol_cqe->i_flags; |
1458 | hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn); | |
702dc5e8 JK |
1459 | hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn + |
1460 | csol_cqe->cmd_wnd - 1); | |
73133261 | 1461 | |
6733b39a | 1462 | hdr->opcode = ISCSI_OP_NOOP_IN; |
bfead3b2 | 1463 | hdr->itt = io_task->libiscsi_itt; |
6733b39a JK |
1464 | __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0); |
1465 | } | |
1466 | ||
73133261 JSJ |
1467 | static void adapter_get_sol_cqe(struct beiscsi_hba *phba, |
1468 | struct sol_cqe *psol, | |
1469 | struct common_sol_cqe *csol_cqe) | |
1470 | { | |
2c9dfd36 JK |
1471 | if (is_chip_be2_be3r(phba)) { |
1472 | csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe, | |
1473 | i_exp_cmd_sn, psol); | |
1474 | csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe, | |
1475 | i_res_cnt, psol); | |
1476 | csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe, | |
1477 | i_cmd_wnd, psol); | |
1478 | csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe, | |
1479 | wrb_index, psol); | |
1480 | csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe, | |
1481 | cid, psol); | |
1482 | csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe, | |
1483 | hw_sts, psol); | |
1484 | csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe, | |
1485 | i_resp, psol); | |
1486 | csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe, | |
1487 | i_sts, psol); | |
1488 | csol_cqe->i_flags = AMAP_GET_BITS(struct amap_sol_cqe, | |
1489 | i_flags, psol); | |
1490 | } else { | |
73133261 JSJ |
1491 | csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe_v2, |
1492 | i_exp_cmd_sn, psol); | |
1493 | csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe_v2, | |
1494 | i_res_cnt, psol); | |
1495 | csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe_v2, | |
1496 | wrb_index, psol); | |
1497 | csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe_v2, | |
1498 | cid, psol); | |
1499 | csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2, | |
1500 | hw_sts, psol); | |
702dc5e8 | 1501 | csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe_v2, |
73133261 JSJ |
1502 | i_cmd_wnd, psol); |
1503 | if (AMAP_GET_BITS(struct amap_sol_cqe_v2, | |
1504 | cmd_cmpl, psol)) | |
1505 | csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2, | |
1506 | i_sts, psol); | |
1507 | else | |
1508 | csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe_v2, | |
1509 | i_sts, psol); | |
1510 | if (AMAP_GET_BITS(struct amap_sol_cqe_v2, | |
1511 | u, psol)) | |
1512 | csol_cqe->i_flags = ISCSI_FLAG_CMD_UNDERFLOW; | |
1513 | ||
1514 | if (AMAP_GET_BITS(struct amap_sol_cqe_v2, | |
1515 | o, psol)) | |
1516 | csol_cqe->i_flags |= ISCSI_FLAG_CMD_OVERFLOW; | |
73133261 JSJ |
1517 | } |
1518 | } | |
1519 | ||
1520 | ||
6733b39a JK |
1521 | static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn, |
1522 | struct beiscsi_hba *phba, struct sol_cqe *psol) | |
1523 | { | |
1524 | struct hwi_wrb_context *pwrb_context; | |
1525 | struct wrb_handle *pwrb_handle; | |
1526 | struct iscsi_wrb *pwrb = NULL; | |
1527 | struct hwi_controller *phwi_ctrlr; | |
1528 | struct iscsi_task *task; | |
bfead3b2 | 1529 | unsigned int type; |
6733b39a JK |
1530 | struct iscsi_conn *conn = beiscsi_conn->conn; |
1531 | struct iscsi_session *session = conn->session; | |
73133261 | 1532 | struct common_sol_cqe csol_cqe = {0}; |
a7909b39 | 1533 | uint16_t cri_index = 0; |
6733b39a JK |
1534 | |
1535 | phwi_ctrlr = phba->phwi_ctrlr; | |
73133261 JSJ |
1536 | |
1537 | /* Copy the elements to a common structure */ | |
1538 | adapter_get_sol_cqe(phba, psol, &csol_cqe); | |
1539 | ||
a7909b39 JK |
1540 | cri_index = BE_GET_CRI_FROM_CID(csol_cqe.cid); |
1541 | pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; | |
73133261 JSJ |
1542 | |
1543 | pwrb_handle = pwrb_context->pwrb_handle_basestd[ | |
1544 | csol_cqe.wrb_index]; | |
1545 | ||
32951dd8 JK |
1546 | task = pwrb_handle->pio_handle; |
1547 | pwrb = pwrb_handle->pwrb; | |
73133261 | 1548 | type = ((struct beiscsi_io_task *)task->dd_data)->wrb_type; |
32951dd8 | 1549 | |
659743b0 | 1550 | spin_lock_bh(&session->back_lock); |
bfead3b2 | 1551 | switch (type) { |
6733b39a JK |
1552 | case HWH_TYPE_IO: |
1553 | case HWH_TYPE_IO_RD: | |
1554 | if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == | |
dafab8e0 | 1555 | ISCSI_OP_NOOP_OUT) |
73133261 | 1556 | be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe); |
dafab8e0 | 1557 | else |
73133261 | 1558 | be_complete_io(beiscsi_conn, task, &csol_cqe); |
6733b39a JK |
1559 | break; |
1560 | ||
1561 | case HWH_TYPE_LOGOUT: | |
dafab8e0 | 1562 | if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT) |
73133261 | 1563 | be_complete_logout(beiscsi_conn, task, &csol_cqe); |
dafab8e0 | 1564 | else |
73133261 | 1565 | be_complete_tmf(beiscsi_conn, task, &csol_cqe); |
6733b39a JK |
1566 | break; |
1567 | ||
1568 | case HWH_TYPE_LOGIN: | |
99bc5d55 JSJ |
1569 | beiscsi_log(phba, KERN_ERR, |
1570 | BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, | |
1571 | "BM_%d :\t\t No HWH_TYPE_LOGIN Expected in" | |
1572 | " hwi_complete_cmd- Solicited path\n"); | |
6733b39a JK |
1573 | break; |
1574 | ||
6733b39a | 1575 | case HWH_TYPE_NOP: |
73133261 | 1576 | be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe); |
6733b39a JK |
1577 | break; |
1578 | ||
1579 | default: | |
99bc5d55 JSJ |
1580 | beiscsi_log(phba, KERN_WARNING, |
1581 | BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, | |
1582 | "BM_%d : In hwi_complete_cmd, unknown type = %d" | |
1583 | "wrb_index 0x%x CID 0x%x\n", type, | |
73133261 JSJ |
1584 | csol_cqe.wrb_index, |
1585 | csol_cqe.cid); | |
6733b39a JK |
1586 | break; |
1587 | } | |
35e66019 | 1588 | |
659743b0 | 1589 | spin_unlock_bh(&session->back_lock); |
6733b39a JK |
1590 | } |
1591 | ||
1592 | static struct list_head *hwi_get_async_busy_list(struct hwi_async_pdu_context | |
1593 | *pasync_ctx, unsigned int is_header, | |
1594 | unsigned int host_write_ptr) | |
1595 | { | |
1596 | if (is_header) | |
1597 | return &pasync_ctx->async_entry[host_write_ptr]. | |
1598 | header_busy_list; | |
1599 | else | |
1600 | return &pasync_ctx->async_entry[host_write_ptr].data_busy_list; | |
1601 | } | |
1602 | ||
1603 | static struct async_pdu_handle * | |
1604 | hwi_get_async_handle(struct beiscsi_hba *phba, | |
1605 | struct beiscsi_conn *beiscsi_conn, | |
1606 | struct hwi_async_pdu_context *pasync_ctx, | |
1607 | struct i_t_dpdu_cqe *pdpdu_cqe, unsigned int *pcq_index) | |
1608 | { | |
1609 | struct be_bus_address phys_addr; | |
1610 | struct list_head *pbusy_list; | |
1611 | struct async_pdu_handle *pasync_handle = NULL; | |
6733b39a | 1612 | unsigned char is_header = 0; |
73133261 JSJ |
1613 | unsigned int index, dpl; |
1614 | ||
2c9dfd36 JK |
1615 | if (is_chip_be2_be3r(phba)) { |
1616 | dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe, | |
73133261 | 1617 | dpl, pdpdu_cqe); |
2c9dfd36 | 1618 | index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe, |
73133261 JSJ |
1619 | index, pdpdu_cqe); |
1620 | } else { | |
2c9dfd36 | 1621 | dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2, |
73133261 | 1622 | dpl, pdpdu_cqe); |
2c9dfd36 | 1623 | index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2, |
73133261 JSJ |
1624 | index, pdpdu_cqe); |
1625 | } | |
6733b39a JK |
1626 | |
1627 | phys_addr.u.a32.address_lo = | |
73133261 JSJ |
1628 | (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, |
1629 | db_addr_lo) / 32] - dpl); | |
6733b39a | 1630 | phys_addr.u.a32.address_hi = |
73133261 JSJ |
1631 | pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, |
1632 | db_addr_hi) / 32]; | |
6733b39a JK |
1633 | |
1634 | phys_addr.u.a64.address = | |
1635 | *((unsigned long long *)(&phys_addr.u.a64.address)); | |
1636 | ||
1637 | switch (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, code) / 32] | |
1638 | & PDUCQE_CODE_MASK) { | |
1639 | case UNSOL_HDR_NOTIFY: | |
1640 | is_header = 1; | |
1641 | ||
73133261 JSJ |
1642 | pbusy_list = hwi_get_async_busy_list(pasync_ctx, |
1643 | is_header, index); | |
6733b39a JK |
1644 | break; |
1645 | case UNSOL_DATA_NOTIFY: | |
73133261 JSJ |
1646 | pbusy_list = hwi_get_async_busy_list(pasync_ctx, |
1647 | is_header, index); | |
6733b39a JK |
1648 | break; |
1649 | default: | |
1650 | pbusy_list = NULL; | |
99bc5d55 JSJ |
1651 | beiscsi_log(phba, KERN_WARNING, |
1652 | BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, | |
1653 | "BM_%d : Unexpected code=%d\n", | |
1654 | pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, | |
1655 | code) / 32] & PDUCQE_CODE_MASK); | |
6733b39a JK |
1656 | return NULL; |
1657 | } | |
1658 | ||
6733b39a JK |
1659 | WARN_ON(list_empty(pbusy_list)); |
1660 | list_for_each_entry(pasync_handle, pbusy_list, link) { | |
dc63aac6 | 1661 | if (pasync_handle->pa.u.a64.address == phys_addr.u.a64.address) |
6733b39a JK |
1662 | break; |
1663 | } | |
1664 | ||
1665 | WARN_ON(!pasync_handle); | |
1666 | ||
8a86e833 JK |
1667 | pasync_handle->cri = BE_GET_ASYNC_CRI_FROM_CID( |
1668 | beiscsi_conn->beiscsi_conn_cid); | |
6733b39a | 1669 | pasync_handle->is_header = is_header; |
73133261 JSJ |
1670 | pasync_handle->buffer_len = dpl; |
1671 | *pcq_index = index; | |
6733b39a | 1672 | |
6733b39a JK |
1673 | return pasync_handle; |
1674 | } | |
1675 | ||
1676 | static unsigned int | |
99bc5d55 JSJ |
1677 | hwi_update_async_writables(struct beiscsi_hba *phba, |
1678 | struct hwi_async_pdu_context *pasync_ctx, | |
1679 | unsigned int is_header, unsigned int cq_index) | |
6733b39a JK |
1680 | { |
1681 | struct list_head *pbusy_list; | |
1682 | struct async_pdu_handle *pasync_handle; | |
1683 | unsigned int num_entries, writables = 0; | |
1684 | unsigned int *pep_read_ptr, *pwritables; | |
1685 | ||
dc63aac6 | 1686 | num_entries = pasync_ctx->num_entries; |
6733b39a JK |
1687 | if (is_header) { |
1688 | pep_read_ptr = &pasync_ctx->async_header.ep_read_ptr; | |
1689 | pwritables = &pasync_ctx->async_header.writables; | |
6733b39a JK |
1690 | } else { |
1691 | pep_read_ptr = &pasync_ctx->async_data.ep_read_ptr; | |
1692 | pwritables = &pasync_ctx->async_data.writables; | |
6733b39a JK |
1693 | } |
1694 | ||
1695 | while ((*pep_read_ptr) != cq_index) { | |
1696 | (*pep_read_ptr)++; | |
1697 | *pep_read_ptr = (*pep_read_ptr) % num_entries; | |
1698 | ||
1699 | pbusy_list = hwi_get_async_busy_list(pasync_ctx, is_header, | |
1700 | *pep_read_ptr); | |
1701 | if (writables == 0) | |
1702 | WARN_ON(list_empty(pbusy_list)); | |
1703 | ||
1704 | if (!list_empty(pbusy_list)) { | |
1705 | pasync_handle = list_entry(pbusy_list->next, | |
1706 | struct async_pdu_handle, | |
1707 | link); | |
1708 | WARN_ON(!pasync_handle); | |
1709 | pasync_handle->consumed = 1; | |
1710 | } | |
1711 | ||
1712 | writables++; | |
1713 | } | |
1714 | ||
1715 | if (!writables) { | |
99bc5d55 JSJ |
1716 | beiscsi_log(phba, KERN_ERR, |
1717 | BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, | |
1718 | "BM_%d : Duplicate notification received - index 0x%x!!\n", | |
1719 | cq_index); | |
6733b39a JK |
1720 | WARN_ON(1); |
1721 | } | |
1722 | ||
1723 | *pwritables = *pwritables + writables; | |
1724 | return 0; | |
1725 | } | |
1726 | ||
9728d8d0 | 1727 | static void hwi_free_async_msg(struct beiscsi_hba *phba, |
8a86e833 JK |
1728 | struct hwi_async_pdu_context *pasync_ctx, |
1729 | unsigned int cri) | |
6733b39a | 1730 | { |
6733b39a JK |
1731 | struct async_pdu_handle *pasync_handle, *tmp_handle; |
1732 | struct list_head *plist; | |
6733b39a | 1733 | |
6733b39a | 1734 | plist = &pasync_ctx->async_entry[cri].wait_queue.list; |
6733b39a JK |
1735 | list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) { |
1736 | list_del(&pasync_handle->link); | |
1737 | ||
9728d8d0 | 1738 | if (pasync_handle->is_header) { |
6733b39a JK |
1739 | list_add_tail(&pasync_handle->link, |
1740 | &pasync_ctx->async_header.free_list); | |
1741 | pasync_ctx->async_header.free_entries++; | |
6733b39a JK |
1742 | } else { |
1743 | list_add_tail(&pasync_handle->link, | |
1744 | &pasync_ctx->async_data.free_list); | |
1745 | pasync_ctx->async_data.free_entries++; | |
6733b39a JK |
1746 | } |
1747 | } | |
1748 | ||
1749 | INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wait_queue.list); | |
1750 | pasync_ctx->async_entry[cri].wait_queue.hdr_received = 0; | |
1751 | pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0; | |
6733b39a JK |
1752 | } |
1753 | ||
1754 | static struct phys_addr * | |
1755 | hwi_get_ring_address(struct hwi_async_pdu_context *pasync_ctx, | |
1756 | unsigned int is_header, unsigned int host_write_ptr) | |
1757 | { | |
1758 | struct phys_addr *pasync_sge = NULL; | |
1759 | ||
1760 | if (is_header) | |
1761 | pasync_sge = pasync_ctx->async_header.ring_base; | |
1762 | else | |
1763 | pasync_sge = pasync_ctx->async_data.ring_base; | |
1764 | ||
1765 | return pasync_sge + host_write_ptr; | |
1766 | } | |
1767 | ||
1768 | static void hwi_post_async_buffers(struct beiscsi_hba *phba, | |
8a86e833 | 1769 | unsigned int is_header, uint8_t ulp_num) |
6733b39a JK |
1770 | { |
1771 | struct hwi_controller *phwi_ctrlr; | |
1772 | struct hwi_async_pdu_context *pasync_ctx; | |
1773 | struct async_pdu_handle *pasync_handle; | |
1774 | struct list_head *pfree_link, *pbusy_list; | |
1775 | struct phys_addr *pasync_sge; | |
1776 | unsigned int ring_id, num_entries; | |
8a86e833 | 1777 | unsigned int host_write_num, doorbell_offset; |
6733b39a JK |
1778 | unsigned int writables; |
1779 | unsigned int i = 0; | |
1780 | u32 doorbell = 0; | |
1781 | ||
1782 | phwi_ctrlr = phba->phwi_ctrlr; | |
8a86e833 | 1783 | pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr, ulp_num); |
dc63aac6 | 1784 | num_entries = pasync_ctx->num_entries; |
6733b39a JK |
1785 | |
1786 | if (is_header) { | |
6733b39a JK |
1787 | writables = min(pasync_ctx->async_header.writables, |
1788 | pasync_ctx->async_header.free_entries); | |
1789 | pfree_link = pasync_ctx->async_header.free_list.next; | |
1790 | host_write_num = pasync_ctx->async_header.host_write_ptr; | |
8a86e833 JK |
1791 | ring_id = phwi_ctrlr->default_pdu_hdr[ulp_num].id; |
1792 | doorbell_offset = phwi_ctrlr->default_pdu_hdr[ulp_num]. | |
1793 | doorbell_offset; | |
6733b39a | 1794 | } else { |
6733b39a JK |
1795 | writables = min(pasync_ctx->async_data.writables, |
1796 | pasync_ctx->async_data.free_entries); | |
1797 | pfree_link = pasync_ctx->async_data.free_list.next; | |
1798 | host_write_num = pasync_ctx->async_data.host_write_ptr; | |
8a86e833 JK |
1799 | ring_id = phwi_ctrlr->default_pdu_data[ulp_num].id; |
1800 | doorbell_offset = phwi_ctrlr->default_pdu_data[ulp_num]. | |
1801 | doorbell_offset; | |
6733b39a JK |
1802 | } |
1803 | ||
1804 | writables = (writables / 8) * 8; | |
1805 | if (writables) { | |
1806 | for (i = 0; i < writables; i++) { | |
1807 | pbusy_list = | |
1808 | hwi_get_async_busy_list(pasync_ctx, is_header, | |
1809 | host_write_num); | |
1810 | pasync_handle = | |
1811 | list_entry(pfree_link, struct async_pdu_handle, | |
1812 | link); | |
1813 | WARN_ON(!pasync_handle); | |
1814 | pasync_handle->consumed = 0; | |
1815 | ||
1816 | pfree_link = pfree_link->next; | |
1817 | ||
1818 | pasync_sge = hwi_get_ring_address(pasync_ctx, | |
1819 | is_header, host_write_num); | |
1820 | ||
1821 | pasync_sge->hi = pasync_handle->pa.u.a32.address_lo; | |
1822 | pasync_sge->lo = pasync_handle->pa.u.a32.address_hi; | |
1823 | ||
1824 | list_move(&pasync_handle->link, pbusy_list); | |
1825 | ||
1826 | host_write_num++; | |
1827 | host_write_num = host_write_num % num_entries; | |
1828 | } | |
1829 | ||
1830 | if (is_header) { | |
1831 | pasync_ctx->async_header.host_write_ptr = | |
1832 | host_write_num; | |
1833 | pasync_ctx->async_header.free_entries -= writables; | |
1834 | pasync_ctx->async_header.writables -= writables; | |
1835 | pasync_ctx->async_header.busy_entries += writables; | |
1836 | } else { | |
1837 | pasync_ctx->async_data.host_write_ptr = host_write_num; | |
1838 | pasync_ctx->async_data.free_entries -= writables; | |
1839 | pasync_ctx->async_data.writables -= writables; | |
1840 | pasync_ctx->async_data.busy_entries += writables; | |
1841 | } | |
1842 | ||
1843 | doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK; | |
1844 | doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT; | |
1845 | doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT; | |
1846 | doorbell |= (writables & DB_DEF_PDU_CQPROC_MASK) | |
1847 | << DB_DEF_PDU_CQPROC_SHIFT; | |
1848 | ||
8a86e833 | 1849 | iowrite32(doorbell, phba->db_va + doorbell_offset); |
6733b39a JK |
1850 | } |
1851 | } | |
1852 | ||
1853 | static void hwi_flush_default_pdu_buffer(struct beiscsi_hba *phba, | |
1854 | struct beiscsi_conn *beiscsi_conn, | |
1855 | struct i_t_dpdu_cqe *pdpdu_cqe) | |
1856 | { | |
1857 | struct hwi_controller *phwi_ctrlr; | |
1858 | struct hwi_async_pdu_context *pasync_ctx; | |
1859 | struct async_pdu_handle *pasync_handle = NULL; | |
1860 | unsigned int cq_index = -1; | |
8a86e833 JK |
1861 | uint16_t cri_index = BE_GET_CRI_FROM_CID( |
1862 | beiscsi_conn->beiscsi_conn_cid); | |
6733b39a JK |
1863 | |
1864 | phwi_ctrlr = phba->phwi_ctrlr; | |
8a86e833 JK |
1865 | pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr, |
1866 | BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, | |
1867 | cri_index)); | |
6733b39a JK |
1868 | |
1869 | pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx, | |
1870 | pdpdu_cqe, &cq_index); | |
1871 | BUG_ON(pasync_handle->is_header != 0); | |
1872 | if (pasync_handle->consumed == 0) | |
99bc5d55 JSJ |
1873 | hwi_update_async_writables(phba, pasync_ctx, |
1874 | pasync_handle->is_header, cq_index); | |
6733b39a | 1875 | |
8a86e833 JK |
1876 | hwi_free_async_msg(phba, pasync_ctx, pasync_handle->cri); |
1877 | hwi_post_async_buffers(phba, pasync_handle->is_header, | |
1878 | BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, | |
1879 | cri_index)); | |
6733b39a JK |
1880 | } |
1881 | ||
1882 | static unsigned int | |
1883 | hwi_fwd_async_msg(struct beiscsi_conn *beiscsi_conn, | |
1884 | struct beiscsi_hba *phba, | |
1885 | struct hwi_async_pdu_context *pasync_ctx, unsigned short cri) | |
1886 | { | |
1887 | struct list_head *plist; | |
1888 | struct async_pdu_handle *pasync_handle; | |
1889 | void *phdr = NULL; | |
1890 | unsigned int hdr_len = 0, buf_len = 0; | |
1891 | unsigned int status, index = 0, offset = 0; | |
1892 | void *pfirst_buffer = NULL; | |
1893 | unsigned int num_buf = 0; | |
1894 | ||
1895 | plist = &pasync_ctx->async_entry[cri].wait_queue.list; | |
1896 | ||
1897 | list_for_each_entry(pasync_handle, plist, link) { | |
1898 | if (index == 0) { | |
1899 | phdr = pasync_handle->pbuffer; | |
1900 | hdr_len = pasync_handle->buffer_len; | |
1901 | } else { | |
1902 | buf_len = pasync_handle->buffer_len; | |
1903 | if (!num_buf) { | |
1904 | pfirst_buffer = pasync_handle->pbuffer; | |
1905 | num_buf++; | |
1906 | } | |
1907 | memcpy(pfirst_buffer + offset, | |
1908 | pasync_handle->pbuffer, buf_len); | |
f2ba02b8 | 1909 | offset += buf_len; |
6733b39a JK |
1910 | } |
1911 | index++; | |
1912 | } | |
1913 | ||
1914 | status = beiscsi_process_async_pdu(beiscsi_conn, phba, | |
7da50879 | 1915 | phdr, hdr_len, pfirst_buffer, |
f2ba02b8 | 1916 | offset); |
6733b39a | 1917 | |
8a86e833 | 1918 | hwi_free_async_msg(phba, pasync_ctx, cri); |
6733b39a JK |
1919 | return 0; |
1920 | } | |
1921 | ||
1922 | static unsigned int | |
1923 | hwi_gather_async_pdu(struct beiscsi_conn *beiscsi_conn, | |
1924 | struct beiscsi_hba *phba, | |
1925 | struct async_pdu_handle *pasync_handle) | |
1926 | { | |
1927 | struct hwi_async_pdu_context *pasync_ctx; | |
1928 | struct hwi_controller *phwi_ctrlr; | |
1929 | unsigned int bytes_needed = 0, status = 0; | |
1930 | unsigned short cri = pasync_handle->cri; | |
1931 | struct pdu_base *ppdu; | |
1932 | ||
1933 | phwi_ctrlr = phba->phwi_ctrlr; | |
8a86e833 JK |
1934 | pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr, |
1935 | BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, | |
1936 | BE_GET_CRI_FROM_CID(beiscsi_conn-> | |
1937 | beiscsi_conn_cid))); | |
6733b39a JK |
1938 | |
1939 | list_del(&pasync_handle->link); | |
1940 | if (pasync_handle->is_header) { | |
1941 | pasync_ctx->async_header.busy_entries--; | |
1942 | if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) { | |
8a86e833 | 1943 | hwi_free_async_msg(phba, pasync_ctx, cri); |
6733b39a JK |
1944 | BUG(); |
1945 | } | |
1946 | ||
1947 | pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0; | |
1948 | pasync_ctx->async_entry[cri].wait_queue.hdr_received = 1; | |
1949 | pasync_ctx->async_entry[cri].wait_queue.hdr_len = | |
1950 | (unsigned short)pasync_handle->buffer_len; | |
1951 | list_add_tail(&pasync_handle->link, | |
1952 | &pasync_ctx->async_entry[cri].wait_queue.list); | |
1953 | ||
1954 | ppdu = pasync_handle->pbuffer; | |
1955 | bytes_needed = ((((ppdu->dw[offsetof(struct amap_pdu_base, | |
1956 | data_len_hi) / 32] & PDUBASE_DATALENHI_MASK) << 8) & | |
1957 | 0xFFFF0000) | ((be16_to_cpu((ppdu-> | |
1958 | dw[offsetof(struct amap_pdu_base, data_len_lo) / 32] | |
1959 | & PDUBASE_DATALENLO_MASK) >> 16)) & 0x0000FFFF)); | |
1960 | ||
1961 | if (status == 0) { | |
1962 | pasync_ctx->async_entry[cri].wait_queue.bytes_needed = | |
1963 | bytes_needed; | |
1964 | ||
1965 | if (bytes_needed == 0) | |
1966 | status = hwi_fwd_async_msg(beiscsi_conn, phba, | |
1967 | pasync_ctx, cri); | |
1968 | } | |
1969 | } else { | |
1970 | pasync_ctx->async_data.busy_entries--; | |
1971 | if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) { | |
1972 | list_add_tail(&pasync_handle->link, | |
1973 | &pasync_ctx->async_entry[cri].wait_queue. | |
1974 | list); | |
1975 | pasync_ctx->async_entry[cri].wait_queue. | |
1976 | bytes_received += | |
1977 | (unsigned short)pasync_handle->buffer_len; | |
1978 | ||
1979 | if (pasync_ctx->async_entry[cri].wait_queue. | |
1980 | bytes_received >= | |
1981 | pasync_ctx->async_entry[cri].wait_queue. | |
1982 | bytes_needed) | |
1983 | status = hwi_fwd_async_msg(beiscsi_conn, phba, | |
1984 | pasync_ctx, cri); | |
1985 | } | |
1986 | } | |
1987 | return status; | |
1988 | } | |
1989 | ||
1990 | static void hwi_process_default_pdu_ring(struct beiscsi_conn *beiscsi_conn, | |
1991 | struct beiscsi_hba *phba, | |
1992 | struct i_t_dpdu_cqe *pdpdu_cqe) | |
1993 | { | |
1994 | struct hwi_controller *phwi_ctrlr; | |
1995 | struct hwi_async_pdu_context *pasync_ctx; | |
1996 | struct async_pdu_handle *pasync_handle = NULL; | |
1997 | unsigned int cq_index = -1; | |
8a86e833 JK |
1998 | uint16_t cri_index = BE_GET_CRI_FROM_CID( |
1999 | beiscsi_conn->beiscsi_conn_cid); | |
6733b39a JK |
2000 | |
2001 | phwi_ctrlr = phba->phwi_ctrlr; | |
8a86e833 JK |
2002 | pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr, |
2003 | BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, | |
2004 | cri_index)); | |
2005 | ||
6733b39a JK |
2006 | pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx, |
2007 | pdpdu_cqe, &cq_index); | |
2008 | ||
2009 | if (pasync_handle->consumed == 0) | |
99bc5d55 JSJ |
2010 | hwi_update_async_writables(phba, pasync_ctx, |
2011 | pasync_handle->is_header, cq_index); | |
2012 | ||
6733b39a | 2013 | hwi_gather_async_pdu(beiscsi_conn, phba, pasync_handle); |
8a86e833 JK |
2014 | hwi_post_async_buffers(phba, pasync_handle->is_header, |
2015 | BEISCSI_GET_ULP_FROM_CRI( | |
2016 | phwi_ctrlr, cri_index)); | |
6733b39a JK |
2017 | } |
2018 | ||
756d29c8 JK |
2019 | static void beiscsi_process_mcc_isr(struct beiscsi_hba *phba) |
2020 | { | |
2021 | struct be_queue_info *mcc_cq; | |
2022 | struct be_mcc_compl *mcc_compl; | |
2023 | unsigned int num_processed = 0; | |
2024 | ||
2025 | mcc_cq = &phba->ctrl.mcc_obj.cq; | |
2026 | mcc_compl = queue_tail_node(mcc_cq); | |
2027 | mcc_compl->flags = le32_to_cpu(mcc_compl->flags); | |
2028 | while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) { | |
2029 | ||
2030 | if (num_processed >= 32) { | |
2031 | hwi_ring_cq_db(phba, mcc_cq->id, | |
2032 | num_processed, 0, 0); | |
2033 | num_processed = 0; | |
2034 | } | |
2035 | if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) { | |
2036 | /* Interpret flags as an async trailer */ | |
2037 | if (is_link_state_evt(mcc_compl->flags)) | |
2038 | /* Interpret compl as a async link evt */ | |
2039 | beiscsi_async_link_state_process(phba, | |
2040 | (struct be_async_event_link_state *) mcc_compl); | |
2041 | else | |
99bc5d55 JSJ |
2042 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_MBOX, |
2043 | "BM_%d : Unsupported Async Event, flags" | |
2044 | " = 0x%08x\n", | |
2045 | mcc_compl->flags); | |
756d29c8 JK |
2046 | } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) { |
2047 | be_mcc_compl_process_isr(&phba->ctrl, mcc_compl); | |
2048 | atomic_dec(&phba->ctrl.mcc_obj.q.used); | |
2049 | } | |
2050 | ||
2051 | mcc_compl->flags = 0; | |
2052 | queue_tail_inc(mcc_cq); | |
2053 | mcc_compl = queue_tail_node(mcc_cq); | |
2054 | mcc_compl->flags = le32_to_cpu(mcc_compl->flags); | |
2055 | num_processed++; | |
2056 | } | |
2057 | ||
2058 | if (num_processed > 0) | |
2059 | hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1, 0); | |
2060 | ||
2061 | } | |
bfead3b2 | 2062 | |
6763daae JSJ |
2063 | /** |
2064 | * beiscsi_process_cq()- Process the Completion Queue | |
2065 | * @pbe_eq: Event Q on which the Completion has come | |
2066 | * | |
2067 | * return | |
2068 | * Number of Completion Entries processed. | |
2069 | **/ | |
b7ab35b1 | 2070 | unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq) |
6733b39a | 2071 | { |
6733b39a JK |
2072 | struct be_queue_info *cq; |
2073 | struct sol_cqe *sol; | |
2074 | struct dmsg_cqe *dmsg; | |
2075 | unsigned int num_processed = 0; | |
2076 | unsigned int tot_nump = 0; | |
0a513dd8 | 2077 | unsigned short code = 0, cid = 0; |
a7909b39 | 2078 | uint16_t cri_index = 0; |
6733b39a | 2079 | struct beiscsi_conn *beiscsi_conn; |
c2462288 JK |
2080 | struct beiscsi_endpoint *beiscsi_ep; |
2081 | struct iscsi_endpoint *ep; | |
bfead3b2 | 2082 | struct beiscsi_hba *phba; |
6733b39a | 2083 | |
bfead3b2 | 2084 | cq = pbe_eq->cq; |
6733b39a | 2085 | sol = queue_tail_node(cq); |
bfead3b2 | 2086 | phba = pbe_eq->phba; |
6733b39a JK |
2087 | |
2088 | while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] & | |
2089 | CQE_VALID_MASK) { | |
2090 | be_dws_le_to_cpu(sol, sizeof(struct sol_cqe)); | |
2091 | ||
73133261 JSJ |
2092 | code = (sol->dw[offsetof(struct amap_sol_cqe, code) / |
2093 | 32] & CQE_CODE_MASK); | |
2094 | ||
2095 | /* Get the CID */ | |
2c9dfd36 JK |
2096 | if (is_chip_be2_be3r(phba)) { |
2097 | cid = AMAP_GET_BITS(struct amap_sol_cqe, cid, sol); | |
2098 | } else { | |
73133261 JSJ |
2099 | if ((code == DRIVERMSG_NOTIFY) || |
2100 | (code == UNSOL_HDR_NOTIFY) || | |
2101 | (code == UNSOL_DATA_NOTIFY)) | |
2102 | cid = AMAP_GET_BITS( | |
2103 | struct amap_i_t_dpdu_cqe_v2, | |
2104 | cid, sol); | |
2105 | else | |
2106 | cid = AMAP_GET_BITS(struct amap_sol_cqe_v2, | |
2107 | cid, sol); | |
2c9dfd36 | 2108 | } |
32951dd8 | 2109 | |
a7909b39 JK |
2110 | cri_index = BE_GET_CRI_FROM_CID(cid); |
2111 | ep = phba->ep_array[cri_index]; | |
b7ab35b1 JK |
2112 | |
2113 | if (ep == NULL) { | |
2114 | /* connection has already been freed | |
2115 | * just move on to next one | |
2116 | */ | |
2117 | beiscsi_log(phba, KERN_WARNING, | |
2118 | BEISCSI_LOG_INIT, | |
2119 | "BM_%d : proc cqe of disconn ep: cid %d\n", | |
2120 | cid); | |
2121 | goto proc_next_cqe; | |
2122 | } | |
2123 | ||
c2462288 JK |
2124 | beiscsi_ep = ep->dd_data; |
2125 | beiscsi_conn = beiscsi_ep->conn; | |
756d29c8 | 2126 | |
6733b39a | 2127 | if (num_processed >= 32) { |
bfead3b2 | 2128 | hwi_ring_cq_db(phba, cq->id, |
6733b39a JK |
2129 | num_processed, 0, 0); |
2130 | tot_nump += num_processed; | |
2131 | num_processed = 0; | |
2132 | } | |
2133 | ||
0a513dd8 | 2134 | switch (code) { |
6733b39a JK |
2135 | case SOL_CMD_COMPLETE: |
2136 | hwi_complete_cmd(beiscsi_conn, phba, sol); | |
2137 | break; | |
2138 | case DRIVERMSG_NOTIFY: | |
99bc5d55 JSJ |
2139 | beiscsi_log(phba, KERN_INFO, |
2140 | BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, | |
6763daae JSJ |
2141 | "BM_%d : Received %s[%d] on CID : %d\n", |
2142 | cqe_desc[code], code, cid); | |
99bc5d55 | 2143 | |
6733b39a JK |
2144 | dmsg = (struct dmsg_cqe *)sol; |
2145 | hwi_complete_drvr_msgs(beiscsi_conn, phba, sol); | |
2146 | break; | |
2147 | case UNSOL_HDR_NOTIFY: | |
99bc5d55 JSJ |
2148 | beiscsi_log(phba, KERN_INFO, |
2149 | BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, | |
6763daae JSJ |
2150 | "BM_%d : Received %s[%d] on CID : %d\n", |
2151 | cqe_desc[code], code, cid); | |
99bc5d55 | 2152 | |
8f09a3b9 | 2153 | spin_lock_bh(&phba->async_pdu_lock); |
bfead3b2 JK |
2154 | hwi_process_default_pdu_ring(beiscsi_conn, phba, |
2155 | (struct i_t_dpdu_cqe *)sol); | |
8f09a3b9 | 2156 | spin_unlock_bh(&phba->async_pdu_lock); |
bfead3b2 | 2157 | break; |
6733b39a | 2158 | case UNSOL_DATA_NOTIFY: |
99bc5d55 JSJ |
2159 | beiscsi_log(phba, KERN_INFO, |
2160 | BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, | |
6763daae JSJ |
2161 | "BM_%d : Received %s[%d] on CID : %d\n", |
2162 | cqe_desc[code], code, cid); | |
99bc5d55 | 2163 | |
8f09a3b9 | 2164 | spin_lock_bh(&phba->async_pdu_lock); |
6733b39a JK |
2165 | hwi_process_default_pdu_ring(beiscsi_conn, phba, |
2166 | (struct i_t_dpdu_cqe *)sol); | |
8f09a3b9 | 2167 | spin_unlock_bh(&phba->async_pdu_lock); |
6733b39a JK |
2168 | break; |
2169 | case CXN_INVALIDATE_INDEX_NOTIFY: | |
2170 | case CMD_INVALIDATED_NOTIFY: | |
2171 | case CXN_INVALIDATE_NOTIFY: | |
99bc5d55 JSJ |
2172 | beiscsi_log(phba, KERN_ERR, |
2173 | BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, | |
6763daae JSJ |
2174 | "BM_%d : Ignoring %s[%d] on CID : %d\n", |
2175 | cqe_desc[code], code, cid); | |
6733b39a JK |
2176 | break; |
2177 | case SOL_CMD_KILLED_DATA_DIGEST_ERR: | |
2178 | case CMD_KILLED_INVALID_STATSN_RCVD: | |
2179 | case CMD_KILLED_INVALID_R2T_RCVD: | |
2180 | case CMD_CXN_KILLED_LUN_INVALID: | |
2181 | case CMD_CXN_KILLED_ICD_INVALID: | |
2182 | case CMD_CXN_KILLED_ITT_INVALID: | |
2183 | case CMD_CXN_KILLED_SEQ_OUTOFORDER: | |
2184 | case CMD_CXN_KILLED_INVALID_DATASN_RCVD: | |
99bc5d55 JSJ |
2185 | beiscsi_log(phba, KERN_ERR, |
2186 | BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, | |
6763daae JSJ |
2187 | "BM_%d : Cmd Notification %s[%d] on CID : %d\n", |
2188 | cqe_desc[code], code, cid); | |
6733b39a JK |
2189 | break; |
2190 | case UNSOL_DATA_DIGEST_ERROR_NOTIFY: | |
99bc5d55 JSJ |
2191 | beiscsi_log(phba, KERN_ERR, |
2192 | BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, | |
6763daae JSJ |
2193 | "BM_%d : Dropping %s[%d] on DPDU ring on CID : %d\n", |
2194 | cqe_desc[code], code, cid); | |
8f09a3b9 | 2195 | spin_lock_bh(&phba->async_pdu_lock); |
6733b39a JK |
2196 | hwi_flush_default_pdu_buffer(phba, beiscsi_conn, |
2197 | (struct i_t_dpdu_cqe *) sol); | |
8f09a3b9 | 2198 | spin_unlock_bh(&phba->async_pdu_lock); |
6733b39a JK |
2199 | break; |
2200 | case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL: | |
2201 | case CXN_KILLED_BURST_LEN_MISMATCH: | |
2202 | case CXN_KILLED_AHS_RCVD: | |
2203 | case CXN_KILLED_HDR_DIGEST_ERR: | |
2204 | case CXN_KILLED_UNKNOWN_HDR: | |
2205 | case CXN_KILLED_STALE_ITT_TTT_RCVD: | |
2206 | case CXN_KILLED_INVALID_ITT_TTT_RCVD: | |
2207 | case CXN_KILLED_TIMED_OUT: | |
2208 | case CXN_KILLED_FIN_RCVD: | |
6763daae JSJ |
2209 | case CXN_KILLED_RST_SENT: |
2210 | case CXN_KILLED_RST_RCVD: | |
6733b39a JK |
2211 | case CXN_KILLED_BAD_UNSOL_PDU_RCVD: |
2212 | case CXN_KILLED_BAD_WRB_INDEX_ERROR: | |
2213 | case CXN_KILLED_OVER_RUN_RESIDUAL: | |
2214 | case CXN_KILLED_UNDER_RUN_RESIDUAL: | |
2215 | case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN: | |
99bc5d55 JSJ |
2216 | beiscsi_log(phba, KERN_ERR, |
2217 | BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, | |
6763daae JSJ |
2218 | "BM_%d : Event %s[%d] received on CID : %d\n", |
2219 | cqe_desc[code], code, cid); | |
0a513dd8 JSJ |
2220 | if (beiscsi_conn) |
2221 | iscsi_conn_failure(beiscsi_conn->conn, | |
2222 | ISCSI_ERR_CONN_FAILED); | |
6733b39a JK |
2223 | break; |
2224 | default: | |
99bc5d55 JSJ |
2225 | beiscsi_log(phba, KERN_ERR, |
2226 | BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, | |
6763daae JSJ |
2227 | "BM_%d : Invalid CQE Event Received Code : %d" |
2228 | "CID 0x%x...\n", | |
0a513dd8 | 2229 | code, cid); |
6733b39a JK |
2230 | break; |
2231 | } | |
2232 | ||
b7ab35b1 | 2233 | proc_next_cqe: |
6733b39a JK |
2234 | AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0); |
2235 | queue_tail_inc(cq); | |
2236 | sol = queue_tail_node(cq); | |
2237 | num_processed++; | |
2238 | } | |
2239 | ||
2240 | if (num_processed > 0) { | |
2241 | tot_nump += num_processed; | |
bfead3b2 | 2242 | hwi_ring_cq_db(phba, cq->id, num_processed, 1, 0); |
6733b39a JK |
2243 | } |
2244 | return tot_nump; | |
2245 | } | |
2246 | ||
756d29c8 | 2247 | void beiscsi_process_all_cqs(struct work_struct *work) |
6733b39a JK |
2248 | { |
2249 | unsigned long flags; | |
bfead3b2 JK |
2250 | struct hwi_controller *phwi_ctrlr; |
2251 | struct hwi_context_memory *phwi_context; | |
72fb46a9 JSJ |
2252 | struct beiscsi_hba *phba; |
2253 | struct be_eq_obj *pbe_eq = | |
2254 | container_of(work, struct be_eq_obj, work_cqs); | |
6733b39a | 2255 | |
72fb46a9 | 2256 | phba = pbe_eq->phba; |
bfead3b2 JK |
2257 | phwi_ctrlr = phba->phwi_ctrlr; |
2258 | phwi_context = phwi_ctrlr->phwi_ctxt; | |
bfead3b2 | 2259 | |
72fb46a9 | 2260 | if (pbe_eq->todo_mcc_cq) { |
6733b39a | 2261 | spin_lock_irqsave(&phba->isr_lock, flags); |
72fb46a9 | 2262 | pbe_eq->todo_mcc_cq = false; |
6733b39a | 2263 | spin_unlock_irqrestore(&phba->isr_lock, flags); |
756d29c8 | 2264 | beiscsi_process_mcc_isr(phba); |
6733b39a JK |
2265 | } |
2266 | ||
72fb46a9 | 2267 | if (pbe_eq->todo_cq) { |
6733b39a | 2268 | spin_lock_irqsave(&phba->isr_lock, flags); |
72fb46a9 | 2269 | pbe_eq->todo_cq = false; |
6733b39a | 2270 | spin_unlock_irqrestore(&phba->isr_lock, flags); |
bfead3b2 | 2271 | beiscsi_process_cq(pbe_eq); |
6733b39a | 2272 | } |
72fb46a9 JSJ |
2273 | |
2274 | /* rearm EQ for further interrupts */ | |
2275 | hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1); | |
6733b39a JK |
2276 | } |
2277 | ||
2278 | static int be_iopoll(struct blk_iopoll *iop, int budget) | |
2279 | { | |
ad3f428e | 2280 | unsigned int ret; |
6733b39a | 2281 | struct beiscsi_hba *phba; |
bfead3b2 | 2282 | struct be_eq_obj *pbe_eq; |
6733b39a | 2283 | |
bfead3b2 JK |
2284 | pbe_eq = container_of(iop, struct be_eq_obj, iopoll); |
2285 | ret = beiscsi_process_cq(pbe_eq); | |
73af08e1 | 2286 | pbe_eq->cq_count += ret; |
6733b39a | 2287 | if (ret < budget) { |
bfead3b2 | 2288 | phba = pbe_eq->phba; |
6733b39a | 2289 | blk_iopoll_complete(iop); |
99bc5d55 JSJ |
2290 | beiscsi_log(phba, KERN_INFO, |
2291 | BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, | |
2292 | "BM_%d : rearm pbe_eq->q.id =%d\n", | |
2293 | pbe_eq->q.id); | |
bfead3b2 | 2294 | hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1); |
6733b39a JK |
2295 | } |
2296 | return ret; | |
2297 | } | |
2298 | ||
09a1093a JSJ |
2299 | static void |
2300 | hwi_write_sgl_v2(struct iscsi_wrb *pwrb, struct scatterlist *sg, | |
2301 | unsigned int num_sg, struct beiscsi_io_task *io_task) | |
2302 | { | |
2303 | struct iscsi_sge *psgl; | |
2304 | unsigned int sg_len, index; | |
2305 | unsigned int sge_len = 0; | |
2306 | unsigned long long addr; | |
2307 | struct scatterlist *l_sg; | |
2308 | unsigned int offset; | |
2309 | ||
2310 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_lo, pwrb, | |
2311 | io_task->bhs_pa.u.a32.address_lo); | |
2312 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_hi, pwrb, | |
2313 | io_task->bhs_pa.u.a32.address_hi); | |
2314 | ||
2315 | l_sg = sg; | |
2316 | for (index = 0; (index < num_sg) && (index < 2); index++, | |
2317 | sg = sg_next(sg)) { | |
2318 | if (index == 0) { | |
2319 | sg_len = sg_dma_len(sg); | |
2320 | addr = (u64) sg_dma_address(sg); | |
2321 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, | |
2322 | sge0_addr_lo, pwrb, | |
2323 | lower_32_bits(addr)); | |
2324 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, | |
2325 | sge0_addr_hi, pwrb, | |
2326 | upper_32_bits(addr)); | |
2327 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, | |
2328 | sge0_len, pwrb, | |
2329 | sg_len); | |
2330 | sge_len = sg_len; | |
2331 | } else { | |
2332 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_r2t_offset, | |
2333 | pwrb, sge_len); | |
2334 | sg_len = sg_dma_len(sg); | |
2335 | addr = (u64) sg_dma_address(sg); | |
2336 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, | |
2337 | sge1_addr_lo, pwrb, | |
2338 | lower_32_bits(addr)); | |
2339 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, | |
2340 | sge1_addr_hi, pwrb, | |
2341 | upper_32_bits(addr)); | |
2342 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, | |
2343 | sge1_len, pwrb, | |
2344 | sg_len); | |
2345 | } | |
2346 | } | |
2347 | psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag; | |
2348 | memset(psgl, 0, sizeof(*psgl) * BE2_SGE); | |
2349 | ||
2350 | AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2); | |
2351 | ||
2352 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, | |
2353 | io_task->bhs_pa.u.a32.address_hi); | |
2354 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, | |
2355 | io_task->bhs_pa.u.a32.address_lo); | |
2356 | ||
2357 | if (num_sg == 1) { | |
2358 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb, | |
2359 | 1); | |
2360 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb, | |
2361 | 0); | |
2362 | } else if (num_sg == 2) { | |
2363 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb, | |
2364 | 0); | |
2365 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb, | |
2366 | 1); | |
2367 | } else { | |
2368 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb, | |
2369 | 0); | |
2370 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb, | |
2371 | 0); | |
2372 | } | |
2373 | ||
2374 | sg = l_sg; | |
2375 | psgl++; | |
2376 | psgl++; | |
2377 | offset = 0; | |
2378 | for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) { | |
2379 | sg_len = sg_dma_len(sg); | |
2380 | addr = (u64) sg_dma_address(sg); | |
2381 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, | |
2382 | lower_32_bits(addr)); | |
2383 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, | |
2384 | upper_32_bits(addr)); | |
2385 | AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len); | |
2386 | AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset); | |
2387 | AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0); | |
2388 | offset += sg_len; | |
2389 | } | |
2390 | psgl--; | |
2391 | AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1); | |
2392 | } | |
2393 | ||
6733b39a JK |
2394 | static void |
2395 | hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg, | |
2396 | unsigned int num_sg, struct beiscsi_io_task *io_task) | |
2397 | { | |
2398 | struct iscsi_sge *psgl; | |
58ff4bd0 | 2399 | unsigned int sg_len, index; |
6733b39a JK |
2400 | unsigned int sge_len = 0; |
2401 | unsigned long long addr; | |
2402 | struct scatterlist *l_sg; | |
2403 | unsigned int offset; | |
2404 | ||
2405 | AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb, | |
2406 | io_task->bhs_pa.u.a32.address_lo); | |
2407 | AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb, | |
2408 | io_task->bhs_pa.u.a32.address_hi); | |
2409 | ||
2410 | l_sg = sg; | |
48bd86cf JK |
2411 | for (index = 0; (index < num_sg) && (index < 2); index++, |
2412 | sg = sg_next(sg)) { | |
6733b39a JK |
2413 | if (index == 0) { |
2414 | sg_len = sg_dma_len(sg); | |
2415 | addr = (u64) sg_dma_address(sg); | |
2416 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb, | |
457ff3b7 | 2417 | ((u32)(addr & 0xFFFFFFFF))); |
6733b39a | 2418 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb, |
457ff3b7 | 2419 | ((u32)(addr >> 32))); |
6733b39a JK |
2420 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb, |
2421 | sg_len); | |
2422 | sge_len = sg_len; | |
6733b39a | 2423 | } else { |
6733b39a JK |
2424 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset, |
2425 | pwrb, sge_len); | |
2426 | sg_len = sg_dma_len(sg); | |
2427 | addr = (u64) sg_dma_address(sg); | |
2428 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb, | |
457ff3b7 | 2429 | ((u32)(addr & 0xFFFFFFFF))); |
6733b39a | 2430 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb, |
457ff3b7 | 2431 | ((u32)(addr >> 32))); |
6733b39a JK |
2432 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb, |
2433 | sg_len); | |
2434 | } | |
2435 | } | |
2436 | psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag; | |
2437 | memset(psgl, 0, sizeof(*psgl) * BE2_SGE); | |
2438 | ||
2439 | AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2); | |
2440 | ||
2441 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, | |
2442 | io_task->bhs_pa.u.a32.address_hi); | |
2443 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, | |
2444 | io_task->bhs_pa.u.a32.address_lo); | |
2445 | ||
caf818f1 JK |
2446 | if (num_sg == 1) { |
2447 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, | |
2448 | 1); | |
2449 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb, | |
2450 | 0); | |
2451 | } else if (num_sg == 2) { | |
2452 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, | |
2453 | 0); | |
2454 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb, | |
2455 | 1); | |
2456 | } else { | |
2457 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, | |
2458 | 0); | |
2459 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb, | |
2460 | 0); | |
2461 | } | |
6733b39a JK |
2462 | sg = l_sg; |
2463 | psgl++; | |
2464 | psgl++; | |
2465 | offset = 0; | |
48bd86cf | 2466 | for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) { |
6733b39a JK |
2467 | sg_len = sg_dma_len(sg); |
2468 | addr = (u64) sg_dma_address(sg); | |
2469 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, | |
2470 | (addr & 0xFFFFFFFF)); | |
2471 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, | |
2472 | (addr >> 32)); | |
2473 | AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len); | |
2474 | AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset); | |
2475 | AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0); | |
2476 | offset += sg_len; | |
2477 | } | |
2478 | psgl--; | |
2479 | AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1); | |
2480 | } | |
2481 | ||
d629c471 JSJ |
2482 | /** |
2483 | * hwi_write_buffer()- Populate the WRB with task info | |
2484 | * @pwrb: ptr to the WRB entry | |
2485 | * @task: iscsi task which is to be executed | |
2486 | **/ | |
6733b39a JK |
2487 | static void hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task) |
2488 | { | |
2489 | struct iscsi_sge *psgl; | |
6733b39a JK |
2490 | struct beiscsi_io_task *io_task = task->dd_data; |
2491 | struct beiscsi_conn *beiscsi_conn = io_task->conn; | |
2492 | struct beiscsi_hba *phba = beiscsi_conn->phba; | |
09a1093a | 2493 | uint8_t dsp_value = 0; |
6733b39a JK |
2494 | |
2495 | io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2; | |
2496 | AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb, | |
2497 | io_task->bhs_pa.u.a32.address_lo); | |
2498 | AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb, | |
2499 | io_task->bhs_pa.u.a32.address_hi); | |
2500 | ||
2501 | if (task->data) { | |
09a1093a JSJ |
2502 | |
2503 | /* Check for the data_count */ | |
2504 | dsp_value = (task->data_count) ? 1 : 0; | |
2505 | ||
2c9dfd36 JK |
2506 | if (is_chip_be2_be3r(phba)) |
2507 | AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, | |
09a1093a JSJ |
2508 | pwrb, dsp_value); |
2509 | else | |
2c9dfd36 | 2510 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, |
09a1093a JSJ |
2511 | pwrb, dsp_value); |
2512 | ||
2513 | /* Map addr only if there is data_count */ | |
2514 | if (dsp_value) { | |
d629c471 JSJ |
2515 | io_task->mtask_addr = pci_map_single(phba->pcidev, |
2516 | task->data, | |
2517 | task->data_count, | |
2518 | PCI_DMA_TODEVICE); | |
d629c471 | 2519 | io_task->mtask_data_count = task->data_count; |
09a1093a | 2520 | } else |
d629c471 | 2521 | io_task->mtask_addr = 0; |
09a1093a | 2522 | |
6733b39a | 2523 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb, |
d629c471 | 2524 | lower_32_bits(io_task->mtask_addr)); |
6733b39a | 2525 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb, |
d629c471 | 2526 | upper_32_bits(io_task->mtask_addr)); |
6733b39a JK |
2527 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb, |
2528 | task->data_count); | |
2529 | ||
2530 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1); | |
2531 | } else { | |
2532 | AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0); | |
d629c471 | 2533 | io_task->mtask_addr = 0; |
6733b39a JK |
2534 | } |
2535 | ||
2536 | psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag; | |
2537 | ||
2538 | AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len); | |
2539 | ||
2540 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, | |
2541 | io_task->bhs_pa.u.a32.address_hi); | |
2542 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, | |
2543 | io_task->bhs_pa.u.a32.address_lo); | |
2544 | if (task->data) { | |
2545 | psgl++; | |
2546 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0); | |
2547 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0); | |
2548 | AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0); | |
2549 | AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0); | |
2550 | AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0); | |
2551 | AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0); | |
2552 | ||
2553 | psgl++; | |
2554 | if (task->data) { | |
2555 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, | |
d629c471 | 2556 | lower_32_bits(io_task->mtask_addr)); |
6733b39a | 2557 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, |
d629c471 | 2558 | upper_32_bits(io_task->mtask_addr)); |
6733b39a JK |
2559 | } |
2560 | AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106); | |
2561 | } | |
2562 | AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1); | |
2563 | } | |
2564 | ||
843ae752 JK |
2565 | /** |
2566 | * beiscsi_find_mem_req()- Find mem needed | |
2567 | * @phba: ptr to HBA struct | |
2568 | **/ | |
6733b39a JK |
2569 | static void beiscsi_find_mem_req(struct beiscsi_hba *phba) |
2570 | { | |
8a86e833 | 2571 | uint8_t mem_descr_index, ulp_num; |
bfead3b2 | 2572 | unsigned int num_cq_pages, num_async_pdu_buf_pages; |
6733b39a JK |
2573 | unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn; |
2574 | unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages; | |
2575 | ||
2576 | num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \ | |
2577 | sizeof(struct sol_cqe)); | |
6733b39a JK |
2578 | |
2579 | phba->params.hwi_ws_sz = sizeof(struct hwi_controller); | |
2580 | ||
2581 | phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 * | |
2582 | BE_ISCSI_PDU_HEADER_SIZE; | |
2583 | phba->mem_req[HWI_MEM_ADDN_CONTEXT] = | |
2584 | sizeof(struct hwi_context_memory); | |
2585 | ||
6733b39a JK |
2586 | |
2587 | phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb) | |
2588 | * (phba->params.wrbs_per_cxn) | |
2589 | * phba->params.cxns_per_ctrl; | |
2590 | wrb_sz_per_cxn = sizeof(struct wrb_handle) * | |
2591 | (phba->params.wrbs_per_cxn); | |
2592 | phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) * | |
2593 | phba->params.cxns_per_ctrl); | |
2594 | ||
2595 | phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) * | |
2596 | phba->params.icds_per_ctrl; | |
2597 | phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) * | |
2598 | phba->params.num_sge_per_io * phba->params.icds_per_ctrl; | |
8a86e833 JK |
2599 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { |
2600 | if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { | |
6733b39a | 2601 | |
8a86e833 JK |
2602 | num_async_pdu_buf_sgl_pages = |
2603 | PAGES_REQUIRED(BEISCSI_GET_CID_COUNT( | |
2604 | phba, ulp_num) * | |
2605 | sizeof(struct phys_addr)); | |
2606 | ||
2607 | num_async_pdu_buf_pages = | |
2608 | PAGES_REQUIRED(BEISCSI_GET_CID_COUNT( | |
2609 | phba, ulp_num) * | |
2610 | phba->params.defpdu_hdr_sz); | |
2611 | ||
2612 | num_async_pdu_data_pages = | |
2613 | PAGES_REQUIRED(BEISCSI_GET_CID_COUNT( | |
2614 | phba, ulp_num) * | |
2615 | phba->params.defpdu_data_sz); | |
2616 | ||
2617 | num_async_pdu_data_sgl_pages = | |
2618 | PAGES_REQUIRED(BEISCSI_GET_CID_COUNT( | |
2619 | phba, ulp_num) * | |
2620 | sizeof(struct phys_addr)); | |
2621 | ||
a129d92f JK |
2622 | mem_descr_index = (HWI_MEM_TEMPLATE_HDR_ULP0 + |
2623 | (ulp_num * MEM_DESCR_OFFSET)); | |
2624 | phba->mem_req[mem_descr_index] = | |
2625 | BEISCSI_GET_CID_COUNT(phba, ulp_num) * | |
2626 | BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE; | |
2627 | ||
8a86e833 JK |
2628 | mem_descr_index = (HWI_MEM_ASYNC_HEADER_BUF_ULP0 + |
2629 | (ulp_num * MEM_DESCR_OFFSET)); | |
2630 | phba->mem_req[mem_descr_index] = | |
2631 | num_async_pdu_buf_pages * | |
2632 | PAGE_SIZE; | |
2633 | ||
2634 | mem_descr_index = (HWI_MEM_ASYNC_DATA_BUF_ULP0 + | |
2635 | (ulp_num * MEM_DESCR_OFFSET)); | |
2636 | phba->mem_req[mem_descr_index] = | |
2637 | num_async_pdu_data_pages * | |
2638 | PAGE_SIZE; | |
2639 | ||
2640 | mem_descr_index = (HWI_MEM_ASYNC_HEADER_RING_ULP0 + | |
2641 | (ulp_num * MEM_DESCR_OFFSET)); | |
2642 | phba->mem_req[mem_descr_index] = | |
2643 | num_async_pdu_buf_sgl_pages * | |
2644 | PAGE_SIZE; | |
2645 | ||
2646 | mem_descr_index = (HWI_MEM_ASYNC_DATA_RING_ULP0 + | |
2647 | (ulp_num * MEM_DESCR_OFFSET)); | |
2648 | phba->mem_req[mem_descr_index] = | |
2649 | num_async_pdu_data_sgl_pages * | |
2650 | PAGE_SIZE; | |
2651 | ||
2652 | mem_descr_index = (HWI_MEM_ASYNC_HEADER_HANDLE_ULP0 + | |
2653 | (ulp_num * MEM_DESCR_OFFSET)); | |
2654 | phba->mem_req[mem_descr_index] = | |
2655 | BEISCSI_GET_CID_COUNT(phba, ulp_num) * | |
2656 | sizeof(struct async_pdu_handle); | |
2657 | ||
2658 | mem_descr_index = (HWI_MEM_ASYNC_DATA_HANDLE_ULP0 + | |
2659 | (ulp_num * MEM_DESCR_OFFSET)); | |
2660 | phba->mem_req[mem_descr_index] = | |
2661 | BEISCSI_GET_CID_COUNT(phba, ulp_num) * | |
2662 | sizeof(struct async_pdu_handle); | |
2663 | ||
2664 | mem_descr_index = (HWI_MEM_ASYNC_PDU_CONTEXT_ULP0 + | |
2665 | (ulp_num * MEM_DESCR_OFFSET)); | |
2666 | phba->mem_req[mem_descr_index] = | |
2667 | sizeof(struct hwi_async_pdu_context) + | |
2668 | (BEISCSI_GET_CID_COUNT(phba, ulp_num) * | |
2669 | sizeof(struct hwi_async_entry)); | |
2670 | } | |
2671 | } | |
6733b39a JK |
2672 | } |
2673 | ||
2674 | static int beiscsi_alloc_mem(struct beiscsi_hba *phba) | |
2675 | { | |
6733b39a | 2676 | dma_addr_t bus_add; |
a7909b39 JK |
2677 | struct hwi_controller *phwi_ctrlr; |
2678 | struct be_mem_descriptor *mem_descr; | |
6733b39a JK |
2679 | struct mem_array *mem_arr, *mem_arr_orig; |
2680 | unsigned int i, j, alloc_size, curr_alloc_size; | |
2681 | ||
3ec78271 | 2682 | phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL); |
6733b39a JK |
2683 | if (!phba->phwi_ctrlr) |
2684 | return -ENOMEM; | |
2685 | ||
a7909b39 JK |
2686 | /* Allocate memory for wrb_context */ |
2687 | phwi_ctrlr = phba->phwi_ctrlr; | |
2688 | phwi_ctrlr->wrb_context = kzalloc(sizeof(struct hwi_wrb_context) * | |
2689 | phba->params.cxns_per_ctrl, | |
2690 | GFP_KERNEL); | |
2691 | if (!phwi_ctrlr->wrb_context) | |
2692 | return -ENOMEM; | |
2693 | ||
6733b39a JK |
2694 | phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr), |
2695 | GFP_KERNEL); | |
2696 | if (!phba->init_mem) { | |
a7909b39 | 2697 | kfree(phwi_ctrlr->wrb_context); |
6733b39a JK |
2698 | kfree(phba->phwi_ctrlr); |
2699 | return -ENOMEM; | |
2700 | } | |
2701 | ||
2702 | mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT, | |
2703 | GFP_KERNEL); | |
2704 | if (!mem_arr_orig) { | |
2705 | kfree(phba->init_mem); | |
a7909b39 | 2706 | kfree(phwi_ctrlr->wrb_context); |
6733b39a JK |
2707 | kfree(phba->phwi_ctrlr); |
2708 | return -ENOMEM; | |
2709 | } | |
2710 | ||
2711 | mem_descr = phba->init_mem; | |
2712 | for (i = 0; i < SE_MEM_MAX; i++) { | |
8a86e833 JK |
2713 | if (!phba->mem_req[i]) { |
2714 | mem_descr->mem_array = NULL; | |
2715 | mem_descr++; | |
2716 | continue; | |
2717 | } | |
2718 | ||
6733b39a JK |
2719 | j = 0; |
2720 | mem_arr = mem_arr_orig; | |
2721 | alloc_size = phba->mem_req[i]; | |
2722 | memset(mem_arr, 0, sizeof(struct mem_array) * | |
2723 | BEISCSI_MAX_FRAGS_INIT); | |
2724 | curr_alloc_size = min(be_max_phys_size * 1024, alloc_size); | |
2725 | do { | |
2726 | mem_arr->virtual_address = pci_alloc_consistent( | |
2727 | phba->pcidev, | |
2728 | curr_alloc_size, | |
2729 | &bus_add); | |
2730 | if (!mem_arr->virtual_address) { | |
2731 | if (curr_alloc_size <= BE_MIN_MEM_SIZE) | |
2732 | goto free_mem; | |
2733 | if (curr_alloc_size - | |
2734 | rounddown_pow_of_two(curr_alloc_size)) | |
2735 | curr_alloc_size = rounddown_pow_of_two | |
2736 | (curr_alloc_size); | |
2737 | else | |
2738 | curr_alloc_size = curr_alloc_size / 2; | |
2739 | } else { | |
2740 | mem_arr->bus_address.u. | |
2741 | a64.address = (__u64) bus_add; | |
2742 | mem_arr->size = curr_alloc_size; | |
2743 | alloc_size -= curr_alloc_size; | |
2744 | curr_alloc_size = min(be_max_phys_size * | |
2745 | 1024, alloc_size); | |
2746 | j++; | |
2747 | mem_arr++; | |
2748 | } | |
2749 | } while (alloc_size); | |
2750 | mem_descr->num_elements = j; | |
2751 | mem_descr->size_in_bytes = phba->mem_req[i]; | |
2752 | mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j, | |
2753 | GFP_KERNEL); | |
2754 | if (!mem_descr->mem_array) | |
2755 | goto free_mem; | |
2756 | ||
2757 | memcpy(mem_descr->mem_array, mem_arr_orig, | |
2758 | sizeof(struct mem_array) * j); | |
2759 | mem_descr++; | |
2760 | } | |
2761 | kfree(mem_arr_orig); | |
2762 | return 0; | |
2763 | free_mem: | |
2764 | mem_descr->num_elements = j; | |
2765 | while ((i) || (j)) { | |
2766 | for (j = mem_descr->num_elements; j > 0; j--) { | |
2767 | pci_free_consistent(phba->pcidev, | |
2768 | mem_descr->mem_array[j - 1].size, | |
2769 | mem_descr->mem_array[j - 1]. | |
2770 | virtual_address, | |
457ff3b7 JK |
2771 | (unsigned long)mem_descr-> |
2772 | mem_array[j - 1]. | |
6733b39a JK |
2773 | bus_address.u.a64.address); |
2774 | } | |
2775 | if (i) { | |
2776 | i--; | |
2777 | kfree(mem_descr->mem_array); | |
2778 | mem_descr--; | |
2779 | } | |
2780 | } | |
2781 | kfree(mem_arr_orig); | |
2782 | kfree(phba->init_mem); | |
a7909b39 | 2783 | kfree(phba->phwi_ctrlr->wrb_context); |
6733b39a JK |
2784 | kfree(phba->phwi_ctrlr); |
2785 | return -ENOMEM; | |
2786 | } | |
2787 | ||
2788 | static int beiscsi_get_memory(struct beiscsi_hba *phba) | |
2789 | { | |
2790 | beiscsi_find_mem_req(phba); | |
2791 | return beiscsi_alloc_mem(phba); | |
2792 | } | |
2793 | ||
2794 | static void iscsi_init_global_templates(struct beiscsi_hba *phba) | |
2795 | { | |
2796 | struct pdu_data_out *pdata_out; | |
2797 | struct pdu_nop_out *pnop_out; | |
2798 | struct be_mem_descriptor *mem_descr; | |
2799 | ||
2800 | mem_descr = phba->init_mem; | |
2801 | mem_descr += ISCSI_MEM_GLOBAL_HEADER; | |
2802 | pdata_out = | |
2803 | (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address; | |
2804 | memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE); | |
2805 | ||
2806 | AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out, | |
2807 | IIOC_SCSI_DATA); | |
2808 | ||
2809 | pnop_out = | |
2810 | (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0]. | |
2811 | virtual_address + BE_ISCSI_PDU_HEADER_SIZE); | |
2812 | ||
2813 | memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE); | |
2814 | AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF); | |
2815 | AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1); | |
2816 | AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0); | |
2817 | } | |
2818 | ||
3ec78271 | 2819 | static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba) |
6733b39a JK |
2820 | { |
2821 | struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb; | |
a7909b39 | 2822 | struct hwi_context_memory *phwi_ctxt; |
3ec78271 | 2823 | struct wrb_handle *pwrb_handle = NULL; |
6733b39a JK |
2824 | struct hwi_controller *phwi_ctrlr; |
2825 | struct hwi_wrb_context *pwrb_context; | |
3ec78271 JK |
2826 | struct iscsi_wrb *pwrb = NULL; |
2827 | unsigned int num_cxn_wrbh = 0; | |
2828 | unsigned int num_cxn_wrb = 0, j, idx = 0, index; | |
6733b39a JK |
2829 | |
2830 | mem_descr_wrbh = phba->init_mem; | |
2831 | mem_descr_wrbh += HWI_MEM_WRBH; | |
2832 | ||
2833 | mem_descr_wrb = phba->init_mem; | |
2834 | mem_descr_wrb += HWI_MEM_WRB; | |
6733b39a JK |
2835 | phwi_ctrlr = phba->phwi_ctrlr; |
2836 | ||
a7909b39 JK |
2837 | /* Allocate memory for WRBQ */ |
2838 | phwi_ctxt = phwi_ctrlr->phwi_ctxt; | |
2839 | phwi_ctxt->be_wrbq = kzalloc(sizeof(struct be_queue_info) * | |
843ae752 | 2840 | phba->params.cxns_per_ctrl, |
a7909b39 JK |
2841 | GFP_KERNEL); |
2842 | if (!phwi_ctxt->be_wrbq) { | |
2843 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
2844 | "BM_%d : WRBQ Mem Alloc Failed\n"); | |
2845 | return -ENOMEM; | |
2846 | } | |
2847 | ||
2848 | for (index = 0; index < phba->params.cxns_per_ctrl; index++) { | |
6733b39a | 2849 | pwrb_context = &phwi_ctrlr->wrb_context[index]; |
6733b39a JK |
2850 | pwrb_context->pwrb_handle_base = |
2851 | kzalloc(sizeof(struct wrb_handle *) * | |
2852 | phba->params.wrbs_per_cxn, GFP_KERNEL); | |
3ec78271 | 2853 | if (!pwrb_context->pwrb_handle_base) { |
99bc5d55 JSJ |
2854 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
2855 | "BM_%d : Mem Alloc Failed. Failing to load\n"); | |
3ec78271 JK |
2856 | goto init_wrb_hndl_failed; |
2857 | } | |
6733b39a JK |
2858 | pwrb_context->pwrb_handle_basestd = |
2859 | kzalloc(sizeof(struct wrb_handle *) * | |
2860 | phba->params.wrbs_per_cxn, GFP_KERNEL); | |
3ec78271 | 2861 | if (!pwrb_context->pwrb_handle_basestd) { |
99bc5d55 JSJ |
2862 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
2863 | "BM_%d : Mem Alloc Failed. Failing to load\n"); | |
3ec78271 JK |
2864 | goto init_wrb_hndl_failed; |
2865 | } | |
2866 | if (!num_cxn_wrbh) { | |
2867 | pwrb_handle = | |
2868 | mem_descr_wrbh->mem_array[idx].virtual_address; | |
2869 | num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) / | |
2870 | ((sizeof(struct wrb_handle)) * | |
2871 | phba->params.wrbs_per_cxn)); | |
2872 | idx++; | |
2873 | } | |
2874 | pwrb_context->alloc_index = 0; | |
2875 | pwrb_context->wrb_handles_available = 0; | |
2876 | pwrb_context->free_index = 0; | |
2877 | ||
6733b39a | 2878 | if (num_cxn_wrbh) { |
6733b39a JK |
2879 | for (j = 0; j < phba->params.wrbs_per_cxn; j++) { |
2880 | pwrb_context->pwrb_handle_base[j] = pwrb_handle; | |
2881 | pwrb_context->pwrb_handle_basestd[j] = | |
2882 | pwrb_handle; | |
2883 | pwrb_context->wrb_handles_available++; | |
bfead3b2 | 2884 | pwrb_handle->wrb_index = j; |
6733b39a JK |
2885 | pwrb_handle++; |
2886 | } | |
6733b39a JK |
2887 | num_cxn_wrbh--; |
2888 | } | |
2889 | } | |
2890 | idx = 0; | |
a7909b39 | 2891 | for (index = 0; index < phba->params.cxns_per_ctrl; index++) { |
6733b39a | 2892 | pwrb_context = &phwi_ctrlr->wrb_context[index]; |
3ec78271 | 2893 | if (!num_cxn_wrb) { |
6733b39a | 2894 | pwrb = mem_descr_wrb->mem_array[idx].virtual_address; |
7c56533c | 2895 | num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) / |
3ec78271 JK |
2896 | ((sizeof(struct iscsi_wrb) * |
2897 | phba->params.wrbs_per_cxn)); | |
2898 | idx++; | |
2899 | } | |
2900 | ||
2901 | if (num_cxn_wrb) { | |
6733b39a JK |
2902 | for (j = 0; j < phba->params.wrbs_per_cxn; j++) { |
2903 | pwrb_handle = pwrb_context->pwrb_handle_base[j]; | |
2904 | pwrb_handle->pwrb = pwrb; | |
2905 | pwrb++; | |
2906 | } | |
2907 | num_cxn_wrb--; | |
2908 | } | |
2909 | } | |
3ec78271 JK |
2910 | return 0; |
2911 | init_wrb_hndl_failed: | |
2912 | for (j = index; j > 0; j--) { | |
2913 | pwrb_context = &phwi_ctrlr->wrb_context[j]; | |
2914 | kfree(pwrb_context->pwrb_handle_base); | |
2915 | kfree(pwrb_context->pwrb_handle_basestd); | |
2916 | } | |
2917 | return -ENOMEM; | |
6733b39a JK |
2918 | } |
2919 | ||
a7909b39 | 2920 | static int hwi_init_async_pdu_ctx(struct beiscsi_hba *phba) |
6733b39a | 2921 | { |
8a86e833 | 2922 | uint8_t ulp_num; |
6733b39a JK |
2923 | struct hwi_controller *phwi_ctrlr; |
2924 | struct hba_parameters *p = &phba->params; | |
2925 | struct hwi_async_pdu_context *pasync_ctx; | |
2926 | struct async_pdu_handle *pasync_header_h, *pasync_data_h; | |
dc63aac6 | 2927 | unsigned int index, idx, num_per_mem, num_async_data; |
6733b39a JK |
2928 | struct be_mem_descriptor *mem_descr; |
2929 | ||
8a86e833 JK |
2930 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { |
2931 | if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { | |
6733b39a | 2932 | |
8a86e833 JK |
2933 | mem_descr = (struct be_mem_descriptor *)phba->init_mem; |
2934 | mem_descr += (HWI_MEM_ASYNC_PDU_CONTEXT_ULP0 + | |
2935 | (ulp_num * MEM_DESCR_OFFSET)); | |
2936 | ||
2937 | phwi_ctrlr = phba->phwi_ctrlr; | |
2938 | phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num] = | |
2939 | (struct hwi_async_pdu_context *) | |
2940 | mem_descr->mem_array[0].virtual_address; | |
2941 | ||
2942 | pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num]; | |
2943 | memset(pasync_ctx, 0, sizeof(*pasync_ctx)); | |
2944 | ||
2945 | pasync_ctx->async_entry = | |
2946 | (struct hwi_async_entry *) | |
2947 | ((long unsigned int)pasync_ctx + | |
2948 | sizeof(struct hwi_async_pdu_context)); | |
2949 | ||
2950 | pasync_ctx->num_entries = BEISCSI_GET_CID_COUNT(phba, | |
2951 | ulp_num); | |
2952 | pasync_ctx->buffer_size = p->defpdu_hdr_sz; | |
2953 | ||
2954 | mem_descr = (struct be_mem_descriptor *)phba->init_mem; | |
2955 | mem_descr += HWI_MEM_ASYNC_HEADER_BUF_ULP0 + | |
2956 | (ulp_num * MEM_DESCR_OFFSET); | |
2957 | if (mem_descr->mem_array[0].virtual_address) { | |
2958 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, | |
2959 | "BM_%d : hwi_init_async_pdu_ctx" | |
2960 | " HWI_MEM_ASYNC_HEADER_BUF_ULP%d va=%p\n", | |
2961 | ulp_num, | |
2962 | mem_descr->mem_array[0]. | |
2963 | virtual_address); | |
2964 | } else | |
2965 | beiscsi_log(phba, KERN_WARNING, | |
2966 | BEISCSI_LOG_INIT, | |
2967 | "BM_%d : No Virtual address for ULP : %d\n", | |
2968 | ulp_num); | |
2969 | ||
2970 | pasync_ctx->async_header.va_base = | |
6733b39a | 2971 | mem_descr->mem_array[0].virtual_address; |
6733b39a | 2972 | |
8a86e833 JK |
2973 | pasync_ctx->async_header.pa_base.u.a64.address = |
2974 | mem_descr->mem_array[0]. | |
2975 | bus_address.u.a64.address; | |
6733b39a | 2976 | |
8a86e833 JK |
2977 | mem_descr = (struct be_mem_descriptor *)phba->init_mem; |
2978 | mem_descr += HWI_MEM_ASYNC_HEADER_RING_ULP0 + | |
2979 | (ulp_num * MEM_DESCR_OFFSET); | |
2980 | if (mem_descr->mem_array[0].virtual_address) { | |
2981 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, | |
2982 | "BM_%d : hwi_init_async_pdu_ctx" | |
2983 | " HWI_MEM_ASYNC_HEADER_RING_ULP%d va=%p\n", | |
2984 | ulp_num, | |
2985 | mem_descr->mem_array[0]. | |
2986 | virtual_address); | |
2987 | } else | |
2988 | beiscsi_log(phba, KERN_WARNING, | |
2989 | BEISCSI_LOG_INIT, | |
2990 | "BM_%d : No Virtual address for ULP : %d\n", | |
2991 | ulp_num); | |
2992 | ||
2993 | pasync_ctx->async_header.ring_base = | |
2994 | mem_descr->mem_array[0].virtual_address; | |
6733b39a | 2995 | |
8a86e833 JK |
2996 | mem_descr = (struct be_mem_descriptor *)phba->init_mem; |
2997 | mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE_ULP0 + | |
2998 | (ulp_num * MEM_DESCR_OFFSET); | |
2999 | if (mem_descr->mem_array[0].virtual_address) { | |
3000 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, | |
3001 | "BM_%d : hwi_init_async_pdu_ctx" | |
3002 | " HWI_MEM_ASYNC_HEADER_HANDLE_ULP%d va=%p\n", | |
3003 | ulp_num, | |
3004 | mem_descr->mem_array[0]. | |
3005 | virtual_address); | |
3006 | } else | |
3007 | beiscsi_log(phba, KERN_WARNING, | |
3008 | BEISCSI_LOG_INIT, | |
3009 | "BM_%d : No Virtual address for ULP : %d\n", | |
3010 | ulp_num); | |
3011 | ||
3012 | pasync_ctx->async_header.handle_base = | |
3013 | mem_descr->mem_array[0].virtual_address; | |
3014 | pasync_ctx->async_header.writables = 0; | |
3015 | INIT_LIST_HEAD(&pasync_ctx->async_header.free_list); | |
3016 | ||
3017 | mem_descr = (struct be_mem_descriptor *)phba->init_mem; | |
3018 | mem_descr += HWI_MEM_ASYNC_DATA_RING_ULP0 + | |
3019 | (ulp_num * MEM_DESCR_OFFSET); | |
3020 | if (mem_descr->mem_array[0].virtual_address) { | |
3021 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, | |
3022 | "BM_%d : hwi_init_async_pdu_ctx" | |
3023 | " HWI_MEM_ASYNC_DATA_RING_ULP%d va=%p\n", | |
3024 | ulp_num, | |
3025 | mem_descr->mem_array[0]. | |
3026 | virtual_address); | |
3027 | } else | |
3028 | beiscsi_log(phba, KERN_WARNING, | |
3029 | BEISCSI_LOG_INIT, | |
3030 | "BM_%d : No Virtual address for ULP : %d\n", | |
3031 | ulp_num); | |
3032 | ||
3033 | pasync_ctx->async_data.ring_base = | |
3034 | mem_descr->mem_array[0].virtual_address; | |
6733b39a | 3035 | |
8a86e833 JK |
3036 | mem_descr = (struct be_mem_descriptor *)phba->init_mem; |
3037 | mem_descr += HWI_MEM_ASYNC_DATA_HANDLE_ULP0 + | |
3038 | (ulp_num * MEM_DESCR_OFFSET); | |
3039 | if (!mem_descr->mem_array[0].virtual_address) | |
3040 | beiscsi_log(phba, KERN_WARNING, | |
3041 | BEISCSI_LOG_INIT, | |
3042 | "BM_%d : No Virtual address for ULP : %d\n", | |
3043 | ulp_num); | |
99bc5d55 | 3044 | |
8a86e833 JK |
3045 | pasync_ctx->async_data.handle_base = |
3046 | mem_descr->mem_array[0].virtual_address; | |
3047 | pasync_ctx->async_data.writables = 0; | |
3048 | INIT_LIST_HEAD(&pasync_ctx->async_data.free_list); | |
3049 | ||
3050 | pasync_header_h = | |
3051 | (struct async_pdu_handle *) | |
3052 | pasync_ctx->async_header.handle_base; | |
3053 | pasync_data_h = | |
3054 | (struct async_pdu_handle *) | |
3055 | pasync_ctx->async_data.handle_base; | |
3056 | ||
3057 | mem_descr = (struct be_mem_descriptor *)phba->init_mem; | |
3058 | mem_descr += HWI_MEM_ASYNC_DATA_BUF_ULP0 + | |
3059 | (ulp_num * MEM_DESCR_OFFSET); | |
3060 | if (mem_descr->mem_array[0].virtual_address) { | |
3061 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, | |
3062 | "BM_%d : hwi_init_async_pdu_ctx" | |
3063 | " HWI_MEM_ASYNC_DATA_BUF_ULP%d va=%p\n", | |
3064 | ulp_num, | |
3065 | mem_descr->mem_array[0]. | |
3066 | virtual_address); | |
3067 | } else | |
3068 | beiscsi_log(phba, KERN_WARNING, | |
3069 | BEISCSI_LOG_INIT, | |
3070 | "BM_%d : No Virtual address for ULP : %d\n", | |
3071 | ulp_num); | |
3072 | ||
3073 | idx = 0; | |
dc63aac6 JK |
3074 | pasync_ctx->async_data.va_base = |
3075 | mem_descr->mem_array[idx].virtual_address; | |
3076 | pasync_ctx->async_data.pa_base.u.a64.address = | |
3077 | mem_descr->mem_array[idx]. | |
3078 | bus_address.u.a64.address; | |
3079 | ||
3080 | num_async_data = ((mem_descr->mem_array[idx].size) / | |
3081 | phba->params.defpdu_data_sz); | |
8a86e833 | 3082 | num_per_mem = 0; |
6733b39a | 3083 | |
8a86e833 JK |
3084 | for (index = 0; index < BEISCSI_GET_CID_COUNT |
3085 | (phba, ulp_num); index++) { | |
3086 | pasync_header_h->cri = -1; | |
3087 | pasync_header_h->index = (char)index; | |
3088 | INIT_LIST_HEAD(&pasync_header_h->link); | |
3089 | pasync_header_h->pbuffer = | |
3090 | (void *)((unsigned long) | |
3091 | (pasync_ctx-> | |
3092 | async_header.va_base) + | |
3093 | (p->defpdu_hdr_sz * index)); | |
3094 | ||
3095 | pasync_header_h->pa.u.a64.address = | |
3096 | pasync_ctx->async_header.pa_base.u.a64. | |
3097 | address + (p->defpdu_hdr_sz * index); | |
3098 | ||
3099 | list_add_tail(&pasync_header_h->link, | |
3100 | &pasync_ctx->async_header. | |
3101 | free_list); | |
3102 | pasync_header_h++; | |
3103 | pasync_ctx->async_header.free_entries++; | |
3104 | pasync_ctx->async_header.writables++; | |
3105 | ||
3106 | INIT_LIST_HEAD(&pasync_ctx->async_entry[index]. | |
3107 | wait_queue.list); | |
3108 | INIT_LIST_HEAD(&pasync_ctx->async_entry[index]. | |
3109 | header_busy_list); | |
3110 | pasync_data_h->cri = -1; | |
3111 | pasync_data_h->index = (char)index; | |
3112 | INIT_LIST_HEAD(&pasync_data_h->link); | |
3113 | ||
3114 | if (!num_async_data) { | |
3115 | num_per_mem = 0; | |
3116 | idx++; | |
3117 | pasync_ctx->async_data.va_base = | |
3118 | mem_descr->mem_array[idx]. | |
3119 | virtual_address; | |
3120 | pasync_ctx->async_data.pa_base.u. | |
3121 | a64.address = | |
3122 | mem_descr->mem_array[idx]. | |
3123 | bus_address.u.a64.address; | |
3124 | num_async_data = | |
3125 | ((mem_descr->mem_array[idx]. | |
3126 | size) / | |
3127 | phba->params.defpdu_data_sz); | |
3128 | } | |
3129 | pasync_data_h->pbuffer = | |
3130 | (void *)((unsigned long) | |
3131 | (pasync_ctx->async_data.va_base) + | |
3132 | (p->defpdu_data_sz * num_per_mem)); | |
3133 | ||
3134 | pasync_data_h->pa.u.a64.address = | |
3135 | pasync_ctx->async_data.pa_base.u.a64. | |
3136 | address + (p->defpdu_data_sz * | |
3137 | num_per_mem); | |
3138 | num_per_mem++; | |
3139 | num_async_data--; | |
3140 | ||
3141 | list_add_tail(&pasync_data_h->link, | |
3142 | &pasync_ctx->async_data. | |
3143 | free_list); | |
3144 | pasync_data_h++; | |
3145 | pasync_ctx->async_data.free_entries++; | |
3146 | pasync_ctx->async_data.writables++; | |
3147 | ||
3148 | INIT_LIST_HEAD(&pasync_ctx->async_entry[index]. | |
3149 | data_busy_list); | |
3150 | } | |
6733b39a | 3151 | |
8a86e833 JK |
3152 | pasync_ctx->async_header.host_write_ptr = 0; |
3153 | pasync_ctx->async_header.ep_read_ptr = -1; | |
3154 | pasync_ctx->async_data.host_write_ptr = 0; | |
3155 | pasync_ctx->async_data.ep_read_ptr = -1; | |
3156 | } | |
6733b39a JK |
3157 | } |
3158 | ||
a7909b39 | 3159 | return 0; |
6733b39a JK |
3160 | } |
3161 | ||
3162 | static int | |
3163 | be_sgl_create_contiguous(void *virtual_address, | |
3164 | u64 physical_address, u32 length, | |
3165 | struct be_dma_mem *sgl) | |
3166 | { | |
3167 | WARN_ON(!virtual_address); | |
3168 | WARN_ON(!physical_address); | |
3169 | WARN_ON(!length > 0); | |
3170 | WARN_ON(!sgl); | |
3171 | ||
3172 | sgl->va = virtual_address; | |
457ff3b7 | 3173 | sgl->dma = (unsigned long)physical_address; |
6733b39a JK |
3174 | sgl->size = length; |
3175 | ||
3176 | return 0; | |
3177 | } | |
3178 | ||
3179 | static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl) | |
3180 | { | |
3181 | memset(sgl, 0, sizeof(*sgl)); | |
3182 | } | |
3183 | ||
3184 | static void | |
3185 | hwi_build_be_sgl_arr(struct beiscsi_hba *phba, | |
3186 | struct mem_array *pmem, struct be_dma_mem *sgl) | |
3187 | { | |
3188 | if (sgl->va) | |
3189 | be_sgl_destroy_contiguous(sgl); | |
3190 | ||
3191 | be_sgl_create_contiguous(pmem->virtual_address, | |
3192 | pmem->bus_address.u.a64.address, | |
3193 | pmem->size, sgl); | |
3194 | } | |
3195 | ||
3196 | static void | |
3197 | hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba, | |
3198 | struct mem_array *pmem, struct be_dma_mem *sgl) | |
3199 | { | |
3200 | if (sgl->va) | |
3201 | be_sgl_destroy_contiguous(sgl); | |
3202 | ||
3203 | be_sgl_create_contiguous((unsigned char *)pmem->virtual_address, | |
3204 | pmem->bus_address.u.a64.address, | |
3205 | pmem->size, sgl); | |
3206 | } | |
3207 | ||
3208 | static int be_fill_queue(struct be_queue_info *q, | |
3209 | u16 len, u16 entry_size, void *vaddress) | |
3210 | { | |
3211 | struct be_dma_mem *mem = &q->dma_mem; | |
3212 | ||
3213 | memset(q, 0, sizeof(*q)); | |
3214 | q->len = len; | |
3215 | q->entry_size = entry_size; | |
3216 | mem->size = len * entry_size; | |
3217 | mem->va = vaddress; | |
3218 | if (!mem->va) | |
3219 | return -ENOMEM; | |
3220 | memset(mem->va, 0, mem->size); | |
3221 | return 0; | |
3222 | } | |
3223 | ||
bfead3b2 | 3224 | static int beiscsi_create_eqs(struct beiscsi_hba *phba, |
6733b39a JK |
3225 | struct hwi_context_memory *phwi_context) |
3226 | { | |
bfead3b2 | 3227 | unsigned int i, num_eq_pages; |
99bc5d55 | 3228 | int ret = 0, eq_for_mcc; |
6733b39a JK |
3229 | struct be_queue_info *eq; |
3230 | struct be_dma_mem *mem; | |
6733b39a | 3231 | void *eq_vaddress; |
bfead3b2 | 3232 | dma_addr_t paddr; |
6733b39a | 3233 | |
bfead3b2 JK |
3234 | num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \ |
3235 | sizeof(struct be_eq_entry)); | |
6733b39a | 3236 | |
bfead3b2 JK |
3237 | if (phba->msix_enabled) |
3238 | eq_for_mcc = 1; | |
3239 | else | |
3240 | eq_for_mcc = 0; | |
3241 | for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) { | |
3242 | eq = &phwi_context->be_eq[i].q; | |
3243 | mem = &eq->dma_mem; | |
3244 | phwi_context->be_eq[i].phba = phba; | |
3245 | eq_vaddress = pci_alloc_consistent(phba->pcidev, | |
3246 | num_eq_pages * PAGE_SIZE, | |
3247 | &paddr); | |
3248 | if (!eq_vaddress) | |
3249 | goto create_eq_error; | |
3250 | ||
3251 | mem->va = eq_vaddress; | |
3252 | ret = be_fill_queue(eq, phba->params.num_eq_entries, | |
3253 | sizeof(struct be_eq_entry), eq_vaddress); | |
3254 | if (ret) { | |
99bc5d55 JSJ |
3255 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3256 | "BM_%d : be_fill_queue Failed for EQ\n"); | |
bfead3b2 JK |
3257 | goto create_eq_error; |
3258 | } | |
6733b39a | 3259 | |
bfead3b2 JK |
3260 | mem->dma = paddr; |
3261 | ret = beiscsi_cmd_eq_create(&phba->ctrl, eq, | |
3262 | phwi_context->cur_eqd); | |
3263 | if (ret) { | |
99bc5d55 JSJ |
3264 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3265 | "BM_%d : beiscsi_cmd_eq_create" | |
3266 | "Failed for EQ\n"); | |
bfead3b2 JK |
3267 | goto create_eq_error; |
3268 | } | |
99bc5d55 JSJ |
3269 | |
3270 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, | |
3271 | "BM_%d : eqid = %d\n", | |
3272 | phwi_context->be_eq[i].q.id); | |
6733b39a | 3273 | } |
6733b39a | 3274 | return 0; |
bfead3b2 | 3275 | create_eq_error: |
107dfcba | 3276 | for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) { |
bfead3b2 JK |
3277 | eq = &phwi_context->be_eq[i].q; |
3278 | mem = &eq->dma_mem; | |
3279 | if (mem->va) | |
3280 | pci_free_consistent(phba->pcidev, num_eq_pages | |
3281 | * PAGE_SIZE, | |
3282 | mem->va, mem->dma); | |
3283 | } | |
3284 | return ret; | |
6733b39a JK |
3285 | } |
3286 | ||
bfead3b2 | 3287 | static int beiscsi_create_cqs(struct beiscsi_hba *phba, |
6733b39a JK |
3288 | struct hwi_context_memory *phwi_context) |
3289 | { | |
bfead3b2 | 3290 | unsigned int i, num_cq_pages; |
99bc5d55 | 3291 | int ret = 0; |
6733b39a JK |
3292 | struct be_queue_info *cq, *eq; |
3293 | struct be_dma_mem *mem; | |
bfead3b2 | 3294 | struct be_eq_obj *pbe_eq; |
6733b39a | 3295 | void *cq_vaddress; |
bfead3b2 | 3296 | dma_addr_t paddr; |
6733b39a | 3297 | |
bfead3b2 JK |
3298 | num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \ |
3299 | sizeof(struct sol_cqe)); | |
6733b39a | 3300 | |
bfead3b2 JK |
3301 | for (i = 0; i < phba->num_cpus; i++) { |
3302 | cq = &phwi_context->be_cq[i]; | |
3303 | eq = &phwi_context->be_eq[i].q; | |
3304 | pbe_eq = &phwi_context->be_eq[i]; | |
3305 | pbe_eq->cq = cq; | |
3306 | pbe_eq->phba = phba; | |
3307 | mem = &cq->dma_mem; | |
3308 | cq_vaddress = pci_alloc_consistent(phba->pcidev, | |
3309 | num_cq_pages * PAGE_SIZE, | |
3310 | &paddr); | |
3311 | if (!cq_vaddress) | |
3312 | goto create_cq_error; | |
7da50879 | 3313 | ret = be_fill_queue(cq, phba->params.num_cq_entries, |
bfead3b2 JK |
3314 | sizeof(struct sol_cqe), cq_vaddress); |
3315 | if (ret) { | |
99bc5d55 JSJ |
3316 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3317 | "BM_%d : be_fill_queue Failed " | |
3318 | "for ISCSI CQ\n"); | |
bfead3b2 JK |
3319 | goto create_cq_error; |
3320 | } | |
3321 | ||
3322 | mem->dma = paddr; | |
3323 | ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false, | |
3324 | false, 0); | |
3325 | if (ret) { | |
99bc5d55 JSJ |
3326 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3327 | "BM_%d : beiscsi_cmd_eq_create" | |
3328 | "Failed for ISCSI CQ\n"); | |
bfead3b2 JK |
3329 | goto create_cq_error; |
3330 | } | |
99bc5d55 JSJ |
3331 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
3332 | "BM_%d : iscsi cq_id is %d for eq_id %d\n" | |
3333 | "iSCSI CQ CREATED\n", cq->id, eq->id); | |
6733b39a | 3334 | } |
6733b39a | 3335 | return 0; |
bfead3b2 JK |
3336 | |
3337 | create_cq_error: | |
3338 | for (i = 0; i < phba->num_cpus; i++) { | |
3339 | cq = &phwi_context->be_cq[i]; | |
3340 | mem = &cq->dma_mem; | |
3341 | if (mem->va) | |
3342 | pci_free_consistent(phba->pcidev, num_cq_pages | |
3343 | * PAGE_SIZE, | |
3344 | mem->va, mem->dma); | |
3345 | } | |
3346 | return ret; | |
3347 | ||
6733b39a JK |
3348 | } |
3349 | ||
3350 | static int | |
3351 | beiscsi_create_def_hdr(struct beiscsi_hba *phba, | |
3352 | struct hwi_context_memory *phwi_context, | |
3353 | struct hwi_controller *phwi_ctrlr, | |
8a86e833 | 3354 | unsigned int def_pdu_ring_sz, uint8_t ulp_num) |
6733b39a JK |
3355 | { |
3356 | unsigned int idx; | |
3357 | int ret; | |
3358 | struct be_queue_info *dq, *cq; | |
3359 | struct be_dma_mem *mem; | |
3360 | struct be_mem_descriptor *mem_descr; | |
3361 | void *dq_vaddress; | |
3362 | ||
3363 | idx = 0; | |
8a86e833 | 3364 | dq = &phwi_context->be_def_hdrq[ulp_num]; |
bfead3b2 | 3365 | cq = &phwi_context->be_cq[0]; |
6733b39a JK |
3366 | mem = &dq->dma_mem; |
3367 | mem_descr = phba->init_mem; | |
8a86e833 JK |
3368 | mem_descr += HWI_MEM_ASYNC_HEADER_RING_ULP0 + |
3369 | (ulp_num * MEM_DESCR_OFFSET); | |
6733b39a JK |
3370 | dq_vaddress = mem_descr->mem_array[idx].virtual_address; |
3371 | ret = be_fill_queue(dq, mem_descr->mem_array[0].size / | |
3372 | sizeof(struct phys_addr), | |
3373 | sizeof(struct phys_addr), dq_vaddress); | |
3374 | if (ret) { | |
99bc5d55 | 3375 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
8a86e833 JK |
3376 | "BM_%d : be_fill_queue Failed for DEF PDU HDR on ULP : %d\n", |
3377 | ulp_num); | |
3378 | ||
6733b39a JK |
3379 | return ret; |
3380 | } | |
457ff3b7 JK |
3381 | mem->dma = (unsigned long)mem_descr->mem_array[idx]. |
3382 | bus_address.u.a64.address; | |
6733b39a JK |
3383 | ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq, |
3384 | def_pdu_ring_sz, | |
8a86e833 JK |
3385 | phba->params.defpdu_hdr_sz, |
3386 | BEISCSI_DEFQ_HDR, ulp_num); | |
6733b39a | 3387 | if (ret) { |
99bc5d55 | 3388 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
8a86e833 JK |
3389 | "BM_%d : be_cmd_create_default_pdu_queue Failed DEFHDR on ULP : %d\n", |
3390 | ulp_num); | |
3391 | ||
6733b39a JK |
3392 | return ret; |
3393 | } | |
99bc5d55 | 3394 | |
8a86e833 JK |
3395 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
3396 | "BM_%d : iscsi hdr def pdu id for ULP : %d is %d\n", | |
3397 | ulp_num, | |
3398 | phwi_context->be_def_hdrq[ulp_num].id); | |
3399 | hwi_post_async_buffers(phba, BEISCSI_DEFQ_HDR, ulp_num); | |
6733b39a JK |
3400 | return 0; |
3401 | } | |
3402 | ||
3403 | static int | |
3404 | beiscsi_create_def_data(struct beiscsi_hba *phba, | |
3405 | struct hwi_context_memory *phwi_context, | |
3406 | struct hwi_controller *phwi_ctrlr, | |
8a86e833 | 3407 | unsigned int def_pdu_ring_sz, uint8_t ulp_num) |
6733b39a JK |
3408 | { |
3409 | unsigned int idx; | |
3410 | int ret; | |
3411 | struct be_queue_info *dataq, *cq; | |
3412 | struct be_dma_mem *mem; | |
3413 | struct be_mem_descriptor *mem_descr; | |
3414 | void *dq_vaddress; | |
3415 | ||
3416 | idx = 0; | |
8a86e833 | 3417 | dataq = &phwi_context->be_def_dataq[ulp_num]; |
bfead3b2 | 3418 | cq = &phwi_context->be_cq[0]; |
6733b39a JK |
3419 | mem = &dataq->dma_mem; |
3420 | mem_descr = phba->init_mem; | |
8a86e833 JK |
3421 | mem_descr += HWI_MEM_ASYNC_DATA_RING_ULP0 + |
3422 | (ulp_num * MEM_DESCR_OFFSET); | |
6733b39a JK |
3423 | dq_vaddress = mem_descr->mem_array[idx].virtual_address; |
3424 | ret = be_fill_queue(dataq, mem_descr->mem_array[0].size / | |
3425 | sizeof(struct phys_addr), | |
3426 | sizeof(struct phys_addr), dq_vaddress); | |
3427 | if (ret) { | |
99bc5d55 | 3428 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
8a86e833 JK |
3429 | "BM_%d : be_fill_queue Failed for DEF PDU " |
3430 | "DATA on ULP : %d\n", | |
3431 | ulp_num); | |
3432 | ||
6733b39a JK |
3433 | return ret; |
3434 | } | |
457ff3b7 JK |
3435 | mem->dma = (unsigned long)mem_descr->mem_array[idx]. |
3436 | bus_address.u.a64.address; | |
6733b39a JK |
3437 | ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq, |
3438 | def_pdu_ring_sz, | |
8a86e833 JK |
3439 | phba->params.defpdu_data_sz, |
3440 | BEISCSI_DEFQ_DATA, ulp_num); | |
6733b39a | 3441 | if (ret) { |
99bc5d55 JSJ |
3442 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3443 | "BM_%d be_cmd_create_default_pdu_queue" | |
8a86e833 JK |
3444 | " Failed for DEF PDU DATA on ULP : %d\n", |
3445 | ulp_num); | |
6733b39a JK |
3446 | return ret; |
3447 | } | |
8a86e833 | 3448 | |
99bc5d55 | 3449 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
8a86e833 JK |
3450 | "BM_%d : iscsi def data id on ULP : %d is %d\n", |
3451 | ulp_num, | |
3452 | phwi_context->be_def_dataq[ulp_num].id); | |
99bc5d55 | 3453 | |
8a86e833 | 3454 | hwi_post_async_buffers(phba, BEISCSI_DEFQ_DATA, ulp_num); |
99bc5d55 | 3455 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
8a86e833 JK |
3456 | "BM_%d : DEFAULT PDU DATA RING CREATED" |
3457 | "on ULP : %d\n", ulp_num); | |
99bc5d55 | 3458 | |
6733b39a JK |
3459 | return 0; |
3460 | } | |
3461 | ||
15a90fe0 JK |
3462 | |
3463 | static int | |
3464 | beiscsi_post_template_hdr(struct beiscsi_hba *phba) | |
3465 | { | |
3466 | struct be_mem_descriptor *mem_descr; | |
3467 | struct mem_array *pm_arr; | |
3468 | struct be_dma_mem sgl; | |
a129d92f | 3469 | int status, ulp_num; |
15a90fe0 | 3470 | |
a129d92f JK |
3471 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { |
3472 | if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { | |
3473 | mem_descr = (struct be_mem_descriptor *)phba->init_mem; | |
3474 | mem_descr += HWI_MEM_TEMPLATE_HDR_ULP0 + | |
3475 | (ulp_num * MEM_DESCR_OFFSET); | |
3476 | pm_arr = mem_descr->mem_array; | |
15a90fe0 | 3477 | |
a129d92f JK |
3478 | hwi_build_be_sgl_arr(phba, pm_arr, &sgl); |
3479 | status = be_cmd_iscsi_post_template_hdr( | |
3480 | &phba->ctrl, &sgl); | |
15a90fe0 | 3481 | |
a129d92f JK |
3482 | if (status != 0) { |
3483 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
3484 | "BM_%d : Post Template HDR Failed for" | |
3485 | "ULP_%d\n", ulp_num); | |
3486 | return status; | |
3487 | } | |
3488 | ||
3489 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, | |
3490 | "BM_%d : Template HDR Pages Posted for" | |
3491 | "ULP_%d\n", ulp_num); | |
15a90fe0 JK |
3492 | } |
3493 | } | |
15a90fe0 JK |
3494 | return 0; |
3495 | } | |
3496 | ||
6733b39a JK |
3497 | static int |
3498 | beiscsi_post_pages(struct beiscsi_hba *phba) | |
3499 | { | |
3500 | struct be_mem_descriptor *mem_descr; | |
3501 | struct mem_array *pm_arr; | |
3502 | unsigned int page_offset, i; | |
3503 | struct be_dma_mem sgl; | |
843ae752 | 3504 | int status, ulp_num = 0; |
6733b39a JK |
3505 | |
3506 | mem_descr = phba->init_mem; | |
3507 | mem_descr += HWI_MEM_SGE; | |
3508 | pm_arr = mem_descr->mem_array; | |
3509 | ||
90622db3 JK |
3510 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) |
3511 | if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) | |
3512 | break; | |
3513 | ||
6733b39a | 3514 | page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io * |
843ae752 | 3515 | phba->fw_config.iscsi_icd_start[ulp_num]) / PAGE_SIZE; |
6733b39a JK |
3516 | for (i = 0; i < mem_descr->num_elements; i++) { |
3517 | hwi_build_be_sgl_arr(phba, pm_arr, &sgl); | |
3518 | status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl, | |
3519 | page_offset, | |
3520 | (pm_arr->size / PAGE_SIZE)); | |
3521 | page_offset += pm_arr->size / PAGE_SIZE; | |
3522 | if (status != 0) { | |
99bc5d55 JSJ |
3523 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3524 | "BM_%d : post sgl failed.\n"); | |
6733b39a JK |
3525 | return status; |
3526 | } | |
3527 | pm_arr++; | |
3528 | } | |
99bc5d55 JSJ |
3529 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
3530 | "BM_%d : POSTED PAGES\n"); | |
6733b39a JK |
3531 | return 0; |
3532 | } | |
3533 | ||
bfead3b2 JK |
3534 | static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q) |
3535 | { | |
3536 | struct be_dma_mem *mem = &q->dma_mem; | |
c8b25598 | 3537 | if (mem->va) { |
bfead3b2 JK |
3538 | pci_free_consistent(phba->pcidev, mem->size, |
3539 | mem->va, mem->dma); | |
c8b25598 JK |
3540 | mem->va = NULL; |
3541 | } | |
bfead3b2 JK |
3542 | } |
3543 | ||
3544 | static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q, | |
3545 | u16 len, u16 entry_size) | |
3546 | { | |
3547 | struct be_dma_mem *mem = &q->dma_mem; | |
3548 | ||
3549 | memset(q, 0, sizeof(*q)); | |
3550 | q->len = len; | |
3551 | q->entry_size = entry_size; | |
3552 | mem->size = len * entry_size; | |
7c845eb5 | 3553 | mem->va = pci_zalloc_consistent(phba->pcidev, mem->size, &mem->dma); |
bfead3b2 | 3554 | if (!mem->va) |
d3ad2bb3 | 3555 | return -ENOMEM; |
bfead3b2 JK |
3556 | return 0; |
3557 | } | |
3558 | ||
6733b39a JK |
3559 | static int |
3560 | beiscsi_create_wrb_rings(struct beiscsi_hba *phba, | |
3561 | struct hwi_context_memory *phwi_context, | |
3562 | struct hwi_controller *phwi_ctrlr) | |
3563 | { | |
3564 | unsigned int wrb_mem_index, offset, size, num_wrb_rings; | |
3565 | u64 pa_addr_lo; | |
4eea99d5 | 3566 | unsigned int idx, num, i, ulp_num; |
6733b39a JK |
3567 | struct mem_array *pwrb_arr; |
3568 | void *wrb_vaddr; | |
3569 | struct be_dma_mem sgl; | |
3570 | struct be_mem_descriptor *mem_descr; | |
a7909b39 | 3571 | struct hwi_wrb_context *pwrb_context; |
6733b39a | 3572 | int status; |
4eea99d5 JK |
3573 | uint8_t ulp_count = 0, ulp_base_num = 0; |
3574 | uint16_t cid_count_ulp[BEISCSI_ULP_COUNT] = { 0 }; | |
6733b39a JK |
3575 | |
3576 | idx = 0; | |
3577 | mem_descr = phba->init_mem; | |
3578 | mem_descr += HWI_MEM_WRB; | |
3579 | pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl, | |
3580 | GFP_KERNEL); | |
3581 | if (!pwrb_arr) { | |
99bc5d55 JSJ |
3582 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3583 | "BM_%d : Memory alloc failed in create wrb ring.\n"); | |
6733b39a JK |
3584 | return -ENOMEM; |
3585 | } | |
3586 | wrb_vaddr = mem_descr->mem_array[idx].virtual_address; | |
3587 | pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address; | |
3588 | num_wrb_rings = mem_descr->mem_array[idx].size / | |
3589 | (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb)); | |
3590 | ||
3591 | for (num = 0; num < phba->params.cxns_per_ctrl; num++) { | |
3592 | if (num_wrb_rings) { | |
3593 | pwrb_arr[num].virtual_address = wrb_vaddr; | |
3594 | pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo; | |
3595 | pwrb_arr[num].size = phba->params.wrbs_per_cxn * | |
3596 | sizeof(struct iscsi_wrb); | |
3597 | wrb_vaddr += pwrb_arr[num].size; | |
3598 | pa_addr_lo += pwrb_arr[num].size; | |
3599 | num_wrb_rings--; | |
3600 | } else { | |
3601 | idx++; | |
3602 | wrb_vaddr = mem_descr->mem_array[idx].virtual_address; | |
3603 | pa_addr_lo = mem_descr->mem_array[idx].\ | |
3604 | bus_address.u.a64.address; | |
3605 | num_wrb_rings = mem_descr->mem_array[idx].size / | |
3606 | (phba->params.wrbs_per_cxn * | |
3607 | sizeof(struct iscsi_wrb)); | |
3608 | pwrb_arr[num].virtual_address = wrb_vaddr; | |
3609 | pwrb_arr[num].bus_address.u.a64.address\ | |
3610 | = pa_addr_lo; | |
3611 | pwrb_arr[num].size = phba->params.wrbs_per_cxn * | |
3612 | sizeof(struct iscsi_wrb); | |
3613 | wrb_vaddr += pwrb_arr[num].size; | |
3614 | pa_addr_lo += pwrb_arr[num].size; | |
3615 | num_wrb_rings--; | |
3616 | } | |
3617 | } | |
4eea99d5 JK |
3618 | |
3619 | /* Get the ULP Count */ | |
3620 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) | |
3621 | if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { | |
3622 | ulp_count++; | |
3623 | ulp_base_num = ulp_num; | |
3624 | cid_count_ulp[ulp_num] = | |
3625 | BEISCSI_GET_CID_COUNT(phba, ulp_num); | |
3626 | } | |
3627 | ||
6733b39a JK |
3628 | for (i = 0; i < phba->params.cxns_per_ctrl; i++) { |
3629 | wrb_mem_index = 0; | |
3630 | offset = 0; | |
3631 | size = 0; | |
3632 | ||
4eea99d5 JK |
3633 | if (ulp_count > 1) { |
3634 | ulp_base_num = (ulp_base_num + 1) % BEISCSI_ULP_COUNT; | |
3635 | ||
3636 | if (!cid_count_ulp[ulp_base_num]) | |
3637 | ulp_base_num = (ulp_base_num + 1) % | |
3638 | BEISCSI_ULP_COUNT; | |
3639 | ||
3640 | cid_count_ulp[ulp_base_num]--; | |
3641 | } | |
3642 | ||
3643 | ||
6733b39a JK |
3644 | hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl); |
3645 | status = be_cmd_wrbq_create(&phba->ctrl, &sgl, | |
4eea99d5 JK |
3646 | &phwi_context->be_wrbq[i], |
3647 | &phwi_ctrlr->wrb_context[i], | |
3648 | ulp_base_num); | |
6733b39a | 3649 | if (status != 0) { |
99bc5d55 JSJ |
3650 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3651 | "BM_%d : wrbq create failed."); | |
1462b8ff | 3652 | kfree(pwrb_arr); |
6733b39a JK |
3653 | return status; |
3654 | } | |
a7909b39 | 3655 | pwrb_context = &phwi_ctrlr->wrb_context[i]; |
a7909b39 | 3656 | BE_SET_CID_TO_CRI(i, pwrb_context->cid); |
6733b39a JK |
3657 | } |
3658 | kfree(pwrb_arr); | |
3659 | return 0; | |
3660 | } | |
3661 | ||
3662 | static void free_wrb_handles(struct beiscsi_hba *phba) | |
3663 | { | |
3664 | unsigned int index; | |
3665 | struct hwi_controller *phwi_ctrlr; | |
3666 | struct hwi_wrb_context *pwrb_context; | |
3667 | ||
3668 | phwi_ctrlr = phba->phwi_ctrlr; | |
a7909b39 | 3669 | for (index = 0; index < phba->params.cxns_per_ctrl; index++) { |
6733b39a JK |
3670 | pwrb_context = &phwi_ctrlr->wrb_context[index]; |
3671 | kfree(pwrb_context->pwrb_handle_base); | |
3672 | kfree(pwrb_context->pwrb_handle_basestd); | |
3673 | } | |
3674 | } | |
3675 | ||
bfead3b2 JK |
3676 | static void be_mcc_queues_destroy(struct beiscsi_hba *phba) |
3677 | { | |
3678 | struct be_queue_info *q; | |
3679 | struct be_ctrl_info *ctrl = &phba->ctrl; | |
3680 | ||
3681 | q = &phba->ctrl.mcc_obj.q; | |
3682 | if (q->created) | |
3683 | beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ); | |
3684 | be_queue_free(phba, q); | |
3685 | ||
3686 | q = &phba->ctrl.mcc_obj.cq; | |
3687 | if (q->created) | |
3688 | beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ); | |
3689 | be_queue_free(phba, q); | |
3690 | } | |
3691 | ||
6733b39a JK |
3692 | static void hwi_cleanup(struct beiscsi_hba *phba) |
3693 | { | |
3694 | struct be_queue_info *q; | |
3695 | struct be_ctrl_info *ctrl = &phba->ctrl; | |
3696 | struct hwi_controller *phwi_ctrlr; | |
3697 | struct hwi_context_memory *phwi_context; | |
a7909b39 | 3698 | struct hwi_async_pdu_context *pasync_ctx; |
23188167 | 3699 | int i, eq_for_mcc, ulp_num; |
6733b39a JK |
3700 | |
3701 | phwi_ctrlr = phba->phwi_ctrlr; | |
3702 | phwi_context = phwi_ctrlr->phwi_ctxt; | |
15a90fe0 JK |
3703 | |
3704 | be_cmd_iscsi_remove_template_hdr(ctrl); | |
3705 | ||
6733b39a JK |
3706 | for (i = 0; i < phba->params.cxns_per_ctrl; i++) { |
3707 | q = &phwi_context->be_wrbq[i]; | |
3708 | if (q->created) | |
3709 | beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ); | |
3710 | } | |
a7909b39 | 3711 | kfree(phwi_context->be_wrbq); |
6733b39a JK |
3712 | free_wrb_handles(phba); |
3713 | ||
8a86e833 JK |
3714 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { |
3715 | if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { | |
6733b39a | 3716 | |
8a86e833 JK |
3717 | q = &phwi_context->be_def_hdrq[ulp_num]; |
3718 | if (q->created) | |
3719 | beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ); | |
3720 | ||
3721 | q = &phwi_context->be_def_dataq[ulp_num]; | |
3722 | if (q->created) | |
3723 | beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ); | |
3724 | ||
3725 | pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num]; | |
3726 | } | |
3727 | } | |
6733b39a JK |
3728 | |
3729 | beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL); | |
3730 | ||
bfead3b2 JK |
3731 | for (i = 0; i < (phba->num_cpus); i++) { |
3732 | q = &phwi_context->be_cq[i]; | |
3733 | if (q->created) | |
3734 | beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ); | |
3735 | } | |
23188167 JK |
3736 | |
3737 | be_mcc_queues_destroy(phba); | |
bfead3b2 | 3738 | if (phba->msix_enabled) |
23188167 | 3739 | eq_for_mcc = 1; |
bfead3b2 | 3740 | else |
23188167 JK |
3741 | eq_for_mcc = 0; |
3742 | for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) { | |
bfead3b2 JK |
3743 | q = &phwi_context->be_eq[i].q; |
3744 | if (q->created) | |
3745 | beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ); | |
3746 | } | |
0283fbb1 | 3747 | be_cmd_fw_uninit(ctrl); |
bfead3b2 | 3748 | } |
6733b39a | 3749 | |
bfead3b2 JK |
3750 | static int be_mcc_queues_create(struct beiscsi_hba *phba, |
3751 | struct hwi_context_memory *phwi_context) | |
3752 | { | |
3753 | struct be_queue_info *q, *cq; | |
3754 | struct be_ctrl_info *ctrl = &phba->ctrl; | |
3755 | ||
3756 | /* Alloc MCC compl queue */ | |
3757 | cq = &phba->ctrl.mcc_obj.cq; | |
3758 | if (be_queue_alloc(phba, cq, MCC_CQ_LEN, | |
3759 | sizeof(struct be_mcc_compl))) | |
3760 | goto err; | |
3761 | /* Ask BE to create MCC compl queue; */ | |
3762 | if (phba->msix_enabled) { | |
3763 | if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq | |
3764 | [phba->num_cpus].q, false, true, 0)) | |
3765 | goto mcc_cq_free; | |
3766 | } else { | |
3767 | if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q, | |
3768 | false, true, 0)) | |
3769 | goto mcc_cq_free; | |
3770 | } | |
3771 | ||
3772 | /* Alloc MCC queue */ | |
3773 | q = &phba->ctrl.mcc_obj.q; | |
3774 | if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb))) | |
3775 | goto mcc_cq_destroy; | |
3776 | ||
3777 | /* Ask BE to create MCC queue */ | |
35e66019 | 3778 | if (beiscsi_cmd_mccq_create(phba, q, cq)) |
bfead3b2 JK |
3779 | goto mcc_q_free; |
3780 | ||
3781 | return 0; | |
3782 | ||
3783 | mcc_q_free: | |
3784 | be_queue_free(phba, q); | |
3785 | mcc_cq_destroy: | |
3786 | beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ); | |
3787 | mcc_cq_free: | |
3788 | be_queue_free(phba, cq); | |
3789 | err: | |
d3ad2bb3 | 3790 | return -ENOMEM; |
bfead3b2 JK |
3791 | } |
3792 | ||
107dfcba JSJ |
3793 | /** |
3794 | * find_num_cpus()- Get the CPU online count | |
3795 | * @phba: ptr to priv structure | |
3796 | * | |
3797 | * CPU count is used for creating EQ. | |
3798 | **/ | |
3799 | static void find_num_cpus(struct beiscsi_hba *phba) | |
bfead3b2 JK |
3800 | { |
3801 | int num_cpus = 0; | |
3802 | ||
3803 | num_cpus = num_online_cpus(); | |
bfead3b2 | 3804 | |
22abeef0 JSJ |
3805 | switch (phba->generation) { |
3806 | case BE_GEN2: | |
3807 | case BE_GEN3: | |
3808 | phba->num_cpus = (num_cpus > BEISCSI_MAX_NUM_CPUS) ? | |
3809 | BEISCSI_MAX_NUM_CPUS : num_cpus; | |
3810 | break; | |
3811 | case BE_GEN4: | |
68c26a3a JK |
3812 | /* |
3813 | * If eqid_count == 1 fall back to | |
3814 | * INTX mechanism | |
3815 | **/ | |
3816 | if (phba->fw_config.eqid_count == 1) { | |
3817 | enable_msix = 0; | |
3818 | phba->num_cpus = 1; | |
3819 | return; | |
3820 | } | |
3821 | ||
3822 | phba->num_cpus = | |
3823 | (num_cpus > (phba->fw_config.eqid_count - 1)) ? | |
3824 | (phba->fw_config.eqid_count - 1) : num_cpus; | |
22abeef0 JSJ |
3825 | break; |
3826 | default: | |
3827 | phba->num_cpus = 1; | |
3828 | } | |
6733b39a JK |
3829 | } |
3830 | ||
3831 | static int hwi_init_port(struct beiscsi_hba *phba) | |
3832 | { | |
3833 | struct hwi_controller *phwi_ctrlr; | |
3834 | struct hwi_context_memory *phwi_context; | |
3835 | unsigned int def_pdu_ring_sz; | |
3836 | struct be_ctrl_info *ctrl = &phba->ctrl; | |
8a86e833 | 3837 | int status, ulp_num; |
6733b39a | 3838 | |
6733b39a | 3839 | phwi_ctrlr = phba->phwi_ctrlr; |
6733b39a | 3840 | phwi_context = phwi_ctrlr->phwi_ctxt; |
73af08e1 | 3841 | phwi_context->max_eqd = 128; |
bfead3b2 | 3842 | phwi_context->min_eqd = 0; |
73af08e1 | 3843 | phwi_context->cur_eqd = 0; |
6733b39a | 3844 | be_cmd_fw_initialize(&phba->ctrl); |
bfead3b2 JK |
3845 | |
3846 | status = beiscsi_create_eqs(phba, phwi_context); | |
6733b39a | 3847 | if (status != 0) { |
99bc5d55 JSJ |
3848 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3849 | "BM_%d : EQ not created\n"); | |
6733b39a JK |
3850 | goto error; |
3851 | } | |
3852 | ||
bfead3b2 JK |
3853 | status = be_mcc_queues_create(phba, phwi_context); |
3854 | if (status != 0) | |
3855 | goto error; | |
3856 | ||
3857 | status = mgmt_check_supported_fw(ctrl, phba); | |
6733b39a | 3858 | if (status != 0) { |
99bc5d55 JSJ |
3859 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3860 | "BM_%d : Unsupported fw version\n"); | |
6733b39a JK |
3861 | goto error; |
3862 | } | |
3863 | ||
bfead3b2 | 3864 | status = beiscsi_create_cqs(phba, phwi_context); |
6733b39a | 3865 | if (status != 0) { |
99bc5d55 JSJ |
3866 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3867 | "BM_%d : CQ not created\n"); | |
6733b39a JK |
3868 | goto error; |
3869 | } | |
3870 | ||
8a86e833 JK |
3871 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { |
3872 | if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { | |
6733b39a | 3873 | |
8a86e833 JK |
3874 | def_pdu_ring_sz = |
3875 | BEISCSI_GET_CID_COUNT(phba, ulp_num) * | |
3876 | sizeof(struct phys_addr); | |
3877 | ||
3878 | status = beiscsi_create_def_hdr(phba, phwi_context, | |
3879 | phwi_ctrlr, | |
3880 | def_pdu_ring_sz, | |
3881 | ulp_num); | |
3882 | if (status != 0) { | |
3883 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
3884 | "BM_%d : Default Header not created for ULP : %d\n", | |
3885 | ulp_num); | |
3886 | goto error; | |
3887 | } | |
3888 | ||
3889 | status = beiscsi_create_def_data(phba, phwi_context, | |
3890 | phwi_ctrlr, | |
3891 | def_pdu_ring_sz, | |
3892 | ulp_num); | |
3893 | if (status != 0) { | |
3894 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
3895 | "BM_%d : Default Data not created for ULP : %d\n", | |
3896 | ulp_num); | |
3897 | goto error; | |
3898 | } | |
3899 | } | |
6733b39a JK |
3900 | } |
3901 | ||
3902 | status = beiscsi_post_pages(phba); | |
3903 | if (status != 0) { | |
99bc5d55 JSJ |
3904 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3905 | "BM_%d : Post SGL Pages Failed\n"); | |
6733b39a JK |
3906 | goto error; |
3907 | } | |
3908 | ||
15a90fe0 JK |
3909 | status = beiscsi_post_template_hdr(phba); |
3910 | if (status != 0) { | |
3911 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
3912 | "BM_%d : Template HDR Posting for CXN Failed\n"); | |
3913 | } | |
3914 | ||
6733b39a JK |
3915 | status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr); |
3916 | if (status != 0) { | |
99bc5d55 JSJ |
3917 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3918 | "BM_%d : WRB Rings not created\n"); | |
6733b39a JK |
3919 | goto error; |
3920 | } | |
3921 | ||
8a86e833 JK |
3922 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { |
3923 | uint16_t async_arr_idx = 0; | |
3924 | ||
3925 | if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { | |
3926 | uint16_t cri = 0; | |
3927 | struct hwi_async_pdu_context *pasync_ctx; | |
3928 | ||
3929 | pasync_ctx = HWI_GET_ASYNC_PDU_CTX( | |
3930 | phwi_ctrlr, ulp_num); | |
3931 | for (cri = 0; cri < | |
3932 | phba->params.cxns_per_ctrl; cri++) { | |
3933 | if (ulp_num == BEISCSI_GET_ULP_FROM_CRI | |
3934 | (phwi_ctrlr, cri)) | |
3935 | pasync_ctx->cid_to_async_cri_map[ | |
3936 | phwi_ctrlr->wrb_context[cri].cid] = | |
3937 | async_arr_idx++; | |
3938 | } | |
3939 | } | |
3940 | } | |
3941 | ||
99bc5d55 JSJ |
3942 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
3943 | "BM_%d : hwi_init_port success\n"); | |
6733b39a JK |
3944 | return 0; |
3945 | ||
3946 | error: | |
99bc5d55 JSJ |
3947 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3948 | "BM_%d : hwi_init_port failed"); | |
6733b39a | 3949 | hwi_cleanup(phba); |
a49e06d5 | 3950 | return status; |
6733b39a JK |
3951 | } |
3952 | ||
6733b39a JK |
3953 | static int hwi_init_controller(struct beiscsi_hba *phba) |
3954 | { | |
3955 | struct hwi_controller *phwi_ctrlr; | |
3956 | ||
3957 | phwi_ctrlr = phba->phwi_ctrlr; | |
3958 | if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) { | |
3959 | phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba-> | |
3960 | init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address; | |
99bc5d55 JSJ |
3961 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
3962 | "BM_%d : phwi_ctrlr->phwi_ctxt=%p\n", | |
3963 | phwi_ctrlr->phwi_ctxt); | |
6733b39a | 3964 | } else { |
99bc5d55 JSJ |
3965 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3966 | "BM_%d : HWI_MEM_ADDN_CONTEXT is more " | |
3967 | "than one element.Failing to load\n"); | |
6733b39a JK |
3968 | return -ENOMEM; |
3969 | } | |
3970 | ||
3971 | iscsi_init_global_templates(phba); | |
3ec78271 JK |
3972 | if (beiscsi_init_wrb_handle(phba)) |
3973 | return -ENOMEM; | |
3974 | ||
a7909b39 JK |
3975 | if (hwi_init_async_pdu_ctx(phba)) { |
3976 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
3977 | "BM_%d : hwi_init_async_pdu_ctx failed\n"); | |
3978 | return -ENOMEM; | |
3979 | } | |
3980 | ||
6733b39a | 3981 | if (hwi_init_port(phba) != 0) { |
99bc5d55 JSJ |
3982 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3983 | "BM_%d : hwi_init_controller failed\n"); | |
3984 | ||
6733b39a JK |
3985 | return -ENOMEM; |
3986 | } | |
3987 | return 0; | |
3988 | } | |
3989 | ||
3990 | static void beiscsi_free_mem(struct beiscsi_hba *phba) | |
3991 | { | |
3992 | struct be_mem_descriptor *mem_descr; | |
3993 | int i, j; | |
3994 | ||
3995 | mem_descr = phba->init_mem; | |
3996 | i = 0; | |
3997 | j = 0; | |
3998 | for (i = 0; i < SE_MEM_MAX; i++) { | |
3999 | for (j = mem_descr->num_elements; j > 0; j--) { | |
4000 | pci_free_consistent(phba->pcidev, | |
4001 | mem_descr->mem_array[j - 1].size, | |
4002 | mem_descr->mem_array[j - 1].virtual_address, | |
457ff3b7 JK |
4003 | (unsigned long)mem_descr->mem_array[j - 1]. |
4004 | bus_address.u.a64.address); | |
6733b39a | 4005 | } |
8a86e833 | 4006 | |
6733b39a JK |
4007 | kfree(mem_descr->mem_array); |
4008 | mem_descr++; | |
4009 | } | |
4010 | kfree(phba->init_mem); | |
a7909b39 | 4011 | kfree(phba->phwi_ctrlr->wrb_context); |
6733b39a JK |
4012 | kfree(phba->phwi_ctrlr); |
4013 | } | |
4014 | ||
4015 | static int beiscsi_init_controller(struct beiscsi_hba *phba) | |
4016 | { | |
4017 | int ret = -ENOMEM; | |
4018 | ||
4019 | ret = beiscsi_get_memory(phba); | |
4020 | if (ret < 0) { | |
99bc5d55 JSJ |
4021 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
4022 | "BM_%d : beiscsi_dev_probe -" | |
4023 | "Failed in beiscsi_alloc_memory\n"); | |
6733b39a JK |
4024 | return ret; |
4025 | } | |
4026 | ||
4027 | ret = hwi_init_controller(phba); | |
4028 | if (ret) | |
4029 | goto free_init; | |
99bc5d55 JSJ |
4030 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
4031 | "BM_%d : Return success from beiscsi_init_controller"); | |
4032 | ||
6733b39a JK |
4033 | return 0; |
4034 | ||
4035 | free_init: | |
4036 | beiscsi_free_mem(phba); | |
a49e06d5 | 4037 | return ret; |
6733b39a JK |
4038 | } |
4039 | ||
4040 | static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba) | |
4041 | { | |
4042 | struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg; | |
4043 | struct sgl_handle *psgl_handle; | |
4044 | struct iscsi_sge *pfrag; | |
90622db3 JK |
4045 | unsigned int arr_index, i, idx; |
4046 | unsigned int ulp_icd_start, ulp_num = 0; | |
6733b39a JK |
4047 | |
4048 | phba->io_sgl_hndl_avbl = 0; | |
4049 | phba->eh_sgl_hndl_avbl = 0; | |
bfead3b2 | 4050 | |
6733b39a JK |
4051 | mem_descr_sglh = phba->init_mem; |
4052 | mem_descr_sglh += HWI_MEM_SGLH; | |
4053 | if (1 == mem_descr_sglh->num_elements) { | |
4054 | phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) * | |
4055 | phba->params.ios_per_ctrl, | |
4056 | GFP_KERNEL); | |
4057 | if (!phba->io_sgl_hndl_base) { | |
99bc5d55 JSJ |
4058 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
4059 | "BM_%d : Mem Alloc Failed. Failing to load\n"); | |
6733b39a JK |
4060 | return -ENOMEM; |
4061 | } | |
4062 | phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) * | |
4063 | (phba->params.icds_per_ctrl - | |
4064 | phba->params.ios_per_ctrl), | |
4065 | GFP_KERNEL); | |
4066 | if (!phba->eh_sgl_hndl_base) { | |
4067 | kfree(phba->io_sgl_hndl_base); | |
99bc5d55 JSJ |
4068 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
4069 | "BM_%d : Mem Alloc Failed. Failing to load\n"); | |
6733b39a JK |
4070 | return -ENOMEM; |
4071 | } | |
4072 | } else { | |
99bc5d55 JSJ |
4073 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
4074 | "BM_%d : HWI_MEM_SGLH is more than one element." | |
4075 | "Failing to load\n"); | |
6733b39a JK |
4076 | return -ENOMEM; |
4077 | } | |
4078 | ||
4079 | arr_index = 0; | |
4080 | idx = 0; | |
4081 | while (idx < mem_descr_sglh->num_elements) { | |
4082 | psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address; | |
4083 | ||
4084 | for (i = 0; i < (mem_descr_sglh->mem_array[idx].size / | |
4085 | sizeof(struct sgl_handle)); i++) { | |
4086 | if (arr_index < phba->params.ios_per_ctrl) { | |
4087 | phba->io_sgl_hndl_base[arr_index] = psgl_handle; | |
4088 | phba->io_sgl_hndl_avbl++; | |
4089 | arr_index++; | |
4090 | } else { | |
4091 | phba->eh_sgl_hndl_base[arr_index - | |
4092 | phba->params.ios_per_ctrl] = | |
4093 | psgl_handle; | |
4094 | arr_index++; | |
4095 | phba->eh_sgl_hndl_avbl++; | |
4096 | } | |
4097 | psgl_handle++; | |
4098 | } | |
4099 | idx++; | |
4100 | } | |
99bc5d55 JSJ |
4101 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
4102 | "BM_%d : phba->io_sgl_hndl_avbl=%d" | |
4103 | "phba->eh_sgl_hndl_avbl=%d\n", | |
4104 | phba->io_sgl_hndl_avbl, | |
4105 | phba->eh_sgl_hndl_avbl); | |
4106 | ||
6733b39a JK |
4107 | mem_descr_sg = phba->init_mem; |
4108 | mem_descr_sg += HWI_MEM_SGE; | |
99bc5d55 JSJ |
4109 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
4110 | "\n BM_%d : mem_descr_sg->num_elements=%d\n", | |
4111 | mem_descr_sg->num_elements); | |
4112 | ||
90622db3 JK |
4113 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) |
4114 | if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) | |
4115 | break; | |
4116 | ||
4117 | ulp_icd_start = phba->fw_config.iscsi_icd_start[ulp_num]; | |
4118 | ||
6733b39a JK |
4119 | arr_index = 0; |
4120 | idx = 0; | |
4121 | while (idx < mem_descr_sg->num_elements) { | |
4122 | pfrag = mem_descr_sg->mem_array[idx].virtual_address; | |
4123 | ||
4124 | for (i = 0; | |
4125 | i < (mem_descr_sg->mem_array[idx].size) / | |
4126 | (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io); | |
4127 | i++) { | |
4128 | if (arr_index < phba->params.ios_per_ctrl) | |
4129 | psgl_handle = phba->io_sgl_hndl_base[arr_index]; | |
4130 | else | |
4131 | psgl_handle = phba->eh_sgl_hndl_base[arr_index - | |
4132 | phba->params.ios_per_ctrl]; | |
4133 | psgl_handle->pfrag = pfrag; | |
4134 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0); | |
4135 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0); | |
4136 | pfrag += phba->params.num_sge_per_io; | |
90622db3 | 4137 | psgl_handle->sgl_index = ulp_icd_start + arr_index++; |
6733b39a JK |
4138 | } |
4139 | idx++; | |
4140 | } | |
4141 | phba->io_sgl_free_index = 0; | |
4142 | phba->io_sgl_alloc_index = 0; | |
4143 | phba->eh_sgl_free_index = 0; | |
4144 | phba->eh_sgl_alloc_index = 0; | |
4145 | return 0; | |
4146 | } | |
4147 | ||
4148 | static int hba_setup_cid_tbls(struct beiscsi_hba *phba) | |
4149 | { | |
0a3db7c0 JK |
4150 | int ret; |
4151 | uint16_t i, ulp_num; | |
4152 | struct ulp_cid_info *ptr_cid_info = NULL; | |
6733b39a | 4153 | |
0a3db7c0 JK |
4154 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { |
4155 | if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) { | |
4156 | ptr_cid_info = kzalloc(sizeof(struct ulp_cid_info), | |
4157 | GFP_KERNEL); | |
4158 | ||
4159 | if (!ptr_cid_info) { | |
4160 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
4161 | "BM_%d : Failed to allocate memory" | |
4162 | "for ULP_CID_INFO for ULP : %d\n", | |
4163 | ulp_num); | |
4164 | ret = -ENOMEM; | |
4165 | goto free_memory; | |
4166 | ||
4167 | } | |
4168 | ||
4169 | /* Allocate memory for CID array */ | |
4170 | ptr_cid_info->cid_array = kzalloc(sizeof(void *) * | |
4171 | BEISCSI_GET_CID_COUNT(phba, | |
4172 | ulp_num), GFP_KERNEL); | |
4173 | if (!ptr_cid_info->cid_array) { | |
4174 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
4175 | "BM_%d : Failed to allocate memory" | |
4176 | "for CID_ARRAY for ULP : %d\n", | |
4177 | ulp_num); | |
4178 | kfree(ptr_cid_info); | |
4179 | ptr_cid_info = NULL; | |
4180 | ret = -ENOMEM; | |
4181 | ||
4182 | goto free_memory; | |
4183 | } | |
4184 | ptr_cid_info->avlbl_cids = BEISCSI_GET_CID_COUNT( | |
4185 | phba, ulp_num); | |
4186 | ||
4187 | /* Save the cid_info_array ptr */ | |
4188 | phba->cid_array_info[ulp_num] = ptr_cid_info; | |
4189 | } | |
6733b39a | 4190 | } |
c2462288 | 4191 | phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) * |
a7909b39 | 4192 | phba->params.cxns_per_ctrl, GFP_KERNEL); |
6733b39a | 4193 | if (!phba->ep_array) { |
99bc5d55 JSJ |
4194 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
4195 | "BM_%d : Failed to allocate memory in " | |
4196 | "hba_setup_cid_tbls\n"); | |
0a3db7c0 JK |
4197 | ret = -ENOMEM; |
4198 | ||
4199 | goto free_memory; | |
6733b39a | 4200 | } |
a7909b39 JK |
4201 | |
4202 | phba->conn_table = kzalloc(sizeof(struct beiscsi_conn *) * | |
4203 | phba->params.cxns_per_ctrl, GFP_KERNEL); | |
4204 | if (!phba->conn_table) { | |
4205 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
4206 | "BM_%d : Failed to allocate memory in" | |
4207 | "hba_setup_cid_tbls\n"); | |
4208 | ||
a7909b39 | 4209 | kfree(phba->ep_array); |
a7909b39 | 4210 | phba->ep_array = NULL; |
0a3db7c0 | 4211 | ret = -ENOMEM; |
5f2d25ef TH |
4212 | |
4213 | goto free_memory; | |
6733b39a | 4214 | } |
a7909b39 | 4215 | |
0a3db7c0 JK |
4216 | for (i = 0; i < phba->params.cxns_per_ctrl; i++) { |
4217 | ulp_num = phba->phwi_ctrlr->wrb_context[i].ulp_num; | |
4218 | ||
4219 | ptr_cid_info = phba->cid_array_info[ulp_num]; | |
4220 | ptr_cid_info->cid_array[ptr_cid_info->cid_alloc++] = | |
4221 | phba->phwi_ctrlr->wrb_context[i].cid; | |
4222 | ||
4223 | } | |
4224 | ||
4225 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { | |
4226 | if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) { | |
4227 | ptr_cid_info = phba->cid_array_info[ulp_num]; | |
a7909b39 | 4228 | |
0a3db7c0 JK |
4229 | ptr_cid_info->cid_alloc = 0; |
4230 | ptr_cid_info->cid_free = 0; | |
4231 | } | |
4232 | } | |
6733b39a | 4233 | return 0; |
0a3db7c0 JK |
4234 | |
4235 | free_memory: | |
4236 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { | |
4237 | if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) { | |
4238 | ptr_cid_info = phba->cid_array_info[ulp_num]; | |
4239 | ||
4240 | if (ptr_cid_info) { | |
4241 | kfree(ptr_cid_info->cid_array); | |
4242 | kfree(ptr_cid_info); | |
4243 | phba->cid_array_info[ulp_num] = NULL; | |
4244 | } | |
4245 | } | |
4246 | } | |
4247 | ||
4248 | return ret; | |
6733b39a JK |
4249 | } |
4250 | ||
238f6b72 | 4251 | static void hwi_enable_intr(struct beiscsi_hba *phba) |
6733b39a JK |
4252 | { |
4253 | struct be_ctrl_info *ctrl = &phba->ctrl; | |
4254 | struct hwi_controller *phwi_ctrlr; | |
4255 | struct hwi_context_memory *phwi_context; | |
4256 | struct be_queue_info *eq; | |
4257 | u8 __iomem *addr; | |
bfead3b2 | 4258 | u32 reg, i; |
6733b39a JK |
4259 | u32 enabled; |
4260 | ||
4261 | phwi_ctrlr = phba->phwi_ctrlr; | |
4262 | phwi_context = phwi_ctrlr->phwi_ctxt; | |
4263 | ||
6733b39a JK |
4264 | addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg + |
4265 | PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET); | |
4266 | reg = ioread32(addr); | |
6733b39a JK |
4267 | |
4268 | enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; | |
4269 | if (!enabled) { | |
4270 | reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; | |
99bc5d55 JSJ |
4271 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
4272 | "BM_%d : reg =x%08x addr=%p\n", reg, addr); | |
6733b39a | 4273 | iowrite32(reg, addr); |
665d6d94 JK |
4274 | } |
4275 | ||
4276 | if (!phba->msix_enabled) { | |
4277 | eq = &phwi_context->be_eq[0].q; | |
99bc5d55 JSJ |
4278 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
4279 | "BM_%d : eq->id=%d\n", eq->id); | |
4280 | ||
665d6d94 JK |
4281 | hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1); |
4282 | } else { | |
4283 | for (i = 0; i <= phba->num_cpus; i++) { | |
4284 | eq = &phwi_context->be_eq[i].q; | |
99bc5d55 JSJ |
4285 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
4286 | "BM_%d : eq->id=%d\n", eq->id); | |
bfead3b2 JK |
4287 | hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1); |
4288 | } | |
c03af1ae | 4289 | } |
6733b39a JK |
4290 | } |
4291 | ||
4292 | static void hwi_disable_intr(struct beiscsi_hba *phba) | |
4293 | { | |
4294 | struct be_ctrl_info *ctrl = &phba->ctrl; | |
4295 | ||
4296 | u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET; | |
4297 | u32 reg = ioread32(addr); | |
4298 | ||
4299 | u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; | |
4300 | if (enabled) { | |
4301 | reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; | |
4302 | iowrite32(reg, addr); | |
4303 | } else | |
99bc5d55 JSJ |
4304 | beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT, |
4305 | "BM_%d : In hwi_disable_intr, Already Disabled\n"); | |
6733b39a JK |
4306 | } |
4307 | ||
9aef4200 JSJ |
4308 | /** |
4309 | * beiscsi_get_boot_info()- Get the boot session info | |
4310 | * @phba: The device priv structure instance | |
4311 | * | |
4312 | * Get the boot target info and store in driver priv structure | |
4313 | * | |
4314 | * return values | |
4315 | * Success: 0 | |
4316 | * Failure: Non-Zero Value | |
4317 | **/ | |
c7acc5b8 JK |
4318 | static int beiscsi_get_boot_info(struct beiscsi_hba *phba) |
4319 | { | |
0e43895e | 4320 | struct be_cmd_get_session_resp *session_resp; |
c7acc5b8 | 4321 | struct be_dma_mem nonemb_cmd; |
e175defe | 4322 | unsigned int tag; |
9aef4200 | 4323 | unsigned int s_handle; |
f457a46f | 4324 | int ret = -ENOMEM; |
c7acc5b8 | 4325 | |
9aef4200 JSJ |
4326 | /* Get the session handle of the boot target */ |
4327 | ret = be_mgmt_get_boot_shandle(phba, &s_handle); | |
4328 | if (ret) { | |
99bc5d55 JSJ |
4329 | beiscsi_log(phba, KERN_ERR, |
4330 | BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG, | |
4331 | "BM_%d : No boot session\n"); | |
9aef4200 | 4332 | return ret; |
c7acc5b8 | 4333 | } |
7c845eb5 JP |
4334 | nonemb_cmd.va = pci_zalloc_consistent(phba->ctrl.pdev, |
4335 | sizeof(*session_resp), | |
4336 | &nonemb_cmd.dma); | |
c7acc5b8 | 4337 | if (nonemb_cmd.va == NULL) { |
99bc5d55 JSJ |
4338 | beiscsi_log(phba, KERN_ERR, |
4339 | BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG, | |
4340 | "BM_%d : Failed to allocate memory for" | |
4341 | "beiscsi_get_session_info\n"); | |
4342 | ||
c7acc5b8 JK |
4343 | return -ENOMEM; |
4344 | } | |
4345 | ||
9aef4200 | 4346 | tag = mgmt_get_session_info(phba, s_handle, |
0e43895e | 4347 | &nonemb_cmd); |
c7acc5b8 | 4348 | if (!tag) { |
99bc5d55 JSJ |
4349 | beiscsi_log(phba, KERN_ERR, |
4350 | BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG, | |
4351 | "BM_%d : beiscsi_get_session_info" | |
4352 | " Failed\n"); | |
4353 | ||
c7acc5b8 | 4354 | goto boot_freemem; |
e175defe | 4355 | } |
c7acc5b8 | 4356 | |
1957aa7f | 4357 | ret = beiscsi_mccq_compl(phba, tag, NULL, &nonemb_cmd); |
e175defe | 4358 | if (ret) { |
99bc5d55 JSJ |
4359 | beiscsi_log(phba, KERN_ERR, |
4360 | BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG, | |
e175defe | 4361 | "BM_%d : beiscsi_get_session_info Failed"); |
1957aa7f JK |
4362 | |
4363 | if (ret != -EBUSY) | |
4364 | goto boot_freemem; | |
4365 | else | |
4366 | return ret; | |
c7acc5b8 | 4367 | } |
e175defe | 4368 | |
c7acc5b8 | 4369 | session_resp = nonemb_cmd.va ; |
f457a46f | 4370 | |
c7acc5b8 JK |
4371 | memcpy(&phba->boot_sess, &session_resp->session_info, |
4372 | sizeof(struct mgmt_session_info)); | |
f457a46f MC |
4373 | ret = 0; |
4374 | ||
c7acc5b8 JK |
4375 | boot_freemem: |
4376 | pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, | |
4377 | nonemb_cmd.va, nonemb_cmd.dma); | |
f457a46f MC |
4378 | return ret; |
4379 | } | |
4380 | ||
4381 | static void beiscsi_boot_release(void *data) | |
4382 | { | |
4383 | struct beiscsi_hba *phba = data; | |
4384 | ||
4385 | scsi_host_put(phba->shost); | |
4386 | } | |
4387 | ||
4388 | static int beiscsi_setup_boot_info(struct beiscsi_hba *phba) | |
4389 | { | |
4390 | struct iscsi_boot_kobj *boot_kobj; | |
4391 | ||
a3d313ea JK |
4392 | /* it has been created previously */ |
4393 | if (phba->boot_kset) | |
4394 | return 0; | |
4395 | ||
f457a46f MC |
4396 | /* get boot info using mgmt cmd */ |
4397 | if (beiscsi_get_boot_info(phba)) | |
4398 | /* Try to see if we can carry on without this */ | |
4399 | return 0; | |
4400 | ||
4401 | phba->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no); | |
4402 | if (!phba->boot_kset) | |
4403 | return -ENOMEM; | |
4404 | ||
4405 | /* get a ref because the show function will ref the phba */ | |
4406 | if (!scsi_host_get(phba->shost)) | |
4407 | goto free_kset; | |
4408 | boot_kobj = iscsi_boot_create_target(phba->boot_kset, 0, phba, | |
4409 | beiscsi_show_boot_tgt_info, | |
4410 | beiscsi_tgt_get_attr_visibility, | |
4411 | beiscsi_boot_release); | |
4412 | if (!boot_kobj) | |
4413 | goto put_shost; | |
4414 | ||
4415 | if (!scsi_host_get(phba->shost)) | |
4416 | goto free_kset; | |
4417 | boot_kobj = iscsi_boot_create_initiator(phba->boot_kset, 0, phba, | |
4418 | beiscsi_show_boot_ini_info, | |
4419 | beiscsi_ini_get_attr_visibility, | |
4420 | beiscsi_boot_release); | |
4421 | if (!boot_kobj) | |
4422 | goto put_shost; | |
4423 | ||
4424 | if (!scsi_host_get(phba->shost)) | |
4425 | goto free_kset; | |
4426 | boot_kobj = iscsi_boot_create_ethernet(phba->boot_kset, 0, phba, | |
4427 | beiscsi_show_boot_eth_info, | |
4428 | beiscsi_eth_get_attr_visibility, | |
4429 | beiscsi_boot_release); | |
4430 | if (!boot_kobj) | |
4431 | goto put_shost; | |
4432 | return 0; | |
4433 | ||
4434 | put_shost: | |
4435 | scsi_host_put(phba->shost); | |
4436 | free_kset: | |
4437 | iscsi_boot_destroy_kset(phba->boot_kset); | |
c7acc5b8 JK |
4438 | return -ENOMEM; |
4439 | } | |
4440 | ||
6733b39a JK |
4441 | static int beiscsi_init_port(struct beiscsi_hba *phba) |
4442 | { | |
4443 | int ret; | |
4444 | ||
4445 | ret = beiscsi_init_controller(phba); | |
4446 | if (ret < 0) { | |
99bc5d55 JSJ |
4447 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
4448 | "BM_%d : beiscsi_dev_probe - Failed in" | |
4449 | "beiscsi_init_controller\n"); | |
6733b39a JK |
4450 | return ret; |
4451 | } | |
4452 | ret = beiscsi_init_sgl_handle(phba); | |
4453 | if (ret < 0) { | |
99bc5d55 JSJ |
4454 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
4455 | "BM_%d : beiscsi_dev_probe - Failed in" | |
4456 | "beiscsi_init_sgl_handle\n"); | |
6733b39a JK |
4457 | goto do_cleanup_ctrlr; |
4458 | } | |
4459 | ||
4460 | if (hba_setup_cid_tbls(phba)) { | |
99bc5d55 JSJ |
4461 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
4462 | "BM_%d : Failed in hba_setup_cid_tbls\n"); | |
6733b39a JK |
4463 | kfree(phba->io_sgl_hndl_base); |
4464 | kfree(phba->eh_sgl_hndl_base); | |
4465 | goto do_cleanup_ctrlr; | |
4466 | } | |
4467 | ||
4468 | return ret; | |
4469 | ||
4470 | do_cleanup_ctrlr: | |
4471 | hwi_cleanup(phba); | |
4472 | return ret; | |
4473 | } | |
4474 | ||
4475 | static void hwi_purge_eq(struct beiscsi_hba *phba) | |
4476 | { | |
4477 | struct hwi_controller *phwi_ctrlr; | |
4478 | struct hwi_context_memory *phwi_context; | |
4479 | struct be_queue_info *eq; | |
4480 | struct be_eq_entry *eqe = NULL; | |
bfead3b2 | 4481 | int i, eq_msix; |
756d29c8 | 4482 | unsigned int num_processed; |
6733b39a JK |
4483 | |
4484 | phwi_ctrlr = phba->phwi_ctrlr; | |
4485 | phwi_context = phwi_ctrlr->phwi_ctxt; | |
bfead3b2 JK |
4486 | if (phba->msix_enabled) |
4487 | eq_msix = 1; | |
4488 | else | |
4489 | eq_msix = 0; | |
6733b39a | 4490 | |
bfead3b2 JK |
4491 | for (i = 0; i < (phba->num_cpus + eq_msix); i++) { |
4492 | eq = &phwi_context->be_eq[i].q; | |
6733b39a | 4493 | eqe = queue_tail_node(eq); |
756d29c8 | 4494 | num_processed = 0; |
bfead3b2 JK |
4495 | while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] |
4496 | & EQE_VALID_MASK) { | |
4497 | AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); | |
4498 | queue_tail_inc(eq); | |
4499 | eqe = queue_tail_node(eq); | |
756d29c8 | 4500 | num_processed++; |
bfead3b2 | 4501 | } |
756d29c8 JK |
4502 | |
4503 | if (num_processed) | |
4504 | hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1); | |
6733b39a JK |
4505 | } |
4506 | } | |
4507 | ||
4508 | static void beiscsi_clean_port(struct beiscsi_hba *phba) | |
4509 | { | |
0a3db7c0 JK |
4510 | int mgmt_status, ulp_num; |
4511 | struct ulp_cid_info *ptr_cid_info = NULL; | |
6733b39a | 4512 | |
bd41c2bd JK |
4513 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { |
4514 | if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) { | |
4515 | mgmt_status = mgmt_epfw_cleanup(phba, ulp_num); | |
4516 | if (mgmt_status) | |
4517 | beiscsi_log(phba, KERN_WARNING, | |
4518 | BEISCSI_LOG_INIT, | |
4519 | "BM_%d : mgmt_epfw_cleanup FAILED" | |
4520 | " for ULP_%d\n", ulp_num); | |
4521 | } | |
4522 | } | |
756d29c8 | 4523 | |
6733b39a | 4524 | hwi_purge_eq(phba); |
756d29c8 | 4525 | hwi_cleanup(phba); |
6733b39a JK |
4526 | kfree(phba->io_sgl_hndl_base); |
4527 | kfree(phba->eh_sgl_hndl_base); | |
6733b39a | 4528 | kfree(phba->ep_array); |
a7909b39 | 4529 | kfree(phba->conn_table); |
0a3db7c0 JK |
4530 | |
4531 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { | |
4532 | if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) { | |
4533 | ptr_cid_info = phba->cid_array_info[ulp_num]; | |
4534 | ||
4535 | if (ptr_cid_info) { | |
4536 | kfree(ptr_cid_info->cid_array); | |
4537 | kfree(ptr_cid_info); | |
4538 | phba->cid_array_info[ulp_num] = NULL; | |
4539 | } | |
4540 | } | |
4541 | } | |
4542 | ||
6733b39a JK |
4543 | } |
4544 | ||
43f388b0 JK |
4545 | /** |
4546 | * beiscsi_free_mgmt_task_handles()- Free driver CXN resources | |
4547 | * @beiscsi_conn: ptr to the conn to be cleaned up | |
4a4a11b9 | 4548 | * @task: ptr to iscsi_task resource to be freed. |
43f388b0 JK |
4549 | * |
4550 | * Free driver mgmt resources binded to CXN. | |
4551 | **/ | |
4552 | void | |
4a4a11b9 JK |
4553 | beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn, |
4554 | struct iscsi_task *task) | |
43f388b0 JK |
4555 | { |
4556 | struct beiscsi_io_task *io_task; | |
4557 | struct beiscsi_hba *phba = beiscsi_conn->phba; | |
4558 | struct hwi_wrb_context *pwrb_context; | |
4559 | struct hwi_controller *phwi_ctrlr; | |
a7909b39 JK |
4560 | uint16_t cri_index = BE_GET_CRI_FROM_CID( |
4561 | beiscsi_conn->beiscsi_conn_cid); | |
43f388b0 JK |
4562 | |
4563 | phwi_ctrlr = phba->phwi_ctrlr; | |
a7909b39 JK |
4564 | pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; |
4565 | ||
4a4a11b9 | 4566 | io_task = task->dd_data; |
43f388b0 JK |
4567 | |
4568 | if (io_task->pwrb_handle) { | |
4569 | memset(io_task->pwrb_handle->pwrb, 0, | |
4570 | sizeof(struct iscsi_wrb)); | |
4571 | free_wrb_handle(phba, pwrb_context, | |
4572 | io_task->pwrb_handle); | |
4573 | io_task->pwrb_handle = NULL; | |
4574 | } | |
4575 | ||
4576 | if (io_task->psgl_handle) { | |
4577 | spin_lock_bh(&phba->mgmt_sgl_lock); | |
4578 | free_mgmt_sgl_handle(phba, | |
4579 | io_task->psgl_handle); | |
43f388b0 | 4580 | io_task->psgl_handle = NULL; |
4a4a11b9 | 4581 | spin_unlock_bh(&phba->mgmt_sgl_lock); |
43f388b0 JK |
4582 | } |
4583 | ||
4584 | if (io_task->mtask_addr) | |
4585 | pci_unmap_single(phba->pcidev, | |
4586 | io_task->mtask_addr, | |
4587 | io_task->mtask_data_count, | |
4588 | PCI_DMA_TODEVICE); | |
4589 | } | |
4590 | ||
d629c471 JSJ |
4591 | /** |
4592 | * beiscsi_cleanup_task()- Free driver resources of the task | |
4593 | * @task: ptr to the iscsi task | |
4594 | * | |
4595 | **/ | |
1282ab76 MC |
4596 | static void beiscsi_cleanup_task(struct iscsi_task *task) |
4597 | { | |
4598 | struct beiscsi_io_task *io_task = task->dd_data; | |
4599 | struct iscsi_conn *conn = task->conn; | |
4600 | struct beiscsi_conn *beiscsi_conn = conn->dd_data; | |
4601 | struct beiscsi_hba *phba = beiscsi_conn->phba; | |
4602 | struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess; | |
4603 | struct hwi_wrb_context *pwrb_context; | |
4604 | struct hwi_controller *phwi_ctrlr; | |
a7909b39 JK |
4605 | uint16_t cri_index = BE_GET_CRI_FROM_CID( |
4606 | beiscsi_conn->beiscsi_conn_cid); | |
1282ab76 MC |
4607 | |
4608 | phwi_ctrlr = phba->phwi_ctrlr; | |
a7909b39 | 4609 | pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; |
1282ab76 MC |
4610 | |
4611 | if (io_task->cmd_bhs) { | |
4612 | pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs, | |
4613 | io_task->bhs_pa.u.a64.address); | |
4614 | io_task->cmd_bhs = NULL; | |
4615 | } | |
4616 | ||
4617 | if (task->sc) { | |
4618 | if (io_task->pwrb_handle) { | |
4619 | free_wrb_handle(phba, pwrb_context, | |
4620 | io_task->pwrb_handle); | |
4621 | io_task->pwrb_handle = NULL; | |
4622 | } | |
4623 | ||
4624 | if (io_task->psgl_handle) { | |
4625 | spin_lock(&phba->io_sgl_lock); | |
4626 | free_io_sgl_handle(phba, io_task->psgl_handle); | |
4627 | spin_unlock(&phba->io_sgl_lock); | |
4628 | io_task->psgl_handle = NULL; | |
4629 | } | |
da334977 JK |
4630 | |
4631 | if (io_task->scsi_cmnd) { | |
4632 | scsi_dma_unmap(io_task->scsi_cmnd); | |
4633 | io_task->scsi_cmnd = NULL; | |
4634 | } | |
1282ab76 | 4635 | } else { |
43f388b0 | 4636 | if (!beiscsi_conn->login_in_progress) |
4a4a11b9 | 4637 | beiscsi_free_mgmt_task_handles(beiscsi_conn, task); |
1282ab76 MC |
4638 | } |
4639 | } | |
4640 | ||
6733b39a JK |
4641 | void |
4642 | beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn, | |
4643 | struct beiscsi_offload_params *params) | |
4644 | { | |
4645 | struct wrb_handle *pwrb_handle; | |
6733b39a | 4646 | struct beiscsi_hba *phba = beiscsi_conn->phba; |
1282ab76 MC |
4647 | struct iscsi_task *task = beiscsi_conn->task; |
4648 | struct iscsi_session *session = task->conn->session; | |
6733b39a JK |
4649 | u32 doorbell = 0; |
4650 | ||
4651 | /* | |
4652 | * We can always use 0 here because it is reserved by libiscsi for | |
4653 | * login/startup related tasks. | |
4654 | */ | |
1282ab76 | 4655 | beiscsi_conn->login_in_progress = 0; |
659743b0 | 4656 | spin_lock_bh(&session->back_lock); |
1282ab76 | 4657 | beiscsi_cleanup_task(task); |
659743b0 | 4658 | spin_unlock_bh(&session->back_lock); |
1282ab76 | 4659 | |
a7909b39 | 4660 | pwrb_handle = alloc_wrb_handle(phba, beiscsi_conn->beiscsi_conn_cid); |
6733b39a | 4661 | |
acb9693c | 4662 | /* Check for the adapter family */ |
2c9dfd36 | 4663 | if (is_chip_be2_be3r(phba)) |
acb9693c JSJ |
4664 | beiscsi_offload_cxn_v0(params, pwrb_handle, |
4665 | phba->init_mem); | |
2c9dfd36 JK |
4666 | else |
4667 | beiscsi_offload_cxn_v2(params, pwrb_handle); | |
6733b39a | 4668 | |
acb9693c JSJ |
4669 | be_dws_le_to_cpu(pwrb_handle->pwrb, |
4670 | sizeof(struct iscsi_target_context_update_wrb)); | |
6733b39a JK |
4671 | |
4672 | doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK; | |
32951dd8 | 4673 | doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK) |
bfead3b2 | 4674 | << DB_DEF_PDU_WRB_INDEX_SHIFT; |
6733b39a | 4675 | doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT; |
1e4be6ff JK |
4676 | iowrite32(doorbell, phba->db_va + |
4677 | beiscsi_conn->doorbell_offset); | |
6733b39a JK |
4678 | } |
4679 | ||
4680 | static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt, | |
4681 | int *index, int *age) | |
4682 | { | |
bfead3b2 | 4683 | *index = (int)itt; |
6733b39a JK |
4684 | if (age) |
4685 | *age = conn->session->age; | |
4686 | } | |
4687 | ||
4688 | /** | |
4689 | * beiscsi_alloc_pdu - allocates pdu and related resources | |
4690 | * @task: libiscsi task | |
4691 | * @opcode: opcode of pdu for task | |
4692 | * | |
4693 | * This is called with the session lock held. It will allocate | |
4694 | * the wrb and sgl if needed for the command. And it will prep | |
4695 | * the pdu's itt. beiscsi_parse_pdu will later translate | |
4696 | * the pdu itt to the libiscsi task itt. | |
4697 | */ | |
4698 | static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode) | |
4699 | { | |
4700 | struct beiscsi_io_task *io_task = task->dd_data; | |
4701 | struct iscsi_conn *conn = task->conn; | |
4702 | struct beiscsi_conn *beiscsi_conn = conn->dd_data; | |
4703 | struct beiscsi_hba *phba = beiscsi_conn->phba; | |
4704 | struct hwi_wrb_context *pwrb_context; | |
4705 | struct hwi_controller *phwi_ctrlr; | |
4706 | itt_t itt; | |
a7909b39 | 4707 | uint16_t cri_index = 0; |
2afc95bf JK |
4708 | struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess; |
4709 | dma_addr_t paddr; | |
6733b39a | 4710 | |
2afc95bf | 4711 | io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool, |
bc7accec | 4712 | GFP_ATOMIC, &paddr); |
2afc95bf JK |
4713 | if (!io_task->cmd_bhs) |
4714 | return -ENOMEM; | |
2afc95bf | 4715 | io_task->bhs_pa.u.a64.address = paddr; |
bfead3b2 | 4716 | io_task->libiscsi_itt = (itt_t)task->itt; |
6733b39a JK |
4717 | io_task->conn = beiscsi_conn; |
4718 | ||
4719 | task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr; | |
4720 | task->hdr_max = sizeof(struct be_cmd_bhs); | |
d2cecf0d | 4721 | io_task->psgl_handle = NULL; |
3ec78271 | 4722 | io_task->pwrb_handle = NULL; |
6733b39a JK |
4723 | |
4724 | if (task->sc) { | |
4725 | spin_lock(&phba->io_sgl_lock); | |
4726 | io_task->psgl_handle = alloc_io_sgl_handle(phba); | |
4727 | spin_unlock(&phba->io_sgl_lock); | |
8359c79b JSJ |
4728 | if (!io_task->psgl_handle) { |
4729 | beiscsi_log(phba, KERN_ERR, | |
4730 | BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, | |
4731 | "BM_%d : Alloc of IO_SGL_ICD Failed" | |
4732 | "for the CID : %d\n", | |
4733 | beiscsi_conn->beiscsi_conn_cid); | |
2afc95bf | 4734 | goto free_hndls; |
8359c79b | 4735 | } |
d2cecf0d | 4736 | io_task->pwrb_handle = alloc_wrb_handle(phba, |
a7909b39 | 4737 | beiscsi_conn->beiscsi_conn_cid); |
8359c79b JSJ |
4738 | if (!io_task->pwrb_handle) { |
4739 | beiscsi_log(phba, KERN_ERR, | |
4740 | BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, | |
4741 | "BM_%d : Alloc of WRB_HANDLE Failed" | |
4742 | "for the CID : %d\n", | |
4743 | beiscsi_conn->beiscsi_conn_cid); | |
d2cecf0d | 4744 | goto free_io_hndls; |
8359c79b | 4745 | } |
6733b39a JK |
4746 | } else { |
4747 | io_task->scsi_cmnd = NULL; | |
d7aea67b | 4748 | if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) { |
43f388b0 | 4749 | beiscsi_conn->task = task; |
6733b39a JK |
4750 | if (!beiscsi_conn->login_in_progress) { |
4751 | spin_lock(&phba->mgmt_sgl_lock); | |
4752 | io_task->psgl_handle = (struct sgl_handle *) | |
4753 | alloc_mgmt_sgl_handle(phba); | |
4754 | spin_unlock(&phba->mgmt_sgl_lock); | |
8359c79b JSJ |
4755 | if (!io_task->psgl_handle) { |
4756 | beiscsi_log(phba, KERN_ERR, | |
4757 | BEISCSI_LOG_IO | | |
4758 | BEISCSI_LOG_CONFIG, | |
4759 | "BM_%d : Alloc of MGMT_SGL_ICD Failed" | |
4760 | "for the CID : %d\n", | |
4761 | beiscsi_conn-> | |
4762 | beiscsi_conn_cid); | |
2afc95bf | 4763 | goto free_hndls; |
8359c79b | 4764 | } |
2afc95bf | 4765 | |
6733b39a JK |
4766 | beiscsi_conn->login_in_progress = 1; |
4767 | beiscsi_conn->plogin_sgl_handle = | |
4768 | io_task->psgl_handle; | |
d2cecf0d JK |
4769 | io_task->pwrb_handle = |
4770 | alloc_wrb_handle(phba, | |
a7909b39 | 4771 | beiscsi_conn->beiscsi_conn_cid); |
8359c79b JSJ |
4772 | if (!io_task->pwrb_handle) { |
4773 | beiscsi_log(phba, KERN_ERR, | |
4774 | BEISCSI_LOG_IO | | |
4775 | BEISCSI_LOG_CONFIG, | |
4776 | "BM_%d : Alloc of WRB_HANDLE Failed" | |
4777 | "for the CID : %d\n", | |
4778 | beiscsi_conn-> | |
4779 | beiscsi_conn_cid); | |
4780 | goto free_mgmt_hndls; | |
4781 | } | |
d2cecf0d JK |
4782 | beiscsi_conn->plogin_wrb_handle = |
4783 | io_task->pwrb_handle; | |
4784 | ||
6733b39a JK |
4785 | } else { |
4786 | io_task->psgl_handle = | |
4787 | beiscsi_conn->plogin_sgl_handle; | |
d2cecf0d JK |
4788 | io_task->pwrb_handle = |
4789 | beiscsi_conn->plogin_wrb_handle; | |
6733b39a JK |
4790 | } |
4791 | } else { | |
4792 | spin_lock(&phba->mgmt_sgl_lock); | |
4793 | io_task->psgl_handle = alloc_mgmt_sgl_handle(phba); | |
4794 | spin_unlock(&phba->mgmt_sgl_lock); | |
8359c79b JSJ |
4795 | if (!io_task->psgl_handle) { |
4796 | beiscsi_log(phba, KERN_ERR, | |
4797 | BEISCSI_LOG_IO | | |
4798 | BEISCSI_LOG_CONFIG, | |
4799 | "BM_%d : Alloc of MGMT_SGL_ICD Failed" | |
4800 | "for the CID : %d\n", | |
4801 | beiscsi_conn-> | |
4802 | beiscsi_conn_cid); | |
2afc95bf | 4803 | goto free_hndls; |
8359c79b | 4804 | } |
d2cecf0d JK |
4805 | io_task->pwrb_handle = |
4806 | alloc_wrb_handle(phba, | |
a7909b39 | 4807 | beiscsi_conn->beiscsi_conn_cid); |
8359c79b JSJ |
4808 | if (!io_task->pwrb_handle) { |
4809 | beiscsi_log(phba, KERN_ERR, | |
4810 | BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, | |
4811 | "BM_%d : Alloc of WRB_HANDLE Failed" | |
4812 | "for the CID : %d\n", | |
4813 | beiscsi_conn->beiscsi_conn_cid); | |
d2cecf0d | 4814 | goto free_mgmt_hndls; |
8359c79b | 4815 | } |
d2cecf0d | 4816 | |
6733b39a JK |
4817 | } |
4818 | } | |
bfead3b2 JK |
4819 | itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle-> |
4820 | wrb_index << 16) | (unsigned int) | |
4821 | (io_task->psgl_handle->sgl_index)); | |
32951dd8 | 4822 | io_task->pwrb_handle->pio_handle = task; |
bfead3b2 | 4823 | |
6733b39a JK |
4824 | io_task->cmd_bhs->iscsi_hdr.itt = itt; |
4825 | return 0; | |
2afc95bf | 4826 | |
d2cecf0d JK |
4827 | free_io_hndls: |
4828 | spin_lock(&phba->io_sgl_lock); | |
4829 | free_io_sgl_handle(phba, io_task->psgl_handle); | |
4830 | spin_unlock(&phba->io_sgl_lock); | |
4831 | goto free_hndls; | |
4832 | free_mgmt_hndls: | |
4833 | spin_lock(&phba->mgmt_sgl_lock); | |
4834 | free_mgmt_sgl_handle(phba, io_task->psgl_handle); | |
a7909b39 | 4835 | io_task->psgl_handle = NULL; |
d2cecf0d | 4836 | spin_unlock(&phba->mgmt_sgl_lock); |
2afc95bf JK |
4837 | free_hndls: |
4838 | phwi_ctrlr = phba->phwi_ctrlr; | |
a7909b39 JK |
4839 | cri_index = BE_GET_CRI_FROM_CID( |
4840 | beiscsi_conn->beiscsi_conn_cid); | |
4841 | pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; | |
d2cecf0d JK |
4842 | if (io_task->pwrb_handle) |
4843 | free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle); | |
2afc95bf JK |
4844 | io_task->pwrb_handle = NULL; |
4845 | pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs, | |
4846 | io_task->bhs_pa.u.a64.address); | |
1282ab76 | 4847 | io_task->cmd_bhs = NULL; |
2afc95bf | 4848 | return -ENOMEM; |
6733b39a | 4849 | } |
09a1093a JSJ |
4850 | int beiscsi_iotask_v2(struct iscsi_task *task, struct scatterlist *sg, |
4851 | unsigned int num_sg, unsigned int xferlen, | |
4852 | unsigned int writedir) | |
4853 | { | |
4854 | ||
4855 | struct beiscsi_io_task *io_task = task->dd_data; | |
4856 | struct iscsi_conn *conn = task->conn; | |
4857 | struct beiscsi_conn *beiscsi_conn = conn->dd_data; | |
4858 | struct beiscsi_hba *phba = beiscsi_conn->phba; | |
4859 | struct iscsi_wrb *pwrb = NULL; | |
4860 | unsigned int doorbell = 0; | |
4861 | ||
4862 | pwrb = io_task->pwrb_handle->pwrb; | |
09a1093a JSJ |
4863 | |
4864 | io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0; | |
4865 | io_task->bhs_len = sizeof(struct be_cmd_bhs); | |
4866 | ||
4867 | if (writedir) { | |
4868 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb, | |
4869 | INI_WR_CMD); | |
4870 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 1); | |
4871 | } else { | |
4872 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb, | |
4873 | INI_RD_CMD); | |
4874 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 0); | |
4875 | } | |
4876 | ||
4877 | io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb_v2, | |
4878 | type, pwrb); | |
4879 | ||
4880 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, lun, pwrb, | |
4881 | cpu_to_be16(*(unsigned short *) | |
4882 | &io_task->cmd_bhs->iscsi_hdr.lun)); | |
4883 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb, xferlen); | |
4884 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb, | |
4885 | io_task->pwrb_handle->wrb_index); | |
4886 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb, | |
4887 | be32_to_cpu(task->cmdsn)); | |
4888 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb, | |
4889 | io_task->psgl_handle->sgl_index); | |
4890 | ||
4891 | hwi_write_sgl_v2(pwrb, sg, num_sg, io_task); | |
4892 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb, | |
4893 | io_task->pwrb_handle->nxt_wrb_index); | |
4894 | ||
4895 | be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb)); | |
4896 | ||
4897 | doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK; | |
4898 | doorbell |= (io_task->pwrb_handle->wrb_index & | |
4899 | DB_DEF_PDU_WRB_INDEX_MASK) << | |
4900 | DB_DEF_PDU_WRB_INDEX_SHIFT; | |
4901 | doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT; | |
1e4be6ff JK |
4902 | iowrite32(doorbell, phba->db_va + |
4903 | beiscsi_conn->doorbell_offset); | |
09a1093a JSJ |
4904 | return 0; |
4905 | } | |
6733b39a | 4906 | |
6733b39a JK |
4907 | static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg, |
4908 | unsigned int num_sg, unsigned int xferlen, | |
4909 | unsigned int writedir) | |
4910 | { | |
4911 | ||
4912 | struct beiscsi_io_task *io_task = task->dd_data; | |
4913 | struct iscsi_conn *conn = task->conn; | |
4914 | struct beiscsi_conn *beiscsi_conn = conn->dd_data; | |
4915 | struct beiscsi_hba *phba = beiscsi_conn->phba; | |
4916 | struct iscsi_wrb *pwrb = NULL; | |
4917 | unsigned int doorbell = 0; | |
4918 | ||
4919 | pwrb = io_task->pwrb_handle->pwrb; | |
6733b39a JK |
4920 | io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0; |
4921 | io_task->bhs_len = sizeof(struct be_cmd_bhs); | |
4922 | ||
4923 | if (writedir) { | |
32951dd8 JK |
4924 | AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb, |
4925 | INI_WR_CMD); | |
6733b39a | 4926 | AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1); |
6733b39a | 4927 | } else { |
32951dd8 JK |
4928 | AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb, |
4929 | INI_RD_CMD); | |
6733b39a JK |
4930 | AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0); |
4931 | } | |
6733b39a | 4932 | |
09a1093a JSJ |
4933 | io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb, |
4934 | type, pwrb); | |
4935 | ||
6733b39a | 4936 | AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb, |
dc63aac6 JK |
4937 | cpu_to_be16(*(unsigned short *) |
4938 | &io_task->cmd_bhs->iscsi_hdr.lun)); | |
6733b39a JK |
4939 | AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen); |
4940 | AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb, | |
4941 | io_task->pwrb_handle->wrb_index); | |
4942 | AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, | |
4943 | be32_to_cpu(task->cmdsn)); | |
4944 | AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb, | |
4945 | io_task->psgl_handle->sgl_index); | |
4946 | ||
4947 | hwi_write_sgl(pwrb, sg, num_sg, io_task); | |
4948 | ||
4949 | AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb, | |
4950 | io_task->pwrb_handle->nxt_wrb_index); | |
4951 | be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb)); | |
4952 | ||
4953 | doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK; | |
32951dd8 | 4954 | doorbell |= (io_task->pwrb_handle->wrb_index & |
6733b39a JK |
4955 | DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT; |
4956 | doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT; | |
4957 | ||
1e4be6ff JK |
4958 | iowrite32(doorbell, phba->db_va + |
4959 | beiscsi_conn->doorbell_offset); | |
6733b39a JK |
4960 | return 0; |
4961 | } | |
4962 | ||
4963 | static int beiscsi_mtask(struct iscsi_task *task) | |
4964 | { | |
dafab8e0 | 4965 | struct beiscsi_io_task *io_task = task->dd_data; |
6733b39a JK |
4966 | struct iscsi_conn *conn = task->conn; |
4967 | struct beiscsi_conn *beiscsi_conn = conn->dd_data; | |
4968 | struct beiscsi_hba *phba = beiscsi_conn->phba; | |
4969 | struct iscsi_wrb *pwrb = NULL; | |
4970 | unsigned int doorbell = 0; | |
dafab8e0 | 4971 | unsigned int cid; |
09a1093a | 4972 | unsigned int pwrb_typeoffset = 0; |
6733b39a | 4973 | |
bfead3b2 | 4974 | cid = beiscsi_conn->beiscsi_conn_cid; |
6733b39a | 4975 | pwrb = io_task->pwrb_handle->pwrb; |
caf818f1 | 4976 | memset(pwrb, 0, sizeof(*pwrb)); |
09a1093a | 4977 | |
2c9dfd36 | 4978 | if (is_chip_be2_be3r(phba)) { |
09a1093a JSJ |
4979 | AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, |
4980 | be32_to_cpu(task->cmdsn)); | |
4981 | AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb, | |
4982 | io_task->pwrb_handle->wrb_index); | |
4983 | AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb, | |
4984 | io_task->psgl_handle->sgl_index); | |
4985 | AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, | |
4986 | task->data_count); | |
4987 | AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb, | |
4988 | io_task->pwrb_handle->nxt_wrb_index); | |
4989 | pwrb_typeoffset = BE_WRB_TYPE_OFFSET; | |
2c9dfd36 JK |
4990 | } else { |
4991 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb, | |
4992 | be32_to_cpu(task->cmdsn)); | |
4993 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb, | |
4994 | io_task->pwrb_handle->wrb_index); | |
4995 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb, | |
4996 | io_task->psgl_handle->sgl_index); | |
4997 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb, | |
4998 | task->data_count); | |
4999 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb, | |
5000 | io_task->pwrb_handle->nxt_wrb_index); | |
5001 | pwrb_typeoffset = SKH_WRB_TYPE_OFFSET; | |
09a1093a JSJ |
5002 | } |
5003 | ||
dafab8e0 | 5004 | |
6733b39a JK |
5005 | switch (task->hdr->opcode & ISCSI_OPCODE_MASK) { |
5006 | case ISCSI_OP_LOGIN: | |
6733b39a | 5007 | AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1); |
09a1093a | 5008 | ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset); |
6733b39a JK |
5009 | hwi_write_buffer(pwrb, task); |
5010 | break; | |
5011 | case ISCSI_OP_NOOP_OUT: | |
1390b01b | 5012 | if (task->hdr->ttt != ISCSI_RESERVED_TAG) { |
09a1093a | 5013 | ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset); |
2c9dfd36 JK |
5014 | if (is_chip_be2_be3r(phba)) |
5015 | AMAP_SET_BITS(struct amap_iscsi_wrb, | |
09a1093a JSJ |
5016 | dmsg, pwrb, 1); |
5017 | else | |
2c9dfd36 | 5018 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, |
09a1093a | 5019 | dmsg, pwrb, 1); |
1390b01b | 5020 | } else { |
09a1093a | 5021 | ADAPTER_SET_WRB_TYPE(pwrb, INI_RD_CMD, pwrb_typeoffset); |
2c9dfd36 JK |
5022 | if (is_chip_be2_be3r(phba)) |
5023 | AMAP_SET_BITS(struct amap_iscsi_wrb, | |
09a1093a JSJ |
5024 | dmsg, pwrb, 0); |
5025 | else | |
2c9dfd36 | 5026 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, |
09a1093a | 5027 | dmsg, pwrb, 0); |
1390b01b | 5028 | } |
6733b39a JK |
5029 | hwi_write_buffer(pwrb, task); |
5030 | break; | |
5031 | case ISCSI_OP_TEXT: | |
09a1093a | 5032 | ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset); |
6733b39a JK |
5033 | hwi_write_buffer(pwrb, task); |
5034 | break; | |
5035 | case ISCSI_OP_SCSI_TMFUNC: | |
09a1093a | 5036 | ADAPTER_SET_WRB_TYPE(pwrb, INI_TMF_CMD, pwrb_typeoffset); |
6733b39a JK |
5037 | hwi_write_buffer(pwrb, task); |
5038 | break; | |
5039 | case ISCSI_OP_LOGOUT: | |
09a1093a | 5040 | ADAPTER_SET_WRB_TYPE(pwrb, HWH_TYPE_LOGOUT, pwrb_typeoffset); |
6733b39a JK |
5041 | hwi_write_buffer(pwrb, task); |
5042 | break; | |
5043 | ||
5044 | default: | |
99bc5d55 JSJ |
5045 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG, |
5046 | "BM_%d : opcode =%d Not supported\n", | |
5047 | task->hdr->opcode & ISCSI_OPCODE_MASK); | |
5048 | ||
6733b39a JK |
5049 | return -EINVAL; |
5050 | } | |
5051 | ||
09a1093a | 5052 | /* Set the task type */ |
2c9dfd36 JK |
5053 | io_task->wrb_type = (is_chip_be2_be3r(phba)) ? |
5054 | AMAP_GET_BITS(struct amap_iscsi_wrb, type, pwrb) : | |
5055 | AMAP_GET_BITS(struct amap_iscsi_wrb_v2, type, pwrb); | |
6733b39a | 5056 | |
bfead3b2 | 5057 | doorbell |= cid & DB_WRB_POST_CID_MASK; |
32951dd8 | 5058 | doorbell |= (io_task->pwrb_handle->wrb_index & |
6733b39a JK |
5059 | DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT; |
5060 | doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT; | |
1e4be6ff JK |
5061 | iowrite32(doorbell, phba->db_va + |
5062 | beiscsi_conn->doorbell_offset); | |
6733b39a JK |
5063 | return 0; |
5064 | } | |
5065 | ||
5066 | static int beiscsi_task_xmit(struct iscsi_task *task) | |
5067 | { | |
6733b39a JK |
5068 | struct beiscsi_io_task *io_task = task->dd_data; |
5069 | struct scsi_cmnd *sc = task->sc; | |
09a1093a | 5070 | struct beiscsi_hba *phba = NULL; |
6733b39a JK |
5071 | struct scatterlist *sg; |
5072 | int num_sg; | |
5073 | unsigned int writedir = 0, xferlen = 0; | |
5074 | ||
09a1093a JSJ |
5075 | phba = ((struct beiscsi_conn *)task->conn->dd_data)->phba; |
5076 | ||
6733b39a JK |
5077 | if (!sc) |
5078 | return beiscsi_mtask(task); | |
5079 | ||
5080 | io_task->scsi_cmnd = sc; | |
5081 | num_sg = scsi_dma_map(sc); | |
5082 | if (num_sg < 0) { | |
99bc5d55 JSJ |
5083 | struct iscsi_conn *conn = task->conn; |
5084 | struct beiscsi_hba *phba = NULL; | |
5085 | ||
5086 | phba = ((struct beiscsi_conn *)conn->dd_data)->phba; | |
afb96058 JK |
5087 | beiscsi_log(phba, KERN_ERR, |
5088 | BEISCSI_LOG_IO | BEISCSI_LOG_ISCSI, | |
5089 | "BM_%d : scsi_dma_map Failed " | |
5090 | "Driver_ITT : 0x%x ITT : 0x%x Xferlen : 0x%x\n", | |
5091 | be32_to_cpu(io_task->cmd_bhs->iscsi_hdr.itt), | |
5092 | io_task->libiscsi_itt, scsi_bufflen(sc)); | |
99bc5d55 | 5093 | |
6733b39a JK |
5094 | return num_sg; |
5095 | } | |
6733b39a JK |
5096 | xferlen = scsi_bufflen(sc); |
5097 | sg = scsi_sglist(sc); | |
99bc5d55 | 5098 | if (sc->sc_data_direction == DMA_TO_DEVICE) |
6733b39a | 5099 | writedir = 1; |
99bc5d55 | 5100 | else |
6733b39a | 5101 | writedir = 0; |
99bc5d55 | 5102 | |
09a1093a | 5103 | return phba->iotask_fn(task, sg, num_sg, xferlen, writedir); |
6733b39a JK |
5104 | } |
5105 | ||
ffce3e2e JK |
5106 | /** |
5107 | * beiscsi_bsg_request - handle bsg request from ISCSI transport | |
5108 | * @job: job to handle | |
5109 | */ | |
5110 | static int beiscsi_bsg_request(struct bsg_job *job) | |
5111 | { | |
5112 | struct Scsi_Host *shost; | |
5113 | struct beiscsi_hba *phba; | |
5114 | struct iscsi_bsg_request *bsg_req = job->request; | |
5115 | int rc = -EINVAL; | |
5116 | unsigned int tag; | |
5117 | struct be_dma_mem nonemb_cmd; | |
5118 | struct be_cmd_resp_hdr *resp; | |
5119 | struct iscsi_bsg_reply *bsg_reply = job->reply; | |
5120 | unsigned short status, extd_status; | |
5121 | ||
5122 | shost = iscsi_job_to_shost(job); | |
5123 | phba = iscsi_host_priv(shost); | |
5124 | ||
5125 | switch (bsg_req->msgcode) { | |
5126 | case ISCSI_BSG_HST_VENDOR: | |
5127 | nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev, | |
5128 | job->request_payload.payload_len, | |
5129 | &nonemb_cmd.dma); | |
5130 | if (nonemb_cmd.va == NULL) { | |
99bc5d55 JSJ |
5131 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG, |
5132 | "BM_%d : Failed to allocate memory for " | |
5133 | "beiscsi_bsg_request\n"); | |
8359c79b | 5134 | return -ENOMEM; |
ffce3e2e JK |
5135 | } |
5136 | tag = mgmt_vendor_specific_fw_cmd(&phba->ctrl, phba, job, | |
5137 | &nonemb_cmd); | |
5138 | if (!tag) { | |
99bc5d55 | 5139 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG, |
8359c79b | 5140 | "BM_%d : MBX Tag Allocation Failed\n"); |
99bc5d55 | 5141 | |
ffce3e2e JK |
5142 | pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, |
5143 | nonemb_cmd.va, nonemb_cmd.dma); | |
5144 | return -EAGAIN; | |
e175defe JSJ |
5145 | } |
5146 | ||
5147 | rc = wait_event_interruptible_timeout( | |
5148 | phba->ctrl.mcc_wait[tag], | |
5149 | phba->ctrl.mcc_numtag[tag], | |
5150 | msecs_to_jiffies( | |
5151 | BEISCSI_HOST_MBX_TIMEOUT)); | |
ffce3e2e JK |
5152 | extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8; |
5153 | status = phba->ctrl.mcc_numtag[tag] & 0x000000FF; | |
5154 | free_mcc_tag(&phba->ctrl, tag); | |
5155 | resp = (struct be_cmd_resp_hdr *)nonemb_cmd.va; | |
5156 | sg_copy_from_buffer(job->reply_payload.sg_list, | |
5157 | job->reply_payload.sg_cnt, | |
5158 | nonemb_cmd.va, (resp->response_length | |
5159 | + sizeof(*resp))); | |
5160 | bsg_reply->reply_payload_rcv_len = resp->response_length; | |
5161 | bsg_reply->result = status; | |
5162 | bsg_job_done(job, bsg_reply->result, | |
5163 | bsg_reply->reply_payload_rcv_len); | |
5164 | pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, | |
5165 | nonemb_cmd.va, nonemb_cmd.dma); | |
5166 | if (status || extd_status) { | |
99bc5d55 | 5167 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG, |
8359c79b | 5168 | "BM_%d : MBX Cmd Failed" |
99bc5d55 JSJ |
5169 | " status = %d extd_status = %d\n", |
5170 | status, extd_status); | |
5171 | ||
ffce3e2e | 5172 | return -EIO; |
8359c79b JSJ |
5173 | } else { |
5174 | rc = 0; | |
ffce3e2e JK |
5175 | } |
5176 | break; | |
5177 | ||
5178 | default: | |
99bc5d55 JSJ |
5179 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG, |
5180 | "BM_%d : Unsupported bsg command: 0x%x\n", | |
5181 | bsg_req->msgcode); | |
ffce3e2e JK |
5182 | break; |
5183 | } | |
5184 | ||
5185 | return rc; | |
5186 | } | |
5187 | ||
99bc5d55 JSJ |
5188 | void beiscsi_hba_attrs_init(struct beiscsi_hba *phba) |
5189 | { | |
5190 | /* Set the logging parameter */ | |
5191 | beiscsi_log_enable_init(phba, beiscsi_log_enable); | |
5192 | } | |
5193 | ||
4d4d1ef8 JSJ |
5194 | /* |
5195 | * beiscsi_quiesce()- Cleanup Driver resources | |
5196 | * @phba: Instance Priv structure | |
3567f36a | 5197 | * @unload_state:i Clean or EEH unload state |
4d4d1ef8 JSJ |
5198 | * |
5199 | * Free the OS and HW resources held by the driver | |
5200 | **/ | |
3567f36a JK |
5201 | static void beiscsi_quiesce(struct beiscsi_hba *phba, |
5202 | uint32_t unload_state) | |
6733b39a | 5203 | { |
bfead3b2 JK |
5204 | struct hwi_controller *phwi_ctrlr; |
5205 | struct hwi_context_memory *phwi_context; | |
5206 | struct be_eq_obj *pbe_eq; | |
5207 | unsigned int i, msix_vec; | |
6733b39a | 5208 | |
bfead3b2 JK |
5209 | phwi_ctrlr = phba->phwi_ctrlr; |
5210 | phwi_context = phwi_ctrlr->phwi_ctxt; | |
6733b39a | 5211 | hwi_disable_intr(phba); |
bfead3b2 JK |
5212 | if (phba->msix_enabled) { |
5213 | for (i = 0; i <= phba->num_cpus; i++) { | |
5214 | msix_vec = phba->msix_entries[i].vector; | |
3567f36a | 5215 | synchronize_irq(msix_vec); |
bfead3b2 | 5216 | free_irq(msix_vec, &phwi_context->be_eq[i]); |
8fcfb210 | 5217 | kfree(phba->msi_name[i]); |
bfead3b2 JK |
5218 | } |
5219 | } else | |
3567f36a JK |
5220 | if (phba->pcidev->irq) { |
5221 | synchronize_irq(phba->pcidev->irq); | |
bfead3b2 | 5222 | free_irq(phba->pcidev->irq, phba); |
3567f36a | 5223 | } |
bfead3b2 | 5224 | pci_disable_msix(phba->pcidev); |
53281edb | 5225 | cancel_delayed_work_sync(&phba->beiscsi_hw_check_task); |
3567f36a | 5226 | |
89f8b33c JA |
5227 | for (i = 0; i < phba->num_cpus; i++) { |
5228 | pbe_eq = &phwi_context->be_eq[i]; | |
5229 | blk_iopoll_disable(&pbe_eq->iopoll); | |
5230 | } | |
6733b39a | 5231 | |
3567f36a JK |
5232 | if (unload_state == BEISCSI_CLEAN_UNLOAD) { |
5233 | destroy_workqueue(phba->wq); | |
5234 | beiscsi_clean_port(phba); | |
5235 | beiscsi_free_mem(phba); | |
e9b91193 | 5236 | |
3567f36a JK |
5237 | beiscsi_unmap_pci_function(phba); |
5238 | pci_free_consistent(phba->pcidev, | |
5239 | phba->ctrl.mbox_mem_alloced.size, | |
5240 | phba->ctrl.mbox_mem_alloced.va, | |
5241 | phba->ctrl.mbox_mem_alloced.dma); | |
5242 | } else { | |
5243 | hwi_purge_eq(phba); | |
5244 | hwi_cleanup(phba); | |
5245 | } | |
7a158003 | 5246 | |
25602c97 JK |
5247 | } |
5248 | ||
5249 | static void beiscsi_remove(struct pci_dev *pcidev) | |
5250 | { | |
5251 | ||
5252 | struct beiscsi_hba *phba = NULL; | |
5253 | ||
5254 | phba = pci_get_drvdata(pcidev); | |
5255 | if (!phba) { | |
5256 | dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n"); | |
5257 | return; | |
5258 | } | |
5259 | ||
0e43895e | 5260 | beiscsi_destroy_def_ifaces(phba); |
3567f36a | 5261 | beiscsi_quiesce(phba, BEISCSI_CLEAN_UNLOAD); |
9d045163 | 5262 | iscsi_boot_destroy_kset(phba->boot_kset); |
6733b39a JK |
5263 | iscsi_host_remove(phba->shost); |
5264 | pci_dev_put(phba->pcidev); | |
5265 | iscsi_host_free(phba->shost); | |
3567f36a JK |
5266 | pci_disable_pcie_error_reporting(pcidev); |
5267 | pci_set_drvdata(pcidev, NULL); | |
8dce69ff | 5268 | pci_disable_device(pcidev); |
6733b39a JK |
5269 | } |
5270 | ||
25602c97 JK |
5271 | static void beiscsi_shutdown(struct pci_dev *pcidev) |
5272 | { | |
5273 | ||
5274 | struct beiscsi_hba *phba = NULL; | |
5275 | ||
5276 | phba = (struct beiscsi_hba *)pci_get_drvdata(pcidev); | |
5277 | if (!phba) { | |
5278 | dev_err(&pcidev->dev, "beiscsi_shutdown called with no phba\n"); | |
5279 | return; | |
5280 | } | |
5281 | ||
9343be74 JK |
5282 | phba->state = BE_ADAPTER_STATE_SHUTDOWN; |
5283 | iscsi_host_for_each_session(phba->shost, be2iscsi_fail_session); | |
3567f36a | 5284 | beiscsi_quiesce(phba, BEISCSI_CLEAN_UNLOAD); |
8dce69ff | 5285 | pci_disable_device(pcidev); |
25602c97 JK |
5286 | } |
5287 | ||
bfead3b2 JK |
5288 | static void beiscsi_msix_enable(struct beiscsi_hba *phba) |
5289 | { | |
5290 | int i, status; | |
5291 | ||
5292 | for (i = 0; i <= phba->num_cpus; i++) | |
5293 | phba->msix_entries[i].entry = i; | |
5294 | ||
e149fc13 AG |
5295 | status = pci_enable_msix_range(phba->pcidev, phba->msix_entries, |
5296 | phba->num_cpus + 1, phba->num_cpus + 1); | |
5297 | if (status > 0) | |
bfead3b2 JK |
5298 | phba->msix_enabled = true; |
5299 | ||
5300 | return; | |
5301 | } | |
5302 | ||
73af08e1 JK |
5303 | static void be_eqd_update(struct beiscsi_hba *phba) |
5304 | { | |
5305 | struct be_set_eqd set_eqd[MAX_CPUS]; | |
5306 | struct be_aic_obj *aic; | |
5307 | struct be_eq_obj *pbe_eq; | |
5308 | struct hwi_controller *phwi_ctrlr; | |
5309 | struct hwi_context_memory *phwi_context; | |
5310 | int eqd, i, num = 0; | |
5311 | ulong now; | |
5312 | u32 pps, delta; | |
5313 | unsigned int tag; | |
5314 | ||
5315 | phwi_ctrlr = phba->phwi_ctrlr; | |
5316 | phwi_context = phwi_ctrlr->phwi_ctxt; | |
5317 | ||
5318 | for (i = 0; i <= phba->num_cpus; i++) { | |
5319 | aic = &phba->aic_obj[i]; | |
5320 | pbe_eq = &phwi_context->be_eq[i]; | |
5321 | now = jiffies; | |
5322 | if (!aic->jiffs || time_before(now, aic->jiffs) || | |
5323 | pbe_eq->cq_count < aic->eq_prev) { | |
5324 | aic->jiffs = now; | |
5325 | aic->eq_prev = pbe_eq->cq_count; | |
5326 | continue; | |
5327 | } | |
5328 | delta = jiffies_to_msecs(now - aic->jiffs); | |
5329 | pps = (((u32)(pbe_eq->cq_count - aic->eq_prev) * 1000) / delta); | |
5330 | eqd = (pps / 1500) << 2; | |
5331 | ||
5332 | if (eqd < 8) | |
5333 | eqd = 0; | |
5334 | eqd = min_t(u32, eqd, phwi_context->max_eqd); | |
5335 | eqd = max_t(u32, eqd, phwi_context->min_eqd); | |
5336 | ||
5337 | aic->jiffs = now; | |
5338 | aic->eq_prev = pbe_eq->cq_count; | |
5339 | ||
5340 | if (eqd != aic->prev_eqd) { | |
5341 | set_eqd[num].delay_multiplier = (eqd * 65)/100; | |
5342 | set_eqd[num].eq_id = pbe_eq->q.id; | |
5343 | aic->prev_eqd = eqd; | |
5344 | num++; | |
5345 | } | |
5346 | } | |
5347 | if (num) { | |
5348 | tag = be_cmd_modify_eq_delay(phba, set_eqd, num); | |
5349 | if (tag) | |
5350 | beiscsi_mccq_compl(phba, tag, NULL, NULL); | |
5351 | } | |
5352 | } | |
5353 | ||
a3d313ea JK |
5354 | static void be_check_boot_session(struct beiscsi_hba *phba) |
5355 | { | |
5356 | if (beiscsi_setup_boot_info(phba)) | |
5357 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
5358 | "BM_%d : Could not set up " | |
5359 | "iSCSI boot info on async event.\n"); | |
5360 | } | |
5361 | ||
7a158003 JSJ |
5362 | /* |
5363 | * beiscsi_hw_health_check()- Check adapter health | |
5364 | * @work: work item to check HW health | |
5365 | * | |
5366 | * Check if adapter in an unrecoverable state or not. | |
5367 | **/ | |
5368 | static void | |
5369 | beiscsi_hw_health_check(struct work_struct *work) | |
5370 | { | |
5371 | struct beiscsi_hba *phba = | |
5372 | container_of(work, struct beiscsi_hba, | |
5373 | beiscsi_hw_check_task.work); | |
5374 | ||
73af08e1 JK |
5375 | be_eqd_update(phba); |
5376 | ||
a3d313ea JK |
5377 | if (phba->state & BE_ADAPTER_CHECK_BOOT) { |
5378 | phba->state &= ~BE_ADAPTER_CHECK_BOOT; | |
5379 | be_check_boot_session(phba); | |
5380 | } | |
5381 | ||
7a158003 JSJ |
5382 | beiscsi_ue_detect(phba); |
5383 | ||
5384 | schedule_delayed_work(&phba->beiscsi_hw_check_task, | |
5385 | msecs_to_jiffies(1000)); | |
5386 | } | |
5387 | ||
3567f36a JK |
5388 | |
5389 | static pci_ers_result_t beiscsi_eeh_err_detected(struct pci_dev *pdev, | |
5390 | pci_channel_state_t state) | |
5391 | { | |
5392 | struct beiscsi_hba *phba = NULL; | |
5393 | ||
5394 | phba = (struct beiscsi_hba *)pci_get_drvdata(pdev); | |
5395 | phba->state |= BE_ADAPTER_PCI_ERR; | |
5396 | ||
5397 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
5398 | "BM_%d : EEH error detected\n"); | |
5399 | ||
5400 | beiscsi_quiesce(phba, BEISCSI_EEH_UNLOAD); | |
5401 | ||
5402 | if (state == pci_channel_io_perm_failure) { | |
5403 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
5404 | "BM_%d : EEH : State PERM Failure"); | |
5405 | return PCI_ERS_RESULT_DISCONNECT; | |
5406 | } | |
5407 | ||
5408 | pci_disable_device(pdev); | |
5409 | ||
5410 | /* The error could cause the FW to trigger a flash debug dump. | |
5411 | * Resetting the card while flash dump is in progress | |
5412 | * can cause it not to recover; wait for it to finish. | |
5413 | * Wait only for first function as it is needed only once per | |
5414 | * adapter. | |
5415 | **/ | |
5416 | if (pdev->devfn == 0) | |
5417 | ssleep(30); | |
5418 | ||
5419 | return PCI_ERS_RESULT_NEED_RESET; | |
5420 | } | |
5421 | ||
5422 | static pci_ers_result_t beiscsi_eeh_reset(struct pci_dev *pdev) | |
5423 | { | |
5424 | struct beiscsi_hba *phba = NULL; | |
5425 | int status = 0; | |
5426 | ||
5427 | phba = (struct beiscsi_hba *)pci_get_drvdata(pdev); | |
5428 | ||
5429 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
5430 | "BM_%d : EEH Reset\n"); | |
5431 | ||
5432 | status = pci_enable_device(pdev); | |
5433 | if (status) | |
5434 | return PCI_ERS_RESULT_DISCONNECT; | |
5435 | ||
5436 | pci_set_master(pdev); | |
5437 | pci_set_power_state(pdev, PCI_D0); | |
5438 | pci_restore_state(pdev); | |
5439 | ||
5440 | /* Wait for the CHIP Reset to complete */ | |
5441 | status = be_chk_reset_complete(phba); | |
5442 | if (!status) { | |
5443 | beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT, | |
5444 | "BM_%d : EEH Reset Completed\n"); | |
5445 | } else { | |
5446 | beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT, | |
5447 | "BM_%d : EEH Reset Completion Failure\n"); | |
5448 | return PCI_ERS_RESULT_DISCONNECT; | |
5449 | } | |
5450 | ||
5451 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
5452 | return PCI_ERS_RESULT_RECOVERED; | |
5453 | } | |
5454 | ||
5455 | static void beiscsi_eeh_resume(struct pci_dev *pdev) | |
5456 | { | |
5457 | int ret = 0, i; | |
5458 | struct be_eq_obj *pbe_eq; | |
5459 | struct beiscsi_hba *phba = NULL; | |
5460 | struct hwi_controller *phwi_ctrlr; | |
5461 | struct hwi_context_memory *phwi_context; | |
5462 | ||
5463 | phba = (struct beiscsi_hba *)pci_get_drvdata(pdev); | |
5464 | pci_save_state(pdev); | |
5465 | ||
5466 | if (enable_msix) | |
5467 | find_num_cpus(phba); | |
5468 | else | |
5469 | phba->num_cpus = 1; | |
5470 | ||
5471 | if (enable_msix) { | |
5472 | beiscsi_msix_enable(phba); | |
5473 | if (!phba->msix_enabled) | |
5474 | phba->num_cpus = 1; | |
5475 | } | |
5476 | ||
5477 | ret = beiscsi_cmd_reset_function(phba); | |
5478 | if (ret) { | |
5479 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
5480 | "BM_%d : Reset Failed\n"); | |
5481 | goto ret_err; | |
5482 | } | |
5483 | ||
5484 | ret = be_chk_reset_complete(phba); | |
5485 | if (ret) { | |
5486 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
5487 | "BM_%d : Failed to get out of reset.\n"); | |
5488 | goto ret_err; | |
5489 | } | |
5490 | ||
5491 | beiscsi_get_params(phba); | |
5492 | phba->shost->max_id = phba->params.cxns_per_ctrl; | |
5493 | phba->shost->can_queue = phba->params.ios_per_ctrl; | |
5494 | ret = hwi_init_controller(phba); | |
5495 | ||
5496 | for (i = 0; i < MAX_MCC_CMD; i++) { | |
5497 | init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]); | |
5498 | phba->ctrl.mcc_tag[i] = i + 1; | |
5499 | phba->ctrl.mcc_numtag[i + 1] = 0; | |
5500 | phba->ctrl.mcc_tag_available++; | |
5501 | } | |
5502 | ||
5503 | phwi_ctrlr = phba->phwi_ctrlr; | |
5504 | phwi_context = phwi_ctrlr->phwi_ctxt; | |
5505 | ||
89f8b33c | 5506 | for (i = 0; i < phba->num_cpus; i++) { |
3567f36a | 5507 | pbe_eq = &phwi_context->be_eq[i]; |
89f8b33c JA |
5508 | blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget, |
5509 | be_iopoll); | |
5510 | blk_iopoll_enable(&pbe_eq->iopoll); | |
3567f36a JK |
5511 | } |
5512 | ||
89f8b33c JA |
5513 | i = (phba->msix_enabled) ? i : 0; |
5514 | /* Work item for MCC handling */ | |
5515 | pbe_eq = &phwi_context->be_eq[i]; | |
5516 | INIT_WORK(&pbe_eq->work_cqs, beiscsi_process_all_cqs); | |
5517 | ||
3567f36a JK |
5518 | ret = beiscsi_init_irqs(phba); |
5519 | if (ret < 0) { | |
5520 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
5521 | "BM_%d : beiscsi_eeh_resume - " | |
5522 | "Failed to beiscsi_init_irqs\n"); | |
5523 | goto ret_err; | |
5524 | } | |
5525 | ||
5526 | hwi_enable_intr(phba); | |
5527 | phba->state &= ~BE_ADAPTER_PCI_ERR; | |
5528 | ||
5529 | return; | |
5530 | ret_err: | |
5531 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
5532 | "BM_%d : AER EEH Resume Failed\n"); | |
5533 | } | |
5534 | ||
6f039790 GKH |
5535 | static int beiscsi_dev_probe(struct pci_dev *pcidev, |
5536 | const struct pci_device_id *id) | |
6733b39a JK |
5537 | { |
5538 | struct beiscsi_hba *phba = NULL; | |
bfead3b2 JK |
5539 | struct hwi_controller *phwi_ctrlr; |
5540 | struct hwi_context_memory *phwi_context; | |
5541 | struct be_eq_obj *pbe_eq; | |
3567f36a | 5542 | int ret = 0, i; |
6733b39a JK |
5543 | |
5544 | ret = beiscsi_enable_pci(pcidev); | |
5545 | if (ret < 0) { | |
99bc5d55 JSJ |
5546 | dev_err(&pcidev->dev, |
5547 | "beiscsi_dev_probe - Failed to enable pci device\n"); | |
6733b39a JK |
5548 | return ret; |
5549 | } | |
5550 | ||
5551 | phba = beiscsi_hba_alloc(pcidev); | |
5552 | if (!phba) { | |
99bc5d55 JSJ |
5553 | dev_err(&pcidev->dev, |
5554 | "beiscsi_dev_probe - Failed in beiscsi_hba_alloc\n"); | |
6733b39a JK |
5555 | goto disable_pci; |
5556 | } | |
5557 | ||
3567f36a JK |
5558 | /* Enable EEH reporting */ |
5559 | ret = pci_enable_pcie_error_reporting(pcidev); | |
5560 | if (ret) | |
5561 | beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT, | |
5562 | "BM_%d : PCIe Error Reporting " | |
5563 | "Enabling Failed\n"); | |
5564 | ||
5565 | pci_save_state(pcidev); | |
5566 | ||
99bc5d55 JSJ |
5567 | /* Initialize Driver configuration Paramters */ |
5568 | beiscsi_hba_attrs_init(phba); | |
5569 | ||
e175defe | 5570 | phba->fw_timeout = false; |
6c83185a | 5571 | phba->mac_addr_set = false; |
e175defe JSJ |
5572 | |
5573 | ||
f98c96b0 JK |
5574 | switch (pcidev->device) { |
5575 | case BE_DEVICE_ID1: | |
5576 | case OC_DEVICE_ID1: | |
5577 | case OC_DEVICE_ID2: | |
5578 | phba->generation = BE_GEN2; | |
09a1093a | 5579 | phba->iotask_fn = beiscsi_iotask; |
f98c96b0 JK |
5580 | break; |
5581 | case BE_DEVICE_ID2: | |
5582 | case OC_DEVICE_ID3: | |
5583 | phba->generation = BE_GEN3; | |
09a1093a | 5584 | phba->iotask_fn = beiscsi_iotask; |
f98c96b0 | 5585 | break; |
139a1b1e JSJ |
5586 | case OC_SKH_ID1: |
5587 | phba->generation = BE_GEN4; | |
09a1093a | 5588 | phba->iotask_fn = beiscsi_iotask_v2; |
bf9131cb | 5589 | break; |
f98c96b0 JK |
5590 | default: |
5591 | phba->generation = 0; | |
5592 | } | |
5593 | ||
6733b39a JK |
5594 | ret = be_ctrl_init(phba, pcidev); |
5595 | if (ret) { | |
99bc5d55 JSJ |
5596 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
5597 | "BM_%d : beiscsi_dev_probe-" | |
5598 | "Failed in be_ctrl_init\n"); | |
6733b39a JK |
5599 | goto hba_free; |
5600 | } | |
5601 | ||
4d4d1ef8 JSJ |
5602 | ret = beiscsi_cmd_reset_function(phba); |
5603 | if (ret) { | |
5604 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
92665a66 | 5605 | "BM_%d : Reset Failed\n"); |
4d4d1ef8 JSJ |
5606 | goto hba_free; |
5607 | } | |
5608 | ret = be_chk_reset_complete(phba); | |
5609 | if (ret) { | |
5610 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
92665a66 | 5611 | "BM_%d : Failed to get out of reset.\n"); |
4d4d1ef8 | 5612 | goto hba_free; |
e9b91193 JK |
5613 | } |
5614 | ||
6733b39a JK |
5615 | spin_lock_init(&phba->io_sgl_lock); |
5616 | spin_lock_init(&phba->mgmt_sgl_lock); | |
5617 | spin_lock_init(&phba->isr_lock); | |
8f09a3b9 | 5618 | spin_lock_init(&phba->async_pdu_lock); |
7da50879 JK |
5619 | ret = mgmt_get_fw_config(&phba->ctrl, phba); |
5620 | if (ret != 0) { | |
99bc5d55 JSJ |
5621 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
5622 | "BM_%d : Error getting fw config\n"); | |
7da50879 JK |
5623 | goto free_port; |
5624 | } | |
68c26a3a JK |
5625 | |
5626 | if (enable_msix) | |
5627 | find_num_cpus(phba); | |
5628 | else | |
5629 | phba->num_cpus = 1; | |
5630 | ||
5631 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, | |
5632 | "BM_%d : num_cpus = %d\n", | |
5633 | phba->num_cpus); | |
5634 | ||
5635 | if (enable_msix) { | |
5636 | beiscsi_msix_enable(phba); | |
5637 | if (!phba->msix_enabled) | |
5638 | phba->num_cpus = 1; | |
5639 | } | |
5640 | ||
843ae752 | 5641 | phba->shost->max_id = phba->params.cxns_per_ctrl; |
6733b39a | 5642 | beiscsi_get_params(phba); |
aa874f07 | 5643 | phba->shost->can_queue = phba->params.ios_per_ctrl; |
6733b39a JK |
5644 | ret = beiscsi_init_port(phba); |
5645 | if (ret < 0) { | |
99bc5d55 JSJ |
5646 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
5647 | "BM_%d : beiscsi_dev_probe-" | |
5648 | "Failed in beiscsi_init_port\n"); | |
6733b39a JK |
5649 | goto free_port; |
5650 | } | |
5651 | ||
3567f36a | 5652 | for (i = 0; i < MAX_MCC_CMD; i++) { |
756d29c8 JK |
5653 | init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]); |
5654 | phba->ctrl.mcc_tag[i] = i + 1; | |
5655 | phba->ctrl.mcc_numtag[i + 1] = 0; | |
5656 | phba->ctrl.mcc_tag_available++; | |
1957aa7f | 5657 | memset(&phba->ctrl.ptag_state[i].tag_mem_state, 0, |
8fc01eaa | 5658 | sizeof(struct be_dma_mem)); |
756d29c8 JK |
5659 | } |
5660 | ||
5661 | phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0; | |
5662 | ||
72fb46a9 | 5663 | snprintf(phba->wq_name, sizeof(phba->wq_name), "beiscsi_%02x_wq", |
6733b39a | 5664 | phba->shost->host_no); |
d8537548 | 5665 | phba->wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 1, phba->wq_name); |
6733b39a | 5666 | if (!phba->wq) { |
99bc5d55 JSJ |
5667 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
5668 | "BM_%d : beiscsi_dev_probe-" | |
5669 | "Failed to allocate work queue\n"); | |
6733b39a JK |
5670 | goto free_twq; |
5671 | } | |
5672 | ||
7a158003 JSJ |
5673 | INIT_DELAYED_WORK(&phba->beiscsi_hw_check_task, |
5674 | beiscsi_hw_health_check); | |
6733b39a | 5675 | |
bfead3b2 JK |
5676 | phwi_ctrlr = phba->phwi_ctrlr; |
5677 | phwi_context = phwi_ctrlr->phwi_ctxt; | |
72fb46a9 | 5678 | |
89f8b33c | 5679 | for (i = 0; i < phba->num_cpus; i++) { |
72fb46a9 | 5680 | pbe_eq = &phwi_context->be_eq[i]; |
89f8b33c JA |
5681 | blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget, |
5682 | be_iopoll); | |
5683 | blk_iopoll_enable(&pbe_eq->iopoll); | |
6733b39a | 5684 | } |
72fb46a9 | 5685 | |
89f8b33c JA |
5686 | i = (phba->msix_enabled) ? i : 0; |
5687 | /* Work item for MCC handling */ | |
5688 | pbe_eq = &phwi_context->be_eq[i]; | |
5689 | INIT_WORK(&pbe_eq->work_cqs, beiscsi_process_all_cqs); | |
5690 | ||
6733b39a JK |
5691 | ret = beiscsi_init_irqs(phba); |
5692 | if (ret < 0) { | |
99bc5d55 JSJ |
5693 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
5694 | "BM_%d : beiscsi_dev_probe-" | |
5695 | "Failed to beiscsi_init_irqs\n"); | |
6733b39a JK |
5696 | goto free_blkenbld; |
5697 | } | |
238f6b72 | 5698 | hwi_enable_intr(phba); |
f457a46f | 5699 | |
0598b8af JK |
5700 | if (iscsi_host_add(phba->shost, &phba->pcidev->dev)) |
5701 | goto free_blkenbld; | |
5702 | ||
f457a46f MC |
5703 | if (beiscsi_setup_boot_info(phba)) |
5704 | /* | |
5705 | * log error but continue, because we may not be using | |
5706 | * iscsi boot. | |
5707 | */ | |
99bc5d55 JSJ |
5708 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
5709 | "BM_%d : Could not set up " | |
5710 | "iSCSI boot info.\n"); | |
f457a46f | 5711 | |
0e43895e | 5712 | beiscsi_create_def_ifaces(phba); |
7a158003 JSJ |
5713 | schedule_delayed_work(&phba->beiscsi_hw_check_task, |
5714 | msecs_to_jiffies(1000)); | |
5715 | ||
99bc5d55 JSJ |
5716 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
5717 | "\n\n\n BM_%d : SUCCESS - DRIVER LOADED\n\n\n"); | |
6733b39a JK |
5718 | return 0; |
5719 | ||
6733b39a JK |
5720 | free_blkenbld: |
5721 | destroy_workqueue(phba->wq); | |
89f8b33c JA |
5722 | for (i = 0; i < phba->num_cpus; i++) { |
5723 | pbe_eq = &phwi_context->be_eq[i]; | |
5724 | blk_iopoll_disable(&pbe_eq->iopoll); | |
5725 | } | |
6733b39a JK |
5726 | free_twq: |
5727 | beiscsi_clean_port(phba); | |
5728 | beiscsi_free_mem(phba); | |
5729 | free_port: | |
5730 | pci_free_consistent(phba->pcidev, | |
5731 | phba->ctrl.mbox_mem_alloced.size, | |
5732 | phba->ctrl.mbox_mem_alloced.va, | |
5733 | phba->ctrl.mbox_mem_alloced.dma); | |
5734 | beiscsi_unmap_pci_function(phba); | |
5735 | hba_free: | |
238f6b72 JK |
5736 | if (phba->msix_enabled) |
5737 | pci_disable_msix(phba->pcidev); | |
6733b39a JK |
5738 | iscsi_host_remove(phba->shost); |
5739 | pci_dev_put(phba->pcidev); | |
5740 | iscsi_host_free(phba->shost); | |
5741 | disable_pci: | |
5742 | pci_disable_device(pcidev); | |
5743 | return ret; | |
5744 | } | |
5745 | ||
3567f36a JK |
5746 | static struct pci_error_handlers beiscsi_eeh_handlers = { |
5747 | .error_detected = beiscsi_eeh_err_detected, | |
5748 | .slot_reset = beiscsi_eeh_reset, | |
5749 | .resume = beiscsi_eeh_resume, | |
5750 | }; | |
5751 | ||
6733b39a JK |
5752 | struct iscsi_transport beiscsi_iscsi_transport = { |
5753 | .owner = THIS_MODULE, | |
5754 | .name = DRV_NAME, | |
9db0fb3a | 5755 | .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO | |
6733b39a | 5756 | CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD, |
6733b39a JK |
5757 | .create_session = beiscsi_session_create, |
5758 | .destroy_session = beiscsi_session_destroy, | |
5759 | .create_conn = beiscsi_conn_create, | |
5760 | .bind_conn = beiscsi_conn_bind, | |
5761 | .destroy_conn = iscsi_conn_teardown, | |
3128c6c7 | 5762 | .attr_is_visible = be2iscsi_attr_is_visible, |
0e43895e MC |
5763 | .set_iface_param = be2iscsi_iface_set_param, |
5764 | .get_iface_param = be2iscsi_iface_get_param, | |
6733b39a | 5765 | .set_param = beiscsi_set_param, |
c7f7fd5b | 5766 | .get_conn_param = iscsi_conn_get_param, |
6733b39a JK |
5767 | .get_session_param = iscsi_session_get_param, |
5768 | .get_host_param = beiscsi_get_host_param, | |
5769 | .start_conn = beiscsi_conn_start, | |
fa95d206 | 5770 | .stop_conn = iscsi_conn_stop, |
6733b39a JK |
5771 | .send_pdu = iscsi_conn_send_pdu, |
5772 | .xmit_task = beiscsi_task_xmit, | |
5773 | .cleanup_task = beiscsi_cleanup_task, | |
5774 | .alloc_pdu = beiscsi_alloc_pdu, | |
5775 | .parse_pdu_itt = beiscsi_parse_pdu, | |
5776 | .get_stats = beiscsi_conn_get_stats, | |
c7f7fd5b | 5777 | .get_ep_param = beiscsi_ep_get_param, |
6733b39a JK |
5778 | .ep_connect = beiscsi_ep_connect, |
5779 | .ep_poll = beiscsi_ep_poll, | |
5780 | .ep_disconnect = beiscsi_ep_disconnect, | |
5781 | .session_recovery_timedout = iscsi_session_recovery_timedout, | |
ffce3e2e | 5782 | .bsg_request = beiscsi_bsg_request, |
6733b39a JK |
5783 | }; |
5784 | ||
5785 | static struct pci_driver beiscsi_pci_driver = { | |
5786 | .name = DRV_NAME, | |
5787 | .probe = beiscsi_dev_probe, | |
5788 | .remove = beiscsi_remove, | |
25602c97 | 5789 | .shutdown = beiscsi_shutdown, |
3567f36a JK |
5790 | .id_table = beiscsi_pci_id_table, |
5791 | .err_handler = &beiscsi_eeh_handlers | |
6733b39a JK |
5792 | }; |
5793 | ||
bfead3b2 | 5794 | |
6733b39a JK |
5795 | static int __init beiscsi_module_init(void) |
5796 | { | |
5797 | int ret; | |
5798 | ||
5799 | beiscsi_scsi_transport = | |
5800 | iscsi_register_transport(&beiscsi_iscsi_transport); | |
5801 | if (!beiscsi_scsi_transport) { | |
99bc5d55 JSJ |
5802 | printk(KERN_ERR |
5803 | "beiscsi_module_init - Unable to register beiscsi transport.\n"); | |
f55a24f2 | 5804 | return -ENOMEM; |
6733b39a | 5805 | } |
99bc5d55 JSJ |
5806 | printk(KERN_INFO "In beiscsi_module_init, tt=%p\n", |
5807 | &beiscsi_iscsi_transport); | |
6733b39a JK |
5808 | |
5809 | ret = pci_register_driver(&beiscsi_pci_driver); | |
5810 | if (ret) { | |
99bc5d55 JSJ |
5811 | printk(KERN_ERR |
5812 | "beiscsi_module_init - Unable to register beiscsi pci driver.\n"); | |
6733b39a JK |
5813 | goto unregister_iscsi_transport; |
5814 | } | |
5815 | return 0; | |
5816 | ||
5817 | unregister_iscsi_transport: | |
5818 | iscsi_unregister_transport(&beiscsi_iscsi_transport); | |
5819 | return ret; | |
5820 | } | |
5821 | ||
5822 | static void __exit beiscsi_module_exit(void) | |
5823 | { | |
5824 | pci_unregister_driver(&beiscsi_pci_driver); | |
5825 | iscsi_unregister_transport(&beiscsi_iscsi_transport); | |
5826 | } | |
5827 | ||
5828 | module_init(beiscsi_module_init); | |
5829 | module_exit(beiscsi_module_exit); |