projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
spi: imx: Add loopback mode support
[deliverable/linux.git] / drivers / spi / spi-imx.c
CommitLineData
b5f3294f
SH		 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation
17 * 51 Franklin Street, Fifth Floor
18 * Boston, MA 02110-1301, USA.
19 */
20
21#include <linux/clk.h>
22#include <linux/completion.h>
23#include <linux/delay.h>
f62caccd
RG		 24#include <linux/dmaengine.h>
25#include <linux/dma-mapping.h>
b5f3294f
SH		 26#include <linux/err.h>
27#include <linux/gpio.h>
b5f3294f
SH		 28#include <linux/interrupt.h>
29#include <linux/io.h>
30#include <linux/irq.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/platform_device.h>
5a0e3ad6 34#include <linux/slab.h>
b5f3294f
SH		 35#include <linux/spi/spi.h>
36#include <linux/spi/spi_bitbang.h>
37#include <linux/types.h>
22a85e4c
SG		 38#include <linux/of.h>
39#include <linux/of_device.h>
40#include <linux/of_gpio.h>
b5f3294f 41
f62caccd 42#include <linux/platform_data/dma-imx.h>
82906b13 43#include <linux/platform_data/spi-imx.h>
b5f3294f
SH		 44
45#define DRIVER_NAME "spi_imx"
46
47#define MXC_CSPIRXDATA 0x00
48#define MXC_CSPITXDATA 0x04
49#define MXC_CSPICTRL 0x08
50#define MXC_CSPIINT 0x0c
51#define MXC_RESET 0x1c
52
53/* generic defines to abstract from the different register layouts */
54#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
55#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
56
f62caccd
RG		 57/* The maximum bytes that a sdma BD can transfer.*/
58#define MAX_SDMA_BD_BYTES (1 << 15)
59#define IMX_DMA_TIMEOUT (msecs_to_jiffies(3000))
6cdeb002 60struct spi_imx_config {
b5f3294f
SH		 61 unsigned int speed_hz;
62 unsigned int bpw;
63 unsigned int mode;
3b2aa89e 64 u8 cs;
b5f3294f
SH		 65};
66
f4ba6315 67enum spi_imx_devtype {
04ee5854
SG		 68 IMX1_CSPI,
69 IMX21_CSPI,
70 IMX27_CSPI,
71 IMX31_CSPI,
72 IMX35_CSPI, /* CSPI on all i.mx except above */
73 IMX51_ECSPI, /* ECSPI on i.mx51 and later */
f4ba6315
UKK		 74};
75
76struct spi_imx_data;
77
78struct spi_imx_devtype_data {
79 void (*intctrl)(struct spi_imx_data *, int);
80 int (*config)(struct spi_imx_data *, struct spi_imx_config *);
81 void (*trigger)(struct spi_imx_data *);
82 int (*rx_available)(struct spi_imx_data *);
1723e66b 83 void (*reset)(struct spi_imx_data *);
04ee5854 84 enum spi_imx_devtype devtype;
f4ba6315
UKK		 85};
86
6cdeb002 87struct spi_imx_data {
b5f3294f
SH		 88 struct spi_bitbang bitbang;
89
90 struct completion xfer_done;
cc4d22ae 91 void __iomem *base;
aa29d840
SH		 92 struct clk *clk_per;
93 struct clk *clk_ipg;
b5f3294f 94 unsigned long spi_clk;
b5f3294f
SH		 95
96 unsigned int count;
6cdeb002
UKK		 97 void (*tx)(struct spi_imx_data *);
98 void (*rx)(struct spi_imx_data *);
b5f3294f
SH		 99 void *rx_buf;
100 const void *tx_buf;
101 unsigned int txfifo; /* number of words pushed in tx FIFO */
102
f62caccd
RG		 103 /* DMA */
104 unsigned int dma_is_inited;
105 unsigned int dma_finished;
106 bool usedma;
107 u32 rx_wml;
108 u32 tx_wml;
109 u32 rxt_wml;
110 struct completion dma_rx_completion;
111 struct completion dma_tx_completion;
112
80023cb3 113 const struct spi_imx_devtype_data *devtype_data;
c2387cb9 114 int chipselect[0];
b5f3294f
SH		 115};
116
04ee5854
SG		 117static inline int is_imx27_cspi(struct spi_imx_data *d)
118{
119 return d->devtype_data->devtype == IMX27_CSPI;
120}
121
122static inline int is_imx35_cspi(struct spi_imx_data *d)
123{
124 return d->devtype_data->devtype == IMX35_CSPI;
125}
126
127static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d)
128{
129 return (d->devtype_data->devtype == IMX51_ECSPI) ? 64 : 8;
130}
131
b5f3294f 132#define MXC_SPI_BUF_RX(type) \
6cdeb002 133static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
b5f3294f 134{ \
6cdeb002 135 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
b5f3294f 136 \
6cdeb002
UKK		 137 if (spi_imx->rx_buf) { \
138 *(type *)spi_imx->rx_buf = val; \
139 spi_imx->rx_buf += sizeof(type); \
b5f3294f
SH		 140 } \
141}
142
143#define MXC_SPI_BUF_TX(type) \
6cdeb002 144static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
b5f3294f
SH		 145{ \
146 type val = 0; \
147 \
6cdeb002
UKK		 148 if (spi_imx->tx_buf) { \
149 val = *(type *)spi_imx->tx_buf; \
150 spi_imx->tx_buf += sizeof(type); \
b5f3294f
SH		 151 } \
152 \
6cdeb002 153 spi_imx->count -= sizeof(type); \
b5f3294f 154 \
6cdeb002 155 writel(val, spi_imx->base + MXC_CSPITXDATA); \
b5f3294f
SH		 156}
157
158MXC_SPI_BUF_RX(u8)
159MXC_SPI_BUF_TX(u8)
160MXC_SPI_BUF_RX(u16)
161MXC_SPI_BUF_TX(u16)
162MXC_SPI_BUF_RX(u32)
163MXC_SPI_BUF_TX(u32)
164
165/* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
166 * (which is currently not the case in this driver)
167 */
168static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
169 256, 384, 512, 768, 1024};
170
171/* MX21, MX27 */
6cdeb002 172static unsigned int spi_imx_clkdiv_1(unsigned int fin,
04ee5854 173 unsigned int fspi, unsigned int max)
b5f3294f 174{
04ee5854 175 int i;
b5f3294f
SH		 176
177 for (i = 2; i < max; i++)
178 if (fspi * mxc_clkdivs[i] >= fin)
179 return i;
180
181 return max;
182}
183
0b599603 184/* MX1, MX31, MX35, MX51 CSPI */
6cdeb002 185static unsigned int spi_imx_clkdiv_2(unsigned int fin,
b5f3294f
SH		 186 unsigned int fspi)
187{
188 int i, div = 4;
189
190 for (i = 0; i < 7; i++) {
191 if (fspi * div >= fin)
192 return i;
193 div <<= 1;
194 }
195
196 return 7;
197}
198
f62caccd
RG		 199static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
200 struct spi_transfer *transfer)
201{
202 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
203
f6ee9b58
SH		 204 if (spi_imx->dma_is_inited
205 && transfer->len > spi_imx->rx_wml * sizeof(u32)
206 && transfer->len > spi_imx->tx_wml * sizeof(u32))
f62caccd
RG		 207 return true;
208 return false;
209}
210
66de757c
SG		 211#define MX51_ECSPI_CTRL 0x08
212#define MX51_ECSPI_CTRL_ENABLE (1 << 0)
213#define MX51_ECSPI_CTRL_XCH (1 << 2)
f62caccd 214#define MX51_ECSPI_CTRL_SMC (1 << 3)
66de757c
SG		 215#define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
216#define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
217#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
218#define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
219#define MX51_ECSPI_CTRL_BL_OFFSET 20
220
221#define MX51_ECSPI_CONFIG 0x0c
222#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
223#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
224#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
225#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
c09b890b 226#define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
66de757c
SG		 227
228#define MX51_ECSPI_INT 0x10
229#define MX51_ECSPI_INT_TEEN (1 << 0)
230#define MX51_ECSPI_INT_RREN (1 << 3)
231
f62caccd
RG		 232#define MX51_ECSPI_DMA 0x14
233#define MX51_ECSPI_DMA_TX_WML_OFFSET 0
234#define MX51_ECSPI_DMA_TX_WML_MASK 0x3F
235#define MX51_ECSPI_DMA_RX_WML_OFFSET 16
236#define MX51_ECSPI_DMA_RX_WML_MASK (0x3F << 16)
237#define MX51_ECSPI_DMA_RXT_WML_OFFSET 24
238#define MX51_ECSPI_DMA_RXT_WML_MASK (0x3F << 24)
239
240#define MX51_ECSPI_DMA_TEDEN_OFFSET 7
241#define MX51_ECSPI_DMA_RXDEN_OFFSET 23
242#define MX51_ECSPI_DMA_RXTDEN_OFFSET 31
243
66de757c
SG		 244#define MX51_ECSPI_STAT 0x18
245#define MX51_ECSPI_STAT_RR (1 << 3)
0b599603 246
9f6aa42b
FE		 247#define MX51_ECSPI_TESTREG 0x20
248#define MX51_ECSPI_TESTREG_LBC BIT(31)
249
0b599603 250/* MX51 eCSPI */
6fd8b850
MV		 251static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi,
252 unsigned int *fres)
0b599603
UKK		 253{
254 /*
255 * there are two 4-bit dividers, the pre-divider divides by
256 * $pre, the post-divider by 2^$post
257 */
258 unsigned int pre, post;
259
260 if (unlikely(fspi > fin))
261 return 0;
262
263 post = fls(fin) - fls(fspi);
264 if (fin > fspi << post)
265 post++;
266
267 /* now we have: (fin <= fspi << post) with post being minimal */
268
269 post = max(4U, post) - 4;
270 if (unlikely(post > 0xf)) {
271 pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
272 __func__, fspi, fin);
273 return 0xff;
274 }
275
276 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
277
278 pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
279 __func__, fin, fspi, post, pre);
6fd8b850
MV		 280
281 /* Resulting frequency for the SCLK line. */
282 *fres = (fin / (pre + 1)) >> post;
283
66de757c
SG		 284 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
285 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
0b599603
UKK		 286}
287
66de757c 288static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
0b599603
UKK		 289{
290 unsigned val = 0;
291
292 if (enable & MXC_INT_TE)
66de757c 293 val |= MX51_ECSPI_INT_TEEN;
0b599603
UKK		 294
295 if (enable & MXC_INT_RR)
66de757c 296 val |= MX51_ECSPI_INT_RREN;
0b599603 297
66de757c 298 writel(val, spi_imx->base + MX51_ECSPI_INT);
0b599603
UKK		 299}
300
66de757c 301static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
0b599603 302{
f62caccd
RG		 303 u32 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
304
305 if (!spi_imx->usedma)
306 reg |= MX51_ECSPI_CTRL_XCH;
307 else if (!spi_imx->dma_finished)
308 reg |= MX51_ECSPI_CTRL_SMC;
309 else
310 reg &= ~MX51_ECSPI_CTRL_SMC;
66de757c 311 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
0b599603
UKK		 312}
313
66de757c 314static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
0b599603
UKK		 315 struct spi_imx_config *config)
316{
f62caccd
RG		 317 u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0, dma = 0;
318 u32 tx_wml_cfg, rx_wml_cfg, rxt_wml_cfg;
9f6aa42b 319 u32 clk = config->speed_hz, delay, reg;
0b599603 320
f020c39e
SH		 321 /*
322 * The hardware seems to have a race condition when changing modes. The
323 * current assumption is that the selection of the channel arrives
324 * earlier in the hardware than the mode bits when they are written at
325 * the same time.
326 * So set master mode for all channels as we do not support slave mode.
327 */
66de757c 328 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
0b599603
UKK		 329
330 /* set clock speed */
6fd8b850 331 ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz, &clk);
0b599603
UKK		 332
333 /* set chip select to use */
66de757c 334 ctrl |= MX51_ECSPI_CTRL_CS(config->cs);
0b599603 335
66de757c 336 ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
0b599603 337
66de757c 338 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs);
0b599603
UKK		 339
340 if (config->mode & SPI_CPHA)
66de757c 341 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
1476253c
AK		 342 else
343 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
0b599603 344
c09b890b 345 if (config->mode & SPI_CPOL) {
66de757c 346 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
c09b890b 347 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
1476253c
AK		 348 } else {
349 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
350 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
c09b890b 351 }
0b599603 352 if (config->mode & SPI_CS_HIGH)
66de757c 353 cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
1476253c
AK		 354 else
355 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(config->cs);
0b599603 356
9f6aa42b
FE		 357 reg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
358 if (config->mode & SPI_LOOP)
359 reg |= MX51_ECSPI_TESTREG_LBC;
360 else
361 reg &= ~MX51_ECSPI_TESTREG_LBC;
362 writel(reg, spi_imx->base + MX51_ECSPI_TESTREG);
363
66de757c
SG		 364 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
365 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
0b599603 366
6fd8b850
MV		 367 /*
368 * Wait until the changes in the configuration register CONFIGREG
369 * propagate into the hardware. It takes exactly one tick of the
370 * SCLK clock, but we will wait two SCLK clock just to be sure. The
371 * effect of the delay it takes for the hardware to apply changes
372 * is noticable if the SCLK clock run very slow. In such a case, if
373 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
374 * be asserted before the SCLK polarity changes, which would disrupt
375 * the SPI communication as the device on the other end would consider
376 * the change of SCLK polarity as a clock tick already.
377 */
378 delay = (2 * 1000000) / clk;
379 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
380 udelay(delay);
381 else /* SCLK is _very_ slow */
382 usleep_range(delay, delay + 10);
383
f62caccd
RG		 384 /*
385 * Configure the DMA register: setup the watermark
386 * and enable DMA request.
387 */
388 if (spi_imx->dma_is_inited) {
389 dma = readl(spi_imx->base + MX51_ECSPI_DMA);
390
f62caccd
RG		 391 spi_imx->rxt_wml = spi_imx_get_fifosize(spi_imx) / 2;
392 rx_wml_cfg = spi_imx->rx_wml << MX51_ECSPI_DMA_RX_WML_OFFSET;
393 tx_wml_cfg = spi_imx->tx_wml << MX51_ECSPI_DMA_TX_WML_OFFSET;
394 rxt_wml_cfg = spi_imx->rxt_wml << MX51_ECSPI_DMA_RXT_WML_OFFSET;
395 dma = (dma & ~MX51_ECSPI_DMA_TX_WML_MASK
396 & ~MX51_ECSPI_DMA_RX_WML_MASK
397 & ~MX51_ECSPI_DMA_RXT_WML_MASK)
398 | rx_wml_cfg | tx_wml_cfg | rxt_wml_cfg
399 |(1 << MX51_ECSPI_DMA_TEDEN_OFFSET)
400 |(1 << MX51_ECSPI_DMA_RXDEN_OFFSET)
401 |(1 << MX51_ECSPI_DMA_RXTDEN_OFFSET);
402
403 writel(dma, spi_imx->base + MX51_ECSPI_DMA);
404 }
405
0b599603
UKK		 406 return 0;
407}
408
66de757c 409static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
0b599603 410{
66de757c 411 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
0b599603
UKK		 412}
413
66de757c 414static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx)
0b599603
UKK		 415{
416 /* drain receive buffer */
66de757c 417 while (mx51_ecspi_rx_available(spi_imx))
0b599603
UKK		 418 readl(spi_imx->base + MXC_CSPIRXDATA);
419}
420
b5f3294f
SH		 421#define MX31_INTREG_TEEN (1 << 0)
422#define MX31_INTREG_RREN (1 << 3)
423
424#define MX31_CSPICTRL_ENABLE (1 << 0)
425#define MX31_CSPICTRL_MASTER (1 << 1)
426#define MX31_CSPICTRL_XCH (1 << 2)
427#define MX31_CSPICTRL_POL (1 << 4)
428#define MX31_CSPICTRL_PHA (1 << 5)
429#define MX31_CSPICTRL_SSCTL (1 << 6)
430#define MX31_CSPICTRL_SSPOL (1 << 7)
431#define MX31_CSPICTRL_BC_SHIFT 8
432#define MX35_CSPICTRL_BL_SHIFT 20
433#define MX31_CSPICTRL_CS_SHIFT 24
434#define MX35_CSPICTRL_CS_SHIFT 12
435#define MX31_CSPICTRL_DR_SHIFT 16
436
437#define MX31_CSPISTATUS 0x14
438#define MX31_STATUS_RR (1 << 3)
439
440/* These functions also work for the i.MX35, but be aware that
441 * the i.MX35 has a slightly different register layout for bits
442 * we do not use here.
443 */
f4ba6315 444static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
b5f3294f
SH		 445{
446 unsigned int val = 0;
447
448 if (enable & MXC_INT_TE)
449 val |= MX31_INTREG_TEEN;
450 if (enable & MXC_INT_RR)
451 val |= MX31_INTREG_RREN;
452
6cdeb002 453 writel(val, spi_imx->base + MXC_CSPIINT);
b5f3294f
SH		 454}
455
f4ba6315 456static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
b5f3294f
SH		 457{
458 unsigned int reg;
459
6cdeb002 460 reg = readl(spi_imx->base + MXC_CSPICTRL);
b5f3294f 461 reg |= MX31_CSPICTRL_XCH;
6cdeb002 462 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 463}
464
2a64a90a 465static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
1723e66b
UKK		 466 struct spi_imx_config *config)
467{
468 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
3b2aa89e 469 int cs = spi_imx->chipselect[config->cs];
1723e66b
UKK		 470
471 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
472 MX31_CSPICTRL_DR_SHIFT;
473
04ee5854 474 if (is_imx35_cspi(spi_imx)) {
2a64a90a
SG		 475 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
476 reg |= MX31_CSPICTRL_SSCTL;
477 } else {
478 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
479 }
1723e66b
UKK		 480
481 if (config->mode & SPI_CPHA)
482 reg |= MX31_CSPICTRL_PHA;
483 if (config->mode & SPI_CPOL)
484 reg |= MX31_CSPICTRL_POL;
485 if (config->mode & SPI_CS_HIGH)
486 reg |= MX31_CSPICTRL_SSPOL;
3b2aa89e 487 if (cs < 0)
2a64a90a 488 reg |= (cs + 32) <<
04ee5854
SG		 489 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
490 MX31_CSPICTRL_CS_SHIFT);
1723e66b
UKK		 491
492 writel(reg, spi_imx->base + MXC_CSPICTRL);
493
494 return 0;
495}
496
f4ba6315 497static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
b5f3294f 498{
6cdeb002 499 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
b5f3294f
SH		 500}
501
2a64a90a 502static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx)
1723e66b
UKK		 503{
504 /* drain receive buffer */
2a64a90a 505 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
1723e66b
UKK		 506 readl(spi_imx->base + MXC_CSPIRXDATA);
507}
508
3451fb15
SG		 509#define MX21_INTREG_RR (1 << 4)
510#define MX21_INTREG_TEEN (1 << 9)
511#define MX21_INTREG_RREN (1 << 13)
512
513#define MX21_CSPICTRL_POL (1 << 5)
514#define MX21_CSPICTRL_PHA (1 << 6)
515#define MX21_CSPICTRL_SSPOL (1 << 8)
516#define MX21_CSPICTRL_XCH (1 << 9)
517#define MX21_CSPICTRL_ENABLE (1 << 10)
518#define MX21_CSPICTRL_MASTER (1 << 11)
519#define MX21_CSPICTRL_DR_SHIFT 14
520#define MX21_CSPICTRL_CS_SHIFT 19
521
522static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
b5f3294f
SH		 523{
524 unsigned int val = 0;
525
526 if (enable & MXC_INT_TE)
3451fb15 527 val |= MX21_INTREG_TEEN;
b5f3294f 528 if (enable & MXC_INT_RR)
3451fb15 529 val |= MX21_INTREG_RREN;
b5f3294f 530
6cdeb002 531 writel(val, spi_imx->base + MXC_CSPIINT);
b5f3294f
SH		 532}
533
3451fb15 534static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
b5f3294f
SH		 535{
536 unsigned int reg;
537
6cdeb002 538 reg = readl(spi_imx->base + MXC_CSPICTRL);
3451fb15 539 reg |= MX21_CSPICTRL_XCH;
6cdeb002 540 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 541}
542
3451fb15 543static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx,
6cdeb002 544 struct spi_imx_config *config)
b5f3294f 545{
3451fb15 546 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
3b2aa89e 547 int cs = spi_imx->chipselect[config->cs];
04ee5854 548 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
b5f3294f 549
04ee5854 550 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) <<
3451fb15 551 MX21_CSPICTRL_DR_SHIFT;
b5f3294f
SH		 552 reg |= config->bpw - 1;
553
554 if (config->mode & SPI_CPHA)
3451fb15 555 reg |= MX21_CSPICTRL_PHA;
b5f3294f 556 if (config->mode & SPI_CPOL)
3451fb15 557 reg |= MX21_CSPICTRL_POL;
b5f3294f 558 if (config->mode & SPI_CS_HIGH)
3451fb15 559 reg |= MX21_CSPICTRL_SSPOL;
3b2aa89e 560 if (cs < 0)
3451fb15 561 reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT;
b5f3294f 562
6cdeb002 563 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 564
565 return 0;
566}
567
3451fb15 568static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx)
b5f3294f 569{
3451fb15 570 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
b5f3294f
SH		 571}
572
3451fb15 573static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx)
1723e66b
UKK		 574{
575 writel(1, spi_imx->base + MXC_RESET);
576}
577
b5f3294f
SH		 578#define MX1_INTREG_RR (1 << 3)
579#define MX1_INTREG_TEEN (1 << 8)
580#define MX1_INTREG_RREN (1 << 11)
581
582#define MX1_CSPICTRL_POL (1 << 4)
583#define MX1_CSPICTRL_PHA (1 << 5)
584#define MX1_CSPICTRL_XCH (1 << 8)
585#define MX1_CSPICTRL_ENABLE (1 << 9)
586#define MX1_CSPICTRL_MASTER (1 << 10)
587#define MX1_CSPICTRL_DR_SHIFT 13
588
f4ba6315 589static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
b5f3294f
SH		 590{
591 unsigned int val = 0;
592
593 if (enable & MXC_INT_TE)
594 val |= MX1_INTREG_TEEN;
595 if (enable & MXC_INT_RR)
596 val |= MX1_INTREG_RREN;
597
6cdeb002 598 writel(val, spi_imx->base + MXC_CSPIINT);
b5f3294f
SH		 599}
600
f4ba6315 601static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
b5f3294f
SH		 602{
603 unsigned int reg;
604
6cdeb002 605 reg = readl(spi_imx->base + MXC_CSPICTRL);
b5f3294f 606 reg |= MX1_CSPICTRL_XCH;
6cdeb002 607 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 608}
609
f4ba6315 610static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
6cdeb002 611 struct spi_imx_config *config)
b5f3294f
SH		 612{
613 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
614
6cdeb002 615 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
b5f3294f
SH		 616 MX1_CSPICTRL_DR_SHIFT;
617 reg |= config->bpw - 1;
618
619 if (config->mode & SPI_CPHA)
620 reg |= MX1_CSPICTRL_PHA;
621 if (config->mode & SPI_CPOL)
622 reg |= MX1_CSPICTRL_POL;
623
6cdeb002 624 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 625
626 return 0;
627}
628
f4ba6315 629static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
b5f3294f 630{
6cdeb002 631 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
b5f3294f
SH		 632}
633
1723e66b
UKK		 634static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
635{
636 writel(1, spi_imx->base + MXC_RESET);
637}
638
04ee5854
SG		 639static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
640 .intctrl = mx1_intctrl,
641 .config = mx1_config,
642 .trigger = mx1_trigger,
643 .rx_available = mx1_rx_available,
644 .reset = mx1_reset,
645 .devtype = IMX1_CSPI,
646};
647
648static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
649 .intctrl = mx21_intctrl,
650 .config = mx21_config,
651 .trigger = mx21_trigger,
652 .rx_available = mx21_rx_available,
653 .reset = mx21_reset,
654 .devtype = IMX21_CSPI,
655};
656
657static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
658 /* i.mx27 cspi shares the functions with i.mx21 one */
659 .intctrl = mx21_intctrl,
660 .config = mx21_config,
661 .trigger = mx21_trigger,
662 .rx_available = mx21_rx_available,
663 .reset = mx21_reset,
664 .devtype = IMX27_CSPI,
665};
666
667static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
668 .intctrl = mx31_intctrl,
669 .config = mx31_config,
670 .trigger = mx31_trigger,
671 .rx_available = mx31_rx_available,
672 .reset = mx31_reset,
673 .devtype = IMX31_CSPI,
674};
675
676static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
677 /* i.mx35 and later cspi shares the functions with i.mx31 one */
678 .intctrl = mx31_intctrl,
679 .config = mx31_config,
680 .trigger = mx31_trigger,
681 .rx_available = mx31_rx_available,
682 .reset = mx31_reset,
683 .devtype = IMX35_CSPI,
684};
685
686static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
687 .intctrl = mx51_ecspi_intctrl,
688 .config = mx51_ecspi_config,
689 .trigger = mx51_ecspi_trigger,
690 .rx_available = mx51_ecspi_rx_available,
691 .reset = mx51_ecspi_reset,
692 .devtype = IMX51_ECSPI,
693};
694
db1b8200 695static const struct platform_device_id spi_imx_devtype[] = {
04ee5854
SG		 696 {
697 .name = "imx1-cspi",
698 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
699 }, {
700 .name = "imx21-cspi",
701 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
702 }, {
703 .name = "imx27-cspi",
704 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
705 }, {
706 .name = "imx31-cspi",
707 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
708 }, {
709 .name = "imx35-cspi",
710 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
711 }, {
712 .name = "imx51-ecspi",
713 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
714 }, {
715 /* sentinel */
716 }
f4ba6315
UKK		 717};
718
22a85e4c
SG		 719static const struct of_device_id spi_imx_dt_ids[] = {
720 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
721 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
722 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
723 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
724 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
725 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
726 { /* sentinel */ }
727};
27743e0b 728MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
22a85e4c 729
6cdeb002 730static void spi_imx_chipselect(struct spi_device *spi, int is_active)
b5f3294f 731{
6cdeb002 732 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
6cdeb002 733 int gpio = spi_imx->chipselect[spi->chip_select];
e6a0a8bf
UKK		 734 int active = is_active != BITBANG_CS_INACTIVE;
735 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
b5f3294f 736
8b17e055 737 if (!gpio_is_valid(gpio))
b5f3294f 738 return;
b5f3294f 739
e6a0a8bf 740 gpio_set_value(gpio, dev_is_lowactive ^ active);
b5f3294f
SH		 741}
742
6cdeb002 743static void spi_imx_push(struct spi_imx_data *spi_imx)
b5f3294f 744{
04ee5854 745 while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) {
6cdeb002 746 if (!spi_imx->count)
b5f3294f 747 break;
6cdeb002
UKK		 748 spi_imx->tx(spi_imx);
749 spi_imx->txfifo++;
b5f3294f
SH		 750 }
751
edd501bb 752 spi_imx->devtype_data->trigger(spi_imx);
b5f3294f
SH		 753}
754
6cdeb002 755static irqreturn_t spi_imx_isr(int irq, void *dev_id)
b5f3294f 756{
6cdeb002 757 struct spi_imx_data *spi_imx = dev_id;
b5f3294f 758
edd501bb 759 while (spi_imx->devtype_data->rx_available(spi_imx)) {
6cdeb002
UKK		 760 spi_imx->rx(spi_imx);
761 spi_imx->txfifo--;
b5f3294f
SH		 762 }
763
6cdeb002
UKK		 764 if (spi_imx->count) {
765 spi_imx_push(spi_imx);
b5f3294f
SH		 766 return IRQ_HANDLED;
767 }
768
6cdeb002 769 if (spi_imx->txfifo) {
b5f3294f
SH		 770 /* No data left to push, but still waiting for rx data,
771 * enable receive data available interrupt.
772 */
edd501bb 773 spi_imx->devtype_data->intctrl(
f4ba6315 774 spi_imx, MXC_INT_RR);
b5f3294f
SH		 775 return IRQ_HANDLED;
776 }
777
edd501bb 778 spi_imx->devtype_data->intctrl(spi_imx, 0);
6cdeb002 779 complete(&spi_imx->xfer_done);
b5f3294f
SH		 780
781 return IRQ_HANDLED;
782}
783
6cdeb002 784static int spi_imx_setupxfer(struct spi_device *spi,
b5f3294f
SH		 785 struct spi_transfer *t)
786{
6cdeb002
UKK		 787 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
788 struct spi_imx_config config;
b5f3294f
SH		 789
790 config.bpw = t ? t->bits_per_word : spi->bits_per_word;
791 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
792 config.mode = spi->mode;
3b2aa89e 793 config.cs = spi->chip_select;
b5f3294f 794
462d26b5
SH		 795 if (!config.speed_hz)
796 config.speed_hz = spi->max_speed_hz;
797 if (!config.bpw)
798 config.bpw = spi->bits_per_word;
462d26b5 799
e6a0a8bf
UKK		 800 /* Initialize the functions for transfer */
801 if (config.bpw <= 8) {
802 spi_imx->rx = spi_imx_buf_rx_u8;
803 spi_imx->tx = spi_imx_buf_tx_u8;
804 } else if (config.bpw <= 16) {
805 spi_imx->rx = spi_imx_buf_rx_u16;
806 spi_imx->tx = spi_imx_buf_tx_u16;
6051426f 807 } else {
e6a0a8bf
UKK		 808 spi_imx->rx = spi_imx_buf_rx_u32;
809 spi_imx->tx = spi_imx_buf_tx_u32;
24778be2 810 }
e6a0a8bf 811
edd501bb 812 spi_imx->devtype_data->config(spi_imx, &config);
b5f3294f
SH		 813
814 return 0;
815}
816
f62caccd
RG		 817static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
818{
819 struct spi_master *master = spi_imx->bitbang.master;
820
821 if (master->dma_rx) {
822 dma_release_channel(master->dma_rx);
823 master->dma_rx = NULL;
824 }
825
826 if (master->dma_tx) {
827 dma_release_channel(master->dma_tx);
828 master->dma_tx = NULL;
829 }
830
831 spi_imx->dma_is_inited = 0;
832}
833
834static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
835 struct spi_master *master,
836 const struct resource *res)
837{
838 struct dma_slave_config slave_config = {};
839 int ret;
840
a02bb401
RG		 841 /* use pio mode for i.mx6dl chip TKT238285 */
842 if (of_machine_is_compatible("fsl,imx6dl"))
843 return 0;
844
f62caccd
RG		 845 /* Prepare for TX DMA: */
846 master->dma_tx = dma_request_slave_channel(dev, "tx");
847 if (!master->dma_tx) {
848 dev_err(dev, "cannot get the TX DMA channel!\n");
849 ret = -EINVAL;
850 goto err;
851 }
852
853 slave_config.direction = DMA_MEM_TO_DEV;
854 slave_config.dst_addr = res->start + MXC_CSPITXDATA;
855 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
856 slave_config.dst_maxburst = spi_imx_get_fifosize(spi_imx) / 2;
857 ret = dmaengine_slave_config(master->dma_tx, &slave_config);
858 if (ret) {
859 dev_err(dev, "error in TX dma configuration.\n");
860 goto err;
861 }
862
863 /* Prepare for RX : */
864 master->dma_rx = dma_request_slave_channel(dev, "rx");
865 if (!master->dma_rx) {
866 dev_dbg(dev, "cannot get the DMA channel.\n");
867 ret = -EINVAL;
868 goto err;
869 }
870
871 slave_config.direction = DMA_DEV_TO_MEM;
872 slave_config.src_addr = res->start + MXC_CSPIRXDATA;
873 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
874 slave_config.src_maxburst = spi_imx_get_fifosize(spi_imx) / 2;
875 ret = dmaengine_slave_config(master->dma_rx, &slave_config);
876 if (ret) {
877 dev_err(dev, "error in RX dma configuration.\n");
878 goto err;
879 }
880
881 init_completion(&spi_imx->dma_rx_completion);
882 init_completion(&spi_imx->dma_tx_completion);
883 master->can_dma = spi_imx_can_dma;
884 master->max_dma_len = MAX_SDMA_BD_BYTES;
885 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
886 SPI_MASTER_MUST_TX;
f511ab09
LS		 887 spi_imx->tx_wml = spi_imx_get_fifosize(spi_imx) / 2;
888 spi_imx->rx_wml = spi_imx_get_fifosize(spi_imx) / 2;
f62caccd
RG		 889 spi_imx->dma_is_inited = 1;
890
891 return 0;
892err:
893 spi_imx_sdma_exit(spi_imx);
894 return ret;
895}
896
897static void spi_imx_dma_rx_callback(void *cookie)
898{
899 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
900
901 complete(&spi_imx->dma_rx_completion);
902}
903
904static void spi_imx_dma_tx_callback(void *cookie)
905{
906 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
907
908 complete(&spi_imx->dma_tx_completion);
909}
910
911static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
912 struct spi_transfer *transfer)
913{
914 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
915 int ret;
56536a7f 916 unsigned long timeout;
f62caccd
RG		 917 u32 dma;
918 int left;
919 struct spi_master *master = spi_imx->bitbang.master;
920 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
921
922 if (tx) {
923 desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
e8361f70 924 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
f62caccd
RG		 925 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
926 if (!desc_tx)
927 goto no_dma;
928
929 desc_tx->callback = spi_imx_dma_tx_callback;
930 desc_tx->callback_param = (void *)spi_imx;
931 dmaengine_submit(desc_tx);
932 }
933
934 if (rx) {
935 desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
e8361f70 936 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
f62caccd
RG		 937 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
938 if (!desc_rx)
939 goto no_dma;
940
941 desc_rx->callback = spi_imx_dma_rx_callback;
942 desc_rx->callback_param = (void *)spi_imx;
943 dmaengine_submit(desc_rx);
944 }
945
946 reinit_completion(&spi_imx->dma_rx_completion);
947 reinit_completion(&spi_imx->dma_tx_completion);
948
949 /* Trigger the cspi module. */
950 spi_imx->dma_finished = 0;
951
952 dma = readl(spi_imx->base + MX51_ECSPI_DMA);
953 dma = dma & (~MX51_ECSPI_DMA_RXT_WML_MASK);
954 /* Change RX_DMA_LENGTH trigger dma fetch tail data */
955 left = transfer->len % spi_imx->rxt_wml;
956 if (left)
957 writel(dma | (left << MX51_ECSPI_DMA_RXT_WML_OFFSET),
958 spi_imx->base + MX51_ECSPI_DMA);
959 spi_imx->devtype_data->trigger(spi_imx);
960
961 dma_async_issue_pending(master->dma_tx);
962 dma_async_issue_pending(master->dma_rx);
963 /* Wait SDMA to finish the data transfer.*/
56536a7f 964 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
f62caccd 965 IMX_DMA_TIMEOUT);
56536a7f 966 if (!timeout) {
f62caccd
RG		 967 pr_warn("%s %s: I/O Error in DMA TX\n",
968 dev_driver_string(&master->dev),
969 dev_name(&master->dev));
970 dmaengine_terminate_all(master->dma_tx);
971 } else {
56536a7f
NMG		 972 timeout = wait_for_completion_timeout(
973 &spi_imx->dma_rx_completion, IMX_DMA_TIMEOUT);
974 if (!timeout) {
f62caccd
RG		 975 pr_warn("%s %s: I/O Error in DMA RX\n",
976 dev_driver_string(&master->dev),
977 dev_name(&master->dev));
978 spi_imx->devtype_data->reset(spi_imx);
979 dmaengine_terminate_all(master->dma_rx);
980 }
981 writel(dma |
982 spi_imx->rxt_wml << MX51_ECSPI_DMA_RXT_WML_OFFSET,
983 spi_imx->base + MX51_ECSPI_DMA);
984 }
985
986 spi_imx->dma_finished = 1;
987 spi_imx->devtype_data->trigger(spi_imx);
988
56536a7f 989 if (!timeout)
f62caccd 990 ret = -ETIMEDOUT;
56536a7f 991 else
f62caccd
RG		 992 ret = transfer->len;
993
994 return ret;
995
996no_dma:
997 pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
998 dev_driver_string(&master->dev),
999 dev_name(&master->dev));
1000 return -EAGAIN;
1001}
1002
1003static int spi_imx_pio_transfer(struct spi_device *spi,
b5f3294f
SH		 1004 struct spi_transfer *transfer)
1005{
6cdeb002 1006 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
b5f3294f 1007
6cdeb002
UKK		 1008 spi_imx->tx_buf = transfer->tx_buf;
1009 spi_imx->rx_buf = transfer->rx_buf;
1010 spi_imx->count = transfer->len;
1011 spi_imx->txfifo = 0;
b5f3294f 1012
aa0fe826 1013 reinit_completion(&spi_imx->xfer_done);
b5f3294f 1014
6cdeb002 1015 spi_imx_push(spi_imx);
b5f3294f 1016
edd501bb 1017 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
b5f3294f 1018
6cdeb002 1019 wait_for_completion(&spi_imx->xfer_done);
b5f3294f
SH		 1020
1021 return transfer->len;
1022}
1023
f62caccd
RG		 1024static int spi_imx_transfer(struct spi_device *spi,
1025 struct spi_transfer *transfer)
1026{
1027 int ret;
1028 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1029
1030 if (spi_imx->bitbang.master->can_dma &&
1031 spi_imx_can_dma(spi_imx->bitbang.master, spi, transfer)) {
1032 spi_imx->usedma = true;
1033 ret = spi_imx_dma_transfer(spi_imx, transfer);
1034 if (ret != -EAGAIN)
1035 return ret;
1036 }
1037 spi_imx->usedma = false;
1038
1039 return spi_imx_pio_transfer(spi, transfer);
1040}
1041
6cdeb002 1042static int spi_imx_setup(struct spi_device *spi)
b5f3294f 1043{
6c23e5d4
SH		 1044 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1045 int gpio = spi_imx->chipselect[spi->chip_select];
1046
f4d4ecfe 1047 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
b5f3294f
SH		 1048 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1049
8b17e055 1050 if (gpio_is_valid(gpio))
6c23e5d4
SH		 1051 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
1052
6cdeb002 1053 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
b5f3294f
SH		 1054
1055 return 0;
1056}
1057
6cdeb002 1058static void spi_imx_cleanup(struct spi_device *spi)
b5f3294f
SH		 1059{
1060}
1061
9e556dcc
HS		 1062static int
1063spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1064{
1065 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1066 int ret;
1067
1068 ret = clk_enable(spi_imx->clk_per);
1069 if (ret)
1070 return ret;
1071
1072 ret = clk_enable(spi_imx->clk_ipg);
1073 if (ret) {
1074 clk_disable(spi_imx->clk_per);
1075 return ret;
1076 }
1077
1078 return 0;
1079}
1080
1081static int
1082spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1083{
1084 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1085
1086 clk_disable(spi_imx->clk_ipg);
1087 clk_disable(spi_imx->clk_per);
1088 return 0;
1089}
1090
fd4a319b 1091static int spi_imx_probe(struct platform_device *pdev)
b5f3294f 1092{
22a85e4c
SG		 1093 struct device_node *np = pdev->dev.of_node;
1094 const struct of_device_id *of_id =
1095 of_match_device(spi_imx_dt_ids, &pdev->dev);
1096 struct spi_imx_master *mxc_platform_info =
1097 dev_get_platdata(&pdev->dev);
b5f3294f 1098 struct spi_master *master;
6cdeb002 1099 struct spi_imx_data *spi_imx;
b5f3294f 1100 struct resource *res;
4b5d6aad 1101 int i, ret, num_cs, irq;
b5f3294f 1102
22a85e4c 1103 if (!np && !mxc_platform_info) {
b5f3294f
SH		 1104 dev_err(&pdev->dev, "can't get the platform data\n");
1105 return -EINVAL;
1106 }
1107
22a85e4c 1108 ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs);
39ec0d38
LW		 1109 if (ret < 0) {
1110 if (mxc_platform_info)
1111 num_cs = mxc_platform_info->num_chipselect;
1112 else
1113 return ret;
1114 }
22a85e4c 1115
c2387cb9
SG		 1116 master = spi_alloc_master(&pdev->dev,
1117 sizeof(struct spi_imx_data) + sizeof(int) * num_cs);
b5f3294f
SH		 1118 if (!master)
1119 return -ENOMEM;
1120
1121 platform_set_drvdata(pdev, master);
1122
24778be2 1123 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
b5f3294f 1124 master->bus_num = pdev->id;
c2387cb9 1125 master->num_chipselect = num_cs;
b5f3294f 1126
6cdeb002 1127 spi_imx = spi_master_get_devdata(master);
94c69f76 1128 spi_imx->bitbang.master = master;
b5f3294f
SH		 1129
1130 for (i = 0; i < master->num_chipselect; i++) {
22a85e4c 1131 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
8b17e055 1132 if (!gpio_is_valid(cs_gpio) && mxc_platform_info)
22a85e4c 1133 cs_gpio = mxc_platform_info->chipselect[i];
4cc122ac
FE		 1134
1135 spi_imx->chipselect[i] = cs_gpio;
8b17e055 1136 if (!gpio_is_valid(cs_gpio))
b5f3294f 1137 continue;
4cc122ac 1138
130b82c0
FE		 1139 ret = devm_gpio_request(&pdev->dev, spi_imx->chipselect[i],
1140 DRIVER_NAME);
b5f3294f 1141 if (ret) {
bbd050af 1142 dev_err(&pdev->dev, "can't get cs gpios\n");
130b82c0 1143 goto out_master_put;
b5f3294f 1144 }
b5f3294f
SH		 1145 }
1146
6cdeb002
UKK		 1147 spi_imx->bitbang.chipselect = spi_imx_chipselect;
1148 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1149 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1150 spi_imx->bitbang.master->setup = spi_imx_setup;
1151 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
9e556dcc
HS		 1152 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1153 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
9f6aa42b
FE		 1154 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
1155 SPI_LOOP;
b5f3294f 1156
6cdeb002 1157 init_completion(&spi_imx->xfer_done);
b5f3294f 1158
22a85e4c 1159 spi_imx->devtype_data = of_id ? of_id->data :
04ee5854 1160 (struct spi_imx_devtype_data *) pdev->id_entry->driver_data;
f4ba6315 1161
b5f3294f 1162 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
130b82c0
FE		 1163 spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1164 if (IS_ERR(spi_imx->base)) {
1165 ret = PTR_ERR(spi_imx->base);
1166 goto out_master_put;
b5f3294f
SH		 1167 }
1168
4b5d6aad
FE		 1169 irq = platform_get_irq(pdev, 0);
1170 if (irq < 0) {
1171 ret = irq;
130b82c0 1172 goto out_master_put;
b5f3294f
SH		 1173 }
1174
4b5d6aad 1175 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
8fc39b51 1176 dev_name(&pdev->dev), spi_imx);
b5f3294f 1177 if (ret) {
4b5d6aad 1178 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
130b82c0 1179 goto out_master_put;
b5f3294f
SH		 1180 }
1181
aa29d840
SH		 1182 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1183 if (IS_ERR(spi_imx->clk_ipg)) {
1184 ret = PTR_ERR(spi_imx->clk_ipg);
130b82c0 1185 goto out_master_put;
b5f3294f
SH		 1186 }
1187
aa29d840
SH		 1188 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1189 if (IS_ERR(spi_imx->clk_per)) {
1190 ret = PTR_ERR(spi_imx->clk_per);
130b82c0 1191 goto out_master_put;
aa29d840
SH		 1192 }
1193
83174626
FE		 1194 ret = clk_prepare_enable(spi_imx->clk_per);
1195 if (ret)
1196 goto out_master_put;
1197
1198 ret = clk_prepare_enable(spi_imx->clk_ipg);
1199 if (ret)
1200 goto out_put_per;
aa29d840
SH		 1201
1202 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
f62caccd
RG		 1203 /*
1204 * Only validated on i.mx6 now, can remove the constrain if validated on
1205 * other chips.
1206 */
1207 if (spi_imx->devtype_data == &imx51_ecspi_devtype_data
1208 && spi_imx_sdma_init(&pdev->dev, spi_imx, master, res))
1209 dev_err(&pdev->dev, "dma setup error,use pio instead\n");
b5f3294f 1210
edd501bb 1211 spi_imx->devtype_data->reset(spi_imx);
ce1807b2 1212
edd501bb 1213 spi_imx->devtype_data->intctrl(spi_imx, 0);
b5f3294f 1214
22a85e4c 1215 master->dev.of_node = pdev->dev.of_node;
6cdeb002 1216 ret = spi_bitbang_start(&spi_imx->bitbang);
b5f3294f
SH		 1217 if (ret) {
1218 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
1219 goto out_clk_put;
1220 }
1221
1222 dev_info(&pdev->dev, "probed\n");
1223
9e556dcc
HS		 1224 clk_disable(spi_imx->clk_ipg);
1225 clk_disable(spi_imx->clk_per);
b5f3294f
SH		 1226 return ret;
1227
1228out_clk_put:
aa29d840 1229 clk_disable_unprepare(spi_imx->clk_ipg);
83174626
FE		 1230out_put_per:
1231 clk_disable_unprepare(spi_imx->clk_per);
130b82c0 1232out_master_put:
b5f3294f 1233 spi_master_put(master);
130b82c0 1234
b5f3294f
SH		 1235 return ret;
1236}
1237
fd4a319b 1238static int spi_imx_remove(struct platform_device *pdev)
b5f3294f
SH		 1239{
1240 struct spi_master *master = platform_get_drvdata(pdev);
6cdeb002 1241 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
b5f3294f 1242
6cdeb002 1243 spi_bitbang_stop(&spi_imx->bitbang);
b5f3294f 1244
6cdeb002 1245 writel(0, spi_imx->base + MXC_CSPICTRL);
fd40dccb
PDM		 1246 clk_unprepare(spi_imx->clk_ipg);
1247 clk_unprepare(spi_imx->clk_per);
f62caccd 1248 spi_imx_sdma_exit(spi_imx);
b5f3294f
SH		 1249 spi_master_put(master);
1250
b5f3294f
SH		 1251 return 0;
1252}
1253
6cdeb002 1254static struct platform_driver spi_imx_driver = {
b5f3294f
SH		 1255 .driver = {
1256 .name = DRIVER_NAME,
22a85e4c 1257 .of_match_table = spi_imx_dt_ids,
b5f3294f 1258 },
f4ba6315 1259 .id_table = spi_imx_devtype,
6cdeb002 1260 .probe = spi_imx_probe,
fd4a319b 1261 .remove = spi_imx_remove,
b5f3294f 1262};
940ab889 1263module_platform_driver(spi_imx_driver);
b5f3294f
SH		 1264
1265MODULE_DESCRIPTION("SPI Master Controller driver");
1266MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1267MODULE_LICENSE("GPL");
3133fba3 1268MODULE_ALIAS("platform:" DRIVER_NAME);
Linux kernel - Deliverables
This page took 0.403171 seconds and 5 git commands to generate.