Commit | Line | Data |
---|---|---|
b5f3294f SH |
1 | /* |
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * Copyright (C) 2008 Juergen Beisert | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the | |
16 | * Free Software Foundation | |
17 | * 51 Franklin Street, Fifth Floor | |
18 | * Boston, MA 02110-1301, USA. | |
19 | */ | |
20 | ||
21 | #include <linux/clk.h> | |
22 | #include <linux/completion.h> | |
23 | #include <linux/delay.h> | |
f62caccd RG |
24 | #include <linux/dmaengine.h> |
25 | #include <linux/dma-mapping.h> | |
b5f3294f SH |
26 | #include <linux/err.h> |
27 | #include <linux/gpio.h> | |
b5f3294f SH |
28 | #include <linux/interrupt.h> |
29 | #include <linux/io.h> | |
30 | #include <linux/irq.h> | |
31 | #include <linux/kernel.h> | |
32 | #include <linux/module.h> | |
33 | #include <linux/platform_device.h> | |
5a0e3ad6 | 34 | #include <linux/slab.h> |
b5f3294f SH |
35 | #include <linux/spi/spi.h> |
36 | #include <linux/spi/spi_bitbang.h> | |
37 | #include <linux/types.h> | |
22a85e4c SG |
38 | #include <linux/of.h> |
39 | #include <linux/of_device.h> | |
40 | #include <linux/of_gpio.h> | |
b5f3294f | 41 | |
f62caccd | 42 | #include <linux/platform_data/dma-imx.h> |
82906b13 | 43 | #include <linux/platform_data/spi-imx.h> |
b5f3294f SH |
44 | |
45 | #define DRIVER_NAME "spi_imx" | |
46 | ||
47 | #define MXC_CSPIRXDATA 0x00 | |
48 | #define MXC_CSPITXDATA 0x04 | |
49 | #define MXC_CSPICTRL 0x08 | |
50 | #define MXC_CSPIINT 0x0c | |
51 | #define MXC_RESET 0x1c | |
52 | ||
53 | /* generic defines to abstract from the different register layouts */ | |
54 | #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */ | |
55 | #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */ | |
56 | ||
f62caccd RG |
57 | /* The maximum bytes that a sdma BD can transfer.*/ |
58 | #define MAX_SDMA_BD_BYTES (1 << 15) | |
6cdeb002 | 59 | struct spi_imx_config { |
b5f3294f SH |
60 | unsigned int speed_hz; |
61 | unsigned int bpw; | |
62 | unsigned int mode; | |
3b2aa89e | 63 | u8 cs; |
b5f3294f SH |
64 | }; |
65 | ||
f4ba6315 | 66 | enum spi_imx_devtype { |
04ee5854 SG |
67 | IMX1_CSPI, |
68 | IMX21_CSPI, | |
69 | IMX27_CSPI, | |
70 | IMX31_CSPI, | |
71 | IMX35_CSPI, /* CSPI on all i.mx except above */ | |
72 | IMX51_ECSPI, /* ECSPI on i.mx51 and later */ | |
f4ba6315 UKK |
73 | }; |
74 | ||
75 | struct spi_imx_data; | |
76 | ||
77 | struct spi_imx_devtype_data { | |
78 | void (*intctrl)(struct spi_imx_data *, int); | |
79 | int (*config)(struct spi_imx_data *, struct spi_imx_config *); | |
80 | void (*trigger)(struct spi_imx_data *); | |
81 | int (*rx_available)(struct spi_imx_data *); | |
1723e66b | 82 | void (*reset)(struct spi_imx_data *); |
04ee5854 | 83 | enum spi_imx_devtype devtype; |
f4ba6315 UKK |
84 | }; |
85 | ||
6cdeb002 | 86 | struct spi_imx_data { |
b5f3294f | 87 | struct spi_bitbang bitbang; |
6aa800ca | 88 | struct device *dev; |
b5f3294f SH |
89 | |
90 | struct completion xfer_done; | |
cc4d22ae | 91 | void __iomem *base; |
aa29d840 SH |
92 | struct clk *clk_per; |
93 | struct clk *clk_ipg; | |
b5f3294f | 94 | unsigned long spi_clk; |
4bfe927a | 95 | unsigned int spi_bus_clk; |
b5f3294f SH |
96 | |
97 | unsigned int count; | |
6cdeb002 UKK |
98 | void (*tx)(struct spi_imx_data *); |
99 | void (*rx)(struct spi_imx_data *); | |
b5f3294f SH |
100 | void *rx_buf; |
101 | const void *tx_buf; | |
102 | unsigned int txfifo; /* number of words pushed in tx FIFO */ | |
103 | ||
f62caccd RG |
104 | /* DMA */ |
105 | unsigned int dma_is_inited; | |
106 | unsigned int dma_finished; | |
107 | bool usedma; | |
0dfbaa89 | 108 | u32 wml; |
f62caccd RG |
109 | struct completion dma_rx_completion; |
110 | struct completion dma_tx_completion; | |
111 | ||
80023cb3 | 112 | const struct spi_imx_devtype_data *devtype_data; |
c2387cb9 | 113 | int chipselect[0]; |
b5f3294f SH |
114 | }; |
115 | ||
04ee5854 SG |
116 | static inline int is_imx27_cspi(struct spi_imx_data *d) |
117 | { | |
118 | return d->devtype_data->devtype == IMX27_CSPI; | |
119 | } | |
120 | ||
121 | static inline int is_imx35_cspi(struct spi_imx_data *d) | |
122 | { | |
123 | return d->devtype_data->devtype == IMX35_CSPI; | |
124 | } | |
125 | ||
f8a87617 AB |
126 | static inline int is_imx51_ecspi(struct spi_imx_data *d) |
127 | { | |
128 | return d->devtype_data->devtype == IMX51_ECSPI; | |
129 | } | |
130 | ||
04ee5854 SG |
131 | static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d) |
132 | { | |
f8a87617 | 133 | return is_imx51_ecspi(d) ? 64 : 8; |
04ee5854 SG |
134 | } |
135 | ||
b5f3294f | 136 | #define MXC_SPI_BUF_RX(type) \ |
6cdeb002 | 137 | static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \ |
b5f3294f | 138 | { \ |
6cdeb002 | 139 | unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \ |
b5f3294f | 140 | \ |
6cdeb002 UKK |
141 | if (spi_imx->rx_buf) { \ |
142 | *(type *)spi_imx->rx_buf = val; \ | |
143 | spi_imx->rx_buf += sizeof(type); \ | |
b5f3294f SH |
144 | } \ |
145 | } | |
146 | ||
147 | #define MXC_SPI_BUF_TX(type) \ | |
6cdeb002 | 148 | static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \ |
b5f3294f SH |
149 | { \ |
150 | type val = 0; \ | |
151 | \ | |
6cdeb002 UKK |
152 | if (spi_imx->tx_buf) { \ |
153 | val = *(type *)spi_imx->tx_buf; \ | |
154 | spi_imx->tx_buf += sizeof(type); \ | |
b5f3294f SH |
155 | } \ |
156 | \ | |
6cdeb002 | 157 | spi_imx->count -= sizeof(type); \ |
b5f3294f | 158 | \ |
6cdeb002 | 159 | writel(val, spi_imx->base + MXC_CSPITXDATA); \ |
b5f3294f SH |
160 | } |
161 | ||
162 | MXC_SPI_BUF_RX(u8) | |
163 | MXC_SPI_BUF_TX(u8) | |
164 | MXC_SPI_BUF_RX(u16) | |
165 | MXC_SPI_BUF_TX(u16) | |
166 | MXC_SPI_BUF_RX(u32) | |
167 | MXC_SPI_BUF_TX(u32) | |
168 | ||
169 | /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set | |
170 | * (which is currently not the case in this driver) | |
171 | */ | |
172 | static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192, | |
173 | 256, 384, 512, 768, 1024}; | |
174 | ||
175 | /* MX21, MX27 */ | |
6cdeb002 | 176 | static unsigned int spi_imx_clkdiv_1(unsigned int fin, |
04ee5854 | 177 | unsigned int fspi, unsigned int max) |
b5f3294f | 178 | { |
04ee5854 | 179 | int i; |
b5f3294f SH |
180 | |
181 | for (i = 2; i < max; i++) | |
182 | if (fspi * mxc_clkdivs[i] >= fin) | |
183 | return i; | |
184 | ||
185 | return max; | |
186 | } | |
187 | ||
0b599603 | 188 | /* MX1, MX31, MX35, MX51 CSPI */ |
6cdeb002 | 189 | static unsigned int spi_imx_clkdiv_2(unsigned int fin, |
b5f3294f SH |
190 | unsigned int fspi) |
191 | { | |
192 | int i, div = 4; | |
193 | ||
194 | for (i = 0; i < 7; i++) { | |
195 | if (fspi * div >= fin) | |
196 | return i; | |
197 | div <<= 1; | |
198 | } | |
199 | ||
200 | return 7; | |
201 | } | |
202 | ||
f62caccd RG |
203 | static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi, |
204 | struct spi_transfer *transfer) | |
205 | { | |
206 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); | |
207 | ||
390f0ffe AB |
208 | if (spi_imx->dma_is_inited && transfer->len >= spi_imx->wml && |
209 | (transfer->len % spi_imx->wml) == 0) | |
f62caccd RG |
210 | return true; |
211 | return false; | |
212 | } | |
213 | ||
66de757c SG |
214 | #define MX51_ECSPI_CTRL 0x08 |
215 | #define MX51_ECSPI_CTRL_ENABLE (1 << 0) | |
216 | #define MX51_ECSPI_CTRL_XCH (1 << 2) | |
f62caccd | 217 | #define MX51_ECSPI_CTRL_SMC (1 << 3) |
66de757c SG |
218 | #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4) |
219 | #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8 | |
220 | #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12 | |
221 | #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) | |
222 | #define MX51_ECSPI_CTRL_BL_OFFSET 20 | |
223 | ||
224 | #define MX51_ECSPI_CONFIG 0x0c | |
225 | #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) | |
226 | #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) | |
227 | #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) | |
228 | #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) | |
c09b890b | 229 | #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20)) |
66de757c SG |
230 | |
231 | #define MX51_ECSPI_INT 0x10 | |
232 | #define MX51_ECSPI_INT_TEEN (1 << 0) | |
233 | #define MX51_ECSPI_INT_RREN (1 << 3) | |
234 | ||
f62caccd RG |
235 | #define MX51_ECSPI_DMA 0x14 |
236 | #define MX51_ECSPI_DMA_TX_WML_OFFSET 0 | |
237 | #define MX51_ECSPI_DMA_TX_WML_MASK 0x3F | |
238 | #define MX51_ECSPI_DMA_RX_WML_OFFSET 16 | |
239 | #define MX51_ECSPI_DMA_RX_WML_MASK (0x3F << 16) | |
240 | #define MX51_ECSPI_DMA_RXT_WML_OFFSET 24 | |
241 | #define MX51_ECSPI_DMA_RXT_WML_MASK (0x3F << 24) | |
242 | ||
243 | #define MX51_ECSPI_DMA_TEDEN_OFFSET 7 | |
244 | #define MX51_ECSPI_DMA_RXDEN_OFFSET 23 | |
245 | #define MX51_ECSPI_DMA_RXTDEN_OFFSET 31 | |
246 | ||
66de757c SG |
247 | #define MX51_ECSPI_STAT 0x18 |
248 | #define MX51_ECSPI_STAT_RR (1 << 3) | |
0b599603 | 249 | |
9f6aa42b FE |
250 | #define MX51_ECSPI_TESTREG 0x20 |
251 | #define MX51_ECSPI_TESTREG_LBC BIT(31) | |
252 | ||
0b599603 | 253 | /* MX51 eCSPI */ |
6aa800ca SH |
254 | static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx, |
255 | unsigned int fspi, unsigned int *fres) | |
0b599603 UKK |
256 | { |
257 | /* | |
258 | * there are two 4-bit dividers, the pre-divider divides by | |
259 | * $pre, the post-divider by 2^$post | |
260 | */ | |
261 | unsigned int pre, post; | |
6aa800ca | 262 | unsigned int fin = spi_imx->spi_clk; |
0b599603 UKK |
263 | |
264 | if (unlikely(fspi > fin)) | |
265 | return 0; | |
266 | ||
267 | post = fls(fin) - fls(fspi); | |
268 | if (fin > fspi << post) | |
269 | post++; | |
270 | ||
271 | /* now we have: (fin <= fspi << post) with post being minimal */ | |
272 | ||
273 | post = max(4U, post) - 4; | |
274 | if (unlikely(post > 0xf)) { | |
6aa800ca SH |
275 | dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n", |
276 | fspi, fin); | |
0b599603 UKK |
277 | return 0xff; |
278 | } | |
279 | ||
280 | pre = DIV_ROUND_UP(fin, fspi << post) - 1; | |
281 | ||
6aa800ca | 282 | dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n", |
0b599603 | 283 | __func__, fin, fspi, post, pre); |
6fd8b850 MV |
284 | |
285 | /* Resulting frequency for the SCLK line. */ | |
286 | *fres = (fin / (pre + 1)) >> post; | |
287 | ||
66de757c SG |
288 | return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) | |
289 | (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET); | |
0b599603 UKK |
290 | } |
291 | ||
66de757c | 292 | static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable) |
0b599603 UKK |
293 | { |
294 | unsigned val = 0; | |
295 | ||
296 | if (enable & MXC_INT_TE) | |
66de757c | 297 | val |= MX51_ECSPI_INT_TEEN; |
0b599603 UKK |
298 | |
299 | if (enable & MXC_INT_RR) | |
66de757c | 300 | val |= MX51_ECSPI_INT_RREN; |
0b599603 | 301 | |
66de757c | 302 | writel(val, spi_imx->base + MX51_ECSPI_INT); |
0b599603 UKK |
303 | } |
304 | ||
66de757c | 305 | static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx) |
0b599603 | 306 | { |
f62caccd RG |
307 | u32 reg = readl(spi_imx->base + MX51_ECSPI_CTRL); |
308 | ||
309 | if (!spi_imx->usedma) | |
310 | reg |= MX51_ECSPI_CTRL_XCH; | |
311 | else if (!spi_imx->dma_finished) | |
312 | reg |= MX51_ECSPI_CTRL_SMC; | |
313 | else | |
314 | reg &= ~MX51_ECSPI_CTRL_SMC; | |
66de757c | 315 | writel(reg, spi_imx->base + MX51_ECSPI_CTRL); |
0b599603 UKK |
316 | } |
317 | ||
66de757c | 318 | static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx, |
0b599603 UKK |
319 | struct spi_imx_config *config) |
320 | { | |
f62caccd RG |
321 | u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0, dma = 0; |
322 | u32 tx_wml_cfg, rx_wml_cfg, rxt_wml_cfg; | |
9f6aa42b | 323 | u32 clk = config->speed_hz, delay, reg; |
0b599603 | 324 | |
f020c39e SH |
325 | /* |
326 | * The hardware seems to have a race condition when changing modes. The | |
327 | * current assumption is that the selection of the channel arrives | |
328 | * earlier in the hardware than the mode bits when they are written at | |
329 | * the same time. | |
330 | * So set master mode for all channels as we do not support slave mode. | |
331 | */ | |
66de757c | 332 | ctrl |= MX51_ECSPI_CTRL_MODE_MASK; |
0b599603 UKK |
333 | |
334 | /* set clock speed */ | |
6aa800ca | 335 | ctrl |= mx51_ecspi_clkdiv(spi_imx, config->speed_hz, &clk); |
4bfe927a | 336 | spi_imx->spi_bus_clk = clk; |
0b599603 UKK |
337 | |
338 | /* set chip select to use */ | |
66de757c | 339 | ctrl |= MX51_ECSPI_CTRL_CS(config->cs); |
0b599603 | 340 | |
66de757c | 341 | ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET; |
0b599603 | 342 | |
66de757c | 343 | cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs); |
0b599603 UKK |
344 | |
345 | if (config->mode & SPI_CPHA) | |
66de757c | 346 | cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs); |
1476253c AK |
347 | else |
348 | cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(config->cs); | |
0b599603 | 349 | |
c09b890b | 350 | if (config->mode & SPI_CPOL) { |
66de757c | 351 | cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs); |
c09b890b | 352 | cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs); |
1476253c AK |
353 | } else { |
354 | cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(config->cs); | |
355 | cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(config->cs); | |
c09b890b | 356 | } |
0b599603 | 357 | if (config->mode & SPI_CS_HIGH) |
66de757c | 358 | cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs); |
1476253c AK |
359 | else |
360 | cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(config->cs); | |
0b599603 | 361 | |
f677f17c AB |
362 | /* CTRL register always go first to bring out controller from reset */ |
363 | writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); | |
364 | ||
9f6aa42b FE |
365 | reg = readl(spi_imx->base + MX51_ECSPI_TESTREG); |
366 | if (config->mode & SPI_LOOP) | |
367 | reg |= MX51_ECSPI_TESTREG_LBC; | |
368 | else | |
369 | reg &= ~MX51_ECSPI_TESTREG_LBC; | |
370 | writel(reg, spi_imx->base + MX51_ECSPI_TESTREG); | |
371 | ||
66de757c | 372 | writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); |
0b599603 | 373 | |
6fd8b850 MV |
374 | /* |
375 | * Wait until the changes in the configuration register CONFIGREG | |
376 | * propagate into the hardware. It takes exactly one tick of the | |
377 | * SCLK clock, but we will wait two SCLK clock just to be sure. The | |
378 | * effect of the delay it takes for the hardware to apply changes | |
379 | * is noticable if the SCLK clock run very slow. In such a case, if | |
380 | * the polarity of SCLK should be inverted, the GPIO ChipSelect might | |
381 | * be asserted before the SCLK polarity changes, which would disrupt | |
382 | * the SPI communication as the device on the other end would consider | |
383 | * the change of SCLK polarity as a clock tick already. | |
384 | */ | |
385 | delay = (2 * 1000000) / clk; | |
386 | if (likely(delay < 10)) /* SCLK is faster than 100 kHz */ | |
387 | udelay(delay); | |
388 | else /* SCLK is _very_ slow */ | |
389 | usleep_range(delay, delay + 10); | |
390 | ||
f62caccd RG |
391 | /* |
392 | * Configure the DMA register: setup the watermark | |
393 | * and enable DMA request. | |
394 | */ | |
395 | if (spi_imx->dma_is_inited) { | |
396 | dma = readl(spi_imx->base + MX51_ECSPI_DMA); | |
397 | ||
0dfbaa89 AB |
398 | rx_wml_cfg = spi_imx->wml << MX51_ECSPI_DMA_RX_WML_OFFSET; |
399 | tx_wml_cfg = spi_imx->wml << MX51_ECSPI_DMA_TX_WML_OFFSET; | |
400 | rxt_wml_cfg = spi_imx->wml << MX51_ECSPI_DMA_RXT_WML_OFFSET; | |
f62caccd RG |
401 | dma = (dma & ~MX51_ECSPI_DMA_TX_WML_MASK |
402 | & ~MX51_ECSPI_DMA_RX_WML_MASK | |
403 | & ~MX51_ECSPI_DMA_RXT_WML_MASK) | |
404 | | rx_wml_cfg | tx_wml_cfg | rxt_wml_cfg | |
405 | |(1 << MX51_ECSPI_DMA_TEDEN_OFFSET) | |
406 | |(1 << MX51_ECSPI_DMA_RXDEN_OFFSET) | |
407 | |(1 << MX51_ECSPI_DMA_RXTDEN_OFFSET); | |
408 | ||
409 | writel(dma, spi_imx->base + MX51_ECSPI_DMA); | |
410 | } | |
411 | ||
0b599603 UKK |
412 | return 0; |
413 | } | |
414 | ||
66de757c | 415 | static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx) |
0b599603 | 416 | { |
66de757c | 417 | return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; |
0b599603 UKK |
418 | } |
419 | ||
66de757c | 420 | static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx) |
0b599603 UKK |
421 | { |
422 | /* drain receive buffer */ | |
66de757c | 423 | while (mx51_ecspi_rx_available(spi_imx)) |
0b599603 UKK |
424 | readl(spi_imx->base + MXC_CSPIRXDATA); |
425 | } | |
426 | ||
b5f3294f SH |
427 | #define MX31_INTREG_TEEN (1 << 0) |
428 | #define MX31_INTREG_RREN (1 << 3) | |
429 | ||
430 | #define MX31_CSPICTRL_ENABLE (1 << 0) | |
431 | #define MX31_CSPICTRL_MASTER (1 << 1) | |
432 | #define MX31_CSPICTRL_XCH (1 << 2) | |
433 | #define MX31_CSPICTRL_POL (1 << 4) | |
434 | #define MX31_CSPICTRL_PHA (1 << 5) | |
435 | #define MX31_CSPICTRL_SSCTL (1 << 6) | |
436 | #define MX31_CSPICTRL_SSPOL (1 << 7) | |
437 | #define MX31_CSPICTRL_BC_SHIFT 8 | |
438 | #define MX35_CSPICTRL_BL_SHIFT 20 | |
439 | #define MX31_CSPICTRL_CS_SHIFT 24 | |
440 | #define MX35_CSPICTRL_CS_SHIFT 12 | |
441 | #define MX31_CSPICTRL_DR_SHIFT 16 | |
442 | ||
443 | #define MX31_CSPISTATUS 0x14 | |
444 | #define MX31_STATUS_RR (1 << 3) | |
445 | ||
446 | /* These functions also work for the i.MX35, but be aware that | |
447 | * the i.MX35 has a slightly different register layout for bits | |
448 | * we do not use here. | |
449 | */ | |
f4ba6315 | 450 | static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable) |
b5f3294f SH |
451 | { |
452 | unsigned int val = 0; | |
453 | ||
454 | if (enable & MXC_INT_TE) | |
455 | val |= MX31_INTREG_TEEN; | |
456 | if (enable & MXC_INT_RR) | |
457 | val |= MX31_INTREG_RREN; | |
458 | ||
6cdeb002 | 459 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
460 | } |
461 | ||
f4ba6315 | 462 | static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
463 | { |
464 | unsigned int reg; | |
465 | ||
6cdeb002 | 466 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
b5f3294f | 467 | reg |= MX31_CSPICTRL_XCH; |
6cdeb002 | 468 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
469 | } |
470 | ||
2a64a90a | 471 | static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx, |
1723e66b UKK |
472 | struct spi_imx_config *config) |
473 | { | |
474 | unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; | |
3b2aa89e | 475 | int cs = spi_imx->chipselect[config->cs]; |
1723e66b UKK |
476 | |
477 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << | |
478 | MX31_CSPICTRL_DR_SHIFT; | |
479 | ||
04ee5854 | 480 | if (is_imx35_cspi(spi_imx)) { |
2a64a90a SG |
481 | reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT; |
482 | reg |= MX31_CSPICTRL_SSCTL; | |
483 | } else { | |
484 | reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT; | |
485 | } | |
1723e66b UKK |
486 | |
487 | if (config->mode & SPI_CPHA) | |
488 | reg |= MX31_CSPICTRL_PHA; | |
489 | if (config->mode & SPI_CPOL) | |
490 | reg |= MX31_CSPICTRL_POL; | |
491 | if (config->mode & SPI_CS_HIGH) | |
492 | reg |= MX31_CSPICTRL_SSPOL; | |
3b2aa89e | 493 | if (cs < 0) |
2a64a90a | 494 | reg |= (cs + 32) << |
04ee5854 SG |
495 | (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT : |
496 | MX31_CSPICTRL_CS_SHIFT); | |
1723e66b UKK |
497 | |
498 | writel(reg, spi_imx->base + MXC_CSPICTRL); | |
499 | ||
500 | return 0; | |
501 | } | |
502 | ||
f4ba6315 | 503 | static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 504 | { |
6cdeb002 | 505 | return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; |
b5f3294f SH |
506 | } |
507 | ||
2a64a90a | 508 | static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx) |
1723e66b UKK |
509 | { |
510 | /* drain receive buffer */ | |
2a64a90a | 511 | while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) |
1723e66b UKK |
512 | readl(spi_imx->base + MXC_CSPIRXDATA); |
513 | } | |
514 | ||
3451fb15 SG |
515 | #define MX21_INTREG_RR (1 << 4) |
516 | #define MX21_INTREG_TEEN (1 << 9) | |
517 | #define MX21_INTREG_RREN (1 << 13) | |
518 | ||
519 | #define MX21_CSPICTRL_POL (1 << 5) | |
520 | #define MX21_CSPICTRL_PHA (1 << 6) | |
521 | #define MX21_CSPICTRL_SSPOL (1 << 8) | |
522 | #define MX21_CSPICTRL_XCH (1 << 9) | |
523 | #define MX21_CSPICTRL_ENABLE (1 << 10) | |
524 | #define MX21_CSPICTRL_MASTER (1 << 11) | |
525 | #define MX21_CSPICTRL_DR_SHIFT 14 | |
526 | #define MX21_CSPICTRL_CS_SHIFT 19 | |
527 | ||
528 | static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable) | |
b5f3294f SH |
529 | { |
530 | unsigned int val = 0; | |
531 | ||
532 | if (enable & MXC_INT_TE) | |
3451fb15 | 533 | val |= MX21_INTREG_TEEN; |
b5f3294f | 534 | if (enable & MXC_INT_RR) |
3451fb15 | 535 | val |= MX21_INTREG_RREN; |
b5f3294f | 536 | |
6cdeb002 | 537 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
538 | } |
539 | ||
3451fb15 | 540 | static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
541 | { |
542 | unsigned int reg; | |
543 | ||
6cdeb002 | 544 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
3451fb15 | 545 | reg |= MX21_CSPICTRL_XCH; |
6cdeb002 | 546 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
547 | } |
548 | ||
3451fb15 | 549 | static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx, |
6cdeb002 | 550 | struct spi_imx_config *config) |
b5f3294f | 551 | { |
3451fb15 | 552 | unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER; |
3b2aa89e | 553 | int cs = spi_imx->chipselect[config->cs]; |
04ee5854 | 554 | unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18; |
b5f3294f | 555 | |
04ee5854 | 556 | reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) << |
3451fb15 | 557 | MX21_CSPICTRL_DR_SHIFT; |
b5f3294f SH |
558 | reg |= config->bpw - 1; |
559 | ||
560 | if (config->mode & SPI_CPHA) | |
3451fb15 | 561 | reg |= MX21_CSPICTRL_PHA; |
b5f3294f | 562 | if (config->mode & SPI_CPOL) |
3451fb15 | 563 | reg |= MX21_CSPICTRL_POL; |
b5f3294f | 564 | if (config->mode & SPI_CS_HIGH) |
3451fb15 | 565 | reg |= MX21_CSPICTRL_SSPOL; |
3b2aa89e | 566 | if (cs < 0) |
3451fb15 | 567 | reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT; |
b5f3294f | 568 | |
6cdeb002 | 569 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
570 | |
571 | return 0; | |
572 | } | |
573 | ||
3451fb15 | 574 | static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 575 | { |
3451fb15 | 576 | return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; |
b5f3294f SH |
577 | } |
578 | ||
3451fb15 | 579 | static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx) |
1723e66b UKK |
580 | { |
581 | writel(1, spi_imx->base + MXC_RESET); | |
582 | } | |
583 | ||
b5f3294f SH |
584 | #define MX1_INTREG_RR (1 << 3) |
585 | #define MX1_INTREG_TEEN (1 << 8) | |
586 | #define MX1_INTREG_RREN (1 << 11) | |
587 | ||
588 | #define MX1_CSPICTRL_POL (1 << 4) | |
589 | #define MX1_CSPICTRL_PHA (1 << 5) | |
590 | #define MX1_CSPICTRL_XCH (1 << 8) | |
591 | #define MX1_CSPICTRL_ENABLE (1 << 9) | |
592 | #define MX1_CSPICTRL_MASTER (1 << 10) | |
593 | #define MX1_CSPICTRL_DR_SHIFT 13 | |
594 | ||
f4ba6315 | 595 | static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable) |
b5f3294f SH |
596 | { |
597 | unsigned int val = 0; | |
598 | ||
599 | if (enable & MXC_INT_TE) | |
600 | val |= MX1_INTREG_TEEN; | |
601 | if (enable & MXC_INT_RR) | |
602 | val |= MX1_INTREG_RREN; | |
603 | ||
6cdeb002 | 604 | writel(val, spi_imx->base + MXC_CSPIINT); |
b5f3294f SH |
605 | } |
606 | ||
f4ba6315 | 607 | static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx) |
b5f3294f SH |
608 | { |
609 | unsigned int reg; | |
610 | ||
6cdeb002 | 611 | reg = readl(spi_imx->base + MXC_CSPICTRL); |
b5f3294f | 612 | reg |= MX1_CSPICTRL_XCH; |
6cdeb002 | 613 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
614 | } |
615 | ||
f4ba6315 | 616 | static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx, |
6cdeb002 | 617 | struct spi_imx_config *config) |
b5f3294f SH |
618 | { |
619 | unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; | |
620 | ||
6cdeb002 | 621 | reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << |
b5f3294f SH |
622 | MX1_CSPICTRL_DR_SHIFT; |
623 | reg |= config->bpw - 1; | |
624 | ||
625 | if (config->mode & SPI_CPHA) | |
626 | reg |= MX1_CSPICTRL_PHA; | |
627 | if (config->mode & SPI_CPOL) | |
628 | reg |= MX1_CSPICTRL_POL; | |
629 | ||
6cdeb002 | 630 | writel(reg, spi_imx->base + MXC_CSPICTRL); |
b5f3294f SH |
631 | |
632 | return 0; | |
633 | } | |
634 | ||
f4ba6315 | 635 | static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx) |
b5f3294f | 636 | { |
6cdeb002 | 637 | return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; |
b5f3294f SH |
638 | } |
639 | ||
1723e66b UKK |
640 | static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx) |
641 | { | |
642 | writel(1, spi_imx->base + MXC_RESET); | |
643 | } | |
644 | ||
04ee5854 SG |
645 | static struct spi_imx_devtype_data imx1_cspi_devtype_data = { |
646 | .intctrl = mx1_intctrl, | |
647 | .config = mx1_config, | |
648 | .trigger = mx1_trigger, | |
649 | .rx_available = mx1_rx_available, | |
650 | .reset = mx1_reset, | |
651 | .devtype = IMX1_CSPI, | |
652 | }; | |
653 | ||
654 | static struct spi_imx_devtype_data imx21_cspi_devtype_data = { | |
655 | .intctrl = mx21_intctrl, | |
656 | .config = mx21_config, | |
657 | .trigger = mx21_trigger, | |
658 | .rx_available = mx21_rx_available, | |
659 | .reset = mx21_reset, | |
660 | .devtype = IMX21_CSPI, | |
661 | }; | |
662 | ||
663 | static struct spi_imx_devtype_data imx27_cspi_devtype_data = { | |
664 | /* i.mx27 cspi shares the functions with i.mx21 one */ | |
665 | .intctrl = mx21_intctrl, | |
666 | .config = mx21_config, | |
667 | .trigger = mx21_trigger, | |
668 | .rx_available = mx21_rx_available, | |
669 | .reset = mx21_reset, | |
670 | .devtype = IMX27_CSPI, | |
671 | }; | |
672 | ||
673 | static struct spi_imx_devtype_data imx31_cspi_devtype_data = { | |
674 | .intctrl = mx31_intctrl, | |
675 | .config = mx31_config, | |
676 | .trigger = mx31_trigger, | |
677 | .rx_available = mx31_rx_available, | |
678 | .reset = mx31_reset, | |
679 | .devtype = IMX31_CSPI, | |
680 | }; | |
681 | ||
682 | static struct spi_imx_devtype_data imx35_cspi_devtype_data = { | |
683 | /* i.mx35 and later cspi shares the functions with i.mx31 one */ | |
684 | .intctrl = mx31_intctrl, | |
685 | .config = mx31_config, | |
686 | .trigger = mx31_trigger, | |
687 | .rx_available = mx31_rx_available, | |
688 | .reset = mx31_reset, | |
689 | .devtype = IMX35_CSPI, | |
690 | }; | |
691 | ||
692 | static struct spi_imx_devtype_data imx51_ecspi_devtype_data = { | |
693 | .intctrl = mx51_ecspi_intctrl, | |
694 | .config = mx51_ecspi_config, | |
695 | .trigger = mx51_ecspi_trigger, | |
696 | .rx_available = mx51_ecspi_rx_available, | |
697 | .reset = mx51_ecspi_reset, | |
698 | .devtype = IMX51_ECSPI, | |
699 | }; | |
700 | ||
db1b8200 | 701 | static const struct platform_device_id spi_imx_devtype[] = { |
04ee5854 SG |
702 | { |
703 | .name = "imx1-cspi", | |
704 | .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data, | |
705 | }, { | |
706 | .name = "imx21-cspi", | |
707 | .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data, | |
708 | }, { | |
709 | .name = "imx27-cspi", | |
710 | .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data, | |
711 | }, { | |
712 | .name = "imx31-cspi", | |
713 | .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data, | |
714 | }, { | |
715 | .name = "imx35-cspi", | |
716 | .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data, | |
717 | }, { | |
718 | .name = "imx51-ecspi", | |
719 | .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data, | |
720 | }, { | |
721 | /* sentinel */ | |
722 | } | |
f4ba6315 UKK |
723 | }; |
724 | ||
22a85e4c SG |
725 | static const struct of_device_id spi_imx_dt_ids[] = { |
726 | { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, }, | |
727 | { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, }, | |
728 | { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, }, | |
729 | { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, }, | |
730 | { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, }, | |
731 | { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, }, | |
732 | { /* sentinel */ } | |
733 | }; | |
27743e0b | 734 | MODULE_DEVICE_TABLE(of, spi_imx_dt_ids); |
22a85e4c | 735 | |
6cdeb002 | 736 | static void spi_imx_chipselect(struct spi_device *spi, int is_active) |
b5f3294f | 737 | { |
6cdeb002 | 738 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
6cdeb002 | 739 | int gpio = spi_imx->chipselect[spi->chip_select]; |
e6a0a8bf UKK |
740 | int active = is_active != BITBANG_CS_INACTIVE; |
741 | int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); | |
b5f3294f | 742 | |
8b17e055 | 743 | if (!gpio_is_valid(gpio)) |
b5f3294f | 744 | return; |
b5f3294f | 745 | |
e6a0a8bf | 746 | gpio_set_value(gpio, dev_is_lowactive ^ active); |
b5f3294f SH |
747 | } |
748 | ||
6cdeb002 | 749 | static void spi_imx_push(struct spi_imx_data *spi_imx) |
b5f3294f | 750 | { |
04ee5854 | 751 | while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) { |
6cdeb002 | 752 | if (!spi_imx->count) |
b5f3294f | 753 | break; |
6cdeb002 UKK |
754 | spi_imx->tx(spi_imx); |
755 | spi_imx->txfifo++; | |
b5f3294f SH |
756 | } |
757 | ||
edd501bb | 758 | spi_imx->devtype_data->trigger(spi_imx); |
b5f3294f SH |
759 | } |
760 | ||
6cdeb002 | 761 | static irqreturn_t spi_imx_isr(int irq, void *dev_id) |
b5f3294f | 762 | { |
6cdeb002 | 763 | struct spi_imx_data *spi_imx = dev_id; |
b5f3294f | 764 | |
edd501bb | 765 | while (spi_imx->devtype_data->rx_available(spi_imx)) { |
6cdeb002 UKK |
766 | spi_imx->rx(spi_imx); |
767 | spi_imx->txfifo--; | |
b5f3294f SH |
768 | } |
769 | ||
6cdeb002 UKK |
770 | if (spi_imx->count) { |
771 | spi_imx_push(spi_imx); | |
b5f3294f SH |
772 | return IRQ_HANDLED; |
773 | } | |
774 | ||
6cdeb002 | 775 | if (spi_imx->txfifo) { |
b5f3294f SH |
776 | /* No data left to push, but still waiting for rx data, |
777 | * enable receive data available interrupt. | |
778 | */ | |
edd501bb | 779 | spi_imx->devtype_data->intctrl( |
f4ba6315 | 780 | spi_imx, MXC_INT_RR); |
b5f3294f SH |
781 | return IRQ_HANDLED; |
782 | } | |
783 | ||
edd501bb | 784 | spi_imx->devtype_data->intctrl(spi_imx, 0); |
6cdeb002 | 785 | complete(&spi_imx->xfer_done); |
b5f3294f SH |
786 | |
787 | return IRQ_HANDLED; | |
788 | } | |
789 | ||
6cdeb002 | 790 | static int spi_imx_setupxfer(struct spi_device *spi, |
b5f3294f SH |
791 | struct spi_transfer *t) |
792 | { | |
6cdeb002 UKK |
793 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
794 | struct spi_imx_config config; | |
b5f3294f SH |
795 | |
796 | config.bpw = t ? t->bits_per_word : spi->bits_per_word; | |
797 | config.speed_hz = t ? t->speed_hz : spi->max_speed_hz; | |
798 | config.mode = spi->mode; | |
3b2aa89e | 799 | config.cs = spi->chip_select; |
b5f3294f | 800 | |
462d26b5 SH |
801 | if (!config.speed_hz) |
802 | config.speed_hz = spi->max_speed_hz; | |
803 | if (!config.bpw) | |
804 | config.bpw = spi->bits_per_word; | |
462d26b5 | 805 | |
e6a0a8bf UKK |
806 | /* Initialize the functions for transfer */ |
807 | if (config.bpw <= 8) { | |
808 | spi_imx->rx = spi_imx_buf_rx_u8; | |
809 | spi_imx->tx = spi_imx_buf_tx_u8; | |
810 | } else if (config.bpw <= 16) { | |
811 | spi_imx->rx = spi_imx_buf_rx_u16; | |
812 | spi_imx->tx = spi_imx_buf_tx_u16; | |
6051426f | 813 | } else { |
e6a0a8bf UKK |
814 | spi_imx->rx = spi_imx_buf_rx_u32; |
815 | spi_imx->tx = spi_imx_buf_tx_u32; | |
24778be2 | 816 | } |
e6a0a8bf | 817 | |
c008a800 SH |
818 | if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t)) |
819 | spi_imx->usedma = 1; | |
820 | else | |
821 | spi_imx->usedma = 0; | |
822 | ||
edd501bb | 823 | spi_imx->devtype_data->config(spi_imx, &config); |
b5f3294f SH |
824 | |
825 | return 0; | |
826 | } | |
827 | ||
f62caccd RG |
828 | static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx) |
829 | { | |
830 | struct spi_master *master = spi_imx->bitbang.master; | |
831 | ||
832 | if (master->dma_rx) { | |
833 | dma_release_channel(master->dma_rx); | |
834 | master->dma_rx = NULL; | |
835 | } | |
836 | ||
837 | if (master->dma_tx) { | |
838 | dma_release_channel(master->dma_tx); | |
839 | master->dma_tx = NULL; | |
840 | } | |
841 | ||
842 | spi_imx->dma_is_inited = 0; | |
843 | } | |
844 | ||
845 | static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx, | |
846 | struct spi_master *master, | |
847 | const struct resource *res) | |
848 | { | |
849 | struct dma_slave_config slave_config = {}; | |
850 | int ret; | |
851 | ||
a02bb401 RG |
852 | /* use pio mode for i.mx6dl chip TKT238285 */ |
853 | if (of_machine_is_compatible("fsl,imx6dl")) | |
854 | return 0; | |
855 | ||
0dfbaa89 AB |
856 | spi_imx->wml = spi_imx_get_fifosize(spi_imx) / 2; |
857 | ||
f62caccd | 858 | /* Prepare for TX DMA: */ |
3760047a AB |
859 | master->dma_tx = dma_request_slave_channel_reason(dev, "tx"); |
860 | if (IS_ERR(master->dma_tx)) { | |
861 | ret = PTR_ERR(master->dma_tx); | |
862 | dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret); | |
863 | master->dma_tx = NULL; | |
f62caccd RG |
864 | goto err; |
865 | } | |
866 | ||
867 | slave_config.direction = DMA_MEM_TO_DEV; | |
868 | slave_config.dst_addr = res->start + MXC_CSPITXDATA; | |
869 | slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
0dfbaa89 | 870 | slave_config.dst_maxburst = spi_imx->wml; |
f62caccd RG |
871 | ret = dmaengine_slave_config(master->dma_tx, &slave_config); |
872 | if (ret) { | |
873 | dev_err(dev, "error in TX dma configuration.\n"); | |
874 | goto err; | |
875 | } | |
876 | ||
877 | /* Prepare for RX : */ | |
3760047a AB |
878 | master->dma_rx = dma_request_slave_channel_reason(dev, "rx"); |
879 | if (IS_ERR(master->dma_rx)) { | |
880 | ret = PTR_ERR(master->dma_rx); | |
881 | dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret); | |
882 | master->dma_rx = NULL; | |
f62caccd RG |
883 | goto err; |
884 | } | |
885 | ||
886 | slave_config.direction = DMA_DEV_TO_MEM; | |
887 | slave_config.src_addr = res->start + MXC_CSPIRXDATA; | |
888 | slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
0dfbaa89 | 889 | slave_config.src_maxburst = spi_imx->wml; |
f62caccd RG |
890 | ret = dmaengine_slave_config(master->dma_rx, &slave_config); |
891 | if (ret) { | |
892 | dev_err(dev, "error in RX dma configuration.\n"); | |
893 | goto err; | |
894 | } | |
895 | ||
896 | init_completion(&spi_imx->dma_rx_completion); | |
897 | init_completion(&spi_imx->dma_tx_completion); | |
898 | master->can_dma = spi_imx_can_dma; | |
899 | master->max_dma_len = MAX_SDMA_BD_BYTES; | |
900 | spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX | | |
901 | SPI_MASTER_MUST_TX; | |
902 | spi_imx->dma_is_inited = 1; | |
903 | ||
904 | return 0; | |
905 | err: | |
906 | spi_imx_sdma_exit(spi_imx); | |
907 | return ret; | |
908 | } | |
909 | ||
910 | static void spi_imx_dma_rx_callback(void *cookie) | |
911 | { | |
912 | struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; | |
913 | ||
914 | complete(&spi_imx->dma_rx_completion); | |
915 | } | |
916 | ||
917 | static void spi_imx_dma_tx_callback(void *cookie) | |
918 | { | |
919 | struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie; | |
920 | ||
921 | complete(&spi_imx->dma_tx_completion); | |
922 | } | |
923 | ||
4bfe927a AB |
924 | static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size) |
925 | { | |
926 | unsigned long timeout = 0; | |
927 | ||
928 | /* Time with actual data transfer and CS change delay related to HW */ | |
929 | timeout = (8 + 4) * size / spi_imx->spi_bus_clk; | |
930 | ||
931 | /* Add extra second for scheduler related activities */ | |
932 | timeout += 1; | |
933 | ||
934 | /* Double calculated timeout */ | |
935 | return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC); | |
936 | } | |
937 | ||
f62caccd RG |
938 | static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx, |
939 | struct spi_transfer *transfer) | |
940 | { | |
941 | struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; | |
942 | int ret; | |
4bfe927a | 943 | unsigned long transfer_timeout; |
56536a7f | 944 | unsigned long timeout; |
f62caccd RG |
945 | struct spi_master *master = spi_imx->bitbang.master; |
946 | struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; | |
947 | ||
948 | if (tx) { | |
949 | desc_tx = dmaengine_prep_slave_sg(master->dma_tx, | |
e8361f70 | 950 | tx->sgl, tx->nents, DMA_MEM_TO_DEV, |
f62caccd RG |
951 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
952 | if (!desc_tx) | |
99f1cf1c | 953 | return -EINVAL; |
f62caccd RG |
954 | |
955 | desc_tx->callback = spi_imx_dma_tx_callback; | |
956 | desc_tx->callback_param = (void *)spi_imx; | |
957 | dmaengine_submit(desc_tx); | |
958 | } | |
959 | ||
960 | if (rx) { | |
961 | desc_rx = dmaengine_prep_slave_sg(master->dma_rx, | |
e8361f70 | 962 | rx->sgl, rx->nents, DMA_DEV_TO_MEM, |
f62caccd | 963 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
99f1cf1c SH |
964 | if (!desc_rx) { |
965 | dmaengine_terminate_all(master->dma_tx); | |
966 | return -EINVAL; | |
967 | } | |
f62caccd RG |
968 | |
969 | desc_rx->callback = spi_imx_dma_rx_callback; | |
970 | desc_rx->callback_param = (void *)spi_imx; | |
971 | dmaengine_submit(desc_rx); | |
972 | } | |
973 | ||
974 | reinit_completion(&spi_imx->dma_rx_completion); | |
975 | reinit_completion(&spi_imx->dma_tx_completion); | |
976 | ||
977 | /* Trigger the cspi module. */ | |
978 | spi_imx->dma_finished = 0; | |
979 | ||
fab44ef1 AB |
980 | /* |
981 | * Set these order to avoid potential RX overflow. The overflow may | |
982 | * happen if we enable SPI HW before starting RX DMA due to rescheduling | |
983 | * for another task and/or interrupt. | |
984 | * So RX DMA enabled first to make sure data would be read out from FIFO | |
985 | * ASAP. TX DMA enabled next to start filling TX FIFO with new data. | |
986 | * And finaly SPI HW enabled to start actual data transfer. | |
987 | */ | |
988 | dma_async_issue_pending(master->dma_rx); | |
989 | dma_async_issue_pending(master->dma_tx); | |
f62caccd RG |
990 | spi_imx->devtype_data->trigger(spi_imx); |
991 | ||
4bfe927a AB |
992 | transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); |
993 | ||
f62caccd | 994 | /* Wait SDMA to finish the data transfer.*/ |
56536a7f | 995 | timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion, |
4bfe927a | 996 | transfer_timeout); |
56536a7f | 997 | if (!timeout) { |
6aa800ca | 998 | dev_err(spi_imx->dev, "I/O Error in DMA TX\n"); |
f62caccd | 999 | dmaengine_terminate_all(master->dma_tx); |
e47b33c0 | 1000 | dmaengine_terminate_all(master->dma_rx); |
f62caccd | 1001 | } else { |
56536a7f | 1002 | timeout = wait_for_completion_timeout( |
4bfe927a | 1003 | &spi_imx->dma_rx_completion, transfer_timeout); |
56536a7f | 1004 | if (!timeout) { |
6aa800ca | 1005 | dev_err(spi_imx->dev, "I/O Error in DMA RX\n"); |
f62caccd RG |
1006 | spi_imx->devtype_data->reset(spi_imx); |
1007 | dmaengine_terminate_all(master->dma_rx); | |
1008 | } | |
f62caccd RG |
1009 | } |
1010 | ||
1011 | spi_imx->dma_finished = 1; | |
1012 | spi_imx->devtype_data->trigger(spi_imx); | |
1013 | ||
56536a7f | 1014 | if (!timeout) |
f62caccd | 1015 | ret = -ETIMEDOUT; |
56536a7f | 1016 | else |
f62caccd RG |
1017 | ret = transfer->len; |
1018 | ||
1019 | return ret; | |
f62caccd RG |
1020 | } |
1021 | ||
1022 | static int spi_imx_pio_transfer(struct spi_device *spi, | |
b5f3294f SH |
1023 | struct spi_transfer *transfer) |
1024 | { | |
6cdeb002 | 1025 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
b5f3294f | 1026 | |
6cdeb002 UKK |
1027 | spi_imx->tx_buf = transfer->tx_buf; |
1028 | spi_imx->rx_buf = transfer->rx_buf; | |
1029 | spi_imx->count = transfer->len; | |
1030 | spi_imx->txfifo = 0; | |
b5f3294f | 1031 | |
aa0fe826 | 1032 | reinit_completion(&spi_imx->xfer_done); |
b5f3294f | 1033 | |
6cdeb002 | 1034 | spi_imx_push(spi_imx); |
b5f3294f | 1035 | |
edd501bb | 1036 | spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); |
b5f3294f | 1037 | |
6cdeb002 | 1038 | wait_for_completion(&spi_imx->xfer_done); |
b5f3294f SH |
1039 | |
1040 | return transfer->len; | |
1041 | } | |
1042 | ||
f62caccd RG |
1043 | static int spi_imx_transfer(struct spi_device *spi, |
1044 | struct spi_transfer *transfer) | |
1045 | { | |
f62caccd RG |
1046 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
1047 | ||
c008a800 | 1048 | if (spi_imx->usedma) |
99f1cf1c | 1049 | return spi_imx_dma_transfer(spi_imx, transfer); |
c008a800 SH |
1050 | else |
1051 | return spi_imx_pio_transfer(spi, transfer); | |
f62caccd RG |
1052 | } |
1053 | ||
6cdeb002 | 1054 | static int spi_imx_setup(struct spi_device *spi) |
b5f3294f | 1055 | { |
6c23e5d4 SH |
1056 | struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); |
1057 | int gpio = spi_imx->chipselect[spi->chip_select]; | |
1058 | ||
f4d4ecfe | 1059 | dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, |
b5f3294f SH |
1060 | spi->mode, spi->bits_per_word, spi->max_speed_hz); |
1061 | ||
8b17e055 | 1062 | if (gpio_is_valid(gpio)) |
6c23e5d4 SH |
1063 | gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1); |
1064 | ||
6cdeb002 | 1065 | spi_imx_chipselect(spi, BITBANG_CS_INACTIVE); |
b5f3294f SH |
1066 | |
1067 | return 0; | |
1068 | } | |
1069 | ||
6cdeb002 | 1070 | static void spi_imx_cleanup(struct spi_device *spi) |
b5f3294f SH |
1071 | { |
1072 | } | |
1073 | ||
9e556dcc HS |
1074 | static int |
1075 | spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg) | |
1076 | { | |
1077 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); | |
1078 | int ret; | |
1079 | ||
1080 | ret = clk_enable(spi_imx->clk_per); | |
1081 | if (ret) | |
1082 | return ret; | |
1083 | ||
1084 | ret = clk_enable(spi_imx->clk_ipg); | |
1085 | if (ret) { | |
1086 | clk_disable(spi_imx->clk_per); | |
1087 | return ret; | |
1088 | } | |
1089 | ||
1090 | return 0; | |
1091 | } | |
1092 | ||
1093 | static int | |
1094 | spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg) | |
1095 | { | |
1096 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); | |
1097 | ||
1098 | clk_disable(spi_imx->clk_ipg); | |
1099 | clk_disable(spi_imx->clk_per); | |
1100 | return 0; | |
1101 | } | |
1102 | ||
fd4a319b | 1103 | static int spi_imx_probe(struct platform_device *pdev) |
b5f3294f | 1104 | { |
22a85e4c SG |
1105 | struct device_node *np = pdev->dev.of_node; |
1106 | const struct of_device_id *of_id = | |
1107 | of_match_device(spi_imx_dt_ids, &pdev->dev); | |
1108 | struct spi_imx_master *mxc_platform_info = | |
1109 | dev_get_platdata(&pdev->dev); | |
b5f3294f | 1110 | struct spi_master *master; |
6cdeb002 | 1111 | struct spi_imx_data *spi_imx; |
b5f3294f | 1112 | struct resource *res; |
4b5d6aad | 1113 | int i, ret, num_cs, irq; |
b5f3294f | 1114 | |
22a85e4c | 1115 | if (!np && !mxc_platform_info) { |
b5f3294f SH |
1116 | dev_err(&pdev->dev, "can't get the platform data\n"); |
1117 | return -EINVAL; | |
1118 | } | |
1119 | ||
22a85e4c | 1120 | ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs); |
39ec0d38 LW |
1121 | if (ret < 0) { |
1122 | if (mxc_platform_info) | |
1123 | num_cs = mxc_platform_info->num_chipselect; | |
1124 | else | |
1125 | return ret; | |
1126 | } | |
22a85e4c | 1127 | |
c2387cb9 SG |
1128 | master = spi_alloc_master(&pdev->dev, |
1129 | sizeof(struct spi_imx_data) + sizeof(int) * num_cs); | |
b5f3294f SH |
1130 | if (!master) |
1131 | return -ENOMEM; | |
1132 | ||
1133 | platform_set_drvdata(pdev, master); | |
1134 | ||
24778be2 | 1135 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); |
b5f3294f | 1136 | master->bus_num = pdev->id; |
c2387cb9 | 1137 | master->num_chipselect = num_cs; |
b5f3294f | 1138 | |
6cdeb002 | 1139 | spi_imx = spi_master_get_devdata(master); |
94c69f76 | 1140 | spi_imx->bitbang.master = master; |
6aa800ca | 1141 | spi_imx->dev = &pdev->dev; |
b5f3294f | 1142 | |
4686d1c3 AB |
1143 | spi_imx->devtype_data = of_id ? of_id->data : |
1144 | (struct spi_imx_devtype_data *)pdev->id_entry->driver_data; | |
1145 | ||
b5f3294f | 1146 | for (i = 0; i < master->num_chipselect; i++) { |
22a85e4c | 1147 | int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); |
8b17e055 | 1148 | if (!gpio_is_valid(cs_gpio) && mxc_platform_info) |
22a85e4c | 1149 | cs_gpio = mxc_platform_info->chipselect[i]; |
4cc122ac FE |
1150 | |
1151 | spi_imx->chipselect[i] = cs_gpio; | |
8b17e055 | 1152 | if (!gpio_is_valid(cs_gpio)) |
b5f3294f | 1153 | continue; |
4cc122ac | 1154 | |
130b82c0 FE |
1155 | ret = devm_gpio_request(&pdev->dev, spi_imx->chipselect[i], |
1156 | DRIVER_NAME); | |
b5f3294f | 1157 | if (ret) { |
bbd050af | 1158 | dev_err(&pdev->dev, "can't get cs gpios\n"); |
130b82c0 | 1159 | goto out_master_put; |
b5f3294f | 1160 | } |
b5f3294f SH |
1161 | } |
1162 | ||
6cdeb002 UKK |
1163 | spi_imx->bitbang.chipselect = spi_imx_chipselect; |
1164 | spi_imx->bitbang.setup_transfer = spi_imx_setupxfer; | |
1165 | spi_imx->bitbang.txrx_bufs = spi_imx_transfer; | |
1166 | spi_imx->bitbang.master->setup = spi_imx_setup; | |
1167 | spi_imx->bitbang.master->cleanup = spi_imx_cleanup; | |
9e556dcc HS |
1168 | spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message; |
1169 | spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message; | |
4686d1c3 AB |
1170 | spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
1171 | if (is_imx51_ecspi(spi_imx)) | |
1172 | spi_imx->bitbang.master->mode_bits |= SPI_LOOP; | |
b5f3294f | 1173 | |
6cdeb002 | 1174 | init_completion(&spi_imx->xfer_done); |
b5f3294f SH |
1175 | |
1176 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
130b82c0 FE |
1177 | spi_imx->base = devm_ioremap_resource(&pdev->dev, res); |
1178 | if (IS_ERR(spi_imx->base)) { | |
1179 | ret = PTR_ERR(spi_imx->base); | |
1180 | goto out_master_put; | |
b5f3294f SH |
1181 | } |
1182 | ||
4b5d6aad FE |
1183 | irq = platform_get_irq(pdev, 0); |
1184 | if (irq < 0) { | |
1185 | ret = irq; | |
130b82c0 | 1186 | goto out_master_put; |
b5f3294f SH |
1187 | } |
1188 | ||
4b5d6aad | 1189 | ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0, |
8fc39b51 | 1190 | dev_name(&pdev->dev), spi_imx); |
b5f3294f | 1191 | if (ret) { |
4b5d6aad | 1192 | dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); |
130b82c0 | 1193 | goto out_master_put; |
b5f3294f SH |
1194 | } |
1195 | ||
aa29d840 SH |
1196 | spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
1197 | if (IS_ERR(spi_imx->clk_ipg)) { | |
1198 | ret = PTR_ERR(spi_imx->clk_ipg); | |
130b82c0 | 1199 | goto out_master_put; |
b5f3294f SH |
1200 | } |
1201 | ||
aa29d840 SH |
1202 | spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); |
1203 | if (IS_ERR(spi_imx->clk_per)) { | |
1204 | ret = PTR_ERR(spi_imx->clk_per); | |
130b82c0 | 1205 | goto out_master_put; |
aa29d840 SH |
1206 | } |
1207 | ||
83174626 FE |
1208 | ret = clk_prepare_enable(spi_imx->clk_per); |
1209 | if (ret) | |
1210 | goto out_master_put; | |
1211 | ||
1212 | ret = clk_prepare_enable(spi_imx->clk_ipg); | |
1213 | if (ret) | |
1214 | goto out_put_per; | |
aa29d840 SH |
1215 | |
1216 | spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); | |
f62caccd RG |
1217 | /* |
1218 | * Only validated on i.mx6 now, can remove the constrain if validated on | |
1219 | * other chips. | |
1220 | */ | |
3760047a AB |
1221 | if (is_imx51_ecspi(spi_imx)) { |
1222 | ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master, res); | |
bf9af08c AB |
1223 | if (ret == -EPROBE_DEFER) |
1224 | goto out_clk_put; | |
1225 | ||
3760047a AB |
1226 | if (ret < 0) |
1227 | dev_err(&pdev->dev, "dma setup error %d, use pio\n", | |
1228 | ret); | |
1229 | } | |
b5f3294f | 1230 | |
edd501bb | 1231 | spi_imx->devtype_data->reset(spi_imx); |
ce1807b2 | 1232 | |
edd501bb | 1233 | spi_imx->devtype_data->intctrl(spi_imx, 0); |
b5f3294f | 1234 | |
22a85e4c | 1235 | master->dev.of_node = pdev->dev.of_node; |
6cdeb002 | 1236 | ret = spi_bitbang_start(&spi_imx->bitbang); |
b5f3294f SH |
1237 | if (ret) { |
1238 | dev_err(&pdev->dev, "bitbang start failed with %d\n", ret); | |
1239 | goto out_clk_put; | |
1240 | } | |
1241 | ||
1242 | dev_info(&pdev->dev, "probed\n"); | |
1243 | ||
9e556dcc HS |
1244 | clk_disable(spi_imx->clk_ipg); |
1245 | clk_disable(spi_imx->clk_per); | |
b5f3294f SH |
1246 | return ret; |
1247 | ||
1248 | out_clk_put: | |
aa29d840 | 1249 | clk_disable_unprepare(spi_imx->clk_ipg); |
83174626 FE |
1250 | out_put_per: |
1251 | clk_disable_unprepare(spi_imx->clk_per); | |
130b82c0 | 1252 | out_master_put: |
b5f3294f | 1253 | spi_master_put(master); |
130b82c0 | 1254 | |
b5f3294f SH |
1255 | return ret; |
1256 | } | |
1257 | ||
fd4a319b | 1258 | static int spi_imx_remove(struct platform_device *pdev) |
b5f3294f SH |
1259 | { |
1260 | struct spi_master *master = platform_get_drvdata(pdev); | |
6cdeb002 | 1261 | struct spi_imx_data *spi_imx = spi_master_get_devdata(master); |
b5f3294f | 1262 | |
6cdeb002 | 1263 | spi_bitbang_stop(&spi_imx->bitbang); |
b5f3294f | 1264 | |
6cdeb002 | 1265 | writel(0, spi_imx->base + MXC_CSPICTRL); |
fd40dccb PDM |
1266 | clk_unprepare(spi_imx->clk_ipg); |
1267 | clk_unprepare(spi_imx->clk_per); | |
f62caccd | 1268 | spi_imx_sdma_exit(spi_imx); |
b5f3294f SH |
1269 | spi_master_put(master); |
1270 | ||
b5f3294f SH |
1271 | return 0; |
1272 | } | |
1273 | ||
6cdeb002 | 1274 | static struct platform_driver spi_imx_driver = { |
b5f3294f SH |
1275 | .driver = { |
1276 | .name = DRIVER_NAME, | |
22a85e4c | 1277 | .of_match_table = spi_imx_dt_ids, |
b5f3294f | 1278 | }, |
f4ba6315 | 1279 | .id_table = spi_imx_devtype, |
6cdeb002 | 1280 | .probe = spi_imx_probe, |
fd4a319b | 1281 | .remove = spi_imx_remove, |
b5f3294f | 1282 | }; |
940ab889 | 1283 | module_platform_driver(spi_imx_driver); |
b5f3294f SH |
1284 | |
1285 | MODULE_DESCRIPTION("SPI Master Controller driver"); | |
1286 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); | |
1287 | MODULE_LICENSE("GPL"); | |
3133fba3 | 1288 | MODULE_ALIAS("platform:" DRIVER_NAME); |