Fix common misspellings
[deliverable/linux.git] / drivers / staging / comedi / drivers / ni_at_a2150.c
CommitLineData
01b0a258
FMH
1/*
2 comedi/drivers/ni_at_a2150.c
3 Driver for National Instruments AT-A2150 boards
4 Copyright (C) 2001, 2002 Frank Mori Hess <fmhess@users.sourceforge.net>
5
6 COMEDI - Linux Control and Measurement Device Interface
7 Copyright (C) 2000 David A. Schleef <ds@schleef.org>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22
23************************************************************************
24*/
25/*
26Driver: ni_at_a2150
27Description: National Instruments AT-A2150
28Author: Frank Mori Hess
29Status: works
30Devices: [National Instruments] AT-A2150C (at_a2150c), AT-2150S (at_a2150s)
31
32If you want to ac couple the board's inputs, use AREF_OTHER.
33
34Configuration options:
35 [0] - I/O port base address
36 [1] - IRQ (optional, required for timed conversions)
37 [2] - DMA (optional, required for timed conversions)
38
39*/
40/*
41Yet another driver for obsolete hardware brought to you by Frank Hess.
42Testing and debugging help provided by Dave Andruczyk.
43
44This driver supports the boards:
45
46AT-A2150C
47AT-A2150S
48
49The only difference is their master clock frequencies.
50
51Options:
52 [0] - base io address
53 [1] - irq
54 [2] - dma channel
55
56References (from ftp://ftp.natinst.com/support/manuals):
57
58 320360.pdf AT-A2150 User Manual
59
60TODO:
61
62analog level triggering
63TRIG_WAKE_EOS
64
65*/
66
25436dc9 67#include <linux/interrupt.h>
5a0e3ad6 68#include <linux/slab.h>
01b0a258
FMH
69#include "../comedidev.h"
70
71#include <linux/ioport.h>
72#include <asm/dma.h>
73
74#include "8253.h"
75#include "comedi_fc.h"
76
77#define A2150_SIZE 28
30c687c1 78#define A2150_DMA_BUFFER_SIZE 0xff00 /* size in bytes of dma buffer */
01b0a258 79
30c687c1
BP
80/* #define A2150_DEBUG enable debugging code */
81#undef A2150_DEBUG /* disable debugging code */
01b0a258
FMH
82
83/* Registers and bits */
84#define CONFIG_REG 0x0
85#define CHANNEL_BITS(x) ((x) & 0x7)
86#define CHANNEL_MASK 0x7
87#define CLOCK_SELECT_BITS(x) (((x) & 0x3) << 3)
88#define CLOCK_DIVISOR_BITS(x) (((x) & 0x3) << 5)
89#define CLOCK_MASK (0xf << 3)
30c687c1
BP
90#define ENABLE0_BIT 0x80 /* enable (don't internally ground) channels 0 and 1 */
91#define ENABLE1_BIT 0x100 /* enable (don't internally ground) channels 2 and 3 */
92#define AC0_BIT 0x200 /* ac couple channels 0,1 */
93#define AC1_BIT 0x400 /* ac couple channels 2,3 */
94#define APD_BIT 0x800 /* analog power down */
95#define DPD_BIT 0x1000 /* digital power down */
96#define TRIGGER_REG 0x2 /* trigger config register */
01b0a258
FMH
97#define POST_TRIGGER_BITS 0x2
98#define DELAY_TRIGGER_BITS 0x3
30c687c1
BP
99#define HW_TRIG_EN 0x10 /* enable hardware trigger */
100#define FIFO_START_REG 0x6 /* software start aquistion trigger */
101#define FIFO_RESET_REG 0x8 /* clears fifo + fifo flags */
102#define FIFO_DATA_REG 0xa /* read data */
103#define DMA_TC_CLEAR_REG 0xe /* clear dma terminal count interrupt */
104#define STATUS_REG 0x12 /* read only */
105#define FNE_BIT 0x1 /* fifo not empty */
106#define OVFL_BIT 0x8 /* fifo overflow */
25985edc 107#define EDAQ_BIT 0x10 /* end of acquisition interrupt */
30c687c1 108#define DCAL_BIT 0x20 /* offset calibration in progress */
25985edc
LDM
109#define INTR_BIT 0x40 /* interrupt has occurred */
110#define DMA_TC_BIT 0x80 /* dma terminal count interrupt has occurred */
01b0a258 111#define ID_BITS(x) (((x) >> 8) & 0x3)
30c687c1
BP
112#define IRQ_DMA_CNTRL_REG 0x12 /* write only */
113#define DMA_CHAN_BITS(x) ((x) & 0x7) /* sets dma channel */
114#define DMA_EN_BIT 0x8 /* enables dma */
115#define IRQ_LVL_BITS(x) (((x) & 0xf) << 4) /* sets irq level */
116#define FIFO_INTR_EN_BIT 0x100 /* enable fifo interrupts */
117#define FIFO_INTR_FHF_BIT 0x200 /* interrupt fifo half full */
118#define DMA_INTR_EN_BIT 0x800 /* enable interrupt on dma terminal count */
119#define DMA_DEM_EN_BIT 0x1000 /* enables demand mode dma */
01b0a258
FMH
120#define I8253_BASE_REG 0x14
121#define I8253_MODE_REG 0x17
30c687c1 122#define HW_COUNT_DISABLE 0x30 /* disable hardware counting of conversions */
01b0a258 123
92b635c5 124struct a2150_board {
01b0a258 125 const char *name;
30c687c1
BP
126 int clock[4]; /* master clock periods, in nanoseconds */
127 int num_clocks; /* number of available master clock speeds */
128 int ai_speed; /* maximum conversion rate in nanoseconds */
92b635c5 129};
01b0a258 130
30c687c1 131/* analog input range */
9ced1de6 132static const struct comedi_lrange range_a2150 = {
01b0a258
FMH
133 1,
134 {
0a85b6f0
MT
135 RANGE(-2.828, 2.828),
136 }
01b0a258
FMH
137};
138
30c687c1 139/* enum must match board indices */
01b0a258 140enum { a2150_c, a2150_s };
92b635c5 141static const struct a2150_board a2150_boards[] = {
01b0a258 142 {
0a85b6f0
MT
143 .name = "at-a2150c",
144 .clock = {31250, 22676, 20833, 19531},
145 .num_clocks = 4,
146 .ai_speed = 19531,
147 },
01b0a258 148 {
0a85b6f0
MT
149 .name = "at-a2150s",
150 .clock = {62500, 50000, 41667, 0},
151 .num_clocks = 3,
152 .ai_speed = 41667,
153 },
01b0a258
FMH
154};
155
156/*
157 * Useful for shorthand access to the particular board structure
158 */
92b635c5 159#define thisboard ((const struct a2150_board *)dev->board_ptr)
01b0a258 160
3cc3872b
BP
161struct a2150_private {
162
01b0a258 163 volatile unsigned int count; /* number of data points left to be taken */
30c687c1
BP
164 unsigned int dma; /* dma channel */
165 s16 *dma_buffer; /* dma buffer */
166 unsigned int dma_transfer_size; /* size in bytes of dma transfers */
167 int irq_dma_bits; /* irq/dma register bits */
168 int config_bits; /* config register bits */
3cc3872b
BP
169};
170
3cc3872b 171#define devpriv ((struct a2150_private *)dev->private)
01b0a258 172
da91b269
BP
173static int a2150_attach(struct comedi_device *dev, struct comedi_devconfig *it);
174static int a2150_detach(struct comedi_device *dev);
175static int a2150_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
01b0a258 176
139dfbdf 177static struct comedi_driver driver_a2150 = {
68c3dbff
BP
178 .driver_name = "ni_at_a2150",
179 .module = THIS_MODULE,
180 .attach = a2150_attach,
181 .detach = a2150_detach,
01b0a258
FMH
182};
183
70265d24 184static irqreturn_t a2150_interrupt(int irq, void *d);
0a85b6f0
MT
185static int a2150_ai_cmdtest(struct comedi_device *dev,
186 struct comedi_subdevice *s, struct comedi_cmd *cmd);
814900c9
BP
187static int a2150_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
188static int a2150_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 189 struct comedi_insn *insn, unsigned int *data);
814900c9 190static int a2150_get_timing(struct comedi_device *dev, unsigned int *period,
0a85b6f0 191 int flags);
814900c9 192static int a2150_probe(struct comedi_device *dev);
0a85b6f0
MT
193static int a2150_set_chanlist(struct comedi_device *dev,
194 unsigned int start_channel,
195 unsigned int num_channels);
01b0a258
FMH
196/*
197 * A convenient macro that defines init_module() and cleanup_module(),
198 * as necessary.
199 */
7114a280
AT
200static int __init driver_a2150_init_module(void)
201{
202 return comedi_driver_register(&driver_a2150);
203}
204
205static void __exit driver_a2150_cleanup_module(void)
206{
207 comedi_driver_unregister(&driver_a2150);
208}
209
210module_init(driver_a2150_init_module);
211module_exit(driver_a2150_cleanup_module);
01b0a258
FMH
212
213#ifdef A2150_DEBUG
214
da91b269 215static void ni_dump_regs(struct comedi_device *dev)
01b0a258 216{
5f74ea14
GKH
217 printk("config bits 0x%x\n", devpriv->config_bits);
218 printk("irq dma bits 0x%x\n", devpriv->irq_dma_bits);
219 printk("status bits 0x%x\n", inw(dev->iobase + STATUS_REG));
01b0a258
FMH
220}
221
222#endif
223
224/* interrupt service routine */
70265d24 225static irqreturn_t a2150_interrupt(int irq, void *d)
01b0a258
FMH
226{
227 int i;
228 int status;
229 unsigned long flags;
71b5f4f1 230 struct comedi_device *dev = d;
34c43922 231 struct comedi_subdevice *s = dev->read_subdev;
d163679c 232 struct comedi_async *async;
ea6d0d4c 233 struct comedi_cmd *cmd;
01b0a258 234 unsigned int max_points, num_points, residue, leftover;
790c5541 235 short dpnt;
01b0a258
FMH
236 static const int sample_size = sizeof(devpriv->dma_buffer[0]);
237
238 if (dev->attached == 0) {
239 comedi_error(dev, "premature interrupt");
240 return IRQ_HANDLED;
241 }
30c687c1 242 /* initialize async here to make sure s is not NULL */
01b0a258
FMH
243 async = s->async;
244 async->events = 0;
245 cmd = &async->cmd;
246
247 status = inw(dev->iobase + STATUS_REG);
248
249 if ((status & INTR_BIT) == 0) {
250 comedi_error(dev, "spurious interrupt");
251 return IRQ_NONE;
252 }
253
254 if (status & OVFL_BIT) {
255 comedi_error(dev, "fifo overflow");
256 a2150_cancel(dev, s);
257 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
258 }
259
260 if ((status & DMA_TC_BIT) == 0) {
261 comedi_error(dev, "caught non-dma interrupt? Aborting.");
262 a2150_cancel(dev, s);
263 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
264 comedi_event(dev, s);
265 return IRQ_HANDLED;
266 }
267
268 flags = claim_dma_lock();
269 disable_dma(devpriv->dma);
270 /* clear flip-flop to make sure 2-byte registers for
271 * count and address get set correctly */
272 clear_dma_ff(devpriv->dma);
273
30c687c1 274 /* figure out how many points to read */
01b0a258
FMH
275 max_points = devpriv->dma_transfer_size / sample_size;
276 /* residue is the number of points left to be done on the dma
277 * transfer. It should always be zero at this point unless
278 * the stop_src is set to external triggering.
279 */
280 residue = get_dma_residue(devpriv->dma) / sample_size;
281 num_points = max_points - residue;
282 if (devpriv->count < num_points && cmd->stop_src == TRIG_COUNT)
283 num_points = devpriv->count;
284
30c687c1 285 /* figure out how many points will be stored next time */
01b0a258
FMH
286 leftover = 0;
287 if (cmd->stop_src == TRIG_NONE) {
288 leftover = devpriv->dma_transfer_size / sample_size;
289 } else if (devpriv->count > max_points) {
290 leftover = devpriv->count - max_points;
291 if (leftover > max_points)
292 leftover = max_points;
293 }
294 /* there should only be a residue if collection was stopped by having
295 * the stop_src set to an external trigger, in which case there
296 * will be no more data
297 */
298 if (residue)
299 leftover = 0;
300
301 for (i = 0; i < num_points; i++) {
302 /* write data point to comedi buffer */
303 dpnt = devpriv->dma_buffer[i];
30c687c1 304 /* convert from 2's complement to unsigned coding */
01b0a258
FMH
305 dpnt ^= 0x8000;
306 cfc_write_to_buffer(s, dpnt);
307 if (cmd->stop_src == TRIG_COUNT) {
308 if (--devpriv->count == 0) { /* end of acquisition */
309 a2150_cancel(dev, s);
310 async->events |= COMEDI_CB_EOA;
311 break;
312 }
313 }
314 }
30c687c1 315 /* re-enable dma */
01b0a258
FMH
316 if (leftover) {
317 set_dma_addr(devpriv->dma, virt_to_bus(devpriv->dma_buffer));
318 set_dma_count(devpriv->dma, leftover * sample_size);
319 enable_dma(devpriv->dma);
320 }
321 release_dma_lock(flags);
322
323 async->events |= COMEDI_CB_BLOCK;
324
325 comedi_event(dev, s);
326
327 /* clear interrupt */
328 outw(0x00, dev->iobase + DMA_TC_CLEAR_REG);
329
330 return IRQ_HANDLED;
331}
332
30c687c1 333/* probes board type, returns offset */
da91b269 334static int a2150_probe(struct comedi_device *dev)
01b0a258
FMH
335{
336 int status = inw(dev->iobase + STATUS_REG);
337 return ID_BITS(status);
338}
339
da91b269 340static int a2150_attach(struct comedi_device *dev, struct comedi_devconfig *it)
01b0a258 341{
34c43922 342 struct comedi_subdevice *s;
01b0a258
FMH
343 unsigned long iobase = it->options[0];
344 unsigned int irq = it->options[1];
345 unsigned int dma = it->options[2];
346 static const int timeout = 2000;
347 int i;
348
349 printk("comedi%d: %s: io 0x%lx", dev->minor, driver_a2150.driver_name,
0a85b6f0 350 iobase);
01b0a258
FMH
351 if (irq) {
352 printk(", irq %u", irq);
353 } else {
354 printk(", no irq");
355 }
356 if (dma) {
357 printk(", dma %u", dma);
358 } else {
359 printk(", no dma");
360 }
361 printk("\n");
362
363 /* allocate and initialize dev->private */
3cc3872b 364 if (alloc_private(dev, sizeof(struct a2150_private)) < 0)
01b0a258
FMH
365 return -ENOMEM;
366
367 if (iobase == 0) {
368 printk(" io base address required\n");
369 return -EINVAL;
370 }
371
372 /* check if io addresses are available */
373 if (!request_region(iobase, A2150_SIZE, driver_a2150.driver_name)) {
374 printk(" I/O port conflict\n");
375 return -EIO;
376 }
377 dev->iobase = iobase;
378
379 /* grab our IRQ */
380 if (irq) {
30c687c1 381 /* check that irq is supported */
01b0a258
FMH
382 if (irq < 3 || irq == 8 || irq == 13 || irq > 15) {
383 printk(" invalid irq line %u\n", irq);
384 return -EINVAL;
385 }
5f74ea14 386 if (request_irq(irq, a2150_interrupt, 0,
01b0a258
FMH
387 driver_a2150.driver_name, dev)) {
388 printk("unable to allocate irq %u\n", irq);
389 return -EINVAL;
390 }
391 devpriv->irq_dma_bits |= IRQ_LVL_BITS(irq);
392 dev->irq = irq;
393 }
30c687c1 394 /* initialize dma */
01b0a258
FMH
395 if (dma) {
396 if (dma == 4 || dma > 7) {
397 printk(" invalid dma channel %u\n", dma);
398 return -EINVAL;
399 }
400 if (request_dma(dma, driver_a2150.driver_name)) {
401 printk(" failed to allocate dma channel %u\n", dma);
402 return -EINVAL;
403 }
404 devpriv->dma = dma;
405 devpriv->dma_buffer =
0a85b6f0 406 kmalloc(A2150_DMA_BUFFER_SIZE, GFP_KERNEL | GFP_DMA);
01b0a258
FMH
407 if (devpriv->dma_buffer == NULL)
408 return -ENOMEM;
409
410 disable_dma(dma);
411 set_dma_mode(dma, DMA_MODE_READ);
412
413 devpriv->irq_dma_bits |= DMA_CHAN_BITS(dma);
414 }
415
416 dev->board_ptr = a2150_boards + a2150_probe(dev);
417 dev->board_name = thisboard->name;
418
419 if (alloc_subdevices(dev, 1) < 0)
420 return -ENOMEM;
421
422 /* analog input subdevice */
423 s = dev->subdevices + 0;
424 dev->read_subdev = s;
425 s->type = COMEDI_SUBD_AI;
426 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_OTHER | SDF_CMD_READ;
427 s->n_chan = 4;
428 s->len_chanlist = 4;
429 s->maxdata = 0xffff;
430 s->range_table = &range_a2150;
431 s->do_cmd = a2150_ai_cmd;
432 s->do_cmdtest = a2150_ai_cmdtest;
433 s->insn_read = a2150_ai_rinsn;
434 s->cancel = a2150_cancel;
435
436 /* need to do this for software counting of completed conversions, to
25985edc 437 * prevent hardware count from stopping acquisition */
01b0a258
FMH
438 outw(HW_COUNT_DISABLE, dev->iobase + I8253_MODE_REG);
439
30c687c1 440 /* set card's irq and dma levels */
01b0a258
FMH
441 outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG);
442
30c687c1 443 /* reset and sync adc clock circuitry */
01b0a258
FMH
444 outw_p(DPD_BIT | APD_BIT, dev->iobase + CONFIG_REG);
445 outw_p(DPD_BIT, dev->iobase + CONFIG_REG);
30c687c1 446 /* initialize configuration register */
01b0a258
FMH
447 devpriv->config_bits = 0;
448 outw(devpriv->config_bits, dev->iobase + CONFIG_REG);
30c687c1 449 /* wait until offset calibration is done, then enable analog inputs */
01b0a258
FMH
450 for (i = 0; i < timeout; i++) {
451 if ((DCAL_BIT & inw(dev->iobase + STATUS_REG)) == 0)
452 break;
5f74ea14 453 udelay(1000);
01b0a258
FMH
454 }
455 if (i == timeout) {
0a85b6f0
MT
456 printk
457 (" timed out waiting for offset calibration to complete\n");
01b0a258
FMH
458 return -ETIME;
459 }
460 devpriv->config_bits |= ENABLE0_BIT | ENABLE1_BIT;
461 outw(devpriv->config_bits, dev->iobase + CONFIG_REG);
462
463 return 0;
464};
465
da91b269 466static int a2150_detach(struct comedi_device *dev)
01b0a258
FMH
467{
468 printk("comedi%d: %s: remove\n", dev->minor, driver_a2150.driver_name);
469
470 /* only free stuff if it has been allocated by _attach */
471 if (dev->iobase) {
30c687c1 472 /* put board in power-down mode */
01b0a258
FMH
473 outw(APD_BIT | DPD_BIT, dev->iobase + CONFIG_REG);
474 release_region(dev->iobase, A2150_SIZE);
475 }
476
477 if (dev->irq)
5f74ea14 478 free_irq(dev->irq, dev);
01b0a258
FMH
479 if (devpriv) {
480 if (devpriv->dma)
481 free_dma(devpriv->dma);
e4e1f289 482 kfree(devpriv->dma_buffer);
01b0a258
FMH
483 }
484
485 return 0;
486};
487
da91b269 488static int a2150_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
01b0a258 489{
30c687c1 490 /* disable dma on card */
01b0a258
FMH
491 devpriv->irq_dma_bits &= ~DMA_INTR_EN_BIT & ~DMA_EN_BIT;
492 outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG);
493
30c687c1 494 /* disable computer's dma */
01b0a258
FMH
495 disable_dma(devpriv->dma);
496
30c687c1 497 /* clear fifo and reset triggering circuitry */
01b0a258
FMH
498 outw(0, dev->iobase + FIFO_RESET_REG);
499
500 return 0;
501}
502
0a85b6f0
MT
503static int a2150_ai_cmdtest(struct comedi_device *dev,
504 struct comedi_subdevice *s, struct comedi_cmd *cmd)
01b0a258
FMH
505{
506 int err = 0;
507 int tmp;
508 int startChan;
509 int i;
510
511 /* step 1: make sure trigger sources are trivially valid */
512
513 tmp = cmd->start_src;
514 cmd->start_src &= TRIG_NOW | TRIG_EXT;
515 if (!cmd->start_src || tmp != cmd->start_src)
516 err++;
517
518 tmp = cmd->scan_begin_src;
519 cmd->scan_begin_src &= TRIG_TIMER;
520 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
521 err++;
522
523 tmp = cmd->convert_src;
524 cmd->convert_src &= TRIG_NOW;
525 if (!cmd->convert_src || tmp != cmd->convert_src)
526 err++;
527
528 tmp = cmd->scan_end_src;
529 cmd->scan_end_src &= TRIG_COUNT;
530 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
531 err++;
532
533 tmp = cmd->stop_src;
534 cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
535 if (!cmd->stop_src || tmp != cmd->stop_src)
536 err++;
537
538 if (err)
539 return 1;
540
541 /* step 2: make sure trigger sources are unique and mutually compatible */
542
543 if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT)
544 err++;
545 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
546 err++;
547
548 if (err)
549 return 2;
550
551 /* step 3: make sure arguments are trivially compatible */
552
553 if (cmd->start_arg != 0) {
554 cmd->start_arg = 0;
555 err++;
556 }
557 if (cmd->convert_src == TRIG_TIMER) {
558 if (cmd->convert_arg < thisboard->ai_speed) {
559 cmd->convert_arg = thisboard->ai_speed;
560 err++;
561 }
562 }
563 if (!cmd->chanlist_len) {
564 cmd->chanlist_len = 1;
565 err++;
566 }
567 if (cmd->scan_end_arg != cmd->chanlist_len) {
568 cmd->scan_end_arg = cmd->chanlist_len;
569 err++;
570 }
571 if (cmd->stop_src == TRIG_COUNT) {
572 if (!cmd->stop_arg) {
573 cmd->stop_arg = 1;
574 err++;
575 }
576 } else { /* TRIG_NONE */
577 if (cmd->stop_arg != 0) {
578 cmd->stop_arg = 0;
579 err++;
580 }
581 }
582
583 if (err)
584 return 3;
585
586 /* step 4: fix up any arguments */
587
588 if (cmd->scan_begin_src == TRIG_TIMER) {
589 tmp = cmd->scan_begin_arg;
590 a2150_get_timing(dev, &cmd->scan_begin_arg, cmd->flags);
591 if (tmp != cmd->scan_begin_arg)
592 err++;
593 }
594
595 if (err)
596 return 4;
597
30c687c1 598 /* check channel/gain list against card's limitations */
01b0a258
FMH
599 if (cmd->chanlist) {
600 startChan = CR_CHAN(cmd->chanlist[0]);
601 for (i = 1; i < cmd->chanlist_len; i++) {
602 if (CR_CHAN(cmd->chanlist[i]) != (startChan + i)) {
603 comedi_error(dev,
0a85b6f0 604 "entries in chanlist must be consecutive channels, counting upwards\n");
01b0a258
FMH
605 err++;
606 }
607 }
608 if (cmd->chanlist_len == 2 && CR_CHAN(cmd->chanlist[0]) == 1) {
609 comedi_error(dev,
0a85b6f0 610 "length 2 chanlist must be channels 0,1 or channels 2,3");
01b0a258
FMH
611 err++;
612 }
613 if (cmd->chanlist_len == 3) {
614 comedi_error(dev,
0a85b6f0 615 "chanlist must have 1,2 or 4 channels");
01b0a258
FMH
616 err++;
617 }
618 if (CR_AREF(cmd->chanlist[0]) != CR_AREF(cmd->chanlist[1]) ||
0a85b6f0 619 CR_AREF(cmd->chanlist[2]) != CR_AREF(cmd->chanlist[3])) {
01b0a258 620 comedi_error(dev,
0a85b6f0 621 "channels 0/1 and 2/3 must have the same analog reference");
01b0a258
FMH
622 err++;
623 }
624 }
625
626 if (err)
627 return 5;
628
629 return 0;
630}
631
da91b269 632static int a2150_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
01b0a258 633{
d163679c 634 struct comedi_async *async = s->async;
ea6d0d4c 635 struct comedi_cmd *cmd = &async->cmd;
01b0a258
FMH
636 unsigned long lock_flags;
637 unsigned int old_config_bits = devpriv->config_bits;
638 unsigned int trigger_bits;
639
640 if (!dev->irq || !devpriv->dma) {
641 comedi_error(dev,
0a85b6f0 642 " irq and dma required, cannot do hardware conversions");
01b0a258
FMH
643 return -1;
644 }
645 if (cmd->flags & TRIG_RT) {
646 comedi_error(dev,
0a85b6f0 647 " dma incompatible with hard real-time interrupt (TRIG_RT), aborting");
01b0a258
FMH
648 return -1;
649 }
30c687c1 650 /* clear fifo and reset triggering circuitry */
01b0a258
FMH
651 outw(0, dev->iobase + FIFO_RESET_REG);
652
653 /* setup chanlist */
654 if (a2150_set_chanlist(dev, CR_CHAN(cmd->chanlist[0]),
0a85b6f0 655 cmd->chanlist_len) < 0)
01b0a258
FMH
656 return -1;
657
30c687c1 658 /* setup ac/dc coupling */
01b0a258
FMH
659 if (CR_AREF(cmd->chanlist[0]) == AREF_OTHER)
660 devpriv->config_bits |= AC0_BIT;
661 else
662 devpriv->config_bits &= ~AC0_BIT;
663 if (CR_AREF(cmd->chanlist[2]) == AREF_OTHER)
664 devpriv->config_bits |= AC1_BIT;
665 else
666 devpriv->config_bits &= ~AC1_BIT;
667
30c687c1 668 /* setup timing */
01b0a258
FMH
669 a2150_get_timing(dev, &cmd->scan_begin_arg, cmd->flags);
670
30c687c1 671 /* send timing, channel, config bits */
01b0a258
FMH
672 outw(devpriv->config_bits, dev->iobase + CONFIG_REG);
673
30c687c1 674 /* initialize number of samples remaining */
01b0a258
FMH
675 devpriv->count = cmd->stop_arg * cmd->chanlist_len;
676
30c687c1 677 /* enable computer's dma */
01b0a258
FMH
678 lock_flags = claim_dma_lock();
679 disable_dma(devpriv->dma);
680 /* clear flip-flop to make sure 2-byte registers for
681 * count and address get set correctly */
682 clear_dma_ff(devpriv->dma);
683 set_dma_addr(devpriv->dma, virt_to_bus(devpriv->dma_buffer));
30c687c1 684 /* set size of transfer to fill in 1/3 second */
01b0a258
FMH
685#define ONE_THIRD_SECOND 333333333
686 devpriv->dma_transfer_size =
0a85b6f0
MT
687 sizeof(devpriv->dma_buffer[0]) * cmd->chanlist_len *
688 ONE_THIRD_SECOND / cmd->scan_begin_arg;
01b0a258
FMH
689 if (devpriv->dma_transfer_size > A2150_DMA_BUFFER_SIZE)
690 devpriv->dma_transfer_size = A2150_DMA_BUFFER_SIZE;
691 if (devpriv->dma_transfer_size < sizeof(devpriv->dma_buffer[0]))
692 devpriv->dma_transfer_size = sizeof(devpriv->dma_buffer[0]);
693 devpriv->dma_transfer_size -=
0a85b6f0 694 devpriv->dma_transfer_size % sizeof(devpriv->dma_buffer[0]);
01b0a258
FMH
695 set_dma_count(devpriv->dma, devpriv->dma_transfer_size);
696 enable_dma(devpriv->dma);
697 release_dma_lock(lock_flags);
698
699 /* clear dma interrupt before enabling it, to try and get rid of that
700 * one spurious interrupt that has been happening */
701 outw(0x00, dev->iobase + DMA_TC_CLEAR_REG);
702
30c687c1 703 /* enable dma on card */
01b0a258
FMH
704 devpriv->irq_dma_bits |= DMA_INTR_EN_BIT | DMA_EN_BIT;
705 outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG);
706
30c687c1 707 /* may need to wait 72 sampling periods if timing was changed */
01b0a258
FMH
708 i8254_load(dev->iobase + I8253_BASE_REG, 0, 2, 72, 0);
709
30c687c1 710 /* setup start triggering */
01b0a258 711 trigger_bits = 0;
30c687c1 712 /* decide if we need to wait 72 periods for valid data */
01b0a258 713 if (cmd->start_src == TRIG_NOW &&
0a85b6f0
MT
714 (old_config_bits & CLOCK_MASK) !=
715 (devpriv->config_bits & CLOCK_MASK)) {
30c687c1 716 /* set trigger source to delay trigger */
01b0a258
FMH
717 trigger_bits |= DELAY_TRIGGER_BITS;
718 } else {
30c687c1 719 /* otherwise no delay */
01b0a258
FMH
720 trigger_bits |= POST_TRIGGER_BITS;
721 }
30c687c1 722 /* enable external hardware trigger */
01b0a258
FMH
723 if (cmd->start_src == TRIG_EXT) {
724 trigger_bits |= HW_TRIG_EN;
725 } else if (cmd->start_src == TRIG_OTHER) {
30c687c1 726 /* XXX add support for level/slope start trigger using TRIG_OTHER */
01b0a258
FMH
727 comedi_error(dev, "you shouldn't see this?");
728 }
30c687c1 729 /* send trigger config bits */
01b0a258
FMH
730 outw(trigger_bits, dev->iobase + TRIGGER_REG);
731
25985edc 732 /* start acquisition for soft trigger */
01b0a258
FMH
733 if (cmd->start_src == TRIG_NOW) {
734 outw(0, dev->iobase + FIFO_START_REG);
735 }
736#ifdef A2150_DEBUG
737 ni_dump_regs(dev);
738#endif
739
740 return 0;
741}
742
da91b269 743static int a2150_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 744 struct comedi_insn *insn, unsigned int *data)
01b0a258
FMH
745{
746 unsigned int i, n;
747 static const int timeout = 100000;
748 static const int filter_delay = 36;
749
30c687c1 750 /* clear fifo and reset triggering circuitry */
01b0a258
FMH
751 outw(0, dev->iobase + FIFO_RESET_REG);
752
753 /* setup chanlist */
754 if (a2150_set_chanlist(dev, CR_CHAN(insn->chanspec), 1) < 0)
755 return -1;
756
30c687c1 757 /* set dc coupling */
01b0a258
FMH
758 devpriv->config_bits &= ~AC0_BIT;
759 devpriv->config_bits &= ~AC1_BIT;
760
30c687c1 761 /* send timing, channel, config bits */
01b0a258
FMH
762 outw(devpriv->config_bits, dev->iobase + CONFIG_REG);
763
30c687c1 764 /* disable dma on card */
01b0a258
FMH
765 devpriv->irq_dma_bits &= ~DMA_INTR_EN_BIT & ~DMA_EN_BIT;
766 outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG);
767
30c687c1 768 /* setup start triggering */
01b0a258
FMH
769 outw(0, dev->iobase + TRIGGER_REG);
770
25985edc 771 /* start acquisition for soft trigger */
01b0a258
FMH
772 outw(0, dev->iobase + FIFO_START_REG);
773
774 /* there is a 35.6 sample delay for data to get through the antialias filter */
775 for (n = 0; n < filter_delay; n++) {
776 for (i = 0; i < timeout; i++) {
777 if (inw(dev->iobase + STATUS_REG) & FNE_BIT)
778 break;
5f74ea14 779 udelay(1);
01b0a258
FMH
780 }
781 if (i == timeout) {
782 comedi_error(dev, "timeout");
783 return -ETIME;
784 }
785 inw(dev->iobase + FIFO_DATA_REG);
786 }
787
30c687c1 788 /* read data */
01b0a258
FMH
789 for (n = 0; n < insn->n; n++) {
790 for (i = 0; i < timeout; i++) {
791 if (inw(dev->iobase + STATUS_REG) & FNE_BIT)
792 break;
5f74ea14 793 udelay(1);
01b0a258
FMH
794 }
795 if (i == timeout) {
796 comedi_error(dev, "timeout");
797 return -ETIME;
798 }
799#ifdef A2150_DEBUG
800 ni_dump_regs(dev);
801#endif
802 data[n] = inw(dev->iobase + FIFO_DATA_REG);
803#ifdef A2150_DEBUG
5f74ea14 804 printk(" data is %i\n", data[n]);
01b0a258
FMH
805#endif
806 data[n] ^= 0x8000;
807 }
808
30c687c1 809 /* clear fifo and reset triggering circuitry */
01b0a258
FMH
810 outw(0, dev->iobase + FIFO_RESET_REG);
811
812 return n;
813}
814
815/* sets bits in devpriv->clock_bits to nearest approximation of requested period,
816 * adjusts requested period to actual timing. */
da91b269 817static int a2150_get_timing(struct comedi_device *dev, unsigned int *period,
0a85b6f0 818 int flags)
01b0a258
FMH
819{
820 int lub, glb, temp;
821 int lub_divisor_shift, lub_index, glb_divisor_shift, glb_index;
822 int i, j;
823
30c687c1 824 /* initialize greatest lower and least upper bounds */
01b0a258
FMH
825 lub_divisor_shift = 3;
826 lub_index = 0;
827 lub = thisboard->clock[lub_index] * (1 << lub_divisor_shift);
828 glb_divisor_shift = 0;
829 glb_index = thisboard->num_clocks - 1;
830 glb = thisboard->clock[glb_index] * (1 << glb_divisor_shift);
831
30c687c1 832 /* make sure period is in available range */
01b0a258
FMH
833 if (*period < glb)
834 *period = glb;
835 if (*period > lub)
836 *period = lub;
837
30c687c1 838 /* we can multiply period by 1, 2, 4, or 8, using (1 << i) */
01b0a258 839 for (i = 0; i < 4; i++) {
30c687c1 840 /* there are a maximum of 4 master clocks */
01b0a258 841 for (j = 0; j < thisboard->num_clocks; j++) {
30c687c1 842 /* temp is the period in nanosec we are evaluating */
01b0a258 843 temp = thisboard->clock[j] * (1 << i);
30c687c1 844 /* if it is the best match yet */
01b0a258
FMH
845 if (temp < lub && temp >= *period) {
846 lub_divisor_shift = i;
847 lub_index = j;
848 lub = temp;
849 }
850 if (temp > glb && temp <= *period) {
851 glb_divisor_shift = i;
852 glb_index = j;
853 glb = temp;
854 }
855 }
856 }
857 flags &= TRIG_ROUND_MASK;
858 switch (flags) {
859 case TRIG_ROUND_NEAREST:
860 default:
30c687c1 861 /* if least upper bound is better approximation */
01b0a258
FMH
862 if (lub - *period < *period - glb) {
863 *period = lub;
864 } else {
865 *period = glb;
866 }
867 break;
868 case TRIG_ROUND_UP:
869 *period = lub;
870 break;
871 case TRIG_ROUND_DOWN:
872 *period = glb;
873 break;
874 }
875
30c687c1 876 /* set clock bits for config register appropriately */
01b0a258
FMH
877 devpriv->config_bits &= ~CLOCK_MASK;
878 if (*period == lub) {
879 devpriv->config_bits |=
0a85b6f0
MT
880 CLOCK_SELECT_BITS(lub_index) |
881 CLOCK_DIVISOR_BITS(lub_divisor_shift);
01b0a258
FMH
882 } else {
883 devpriv->config_bits |=
0a85b6f0
MT
884 CLOCK_SELECT_BITS(glb_index) |
885 CLOCK_DIVISOR_BITS(glb_divisor_shift);
01b0a258
FMH
886 }
887
888 return 0;
889}
890
0a85b6f0
MT
891static int a2150_set_chanlist(struct comedi_device *dev,
892 unsigned int start_channel,
893 unsigned int num_channels)
01b0a258
FMH
894{
895 if (start_channel + num_channels > 4)
896 return -1;
897
898 devpriv->config_bits &= ~CHANNEL_MASK;
899
900 switch (num_channels) {
901 case 1:
902 devpriv->config_bits |= CHANNEL_BITS(0x4 | start_channel);
903 break;
904 case 2:
905 if (start_channel == 0) {
906 devpriv->config_bits |= CHANNEL_BITS(0x2);
907 } else if (start_channel == 2) {
908 devpriv->config_bits |= CHANNEL_BITS(0x3);
909 } else {
910 return -1;
911 }
912 break;
913 case 4:
914 devpriv->config_bits |= CHANNEL_BITS(0x1);
915 break;
916 default:
917 return -1;
918 break;
919 }
920
921 return 0;
922}
90f703d3
AT
923
924MODULE_AUTHOR("Comedi http://www.comedi.org");
925MODULE_DESCRIPTION("Comedi low-level driver");
926MODULE_LICENSE("GPL");
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