projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 0ff59f31 KH |
1 | /* DMA controller registers */ |
| 2 | #define REG8_1(a0) ((const u16[8]) {a0, a0 + 1, a0 + 2, a0 + 3, \ | |
| 3 | a0 + 4, a0 + 5, a0 + 6, a0 + 7}) | |
| 4 | #define REG8_2(a0) ((const u16[8]) {a0, a0 + 2, a0 + 4, a0 + 6, \ | |
| 5 | a0 + 8, a0 + 0xA, a0 + 0xC, a0 + 0xE}) | |
| 6 | #define REG8_8(a0) ((const u16[8]) {a0, a0 + 8, a0 + 0x10, a0 + 0x18, \ | |
| 7 | a0 + 0x20, a0 + 0x28, a0 + 0x30, a0 + 0x38}) | |
| 8 | #define INT_STATUS 0x00 | |
| 9 | #define PB_STATUS 0x01 | |
| 10 | #define DMA_CMD 0x02 | |
| 11 | #define VIDEO_FIFO_STATUS 0x03 | |
| 12 | #define VIDEO_CHANNEL_ID 0x04 | |
| 13 | #define VIDEO_PARSER_STATUS 0x05 | |
| 14 | #define SYS_SOFT_RST 0x06 | |
| 15 | #define DMA_PAGE_TABLE0_ADDR ((const u16[8]) {0x08, 0xD0, 0xD2, 0xD4, \ | |
| 16 | 0xD6, 0xD8, 0xDA, 0xDC}) | |
| 17 | #define DMA_PAGE_TABLE1_ADDR ((const u16[8]) {0x09, 0xD1, 0xD3, 0xD5, \ | |
| 18 | 0xD7, 0xD9, 0xDB, 0xDD}) | |
| 19 | #define DMA_CHANNEL_ENABLE 0x0A | |
| 20 | #define DMA_CONFIG 0x0B | |
| 21 | #define DMA_TIMER_INTERVAL 0x0C | |
| 22 | #define DMA_CHANNEL_TIMEOUT 0x0D | |
| 23 | #define VDMA_CHANNEL_CONFIG REG8_1(0x10) | |
| 24 | #define ADMA_P_ADDR REG8_2(0x18) | |
| 25 | #define ADMA_B_ADDR REG8_2(0x19) | |
| 26 | #define DMA10_P_ADDR 0x28 /* ??? */ | |
| 27 | #define DMA10_B_ADDR 0x29 | |
| 28 | #define VIDEO_CONTROL1 0x2A | |
| 29 | #define VIDEO_CONTROL2 0x2B | |
| 30 | #define AUDIO_CONTROL1 0x2C | |
| 31 | #define AUDIO_CONTROL2 0x2D | |
| 32 | #define PHASE_REF 0x2E | |
| 33 | #define GPIO_REG 0x2F | |
| 34 | #define INTL_HBAR_CTRL REG8_1(0x30) | |
| 35 | #define AUDIO_CONTROL3 0x38 | |
| 36 | #define VIDEO_FIELD_CTRL REG8_1(0x39) | |
| 37 | #define HSCALER_CTRL REG8_1(0x42) | |
| 38 | #define VIDEO_SIZE REG8_1(0x4A) | |
| 39 | #define VIDEO_SIZE_F2 REG8_1(0x52) | |
| 40 | #define MD_CONF REG8_1(0x60) | |
| 41 | #define MD_INIT REG8_1(0x68) | |
| 42 | #define MD_MAP0 REG8_1(0x70) | |
| 43 | #define VDMA_P_ADDR REG8_8(0x80) /* not used in DMA SG mode */ | |
| 44 | #define VDMA_WHP REG8_8(0x81) | |
| 45 | #define VDMA_B_ADDR REG8_8(0x82) | |
| 46 | #define VDMA_F2_P_ADDR REG8_8(0x84) | |
| 47 | #define VDMA_F2_WHP REG8_8(0x85) | |
| 48 | #define VDMA_F2_B_ADDR REG8_8(0x86) | |
| 49 | #define EP_REG_ADDR 0xFE | |
| 50 | #define EP_REG_DATA 0xFF | |
| 51 | ||
| 52 | /* Video decoder registers */ | |
| 53 | #define VDREG8(a0) ((const u16[8]) { \ | |
| 54 | a0 + 0x000, a0 + 0x010, a0 + 0x020, a0 + 0x030, \ | |
| 55 | a0 + 0x100, a0 + 0x110, a0 + 0x120, a0 + 0x130}) | |
| 56 | #define VIDSTAT VDREG8(0x100) | |
| 57 | #define BRIGHT VDREG8(0x101) | |
| 58 | #define CONTRAST VDREG8(0x102) | |
| 59 | #define SHARPNESS VDREG8(0x103) | |
| 60 | #define SAT_U VDREG8(0x104) | |
| 61 | #define SAT_V VDREG8(0x105) | |
| 62 | #define HUE VDREG8(0x106) | |
| 63 | #define CROP_HI VDREG8(0x107) | |
| 64 | #define VDELAY_LO VDREG8(0x108) | |
| 65 | #define VACTIVE_LO VDREG8(0x109) | |
| 66 | #define HDELAY_LO VDREG8(0x10A) | |
| 67 | #define HACTIVE_LO VDREG8(0x10B) | |
| 68 | #define MVSN VDREG8(0x10C) | |
| 69 | #define STATUS2 VDREG8(0x10C) | |
| 70 | #define SDT VDREG8(0x10E) | |
| 71 | #define SDT_EN VDREG8(0x10F) | |
| 72 | ||
| 73 | #define VSCALE_LO VDREG8(0x144) | |
| 74 | #define SCALE_HI VDREG8(0x145) | |
| 75 | #define HSCALE_LO VDREG8(0x146) | |
| 76 | #define F2CROP_HI VDREG8(0x147) | |
| 77 | #define F2VDELAY_LO VDREG8(0x148) | |
| 78 | #define F2VACTIVE_LO VDREG8(0x149) | |
| 79 | #define F2HDELAY_LO VDREG8(0x14A) | |
| 80 | #define F2HACTIVE_LO VDREG8(0x14B) | |
| 81 | #define F2VSCALE_LO VDREG8(0x14C) | |
| 82 | #define F2SCALE_HI VDREG8(0x14D) | |
| 83 | #define F2HSCALE_LO VDREG8(0x14E) | |
| 84 | #define F2CNT VDREG8(0x14F) | |
| 85 | ||
| 86 | #define VDREG2(a0) ((const u16[2]) {a0, a0 + 0x100}) | |
| 87 | #define SRST VDREG2(0x180) | |
| 88 | #define ACNTL VDREG2(0x181) | |
| 89 | #define ACNTL2 VDREG2(0x182) | |
| 90 | #define CNTRL1 VDREG2(0x183) | |
| 91 | #define CKHY VDREG2(0x184) | |
| 92 | #define SHCOR VDREG2(0x185) | |
| 93 | #define CORING VDREG2(0x186) | |
| 94 | #define CLMPG VDREG2(0x187) | |
| 95 | #define IAGC VDREG2(0x188) | |
| 96 | #define VCTRL1 VDREG2(0x18F) | |
| 97 | #define MISC1 VDREG2(0x194) | |
| 98 | #define LOOP VDREG2(0x195) | |
| 99 | #define MISC2 VDREG2(0x196) | |
| 100 | ||
| 101 | #define CLMD VDREG2(0x197) | |
| 102 | #define AIGAIN ((const u16[8]) {0x1D0, 0x1D1, 0x1D2, 0x1D3, \ | |
| 103 | 0x2D0, 0x2D1, 0x2D2, 0x2D3}) |