Merge remote-tracking branch 'tpmdd/next'
[deliverable/linux.git] / drivers / staging / octeon / ethernet.c
CommitLineData
67620987
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1/*
2 * This file is based on code from OCTEON SDK by Cavium Networks.
80ff0fd3
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3 *
4 * Copyright (c) 2003-2007 Cavium Networks
5 *
6 * This file is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, Version 2, as
8 * published by the Free Software Foundation.
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9 */
10
df9244c5 11#include <linux/platform_device.h>
80ff0fd3 12#include <linux/kernel.h>
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13#include <linux/module.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
f6ed1b3b 16#include <linux/phy.h>
5a0e3ad6 17#include <linux/slab.h>
dc890df0 18#include <linux/interrupt.h>
df9244c5 19#include <linux/of_net.h>
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20
21#include <net/dst.h>
22
23#include <asm/octeon/octeon.h>
24
25#include "ethernet-defines.h"
a620c163 26#include "octeon-ethernet.h"
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27#include "ethernet-mem.h"
28#include "ethernet-rx.h"
29#include "ethernet-tx.h"
f696a108 30#include "ethernet-mdio.h"
80ff0fd3 31#include "ethernet-util.h"
80ff0fd3 32
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33#include <asm/octeon/cvmx-pip.h>
34#include <asm/octeon/cvmx-pko.h>
35#include <asm/octeon/cvmx-fau.h>
36#include <asm/octeon/cvmx-ipd.h>
37#include <asm/octeon/cvmx-helper.h>
80ff0fd3 38
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39#include <asm/octeon/cvmx-gmxx-defs.h>
40#include <asm/octeon/cvmx-smix-defs.h>
80ff0fd3 41
90419615 42static int num_packet_buffers = 1024;
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43module_param(num_packet_buffers, int, 0444);
44MODULE_PARM_DESC(num_packet_buffers, "\n"
45 "\tNumber of packet buffers to allocate and store in the\n"
5ff8bebb 46 "\tFPA. By default, 1024 packet buffers are used.\n");
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47
48int pow_receive_group = 15;
49module_param(pow_receive_group, int, 0444);
50MODULE_PARM_DESC(pow_receive_group, "\n"
51 "\tPOW group to receive packets from. All ethernet hardware\n"
d82603c6 52 "\twill be configured to send incoming packets to this POW\n"
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53 "\tgroup. Also any other software can submit packets to this\n"
54 "\tgroup for the kernel to process.");
55
56int pow_send_group = -1;
57module_param(pow_send_group, int, 0644);
58MODULE_PARM_DESC(pow_send_group, "\n"
59 "\tPOW group to send packets to other software on. This\n"
60 "\tcontrols the creation of the virtual device pow0.\n"
61 "\talways_use_pow also depends on this value.");
62
63int always_use_pow;
64module_param(always_use_pow, int, 0444);
65MODULE_PARM_DESC(always_use_pow, "\n"
66 "\tWhen set, always send to the pow group. This will cause\n"
67 "\tpackets sent to real ethernet devices to be sent to the\n"
68 "\tPOW group instead of the hardware. Unless some other\n"
69 "\tapplication changes the config, packets will still be\n"
70 "\treceived from the low level hardware. Use this option\n"
71 "\tto allow a CVMX app to intercept all packets from the\n"
72 "\tlinux kernel. You must specify pow_send_group along with\n"
73 "\tthis option.");
74
75char pow_send_list[128] = "";
76module_param_string(pow_send_list, pow_send_list, sizeof(pow_send_list), 0444);
77MODULE_PARM_DESC(pow_send_list, "\n"
78 "\tComma separated list of ethernet devices that should use the\n"
79 "\tPOW for transmit instead of the actual ethernet hardware. This\n"
80 "\tis a per port version of always_use_pow. always_use_pow takes\n"
81 "\tprecedence over this list. For example, setting this to\n"
82 "\t\"eth2,spi3,spi7\" would cause these three devices to transmit\n"
83 "\tusing the pow_send_group.");
84
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85int rx_napi_weight = 32;
86module_param(rx_napi_weight, int, 0444);
87MODULE_PARM_DESC(rx_napi_weight, "The NAPI WEIGHT parameter.");
13c5939e 88
f8c26486 89
d0fbf9f3 90/*
f8c26486
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91 * cvm_oct_poll_queue_stopping - flag to indicate polling should stop.
92 *
93 * Set to one right before cvm_oct_poll_queue is destroyed.
80ff0fd3 94 */
f8c26486 95atomic_t cvm_oct_poll_queue_stopping = ATOMIC_INIT(0);
80ff0fd3 96
d0fbf9f3 97/*
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98 * Array of every ethernet device owned by this driver indexed by
99 * the ipd input port number.
100 */
101struct net_device *cvm_oct_device[TOTAL_NUMBER_OF_PORTS];
102
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103u64 cvm_oct_tx_poll_interval;
104
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105static void cvm_oct_rx_refill_worker(struct work_struct *work);
106static DECLARE_DELAYED_WORK(cvm_oct_rx_refill_work, cvm_oct_rx_refill_worker);
107
108static void cvm_oct_rx_refill_worker(struct work_struct *work)
80ff0fd3 109{
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110 /*
111 * FPA 0 may have been drained, try to refill it if we need
112 * more than num_packet_buffers / 2, otherwise normal receive
113 * processing will refill it. If it were drained, no packets
114 * could be received so cvm_oct_napi_poll would never be
115 * invoked to do the refill.
116 */
117 cvm_oct_rx_refill_pool(num_packet_buffers / 2);
a620c163 118
f8c26486 119 if (!atomic_read(&cvm_oct_poll_queue_stopping))
6fe5efa1 120 schedule_delayed_work(&cvm_oct_rx_refill_work, HZ);
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121}
122
4898c560 123static void cvm_oct_periodic_worker(struct work_struct *work)
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DD
124{
125 struct octeon_ethernet *priv = container_of(work,
126 struct octeon_ethernet,
4898c560 127 port_periodic_work.work);
a620c163 128
f6ed1b3b 129 if (priv->poll)
f8c26486 130 priv->poll(cvm_oct_device[priv->port]);
a620c163 131
b186410d
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132 cvm_oct_device[priv->port]->netdev_ops->ndo_get_stats(
133 cvm_oct_device[priv->port]);
4898c560 134
f8c26486 135 if (!atomic_read(&cvm_oct_poll_queue_stopping))
6fe5efa1 136 schedule_delayed_work(&priv->port_periodic_work, HZ);
851ec8cd 137}
80ff0fd3 138
4f240906 139static void cvm_oct_configure_common_hw(void)
80ff0fd3 140{
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141 /* Setup the FPA */
142 cvmx_fpa_enable();
143 cvm_oct_mem_fill_fpa(CVMX_FPA_PACKET_POOL, CVMX_FPA_PACKET_POOL_SIZE,
144 num_packet_buffers);
145 cvm_oct_mem_fill_fpa(CVMX_FPA_WQE_POOL, CVMX_FPA_WQE_POOL_SIZE,
146 num_packet_buffers);
147 if (CVMX_FPA_OUTPUT_BUFFER_POOL != CVMX_FPA_PACKET_POOL)
148 cvm_oct_mem_fill_fpa(CVMX_FPA_OUTPUT_BUFFER_POOL,
d5f9bc73 149 CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE, 1024);
80ff0fd3 150
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151#ifdef __LITTLE_ENDIAN
152 {
153 union cvmx_ipd_ctl_status ipd_ctl_status;
4bc8ff74 154
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155 ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS);
156 ipd_ctl_status.s.pkt_lend = 1;
157 ipd_ctl_status.s.wqe_lend = 1;
158 cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_status.u64);
159 }
160#endif
161
cccdb277 162 cvmx_helper_setup_red(num_packet_buffers / 4, num_packet_buffers / 8);
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163}
164
165/**
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166 * cvm_oct_free_work- Free a work queue entry
167 *
168 * @work_queue_entry: Work queue entry to free
80ff0fd3 169 *
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170 * Returns Zero on success, Negative on failure.
171 */
172int cvm_oct_free_work(void *work_queue_entry)
173{
174 cvmx_wqe_t *work = work_queue_entry;
175
176 int segments = work->word2.s.bufs;
177 union cvmx_buf_ptr segment_ptr = work->packet_ptr;
178
179 while (segments--) {
180 union cvmx_buf_ptr next_ptr = *(union cvmx_buf_ptr *)
181 cvmx_phys_to_ptr(segment_ptr.s.addr - 8);
182 if (unlikely(!segment_ptr.s.i))
183 cvmx_fpa_free(cvm_oct_get_buffer_ptr(segment_ptr),
184 segment_ptr.s.pool,
c93b0e75 185 CVMX_FPA_PACKET_POOL_SIZE / 128);
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186 segment_ptr = next_ptr;
187 }
c93b0e75 188 cvmx_fpa_free(work, CVMX_FPA_WQE_POOL, 1);
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189
190 return 0;
191}
192EXPORT_SYMBOL(cvm_oct_free_work);
193
f696a108 194/**
ec977c5b 195 * cvm_oct_common_get_stats - get the low level ethernet statistics
f696a108 196 * @dev: Device to get the statistics from
ec977c5b 197 *
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198 * Returns Pointer to the statistics
199 */
200static struct net_device_stats *cvm_oct_common_get_stats(struct net_device *dev)
201{
202 cvmx_pip_port_status_t rx_status;
203 cvmx_pko_port_status_t tx_status;
204 struct octeon_ethernet *priv = netdev_priv(dev);
205
206 if (priv->port < CVMX_PIP_NUM_INPUT_PORTS) {
207 if (octeon_is_simulation()) {
208 /* The simulator doesn't support statistics */
209 memset(&rx_status, 0, sizeof(rx_status));
210 memset(&tx_status, 0, sizeof(tx_status));
211 } else {
212 cvmx_pip_get_port_status(priv->port, 1, &rx_status);
213 cvmx_pko_get_port_status(priv->port, 1, &tx_status);
214 }
215
216 priv->stats.rx_packets += rx_status.inb_packets;
217 priv->stats.tx_packets += tx_status.packets;
218 priv->stats.rx_bytes += rx_status.inb_octets;
219 priv->stats.tx_bytes += tx_status.octets;
220 priv->stats.multicast += rx_status.multicast_packets;
221 priv->stats.rx_crc_errors += rx_status.inb_errors;
222 priv->stats.rx_frame_errors += rx_status.fcs_align_err_packets;
dcf24f77 223 priv->stats.rx_dropped += rx_status.dropped_packets;
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224 }
225
226 return &priv->stats;
227}
228
229/**
ec977c5b 230 * cvm_oct_common_change_mtu - change the link MTU
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231 * @dev: Device to change
232 * @new_mtu: The new MTU
233 *
234 * Returns Zero on success
235 */
236static int cvm_oct_common_change_mtu(struct net_device *dev, int new_mtu)
237{
238 struct octeon_ethernet *priv = netdev_priv(dev);
239 int interface = INTERFACE(priv->port);
240 int index = INDEX(priv->port);
241#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
242 int vlan_bytes = 4;
243#else
244 int vlan_bytes = 0;
245#endif
246
247 /*
248 * Limit the MTU to make sure the ethernet packets are between
249 * 64 bytes and 65535 bytes.
250 */
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LGL
251 if ((new_mtu + 14 + 4 + vlan_bytes < 64) ||
252 (new_mtu + 14 + 4 + vlan_bytes > 65392)) {
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DD
253 pr_err("MTU must be between %d and %d.\n",
254 64 - 14 - 4 - vlan_bytes, 65392 - 14 - 4 - vlan_bytes);
255 return -EINVAL;
256 }
257 dev->mtu = new_mtu;
258
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LGL
259 if ((interface < 2) &&
260 (cvmx_helper_interface_get_mode(interface) !=
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DD
261 CVMX_HELPER_INTERFACE_MODE_SPI)) {
262 /* Add ethernet header and FCS, and VLAN if configured. */
263 int max_packet = new_mtu + 14 + 4 + vlan_bytes;
264
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LGL
265 if (OCTEON_IS_MODEL(OCTEON_CN3XXX) ||
266 OCTEON_IS_MODEL(OCTEON_CN58XX)) {
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DD
267 /* Signal errors on packets larger than the MTU */
268 cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(index, interface),
269 max_packet);
270 } else {
271 /*
272 * Set the hardware to truncate packets larger
273 * than the MTU and smaller the 64 bytes.
274 */
275 union cvmx_pip_frm_len_chkx frm_len_chk;
39bc7513 276
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DD
277 frm_len_chk.u64 = 0;
278 frm_len_chk.s.minlen = 64;
279 frm_len_chk.s.maxlen = max_packet;
280 cvmx_write_csr(CVMX_PIP_FRM_LEN_CHKX(interface),
281 frm_len_chk.u64);
282 }
283 /*
284 * Set the hardware to truncate packets larger than
285 * the MTU. The jabber register must be set to a
286 * multiple of 8 bytes, so round up.
287 */
288 cvmx_write_csr(CVMX_GMXX_RXX_JABBER(index, interface),
289 (max_packet + 7) & ~7u);
290 }
291 return 0;
292}
293
294/**
ec977c5b 295 * cvm_oct_common_set_multicast_list - set the multicast list
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DD
296 * @dev: Device to work on
297 */
298static void cvm_oct_common_set_multicast_list(struct net_device *dev)
299{
300 union cvmx_gmxx_prtx_cfg gmx_cfg;
301 struct octeon_ethernet *priv = netdev_priv(dev);
302 int interface = INTERFACE(priv->port);
303 int index = INDEX(priv->port);
304
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LGL
305 if ((interface < 2) &&
306 (cvmx_helper_interface_get_mode(interface) !=
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DD
307 CVMX_HELPER_INTERFACE_MODE_SPI)) {
308 union cvmx_gmxx_rxx_adr_ctl control;
39bc7513 309
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DD
310 control.u64 = 0;
311 control.s.bcst = 1; /* Allow broadcast MAC addresses */
312
d5907942 313 if (!netdev_mc_empty(dev) || (dev->flags & IFF_ALLMULTI) ||
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DD
314 (dev->flags & IFF_PROMISC))
315 /* Force accept multicast packets */
316 control.s.mcst = 2;
317 else
215c47c9 318 /* Force reject multicast packets */
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319 control.s.mcst = 1;
320
321 if (dev->flags & IFF_PROMISC)
322 /*
323 * Reject matches if promisc. Since CAM is
324 * shut off, should accept everything.
325 */
326 control.s.cam_mode = 0;
327 else
328 /* Filter packets based on the CAM */
329 control.s.cam_mode = 1;
330
331 gmx_cfg.u64 =
332 cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
333 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface),
334 gmx_cfg.u64 & ~1ull);
335
336 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CTL(index, interface),
337 control.u64);
338 if (dev->flags & IFF_PROMISC)
339 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM_EN
340 (index, interface), 0);
341 else
342 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM_EN
343 (index, interface), 1);
344
345 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface),
346 gmx_cfg.u64);
347 }
348}
349
df9244c5 350static int cvm_oct_set_mac_filter(struct net_device *dev)
f696a108
DD
351{
352 struct octeon_ethernet *priv = netdev_priv(dev);
353 union cvmx_gmxx_prtx_cfg gmx_cfg;
354 int interface = INTERFACE(priv->port);
355 int index = INDEX(priv->port);
356
7636941e
LGL
357 if ((interface < 2) &&
358 (cvmx_helper_interface_get_mode(interface) !=
f696a108
DD
359 CVMX_HELPER_INTERFACE_MODE_SPI)) {
360 int i;
ec2c398e
AO
361 u8 *ptr = dev->dev_addr;
362 u64 mac = 0;
39bc7513 363
f696a108 364 for (i = 0; i < 6; i++)
ec2c398e 365 mac = (mac << 8) | (u64)ptr[i];
f696a108
DD
366
367 gmx_cfg.u64 =
368 cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
369 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface),
370 gmx_cfg.u64 & ~1ull);
371
372 cvmx_write_csr(CVMX_GMXX_SMACX(index, interface), mac);
373 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM0(index, interface),
df9244c5 374 ptr[0]);
f696a108 375 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM1(index, interface),
df9244c5 376 ptr[1]);
f696a108 377 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM2(index, interface),
df9244c5 378 ptr[2]);
f696a108 379 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM3(index, interface),
df9244c5 380 ptr[3]);
f696a108 381 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM4(index, interface),
df9244c5 382 ptr[4]);
f696a108 383 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM5(index, interface),
df9244c5 384 ptr[5]);
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DD
385 cvm_oct_common_set_multicast_list(dev);
386 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface),
387 gmx_cfg.u64);
388 }
389 return 0;
390}
391
90590750
CM
392/**
393 * cvm_oct_common_set_mac_address - set the hardware MAC address for a device
394 * @dev: The device in question.
395 * @addr: Socket address.
396 *
397 * Returns Zero on success
398 */
df9244c5
DD
399static int cvm_oct_common_set_mac_address(struct net_device *dev, void *addr)
400{
401 int r = eth_mac_addr(dev, addr);
402
403 if (r)
404 return r;
405 return cvm_oct_set_mac_filter(dev);
406}
407
f696a108 408/**
ec977c5b 409 * cvm_oct_common_init - per network device initialization
f696a108 410 * @dev: Device to initialize
ec977c5b 411 *
f696a108
DD
412 * Returns Zero on success
413 */
414int cvm_oct_common_init(struct net_device *dev)
415{
f696a108 416 struct octeon_ethernet *priv = netdev_priv(dev);
df9244c5
DD
417 const u8 *mac = NULL;
418
419 if (priv->of_node)
420 mac = of_get_mac_address(priv->of_node);
421
4d978452 422 if (mac)
6c71ea54 423 ether_addr_copy(dev->dev_addr, mac);
15c6ff3b 424 else
df9244c5 425 eth_hw_addr_random(dev);
f696a108
DD
426
427 /*
428 * Force the interface to use the POW send if always_use_pow
429 * was specified or it is in the pow send list.
430 */
7636941e
LGL
431 if ((pow_send_group != -1) &&
432 (always_use_pow || strstr(pow_send_list, dev->name)))
f696a108
DD
433 priv->queue = -1;
434
6646baf7
AK
435 if (priv->queue != -1)
436 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
f696a108 437
f696a108
DD
438 /* We do our own locking, Linux doesn't need to */
439 dev->features |= NETIF_F_LLTX;
7ad24ea4 440 dev->ethtool_ops = &cvm_oct_ethtool_ops;
f696a108 441
df9244c5 442 cvm_oct_set_mac_filter(dev);
f696a108
DD
443 dev->netdev_ops->ndo_change_mtu(dev, dev->mtu);
444
445 /*
446 * Zero out stats for port so we won't mistakenly show
447 * counters from the bootloader.
448 */
449 memset(dev->netdev_ops->ndo_get_stats(dev), 0,
450 sizeof(struct net_device_stats));
451
be76400c
AK
452 if (dev->netdev_ops->ndo_stop)
453 dev->netdev_ops->ndo_stop(dev);
454
f696a108
DD
455 return 0;
456}
457
458void cvm_oct_common_uninit(struct net_device *dev)
459{
86bc5ed6
PR
460 if (dev->phydev)
461 phy_disconnect(dev->phydev);
f696a108
DD
462}
463
9e3ae4f9 464int cvm_oct_common_open(struct net_device *dev,
2c265f74 465 void (*link_poll)(struct net_device *))
9e3ae4f9
AK
466{
467 union cvmx_gmxx_prtx_cfg gmx_cfg;
468 struct octeon_ethernet *priv = netdev_priv(dev);
469 int interface = INTERFACE(priv->port);
470 int index = INDEX(priv->port);
471 cvmx_helper_link_info_t link_info;
472 int rv;
473
474 rv = cvm_oct_phy_setup_device(dev);
475 if (rv)
476 return rv;
477
478 gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
479 gmx_cfg.s.en = 1;
480 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
481
482 if (octeon_is_simulation())
483 return 0;
484
86bc5ed6
PR
485 if (dev->phydev) {
486 int r = phy_read_status(dev->phydev);
9e3ae4f9 487
86bc5ed6 488 if (r == 0 && dev->phydev->link == 0)
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AK
489 netif_carrier_off(dev);
490 cvm_oct_adjust_link(dev);
491 } else {
492 link_info = cvmx_helper_link_get(priv->port);
493 if (!link_info.s.link_up)
494 netif_carrier_off(dev);
495 priv->poll = link_poll;
2c265f74 496 link_poll(dev);
9e3ae4f9
AK
497 }
498
499 return 0;
500}
501
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502void cvm_oct_link_poll(struct net_device *dev)
503{
504 struct octeon_ethernet *priv = netdev_priv(dev);
505 cvmx_helper_link_info_t link_info;
506
507 link_info = cvmx_helper_link_get(priv->port);
508 if (link_info.u64 == priv->link_info)
509 return;
510
511 link_info = cvmx_helper_link_autoconf(priv->port);
512 priv->link_info = link_info.u64;
513
514 if (link_info.s.link_up) {
515 if (!netif_carrier_ok(dev))
516 netif_carrier_on(dev);
517 } else if (netif_carrier_ok(dev)) {
518 netif_carrier_off(dev);
519 }
520 cvm_oct_note_carrier(priv, link_info);
521}
522
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523static int cvm_oct_xaui_open(struct net_device *dev)
524{
525 return cvm_oct_common_open(dev, cvm_oct_link_poll);
526}
527
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DD
528static const struct net_device_ops cvm_oct_npi_netdev_ops = {
529 .ndo_init = cvm_oct_common_init,
530 .ndo_uninit = cvm_oct_common_uninit,
531 .ndo_start_xmit = cvm_oct_xmit,
afc4b13d 532 .ndo_set_rx_mode = cvm_oct_common_set_multicast_list,
f696a108
DD
533 .ndo_set_mac_address = cvm_oct_common_set_mac_address,
534 .ndo_do_ioctl = cvm_oct_ioctl,
535 .ndo_change_mtu = cvm_oct_common_change_mtu,
536 .ndo_get_stats = cvm_oct_common_get_stats,
537#ifdef CONFIG_NET_POLL_CONTROLLER
538 .ndo_poll_controller = cvm_oct_poll_controller,
539#endif
540};
0e350e17 541
f696a108 542static const struct net_device_ops cvm_oct_xaui_netdev_ops = {
41cb5786 543 .ndo_init = cvm_oct_common_init,
3c339145 544 .ndo_uninit = cvm_oct_common_uninit,
f696a108 545 .ndo_open = cvm_oct_xaui_open,
96217ebf 546 .ndo_stop = cvm_oct_common_stop,
f696a108 547 .ndo_start_xmit = cvm_oct_xmit,
afc4b13d 548 .ndo_set_rx_mode = cvm_oct_common_set_multicast_list,
f696a108
DD
549 .ndo_set_mac_address = cvm_oct_common_set_mac_address,
550 .ndo_do_ioctl = cvm_oct_ioctl,
551 .ndo_change_mtu = cvm_oct_common_change_mtu,
552 .ndo_get_stats = cvm_oct_common_get_stats,
553#ifdef CONFIG_NET_POLL_CONTROLLER
554 .ndo_poll_controller = cvm_oct_poll_controller,
555#endif
556};
0e350e17 557
f696a108
DD
558static const struct net_device_ops cvm_oct_sgmii_netdev_ops = {
559 .ndo_init = cvm_oct_sgmii_init,
3c339145 560 .ndo_uninit = cvm_oct_common_uninit,
f696a108 561 .ndo_open = cvm_oct_sgmii_open,
96217ebf 562 .ndo_stop = cvm_oct_common_stop,
f696a108 563 .ndo_start_xmit = cvm_oct_xmit,
afc4b13d 564 .ndo_set_rx_mode = cvm_oct_common_set_multicast_list,
f696a108
DD
565 .ndo_set_mac_address = cvm_oct_common_set_mac_address,
566 .ndo_do_ioctl = cvm_oct_ioctl,
567 .ndo_change_mtu = cvm_oct_common_change_mtu,
568 .ndo_get_stats = cvm_oct_common_get_stats,
569#ifdef CONFIG_NET_POLL_CONTROLLER
570 .ndo_poll_controller = cvm_oct_poll_controller,
571#endif
572};
0e350e17 573
f696a108
DD
574static const struct net_device_ops cvm_oct_spi_netdev_ops = {
575 .ndo_init = cvm_oct_spi_init,
576 .ndo_uninit = cvm_oct_spi_uninit,
577 .ndo_start_xmit = cvm_oct_xmit,
afc4b13d 578 .ndo_set_rx_mode = cvm_oct_common_set_multicast_list,
f696a108
DD
579 .ndo_set_mac_address = cvm_oct_common_set_mac_address,
580 .ndo_do_ioctl = cvm_oct_ioctl,
581 .ndo_change_mtu = cvm_oct_common_change_mtu,
582 .ndo_get_stats = cvm_oct_common_get_stats,
583#ifdef CONFIG_NET_POLL_CONTROLLER
584 .ndo_poll_controller = cvm_oct_poll_controller,
585#endif
586};
0e350e17 587
f696a108 588static const struct net_device_ops cvm_oct_rgmii_netdev_ops = {
710086db
AK
589 .ndo_init = cvm_oct_common_init,
590 .ndo_uninit = cvm_oct_common_uninit,
f696a108 591 .ndo_open = cvm_oct_rgmii_open,
96217ebf 592 .ndo_stop = cvm_oct_common_stop,
f696a108 593 .ndo_start_xmit = cvm_oct_xmit,
afc4b13d 594 .ndo_set_rx_mode = cvm_oct_common_set_multicast_list,
f696a108
DD
595 .ndo_set_mac_address = cvm_oct_common_set_mac_address,
596 .ndo_do_ioctl = cvm_oct_ioctl,
597 .ndo_change_mtu = cvm_oct_common_change_mtu,
598 .ndo_get_stats = cvm_oct_common_get_stats,
599#ifdef CONFIG_NET_POLL_CONTROLLER
600 .ndo_poll_controller = cvm_oct_poll_controller,
601#endif
602};
0e350e17 603
f696a108
DD
604static const struct net_device_ops cvm_oct_pow_netdev_ops = {
605 .ndo_init = cvm_oct_common_init,
606 .ndo_start_xmit = cvm_oct_xmit_pow,
afc4b13d 607 .ndo_set_rx_mode = cvm_oct_common_set_multicast_list,
f696a108
DD
608 .ndo_set_mac_address = cvm_oct_common_set_mac_address,
609 .ndo_do_ioctl = cvm_oct_ioctl,
610 .ndo_change_mtu = cvm_oct_common_change_mtu,
611 .ndo_get_stats = cvm_oct_common_get_stats,
612#ifdef CONFIG_NET_POLL_CONTROLLER
613 .ndo_poll_controller = cvm_oct_poll_controller,
614#endif
615};
616
b186410d
NH
617static struct device_node *cvm_oct_of_get_child(
618 const struct device_node *parent, int reg_val)
df9244c5
DD
619{
620 struct device_node *node = NULL;
621 int size;
622 const __be32 *addr;
623
624 for (;;) {
625 node = of_get_next_child(parent, node);
626 if (!node)
627 break;
628 addr = of_get_property(node, "reg", &size);
629 if (addr && (be32_to_cpu(*addr) == reg_val))
630 break;
631 }
632 return node;
633}
634
4f240906 635static struct device_node *cvm_oct_node_for_port(struct device_node *pip,
ac05a587 636 int interface, int port)
df9244c5
DD
637{
638 struct device_node *ni, *np;
639
640 ni = cvm_oct_of_get_child(pip, interface);
641 if (!ni)
642 return NULL;
643
644 np = cvm_oct_of_get_child(ni, port);
645 of_node_put(ni);
646
647 return np;
648}
649
4f240906 650static int cvm_oct_probe(struct platform_device *pdev)
80ff0fd3
DD
651{
652 int num_interfaces;
653 int interface;
654 int fau = FAU_NUM_PACKET_BUFFERS_TO_FREE;
655 int qos;
df9244c5 656 struct device_node *pip;
80ff0fd3 657
f6ed1b3b 658 octeon_mdiobus_force_mod_depencency();
80ff0fd3 659
df9244c5
DD
660 pip = pdev->dev.of_node;
661 if (!pip) {
662 pr_err("Error: No 'pip' in /aliases\n");
663 return -EINVAL;
664 }
13c5939e 665
f8c26486 666
80ff0fd3
DD
667 cvm_oct_configure_common_hw();
668
669 cvmx_helper_initialize_packet_io_global();
670
671 /* Change the input group for all ports before input is enabled */
672 num_interfaces = cvmx_helper_get_number_of_interfaces();
673 for (interface = 0; interface < num_interfaces; interface++) {
674 int num_ports = cvmx_helper_ports_on_interface(interface);
675 int port;
676
677 for (port = cvmx_helper_get_ipd_port(interface, 0);
678 port < cvmx_helper_get_ipd_port(interface, num_ports);
679 port++) {
680 union cvmx_pip_prt_tagx pip_prt_tagx;
39bc7513 681
80ff0fd3
DD
682 pip_prt_tagx.u64 =
683 cvmx_read_csr(CVMX_PIP_PRT_TAGX(port));
684 pip_prt_tagx.s.grp = pow_receive_group;
685 cvmx_write_csr(CVMX_PIP_PRT_TAGX(port),
686 pip_prt_tagx.u64);
687 }
688 }
689
690 cvmx_helper_ipd_and_packet_input_enable();
691
692 memset(cvm_oct_device, 0, sizeof(cvm_oct_device));
693
694 /*
695 * Initialize the FAU used for counting packet buffers that
696 * need to be freed.
697 */
698 cvmx_fau_atomic_write32(FAU_NUM_PACKET_BUFFERS_TO_FREE, 0);
699
4898c560
DD
700 /* Initialize the FAU used for counting tx SKBs that need to be freed */
701 cvmx_fau_atomic_write32(FAU_TOTAL_TX_TO_CLEAN, 0);
702
80ff0fd3
DD
703 if ((pow_send_group != -1)) {
704 struct net_device *dev;
39bc7513 705
80ff0fd3
DD
706 pr_info("\tConfiguring device for POW only access\n");
707 dev = alloc_etherdev(sizeof(struct octeon_ethernet));
708 if (dev) {
709 /* Initialize the device private structure. */
710 struct octeon_ethernet *priv = netdev_priv(dev);
80ff0fd3 711
f696a108 712 dev->netdev_ops = &cvm_oct_pow_netdev_ops;
80ff0fd3
DD
713 priv->imode = CVMX_HELPER_INTERFACE_MODE_DISABLED;
714 priv->port = CVMX_PIP_NUM_INPUT_PORTS;
715 priv->queue = -1;
716 strcpy(dev->name, "pow%d");
717 for (qos = 0; qos < 16; qos++)
718 skb_queue_head_init(&priv->tx_free_list[qos]);
719
720 if (register_netdev(dev) < 0) {
6568a234 721 pr_err("Failed to register ethernet device for POW\n");
c4711c3a 722 free_netdev(dev);
80ff0fd3
DD
723 } else {
724 cvm_oct_device[CVMX_PIP_NUM_INPUT_PORTS] = dev;
6568a234
DD
725 pr_info("%s: POW send group %d, receive group %d\n",
726 dev->name, pow_send_group,
727 pow_receive_group);
80ff0fd3
DD
728 }
729 } else {
6568a234 730 pr_err("Failed to allocate ethernet device for POW\n");
80ff0fd3
DD
731 }
732 }
733
734 num_interfaces = cvmx_helper_get_number_of_interfaces();
735 for (interface = 0; interface < num_interfaces; interface++) {
736 cvmx_helper_interface_mode_t imode =
737 cvmx_helper_interface_get_mode(interface);
738 int num_ports = cvmx_helper_ports_on_interface(interface);
739 int port;
df9244c5 740 int port_index;
80ff0fd3 741
b186410d
NH
742 for (port_index = 0,
743 port = cvmx_helper_get_ipd_port(interface, 0);
80ff0fd3 744 port < cvmx_helper_get_ipd_port(interface, num_ports);
df9244c5 745 port_index++, port++) {
80ff0fd3
DD
746 struct octeon_ethernet *priv;
747 struct net_device *dev =
748 alloc_etherdev(sizeof(struct octeon_ethernet));
749 if (!dev) {
99f8dbc5
EA
750 pr_err("Failed to allocate ethernet device for port %d\n",
751 port);
80ff0fd3
DD
752 continue;
753 }
80ff0fd3
DD
754
755 /* Initialize the device private structure. */
756 priv = netdev_priv(dev);
ec3a2207 757 priv->netdev = dev;
b186410d
NH
758 priv->of_node = cvm_oct_node_for_port(pip, interface,
759 port_index);
80ff0fd3 760
4898c560
DD
761 INIT_DELAYED_WORK(&priv->port_periodic_work,
762 cvm_oct_periodic_worker);
80ff0fd3
DD
763 priv->imode = imode;
764 priv->port = port;
765 priv->queue = cvmx_pko_get_base_queue(priv->port);
766 priv->fau = fau - cvmx_pko_get_num_queues(port) * 4;
767 for (qos = 0; qos < 16; qos++)
768 skb_queue_head_init(&priv->tx_free_list[qos]);
769 for (qos = 0; qos < cvmx_pko_get_num_queues(port);
770 qos++)
771 cvmx_fau_atomic_write32(priv->fau + qos * 4, 0);
772
773 switch (priv->imode) {
80ff0fd3
DD
774 /* These types don't support ports to IPD/PKO */
775 case CVMX_HELPER_INTERFACE_MODE_DISABLED:
776 case CVMX_HELPER_INTERFACE_MODE_PCIE:
777 case CVMX_HELPER_INTERFACE_MODE_PICMG:
778 break;
779
780 case CVMX_HELPER_INTERFACE_MODE_NPI:
f696a108 781 dev->netdev_ops = &cvm_oct_npi_netdev_ops;
80ff0fd3
DD
782 strcpy(dev->name, "npi%d");
783 break;
784
785 case CVMX_HELPER_INTERFACE_MODE_XAUI:
f696a108 786 dev->netdev_ops = &cvm_oct_xaui_netdev_ops;
80ff0fd3
DD
787 strcpy(dev->name, "xaui%d");
788 break;
789
790 case CVMX_HELPER_INTERFACE_MODE_LOOP:
f696a108 791 dev->netdev_ops = &cvm_oct_npi_netdev_ops;
80ff0fd3
DD
792 strcpy(dev->name, "loop%d");
793 break;
794
795 case CVMX_HELPER_INTERFACE_MODE_SGMII:
f696a108 796 dev->netdev_ops = &cvm_oct_sgmii_netdev_ops;
80ff0fd3
DD
797 strcpy(dev->name, "eth%d");
798 break;
799
800 case CVMX_HELPER_INTERFACE_MODE_SPI:
f696a108 801 dev->netdev_ops = &cvm_oct_spi_netdev_ops;
80ff0fd3
DD
802 strcpy(dev->name, "spi%d");
803 break;
804
805 case CVMX_HELPER_INTERFACE_MODE_RGMII:
806 case CVMX_HELPER_INTERFACE_MODE_GMII:
f696a108 807 dev->netdev_ops = &cvm_oct_rgmii_netdev_ops;
80ff0fd3
DD
808 strcpy(dev->name, "eth%d");
809 break;
810 }
811
f696a108 812 if (!dev->netdev_ops) {
c4711c3a 813 free_netdev(dev);
80ff0fd3 814 } else if (register_netdev(dev) < 0) {
0a5fcc6b 815 pr_err("Failed to register ethernet device for interface %d, port %d\n",
ac05a587 816 interface, priv->port);
c4711c3a 817 free_netdev(dev);
80ff0fd3
DD
818 } else {
819 cvm_oct_device[priv->port] = dev;
820 fau -=
821 cvmx_pko_get_num_queues(priv->port) *
ec2c398e 822 sizeof(u32);
6fe5efa1 823 schedule_delayed_work(&priv->port_periodic_work, HZ);
80ff0fd3
DD
824 }
825 }
826 }
827
4898c560 828 cvm_oct_tx_initialize();
3368c784 829 cvm_oct_rx_initialize();
80ff0fd3 830
4898c560 831 /*
f5801a81 832 * 150 uS: about 10 1500-byte packets at 1GE.
4898c560
DD
833 */
834 cvm_oct_tx_poll_interval = 150 * (octeon_get_clock_rate() / 1000000);
80ff0fd3 835
6fe5efa1 836 schedule_delayed_work(&cvm_oct_rx_refill_work, HZ);
80ff0fd3
DD
837
838 return 0;
839}
840
f7e2f350 841static int cvm_oct_remove(struct platform_device *pdev)
80ff0fd3
DD
842{
843 int port;
844
845 /* Disable POW interrupt */
bcbb1396
AK
846 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
847 cvmx_write_csr(CVMX_SSO_WQ_INT_THRX(pow_receive_group), 0);
848 else
849 cvmx_write_csr(CVMX_POW_WQ_INT_THRX(pow_receive_group), 0);
80ff0fd3
DD
850
851 cvmx_ipd_disable();
852
853 /* Free the interrupt handler */
854 free_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group, cvm_oct_device);
855
f8c26486
DD
856 atomic_inc_return(&cvm_oct_poll_queue_stopping);
857 cancel_delayed_work_sync(&cvm_oct_rx_refill_work);
858
80ff0fd3 859 cvm_oct_rx_shutdown();
4898c560
DD
860 cvm_oct_tx_shutdown();
861
80ff0fd3
DD
862 cvmx_pko_disable();
863
864 /* Free the ethernet devices */
865 for (port = 0; port < TOTAL_NUMBER_OF_PORTS; port++) {
866 if (cvm_oct_device[port]) {
f8c26486
DD
867 struct net_device *dev = cvm_oct_device[port];
868 struct octeon_ethernet *priv = netdev_priv(dev);
39bc7513 869
4898c560 870 cancel_delayed_work_sync(&priv->port_periodic_work);
f8c26486 871
4898c560 872 cvm_oct_tx_shutdown_dev(dev);
f8c26486 873 unregister_netdev(dev);
c4711c3a 874 free_netdev(dev);
80ff0fd3
DD
875 cvm_oct_device[port] = NULL;
876 }
877 }
878
f8c26486 879
80ff0fd3 880 cvmx_pko_shutdown();
80ff0fd3
DD
881
882 cvmx_ipd_free_ptr();
883
884 /* Free the HW pools */
885 cvm_oct_mem_empty_fpa(CVMX_FPA_PACKET_POOL, CVMX_FPA_PACKET_POOL_SIZE,
886 num_packet_buffers);
887 cvm_oct_mem_empty_fpa(CVMX_FPA_WQE_POOL, CVMX_FPA_WQE_POOL_SIZE,
888 num_packet_buffers);
889 if (CVMX_FPA_OUTPUT_BUFFER_POOL != CVMX_FPA_PACKET_POOL)
890 cvm_oct_mem_empty_fpa(CVMX_FPA_OUTPUT_BUFFER_POOL,
891 CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE, 128);
df9244c5 892 return 0;
80ff0fd3
DD
893}
894
87794575 895static const struct of_device_id cvm_oct_match[] = {
df9244c5
DD
896 {
897 .compatible = "cavium,octeon-3860-pip",
898 },
899 {},
900};
901MODULE_DEVICE_TABLE(of, cvm_oct_match);
902
903static struct platform_driver cvm_oct_driver = {
904 .probe = cvm_oct_probe,
095d0bb5 905 .remove = cvm_oct_remove,
df9244c5 906 .driver = {
df9244c5
DD
907 .name = KBUILD_MODNAME,
908 .of_match_table = cvm_oct_match,
909 },
910};
911
912module_platform_driver(cvm_oct_driver);
913
80ff0fd3
DD
914MODULE_LICENSE("GPL");
915MODULE_AUTHOR("Cavium Networks <support@caviumnetworks.com>");
916MODULE_DESCRIPTION("Cavium Networks Octeon ethernet driver.");
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