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serial: 8250_pci: Add WCH CH352 quirk to avoid Xscale detection
[deliverable/linux.git] / drivers / tty / serial / 8250 / 8250_pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
1da177e4
LT		 11 */
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/pci.h>
1da177e4
LT		 15#include <linux/string.h>
16#include <linux/kernel.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/tty.h>
0ad372b9 20#include <linux/serial_reg.h>
1da177e4
LT		 21#include <linux/serial_core.h>
22#include <linux/8250_pci.h>
23#include <linux/bitops.h>
24
25#include <asm/byteorder.h>
26#include <asm/io.h>
27
28#include "8250.h"
29
30#undef SERIAL_DEBUG_PCI
31
1da177e4
LT		 32/*
33 * init function returns:
34 * > 0 - number of ports
35 * = 0 - use board->num_ports
36 * < 0 - error
37 */
38struct pci_serial_quirk {
39 u32 vendor;
40 u32 device;
41 u32 subvendor;
42 u32 subdevice;
5bf8f501 43 int (*probe)(struct pci_dev *dev);
1da177e4 44 int (*init)(struct pci_dev *dev);
975a1a7d
RK		 45 int (*setup)(struct serial_private *,
46 const struct pciserial_board *,
2655a2c7 47 struct uart_8250_port *, int);
1da177e4
LT		 48 void (*exit)(struct pci_dev *dev);
49};
50
51#define PCI_NUM_BAR_RESOURCES 6
52
53struct serial_private {
70db3d91 54 struct pci_dev *dev;
1da177e4
LT		 55 unsigned int nr;
56 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
57 struct pci_serial_quirk *quirk;
58 int line[0];
59};
60
7808edcd 61static int pci_default_setup(struct serial_private*,
2655a2c7 62 const struct pciserial_board*, struct uart_8250_port *, int);
7808edcd 63
1da177e4
LT		 64static void moan_device(const char *str, struct pci_dev *dev)
65{
ad361c98
JP		 66 printk(KERN_WARNING
67 "%s: %s\n"
68 "Please send the output of lspci -vv, this\n"
69 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
70 "manufacturer and name of serial board or\n"
71 "modem board to rmk+serial@arm.linux.org.uk.\n",
1da177e4
LT		 72 pci_name(dev), str, dev->vendor, dev->device,
73 dev->subsystem_vendor, dev->subsystem_device);
74}
75
76static int
2655a2c7 77setup_port(struct serial_private *priv, struct uart_8250_port *port,
1da177e4
LT		 78 int bar, int offset, int regshift)
79{
70db3d91 80 struct pci_dev *dev = priv->dev;
1da177e4
LT		 81 unsigned long base, len;
82
83 if (bar >= PCI_NUM_BAR_RESOURCES)
84 return -EINVAL;
85
72ce9a83
RK		 86 base = pci_resource_start(dev, bar);
87
1da177e4 88 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4
LT		 89 len = pci_resource_len(dev, bar);
90
91 if (!priv->remapped_bar[bar])
6f441fe9 92 priv->remapped_bar[bar] = ioremap_nocache(base, len);
1da177e4
LT		 93 if (!priv->remapped_bar[bar])
94 return -ENOMEM;
95
2655a2c7
AC		 96 port->port.iotype = UPIO_MEM;
97 port->port.iobase = 0;
98 port->port.mapbase = base + offset;
99 port->port.membase = priv->remapped_bar[bar] + offset;
100 port->port.regshift = regshift;
1da177e4 101 } else {
2655a2c7
AC		 102 port->port.iotype = UPIO_PORT;
103 port->port.iobase = base + offset;
104 port->port.mapbase = 0;
105 port->port.membase = NULL;
106 port->port.regshift = 0;
1da177e4
LT		 107 }
108 return 0;
109}
110
02c9b5cf
KJ		 111/*
112 * ADDI-DATA GmbH communication cards <info@addi-data.com>
113 */
114static int addidata_apci7800_setup(struct serial_private *priv,
975a1a7d 115 const struct pciserial_board *board,
2655a2c7 116 struct uart_8250_port *port, int idx)
02c9b5cf
KJ		 117{
118 unsigned int bar = 0, offset = board->first_offset;
119 bar = FL_GET_BASE(board->flags);
120
121 if (idx < 2) {
122 offset += idx * board->uart_offset;
123 } else if ((idx >= 2) && (idx < 4)) {
124 bar += 1;
125 offset += ((idx - 2) * board->uart_offset);
126 } else if ((idx >= 4) && (idx < 6)) {
127 bar += 2;
128 offset += ((idx - 4) * board->uart_offset);
129 } else if (idx >= 6) {
130 bar += 3;
131 offset += ((idx - 6) * board->uart_offset);
132 }
133
134 return setup_port(priv, port, bar, offset, board->reg_shift);
135}
136
1da177e4
LT		 137/*
138 * AFAVLAB uses a different mixture of BARs and offsets
139 * Not that ugly ;) -- HW
140 */
141static int
975a1a7d 142afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 143 struct uart_8250_port *port, int idx)
1da177e4
LT		 144{
145 unsigned int bar, offset = board->first_offset;
5756ee99 146
1da177e4
LT		 147 bar = FL_GET_BASE(board->flags);
148 if (idx < 4)
149 bar += idx;
150 else {
151 bar = 4;
152 offset += (idx - 4) * board->uart_offset;
153 }
154
70db3d91 155 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 156}
157
158/*
159 * HP's Remote Management Console. The Diva chip came in several
160 * different versions. N-class, L2000 and A500 have two Diva chips, each
161 * with 3 UARTs (the third UART on the second chip is unused). Superdome
162 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
163 * one Diva chip, but it has been expanded to 5 UARTs.
164 */
61a116ef 165static int pci_hp_diva_init(struct pci_dev *dev)
1da177e4
LT		 166{
167 int rc = 0;
168
169 switch (dev->subsystem_device) {
170 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
171 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
172 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
173 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
174 rc = 3;
175 break;
176 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
177 rc = 2;
178 break;
179 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
180 rc = 4;
181 break;
182 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 183 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 184 rc = 1;
185 break;
186 }
187
188 return rc;
189}
190
191/*
192 * HP's Diva chip puts the 4th/5th serial port further out, and
193 * some serial ports are supposed to be hidden on certain models.
194 */
195static int
975a1a7d
RK		 196pci_hp_diva_setup(struct serial_private *priv,
197 const struct pciserial_board *board,
2655a2c7 198 struct uart_8250_port *port, int idx)
1da177e4
LT		 199{
200 unsigned int offset = board->first_offset;
201 unsigned int bar = FL_GET_BASE(board->flags);
202
70db3d91 203 switch (priv->dev->subsystem_device) {
1da177e4
LT		 204 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
205 if (idx == 3)
206 idx++;
207 break;
208 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
209 if (idx > 0)
210 idx++;
211 if (idx > 2)
212 idx++;
213 break;
214 }
215 if (idx > 2)
216 offset = 0x18;
217
218 offset += idx * board->uart_offset;
219
70db3d91 220 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 221}
222
223/*
224 * Added for EKF Intel i960 serial boards
225 */
61a116ef 226static int pci_inteli960ni_init(struct pci_dev *dev)
1da177e4
LT		 227{
228 unsigned long oldval;
229
230 if (!(dev->subsystem_device & 0x1000))
231 return -ENODEV;
232
233 /* is firmware started? */
5756ee99
AC		 234 pci_read_config_dword(dev, 0x44, (void *)&oldval);
235 if (oldval == 0x00001000L) { /* RESET value */
1da177e4
LT		 236 printk(KERN_DEBUG "Local i960 firmware missing");
237 return -ENODEV;
238 }
239 return 0;
240}
241
242/*
243 * Some PCI serial cards using the PLX 9050 PCI interface chip require
244 * that the card interrupt be explicitly enabled or disabled. This
245 * seems to be mainly needed on card using the PLX which also use I/O
246 * mapped memory.
247 */
61a116ef 248static int pci_plx9050_init(struct pci_dev *dev)
1da177e4
LT		 249{
250 u8 irq_config;
251 void __iomem *p;
252
253 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
254 moan_device("no memory in bar 0", dev);
255 return 0;
256 }
257
258 irq_config = 0x41;
add7b58e 259 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
5756ee99 260 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
1da177e4 261 irq_config = 0x43;
5756ee99 262
1da177e4 263 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
5756ee99 264 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
1da177e4
LT		 265 /*
266 * As the megawolf cards have the int pins active
267 * high, and have 2 UART chips, both ints must be
268 * enabled on the 9050. Also, the UARTS are set in
269 * 16450 mode by default, so we have to enable the
270 * 16C950 'enhanced' mode so that we can use the
271 * deep FIFOs
272 */
273 irq_config = 0x5b;
1da177e4
LT		 274 /*
275 * enable/disable interrupts
276 */
6f441fe9 277 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 278 if (p == NULL)
279 return -ENOMEM;
280 writel(irq_config, p + 0x4c);
281
282 /*
283 * Read the register back to ensure that it took effect.
284 */
285 readl(p + 0x4c);
286 iounmap(p);
287
288 return 0;
289}
290
ae8d8a14 291static void pci_plx9050_exit(struct pci_dev *dev)
1da177e4
LT		 292{
293 u8 __iomem *p;
294
295 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
296 return;
297
298 /*
299 * disable interrupts
300 */
6f441fe9 301 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 302 if (p != NULL) {
303 writel(0, p + 0x4c);
304
305 /*
306 * Read the register back to ensure that it took effect.
307 */
308 readl(p + 0x4c);
309 iounmap(p);
310 }
311}
312
04bf7e74
WP		 313#define NI8420_INT_ENABLE_REG 0x38
314#define NI8420_INT_ENABLE_BIT 0x2000
315
ae8d8a14 316static void pci_ni8420_exit(struct pci_dev *dev)
04bf7e74
WP		 317{
318 void __iomem *p;
319 unsigned long base, len;
320 unsigned int bar = 0;
321
322 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
323 moan_device("no memory in bar", dev);
324 return;
325 }
326
327 base = pci_resource_start(dev, bar);
328 len = pci_resource_len(dev, bar);
329 p = ioremap_nocache(base, len);
330 if (p == NULL)
331 return;
332
333 /* Disable the CPU Interrupt */
334 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
335 p + NI8420_INT_ENABLE_REG);
336 iounmap(p);
337}
338
339
46a0fac9
SB		 340/* MITE registers */
341#define MITE_IOWBSR1 0xc4
342#define MITE_IOWCR1 0xf4
343#define MITE_LCIMR1 0x08
344#define MITE_LCIMR2 0x10
345
346#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
347
ae8d8a14 348static void pci_ni8430_exit(struct pci_dev *dev)
46a0fac9
SB		 349{
350 void __iomem *p;
351 unsigned long base, len;
352 unsigned int bar = 0;
353
354 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
355 moan_device("no memory in bar", dev);
356 return;
357 }
358
359 base = pci_resource_start(dev, bar);
360 len = pci_resource_len(dev, bar);
361 p = ioremap_nocache(base, len);
362 if (p == NULL)
363 return;
364
365 /* Disable the CPU Interrupt */
366 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
367 iounmap(p);
368}
369
1da177e4
LT		 370/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
371static int
975a1a7d 372sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 373 struct uart_8250_port *port, int idx)
1da177e4
LT		 374{
375 unsigned int bar, offset = board->first_offset;
376
377 bar = 0;
378
379 if (idx < 4) {
380 /* first four channels map to 0, 0x100, 0x200, 0x300 */
381 offset += idx * board->uart_offset;
382 } else if (idx < 8) {
383 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
384 offset += idx * board->uart_offset + 0xC00;
385 } else /* we have only 8 ports on PMC-OCTALPRO */
386 return 1;
387
70db3d91 388 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 389}
390
391/*
392* This does initialization for PMC OCTALPRO cards:
393* maps the device memory, resets the UARTs (needed, bc
394* if the module is removed and inserted again, the card
395* is in the sleep mode) and enables global interrupt.
396*/
397
398/* global control register offset for SBS PMC-OctalPro */
399#define OCT_REG_CR_OFF 0x500
400
61a116ef 401static int sbs_init(struct pci_dev *dev)
1da177e4
LT		 402{
403 u8 __iomem *p;
404
24ed3aba 405 p = pci_ioremap_bar(dev, 0);
1da177e4
LT		 406
407 if (p == NULL)
408 return -ENOMEM;
409 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
5756ee99 410 writeb(0x10, p + OCT_REG_CR_OFF);
1da177e4 411 udelay(50);
5756ee99 412 writeb(0x0, p + OCT_REG_CR_OFF);
1da177e4
LT		 413
414 /* Set bit-2 (INTENABLE) of Control Register */
415 writeb(0x4, p + OCT_REG_CR_OFF);
416 iounmap(p);
417
418 return 0;
419}
420
421/*
422 * Disables the global interrupt of PMC-OctalPro
423 */
424
ae8d8a14 425static void sbs_exit(struct pci_dev *dev)
1da177e4
LT		 426{
427 u8 __iomem *p;
428
24ed3aba 429 p = pci_ioremap_bar(dev, 0);
5756ee99
AC		 430 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
431 if (p != NULL)
1da177e4 432 writeb(0, p + OCT_REG_CR_OFF);
1da177e4
LT		 433 iounmap(p);
434}
435
436/*
437 * SIIG serial cards have an PCI interface chip which also controls
438 * the UART clocking frequency. Each UART can be clocked independently
25985edc 439 * (except cards equipped with 4 UARTs) and initial clocking settings
1da177e4
LT		 440 * are stored in the EEPROM chip. It can cause problems because this
441 * version of serial driver doesn't support differently clocked UART's
442 * on single PCI card. To prevent this, initialization functions set
443 * high frequency clocking for all UART's on given card. It is safe (I
444 * hope) because it doesn't touch EEPROM settings to prevent conflicts
445 * with other OSes (like M$ DOS).
446 *
447 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
5756ee99 448 *
1da177e4
LT		 449 * There is two family of SIIG serial cards with different PCI
450 * interface chip and different configuration methods:
451 * - 10x cards have control registers in IO and/or memory space;
452 * - 20x cards have control registers in standard PCI configuration space.
453 *
67d74b87
RK		 454 * Note: all 10x cards have PCI device ids 0x10..
455 * all 20x cards have PCI device ids 0x20..
456 *
fbc0dc0d
AP		 457 * There are also Quartet Serial cards which use Oxford Semiconductor
458 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
459 *
1da177e4
LT		 460 * Note: some SIIG cards are probed by the parport_serial object.
461 */
462
463#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
464#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
465
466static int pci_siig10x_init(struct pci_dev *dev)
467{
468 u16 data;
469 void __iomem *p;
470
471 switch (dev->device & 0xfff8) {
472 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
473 data = 0xffdf;
474 break;
475 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
476 data = 0xf7ff;
477 break;
478 default: /* 1S1P, 4S */
479 data = 0xfffb;
480 break;
481 }
482
6f441fe9 483 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 484 if (p == NULL)
485 return -ENOMEM;
486
487 writew(readw(p + 0x28) & data, p + 0x28);
488 readw(p + 0x28);
489 iounmap(p);
490 return 0;
491}
492
493#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
494#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
495
496static int pci_siig20x_init(struct pci_dev *dev)
497{
498 u8 data;
499
500 /* Change clock frequency for the first UART. */
501 pci_read_config_byte(dev, 0x6f, &data);
502 pci_write_config_byte(dev, 0x6f, data & 0xef);
503
504 /* If this card has 2 UART, we have to do the same with second UART. */
505 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
506 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
507 pci_read_config_byte(dev, 0x73, &data);
508 pci_write_config_byte(dev, 0x73, data & 0xef);
509 }
510 return 0;
511}
512
67d74b87
RK		 513static int pci_siig_init(struct pci_dev *dev)
514{
515 unsigned int type = dev->device & 0xff00;
516
517 if (type == 0x1000)
518 return pci_siig10x_init(dev);
519 else if (type == 0x2000)
520 return pci_siig20x_init(dev);
521
522 moan_device("Unknown SIIG card", dev);
523 return -ENODEV;
524}
525
3ec9c594 526static int pci_siig_setup(struct serial_private *priv,
975a1a7d 527 const struct pciserial_board *board,
2655a2c7 528 struct uart_8250_port *port, int idx)
3ec9c594
AP		 529{
530 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
531
532 if (idx > 3) {
533 bar = 4;
534 offset = (idx - 4) * 8;
535 }
536
537 return setup_port(priv, port, bar, offset, 0);
538}
539
1da177e4
LT		 540/*
541 * Timedia has an explosion of boards, and to avoid the PCI table from
542 * growing *huge*, we use this function to collapse some 70 entries
543 * in the PCI table into one, for sanity's and compactness's sake.
544 */
e9422e09 545static const unsigned short timedia_single_port[] = {
1da177e4
LT		 546 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
547};
548
e9422e09 549static const unsigned short timedia_dual_port[] = {
1da177e4 550 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
5756ee99
AC		 551 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
552 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1da177e4
LT		 553 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
554 0xD079, 0
555};
556
e9422e09 557static const unsigned short timedia_quad_port[] = {
5756ee99
AC		 558 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
559 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1da177e4
LT		 560 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
561 0xB157, 0
562};
563
e9422e09 564static const unsigned short timedia_eight_port[] = {
5756ee99 565 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1da177e4
LT		 566 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
567};
568
cb3592be 569static const struct timedia_struct {
1da177e4 570 int num;
e9422e09 571 const unsigned short *ids;
1da177e4
LT		 572} timedia_data[] = {
573 { 1, timedia_single_port },
574 { 2, timedia_dual_port },
575 { 4, timedia_quad_port },
e9422e09 576 { 8, timedia_eight_port }
1da177e4
LT		 577};
578
b9b24558
FB		 579/*
580 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
581 * listing them individually, this driver merely grabs them all with
582 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
583 * and should be left free to be claimed by parport_serial instead.
584 */
585static int pci_timedia_probe(struct pci_dev *dev)
586{
587 /*
588 * Check the third digit of the subdevice ID
589 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
590 */
591 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
592 dev_info(&dev->dev,
593 "ignoring Timedia subdevice %04x for parport_serial\n",
594 dev->subsystem_device);
595 return -ENODEV;
596 }
597
598 return 0;
599}
600
61a116ef 601static int pci_timedia_init(struct pci_dev *dev)
1da177e4 602{
e9422e09 603 const unsigned short *ids;
1da177e4
LT		 604 int i, j;
605
e9422e09 606 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
1da177e4
LT		 607 ids = timedia_data[i].ids;
608 for (j = 0; ids[j]; j++)
609 if (dev->subsystem_device == ids[j])
610 return timedia_data[i].num;
611 }
612 return 0;
613}
614
615/*
616 * Timedia/SUNIX uses a mixture of BARs and offsets
617 * Ugh, this is ugly as all hell --- TYT
618 */
619static int
975a1a7d
RK		 620pci_timedia_setup(struct serial_private *priv,
621 const struct pciserial_board *board,
2655a2c7 622 struct uart_8250_port *port, int idx)
1da177e4
LT		 623{
624 unsigned int bar = 0, offset = board->first_offset;
625
626 switch (idx) {
627 case 0:
628 bar = 0;
629 break;
630 case 1:
631 offset = board->uart_offset;
632 bar = 0;
633 break;
634 case 2:
635 bar = 1;
636 break;
637 case 3:
638 offset = board->uart_offset;
c2cd6d3c 639 /* FALLTHROUGH */
1da177e4
LT		 640 case 4: /* BAR 2 */
641 case 5: /* BAR 3 */
642 case 6: /* BAR 4 */
643 case 7: /* BAR 5 */
644 bar = idx - 2;
645 }
646
70db3d91 647 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 648}
649
650/*
651 * Some Titan cards are also a little weird
652 */
653static int
70db3d91 654titan_400l_800l_setup(struct serial_private *priv,
975a1a7d 655 const struct pciserial_board *board,
2655a2c7 656 struct uart_8250_port *port, int idx)
1da177e4
LT		 657{
658 unsigned int bar, offset = board->first_offset;
659
660 switch (idx) {
661 case 0:
662 bar = 1;
663 break;
664 case 1:
665 bar = 2;
666 break;
667 default:
668 bar = 4;
669 offset = (idx - 2) * board->uart_offset;
670 }
671
70db3d91 672 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 673}
674
61a116ef 675static int pci_xircom_init(struct pci_dev *dev)
1da177e4
LT		 676{
677 msleep(100);
678 return 0;
679}
680
04bf7e74
WP		 681static int pci_ni8420_init(struct pci_dev *dev)
682{
683 void __iomem *p;
684 unsigned long base, len;
685 unsigned int bar = 0;
686
687 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
688 moan_device("no memory in bar", dev);
689 return 0;
690 }
691
692 base = pci_resource_start(dev, bar);
693 len = pci_resource_len(dev, bar);
694 p = ioremap_nocache(base, len);
695 if (p == NULL)
696 return -ENOMEM;
697
698 /* Enable CPU Interrupt */
699 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
700 p + NI8420_INT_ENABLE_REG);
701
702 iounmap(p);
703 return 0;
704}
705
46a0fac9
SB		 706#define MITE_IOWBSR1_WSIZE 0xa
707#define MITE_IOWBSR1_WIN_OFFSET 0x800
708#define MITE_IOWBSR1_WENAB (1 << 7)
709#define MITE_LCIMR1_IO_IE_0 (1 << 24)
710#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
711#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
712
713static int pci_ni8430_init(struct pci_dev *dev)
714{
715 void __iomem *p;
716 unsigned long base, len;
717 u32 device_window;
718 unsigned int bar = 0;
719
720 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
721 moan_device("no memory in bar", dev);
722 return 0;
723 }
724
725 base = pci_resource_start(dev, bar);
726 len = pci_resource_len(dev, bar);
727 p = ioremap_nocache(base, len);
728 if (p == NULL)
729 return -ENOMEM;
730
731 /* Set device window address and size in BAR0 */
732 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
733 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
734 writel(device_window, p + MITE_IOWBSR1);
735
736 /* Set window access to go to RAMSEL IO address space */
737 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
738 p + MITE_IOWCR1);
739
740 /* Enable IO Bus Interrupt 0 */
741 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
742
743 /* Enable CPU Interrupt */
744 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
745
746 iounmap(p);
747 return 0;
748}
749
750/* UART Port Control Register */
751#define NI8430_PORTCON 0x0f
752#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
753
754static int
bf538fe4
AC		 755pci_ni8430_setup(struct serial_private *priv,
756 const struct pciserial_board *board,
2655a2c7 757 struct uart_8250_port *port, int idx)
46a0fac9
SB		 758{
759 void __iomem *p;
760 unsigned long base, len;
761 unsigned int bar, offset = board->first_offset;
762
763 if (idx >= board->num_ports)
764 return 1;
765
766 bar = FL_GET_BASE(board->flags);
767 offset += idx * board->uart_offset;
768
769 base = pci_resource_start(priv->dev, bar);
770 len = pci_resource_len(priv->dev, bar);
771 p = ioremap_nocache(base, len);
772
7c9d440e 773 /* enable the transceiver */
46a0fac9
SB		 774 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
775 p + offset + NI8430_PORTCON);
776
777 iounmap(p);
778
779 return setup_port(priv, port, bar, offset, board->reg_shift);
780}
781
7808edcd
NG		 782static int pci_netmos_9900_setup(struct serial_private *priv,
783 const struct pciserial_board *board,
2655a2c7 784 struct uart_8250_port *port, int idx)
7808edcd
NG		 785{
786 unsigned int bar;
787
788 if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
789 /* netmos apparently orders BARs by datasheet layout, so serial
790 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
791 */
792 bar = 3 * idx;
793
794 return setup_port(priv, port, bar, 0, board->reg_shift);
795 } else {
796 return pci_default_setup(priv, board, port, idx);
797 }
798}
799
800/* the 99xx series comes with a range of device IDs and a variety
801 * of capabilities:
802 *
803 * 9900 has varying capabilities and can cascade to sub-controllers
804 * (cascading should be purely internal)
805 * 9904 is hardwired with 4 serial ports
806 * 9912 and 9922 are hardwired with 2 serial ports
807 */
808static int pci_netmos_9900_numports(struct pci_dev *dev)
809{
810 unsigned int c = dev->class;
811 unsigned int pi;
812 unsigned short sub_serports;
813
814 pi = (c & 0xff);
815
816 if (pi == 2) {
817 return 1;
818 } else if ((pi == 0) &&
819 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
820 /* two possibilities: 0x30ps encodes number of parallel and
821 * serial ports, or 0x1000 indicates *something*. This is not
822 * immediately obvious, since the 2s1p+4s configuration seems
823 * to offer all functionality on functions 0..2, while still
824 * advertising the same function 3 as the 4s+2s1p config.
825 */
826 sub_serports = dev->subsystem_device & 0xf;
827 if (sub_serports > 0) {
828 return sub_serports;
829 } else {
830 printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
831 return 0;
832 }
833 }
834
835 moan_device("unknown NetMos/Mostech program interface", dev);
836 return 0;
837}
46a0fac9 838
61a116ef 839static int pci_netmos_init(struct pci_dev *dev)
1da177e4
LT		 840{
841 /* subdevice 0x00PS means <P> parallel, <S> serial */
842 unsigned int num_serial = dev->subsystem_device & 0xf;
843
ac6ec5b1
IS		 844 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
845 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
c4285b47 846 return 0;
7808edcd 847
25cf9bc1
JS		 848 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
849 dev->subsystem_device == 0x0299)
850 return 0;
851
7808edcd
NG		 852 switch (dev->device) { /* FALLTHROUGH on all */
853 case PCI_DEVICE_ID_NETMOS_9904:
854 case PCI_DEVICE_ID_NETMOS_9912:
855 case PCI_DEVICE_ID_NETMOS_9922:
856 case PCI_DEVICE_ID_NETMOS_9900:
857 num_serial = pci_netmos_9900_numports(dev);
858 break;
859
860 default:
861 if (num_serial == 0 ) {
862 moan_device("unknown NetMos/Mostech device", dev);
863 }
864 }
865
1da177e4
LT		 866 if (num_serial == 0)
867 return -ENODEV;
7808edcd 868
1da177e4
LT		 869 return num_serial;
870}
871
84f8c6fc 872/*
84f8c6fc
NV		 873 * These chips are available with optionally one parallel port and up to
874 * two serial ports. Unfortunately they all have the same product id.
875 *
876 * Basic configuration is done over a region of 32 I/O ports. The base
877 * ioport is called INTA or INTC, depending on docs/other drivers.
878 *
879 * The region of the 32 I/O ports is configured in POSIO0R...
880 */
881
882/* registers */
883#define ITE_887x_MISCR 0x9c
884#define ITE_887x_INTCBAR 0x78
885#define ITE_887x_UARTBAR 0x7c
886#define ITE_887x_PS0BAR 0x10
887#define ITE_887x_POSIO0 0x60
888
889/* I/O space size */
890#define ITE_887x_IOSIZE 32
891/* I/O space size (bits 26-24; 8 bytes = 011b) */
892#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
893/* I/O space size (bits 26-24; 32 bytes = 101b) */
894#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
895/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
896#define ITE_887x_POSIO_SPEED (3 << 29)
897/* enable IO_Space bit */
898#define ITE_887x_POSIO_ENABLE (1 << 31)
899
f79abb82 900static int pci_ite887x_init(struct pci_dev *dev)
84f8c6fc
NV		 901{
902 /* inta_addr are the configuration addresses of the ITE */
903 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
904 0x200, 0x280, 0 };
905 int ret, i, type;
906 struct resource *iobase = NULL;
907 u32 miscr, uartbar, ioport;
908
909 /* search for the base-ioport */
910 i = 0;
911 while (inta_addr[i] && iobase == NULL) {
912 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
913 "ite887x");
914 if (iobase != NULL) {
915 /* write POSIO0R - speed | size | ioport */
916 pci_write_config_dword(dev, ITE_887x_POSIO0,
917 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
918 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
919 /* write INTCBAR - ioport */
5756ee99
AC		 920 pci_write_config_dword(dev, ITE_887x_INTCBAR,
921 inta_addr[i]);
84f8c6fc
NV		 922 ret = inb(inta_addr[i]);
923 if (ret != 0xff) {
924 /* ioport connected */
925 break;
926 }
927 release_region(iobase->start, ITE_887x_IOSIZE);
928 iobase = NULL;
929 }
930 i++;
931 }
932
933 if (!inta_addr[i]) {
934 printk(KERN_ERR "ite887x: could not find iobase\n");
935 return -ENODEV;
936 }
937
938 /* start of undocumented type checking (see parport_pc.c) */
939 type = inb(iobase->start + 0x18) & 0x0f;
940
941 switch (type) {
942 case 0x2: /* ITE8871 (1P) */
943 case 0xa: /* ITE8875 (1P) */
944 ret = 0;
945 break;
946 case 0xe: /* ITE8872 (2S1P) */
947 ret = 2;
948 break;
949 case 0x6: /* ITE8873 (1S) */
950 ret = 1;
951 break;
952 case 0x8: /* ITE8874 (2S) */
953 ret = 2;
954 break;
955 default:
956 moan_device("Unknown ITE887x", dev);
957 ret = -ENODEV;
958 }
959
960 /* configure all serial ports */
961 for (i = 0; i < ret; i++) {
962 /* read the I/O port from the device */
963 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
964 &ioport);
965 ioport &= 0x0000FF00; /* the actual base address */
966 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
967 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
968 ITE_887x_POSIO_IOSIZE_8 | ioport);
969
970 /* write the ioport to the UARTBAR */
971 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
972 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
973 uartbar |= (ioport << (16 * i)); /* set the ioport */
974 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
975
976 /* get current config */
977 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
978 /* disable interrupts (UARTx_Routing[3:0]) */
979 miscr &= ~(0xf << (12 - 4 * i));
980 /* activate the UART (UARTx_En) */
981 miscr |= 1 << (23 - i);
982 /* write new config with activated UART */
983 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
984 }
985
986 if (ret <= 0) {
987 /* the device has no UARTs if we get here */
988 release_region(iobase->start, ITE_887x_IOSIZE);
989 }
990
991 return ret;
992}
993
ae8d8a14 994static void pci_ite887x_exit(struct pci_dev *dev)
84f8c6fc
NV		 995{
996 u32 ioport;
997 /* the ioport is bit 0-15 in POSIO0R */
998 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
999 ioport &= 0xffff;
1000 release_region(ioport, ITE_887x_IOSIZE);
1001}
1002
9f2a036a
RK		 1003/*
1004 * Oxford Semiconductor Inc.
1005 * Check that device is part of the Tornado range of devices, then determine
1006 * the number of ports available on the device.
1007 */
1008static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1009{
1010 u8 __iomem *p;
1011 unsigned long deviceID;
1012 unsigned int number_uarts = 0;
1013
1014 /* OxSemi Tornado devices are all 0xCxxx */
1015 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1016 (dev->device & 0xF000) != 0xC000)
1017 return 0;
1018
1019 p = pci_iomap(dev, 0, 5);
1020 if (p == NULL)
1021 return -ENOMEM;
1022
1023 deviceID = ioread32(p);
1024 /* Tornado device */
1025 if (deviceID == 0x07000200) {
1026 number_uarts = ioread8(p + 4);
1027 printk(KERN_DEBUG
1028 "%d ports detected on Oxford PCI Express device\n",
1029 number_uarts);
1030 }
1031 pci_iounmap(dev, p);
1032 return number_uarts;
1033}
1034
eb26dfe8
AC		 1035static int pci_asix_setup(struct serial_private *priv,
1036 const struct pciserial_board *board,
1037 struct uart_8250_port *port, int idx)
1038{
1039 port->bugs |= UART_BUG_PARITY;
1040 return pci_default_setup(priv, board, port, idx);
1041}
1042
55c7c0fd
AC		 1043/* Quatech devices have their own extra interface features */
1044
1045struct quatech_feature {
1046 u16 devid;
1047 bool amcc;
1048};
1049
1050#define QPCR_TEST_FOR1 0x3F
1051#define QPCR_TEST_GET1 0x00
1052#define QPCR_TEST_FOR2 0x40
1053#define QPCR_TEST_GET2 0x40
1054#define QPCR_TEST_FOR3 0x80
1055#define QPCR_TEST_GET3 0x40
1056#define QPCR_TEST_FOR4 0xC0
1057#define QPCR_TEST_GET4 0x80
1058
1059#define QOPR_CLOCK_X1 0x0000
1060#define QOPR_CLOCK_X2 0x0001
1061#define QOPR_CLOCK_X4 0x0002
1062#define QOPR_CLOCK_X8 0x0003
1063#define QOPR_CLOCK_RATE_MASK 0x0003
1064
1065
1066static struct quatech_feature quatech_cards[] = {
1067 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1068 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1069 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1070 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1071 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1072 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1073 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1074 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1075 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1076 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1077 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1078 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1079 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1080 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1081 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1082 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1083 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1084 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1085 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1086 { 0, }
1087};
1088
1089static int pci_quatech_amcc(u16 devid)
1090{
1091 struct quatech_feature *qf = &quatech_cards[0];
1092 while (qf->devid) {
1093 if (qf->devid == devid)
1094 return qf->amcc;
1095 qf++;
1096 }
1097 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1098 return 0;
1099};
1100
1101static int pci_quatech_rqopr(struct uart_8250_port *port)
1102{
1103 unsigned long base = port->port.iobase;
1104 u8 LCR, val;
1105
1106 LCR = inb(base + UART_LCR);
1107 outb(0xBF, base + UART_LCR);
1108 val = inb(base + UART_SCR);
1109 outb(LCR, base + UART_LCR);
1110 return val;
1111}
1112
1113static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1114{
1115 unsigned long base = port->port.iobase;
1116 u8 LCR, val;
1117
1118 LCR = inb(base + UART_LCR);
1119 outb(0xBF, base + UART_LCR);
1120 val = inb(base + UART_SCR);
1121 outb(qopr, base + UART_SCR);
1122 outb(LCR, base + UART_LCR);
1123}
1124
1125static int pci_quatech_rqmcr(struct uart_8250_port *port)
1126{
1127 unsigned long base = port->port.iobase;
1128 u8 LCR, val, qmcr;
1129
1130 LCR = inb(base + UART_LCR);
1131 outb(0xBF, base + UART_LCR);
1132 val = inb(base + UART_SCR);
1133 outb(val | 0x10, base + UART_SCR);
1134 qmcr = inb(base + UART_MCR);
1135 outb(val, base + UART_SCR);
1136 outb(LCR, base + UART_LCR);
1137
1138 return qmcr;
1139}
1140
1141static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1142{
1143 unsigned long base = port->port.iobase;
1144 u8 LCR, val;
1145
1146 LCR = inb(base + UART_LCR);
1147 outb(0xBF, base + UART_LCR);
1148 val = inb(base + UART_SCR);
1149 outb(val | 0x10, base + UART_SCR);
1150 outb(qmcr, base + UART_MCR);
1151 outb(val, base + UART_SCR);
1152 outb(LCR, base + UART_LCR);
1153}
1154
1155static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1156{
1157 unsigned long base = port->port.iobase;
1158 u8 LCR, val;
1159
1160 LCR = inb(base + UART_LCR);
1161 outb(0xBF, base + UART_LCR);
1162 val = inb(base + UART_SCR);
1163 if (val & 0x20) {
1164 outb(0x80, UART_LCR);
1165 if (!(inb(UART_SCR) & 0x20)) {
1166 outb(LCR, base + UART_LCR);
1167 return 1;
1168 }
1169 }
1170 return 0;
1171}
1172
1173static int pci_quatech_test(struct uart_8250_port *port)
1174{
1175 u8 reg;
1176 u8 qopr = pci_quatech_rqopr(port);
1177 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1178 reg = pci_quatech_rqopr(port) & 0xC0;
1179 if (reg != QPCR_TEST_GET1)
1180 return -EINVAL;
1181 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1182 reg = pci_quatech_rqopr(port) & 0xC0;
1183 if (reg != QPCR_TEST_GET2)
1184 return -EINVAL;
1185 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1186 reg = pci_quatech_rqopr(port) & 0xC0;
1187 if (reg != QPCR_TEST_GET3)
1188 return -EINVAL;
1189 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1190 reg = pci_quatech_rqopr(port) & 0xC0;
1191 if (reg != QPCR_TEST_GET4)
1192 return -EINVAL;
1193
1194 pci_quatech_wqopr(port, qopr);
1195 return 0;
1196}
1197
1198static int pci_quatech_clock(struct uart_8250_port *port)
1199{
1200 u8 qopr, reg, set;
1201 unsigned long clock;
1202
1203 if (pci_quatech_test(port) < 0)
1204 return 1843200;
1205
1206 qopr = pci_quatech_rqopr(port);
1207
1208 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1209 reg = pci_quatech_rqopr(port);
1210 if (reg & QOPR_CLOCK_X8) {
1211 clock = 1843200;
1212 goto out;
1213 }
1214 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1215 reg = pci_quatech_rqopr(port);
1216 if (!(reg & QOPR_CLOCK_X8)) {
1217 clock = 1843200;
1218 goto out;
1219 }
1220 reg &= QOPR_CLOCK_X8;
1221 if (reg == QOPR_CLOCK_X2) {
1222 clock = 3685400;
1223 set = QOPR_CLOCK_X2;
1224 } else if (reg == QOPR_CLOCK_X4) {
1225 clock = 7372800;
1226 set = QOPR_CLOCK_X4;
1227 } else if (reg == QOPR_CLOCK_X8) {
1228 clock = 14745600;
1229 set = QOPR_CLOCK_X8;
1230 } else {
1231 clock = 1843200;
1232 set = QOPR_CLOCK_X1;
1233 }
1234 qopr &= ~QOPR_CLOCK_RATE_MASK;
1235 qopr |= set;
1236
1237out:
1238 pci_quatech_wqopr(port, qopr);
1239 return clock;
1240}
1241
1242static int pci_quatech_rs422(struct uart_8250_port *port)
1243{
1244 u8 qmcr;
1245 int rs422 = 0;
1246
1247 if (!pci_quatech_has_qmcr(port))
1248 return 0;
1249 qmcr = pci_quatech_rqmcr(port);
1250 pci_quatech_wqmcr(port, 0xFF);
1251 if (pci_quatech_rqmcr(port))
1252 rs422 = 1;
1253 pci_quatech_wqmcr(port, qmcr);
1254 return rs422;
1255}
1256
1257static int pci_quatech_init(struct pci_dev *dev)
1258{
1259 if (pci_quatech_amcc(dev->device)) {
1260 unsigned long base = pci_resource_start(dev, 0);
1261 if (base) {
1262 u32 tmp;
1263 outl(inl(base + 0x38), base + 0x38);
1264 tmp = inl(base + 0x3c);
1265 outl(tmp | 0x01000000, base + 0x3c);
1266 outl(tmp, base + 0x3c);
1267 }
1268 }
1269 return 0;
1270}
1271
1272static int pci_quatech_setup(struct serial_private *priv,
1273 const struct pciserial_board *board,
1274 struct uart_8250_port *port, int idx)
1275{
1276 /* Needed by pci_quatech calls below */
1277 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1278 /* Set up the clocking */
1279 port->port.uartclk = pci_quatech_clock(port);
1280 /* For now just warn about RS422 */
1281 if (pci_quatech_rs422(port))
1282 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1283 return pci_default_setup(priv, board, port, idx);
1284}
1285
d73dfc6a 1286static void pci_quatech_exit(struct pci_dev *dev)
55c7c0fd
AC		 1287{
1288}
1289
eb26dfe8 1290static int pci_default_setup(struct serial_private *priv,
975a1a7d 1291 const struct pciserial_board *board,
2655a2c7 1292 struct uart_8250_port *port, int idx)
1da177e4
LT		 1293{
1294 unsigned int bar, offset = board->first_offset, maxnr;
1295
1296 bar = FL_GET_BASE(board->flags);
1297 if (board->flags & FL_BASE_BARS)
1298 bar += idx;
1299 else
1300 offset += idx * board->uart_offset;
1301
2427ddd8
GKH		 1302 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1303 (board->reg_shift + 3);
1da177e4
LT		 1304
1305 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1306 return 1;
5756ee99 1307
70db3d91 1308 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 1309}
1310
095e24b0
DB		 1311static int
1312ce4100_serial_setup(struct serial_private *priv,
1313 const struct pciserial_board *board,
2655a2c7 1314 struct uart_8250_port *port, int idx)
095e24b0
DB		 1315{
1316 int ret;
1317
08ec212c 1318 ret = setup_port(priv, port, idx, 0, board->reg_shift);
2655a2c7
AC		 1319 port->port.iotype = UPIO_MEM32;
1320 port->port.type = PORT_XSCALE;
1321 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1322 port->port.regshift = 2;
095e24b0
DB		 1323
1324 return ret;
1325}
1326
d9a0fbfd
AP		 1327static int
1328pci_omegapci_setup(struct serial_private *priv,
1798ca13 1329 const struct pciserial_board *board,
2655a2c7 1330 struct uart_8250_port *port, int idx)
d9a0fbfd
AP		 1331{
1332 return setup_port(priv, port, 2, idx * 8, 0);
1333}
1334
ebebd49a
SH		 1335static int
1336pci_brcm_trumanage_setup(struct serial_private *priv,
1337 const struct pciserial_board *board,
1338 struct uart_8250_port *port, int idx)
1339{
1340 int ret = pci_default_setup(priv, board, port, idx);
1341
1342 port->port.type = PORT_BRCM_TRUMANAGE;
1343 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1344 return ret;
1345}
1346
b6adea33
MCC		 1347static int skip_tx_en_setup(struct serial_private *priv,
1348 const struct pciserial_board *board,
2655a2c7 1349 struct uart_8250_port *port, int idx)
b6adea33 1350{
2655a2c7 1351 port->port.flags |= UPF_NO_TXEN_TEST;
b6adea33
MCC		 1352 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1353 "[%04x:%04x] subsystem [%04x:%04x]\n",
1354 priv->dev->vendor,
1355 priv->dev->device,
1356 priv->dev->subsystem_vendor,
1357 priv->dev->subsystem_device);
1358
1359 return pci_default_setup(priv, board, port, idx);
1360}
1361
0ad372b9
SM		 1362static void kt_handle_break(struct uart_port *p)
1363{
1364 struct uart_8250_port *up =
1365 container_of(p, struct uart_8250_port, port);
1366 /*
1367 * On receipt of a BI, serial device in Intel ME (Intel
1368 * management engine) needs to have its fifos cleared for sane
1369 * SOL (Serial Over Lan) output.
1370 */
1371 serial8250_clear_and_reinit_fifos(up);
1372}
1373
1374static unsigned int kt_serial_in(struct uart_port *p, int offset)
1375{
1376 struct uart_8250_port *up =
1377 container_of(p, struct uart_8250_port, port);
1378 unsigned int val;
1379
1380 /*
1381 * When the Intel ME (management engine) gets reset its serial
1382 * port registers could return 0 momentarily. Functions like
1383 * serial8250_console_write, read and save the IER, perform
1384 * some operation and then restore it. In order to avoid
1385 * setting IER register inadvertently to 0, if the value read
1386 * is 0, double check with ier value in uart_8250_port and use
1387 * that instead. up->ier should be the same value as what is
1388 * currently configured.
1389 */
1390 val = inb(p->iobase + offset);
1391 if (offset == UART_IER) {
1392 if (val == 0)
1393 val = up->ier;
1394 }
1395 return val;
1396}
1397
bc02d15a
DW		 1398static int kt_serial_setup(struct serial_private *priv,
1399 const struct pciserial_board *board,
2655a2c7 1400 struct uart_8250_port *port, int idx)
bc02d15a 1401{
2655a2c7
AC		 1402 port->port.flags |= UPF_BUG_THRE;
1403 port->port.serial_in = kt_serial_in;
1404 port->port.handle_break = kt_handle_break;
bc02d15a
DW		 1405 return skip_tx_en_setup(priv, board, port, idx);
1406}
1407
eb7073db
TM		 1408static int pci_eg20t_init(struct pci_dev *dev)
1409{
1410#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1411 return -ENODEV;
1412#else
1413 return 0;
1414#endif
1415}
1416
06315348
SH		 1417static int
1418pci_xr17c154_setup(struct serial_private *priv,
1419 const struct pciserial_board *board,
2655a2c7 1420 struct uart_8250_port *port, int idx)
06315348 1421{
2655a2c7 1422 port->port.flags |= UPF_EXAR_EFR;
06315348
SH		 1423 return pci_default_setup(priv, board, port, idx);
1424}
1425
dc96efb7
MS		 1426static int
1427pci_xr17v35x_setup(struct serial_private *priv,
1428 const struct pciserial_board *board,
1429 struct uart_8250_port *port, int idx)
1430{
1431 u8 __iomem *p;
1432
1433 p = pci_ioremap_bar(priv->dev, 0);
13c3237d
MS		 1434 if (p == NULL)
1435 return -ENOMEM;
dc96efb7
MS		 1436
1437 port->port.flags |= UPF_EXAR_EFR;
1438
1439 /*
1440 * Setup Multipurpose Input/Output pins.
1441 */
1442 if (idx == 0) {
1443 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1444 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1445 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1446 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1447 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1448 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1449 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1450 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1451 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1452 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1453 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1454 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1455 }
f965b9c4
MS		 1456 writeb(0x00, p + UART_EXAR_8XMODE);
1457 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1458 writeb(128, p + UART_EXAR_TXTRG);
1459 writeb(128, p + UART_EXAR_RXTRG);
dc96efb7
MS		 1460 iounmap(p);
1461
1462 return pci_default_setup(priv, board, port, idx);
1463}
1464
14faa8cc
MS		 1465#define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1466#define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1467#define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1468#define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1469
1470static int
1471pci_fastcom335_setup(struct serial_private *priv,
1472 const struct pciserial_board *board,
1473 struct uart_8250_port *port, int idx)
1474{
1475 u8 __iomem *p;
1476
1477 p = pci_ioremap_bar(priv->dev, 0);
1478 if (p == NULL)
1479 return -ENOMEM;
1480
1481 port->port.flags |= UPF_EXAR_EFR;
1482
1483 /*
1484 * Setup Multipurpose Input/Output pins.
1485 */
1486 if (idx == 0) {
1487 switch (priv->dev->device) {
1488 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1489 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1490 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1491 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1492 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1493 break;
1494 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1495 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1496 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1497 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1498 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1499 break;
1500 }
1501 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1502 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1503 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1504 }
1505 writeb(0x00, p + UART_EXAR_8XMODE);
1506 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1507 writeb(32, p + UART_EXAR_TXTRG);
1508 writeb(32, p + UART_EXAR_RXTRG);
1509 iounmap(p);
1510
1511 return pci_default_setup(priv, board, port, idx);
1512}
1513
6971c635
GA		 1514static int
1515pci_wch_ch353_setup(struct serial_private *priv,
1516 const struct pciserial_board *board,
1517 struct uart_8250_port *port, int idx)
1518{
1519 port->port.flags |= UPF_FIXED_TYPE;
1520 port->port.type = PORT_16550A;
06315348
SH		 1521 return pci_default_setup(priv, board, port, idx);
1522}
1523
1da177e4
LT		 1524#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1525#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1526#define PCI_DEVICE_ID_OCTPRO 0x0001
1527#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1528#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1529#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1530#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
26e8220a
FL		 1531#define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1532#define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
78d70d48 1533#define PCI_VENDOR_ID_ADVANTECH 0x13fe
095e24b0 1534#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
78d70d48 1535#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
66169ad1
YY		 1536#define PCI_DEVICE_ID_TITAN_200I 0x8028
1537#define PCI_DEVICE_ID_TITAN_400I 0x8048
1538#define PCI_DEVICE_ID_TITAN_800I 0x8088
1539#define PCI_DEVICE_ID_TITAN_800EH 0xA007
1540#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1541#define PCI_DEVICE_ID_TITAN_400EH 0xA009
1542#define PCI_DEVICE_ID_TITAN_100E 0xA010
1543#define PCI_DEVICE_ID_TITAN_200E 0xA012
1544#define PCI_DEVICE_ID_TITAN_400E 0xA013
1545#define PCI_DEVICE_ID_TITAN_800E 0xA014
1546#define PCI_DEVICE_ID_TITAN_200EI 0xA016
1547#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1e9deb11
YY		 1548#define PCI_DEVICE_ID_TITAN_400V3 0xA310
1549#define PCI_DEVICE_ID_TITAN_410V3 0xA312
1550#define PCI_DEVICE_ID_TITAN_800V3 0xA314
1551#define PCI_DEVICE_ID_TITAN_800V3B 0xA315
e847003f 1552#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
aa273ae5 1553#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
d9a0fbfd 1554#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
bc02d15a 1555#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
27788c5f 1556#define PCI_VENDOR_ID_WCH 0x4348
8b5c913f 1557#define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
27788c5f
AC		 1558#define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1559#define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1560#define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
6683549e
AC		 1561#define PCI_VENDOR_ID_AGESTAR 0x5372
1562#define PCI_DEVICE_ID_AGESTAR_9375 0x6872
eb26dfe8 1563#define PCI_VENDOR_ID_ASIX 0x9710
14faa8cc
MS		 1564#define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1565#define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
b7b9041b 1566#define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
ebebd49a 1567#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
14faa8cc 1568
abd7baca
SC		 1569#define PCI_VENDOR_ID_SUNIX 0x1fd4
1570#define PCI_DEVICE_ID_SUNIX_1999 0x1999
1571
1da177e4 1572
b76c5a07
CB		 1573/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1574#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
d13402a4 1575#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
b76c5a07 1576
1da177e4
LT		 1577/*
1578 * Master list of serial port init/setup/exit quirks.
1579 * This does not describe the general nature of the port.
1580 * (ie, baud base, number and location of ports, etc)
1581 *
1582 * This list is ordered alphabetically by vendor then device.
1583 * Specific entries must come before more generic entries.
1584 */
7a63ce5a 1585static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
02c9b5cf
KJ		 1586 /*
1587 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1588 */
1589 {
1590 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1591 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1592 .subvendor = PCI_ANY_ID,
1593 .subdevice = PCI_ANY_ID,
1594 .setup = addidata_apci7800_setup,
1595 },
1da177e4 1596 /*
61a116ef 1597 * AFAVLAB cards - these may be called via parport_serial
1da177e4
LT		 1598 * It is not clear whether this applies to all products.
1599 */
1600 {
1601 .vendor = PCI_VENDOR_ID_AFAVLAB,
1602 .device = PCI_ANY_ID,
1603 .subvendor = PCI_ANY_ID,
1604 .subdevice = PCI_ANY_ID,
1605 .setup = afavlab_setup,
1606 },
1607 /*
1608 * HP Diva
1609 */
1610 {
1611 .vendor = PCI_VENDOR_ID_HP,
1612 .device = PCI_DEVICE_ID_HP_DIVA,
1613 .subvendor = PCI_ANY_ID,
1614 .subdevice = PCI_ANY_ID,
1615 .init = pci_hp_diva_init,
1616 .setup = pci_hp_diva_setup,
1617 },
1618 /*
1619 * Intel
1620 */
1621 {
1622 .vendor = PCI_VENDOR_ID_INTEL,
1623 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1624 .subvendor = 0xe4bf,
1625 .subdevice = PCI_ANY_ID,
1626 .init = pci_inteli960ni_init,
1627 .setup = pci_default_setup,
1628 },
b6adea33
MCC		 1629 {
1630 .vendor = PCI_VENDOR_ID_INTEL,
1631 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1632 .subvendor = PCI_ANY_ID,
1633 .subdevice = PCI_ANY_ID,
1634 .setup = skip_tx_en_setup,
1635 },
1636 {
1637 .vendor = PCI_VENDOR_ID_INTEL,
1638 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1639 .subvendor = PCI_ANY_ID,
1640 .subdevice = PCI_ANY_ID,
1641 .setup = skip_tx_en_setup,
1642 },
1643 {
1644 .vendor = PCI_VENDOR_ID_INTEL,
1645 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1646 .subvendor = PCI_ANY_ID,
1647 .subdevice = PCI_ANY_ID,
1648 .setup = skip_tx_en_setup,
1649 },
095e24b0
DB		 1650 {
1651 .vendor = PCI_VENDOR_ID_INTEL,
1652 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1653 .subvendor = PCI_ANY_ID,
1654 .subdevice = PCI_ANY_ID,
1655 .setup = ce4100_serial_setup,
1656 },
bc02d15a
DW		 1657 {
1658 .vendor = PCI_VENDOR_ID_INTEL,
1659 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1660 .subvendor = PCI_ANY_ID,
1661 .subdevice = PCI_ANY_ID,
1662 .setup = kt_serial_setup,
1663 },
84f8c6fc
NV		 1664 /*
1665 * ITE
1666 */
1667 {
1668 .vendor = PCI_VENDOR_ID_ITE,
1669 .device = PCI_DEVICE_ID_ITE_8872,
1670 .subvendor = PCI_ANY_ID,
1671 .subdevice = PCI_ANY_ID,
1672 .init = pci_ite887x_init,
1673 .setup = pci_default_setup,
2d47b716 1674 .exit = pci_ite887x_exit,
84f8c6fc 1675 },
46a0fac9
SB		 1676 /*
1677 * National Instruments
1678 */
04bf7e74
WP		 1679 {
1680 .vendor = PCI_VENDOR_ID_NI,
1681 .device = PCI_DEVICE_ID_NI_PCI23216,
1682 .subvendor = PCI_ANY_ID,
1683 .subdevice = PCI_ANY_ID,
1684 .init = pci_ni8420_init,
1685 .setup = pci_default_setup,
2d47b716 1686 .exit = pci_ni8420_exit,
04bf7e74
WP		 1687 },
1688 {
1689 .vendor = PCI_VENDOR_ID_NI,
1690 .device = PCI_DEVICE_ID_NI_PCI2328,
1691 .subvendor = PCI_ANY_ID,
1692 .subdevice = PCI_ANY_ID,
1693 .init = pci_ni8420_init,
1694 .setup = pci_default_setup,
2d47b716 1695 .exit = pci_ni8420_exit,
04bf7e74
WP		 1696 },
1697 {
1698 .vendor = PCI_VENDOR_ID_NI,
1699 .device = PCI_DEVICE_ID_NI_PCI2324,
1700 .subvendor = PCI_ANY_ID,
1701 .subdevice = PCI_ANY_ID,
1702 .init = pci_ni8420_init,
1703 .setup = pci_default_setup,
2d47b716 1704 .exit = pci_ni8420_exit,
04bf7e74
WP		 1705 },
1706 {
1707 .vendor = PCI_VENDOR_ID_NI,
1708 .device = PCI_DEVICE_ID_NI_PCI2322,
1709 .subvendor = PCI_ANY_ID,
1710 .subdevice = PCI_ANY_ID,
1711 .init = pci_ni8420_init,
1712 .setup = pci_default_setup,
2d47b716 1713 .exit = pci_ni8420_exit,
04bf7e74
WP		 1714 },
1715 {
1716 .vendor = PCI_VENDOR_ID_NI,
1717 .device = PCI_DEVICE_ID_NI_PCI2324I,
1718 .subvendor = PCI_ANY_ID,
1719 .subdevice = PCI_ANY_ID,
1720 .init = pci_ni8420_init,
1721 .setup = pci_default_setup,
2d47b716 1722 .exit = pci_ni8420_exit,
04bf7e74
WP		 1723 },
1724 {
1725 .vendor = PCI_VENDOR_ID_NI,
1726 .device = PCI_DEVICE_ID_NI_PCI2322I,
1727 .subvendor = PCI_ANY_ID,
1728 .subdevice = PCI_ANY_ID,
1729 .init = pci_ni8420_init,
1730 .setup = pci_default_setup,
2d47b716 1731 .exit = pci_ni8420_exit,
04bf7e74
WP		 1732 },
1733 {
1734 .vendor = PCI_VENDOR_ID_NI,
1735 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1736 .subvendor = PCI_ANY_ID,
1737 .subdevice = PCI_ANY_ID,
1738 .init = pci_ni8420_init,
1739 .setup = pci_default_setup,
2d47b716 1740 .exit = pci_ni8420_exit,
04bf7e74
WP		 1741 },
1742 {
1743 .vendor = PCI_VENDOR_ID_NI,
1744 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1745 .subvendor = PCI_ANY_ID,
1746 .subdevice = PCI_ANY_ID,
1747 .init = pci_ni8420_init,
1748 .setup = pci_default_setup,
2d47b716 1749 .exit = pci_ni8420_exit,
04bf7e74
WP		 1750 },
1751 {
1752 .vendor = PCI_VENDOR_ID_NI,
1753 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1754 .subvendor = PCI_ANY_ID,
1755 .subdevice = PCI_ANY_ID,
1756 .init = pci_ni8420_init,
1757 .setup = pci_default_setup,
2d47b716 1758 .exit = pci_ni8420_exit,
04bf7e74
WP		 1759 },
1760 {
1761 .vendor = PCI_VENDOR_ID_NI,
1762 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1763 .subvendor = PCI_ANY_ID,
1764 .subdevice = PCI_ANY_ID,
1765 .init = pci_ni8420_init,
1766 .setup = pci_default_setup,
2d47b716 1767 .exit = pci_ni8420_exit,
04bf7e74
WP		 1768 },
1769 {
1770 .vendor = PCI_VENDOR_ID_NI,
1771 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1772 .subvendor = PCI_ANY_ID,
1773 .subdevice = PCI_ANY_ID,
1774 .init = pci_ni8420_init,
1775 .setup = pci_default_setup,
2d47b716 1776 .exit = pci_ni8420_exit,
04bf7e74
WP		 1777 },
1778 {
1779 .vendor = PCI_VENDOR_ID_NI,
1780 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1781 .subvendor = PCI_ANY_ID,
1782 .subdevice = PCI_ANY_ID,
1783 .init = pci_ni8420_init,
1784 .setup = pci_default_setup,
2d47b716 1785 .exit = pci_ni8420_exit,
04bf7e74 1786 },
46a0fac9
SB		 1787 {
1788 .vendor = PCI_VENDOR_ID_NI,
1789 .device = PCI_ANY_ID,
1790 .subvendor = PCI_ANY_ID,
1791 .subdevice = PCI_ANY_ID,
1792 .init = pci_ni8430_init,
1793 .setup = pci_ni8430_setup,
2d47b716 1794 .exit = pci_ni8430_exit,
46a0fac9 1795 },
55c7c0fd
AC		 1796 /* Quatech */
1797 {
1798 .vendor = PCI_VENDOR_ID_QUATECH,
1799 .device = PCI_ANY_ID,
1800 .subvendor = PCI_ANY_ID,
1801 .subdevice = PCI_ANY_ID,
1802 .init = pci_quatech_init,
1803 .setup = pci_quatech_setup,
d73dfc6a 1804 .exit = pci_quatech_exit,
55c7c0fd 1805 },
1da177e4
LT		 1806 /*
1807 * Panacom
1808 */
1809 {
1810 .vendor = PCI_VENDOR_ID_PANACOM,
1811 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1812 .subvendor = PCI_ANY_ID,
1813 .subdevice = PCI_ANY_ID,
1814 .init = pci_plx9050_init,
1815 .setup = pci_default_setup,
2d47b716 1816 .exit = pci_plx9050_exit,
5756ee99 1817 },
1da177e4
LT		 1818 {
1819 .vendor = PCI_VENDOR_ID_PANACOM,
1820 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1821 .subvendor = PCI_ANY_ID,
1822 .subdevice = PCI_ANY_ID,
1823 .init = pci_plx9050_init,
1824 .setup = pci_default_setup,
2d47b716 1825 .exit = pci_plx9050_exit,
1da177e4
LT		 1826 },
1827 /*
1828 * PLX
1829 */
48212008
TH		 1830 {
1831 .vendor = PCI_VENDOR_ID_PLX,
1832 .device = PCI_DEVICE_ID_PLX_9030,
1833 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1834 .subdevice = PCI_ANY_ID,
1835 .setup = pci_default_setup,
1836 },
add7b58e
BH		 1837 {
1838 .vendor = PCI_VENDOR_ID_PLX,
1839 .device = PCI_DEVICE_ID_PLX_9050,
1840 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1841 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1842 .init = pci_plx9050_init,
1843 .setup = pci_default_setup,
2d47b716 1844 .exit = pci_plx9050_exit,
add7b58e 1845 },
1da177e4
LT		 1846 {
1847 .vendor = PCI_VENDOR_ID_PLX,
1848 .device = PCI_DEVICE_ID_PLX_9050,
1849 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1850 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1851 .init = pci_plx9050_init,
1852 .setup = pci_default_setup,
2d47b716 1853 .exit = pci_plx9050_exit,
1da177e4
LT		 1854 },
1855 {
1856 .vendor = PCI_VENDOR_ID_PLX,
1857 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1858 .subvendor = PCI_VENDOR_ID_PLX,
1859 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1860 .init = pci_plx9050_init,
1861 .setup = pci_default_setup,
2d47b716 1862 .exit = pci_plx9050_exit,
1da177e4
LT		 1863 },
1864 /*
1865 * SBS Technologies, Inc., PMC-OCTALPRO 232
1866 */
1867 {
1868 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1869 .device = PCI_DEVICE_ID_OCTPRO,
1870 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1871 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1872 .init = sbs_init,
1873 .setup = sbs_setup,
2d47b716 1874 .exit = sbs_exit,
1da177e4
LT		 1875 },
1876 /*
1877 * SBS Technologies, Inc., PMC-OCTALPRO 422
1878 */
1879 {
1880 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1881 .device = PCI_DEVICE_ID_OCTPRO,
1882 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1883 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1884 .init = sbs_init,
1885 .setup = sbs_setup,
2d47b716 1886 .exit = sbs_exit,
1da177e4
LT		 1887 },
1888 /*
1889 * SBS Technologies, Inc., P-Octal 232
1890 */
1891 {
1892 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1893 .device = PCI_DEVICE_ID_OCTPRO,
1894 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1895 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1896 .init = sbs_init,
1897 .setup = sbs_setup,
2d47b716 1898 .exit = sbs_exit,
1da177e4
LT		 1899 },
1900 /*
1901 * SBS Technologies, Inc., P-Octal 422
1902 */
1903 {
1904 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1905 .device = PCI_DEVICE_ID_OCTPRO,
1906 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1907 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1908 .init = sbs_init,
1909 .setup = sbs_setup,
2d47b716 1910 .exit = sbs_exit,
1da177e4 1911 },
1da177e4 1912 /*
61a116ef 1913 * SIIG cards - these may be called via parport_serial
1da177e4
LT		 1914 */
1915 {
1916 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 1917 .device = PCI_ANY_ID,
1da177e4
LT		 1918 .subvendor = PCI_ANY_ID,
1919 .subdevice = PCI_ANY_ID,
67d74b87 1920 .init = pci_siig_init,
3ec9c594 1921 .setup = pci_siig_setup,
1da177e4
LT		 1922 },
1923 /*
1924 * Titan cards
1925 */
1926 {
1927 .vendor = PCI_VENDOR_ID_TITAN,
1928 .device = PCI_DEVICE_ID_TITAN_400L,
1929 .subvendor = PCI_ANY_ID,
1930 .subdevice = PCI_ANY_ID,
1931 .setup = titan_400l_800l_setup,
1932 },
1933 {
1934 .vendor = PCI_VENDOR_ID_TITAN,
1935 .device = PCI_DEVICE_ID_TITAN_800L,
1936 .subvendor = PCI_ANY_ID,
1937 .subdevice = PCI_ANY_ID,
1938 .setup = titan_400l_800l_setup,
1939 },
1940 /*
1941 * Timedia cards
1942 */
1943 {
1944 .vendor = PCI_VENDOR_ID_TIMEDIA,
1945 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1946 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1947 .subdevice = PCI_ANY_ID,
b9b24558 1948 .probe = pci_timedia_probe,
1da177e4
LT		 1949 .init = pci_timedia_init,
1950 .setup = pci_timedia_setup,
1951 },
1952 {
1953 .vendor = PCI_VENDOR_ID_TIMEDIA,
1954 .device = PCI_ANY_ID,
1955 .subvendor = PCI_ANY_ID,
1956 .subdevice = PCI_ANY_ID,
1957 .setup = pci_timedia_setup,
1958 },
abd7baca
SC		 1959 /*
1960 * SUNIX (Timedia) cards
1961 * Do not "probe" for these cards as there is at least one combination
1962 * card that should be handled by parport_pc that doesn't match the
1963 * rule in pci_timedia_probe.
1964 * It is part number is MIO5079A but its subdevice ID is 0x0102.
1965 * There are some boards with part number SER5037AL that report
1966 * subdevice ID 0x0002.
1967 */
1968 {
1969 .vendor = PCI_VENDOR_ID_SUNIX,
1970 .device = PCI_DEVICE_ID_SUNIX_1999,
1971 .subvendor = PCI_VENDOR_ID_SUNIX,
1972 .subdevice = PCI_ANY_ID,
1973 .init = pci_timedia_init,
1974 .setup = pci_timedia_setup,
1975 },
06315348
SH		 1976 /*
1977 * Exar cards
1978 */
1979 {
1980 .vendor = PCI_VENDOR_ID_EXAR,
1981 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1982 .subvendor = PCI_ANY_ID,
1983 .subdevice = PCI_ANY_ID,
1984 .setup = pci_xr17c154_setup,
1985 },
1986 {
1987 .vendor = PCI_VENDOR_ID_EXAR,
1988 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1989 .subvendor = PCI_ANY_ID,
1990 .subdevice = PCI_ANY_ID,
1991 .setup = pci_xr17c154_setup,
1992 },
1993 {
1994 .vendor = PCI_VENDOR_ID_EXAR,
1995 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1996 .subvendor = PCI_ANY_ID,
1997 .subdevice = PCI_ANY_ID,
1998 .setup = pci_xr17c154_setup,
1999 },
dc96efb7
MS		 2000 {
2001 .vendor = PCI_VENDOR_ID_EXAR,
2002 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2003 .subvendor = PCI_ANY_ID,
2004 .subdevice = PCI_ANY_ID,
2005 .setup = pci_xr17v35x_setup,
2006 },
2007 {
2008 .vendor = PCI_VENDOR_ID_EXAR,
2009 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2010 .subvendor = PCI_ANY_ID,
2011 .subdevice = PCI_ANY_ID,
2012 .setup = pci_xr17v35x_setup,
2013 },
2014 {
2015 .vendor = PCI_VENDOR_ID_EXAR,
2016 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2017 .subvendor = PCI_ANY_ID,
2018 .subdevice = PCI_ANY_ID,
2019 .setup = pci_xr17v35x_setup,
2020 },
1da177e4
LT		 2021 /*
2022 * Xircom cards
2023 */
2024 {
2025 .vendor = PCI_VENDOR_ID_XIRCOM,
2026 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2027 .subvendor = PCI_ANY_ID,
2028 .subdevice = PCI_ANY_ID,
2029 .init = pci_xircom_init,
2030 .setup = pci_default_setup,
2031 },
2032 /*
61a116ef 2033 * Netmos cards - these may be called via parport_serial
1da177e4
LT		 2034 */
2035 {
2036 .vendor = PCI_VENDOR_ID_NETMOS,
2037 .device = PCI_ANY_ID,
2038 .subvendor = PCI_ANY_ID,
2039 .subdevice = PCI_ANY_ID,
2040 .init = pci_netmos_init,
7808edcd 2041 .setup = pci_netmos_9900_setup,
1da177e4 2042 },
9f2a036a 2043 /*
aa273ae5 2044 * For Oxford Semiconductor Tornado based devices
9f2a036a
RK		 2045 */
2046 {
2047 .vendor = PCI_VENDOR_ID_OXSEMI,
2048 .device = PCI_ANY_ID,
2049 .subvendor = PCI_ANY_ID,
2050 .subdevice = PCI_ANY_ID,
2051 .init = pci_oxsemi_tornado_init,
2052 .setup = pci_default_setup,
2053 },
2054 {
2055 .vendor = PCI_VENDOR_ID_MAINPINE,
2056 .device = PCI_ANY_ID,
2057 .subvendor = PCI_ANY_ID,
2058 .subdevice = PCI_ANY_ID,
2059 .init = pci_oxsemi_tornado_init,
2060 .setup = pci_default_setup,
2061 },
aa273ae5
SK		 2062 {
2063 .vendor = PCI_VENDOR_ID_DIGI,
2064 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2065 .subvendor = PCI_SUBVENDOR_ID_IBM,
2066 .subdevice = PCI_ANY_ID,
2067 .init = pci_oxsemi_tornado_init,
2068 .setup = pci_default_setup,
2069 },
eb7073db
TM		 2070 {
2071 .vendor = PCI_VENDOR_ID_INTEL,
2072 .device = 0x8811,
aaa10eb1
AP		 2073 .subvendor = PCI_ANY_ID,
2074 .subdevice = PCI_ANY_ID,
eb7073db 2075 .init = pci_eg20t_init,
64d91cfa 2076 .setup = pci_default_setup,
eb7073db
TM		 2077 },
2078 {
2079 .vendor = PCI_VENDOR_ID_INTEL,
2080 .device = 0x8812,
aaa10eb1
AP		 2081 .subvendor = PCI_ANY_ID,
2082 .subdevice = PCI_ANY_ID,
eb7073db 2083 .init = pci_eg20t_init,
64d91cfa 2084 .setup = pci_default_setup,
eb7073db
TM		 2085 },
2086 {
2087 .vendor = PCI_VENDOR_ID_INTEL,
2088 .device = 0x8813,
aaa10eb1
AP		 2089 .subvendor = PCI_ANY_ID,
2090 .subdevice = PCI_ANY_ID,
eb7073db 2091 .init = pci_eg20t_init,
64d91cfa 2092 .setup = pci_default_setup,
eb7073db
TM		 2093 },
2094 {
2095 .vendor = PCI_VENDOR_ID_INTEL,
2096 .device = 0x8814,
aaa10eb1
AP		 2097 .subvendor = PCI_ANY_ID,
2098 .subdevice = PCI_ANY_ID,
eb7073db 2099 .init = pci_eg20t_init,
64d91cfa 2100 .setup = pci_default_setup,
eb7073db
TM		 2101 },
2102 {
2103 .vendor = 0x10DB,
2104 .device = 0x8027,
aaa10eb1
AP		 2105 .subvendor = PCI_ANY_ID,
2106 .subdevice = PCI_ANY_ID,
eb7073db 2107 .init = pci_eg20t_init,
64d91cfa 2108 .setup = pci_default_setup,
eb7073db
TM		 2109 },
2110 {
2111 .vendor = 0x10DB,
2112 .device = 0x8028,
aaa10eb1
AP		 2113 .subvendor = PCI_ANY_ID,
2114 .subdevice = PCI_ANY_ID,
eb7073db 2115 .init = pci_eg20t_init,
64d91cfa 2116 .setup = pci_default_setup,
eb7073db
TM		 2117 },
2118 {
2119 .vendor = 0x10DB,
2120 .device = 0x8029,
aaa10eb1
AP		 2121 .subvendor = PCI_ANY_ID,
2122 .subdevice = PCI_ANY_ID,
eb7073db 2123 .init = pci_eg20t_init,
64d91cfa 2124 .setup = pci_default_setup,
eb7073db
TM		 2125 },
2126 {
2127 .vendor = 0x10DB,
2128 .device = 0x800C,
aaa10eb1
AP		 2129 .subvendor = PCI_ANY_ID,
2130 .subdevice = PCI_ANY_ID,
eb7073db 2131 .init = pci_eg20t_init,
64d91cfa 2132 .setup = pci_default_setup,
eb7073db
TM		 2133 },
2134 {
2135 .vendor = 0x10DB,
2136 .device = 0x800D,
aaa10eb1
AP		 2137 .subvendor = PCI_ANY_ID,
2138 .subdevice = PCI_ANY_ID,
eb7073db 2139 .init = pci_eg20t_init,
64d91cfa 2140 .setup = pci_default_setup,
eb7073db 2141 },
d9a0fbfd
AP		 2142 /*
2143 * Cronyx Omega PCI (PLX-chip based)
2144 */
2145 {
2146 .vendor = PCI_VENDOR_ID_PLX,
2147 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2148 .subvendor = PCI_ANY_ID,
2149 .subdevice = PCI_ANY_ID,
2150 .setup = pci_omegapci_setup,
eb26dfe8 2151 },
6971c635
GA		 2152 /* WCH CH353 2S1P card (16550 clone) */
2153 {
27788c5f
AC		 2154 .vendor = PCI_VENDOR_ID_WCH,
2155 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2156 .subvendor = PCI_ANY_ID,
2157 .subdevice = PCI_ANY_ID,
2158 .setup = pci_wch_ch353_setup,
2159 },
2160 /* WCH CH353 4S card (16550 clone) */
2161 {
2162 .vendor = PCI_VENDOR_ID_WCH,
2163 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2164 .subvendor = PCI_ANY_ID,
2165 .subdevice = PCI_ANY_ID,
2166 .setup = pci_wch_ch353_setup,
2167 },
2168 /* WCH CH353 2S1PF card (16550 clone) */
2169 {
2170 .vendor = PCI_VENDOR_ID_WCH,
2171 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2172 .subvendor = PCI_ANY_ID,
2173 .subdevice = PCI_ANY_ID,
6971c635
GA		 2174 .setup = pci_wch_ch353_setup,
2175 },
8b5c913f
WY		 2176 /* WCH CH352 2S card (16550 clone) */
2177 {
2178 .vendor = PCI_VENDOR_ID_WCH,
2179 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2180 .subvendor = PCI_ANY_ID,
2181 .subdevice = PCI_ANY_ID,
2182 .setup = pci_wch_ch353_setup,
2183 },
eb26dfe8
AC		 2184 /*
2185 * ASIX devices with FIFO bug
2186 */
2187 {
2188 .vendor = PCI_VENDOR_ID_ASIX,
2189 .device = PCI_ANY_ID,
2190 .subvendor = PCI_ANY_ID,
2191 .subdevice = PCI_ANY_ID,
2192 .setup = pci_asix_setup,
2193 },
14faa8cc
MS		 2194 /*
2195 * Commtech, Inc. Fastcom adapters
2196 *
2197 */
2198 {
2199 .vendor = PCI_VENDOR_ID_COMMTECH,
2200 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2201 .subvendor = PCI_ANY_ID,
2202 .subdevice = PCI_ANY_ID,
2203 .setup = pci_fastcom335_setup,
2204 },
2205 {
2206 .vendor = PCI_VENDOR_ID_COMMTECH,
2207 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2208 .subvendor = PCI_ANY_ID,
2209 .subdevice = PCI_ANY_ID,
2210 .setup = pci_fastcom335_setup,
2211 },
2212 {
2213 .vendor = PCI_VENDOR_ID_COMMTECH,
2214 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2215 .subvendor = PCI_ANY_ID,
2216 .subdevice = PCI_ANY_ID,
2217 .setup = pci_fastcom335_setup,
2218 },
2219 {
2220 .vendor = PCI_VENDOR_ID_COMMTECH,
2221 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2222 .subvendor = PCI_ANY_ID,
2223 .subdevice = PCI_ANY_ID,
2224 .setup = pci_fastcom335_setup,
2225 },
2226 {
2227 .vendor = PCI_VENDOR_ID_COMMTECH,
2228 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2229 .subvendor = PCI_ANY_ID,
2230 .subdevice = PCI_ANY_ID,
2231 .setup = pci_xr17v35x_setup,
2232 },
2233 {
2234 .vendor = PCI_VENDOR_ID_COMMTECH,
2235 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2236 .subvendor = PCI_ANY_ID,
2237 .subdevice = PCI_ANY_ID,
2238 .setup = pci_xr17v35x_setup,
2239 },
2240 {
2241 .vendor = PCI_VENDOR_ID_COMMTECH,
2242 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2243 .subvendor = PCI_ANY_ID,
2244 .subdevice = PCI_ANY_ID,
2245 .setup = pci_xr17v35x_setup,
2246 },
ebebd49a
SH		 2247 /*
2248 * Broadcom TruManage (NetXtreme)
2249 */
2250 {
2251 .vendor = PCI_VENDOR_ID_BROADCOM,
2252 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2253 .subvendor = PCI_ANY_ID,
2254 .subdevice = PCI_ANY_ID,
2255 .setup = pci_brcm_trumanage_setup,
2256 },
2257
1da177e4
LT		 2258 /*
2259 * Default "match everything" terminator entry
2260 */
2261 {
2262 .vendor = PCI_ANY_ID,
2263 .device = PCI_ANY_ID,
2264 .subvendor = PCI_ANY_ID,
2265 .subdevice = PCI_ANY_ID,
2266 .setup = pci_default_setup,
2267 }
2268};
2269
2270static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2271{
2272 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2273}
2274
2275static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2276{
2277 struct pci_serial_quirk *quirk;
2278
2279 for (quirk = pci_serial_quirks; ; quirk++)
2280 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2281 quirk_id_matches(quirk->device, dev->device) &&
2282 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2283 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
5756ee99 2284 break;
1da177e4
LT		 2285 return quirk;
2286}
2287
dd68e88c 2288static inline int get_pci_irq(struct pci_dev *dev,
975a1a7d 2289 const struct pciserial_board *board)
1da177e4
LT		 2290{
2291 if (board->flags & FL_NOIRQ)
2292 return 0;
2293 else
2294 return dev->irq;
2295}
2296
2297/*
2298 * This is the configuration table for all of the PCI serial boards
2299 * which we support. It is directly indexed by the pci_board_num_t enum
2300 * value, which is encoded in the pci_device_id PCI probe table's
2301 * driver_data member.
2302 *
2303 * The makeup of these names are:
26e92861 2304 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 2305 *
26e92861
GH		 2306 * bn = PCI BAR number
2307 * bt = Index using PCI BARs
2308 * n = number of serial ports
2309 * baud = baud rate
2310 * offsetinhex = offset for each sequential port (in hex)
1da177e4 2311 *
26e92861 2312 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 2313 *
1da177e4
LT		 2314 * Please note: in theory if n = 1, _bt infix should make no difference.
2315 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2316 */
2317enum pci_board_num_t {
2318 pbn_default = 0,
2319
2320 pbn_b0_1_115200,
2321 pbn_b0_2_115200,
2322 pbn_b0_4_115200,
2323 pbn_b0_5_115200,
bf0df636 2324 pbn_b0_8_115200,
1da177e4
LT		 2325
2326 pbn_b0_1_921600,
2327 pbn_b0_2_921600,
2328 pbn_b0_4_921600,
2329
db1de159
DR		 2330 pbn_b0_2_1130000,
2331
fbc0dc0d
AP		 2332 pbn_b0_4_1152000,
2333
14faa8cc
MS		 2334 pbn_b0_2_1152000_200,
2335 pbn_b0_4_1152000_200,
2336 pbn_b0_8_1152000_200,
2337
26e92861
GH		 2338 pbn_b0_2_1843200,
2339 pbn_b0_4_1843200,
2340
2341 pbn_b0_2_1843200_200,
2342 pbn_b0_4_1843200_200,
2343 pbn_b0_8_1843200_200,
2344
7106b4e3
LH		 2345 pbn_b0_1_4000000,
2346
1da177e4
LT		 2347 pbn_b0_bt_1_115200,
2348 pbn_b0_bt_2_115200,
ac6ec5b1 2349 pbn_b0_bt_4_115200,
1da177e4
LT		 2350 pbn_b0_bt_8_115200,
2351
2352 pbn_b0_bt_1_460800,
2353 pbn_b0_bt_2_460800,
2354 pbn_b0_bt_4_460800,
2355
2356 pbn_b0_bt_1_921600,
2357 pbn_b0_bt_2_921600,
2358 pbn_b0_bt_4_921600,
2359 pbn_b0_bt_8_921600,
2360
2361 pbn_b1_1_115200,
2362 pbn_b1_2_115200,
2363 pbn_b1_4_115200,
2364 pbn_b1_8_115200,
04bf7e74 2365 pbn_b1_16_115200,
1da177e4
LT		 2366
2367 pbn_b1_1_921600,
2368 pbn_b1_2_921600,
2369 pbn_b1_4_921600,
2370 pbn_b1_8_921600,
2371
26e92861
GH		 2372 pbn_b1_2_1250000,
2373
84f8c6fc 2374 pbn_b1_bt_1_115200,
04bf7e74
WP		 2375 pbn_b1_bt_2_115200,
2376 pbn_b1_bt_4_115200,
2377
1da177e4
LT		 2378 pbn_b1_bt_2_921600,
2379
2380 pbn_b1_1_1382400,
2381 pbn_b1_2_1382400,
2382 pbn_b1_4_1382400,
2383 pbn_b1_8_1382400,
2384
2385 pbn_b2_1_115200,
737c1756 2386 pbn_b2_2_115200,
a9cccd34 2387 pbn_b2_4_115200,
1da177e4
LT		 2388 pbn_b2_8_115200,
2389
2390 pbn_b2_1_460800,
2391 pbn_b2_4_460800,
2392 pbn_b2_8_460800,
2393 pbn_b2_16_460800,
2394
2395 pbn_b2_1_921600,
2396 pbn_b2_4_921600,
2397 pbn_b2_8_921600,
2398
e847003f
LB		 2399 pbn_b2_8_1152000,
2400
1da177e4
LT		 2401 pbn_b2_bt_1_115200,
2402 pbn_b2_bt_2_115200,
2403 pbn_b2_bt_4_115200,
2404
2405 pbn_b2_bt_2_921600,
2406 pbn_b2_bt_4_921600,
2407
d9004eb4 2408 pbn_b3_2_115200,
1da177e4
LT		 2409 pbn_b3_4_115200,
2410 pbn_b3_8_115200,
2411
66169ad1
YY		 2412 pbn_b4_bt_2_921600,
2413 pbn_b4_bt_4_921600,
2414 pbn_b4_bt_8_921600,
2415
1da177e4
LT		 2416 /*
2417 * Board-specific versions.
2418 */
2419 pbn_panacom,
2420 pbn_panacom2,
2421 pbn_panacom4,
2422 pbn_plx_romulus,
2423 pbn_oxsemi,
7106b4e3
LH		 2424 pbn_oxsemi_1_4000000,
2425 pbn_oxsemi_2_4000000,
2426 pbn_oxsemi_4_4000000,
2427 pbn_oxsemi_8_4000000,
1da177e4
LT		 2428 pbn_intel_i960,
2429 pbn_sgi_ioc3,
1da177e4
LT		 2430 pbn_computone_4,
2431 pbn_computone_6,
2432 pbn_computone_8,
2433 pbn_sbsxrsio,
2434 pbn_exar_XR17C152,
2435 pbn_exar_XR17C154,
2436 pbn_exar_XR17C158,
dc96efb7
MS		 2437 pbn_exar_XR17V352,
2438 pbn_exar_XR17V354,
2439 pbn_exar_XR17V358,
c68d2b15 2440 pbn_exar_ibm_saturn,
aa798505 2441 pbn_pasemi_1682M,
46a0fac9
SB		 2442 pbn_ni8430_2,
2443 pbn_ni8430_4,
2444 pbn_ni8430_8,
2445 pbn_ni8430_16,
1b62cbf2
KJ		 2446 pbn_ADDIDATA_PCIe_1_3906250,
2447 pbn_ADDIDATA_PCIe_2_3906250,
2448 pbn_ADDIDATA_PCIe_4_3906250,
2449 pbn_ADDIDATA_PCIe_8_3906250,
095e24b0 2450 pbn_ce4100_1_115200,
d9a0fbfd 2451 pbn_omegapci,
7808edcd 2452 pbn_NETMOS9900_2s_115200,
ebebd49a 2453 pbn_brcm_trumanage,
1da177e4
LT		 2454};
2455
2456/*
2457 * uart_offset - the space between channels
2458 * reg_shift - describes how the UART registers are mapped
2459 * to PCI memory by the card.
2460 * For example IER register on SBS, Inc. PMC-OctPro is located at
2461 * offset 0x10 from the UART base, while UART_IER is defined as 1
2462 * in include/linux/serial_reg.h,
2463 * see first lines of serial_in() and serial_out() in 8250.c
2464*/
2465
de88b340 2466static struct pciserial_board pci_boards[] = {
1da177e4
LT		 2467 [pbn_default] = {
2468 .flags = FL_BASE0,
2469 .num_ports = 1,
2470 .base_baud = 115200,
2471 .uart_offset = 8,
2472 },
2473 [pbn_b0_1_115200] = {
2474 .flags = FL_BASE0,
2475 .num_ports = 1,
2476 .base_baud = 115200,
2477 .uart_offset = 8,
2478 },
2479 [pbn_b0_2_115200] = {
2480 .flags = FL_BASE0,
2481 .num_ports = 2,
2482 .base_baud = 115200,
2483 .uart_offset = 8,
2484 },
2485 [pbn_b0_4_115200] = {
2486 .flags = FL_BASE0,
2487 .num_ports = 4,
2488 .base_baud = 115200,
2489 .uart_offset = 8,
2490 },
2491 [pbn_b0_5_115200] = {
2492 .flags = FL_BASE0,
2493 .num_ports = 5,
2494 .base_baud = 115200,
2495 .uart_offset = 8,
2496 },
bf0df636
AC		 2497 [pbn_b0_8_115200] = {
2498 .flags = FL_BASE0,
2499 .num_ports = 8,
2500 .base_baud = 115200,
2501 .uart_offset = 8,
2502 },
1da177e4
LT		 2503 [pbn_b0_1_921600] = {
2504 .flags = FL_BASE0,
2505 .num_ports = 1,
2506 .base_baud = 921600,
2507 .uart_offset = 8,
2508 },
2509 [pbn_b0_2_921600] = {
2510 .flags = FL_BASE0,
2511 .num_ports = 2,
2512 .base_baud = 921600,
2513 .uart_offset = 8,
2514 },
2515 [pbn_b0_4_921600] = {
2516 .flags = FL_BASE0,
2517 .num_ports = 4,
2518 .base_baud = 921600,
2519 .uart_offset = 8,
2520 },
db1de159
DR		 2521
2522 [pbn_b0_2_1130000] = {
2523 .flags = FL_BASE0,
2524 .num_ports = 2,
2525 .base_baud = 1130000,
2526 .uart_offset = 8,
2527 },
2528
fbc0dc0d
AP		 2529 [pbn_b0_4_1152000] = {
2530 .flags = FL_BASE0,
2531 .num_ports = 4,
2532 .base_baud = 1152000,
2533 .uart_offset = 8,
2534 },
1da177e4 2535
14faa8cc
MS		 2536 [pbn_b0_2_1152000_200] = {
2537 .flags = FL_BASE0,
2538 .num_ports = 2,
2539 .base_baud = 1152000,
2540 .uart_offset = 0x200,
2541 },
2542
2543 [pbn_b0_4_1152000_200] = {
2544 .flags = FL_BASE0,
2545 .num_ports = 4,
2546 .base_baud = 1152000,
2547 .uart_offset = 0x200,
2548 },
2549
2550 [pbn_b0_8_1152000_200] = {
2551 .flags = FL_BASE0,
4f7d67d0 2552 .num_ports = 8,
14faa8cc
MS		 2553 .base_baud = 1152000,
2554 .uart_offset = 0x200,
2555 },
2556
26e92861
GH		 2557 [pbn_b0_2_1843200] = {
2558 .flags = FL_BASE0,
2559 .num_ports = 2,
2560 .base_baud = 1843200,
2561 .uart_offset = 8,
2562 },
2563 [pbn_b0_4_1843200] = {
2564 .flags = FL_BASE0,
2565 .num_ports = 4,
2566 .base_baud = 1843200,
2567 .uart_offset = 8,
2568 },
2569
2570 [pbn_b0_2_1843200_200] = {
2571 .flags = FL_BASE0,
2572 .num_ports = 2,
2573 .base_baud = 1843200,
2574 .uart_offset = 0x200,
2575 },
2576 [pbn_b0_4_1843200_200] = {
2577 .flags = FL_BASE0,
2578 .num_ports = 4,
2579 .base_baud = 1843200,
2580 .uart_offset = 0x200,
2581 },
2582 [pbn_b0_8_1843200_200] = {
2583 .flags = FL_BASE0,
2584 .num_ports = 8,
2585 .base_baud = 1843200,
2586 .uart_offset = 0x200,
2587 },
7106b4e3
LH		 2588 [pbn_b0_1_4000000] = {
2589 .flags = FL_BASE0,
2590 .num_ports = 1,
2591 .base_baud = 4000000,
2592 .uart_offset = 8,
2593 },
26e92861 2594
1da177e4
LT		 2595 [pbn_b0_bt_1_115200] = {
2596 .flags = FL_BASE0|FL_BASE_BARS,
2597 .num_ports = 1,
2598 .base_baud = 115200,
2599 .uart_offset = 8,
2600 },
2601 [pbn_b0_bt_2_115200] = {
2602 .flags = FL_BASE0|FL_BASE_BARS,
2603 .num_ports = 2,
2604 .base_baud = 115200,
2605 .uart_offset = 8,
2606 },
ac6ec5b1
IS		 2607 [pbn_b0_bt_4_115200] = {
2608 .flags = FL_BASE0|FL_BASE_BARS,
2609 .num_ports = 4,
2610 .base_baud = 115200,
2611 .uart_offset = 8,
2612 },
1da177e4
LT		 2613 [pbn_b0_bt_8_115200] = {
2614 .flags = FL_BASE0|FL_BASE_BARS,
2615 .num_ports = 8,
2616 .base_baud = 115200,
2617 .uart_offset = 8,
2618 },
2619
2620 [pbn_b0_bt_1_460800] = {
2621 .flags = FL_BASE0|FL_BASE_BARS,
2622 .num_ports = 1,
2623 .base_baud = 460800,
2624 .uart_offset = 8,
2625 },
2626 [pbn_b0_bt_2_460800] = {
2627 .flags = FL_BASE0|FL_BASE_BARS,
2628 .num_ports = 2,
2629 .base_baud = 460800,
2630 .uart_offset = 8,
2631 },
2632 [pbn_b0_bt_4_460800] = {
2633 .flags = FL_BASE0|FL_BASE_BARS,
2634 .num_ports = 4,
2635 .base_baud = 460800,
2636 .uart_offset = 8,
2637 },
2638
2639 [pbn_b0_bt_1_921600] = {
2640 .flags = FL_BASE0|FL_BASE_BARS,
2641 .num_ports = 1,
2642 .base_baud = 921600,
2643 .uart_offset = 8,
2644 },
2645 [pbn_b0_bt_2_921600] = {
2646 .flags = FL_BASE0|FL_BASE_BARS,
2647 .num_ports = 2,
2648 .base_baud = 921600,
2649 .uart_offset = 8,
2650 },
2651 [pbn_b0_bt_4_921600] = {
2652 .flags = FL_BASE0|FL_BASE_BARS,
2653 .num_ports = 4,
2654 .base_baud = 921600,
2655 .uart_offset = 8,
2656 },
2657 [pbn_b0_bt_8_921600] = {
2658 .flags = FL_BASE0|FL_BASE_BARS,
2659 .num_ports = 8,
2660 .base_baud = 921600,
2661 .uart_offset = 8,
2662 },
2663
2664 [pbn_b1_1_115200] = {
2665 .flags = FL_BASE1,
2666 .num_ports = 1,
2667 .base_baud = 115200,
2668 .uart_offset = 8,
2669 },
2670 [pbn_b1_2_115200] = {
2671 .flags = FL_BASE1,
2672 .num_ports = 2,
2673 .base_baud = 115200,
2674 .uart_offset = 8,
2675 },
2676 [pbn_b1_4_115200] = {
2677 .flags = FL_BASE1,
2678 .num_ports = 4,
2679 .base_baud = 115200,
2680 .uart_offset = 8,
2681 },
2682 [pbn_b1_8_115200] = {
2683 .flags = FL_BASE1,
2684 .num_ports = 8,
2685 .base_baud = 115200,
2686 .uart_offset = 8,
2687 },
04bf7e74
WP		 2688 [pbn_b1_16_115200] = {
2689 .flags = FL_BASE1,
2690 .num_ports = 16,
2691 .base_baud = 115200,
2692 .uart_offset = 8,
2693 },
1da177e4
LT		 2694
2695 [pbn_b1_1_921600] = {
2696 .flags = FL_BASE1,
2697 .num_ports = 1,
2698 .base_baud = 921600,
2699 .uart_offset = 8,
2700 },
2701 [pbn_b1_2_921600] = {
2702 .flags = FL_BASE1,
2703 .num_ports = 2,
2704 .base_baud = 921600,
2705 .uart_offset = 8,
2706 },
2707 [pbn_b1_4_921600] = {
2708 .flags = FL_BASE1,
2709 .num_ports = 4,
2710 .base_baud = 921600,
2711 .uart_offset = 8,
2712 },
2713 [pbn_b1_8_921600] = {
2714 .flags = FL_BASE1,
2715 .num_ports = 8,
2716 .base_baud = 921600,
2717 .uart_offset = 8,
2718 },
26e92861
GH		 2719 [pbn_b1_2_1250000] = {
2720 .flags = FL_BASE1,
2721 .num_ports = 2,
2722 .base_baud = 1250000,
2723 .uart_offset = 8,
2724 },
1da177e4 2725
84f8c6fc
NV		 2726 [pbn_b1_bt_1_115200] = {
2727 .flags = FL_BASE1|FL_BASE_BARS,
2728 .num_ports = 1,
2729 .base_baud = 115200,
2730 .uart_offset = 8,
2731 },
04bf7e74
WP		 2732 [pbn_b1_bt_2_115200] = {
2733 .flags = FL_BASE1|FL_BASE_BARS,
2734 .num_ports = 2,
2735 .base_baud = 115200,
2736 .uart_offset = 8,
2737 },
2738 [pbn_b1_bt_4_115200] = {
2739 .flags = FL_BASE1|FL_BASE_BARS,
2740 .num_ports = 4,
2741 .base_baud = 115200,
2742 .uart_offset = 8,
2743 },
84f8c6fc 2744
1da177e4
LT		 2745 [pbn_b1_bt_2_921600] = {
2746 .flags = FL_BASE1|FL_BASE_BARS,
2747 .num_ports = 2,
2748 .base_baud = 921600,
2749 .uart_offset = 8,
2750 },
2751
2752 [pbn_b1_1_1382400] = {
2753 .flags = FL_BASE1,
2754 .num_ports = 1,
2755 .base_baud = 1382400,
2756 .uart_offset = 8,
2757 },
2758 [pbn_b1_2_1382400] = {
2759 .flags = FL_BASE1,
2760 .num_ports = 2,
2761 .base_baud = 1382400,
2762 .uart_offset = 8,
2763 },
2764 [pbn_b1_4_1382400] = {
2765 .flags = FL_BASE1,
2766 .num_ports = 4,
2767 .base_baud = 1382400,
2768 .uart_offset = 8,
2769 },
2770 [pbn_b1_8_1382400] = {
2771 .flags = FL_BASE1,
2772 .num_ports = 8,
2773 .base_baud = 1382400,
2774 .uart_offset = 8,
2775 },
2776
2777 [pbn_b2_1_115200] = {
2778 .flags = FL_BASE2,
2779 .num_ports = 1,
2780 .base_baud = 115200,
2781 .uart_offset = 8,
2782 },
737c1756
PH		 2783 [pbn_b2_2_115200] = {
2784 .flags = FL_BASE2,
2785 .num_ports = 2,
2786 .base_baud = 115200,
2787 .uart_offset = 8,
2788 },
a9cccd34
MF		 2789 [pbn_b2_4_115200] = {
2790 .flags = FL_BASE2,
2791 .num_ports = 4,
2792 .base_baud = 115200,
2793 .uart_offset = 8,
2794 },
1da177e4
LT		 2795 [pbn_b2_8_115200] = {
2796 .flags = FL_BASE2,
2797 .num_ports = 8,
2798 .base_baud = 115200,
2799 .uart_offset = 8,
2800 },
2801
2802 [pbn_b2_1_460800] = {
2803 .flags = FL_BASE2,
2804 .num_ports = 1,
2805 .base_baud = 460800,
2806 .uart_offset = 8,
2807 },
2808 [pbn_b2_4_460800] = {
2809 .flags = FL_BASE2,
2810 .num_ports = 4,
2811 .base_baud = 460800,
2812 .uart_offset = 8,
2813 },
2814 [pbn_b2_8_460800] = {
2815 .flags = FL_BASE2,
2816 .num_ports = 8,
2817 .base_baud = 460800,
2818 .uart_offset = 8,
2819 },
2820 [pbn_b2_16_460800] = {
2821 .flags = FL_BASE2,
2822 .num_ports = 16,
2823 .base_baud = 460800,
2824 .uart_offset = 8,
2825 },
2826
2827 [pbn_b2_1_921600] = {
2828 .flags = FL_BASE2,
2829 .num_ports = 1,
2830 .base_baud = 921600,
2831 .uart_offset = 8,
2832 },
2833 [pbn_b2_4_921600] = {
2834 .flags = FL_BASE2,
2835 .num_ports = 4,
2836 .base_baud = 921600,
2837 .uart_offset = 8,
2838 },
2839 [pbn_b2_8_921600] = {
2840 .flags = FL_BASE2,
2841 .num_ports = 8,
2842 .base_baud = 921600,
2843 .uart_offset = 8,
2844 },
2845
e847003f
LB		 2846 [pbn_b2_8_1152000] = {
2847 .flags = FL_BASE2,
2848 .num_ports = 8,
2849 .base_baud = 1152000,
2850 .uart_offset = 8,
2851 },
2852
1da177e4
LT		 2853 [pbn_b2_bt_1_115200] = {
2854 .flags = FL_BASE2|FL_BASE_BARS,
2855 .num_ports = 1,
2856 .base_baud = 115200,
2857 .uart_offset = 8,
2858 },
2859 [pbn_b2_bt_2_115200] = {
2860 .flags = FL_BASE2|FL_BASE_BARS,
2861 .num_ports = 2,
2862 .base_baud = 115200,
2863 .uart_offset = 8,
2864 },
2865 [pbn_b2_bt_4_115200] = {
2866 .flags = FL_BASE2|FL_BASE_BARS,
2867 .num_ports = 4,
2868 .base_baud = 115200,
2869 .uart_offset = 8,
2870 },
2871
2872 [pbn_b2_bt_2_921600] = {
2873 .flags = FL_BASE2|FL_BASE_BARS,
2874 .num_ports = 2,
2875 .base_baud = 921600,
2876 .uart_offset = 8,
2877 },
2878 [pbn_b2_bt_4_921600] = {
2879 .flags = FL_BASE2|FL_BASE_BARS,
2880 .num_ports = 4,
2881 .base_baud = 921600,
2882 .uart_offset = 8,
2883 },
2884
d9004eb4
ABL		 2885 [pbn_b3_2_115200] = {
2886 .flags = FL_BASE3,
2887 .num_ports = 2,
2888 .base_baud = 115200,
2889 .uart_offset = 8,
2890 },
1da177e4
LT		 2891 [pbn_b3_4_115200] = {
2892 .flags = FL_BASE3,
2893 .num_ports = 4,
2894 .base_baud = 115200,
2895 .uart_offset = 8,
2896 },
2897 [pbn_b3_8_115200] = {
2898 .flags = FL_BASE3,
2899 .num_ports = 8,
2900 .base_baud = 115200,
2901 .uart_offset = 8,
2902 },
2903
66169ad1
YY		 2904 [pbn_b4_bt_2_921600] = {
2905 .flags = FL_BASE4,
2906 .num_ports = 2,
2907 .base_baud = 921600,
2908 .uart_offset = 8,
2909 },
2910 [pbn_b4_bt_4_921600] = {
2911 .flags = FL_BASE4,
2912 .num_ports = 4,
2913 .base_baud = 921600,
2914 .uart_offset = 8,
2915 },
2916 [pbn_b4_bt_8_921600] = {
2917 .flags = FL_BASE4,
2918 .num_ports = 8,
2919 .base_baud = 921600,
2920 .uart_offset = 8,
2921 },
2922
1da177e4
LT		 2923 /*
2924 * Entries following this are board-specific.
2925 */
2926
2927 /*
2928 * Panacom - IOMEM
2929 */
2930 [pbn_panacom] = {
2931 .flags = FL_BASE2,
2932 .num_ports = 2,
2933 .base_baud = 921600,
2934 .uart_offset = 0x400,
2935 .reg_shift = 7,
2936 },
2937 [pbn_panacom2] = {
2938 .flags = FL_BASE2|FL_BASE_BARS,
2939 .num_ports = 2,
2940 .base_baud = 921600,
2941 .uart_offset = 0x400,
2942 .reg_shift = 7,
2943 },
2944 [pbn_panacom4] = {
2945 .flags = FL_BASE2|FL_BASE_BARS,
2946 .num_ports = 4,
2947 .base_baud = 921600,
2948 .uart_offset = 0x400,
2949 .reg_shift = 7,
2950 },
2951
2952 /* I think this entry is broken - the first_offset looks wrong --rmk */
2953 [pbn_plx_romulus] = {
2954 .flags = FL_BASE2,
2955 .num_ports = 4,
2956 .base_baud = 921600,
2957 .uart_offset = 8 << 2,
2958 .reg_shift = 2,
2959 .first_offset = 0x03,
2960 },
2961
2962 /*
2963 * This board uses the size of PCI Base region 0 to
2964 * signal now many ports are available
2965 */
2966 [pbn_oxsemi] = {
2967 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2968 .num_ports = 32,
2969 .base_baud = 115200,
2970 .uart_offset = 8,
2971 },
7106b4e3
LH		 2972 [pbn_oxsemi_1_4000000] = {
2973 .flags = FL_BASE0,
2974 .num_ports = 1,
2975 .base_baud = 4000000,
2976 .uart_offset = 0x200,
2977 .first_offset = 0x1000,
2978 },
2979 [pbn_oxsemi_2_4000000] = {
2980 .flags = FL_BASE0,
2981 .num_ports = 2,
2982 .base_baud = 4000000,
2983 .uart_offset = 0x200,
2984 .first_offset = 0x1000,
2985 },
2986 [pbn_oxsemi_4_4000000] = {
2987 .flags = FL_BASE0,
2988 .num_ports = 4,
2989 .base_baud = 4000000,
2990 .uart_offset = 0x200,
2991 .first_offset = 0x1000,
2992 },
2993 [pbn_oxsemi_8_4000000] = {
2994 .flags = FL_BASE0,
2995 .num_ports = 8,
2996 .base_baud = 4000000,
2997 .uart_offset = 0x200,
2998 .first_offset = 0x1000,
2999 },
3000
1da177e4
LT		 3001
3002 /*
3003 * EKF addition for i960 Boards form EKF with serial port.
3004 * Max 256 ports.
3005 */
3006 [pbn_intel_i960] = {
3007 .flags = FL_BASE0,
3008 .num_ports = 32,
3009 .base_baud = 921600,
3010 .uart_offset = 8 << 2,
3011 .reg_shift = 2,
3012 .first_offset = 0x10000,
3013 },
3014 [pbn_sgi_ioc3] = {
3015 .flags = FL_BASE0|FL_NOIRQ,
3016 .num_ports = 1,
3017 .base_baud = 458333,
3018 .uart_offset = 8,
3019 .reg_shift = 0,
3020 .first_offset = 0x20178,
3021 },
3022
1da177e4
LT		 3023 /*
3024 * Computone - uses IOMEM.
3025 */
3026 [pbn_computone_4] = {
3027 .flags = FL_BASE0,
3028 .num_ports = 4,
3029 .base_baud = 921600,
3030 .uart_offset = 0x40,
3031 .reg_shift = 2,
3032 .first_offset = 0x200,
3033 },
3034 [pbn_computone_6] = {
3035 .flags = FL_BASE0,
3036 .num_ports = 6,
3037 .base_baud = 921600,
3038 .uart_offset = 0x40,
3039 .reg_shift = 2,
3040 .first_offset = 0x200,
3041 },
3042 [pbn_computone_8] = {
3043 .flags = FL_BASE0,
3044 .num_ports = 8,
3045 .base_baud = 921600,
3046 .uart_offset = 0x40,
3047 .reg_shift = 2,
3048 .first_offset = 0x200,
3049 },
3050 [pbn_sbsxrsio] = {
3051 .flags = FL_BASE0,
3052 .num_ports = 8,
3053 .base_baud = 460800,
3054 .uart_offset = 256,
3055 .reg_shift = 4,
3056 },
3057 /*
3058 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3059 * Only basic 16550A support.
3060 * XR17C15[24] are not tested, but they should work.
3061 */
3062 [pbn_exar_XR17C152] = {
3063 .flags = FL_BASE0,
3064 .num_ports = 2,
3065 .base_baud = 921600,
3066 .uart_offset = 0x200,
3067 },
3068 [pbn_exar_XR17C154] = {
3069 .flags = FL_BASE0,
3070 .num_ports = 4,
3071 .base_baud = 921600,
3072 .uart_offset = 0x200,
3073 },
3074 [pbn_exar_XR17C158] = {
3075 .flags = FL_BASE0,
3076 .num_ports = 8,
3077 .base_baud = 921600,
3078 .uart_offset = 0x200,
3079 },
dc96efb7
MS		 3080 [pbn_exar_XR17V352] = {
3081 .flags = FL_BASE0,
3082 .num_ports = 2,
3083 .base_baud = 7812500,
3084 .uart_offset = 0x400,
3085 .reg_shift = 0,
3086 .first_offset = 0,
3087 },
3088 [pbn_exar_XR17V354] = {
3089 .flags = FL_BASE0,
3090 .num_ports = 4,
3091 .base_baud = 7812500,
3092 .uart_offset = 0x400,
3093 .reg_shift = 0,
3094 .first_offset = 0,
3095 },
3096 [pbn_exar_XR17V358] = {
3097 .flags = FL_BASE0,
3098 .num_ports = 8,
3099 .base_baud = 7812500,
3100 .uart_offset = 0x400,
3101 .reg_shift = 0,
3102 .first_offset = 0,
3103 },
c68d2b15
BH		 3104 [pbn_exar_ibm_saturn] = {
3105 .flags = FL_BASE0,
3106 .num_ports = 1,
3107 .base_baud = 921600,
3108 .uart_offset = 0x200,
3109 },
3110
aa798505
OJ		 3111 /*
3112 * PA Semi PWRficient PA6T-1682M on-chip UART
3113 */
3114 [pbn_pasemi_1682M] = {
3115 .flags = FL_BASE0,
3116 .num_ports = 1,
3117 .base_baud = 8333333,
3118 },
46a0fac9
SB		 3119 /*
3120 * National Instruments 843x
3121 */
3122 [pbn_ni8430_16] = {
3123 .flags = FL_BASE0,
3124 .num_ports = 16,
3125 .base_baud = 3686400,
3126 .uart_offset = 0x10,
3127 .first_offset = 0x800,
3128 },
3129 [pbn_ni8430_8] = {
3130 .flags = FL_BASE0,
3131 .num_ports = 8,
3132 .base_baud = 3686400,
3133 .uart_offset = 0x10,
3134 .first_offset = 0x800,
3135 },
3136 [pbn_ni8430_4] = {
3137 .flags = FL_BASE0,
3138 .num_ports = 4,
3139 .base_baud = 3686400,
3140 .uart_offset = 0x10,
3141 .first_offset = 0x800,
3142 },
3143 [pbn_ni8430_2] = {
3144 .flags = FL_BASE0,
3145 .num_ports = 2,
3146 .base_baud = 3686400,
3147 .uart_offset = 0x10,
3148 .first_offset = 0x800,
3149 },
1b62cbf2
KJ		 3150 /*
3151 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3152 */
3153 [pbn_ADDIDATA_PCIe_1_3906250] = {
3154 .flags = FL_BASE0,
3155 .num_ports = 1,
3156 .base_baud = 3906250,
3157 .uart_offset = 0x200,
3158 .first_offset = 0x1000,
3159 },
3160 [pbn_ADDIDATA_PCIe_2_3906250] = {
3161 .flags = FL_BASE0,
3162 .num_ports = 2,
3163 .base_baud = 3906250,
3164 .uart_offset = 0x200,
3165 .first_offset = 0x1000,
3166 },
3167 [pbn_ADDIDATA_PCIe_4_3906250] = {
3168 .flags = FL_BASE0,
3169 .num_ports = 4,
3170 .base_baud = 3906250,
3171 .uart_offset = 0x200,
3172 .first_offset = 0x1000,
3173 },
3174 [pbn_ADDIDATA_PCIe_8_3906250] = {
3175 .flags = FL_BASE0,
3176 .num_ports = 8,
3177 .base_baud = 3906250,
3178 .uart_offset = 0x200,
3179 .first_offset = 0x1000,
3180 },
095e24b0 3181 [pbn_ce4100_1_115200] = {
08ec212c
MB		 3182 .flags = FL_BASE_BARS,
3183 .num_ports = 2,
095e24b0
DB		 3184 .base_baud = 921600,
3185 .reg_shift = 2,
3186 },
d9a0fbfd
AP		 3187 [pbn_omegapci] = {
3188 .flags = FL_BASE0,
3189 .num_ports = 8,
3190 .base_baud = 115200,
3191 .uart_offset = 0x200,
3192 },
7808edcd
NG		 3193 [pbn_NETMOS9900_2s_115200] = {
3194 .flags = FL_BASE0,
3195 .num_ports = 2,
3196 .base_baud = 115200,
3197 },
ebebd49a
SH		 3198 [pbn_brcm_trumanage] = {
3199 .flags = FL_BASE0,
3200 .num_ports = 1,
3201 .reg_shift = 2,
3202 .base_baud = 115200,
3203 },
1da177e4
LT		 3204};
3205
6971c635
GA		 3206static const struct pci_device_id blacklist[] = {
3207 /* softmodems */
5756ee99 3208 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
ebf7c066
MS		 3209 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3210 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
6971c635
GA		 3211
3212 /* multi-io cards handled by parport_serial */
3213 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
436bbd43
CS		 3214};
3215
1da177e4
LT		 3216/*
3217 * Given a complete unknown PCI device, try to use some heuristics to
3218 * guess what the configuration might be, based on the pitiful PCI
3219 * serial specs. Returns 0 on success, 1 on failure.
3220 */
9671f099 3221static int
1c7c1fe5 3222serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 3223{
6971c635 3224 const struct pci_device_id *bldev;
1da177e4 3225 int num_iomem, num_port, first_port = -1, i;
5756ee99 3226
1da177e4
LT		 3227 /*
3228 * If it is not a communications device or the programming
3229 * interface is greater than 6, give up.
3230 *
3231 * (Should we try to make guesses for multiport serial devices
5756ee99 3232 * later?)
1da177e4
LT		 3233 */
3234 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3235 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3236 (dev->class & 0xff) > 6)
3237 return -ENODEV;
3238
436bbd43
CS		 3239 /*
3240 * Do not access blacklisted devices that are known not to
6971c635 3241 * feature serial ports or are handled by other modules.
436bbd43 3242 */
6971c635
GA		 3243 for (bldev = blacklist;
3244 bldev < blacklist + ARRAY_SIZE(blacklist);
3245 bldev++) {
3246 if (dev->vendor == bldev->vendor &&
3247 dev->device == bldev->device)
436bbd43
CS		 3248 return -ENODEV;
3249 }
3250
1da177e4
LT		 3251 num_iomem = num_port = 0;
3252 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3253 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3254 num_port++;
3255 if (first_port == -1)
3256 first_port = i;
3257 }
3258 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3259 num_iomem++;
3260 }
3261
3262 /*
3263 * If there is 1 or 0 iomem regions, and exactly one port,
3264 * use it. We guess the number of ports based on the IO
3265 * region size.
3266 */
3267 if (num_iomem <= 1 && num_port == 1) {
3268 board->flags = first_port;
3269 board->num_ports = pci_resource_len(dev, first_port) / 8;
3270 return 0;
3271 }
3272
3273 /*
3274 * Now guess if we've got a board which indexes by BARs.
3275 * Each IO BAR should be 8 bytes, and they should follow
3276 * consecutively.
3277 */
3278 first_port = -1;
3279 num_port = 0;
3280 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3281 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3282 pci_resource_len(dev, i) == 8 &&
3283 (first_port == -1 || (first_port + num_port) == i)) {
3284 num_port++;
3285 if (first_port == -1)
3286 first_port = i;
3287 }
3288 }
3289
3290 if (num_port > 1) {
3291 board->flags = first_port | FL_BASE_BARS;
3292 board->num_ports = num_port;
3293 return 0;
3294 }
3295
3296 return -ENODEV;
3297}
3298
3299static inline int
975a1a7d
RK		 3300serial_pci_matches(const struct pciserial_board *board,
3301 const struct pciserial_board *guessed)
1da177e4
LT		 3302{
3303 return
3304 board->num_ports == guessed->num_ports &&
3305 board->base_baud == guessed->base_baud &&
3306 board->uart_offset == guessed->uart_offset &&
3307 board->reg_shift == guessed->reg_shift &&
3308 board->first_offset == guessed->first_offset;
3309}
3310
241fc436 3311struct serial_private *
975a1a7d 3312pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
1da177e4 3313{
2655a2c7 3314 struct uart_8250_port uart;
1da177e4 3315 struct serial_private *priv;
1da177e4
LT		 3316 struct pci_serial_quirk *quirk;
3317 int rc, nr_ports, i;
3318
1da177e4
LT		 3319 nr_ports = board->num_ports;
3320
3321 /*
3322 * Find an init and setup quirks.
3323 */
3324 quirk = find_quirk(dev);
3325
3326 /*
3327 * Run the new-style initialization function.
3328 * The initialization function returns:
3329 * <0 - error
3330 * 0 - use board->num_ports
3331 * >0 - number of ports
3332 */
3333 if (quirk->init) {
3334 rc = quirk->init(dev);
241fc436
RK		 3335 if (rc < 0) {
3336 priv = ERR_PTR(rc);
3337 goto err_out;
3338 }
1da177e4
LT		 3339 if (rc)
3340 nr_ports = rc;
3341 }
3342
8f31bb39 3343 priv = kzalloc(sizeof(struct serial_private) +
1da177e4
LT		 3344 sizeof(unsigned int) * nr_ports,
3345 GFP_KERNEL);
3346 if (!priv) {
241fc436
RK		 3347 priv = ERR_PTR(-ENOMEM);
3348 goto err_deinit;
1da177e4
LT		 3349 }
3350
70db3d91 3351 priv->dev = dev;
1da177e4 3352 priv->quirk = quirk;
1da177e4 3353
2655a2c7
AC		 3354 memset(&uart, 0, sizeof(uart));
3355 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3356 uart.port.uartclk = board->base_baud * 16;
3357 uart.port.irq = get_pci_irq(dev, board);
3358 uart.port.dev = &dev->dev;
72ce9a83 3359
1da177e4 3360 for (i = 0; i < nr_ports; i++) {
2655a2c7 3361 if (quirk->setup(priv, board, &uart, i))
1da177e4 3362 break;
72ce9a83 3363
1da177e4 3364#ifdef SERIAL_DEBUG_PCI
80647b95 3365 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2655a2c7 3366 uart.port.iobase, uart.port.irq, uart.port.iotype);
1da177e4 3367#endif
5756ee99 3368
2655a2c7 3369 priv->line[i] = serial8250_register_8250_port(&uart);
1da177e4
LT		 3370 if (priv->line[i] < 0) {
3371 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
3372 break;
3373 }
3374 }
1da177e4 3375 priv->nr = i;
241fc436 3376 return priv;
1da177e4 3377
5756ee99 3378err_deinit:
1da177e4
LT		 3379 if (quirk->exit)
3380 quirk->exit(dev);
5756ee99 3381err_out:
241fc436 3382 return priv;
1da177e4 3383}
241fc436 3384EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 3385
241fc436 3386void pciserial_remove_ports(struct serial_private *priv)
1da177e4 3387{
056a8763
RK		 3388 struct pci_serial_quirk *quirk;
3389 int i;
1da177e4 3390
056a8763
RK		 3391 for (i = 0; i < priv->nr; i++)
3392 serial8250_unregister_port(priv->line[i]);
1da177e4 3393
056a8763
RK		 3394 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3395 if (priv->remapped_bar[i])
3396 iounmap(priv->remapped_bar[i]);
3397 priv->remapped_bar[i] = NULL;
3398 }
1da177e4 3399
056a8763
RK		 3400 /*
3401 * Find the exit quirks.
3402 */
241fc436 3403 quirk = find_quirk(priv->dev);
056a8763 3404 if (quirk->exit)
241fc436
RK		 3405 quirk->exit(priv->dev);
3406
3407 kfree(priv);
3408}
3409EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3410
3411void pciserial_suspend_ports(struct serial_private *priv)
3412{
3413 int i;
3414
3415 for (i = 0; i < priv->nr; i++)
3416 if (priv->line[i] >= 0)
3417 serial8250_suspend_port(priv->line[i]);
5f1a3895
DW		 3418
3419 /*
3420 * Ensure that every init quirk is properly torn down
3421 */
3422 if (priv->quirk->exit)
3423 priv->quirk->exit(priv->dev);
241fc436
RK		 3424}
3425EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3426
3427void pciserial_resume_ports(struct serial_private *priv)
3428{
3429 int i;
3430
3431 /*
3432 * Ensure that the board is correctly configured.
3433 */
3434 if (priv->quirk->init)
3435 priv->quirk->init(priv->dev);
3436
3437 for (i = 0; i < priv->nr; i++)
3438 if (priv->line[i] >= 0)
3439 serial8250_resume_port(priv->line[i]);
3440}
3441EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3442
3443/*
3444 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3445 * to the arrangement of serial ports on a PCI card.
3446 */
9671f099 3447static int
241fc436
RK		 3448pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3449{
5bf8f501 3450 struct pci_serial_quirk *quirk;
241fc436 3451 struct serial_private *priv;
975a1a7d
RK		 3452 const struct pciserial_board *board;
3453 struct pciserial_board tmp;
241fc436
RK		 3454 int rc;
3455
5bf8f501
FB		 3456 quirk = find_quirk(dev);
3457 if (quirk->probe) {
3458 rc = quirk->probe(dev);
3459 if (rc)
3460 return rc;
3461 }
3462
241fc436
RK		 3463 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3464 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
3465 ent->driver_data);
3466 return -EINVAL;
3467 }
3468
3469 board = &pci_boards[ent->driver_data];
3470
3471 rc = pci_enable_device(dev);
2807190b 3472 pci_save_state(dev);
241fc436
RK		 3473 if (rc)
3474 return rc;
3475
3476 if (ent->driver_data == pbn_default) {
3477 /*
3478 * Use a copy of the pci_board entry for this;
3479 * avoid changing entries in the table.
3480 */
3481 memcpy(&tmp, board, sizeof(struct pciserial_board));
3482 board = &tmp;
3483
3484 /*
3485 * We matched one of our class entries. Try to
3486 * determine the parameters of this board.
3487 */
975a1a7d 3488 rc = serial_pci_guess_board(dev, &tmp);
241fc436
RK		 3489 if (rc)
3490 goto disable;
3491 } else {
3492 /*
3493 * We matched an explicit entry. If we are able to
3494 * detect this boards settings with our heuristic,
3495 * then we no longer need this entry.
3496 */
3497 memcpy(&tmp, &pci_boards[pbn_default],
3498 sizeof(struct pciserial_board));
3499 rc = serial_pci_guess_board(dev, &tmp);
3500 if (rc == 0 && serial_pci_matches(board, &tmp))
3501 moan_device("Redundant entry in serial pci_table.",
3502 dev);
3503 }
3504
3505 priv = pciserial_init_ports(dev, board);
3506 if (!IS_ERR(priv)) {
3507 pci_set_drvdata(dev, priv);
3508 return 0;
3509 }
3510
3511 rc = PTR_ERR(priv);
1da177e4 3512
241fc436 3513 disable:
056a8763 3514 pci_disable_device(dev);
241fc436
RK		 3515 return rc;
3516}
1da177e4 3517
ae8d8a14 3518static void pciserial_remove_one(struct pci_dev *dev)
241fc436
RK		 3519{
3520 struct serial_private *priv = pci_get_drvdata(dev);
3521
3522 pci_set_drvdata(dev, NULL);
3523
3524 pciserial_remove_ports(priv);
3525
3526 pci_disable_device(dev);
1da177e4
LT		 3527}
3528
1d5e7996 3529#ifdef CONFIG_PM
1da177e4
LT		 3530static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
3531{
3532 struct serial_private *priv = pci_get_drvdata(dev);
3533
241fc436
RK		 3534 if (priv)
3535 pciserial_suspend_ports(priv);
1da177e4 3536
1da177e4
LT		 3537 pci_save_state(dev);
3538 pci_set_power_state(dev, pci_choose_state(dev, state));
3539 return 0;
3540}
3541
3542static int pciserial_resume_one(struct pci_dev *dev)
3543{
ccb9d59e 3544 int err;
1da177e4
LT		 3545 struct serial_private *priv = pci_get_drvdata(dev);
3546
3547 pci_set_power_state(dev, PCI_D0);
3548 pci_restore_state(dev);
3549
3550 if (priv) {
1da177e4
LT		 3551 /*
3552 * The device may have been disabled. Re-enable it.
3553 */
ccb9d59e 3554 err = pci_enable_device(dev);
40836c48 3555 /* FIXME: We cannot simply error out here */
ccb9d59e 3556 if (err)
40836c48 3557 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
241fc436 3558 pciserial_resume_ports(priv);
1da177e4
LT		 3559 }
3560 return 0;
3561}
1d5e7996 3562#endif
1da177e4
LT		 3563
3564static struct pci_device_id serial_pci_tbl[] = {
78d70d48
MB		 3565 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3566 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3567 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3568 pbn_b2_8_921600 },
1da177e4
LT		 3569 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3570 PCI_SUBVENDOR_ID_CONNECT_TECH,
3571 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3572 pbn_b1_8_1382400 },
3573 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3574 PCI_SUBVENDOR_ID_CONNECT_TECH,
3575 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3576 pbn_b1_4_1382400 },
3577 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3578 PCI_SUBVENDOR_ID_CONNECT_TECH,
3579 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3580 pbn_b1_2_1382400 },
3581 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3582 PCI_SUBVENDOR_ID_CONNECT_TECH,
3583 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3584 pbn_b1_8_1382400 },
3585 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3586 PCI_SUBVENDOR_ID_CONNECT_TECH,
3587 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3588 pbn_b1_4_1382400 },
3589 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3590 PCI_SUBVENDOR_ID_CONNECT_TECH,
3591 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3592 pbn_b1_2_1382400 },
3593 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3594 PCI_SUBVENDOR_ID_CONNECT_TECH,
3595 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3596 pbn_b1_8_921600 },
3597 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3598 PCI_SUBVENDOR_ID_CONNECT_TECH,
3599 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3600 pbn_b1_8_921600 },
3601 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3602 PCI_SUBVENDOR_ID_CONNECT_TECH,
3603 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3604 pbn_b1_4_921600 },
3605 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3606 PCI_SUBVENDOR_ID_CONNECT_TECH,
3607 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3608 pbn_b1_4_921600 },
3609 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3610 PCI_SUBVENDOR_ID_CONNECT_TECH,
3611 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3612 pbn_b1_2_921600 },
3613 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3614 PCI_SUBVENDOR_ID_CONNECT_TECH,
3615 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3616 pbn_b1_8_921600 },
3617 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3618 PCI_SUBVENDOR_ID_CONNECT_TECH,
3619 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3620 pbn_b1_8_921600 },
3621 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3622 PCI_SUBVENDOR_ID_CONNECT_TECH,
3623 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3624 pbn_b1_4_921600 },
26e92861
GH		 3625 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3626 PCI_SUBVENDOR_ID_CONNECT_TECH,
3627 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3628 pbn_b1_2_1250000 },
3629 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3630 PCI_SUBVENDOR_ID_CONNECT_TECH,
3631 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3632 pbn_b0_2_1843200 },
3633 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3634 PCI_SUBVENDOR_ID_CONNECT_TECH,
3635 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3636 pbn_b0_4_1843200 },
85d1494e
YY		 3637 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3638 PCI_VENDOR_ID_AFAVLAB,
3639 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3640 pbn_b0_4_1152000 },
26e92861
GH		 3641 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3642 PCI_SUBVENDOR_ID_CONNECT_TECH,
3643 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3644 pbn_b0_2_1843200_200 },
3645 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3646 PCI_SUBVENDOR_ID_CONNECT_TECH,
3647 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3648 pbn_b0_4_1843200_200 },
3649 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3650 PCI_SUBVENDOR_ID_CONNECT_TECH,
3651 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3652 pbn_b0_8_1843200_200 },
3653 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3654 PCI_SUBVENDOR_ID_CONNECT_TECH,
3655 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3656 pbn_b0_2_1843200_200 },
3657 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3658 PCI_SUBVENDOR_ID_CONNECT_TECH,
3659 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3660 pbn_b0_4_1843200_200 },
3661 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3662 PCI_SUBVENDOR_ID_CONNECT_TECH,
3663 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3664 pbn_b0_8_1843200_200 },
3665 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3666 PCI_SUBVENDOR_ID_CONNECT_TECH,
3667 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3668 pbn_b0_2_1843200_200 },
3669 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3670 PCI_SUBVENDOR_ID_CONNECT_TECH,
3671 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3672 pbn_b0_4_1843200_200 },
3673 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3674 PCI_SUBVENDOR_ID_CONNECT_TECH,
3675 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3676 pbn_b0_8_1843200_200 },
3677 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3678 PCI_SUBVENDOR_ID_CONNECT_TECH,
3679 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3680 pbn_b0_2_1843200_200 },
3681 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3682 PCI_SUBVENDOR_ID_CONNECT_TECH,
3683 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3684 pbn_b0_4_1843200_200 },
3685 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3686 PCI_SUBVENDOR_ID_CONNECT_TECH,
3687 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3688 pbn_b0_8_1843200_200 },
c68d2b15
BH		 3689 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3690 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3691 0, 0, pbn_exar_ibm_saturn },
1da177e4
LT		 3692
3693 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
5756ee99 3694 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3695 pbn_b2_bt_1_115200 },
3696 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
5756ee99 3697 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3698 pbn_b2_bt_2_115200 },
3699 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
5756ee99 3700 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3701 pbn_b2_bt_4_115200 },
3702 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
5756ee99 3703 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3704 pbn_b2_bt_2_115200 },
3705 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
5756ee99 3706 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3707 pbn_b2_bt_4_115200 },
3708 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
5756ee99 3709 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 3710 pbn_b2_8_115200 },
e65f0f82
FL		 3711 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3712 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3713 pbn_b2_8_460800 },
1da177e4
LT		 3714 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3715 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3716 pbn_b2_8_115200 },
3717
3718 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3719 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3720 pbn_b2_bt_2_115200 },
3721 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3722 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3723 pbn_b2_bt_2_921600 },
3724 /*
3725 * VScom SPCOM800, from sl@s.pl
3726 */
5756ee99
AC		 3727 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3728 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3729 pbn_b2_8_921600 },
3730 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
5756ee99 3731 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 3732 pbn_b2_4_921600 },
b76c5a07
CB		 3733 /* Unknown card - subdevice 0x1584 */
3734 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3735 PCI_VENDOR_ID_PLX,
3736 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
d13402a4
SA		 3737 pbn_b2_4_115200 },
3738 /* Unknown card - subdevice 0x1588 */
3739 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3740 PCI_VENDOR_ID_PLX,
3741 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
3742 pbn_b2_8_115200 },
1da177e4
LT		 3743 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3744 PCI_SUBVENDOR_ID_KEYSPAN,
3745 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3746 pbn_panacom },
3747 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3748 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3749 pbn_panacom4 },
3750 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3751 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3752 pbn_panacom2 },
a9cccd34
MF		 3753 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3754 PCI_VENDOR_ID_ESDGMBH,
3755 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3756 pbn_b2_4_115200 },
1da177e4
LT		 3757 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3758 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3759 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1da177e4
LT		 3760 pbn_b2_4_460800 },
3761 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3762 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3763 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1da177e4
LT		 3764 pbn_b2_8_460800 },
3765 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3766 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3767 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1da177e4
LT		 3768 pbn_b2_16_460800 },
3769 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3770 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3771 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1da177e4
LT		 3772 pbn_b2_16_460800 },
3773 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3774 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 3775 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1da177e4
LT		 3776 pbn_b2_4_460800 },
3777 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3778 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 3779 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1da177e4 3780 pbn_b2_8_460800 },
add7b58e
BH		 3781 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3782 PCI_SUBVENDOR_ID_EXSYS,
3783 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
ee4cd1b2 3784 pbn_b2_4_115200 },
1da177e4
LT		 3785 /*
3786 * Megawolf Romulus PCI Serial Card, from Mike Hudson
3787 * (Exoray@isys.ca)
3788 */
3789 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3790 0x10b5, 0x106a, 0, 0,
3791 pbn_plx_romulus },
55c7c0fd
AC		 3792 /*
3793 * Quatech cards. These actually have configurable clocks but for
3794 * now we just use the default.
3795 *
3796 * 100 series are RS232, 200 series RS422,
3797 */
1da177e4
LT		 3798 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3799 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3800 pbn_b1_4_115200 },
3801 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3802 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3803 pbn_b1_2_115200 },
55c7c0fd
AC		 3804 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
3805 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3806 pbn_b2_2_115200 },
3807 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
3808 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3809 pbn_b1_2_115200 },
3810 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
3811 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3812 pbn_b2_2_115200 },
3813 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
3814 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3815 pbn_b1_4_115200 },
1da177e4
LT		 3816 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3817 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3818 pbn_b1_8_115200 },
3819 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3820 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3821 pbn_b1_8_115200 },
55c7c0fd
AC		 3822 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
3823 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3824 pbn_b1_4_115200 },
3825 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
3826 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3827 pbn_b1_2_115200 },
3828 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
3829 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3830 pbn_b1_4_115200 },
3831 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
3832 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3833 pbn_b1_2_115200 },
3834 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
3835 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3836 pbn_b2_4_115200 },
3837 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
3838 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3839 pbn_b2_2_115200 },
3840 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
3841 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3842 pbn_b2_1_115200 },
3843 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
3844 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3845 pbn_b2_4_115200 },
3846 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
3847 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3848 pbn_b2_2_115200 },
3849 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
3850 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3851 pbn_b2_1_115200 },
3852 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
3853 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3854 pbn_b0_8_115200 },
3855
1da177e4 3856 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 3857 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3858 0, 0,
1da177e4 3859 pbn_b0_4_921600 },
fbc0dc0d 3860 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 3861 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3862 0, 0,
fbc0dc0d 3863 pbn_b0_4_1152000 },
c9bd9d01
MP		 3864 { PCI_VENDOR_ID_OXSEMI, 0x9505,
3865 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3866 pbn_b0_bt_2_921600 },
db1de159
DR		 3867
3868 /*
3869 * The below card is a little controversial since it is the
3870 * subject of a PCI vendor/device ID clash. (See
3871 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3872 * For now just used the hex ID 0x950a.
3873 */
39aced68 3874 { PCI_VENDOR_ID_OXSEMI, 0x950a,
26e8220a
FL		 3875 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
3876 0, 0, pbn_b0_2_115200 },
3877 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3878 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
3879 0, 0, pbn_b0_2_115200 },
db1de159
DR		 3880 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3881 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3882 pbn_b0_2_1130000 },
70fd8fde
AP		 3883 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3884 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3885 pbn_b0_1_921600 },
1da177e4
LT		 3886 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3887 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3888 pbn_b0_4_115200 },
3889 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3890 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3891 pbn_b0_bt_2_921600 },
e847003f
LB		 3892 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3893 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3894 pbn_b2_8_1152000 },
1da177e4 3895
7106b4e3
LH		 3896 /*
3897 * Oxford Semiconductor Inc. Tornado PCI express device range.
3898 */
3899 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
3900 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3901 pbn_b0_1_4000000 },
3902 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
3903 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3904 pbn_b0_1_4000000 },
3905 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
3906 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3907 pbn_oxsemi_1_4000000 },
3908 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
3909 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3910 pbn_oxsemi_1_4000000 },
3911 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
3912 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3913 pbn_b0_1_4000000 },
3914 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
3915 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3916 pbn_b0_1_4000000 },
3917 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
3918 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3919 pbn_oxsemi_1_4000000 },
3920 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
3921 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3922 pbn_oxsemi_1_4000000 },
3923 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
3924 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3925 pbn_b0_1_4000000 },
3926 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
3927 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3928 pbn_b0_1_4000000 },
3929 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
3930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3931 pbn_b0_1_4000000 },
3932 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
3933 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3934 pbn_b0_1_4000000 },
3935 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
3936 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3937 pbn_oxsemi_2_4000000 },
3938 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
3939 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3940 pbn_oxsemi_2_4000000 },
3941 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
3942 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3943 pbn_oxsemi_4_4000000 },
3944 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
3945 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3946 pbn_oxsemi_4_4000000 },
3947 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
3948 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3949 pbn_oxsemi_8_4000000 },
3950 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
3951 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3952 pbn_oxsemi_8_4000000 },
3953 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
3954 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3955 pbn_oxsemi_1_4000000 },
3956 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
3957 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3958 pbn_oxsemi_1_4000000 },
3959 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
3960 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3961 pbn_oxsemi_1_4000000 },
3962 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
3963 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3964 pbn_oxsemi_1_4000000 },
3965 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
3966 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3967 pbn_oxsemi_1_4000000 },
3968 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
3969 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3970 pbn_oxsemi_1_4000000 },
3971 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
3972 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3973 pbn_oxsemi_1_4000000 },
3974 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
3975 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3976 pbn_oxsemi_1_4000000 },
3977 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
3978 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3979 pbn_oxsemi_1_4000000 },
3980 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
3981 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3982 pbn_oxsemi_1_4000000 },
3983 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
3984 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3985 pbn_oxsemi_1_4000000 },
3986 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
3987 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3988 pbn_oxsemi_1_4000000 },
3989 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
3990 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3991 pbn_oxsemi_1_4000000 },
3992 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
3993 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3994 pbn_oxsemi_1_4000000 },
3995 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
3996 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3997 pbn_oxsemi_1_4000000 },
3998 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
3999 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4000 pbn_oxsemi_1_4000000 },
4001 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4002 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4003 pbn_oxsemi_1_4000000 },
4004 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4005 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4006 pbn_oxsemi_1_4000000 },
4007 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4008 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4009 pbn_oxsemi_1_4000000 },
4010 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4011 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4012 pbn_oxsemi_1_4000000 },
4013 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4014 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4015 pbn_oxsemi_1_4000000 },
4016 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4017 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4018 pbn_oxsemi_1_4000000 },
4019 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4020 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4021 pbn_oxsemi_1_4000000 },
4022 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4023 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4024 pbn_oxsemi_1_4000000 },
4025 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4026 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4027 pbn_oxsemi_1_4000000 },
4028 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4029 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4030 pbn_oxsemi_1_4000000 },
b80de369
LH		 4031 /*
4032 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4033 */
4034 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4035 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4036 pbn_oxsemi_1_4000000 },
4037 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4038 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4039 pbn_oxsemi_2_4000000 },
4040 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4041 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4042 pbn_oxsemi_4_4000000 },
4043 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4044 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4045 pbn_oxsemi_8_4000000 },
aa273ae5
SK		 4046
4047 /*
4048 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4049 */
4050 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4051 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4052 pbn_oxsemi_2_4000000 },
4053
1da177e4
LT		 4054 /*
4055 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4056 * from skokodyn@yahoo.com
4057 */
4058 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4059 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4060 pbn_sbsxrsio },
4061 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4062 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4063 pbn_sbsxrsio },
4064 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4065 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4066 pbn_sbsxrsio },
4067 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4068 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4069 pbn_sbsxrsio },
4070
4071 /*
4072 * Digitan DS560-558, from jimd@esoft.com
4073 */
4074 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
5756ee99 4075 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4076 pbn_b1_1_115200 },
4077
4078 /*
4079 * Titan Electronic cards
4080 * The 400L and 800L have a custom setup quirk.
4081 */
4082 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
5756ee99 4083 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4084 pbn_b0_1_921600 },
4085 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
5756ee99 4086 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4087 pbn_b0_2_921600 },
4088 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
5756ee99 4089 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4090 pbn_b0_4_921600 },
4091 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
5756ee99 4092 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4093 pbn_b0_4_921600 },
4094 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4095 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4096 pbn_b1_1_921600 },
4097 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4098 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4099 pbn_b1_bt_2_921600 },
4100 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4101 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4102 pbn_b0_bt_4_921600 },
4103 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4104 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4105 pbn_b0_bt_8_921600 },
66169ad1
YY		 4106 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4107 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4108 pbn_b4_bt_2_921600 },
4109 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4110 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4111 pbn_b4_bt_4_921600 },
4112 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4113 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4114 pbn_b4_bt_8_921600 },
4115 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4116 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4117 pbn_b0_4_921600 },
4118 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4119 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4120 pbn_b0_4_921600 },
4121 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4122 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4123 pbn_b0_4_921600 },
4124 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4125 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4126 pbn_oxsemi_1_4000000 },
4127 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4128 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4129 pbn_oxsemi_2_4000000 },
4130 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4131 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4132 pbn_oxsemi_4_4000000 },
4133 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4134 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4135 pbn_oxsemi_8_4000000 },
4136 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4137 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4138 pbn_oxsemi_2_4000000 },
4139 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4140 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4141 pbn_oxsemi_2_4000000 },
1e9deb11
YY		 4142 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4143 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4144 pbn_b0_4_921600 },
4145 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4146 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4147 pbn_b0_4_921600 },
4148 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4149 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4150 pbn_b0_4_921600 },
4151 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4152 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4153 pbn_b0_4_921600 },
1da177e4
LT		 4154
4155 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4156 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4157 pbn_b2_1_460800 },
4158 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4159 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4160 pbn_b2_1_460800 },
4161 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4162 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4163 pbn_b2_1_460800 },
4164 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4165 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4166 pbn_b2_bt_2_921600 },
4167 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4168 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4169 pbn_b2_bt_2_921600 },
4170 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4171 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4172 pbn_b2_bt_2_921600 },
4173 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4174 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4175 pbn_b2_bt_4_921600 },
4176 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4177 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4178 pbn_b2_bt_4_921600 },
4179 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4180 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4181 pbn_b2_bt_4_921600 },
4182 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4183 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4184 pbn_b0_1_921600 },
4185 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4186 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4187 pbn_b0_1_921600 },
4188 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4189 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4190 pbn_b0_1_921600 },
4191 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4192 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4193 pbn_b0_bt_2_921600 },
4194 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4195 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4196 pbn_b0_bt_2_921600 },
4197 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4198 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4199 pbn_b0_bt_2_921600 },
4200 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4201 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4202 pbn_b0_bt_4_921600 },
4203 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4204 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4205 pbn_b0_bt_4_921600 },
4206 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4207 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4208 pbn_b0_bt_4_921600 },
3ec9c594
AP		 4209 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4210 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4211 pbn_b0_bt_8_921600 },
4212 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4213 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4214 pbn_b0_bt_8_921600 },
4215 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4216 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4217 pbn_b0_bt_8_921600 },
1da177e4
LT		 4218
4219 /*
4220 * Computone devices submitted by Doug McNash dmcnash@computone.com
4221 */
4222 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4223 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4224 0, 0, pbn_computone_4 },
4225 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4226 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4227 0, 0, pbn_computone_8 },
4228 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4229 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4230 0, 0, pbn_computone_6 },
4231
4232 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4233 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4234 pbn_oxsemi },
4235 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4236 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4237 pbn_b0_bt_1_921600 },
4238
abd7baca
SC		 4239 /*
4240 * SUNIX (TIMEDIA)
4241 */
4242 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4243 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4244 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4245 pbn_b0_bt_1_921600 },
4246
4247 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4248 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4249 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4250 pbn_b0_bt_1_921600 },
4251
1da177e4
LT		 4252 /*
4253 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4254 */
4255 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4256 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4257 pbn_b0_bt_8_115200 },
4258 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4259 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4260 pbn_b0_bt_8_115200 },
4261
4262 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4263 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4264 pbn_b0_bt_2_115200 },
4265 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4266 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4267 pbn_b0_bt_2_115200 },
4268 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4269 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4270 pbn_b0_bt_2_115200 },
b87e5e2b
LB		 4271 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4272 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4273 pbn_b0_bt_2_115200 },
4274 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4275 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4276 pbn_b0_bt_2_115200 },
1da177e4
LT		 4277 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4278 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4279 pbn_b0_bt_4_460800 },
4280 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4281 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4282 pbn_b0_bt_4_460800 },
4283 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4284 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4285 pbn_b0_bt_2_460800 },
4286 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4287 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4288 pbn_b0_bt_2_460800 },
4289 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4290 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4291 pbn_b0_bt_2_460800 },
4292 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4293 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4294 pbn_b0_bt_1_115200 },
4295 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4296 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4297 pbn_b0_bt_1_460800 },
4298
1fb8cacc
RK		 4299 /*
4300 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4301 * Cards are identified by their subsystem vendor IDs, which
4302 * (in hex) match the model number.
4303 *
4304 * Note that JC140x are RS422/485 cards which require ox950
4305 * ACR = 0x10, and as such are not currently fully supported.
4306 */
4307 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4308 0x1204, 0x0004, 0, 0,
4309 pbn_b0_4_921600 },
4310 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4311 0x1208, 0x0004, 0, 0,
4312 pbn_b0_4_921600 },
4313/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4314 0x1402, 0x0002, 0, 0,
4315 pbn_b0_2_921600 }, */
4316/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4317 0x1404, 0x0004, 0, 0,
4318 pbn_b0_4_921600 }, */
4319 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4320 0x1208, 0x0004, 0, 0,
4321 pbn_b0_4_921600 },
4322
2a52fcb5
KY		 4323 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4324 0x1204, 0x0004, 0, 0,
4325 pbn_b0_4_921600 },
4326 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4327 0x1208, 0x0004, 0, 0,
4328 pbn_b0_4_921600 },
4329 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4330 0x1208, 0x0004, 0, 0,
4331 pbn_b0_4_921600 },
1da177e4
LT		 4332 /*
4333 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4334 */
4335 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4336 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4337 pbn_b1_1_1382400 },
4338
4339 /*
4340 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4341 */
4342 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4343 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4344 pbn_b1_1_1382400 },
4345
4346 /*
4347 * RAStel 2 port modem, gerg@moreton.com.au
4348 */
4349 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4350 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4351 pbn_b2_bt_2_115200 },
4352
4353 /*
4354 * EKF addition for i960 Boards form EKF with serial port
4355 */
4356 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4357 0xE4BF, PCI_ANY_ID, 0, 0,
4358 pbn_intel_i960 },
4359
4360 /*
4361 * Xircom Cardbus/Ethernet combos
4362 */
4363 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4364 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4365 pbn_b0_1_115200 },
4366 /*
4367 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4368 */
4369 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4370 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4371 pbn_b0_1_115200 },
4372
4373 /*
4374 * Untested PCI modems, sent in from various folks...
4375 */
4376
4377 /*
4378 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4379 */
4380 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4381 0x1048, 0x1500, 0, 0,
4382 pbn_b1_1_115200 },
4383
4384 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4385 0xFF00, 0, 0, 0,
4386 pbn_sgi_ioc3 },
4387
4388 /*
4389 * HP Diva card
4390 */
4391 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4392 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4393 pbn_b1_1_115200 },
4394 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4395 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4396 pbn_b0_5_115200 },
4397 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4398 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4399 pbn_b2_1_115200 },
4400
d9004eb4
ABL		 4401 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4402 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4403 pbn_b3_2_115200 },
1da177e4
LT		 4404 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4405 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4406 pbn_b3_4_115200 },
4407 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4408 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4409 pbn_b3_8_115200 },
4410
4411 /*
4412 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4413 */
4414 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4415 PCI_ANY_ID, PCI_ANY_ID,
4416 0,
4417 0, pbn_exar_XR17C152 },
4418 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4419 PCI_ANY_ID, PCI_ANY_ID,
4420 0,
4421 0, pbn_exar_XR17C154 },
4422 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4423 PCI_ANY_ID, PCI_ANY_ID,
4424 0,
4425 0, pbn_exar_XR17C158 },
dc96efb7
MS		 4426 /*
4427 * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
4428 */
4429 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4430 PCI_ANY_ID, PCI_ANY_ID,
4431 0,
4432 0, pbn_exar_XR17V352 },
4433 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4434 PCI_ANY_ID, PCI_ANY_ID,
4435 0,
4436 0, pbn_exar_XR17V354 },
4437 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4438 PCI_ANY_ID, PCI_ANY_ID,
4439 0,
4440 0, pbn_exar_XR17V358 },
1da177e4
LT		 4441
4442 /*
4443 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4444 */
4445 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4446 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4447 pbn_b0_1_115200 },
84f8c6fc
NV		 4448 /*
4449 * ITE
4450 */
4451 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4452 PCI_ANY_ID, PCI_ANY_ID,
4453 0, 0,
4454 pbn_b1_bt_1_115200 },
1da177e4 4455
737c1756
PH		 4456 /*
4457 * IntaShield IS-200
4458 */
4459 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4460 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4461 pbn_b2_2_115200 },
4b6f6ce9
IGP		 4462 /*
4463 * IntaShield IS-400
4464 */
4465 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4466 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4467 pbn_b2_4_115200 },
48212008
TH		 4468 /*
4469 * Perle PCI-RAS cards
4470 */
4471 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4472 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4473 0, 0, pbn_b2_4_921600 },
4474 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4475 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4476 0, 0, pbn_b2_8_921600 },
bf0df636
AC		 4477
4478 /*
4479 * Mainpine series cards: Fairly standard layout but fools
4480 * parts of the autodetect in some cases and uses otherwise
4481 * unmatched communications subclasses in the PCI Express case
4482 */
4483
4484 { /* RockForceDUO */
4485 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4486 PCI_VENDOR_ID_MAINPINE, 0x0200,
4487 0, 0, pbn_b0_2_115200 },
4488 { /* RockForceQUATRO */
4489 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4490 PCI_VENDOR_ID_MAINPINE, 0x0300,
4491 0, 0, pbn_b0_4_115200 },
4492 { /* RockForceDUO+ */
4493 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4494 PCI_VENDOR_ID_MAINPINE, 0x0400,
4495 0, 0, pbn_b0_2_115200 },
4496 { /* RockForceQUATRO+ */
4497 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4498 PCI_VENDOR_ID_MAINPINE, 0x0500,
4499 0, 0, pbn_b0_4_115200 },
4500 { /* RockForce+ */
4501 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4502 PCI_VENDOR_ID_MAINPINE, 0x0600,
4503 0, 0, pbn_b0_2_115200 },
4504 { /* RockForce+ */
4505 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4506 PCI_VENDOR_ID_MAINPINE, 0x0700,
4507 0, 0, pbn_b0_4_115200 },
4508 { /* RockForceOCTO+ */
4509 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4510 PCI_VENDOR_ID_MAINPINE, 0x0800,
4511 0, 0, pbn_b0_8_115200 },
4512 { /* RockForceDUO+ */
4513 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4514 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4515 0, 0, pbn_b0_2_115200 },
4516 { /* RockForceQUARTRO+ */
4517 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4518 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4519 0, 0, pbn_b0_4_115200 },
4520 { /* RockForceOCTO+ */
4521 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4522 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4523 0, 0, pbn_b0_8_115200 },
4524 { /* RockForceD1 */
4525 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4526 PCI_VENDOR_ID_MAINPINE, 0x2000,
4527 0, 0, pbn_b0_1_115200 },
4528 { /* RockForceF1 */
4529 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4530 PCI_VENDOR_ID_MAINPINE, 0x2100,
4531 0, 0, pbn_b0_1_115200 },
4532 { /* RockForceD2 */
4533 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4534 PCI_VENDOR_ID_MAINPINE, 0x2200,
4535 0, 0, pbn_b0_2_115200 },
4536 { /* RockForceF2 */
4537 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4538 PCI_VENDOR_ID_MAINPINE, 0x2300,
4539 0, 0, pbn_b0_2_115200 },
4540 { /* RockForceD4 */
4541 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4542 PCI_VENDOR_ID_MAINPINE, 0x2400,
4543 0, 0, pbn_b0_4_115200 },
4544 { /* RockForceF4 */
4545 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4546 PCI_VENDOR_ID_MAINPINE, 0x2500,
4547 0, 0, pbn_b0_4_115200 },
4548 { /* RockForceD8 */
4549 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4550 PCI_VENDOR_ID_MAINPINE, 0x2600,
4551 0, 0, pbn_b0_8_115200 },
4552 { /* RockForceF8 */
4553 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4554 PCI_VENDOR_ID_MAINPINE, 0x2700,
4555 0, 0, pbn_b0_8_115200 },
4556 { /* IQ Express D1 */
4557 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4558 PCI_VENDOR_ID_MAINPINE, 0x3000,
4559 0, 0, pbn_b0_1_115200 },
4560 { /* IQ Express F1 */
4561 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4562 PCI_VENDOR_ID_MAINPINE, 0x3100,
4563 0, 0, pbn_b0_1_115200 },
4564 { /* IQ Express D2 */
4565 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4566 PCI_VENDOR_ID_MAINPINE, 0x3200,
4567 0, 0, pbn_b0_2_115200 },
4568 { /* IQ Express F2 */
4569 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4570 PCI_VENDOR_ID_MAINPINE, 0x3300,
4571 0, 0, pbn_b0_2_115200 },
4572 { /* IQ Express D4 */
4573 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4574 PCI_VENDOR_ID_MAINPINE, 0x3400,
4575 0, 0, pbn_b0_4_115200 },
4576 { /* IQ Express F4 */
4577 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4578 PCI_VENDOR_ID_MAINPINE, 0x3500,
4579 0, 0, pbn_b0_4_115200 },
4580 { /* IQ Express D8 */
4581 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4582 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4583 0, 0, pbn_b0_8_115200 },
4584 { /* IQ Express F8 */
4585 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4586 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4587 0, 0, pbn_b0_8_115200 },
4588
4589
aa798505
OJ		 4590 /*
4591 * PA Semi PA6T-1682M on-chip UART
4592 */
4593 { PCI_VENDOR_ID_PASEMI, 0xa004,
4594 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4595 pbn_pasemi_1682M },
4596
46a0fac9
SB		 4597 /*
4598 * National Instruments
4599 */
04bf7e74
WP		 4600 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4601 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4602 pbn_b1_16_115200 },
4603 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605 pbn_b1_8_115200 },
4606 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4607 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4608 pbn_b1_bt_4_115200 },
4609 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4610 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4611 pbn_b1_bt_2_115200 },
4612 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4613 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4614 pbn_b1_bt_4_115200 },
4615 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4616 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4617 pbn_b1_bt_2_115200 },
4618 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4619 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4620 pbn_b1_16_115200 },
4621 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4622 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4623 pbn_b1_8_115200 },
4624 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4625 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4626 pbn_b1_bt_4_115200 },
4627 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4628 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4629 pbn_b1_bt_2_115200 },
4630 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4631 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4632 pbn_b1_bt_4_115200 },
4633 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4634 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4635 pbn_b1_bt_2_115200 },
46a0fac9
SB		 4636 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4637 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4638 pbn_ni8430_2 },
4639 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4640 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4641 pbn_ni8430_2 },
4642 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4643 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4644 pbn_ni8430_4 },
4645 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
4646 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4647 pbn_ni8430_4 },
4648 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
4649 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4650 pbn_ni8430_8 },
4651 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
4652 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4653 pbn_ni8430_8 },
4654 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
4655 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4656 pbn_ni8430_16 },
4657 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
4658 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4659 pbn_ni8430_16 },
4660 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
4661 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4662 pbn_ni8430_2 },
4663 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
4664 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4665 pbn_ni8430_2 },
4666 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
4667 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4668 pbn_ni8430_4 },
4669 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
4670 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4671 pbn_ni8430_4 },
4672
02c9b5cf
KJ		 4673 /*
4674 * ADDI-DATA GmbH communication cards <info@addi-data.com>
4675 */
4676 { PCI_VENDOR_ID_ADDIDATA,
4677 PCI_DEVICE_ID_ADDIDATA_APCI7500,
4678 PCI_ANY_ID,
4679 PCI_ANY_ID,
4680 0,
4681 0,
4682 pbn_b0_4_115200 },
4683
4684 { PCI_VENDOR_ID_ADDIDATA,
4685 PCI_DEVICE_ID_ADDIDATA_APCI7420,
4686 PCI_ANY_ID,
4687 PCI_ANY_ID,
4688 0,
4689 0,
4690 pbn_b0_2_115200 },
4691
4692 { PCI_VENDOR_ID_ADDIDATA,
4693 PCI_DEVICE_ID_ADDIDATA_APCI7300,
4694 PCI_ANY_ID,
4695 PCI_ANY_ID,
4696 0,
4697 0,
4698 pbn_b0_1_115200 },
4699
4700 { PCI_VENDOR_ID_ADDIDATA_OLD,
4701 PCI_DEVICE_ID_ADDIDATA_APCI7800,
4702 PCI_ANY_ID,
4703 PCI_ANY_ID,
4704 0,
4705 0,
4706 pbn_b1_8_115200 },
4707
4708 { PCI_VENDOR_ID_ADDIDATA,
4709 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
4710 PCI_ANY_ID,
4711 PCI_ANY_ID,
4712 0,
4713 0,
4714 pbn_b0_4_115200 },
4715
4716 { PCI_VENDOR_ID_ADDIDATA,
4717 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
4718 PCI_ANY_ID,
4719 PCI_ANY_ID,
4720 0,
4721 0,
4722 pbn_b0_2_115200 },
4723
4724 { PCI_VENDOR_ID_ADDIDATA,
4725 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4726 PCI_ANY_ID,
4727 PCI_ANY_ID,
4728 0,
4729 0,
4730 pbn_b0_1_115200 },
4731
4732 { PCI_VENDOR_ID_ADDIDATA,
4733 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4734 PCI_ANY_ID,
4735 PCI_ANY_ID,
4736 0,
4737 0,
4738 pbn_b0_4_115200 },
4739
4740 { PCI_VENDOR_ID_ADDIDATA,
4741 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4742 PCI_ANY_ID,
4743 PCI_ANY_ID,
4744 0,
4745 0,
4746 pbn_b0_2_115200 },
4747
4748 { PCI_VENDOR_ID_ADDIDATA,
4749 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4750 PCI_ANY_ID,
4751 PCI_ANY_ID,
4752 0,
4753 0,
4754 pbn_b0_1_115200 },
4755
4756 { PCI_VENDOR_ID_ADDIDATA,
4757 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4758 PCI_ANY_ID,
4759 PCI_ANY_ID,
4760 0,
4761 0,
4762 pbn_b0_8_115200 },
4763
1b62cbf2
KJ		 4764 { PCI_VENDOR_ID_ADDIDATA,
4765 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4766 PCI_ANY_ID,
4767 PCI_ANY_ID,
4768 0,
4769 0,
4770 pbn_ADDIDATA_PCIe_4_3906250 },
4771
4772 { PCI_VENDOR_ID_ADDIDATA,
4773 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4774 PCI_ANY_ID,
4775 PCI_ANY_ID,
4776 0,
4777 0,
4778 pbn_ADDIDATA_PCIe_2_3906250 },
4779
4780 { PCI_VENDOR_ID_ADDIDATA,
4781 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4782 PCI_ANY_ID,
4783 PCI_ANY_ID,
4784 0,
4785 0,
4786 pbn_ADDIDATA_PCIe_1_3906250 },
4787
4788 { PCI_VENDOR_ID_ADDIDATA,
4789 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4790 PCI_ANY_ID,
4791 PCI_ANY_ID,
4792 0,
4793 0,
4794 pbn_ADDIDATA_PCIe_8_3906250 },
4795
25cf9bc1
JS		 4796 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4797 PCI_VENDOR_ID_IBM, 0x0299,
4798 0, 0, pbn_b0_bt_2_115200 },
4799
8d2f8cd4
WY		 4800 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4801 0x1000, 0x0012,
4802 0, 0, pbn_b0_bt_2_115200 },
4803
c4285b47
MB		 4804 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4805 0xA000, 0x1000,
4806 0, 0, pbn_b0_1_115200 },
4807
7808edcd
NG		 4808 /* the 9901 is a rebranded 9912 */
4809 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4810 0xA000, 0x1000,
4811 0, 0, pbn_b0_1_115200 },
4812
4813 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4814 0xA000, 0x1000,
4815 0, 0, pbn_b0_1_115200 },
4816
4817 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4818 0xA000, 0x1000,
4819 0, 0, pbn_b0_1_115200 },
4820
4821 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4822 0xA000, 0x1000,
4823 0, 0, pbn_b0_1_115200 },
4824
4825 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4826 0xA000, 0x3002,
4827 0, 0, pbn_NETMOS9900_2s_115200 },
4828
ac6ec5b1 4829 /*
44178176 4830 * Best Connectivity and Rosewill PCI Multi I/O cards
ac6ec5b1
IS		 4831 */
4832
4833 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4834 0xA000, 0x1000,
4835 0, 0, pbn_b0_1_115200 },
4836
44178176
ES		 4837 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4838 0xA000, 0x3002,
4839 0, 0, pbn_b0_bt_2_115200 },
4840
ac6ec5b1
IS		 4841 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4842 0xA000, 0x3004,
4843 0, 0, pbn_b0_bt_4_115200 },
095e24b0
DB		 4844 /* Intel CE4100 */
4845 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4846 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4847 pbn_ce4100_1_115200 },
4848
d9a0fbfd
AP		 4849 /*
4850 * Cronyx Omega PCI
4851 */
4852 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4853 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4854 pbn_omegapci },
ac6ec5b1 4855
ebebd49a
SH		 4856 /*
4857 * Broadcom TruManage
4858 */
4859 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
4860 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4861 pbn_brcm_trumanage },
4862
6683549e
AC		 4863 /*
4864 * AgeStar as-prs2-009
4865 */
4866 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
4867 PCI_ANY_ID, PCI_ANY_ID,
4868 0, 0, pbn_b0_bt_2_115200 },
27788c5f
AC		 4869
4870 /*
4871 * WCH CH353 series devices: The 2S1P is handled by parport_serial
4872 * so not listed here.
4873 */
4874 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
4875 PCI_ANY_ID, PCI_ANY_ID,
4876 0, 0, pbn_b0_bt_4_115200 },
4877
4878 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
4879 PCI_ANY_ID, PCI_ANY_ID,
4880 0, 0, pbn_b0_bt_2_115200 },
4881
8b5c913f
WY		 4882 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH352_2S,
4883 PCI_ANY_ID, PCI_ANY_ID,
4884 0, 0, pbn_b0_bt_2_115200 },
4885
14faa8cc
MS		 4886 /*
4887 * Commtech, Inc. Fastcom adapters
4888 */
4889 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
4890 PCI_ANY_ID, PCI_ANY_ID,
4891 0,
4892 0, pbn_b0_2_1152000_200 },
4893 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
4894 PCI_ANY_ID, PCI_ANY_ID,
4895 0,
4896 0, pbn_b0_4_1152000_200 },
4897 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
4898 PCI_ANY_ID, PCI_ANY_ID,
4899 0,
4900 0, pbn_b0_4_1152000_200 },
4901 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
4902 PCI_ANY_ID, PCI_ANY_ID,
4903 0,
4904 0, pbn_b0_8_1152000_200 },
4905 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
4906 PCI_ANY_ID, PCI_ANY_ID,
4907 0,
4908 0, pbn_exar_XR17V352 },
4909 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
4910 PCI_ANY_ID, PCI_ANY_ID,
4911 0,
4912 0, pbn_exar_XR17V354 },
4913 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
4914 PCI_ANY_ID, PCI_ANY_ID,
4915 0,
4916 0, pbn_exar_XR17V358 },
4917
1da177e4
LT		 4918 /*
4919 * These entries match devices with class COMMUNICATION_SERIAL,
4920 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4921 */
4922 { PCI_ANY_ID, PCI_ANY_ID,
4923 PCI_ANY_ID, PCI_ANY_ID,
4924 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4925 0xffff00, pbn_default },
4926 { PCI_ANY_ID, PCI_ANY_ID,
4927 PCI_ANY_ID, PCI_ANY_ID,
4928 PCI_CLASS_COMMUNICATION_MODEM << 8,
4929 0xffff00, pbn_default },
4930 { PCI_ANY_ID, PCI_ANY_ID,
4931 PCI_ANY_ID, PCI_ANY_ID,
4932 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4933 0xffff00, pbn_default },
4934 { 0, }
4935};
4936
2807190b
MR		 4937static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4938 pci_channel_state_t state)
4939{
4940 struct serial_private *priv = pci_get_drvdata(dev);
4941
4942 if (state == pci_channel_io_perm_failure)
4943 return PCI_ERS_RESULT_DISCONNECT;
4944
4945 if (priv)
4946 pciserial_suspend_ports(priv);
4947
4948 pci_disable_device(dev);
4949
4950 return PCI_ERS_RESULT_NEED_RESET;
4951}
4952
4953static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4954{
4955 int rc;
4956
4957 rc = pci_enable_device(dev);
4958
4959 if (rc)
4960 return PCI_ERS_RESULT_DISCONNECT;
4961
4962 pci_restore_state(dev);
4963 pci_save_state(dev);
4964
4965 return PCI_ERS_RESULT_RECOVERED;
4966}
4967
4968static void serial8250_io_resume(struct pci_dev *dev)
4969{
4970 struct serial_private *priv = pci_get_drvdata(dev);
4971
4972 if (priv)
4973 pciserial_resume_ports(priv);
4974}
4975
1d352035 4976static const struct pci_error_handlers serial8250_err_handler = {
2807190b
MR		 4977 .error_detected = serial8250_io_error_detected,
4978 .slot_reset = serial8250_io_slot_reset,
4979 .resume = serial8250_io_resume,
4980};
4981
1da177e4
LT		 4982static struct pci_driver serial_pci_driver = {
4983 .name = "serial",
4984 .probe = pciserial_init_one,
2d47b716 4985 .remove = pciserial_remove_one,
1d5e7996 4986#ifdef CONFIG_PM
1da177e4
LT		 4987 .suspend = pciserial_suspend_one,
4988 .resume = pciserial_resume_one,
1d5e7996 4989#endif
1da177e4 4990 .id_table = serial_pci_tbl,
2807190b 4991 .err_handler = &serial8250_err_handler,
1da177e4
LT		 4992};
4993
15a12e83 4994module_pci_driver(serial_pci_driver);
1da177e4
LT		 4995
4996MODULE_LICENSE("GPL");
4997MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4998MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linux kernel - Deliverables
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