projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sc16is7xx: use kthread_worker for tx_work and irq
[deliverable/linux.git] / drivers / tty / serial / sc16is7xx.c
CommitLineData
dfeae619
JR		 1/*
2 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
3 * Author: Jon Ringle <jringle@gridpoint.com>
4 *
5 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13
14#include <linux/bitops.h>
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/device.h>
18#include <linux/gpio.h>
19#include <linux/i2c.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/regmap.h>
24#include <linux/serial_core.h>
25#include <linux/serial.h>
26#include <linux/tty.h>
27#include <linux/tty_flip.h>
2c837a8a 28#include <linux/spi/spi.h>
d952795d 29#include <linux/uaccess.h>
dfeae619
JR		 30
31#define SC16IS7XX_NAME "sc16is7xx"
32
33/* SC16IS7XX register definitions */
34#define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
35#define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
36#define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
37#define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
38#define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
39#define SC16IS7XX_LCR_REG (0x03) /* Line Control */
40#define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
41#define SC16IS7XX_LSR_REG (0x05) /* Line Status */
42#define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
43#define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
44#define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
45#define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
46#define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
47 * - only on 75x/76x
48 */
49#define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
50 * - only on 75x/76x
51 */
52#define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
53 * - only on 75x/76x
54 */
55#define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
56 * - only on 75x/76x
57 */
58#define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
59
60/* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
61#define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
62#define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
63
64/* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
65#define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
66#define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
67
68/* Enhanced Register set: Only if (LCR == 0xBF) */
69#define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
70#define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
71#define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
72#define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
73#define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
74
75/* IER register bits */
76#define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */
77#define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register
78 * interrupt */
79#define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status
80 * interrupt */
81#define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status
82 * interrupt */
83
84/* IER register bits - write only if (EFR[4] == 1) */
85#define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */
86#define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */
87#define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */
88#define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */
89
90/* FCR register bits */
91#define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */
92#define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */
93#define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */
94#define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */
95#define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */
96
97/* FCR register bits - write only if (EFR[4] == 1) */
98#define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */
99#define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */
100
101/* IIR register bits */
102#define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */
103#define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */
104#define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
105#define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
106#define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
107#define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
108#define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
109 * - only on 75x/76x
110 */
111#define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
112 * - only on 75x/76x
113 */
114#define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
115#define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
116 * from active (LOW)
117 * to inactive (HIGH)
118 */
119/* LCR register bits */
120#define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
121#define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
122 *
123 * Word length bits table:
124 * 00 -> 5 bit words
125 * 01 -> 6 bit words
126 * 10 -> 7 bit words
127 * 11 -> 8 bit words
128 */
129#define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
130 *
131 * STOP length bit table:
132 * 0 -> 1 stop bit
133 * 1 -> 1-1.5 stop bits if
134 * word length is 5,
135 * 2 stop bits otherwise
136 */
137#define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
138#define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
139#define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
140#define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
141#define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */
142#define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
143#define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
144#define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
145#define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
146#define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special
147 * reg set */
148#define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced
149 * reg set */
150
151/* MCR register bits */
152#define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement
153 * - only on 75x/76x
154 */
155#define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */
156#define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */
157#define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */
158#define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any
159 * - write enabled
160 * if (EFR[4] == 1)
161 */
162#define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode
163 * - write enabled
164 * if (EFR[4] == 1)
165 */
166#define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4
167 * - write enabled
168 * if (EFR[4] == 1)
169 */
170
171/* LSR register bits */
172#define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */
173#define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */
174#define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */
175#define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */
176#define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */
177#define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */
178#define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */
179#define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */
180#define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */
181
182/* MSR register bits */
183#define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */
184#define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready
185 * or (IO4)
186 * - only on 75x/76x
187 */
188#define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator
189 * or (IO7)
190 * - only on 75x/76x
191 */
192#define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect
193 * or (IO6)
194 * - only on 75x/76x
195 */
196#define SC16IS7XX_MSR_CTS_BIT (1 << 0) /* CTS */
197#define SC16IS7XX_MSR_DSR_BIT (1 << 1) /* DSR (IO4)
198 * - only on 75x/76x
199 */
200#define SC16IS7XX_MSR_RI_BIT (1 << 2) /* RI (IO7)
201 * - only on 75x/76x
202 */
203#define SC16IS7XX_MSR_CD_BIT (1 << 3) /* CD (IO6)
204 * - only on 75x/76x
205 */
206#define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */
207
208/*
209 * TCR register bits
210 * TCR trigger levels are available from 0 to 60 characters with a granularity
211 * of four.
212 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
213 * no built-in hardware check to make sure this condition is met. Also, the TCR
214 * must be programmed with this condition before auto RTS or software flow
215 * control is enabled to avoid spurious operation of the device.
216 */
217#define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
218#define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
219
220/*
221 * TLR register bits
222 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
223 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
224 * trigger levels. Trigger levels from 4 characters to 60 characters are
225 * available with a granularity of four.
226 *
227 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
228 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
229 * the trigger level defined in FCR is discarded. This applies to both transmit
230 * FIFO and receive FIFO trigger level setting.
231 *
232 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
233 * default state, that is, '00'.
234 */
235#define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
236#define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
237
238/* IOControl register bits (Only 750/760) */
239#define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */
240#define SC16IS7XX_IOCONTROL_GPIO_BIT (1 << 1) /* Enable GPIO[7:4] */
241#define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */
242
243/* EFCR register bits */
244#define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop
245 * mode (RS485) */
246#define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */
247#define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */
248#define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */
249#define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */
250#define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode
251 * 0 = rate upto 115.2 kbit/s
252 * - Only 750/760
253 * 1 = rate upto 1.152 Mbit/s
254 * - Only 760
255 */
256
257/* EFR register bits */
258#define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */
259#define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */
260#define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */
261#define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions
262 * and writing to IER[7:4],
263 * FCR[5:4], MCR[7:5]
264 */
265#define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */
266#define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2
267 *
268 * SWFLOW bits 3 & 2 table:
269 * 00 -> no transmitter flow
270 * control
271 * 01 -> transmitter generates
272 * XON2 and XOFF2
273 * 10 -> transmitter generates
274 * XON1 and XOFF1
275 * 11 -> transmitter generates
276 * XON1, XON2, XOFF1 and
277 * XOFF2
278 */
279#define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */
280#define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3
281 *
282 * SWFLOW bits 3 & 2 table:
283 * 00 -> no received flow
284 * control
285 * 01 -> receiver compares
286 * XON2 and XOFF2
287 * 10 -> receiver compares
288 * XON1 and XOFF1
289 * 11 -> receiver compares
290 * XON1, XON2, XOFF1 and
291 * XOFF2
292 */
293
294/* Misc definitions */
295#define SC16IS7XX_FIFO_SIZE (64)
296#define SC16IS7XX_REG_SHIFT 2
297
298struct sc16is7xx_devtype {
299 char name[10];
300 int nr_gpio;
301 int nr_uart;
302};
303
304struct sc16is7xx_one {
305 struct uart_port port;
9e6f4ca3 306 struct kthread_work tx_work;
dfeae619 307 struct work_struct md_work;
dfeae619
JR		 308};
309
310struct sc16is7xx_port {
311 struct uart_driver uart;
312 struct sc16is7xx_devtype *devtype;
313 struct regmap *regmap;
dfeae619
JR		 314 struct clk *clk;
315#ifdef CONFIG_GPIOLIB
316 struct gpio_chip gpio;
317#endif
beb04a9f 318 unsigned char buf[SC16IS7XX_FIFO_SIZE];
9e6f4ca3
JK		 319 struct kthread_worker kworker;
320 struct task_struct *kworker_task;
321 struct kthread_work irq_work;
dfeae619
JR		 322 struct sc16is7xx_one p[0];
323};
324
9e6f4ca3 325#define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e)))
dfeae619
JR		 326#define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
327
328static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
329{
330 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
331 unsigned int val = 0;
332
333 regmap_read(s->regmap,
334 (reg << SC16IS7XX_REG_SHIFT) | port->line, &val);
335
336 return val;
337}
338
339static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
340{
341 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
342
343 regmap_write(s->regmap,
344 (reg << SC16IS7XX_REG_SHIFT) | port->line, val);
345}
346
347static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
348 u8 mask, u8 val)
349{
350 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
351
352 regmap_update_bits(s->regmap,
353 (reg << SC16IS7XX_REG_SHIFT) | port->line,
354 mask, val);
355}
356
357
358static void sc16is7xx_power(struct uart_port *port, int on)
359{
360 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
361 SC16IS7XX_IER_SLEEP_BIT,
362 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
363}
364
365static const struct sc16is7xx_devtype sc16is74x_devtype = {
366 .name = "SC16IS74X",
367 .nr_gpio = 0,
368 .nr_uart = 1,
369};
370
371static const struct sc16is7xx_devtype sc16is750_devtype = {
372 .name = "SC16IS750",
373 .nr_gpio = 8,
374 .nr_uart = 1,
375};
376
377static const struct sc16is7xx_devtype sc16is752_devtype = {
378 .name = "SC16IS752",
379 .nr_gpio = 8,
380 .nr_uart = 2,
381};
382
383static const struct sc16is7xx_devtype sc16is760_devtype = {
384 .name = "SC16IS760",
385 .nr_gpio = 8,
386 .nr_uart = 1,
387};
388
389static const struct sc16is7xx_devtype sc16is762_devtype = {
390 .name = "SC16IS762",
391 .nr_gpio = 8,
392 .nr_uart = 2,
393};
394
395static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
396{
397 switch (reg >> SC16IS7XX_REG_SHIFT) {
398 case SC16IS7XX_RHR_REG:
399 case SC16IS7XX_IIR_REG:
400 case SC16IS7XX_LSR_REG:
401 case SC16IS7XX_MSR_REG:
402 case SC16IS7XX_TXLVL_REG:
403 case SC16IS7XX_RXLVL_REG:
404 case SC16IS7XX_IOSTATE_REG:
405 return true;
406 default:
407 break;
408 }
409
410 return false;
411}
412
413static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
414{
415 switch (reg >> SC16IS7XX_REG_SHIFT) {
416 case SC16IS7XX_RHR_REG:
417 return true;
418 default:
419 break;
420 }
421
422 return false;
423}
424
425static int sc16is7xx_set_baud(struct uart_port *port, int baud)
426{
427 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
428 u8 lcr;
429 u8 prescaler = 0;
430 unsigned long clk = port->uartclk, div = clk / 16 / baud;
431
432 if (div > 0xffff) {
433 prescaler = SC16IS7XX_MCR_CLKSEL_BIT;
434 div /= 4;
435 }
436
437 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
438
439 /* Open the LCR divisors for configuration */
440 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
441 SC16IS7XX_LCR_CONF_MODE_B);
442
443 /* Enable enhanced features */
444 regcache_cache_bypass(s->regmap, true);
445 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
446 SC16IS7XX_EFR_ENABLE_BIT);
447 regcache_cache_bypass(s->regmap, false);
448
449 /* Put LCR back to the normal mode */
450 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
451
452 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
453 SC16IS7XX_MCR_CLKSEL_BIT,
454 prescaler);
455
456 /* Open the LCR divisors for configuration */
457 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
458 SC16IS7XX_LCR_CONF_MODE_A);
459
460 /* Write the new divisor */
461 regcache_cache_bypass(s->regmap, true);
462 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
463 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
464 regcache_cache_bypass(s->regmap, false);
465
466 /* Put LCR back to the normal mode */
467 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
468
469 return DIV_ROUND_CLOSEST(clk / 16, div);
470}
471
472static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
473 unsigned int iir)
474{
475 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
476 unsigned int lsr = 0, ch, flag, bytes_read, i;
dfeae619
JR		 477 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
478
beb04a9f 479 if (unlikely(rxlen >= sizeof(s->buf))) {
dfeae619
JR		 480 dev_warn_ratelimited(port->dev,
481 "Port %i: Possible RX FIFO overrun: %d\n",
482 port->line, rxlen);
483 port->icount.buf_overrun++;
484 /* Ensure sanity of RX level */
beb04a9f 485 rxlen = sizeof(s->buf);
dfeae619
JR		 486 }
487
488 while (rxlen) {
489 /* Only read lsr if there are possible errors in FIFO */
490 if (read_lsr) {
491 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
492 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
493 read_lsr = false; /* No errors left in FIFO */
494 } else
495 lsr = 0;
496
497 if (read_lsr) {
beb04a9f 498 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
dfeae619
JR		 499 bytes_read = 1;
500 } else {
501 regcache_cache_bypass(s->regmap, true);
502 regmap_raw_read(s->regmap, SC16IS7XX_RHR_REG,
beb04a9f 503 s->buf, rxlen);
dfeae619
JR		 504 regcache_cache_bypass(s->regmap, false);
505 bytes_read = rxlen;
506 }
507
508 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
509
510 port->icount.rx++;
511 flag = TTY_NORMAL;
512
513 if (unlikely(lsr)) {
514 if (lsr & SC16IS7XX_LSR_BI_BIT) {
515 port->icount.brk++;
516 if (uart_handle_break(port))
517 continue;
518 } else if (lsr & SC16IS7XX_LSR_PE_BIT)
519 port->icount.parity++;
520 else if (lsr & SC16IS7XX_LSR_FE_BIT)
521 port->icount.frame++;
522 else if (lsr & SC16IS7XX_LSR_OE_BIT)
523 port->icount.overrun++;
524
525 lsr &= port->read_status_mask;
526 if (lsr & SC16IS7XX_LSR_BI_BIT)
527 flag = TTY_BREAK;
528 else if (lsr & SC16IS7XX_LSR_PE_BIT)
529 flag = TTY_PARITY;
530 else if (lsr & SC16IS7XX_LSR_FE_BIT)
531 flag = TTY_FRAME;
532 else if (lsr & SC16IS7XX_LSR_OE_BIT)
533 flag = TTY_OVERRUN;
534 }
535
536 for (i = 0; i < bytes_read; ++i) {
beb04a9f 537 ch = s->buf[i];
dfeae619
JR		 538 if (uart_handle_sysrq_char(port, ch))
539 continue;
540
541 if (lsr & port->ignore_status_mask)
542 continue;
543
544 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
545 flag);
546 }
547 rxlen -= bytes_read;
548 }
549
550 tty_flip_buffer_push(&port->state->port);
551}
552
553static void sc16is7xx_handle_tx(struct uart_port *port)
554{
555 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
556 struct circ_buf *xmit = &port->state->xmit;
557 unsigned int txlen, to_send, i;
dfeae619
JR		 558
559 if (unlikely(port->x_char)) {
560 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
561 port->icount.tx++;
562 port->x_char = 0;
563 return;
564 }
565
566 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
567 return;
568
569 /* Get length of data pending in circular buffer */
570 to_send = uart_circ_chars_pending(xmit);
571 if (likely(to_send)) {
572 /* Limit to size of TX FIFO */
573 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
574 to_send = (to_send > txlen) ? txlen : to_send;
575
576 /* Add data to send */
577 port->icount.tx += to_send;
578
579 /* Convert to linear buffer */
580 for (i = 0; i < to_send; ++i) {
beb04a9f 581 s->buf[i] = xmit->buf[xmit->tail];
dfeae619
JR		 582 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
583 }
584 regcache_cache_bypass(s->regmap, true);
beb04a9f 585 regmap_raw_write(s->regmap, SC16IS7XX_THR_REG, s->buf, to_send);
dfeae619
JR		 586 regcache_cache_bypass(s->regmap, false);
587 }
588
589 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
590 uart_write_wakeup(port);
591}
592
593static void sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
594{
595 struct uart_port *port = &s->p[portno].port;
596
597 do {
598 unsigned int iir, msr, rxlen;
599
600 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
601 if (iir & SC16IS7XX_IIR_NO_INT_BIT)
602 break;
603
604 iir &= SC16IS7XX_IIR_ID_MASK;
605
606 switch (iir) {
607 case SC16IS7XX_IIR_RDI_SRC:
608 case SC16IS7XX_IIR_RLSE_SRC:
609 case SC16IS7XX_IIR_RTOI_SRC:
610 case SC16IS7XX_IIR_XOFFI_SRC:
611 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
612 if (rxlen)
613 sc16is7xx_handle_rx(port, rxlen, iir);
614 break;
615
616 case SC16IS7XX_IIR_CTSRTS_SRC:
617 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG);
618 uart_handle_cts_change(port,
619 !!(msr & SC16IS7XX_MSR_CTS_BIT));
620 break;
621 case SC16IS7XX_IIR_THRI_SRC:
dfeae619 622 sc16is7xx_handle_tx(port);
dfeae619
JR		 623 break;
624 default:
625 dev_err_ratelimited(port->dev,
626 "Port %i: Unexpected interrupt: %x",
627 port->line, iir);
628 break;
629 }
630 } while (1);
631}
632
9e6f4ca3 633static void sc16is7xx_ist(struct kthread_work *ws)
dfeae619 634{
9e6f4ca3 635 struct sc16is7xx_port *s = to_sc16is7xx_port(ws, irq_work);
dfeae619
JR		 636 int i;
637
638 for (i = 0; i < s->uart.nr; ++i)
639 sc16is7xx_port_irq(s, i);
9e6f4ca3
JK		 640}
641
642static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
643{
644 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
645
646 queue_kthread_work(&s->kworker, &s->irq_work);
dfeae619
JR		 647
648 return IRQ_HANDLED;
649}
650
9e6f4ca3 651static void sc16is7xx_tx_proc(struct kthread_work *ws)
dfeae619
JR		 652{
653 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, tx_work);
dfeae619 654
dfeae619 655 sc16is7xx_handle_tx(&one->port);
dfeae619
JR		 656}
657
658static void sc16is7xx_stop_tx(struct uart_port* port)
659{
dfeae619
JR		 660 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
661 SC16IS7XX_IER_THRI_BIT,
662 0);
663}
664
665static void sc16is7xx_stop_rx(struct uart_port* port)
666{
667 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
668
669 one->port.read_status_mask &= ~SC16IS7XX_LSR_DR_BIT;
670 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
671 SC16IS7XX_LSR_DR_BIT,
672 0);
673}
674
675static void sc16is7xx_start_tx(struct uart_port *port)
676{
9e6f4ca3 677 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
dfeae619
JR		 678 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
679
680 /* handle rs485 */
b57d15fe
RRD		 681 if ((port->rs485.flags & SER_RS485_ENABLED) &&
682 (port->rs485.delay_rts_before_send > 0)) {
683 mdelay(port->rs485.delay_rts_before_send);
dfeae619
JR		 684 }
685
9e6f4ca3 686 queue_kthread_work(&s->kworker, &one->tx_work);
dfeae619
JR		 687}
688
689static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
690{
4ae82e5d 691 unsigned int lsr;
dfeae619 692
dfeae619
JR		 693 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
694
4ae82e5d 695 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;
dfeae619
JR		 696}
697
698static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
699{
700 /* DCD and DSR are not wired and CTS/RTS is handled automatically
701 * so just indicate DSR and CAR asserted
702 */
703 return TIOCM_DSR | TIOCM_CAR;
704}
705
706static void sc16is7xx_md_proc(struct work_struct *ws)
707{
708 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, md_work);
709
710 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
711 SC16IS7XX_MCR_LOOP_BIT,
712 (one->port.mctrl & TIOCM_LOOP) ?
713 SC16IS7XX_MCR_LOOP_BIT : 0);
714}
715
716static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
717{
718 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
719
720 schedule_work(&one->md_work);
721}
722
723static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
724{
725 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
726 SC16IS7XX_LCR_TXBREAK_BIT,
727 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
728}
729
730static void sc16is7xx_set_termios(struct uart_port *port,
731 struct ktermios *termios,
732 struct ktermios *old)
733{
734 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
735 unsigned int lcr, flow = 0;
736 int baud;
737
738 /* Mask termios capabilities we don't support */
739 termios->c_cflag &= ~CMSPAR;
740
741 /* Word size */
742 switch (termios->c_cflag & CSIZE) {
743 case CS5:
744 lcr = SC16IS7XX_LCR_WORD_LEN_5;
745 break;
746 case CS6:
747 lcr = SC16IS7XX_LCR_WORD_LEN_6;
748 break;
749 case CS7:
750 lcr = SC16IS7XX_LCR_WORD_LEN_7;
751 break;
752 case CS8:
753 lcr = SC16IS7XX_LCR_WORD_LEN_8;
754 break;
755 default:
756 lcr = SC16IS7XX_LCR_WORD_LEN_8;
757 termios->c_cflag &= ~CSIZE;
758 termios->c_cflag |= CS8;
759 break;
760 }
761
762 /* Parity */
763 if (termios->c_cflag & PARENB) {
764 lcr |= SC16IS7XX_LCR_PARITY_BIT;
765 if (!(termios->c_cflag & PARODD))
766 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
767 }
768
769 /* Stop bits */
770 if (termios->c_cflag & CSTOPB)
771 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
772
773 /* Set read status mask */
774 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
775 if (termios->c_iflag & INPCK)
776 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
777 SC16IS7XX_LSR_FE_BIT;
778 if (termios->c_iflag & (BRKINT | PARMRK))
779 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
780
781 /* Set status ignore mask */
782 port->ignore_status_mask = 0;
783 if (termios->c_iflag & IGNBRK)
784 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
785 if (!(termios->c_cflag & CREAD))
786 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
787
788 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
789 SC16IS7XX_LCR_CONF_MODE_B);
790
791 /* Configure flow control */
792 regcache_cache_bypass(s->regmap, true);
793 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
794 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
795 if (termios->c_cflag & CRTSCTS)
796 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
797 SC16IS7XX_EFR_AUTORTS_BIT;
798 if (termios->c_iflag & IXON)
799 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
800 if (termios->c_iflag & IXOFF)
801 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
802
803 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow);
804 regcache_cache_bypass(s->regmap, false);
805
806 /* Update LCR register */
807 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
808
809 /* Get baud rate generator configuration */
810 baud = uart_get_baud_rate(port, termios, old,
811 port->uartclk / 16 / 4 / 0xffff,
812 port->uartclk / 16);
813
814 /* Setup baudrate generator */
815 baud = sc16is7xx_set_baud(port, baud);
816
817 /* Update timeout according to new baud rate */
818 uart_update_timeout(port, termios->c_cflag, baud);
819}
820
b57d15fe 821static int sc16is7xx_config_rs485(struct uart_port *port,
f0e38115 822 struct serial_rs485 *rs485)
dfeae619 823{
f0e38115
JK		 824 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
825 SC16IS7XX_EFCR_RTS_INVERT_BIT;
826 u32 efcr = 0;
827
828 if (rs485->flags & SER_RS485_ENABLED) {
829 bool rts_during_rx, rts_during_tx;
830
831 rts_during_rx = rs485->flags & SER_RS485_RTS_AFTER_SEND;
832 rts_during_tx = rs485->flags & SER_RS485_RTS_ON_SEND;
833
834 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT;
835
836 if (!rts_during_rx && rts_during_tx)
837 /* default */;
838 else if (rts_during_rx && !rts_during_tx)
839 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
840 else
841 dev_err(port->dev,
842 "unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be set\n",
843 rts_during_tx, rts_during_rx);
5451bb29
JK		 844
845 /*
846 * RTS signal is handled by HW, it's timing can't be influenced.
847 * However, it's sometimes useful to delay TX even without RTS
848 * control therefore we try to handle .delay_rts_before_send.
849 */
850 if (rs485->delay_rts_after_send)
851 return -EINVAL;
f0e38115
JK		 852 }
853
854 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
855
b57d15fe 856 port->rs485 = *rs485;
dfeae619 857
b57d15fe 858 return 0;
dfeae619
JR		 859}
860
861static int sc16is7xx_startup(struct uart_port *port)
862{
863 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
864 unsigned int val;
865
866 sc16is7xx_power(port, 1);
867
868 /* Reset FIFOs*/
869 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
870 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
871 udelay(5);
872 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
873 SC16IS7XX_FCR_FIFO_BIT);
874
875 /* Enable EFR */
876 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
877 SC16IS7XX_LCR_CONF_MODE_B);
878
879 regcache_cache_bypass(s->regmap, true);
880
881 /* Enable write access to enhanced features and internal clock div */
882 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
883 SC16IS7XX_EFR_ENABLE_BIT);
884
885 /* Enable TCR/TLR */
886 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
887 SC16IS7XX_MCR_TCRTLR_BIT,
888 SC16IS7XX_MCR_TCRTLR_BIT);
889
890 /* Configure flow control levels */
891 /* Flow control halt level 48, resume level 24 */
892 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
893 SC16IS7XX_TCR_RX_RESUME(24) |
894 SC16IS7XX_TCR_RX_HALT(48));
895
896 regcache_cache_bypass(s->regmap, false);
897
898 /* Now, initialize the UART */
899 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
900
901 /* Enable the Rx and Tx FIFO */
902 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
903 SC16IS7XX_EFCR_RXDISABLE_BIT |
904 SC16IS7XX_EFCR_TXDISABLE_BIT,
905 0);
906
907 /* Enable RX, TX, CTS change interrupts */
908 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_THRI_BIT |
909 SC16IS7XX_IER_CTSI_BIT;
910 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
911
912 return 0;
913}
914
915static void sc16is7xx_shutdown(struct uart_port *port)
916{
9e6f4ca3
JK		 917 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
918
dfeae619
JR		 919 /* Disable all interrupts */
920 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
921 /* Disable TX/RX */
9764e7a0
JK		 922 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
923 SC16IS7XX_EFCR_RXDISABLE_BIT |
924 SC16IS7XX_EFCR_TXDISABLE_BIT,
925 SC16IS7XX_EFCR_RXDISABLE_BIT |
926 SC16IS7XX_EFCR_TXDISABLE_BIT);
dfeae619
JR		 927
928 sc16is7xx_power(port, 0);
9e6f4ca3
JK		 929
930 flush_kthread_worker(&s->kworker);
dfeae619
JR		 931}
932
933static const char *sc16is7xx_type(struct uart_port *port)
934{
935 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
936
937 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
938}
939
940static int sc16is7xx_request_port(struct uart_port *port)
941{
942 /* Do nothing */
943 return 0;
944}
945
946static void sc16is7xx_config_port(struct uart_port *port, int flags)
947{
948 if (flags & UART_CONFIG_TYPE)
949 port->type = PORT_SC16IS7XX;
950}
951
952static int sc16is7xx_verify_port(struct uart_port *port,
953 struct serial_struct *s)
954{
955 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
956 return -EINVAL;
957 if (s->irq != port->irq)
958 return -EINVAL;
959
960 return 0;
961}
962
963static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
964 unsigned int oldstate)
965{
966 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
967}
968
969static void sc16is7xx_null_void(struct uart_port *port)
970{
971 /* Do nothing */
972}
973
974static const struct uart_ops sc16is7xx_ops = {
975 .tx_empty = sc16is7xx_tx_empty,
976 .set_mctrl = sc16is7xx_set_mctrl,
977 .get_mctrl = sc16is7xx_get_mctrl,
978 .stop_tx = sc16is7xx_stop_tx,
979 .start_tx = sc16is7xx_start_tx,
980 .stop_rx = sc16is7xx_stop_rx,
dfeae619
JR		 981 .break_ctl = sc16is7xx_break_ctl,
982 .startup = sc16is7xx_startup,
983 .shutdown = sc16is7xx_shutdown,
984 .set_termios = sc16is7xx_set_termios,
985 .type = sc16is7xx_type,
986 .request_port = sc16is7xx_request_port,
987 .release_port = sc16is7xx_null_void,
988 .config_port = sc16is7xx_config_port,
989 .verify_port = sc16is7xx_verify_port,
dfeae619
JR		 990 .pm = sc16is7xx_pm,
991};
992
993#ifdef CONFIG_GPIOLIB
994static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
995{
996 unsigned int val;
997 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
998 gpio);
999 struct uart_port *port = &s->p[0].port;
1000
1001 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1002
1003 return !!(val & BIT(offset));
1004}
1005
1006static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
1007{
1008 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1009 gpio);
1010 struct uart_port *port = &s->p[0].port;
1011
1012 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1013 val ? BIT(offset) : 0);
1014}
1015
1016static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1017 unsigned offset)
1018{
1019 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1020 gpio);
1021 struct uart_port *port = &s->p[0].port;
1022
1023 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1024
1025 return 0;
1026}
1027
1028static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1029 unsigned offset, int val)
1030{
1031 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1032 gpio);
1033 struct uart_port *port = &s->p[0].port;
1034
1035 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1036 val ? BIT(offset) : 0);
1037 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1038 BIT(offset));
1039
1040 return 0;
1041}
1042#endif
1043
1044static int sc16is7xx_probe(struct device *dev,
1045 struct sc16is7xx_devtype *devtype,
1046 struct regmap *regmap, int irq, unsigned long flags)
1047{
9e6f4ca3 1048 struct sched_param sched_param = { .sched_priority = MAX_RT_PRIO / 2 };
dfeae619 1049 unsigned long freq, *pfreq = dev_get_platdata(dev);
dfeae619
JR		 1050 int i, ret;
1051 struct sc16is7xx_port *s;
1052
1053 if (IS_ERR(regmap))
1054 return PTR_ERR(regmap);
1055
1056 /* Alloc port structure */
1057 s = devm_kzalloc(dev, sizeof(*s) +
1058 sizeof(struct sc16is7xx_one) * devtype->nr_uart,
1059 GFP_KERNEL);
1060 if (!s) {
1061 dev_err(dev, "Error allocating port structure\n");
1062 return -ENOMEM;
1063 }
1064
dc824ebe
JR		 1065 s->clk = devm_clk_get(dev, NULL);
1066 if (IS_ERR(s->clk)) {
dfeae619
JR		 1067 if (pfreq)
1068 freq = *pfreq;
1069 else
dc824ebe 1070 return PTR_ERR(s->clk);
dfeae619 1071 } else {
0814e8d5 1072 clk_prepare_enable(s->clk);
dc824ebe 1073 freq = clk_get_rate(s->clk);
dfeae619
JR		 1074 }
1075
1076 s->regmap = regmap;
1077 s->devtype = devtype;
1078 dev_set_drvdata(dev, s);
1079
1080 /* Register UART driver */
1081 s->uart.owner = THIS_MODULE;
1082 s->uart.dev_name = "ttySC";
1083 s->uart.nr = devtype->nr_uart;
1084 ret = uart_register_driver(&s->uart);
1085 if (ret) {
1086 dev_err(dev, "Registering UART driver failed\n");
1087 goto out_clk;
1088 }
1089
9e6f4ca3
JK		 1090 init_kthread_worker(&s->kworker);
1091 init_kthread_work(&s->irq_work, sc16is7xx_ist);
1092 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,
1093 "sc16is7xx");
1094 if (IS_ERR(s->kworker_task)) {
1095 ret = PTR_ERR(s->kworker_task);
1096 goto out_uart;
1097 }
1098 sched_setscheduler(s->kworker_task, SCHED_FIFO, &sched_param);
1099
dfeae619
JR		 1100#ifdef CONFIG_GPIOLIB
1101 if (devtype->nr_gpio) {
1102 /* Setup GPIO cotroller */
1103 s->gpio.owner = THIS_MODULE;
1104 s->gpio.dev = dev;
1105 s->gpio.label = dev_name(dev);
1106 s->gpio.direction_input = sc16is7xx_gpio_direction_input;
1107 s->gpio.get = sc16is7xx_gpio_get;
1108 s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1109 s->gpio.set = sc16is7xx_gpio_set;
1110 s->gpio.base = -1;
1111 s->gpio.ngpio = devtype->nr_gpio;
1112 s->gpio.can_sleep = 1;
1113 ret = gpiochip_add(&s->gpio);
1114 if (ret)
9e6f4ca3 1115 goto out_thread;
dfeae619
JR		 1116 }
1117#endif
1118
dfeae619
JR		 1119 for (i = 0; i < devtype->nr_uart; ++i) {
1120 /* Initialize port data */
1121 s->p[i].port.line = i;
1122 s->p[i].port.dev = dev;
1123 s->p[i].port.irq = irq;
1124 s->p[i].port.type = PORT_SC16IS7XX;
1125 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE;
1126 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1127 s->p[i].port.iotype = UPIO_PORT;
1128 s->p[i].port.uartclk = freq;
b57d15fe 1129 s->p[i].port.rs485_config = sc16is7xx_config_rs485;
dfeae619
JR		 1130 s->p[i].port.ops = &sc16is7xx_ops;
1131 /* Disable all interrupts */
1132 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1133 /* Disable TX/RX */
1134 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1135 SC16IS7XX_EFCR_RXDISABLE_BIT |
1136 SC16IS7XX_EFCR_TXDISABLE_BIT);
1137 /* Initialize queue for start TX */
9e6f4ca3 1138 init_kthread_work(&s->p[i].tx_work, sc16is7xx_tx_proc);
dfeae619
JR		 1139 /* Initialize queue for changing mode */
1140 INIT_WORK(&s->p[i].md_work, sc16is7xx_md_proc);
1141 /* Register port */
1142 uart_add_one_port(&s->uart, &s->p[i].port);
1143 /* Go to suspend mode */
1144 sc16is7xx_power(&s->p[i].port, 0);
1145 }
1146
1147 /* Setup interrupt */
9e6f4ca3
JK		 1148 ret = devm_request_irq(dev, irq, sc16is7xx_irq,
1149 IRQF_ONESHOT | flags, dev_name(dev), s);
dfeae619
JR		 1150 if (!ret)
1151 return 0;
1152
11b03ea0
JK		 1153 for (i = 0; i < s->uart.nr; i++)
1154 uart_remove_one_port(&s->uart, &s->p[i].port);
1155
dfeae619
JR		 1156#ifdef CONFIG_GPIOLIB
1157 if (devtype->nr_gpio)
e27e2786 1158 gpiochip_remove(&s->gpio);
dfeae619 1159
9e6f4ca3 1160out_thread:
dfeae619 1161#endif
9e6f4ca3
JK		 1162 kthread_stop(s->kworker_task);
1163
1164out_uart:
dfeae619
JR		 1165 uart_unregister_driver(&s->uart);
1166
1167out_clk:
1168 if (!IS_ERR(s->clk))
1169 clk_disable_unprepare(s->clk);
1170
1171 return ret;
1172}
1173
1174static int sc16is7xx_remove(struct device *dev)
1175{
1176 struct sc16is7xx_port *s = dev_get_drvdata(dev);
e27e2786 1177 int i;
dfeae619
JR		 1178
1179#ifdef CONFIG_GPIOLIB
e27e2786
LW		 1180 if (s->devtype->nr_gpio)
1181 gpiochip_remove(&s->gpio);
dfeae619
JR		 1182#endif
1183
1184 for (i = 0; i < s->uart.nr; i++) {
dfeae619
JR		 1185 cancel_work_sync(&s->p[i].md_work);
1186 uart_remove_one_port(&s->uart, &s->p[i].port);
1187 sc16is7xx_power(&s->p[i].port, 0);
1188 }
1189
9e6f4ca3
JK		 1190 flush_kthread_worker(&s->kworker);
1191 kthread_stop(s->kworker_task);
1192
dfeae619
JR		 1193 uart_unregister_driver(&s->uart);
1194 if (!IS_ERR(s->clk))
1195 clk_disable_unprepare(s->clk);
1196
e27e2786 1197 return 0;
dfeae619
JR		 1198}
1199
1200static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1201 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },
1202 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },
1203 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },
1204 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },
1205 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },
1206 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },
1207 { }
1208};
1209MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1210
1211static struct regmap_config regcfg = {
1212 .reg_bits = 7,
1213 .pad_bits = 1,
1214 .val_bits = 8,
1215 .cache_type = REGCACHE_RBTREE,
1216 .volatile_reg = sc16is7xx_regmap_volatile,
1217 .precious_reg = sc16is7xx_regmap_precious,
1218};
1219
2c837a8a
RKKI		 1220#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1221static int sc16is7xx_spi_probe(struct spi_device *spi)
1222{
1223 struct sc16is7xx_devtype *devtype;
1224 unsigned long flags = 0;
1225 struct regmap *regmap;
1226 int ret;
1227
1228 /* Setup SPI bus */
1229 spi->bits_per_word = 8;
1230 /* only supports mode 0 on SC16IS762 */
1231 spi->mode = spi->mode ? : SPI_MODE_0;
1232 spi->max_speed_hz = spi->max_speed_hz ? : 15000000;
1233 ret = spi_setup(spi);
1234 if (ret)
1235 return ret;
1236
1237 if (spi->dev.of_node) {
1238 const struct of_device_id *of_id =
1239 of_match_device(sc16is7xx_dt_ids, &spi->dev);
1240
1241 devtype = (struct sc16is7xx_devtype *)of_id->data;
1242 } else {
1243 const struct spi_device_id *id_entry = spi_get_device_id(spi);
1244
1245 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data;
1246 flags = IRQF_TRIGGER_FALLING;
1247 }
1248
1249 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1250 (devtype->nr_uart - 1);
1251 regmap = devm_regmap_init_spi(spi, &regcfg);
1252
1253 return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq, flags);
1254}
1255
1256static int sc16is7xx_spi_remove(struct spi_device *spi)
1257{
1258 return sc16is7xx_remove(&spi->dev);
1259}
1260
1261static const struct spi_device_id sc16is7xx_spi_id_table[] = {
1262 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
4117a60c
JK		 1263 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1264 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
2c837a8a
RKKI		 1265 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1266 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1267 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1268 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1269 { }
1270};
1271
1272MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table);
1273
1274static struct spi_driver sc16is7xx_spi_uart_driver = {
1275 .driver = {
1276 .name = SC16IS7XX_NAME,
1277 .owner = THIS_MODULE,
1278 .of_match_table = of_match_ptr(sc16is7xx_dt_ids),
1279 },
1280 .probe = sc16is7xx_spi_probe,
1281 .remove = sc16is7xx_spi_remove,
1282 .id_table = sc16is7xx_spi_id_table,
1283};
1284
1285MODULE_ALIAS("spi:sc16is7xx");
1286#endif
1287
1288#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
dfeae619
JR		 1289static int sc16is7xx_i2c_probe(struct i2c_client *i2c,
1290 const struct i2c_device_id *id)
1291{
1292 struct sc16is7xx_devtype *devtype;
1293 unsigned long flags = 0;
1294 struct regmap *regmap;
1295
1296 if (i2c->dev.of_node) {
1297 const struct of_device_id *of_id =
1298 of_match_device(sc16is7xx_dt_ids, &i2c->dev);
1299
1300 devtype = (struct sc16is7xx_devtype *)of_id->data;
1301 } else {
1302 devtype = (struct sc16is7xx_devtype *)id->driver_data;
1303 flags = IRQF_TRIGGER_FALLING;
1304 }
1305
1306 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1307 (devtype->nr_uart - 1);
1308 regmap = devm_regmap_init_i2c(i2c, &regcfg);
1309
1310 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq, flags);
1311}
1312
1313static int sc16is7xx_i2c_remove(struct i2c_client *client)
1314{
1315 return sc16is7xx_remove(&client->dev);
1316}
1317
1318static const struct i2c_device_id sc16is7xx_i2c_id_table[] = {
1319 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
4117a60c
JK		 1320 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1321 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
dfeae619
JR		 1322 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1323 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1324 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1325 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1326 { }
1327};
1328MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table);
1329
1330static struct i2c_driver sc16is7xx_i2c_uart_driver = {
1331 .driver = {
1332 .name = SC16IS7XX_NAME,
1333 .owner = THIS_MODULE,
1334 .of_match_table = of_match_ptr(sc16is7xx_dt_ids),
1335 },
1336 .probe = sc16is7xx_i2c_probe,
1337 .remove = sc16is7xx_i2c_remove,
1338 .id_table = sc16is7xx_i2c_id_table,
1339};
2c837a8a 1340
dfeae619 1341MODULE_ALIAS("i2c:sc16is7xx");
2c837a8a
RKKI		 1342#endif
1343
1344static int __init sc16is7xx_init(void)
1345{
1346 int ret = 0;
1347#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1348 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver);
1349 if (ret < 0) {
1350 pr_err("failed to init sc16is7xx i2c --> %d\n", ret);
1351 return ret;
1352 }
1353#endif
1354
1355#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1356 ret = spi_register_driver(&sc16is7xx_spi_uart_driver);
1357 if (ret < 0) {
1358 pr_err("failed to init sc16is7xx spi --> %d\n", ret);
1359 return ret;
1360 }
1361#endif
1362 return ret;
1363}
1364module_init(sc16is7xx_init);
1365
1366static void __exit sc16is7xx_exit(void)
1367{
1368#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1369 i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1370#endif
1371
1372#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1373 spi_unregister_driver(&sc16is7xx_spi_uart_driver);
1374#endif
1375}
1376module_exit(sc16is7xx_exit);
dfeae619
JR		 1377
1378MODULE_LICENSE("GPL");
1379MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1380MODULE_DESCRIPTION("SC16IS7XX serial driver");
Linux kernel - Deliverables
This page took 0.151063 seconds and 5 git commands to generate.