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sc16is7xx: use kworker for md_proc
[deliverable/linux.git] / drivers / tty / serial / sc16is7xx.c
CommitLineData
dfeae619
JR		 1/*
2 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
3 * Author: Jon Ringle <jringle@gridpoint.com>
4 *
5 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13
14#include <linux/bitops.h>
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/device.h>
18#include <linux/gpio.h>
19#include <linux/i2c.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/regmap.h>
24#include <linux/serial_core.h>
25#include <linux/serial.h>
26#include <linux/tty.h>
27#include <linux/tty_flip.h>
2c837a8a 28#include <linux/spi/spi.h>
d952795d 29#include <linux/uaccess.h>
dfeae619
JR		 30
31#define SC16IS7XX_NAME "sc16is7xx"
32
33/* SC16IS7XX register definitions */
34#define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
35#define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
36#define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
37#define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
38#define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
39#define SC16IS7XX_LCR_REG (0x03) /* Line Control */
40#define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
41#define SC16IS7XX_LSR_REG (0x05) /* Line Status */
42#define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
43#define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
44#define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
45#define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
46#define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
47 * - only on 75x/76x
48 */
49#define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
50 * - only on 75x/76x
51 */
52#define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
53 * - only on 75x/76x
54 */
55#define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
56 * - only on 75x/76x
57 */
58#define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
59
60/* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
61#define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
62#define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
63
64/* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
65#define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
66#define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
67
68/* Enhanced Register set: Only if (LCR == 0xBF) */
69#define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
70#define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
71#define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
72#define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
73#define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
74
75/* IER register bits */
76#define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */
77#define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register
78 * interrupt */
79#define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status
80 * interrupt */
81#define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status
82 * interrupt */
83
84/* IER register bits - write only if (EFR[4] == 1) */
85#define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */
86#define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */
87#define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */
88#define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */
89
90/* FCR register bits */
91#define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */
92#define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */
93#define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */
94#define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */
95#define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */
96
97/* FCR register bits - write only if (EFR[4] == 1) */
98#define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */
99#define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */
100
101/* IIR register bits */
102#define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */
103#define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */
104#define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
105#define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
106#define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
107#define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
108#define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
109 * - only on 75x/76x
110 */
111#define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
112 * - only on 75x/76x
113 */
114#define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
115#define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
116 * from active (LOW)
117 * to inactive (HIGH)
118 */
119/* LCR register bits */
120#define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
121#define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
122 *
123 * Word length bits table:
124 * 00 -> 5 bit words
125 * 01 -> 6 bit words
126 * 10 -> 7 bit words
127 * 11 -> 8 bit words
128 */
129#define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
130 *
131 * STOP length bit table:
132 * 0 -> 1 stop bit
133 * 1 -> 1-1.5 stop bits if
134 * word length is 5,
135 * 2 stop bits otherwise
136 */
137#define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
138#define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
139#define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
140#define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
141#define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */
142#define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
143#define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
144#define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
145#define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
146#define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special
147 * reg set */
148#define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced
149 * reg set */
150
151/* MCR register bits */
152#define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement
153 * - only on 75x/76x
154 */
155#define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */
156#define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */
157#define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */
158#define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any
159 * - write enabled
160 * if (EFR[4] == 1)
161 */
162#define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode
163 * - write enabled
164 * if (EFR[4] == 1)
165 */
166#define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4
167 * - write enabled
168 * if (EFR[4] == 1)
169 */
170
171/* LSR register bits */
172#define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */
173#define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */
174#define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */
175#define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */
176#define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */
177#define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */
178#define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */
179#define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */
180#define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */
181
182/* MSR register bits */
183#define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */
184#define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready
185 * or (IO4)
186 * - only on 75x/76x
187 */
188#define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator
189 * or (IO7)
190 * - only on 75x/76x
191 */
192#define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect
193 * or (IO6)
194 * - only on 75x/76x
195 */
196#define SC16IS7XX_MSR_CTS_BIT (1 << 0) /* CTS */
197#define SC16IS7XX_MSR_DSR_BIT (1 << 1) /* DSR (IO4)
198 * - only on 75x/76x
199 */
200#define SC16IS7XX_MSR_RI_BIT (1 << 2) /* RI (IO7)
201 * - only on 75x/76x
202 */
203#define SC16IS7XX_MSR_CD_BIT (1 << 3) /* CD (IO6)
204 * - only on 75x/76x
205 */
206#define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */
207
208/*
209 * TCR register bits
210 * TCR trigger levels are available from 0 to 60 characters with a granularity
211 * of four.
212 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
213 * no built-in hardware check to make sure this condition is met. Also, the TCR
214 * must be programmed with this condition before auto RTS or software flow
215 * control is enabled to avoid spurious operation of the device.
216 */
217#define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
218#define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
219
220/*
221 * TLR register bits
222 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
223 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
224 * trigger levels. Trigger levels from 4 characters to 60 characters are
225 * available with a granularity of four.
226 *
227 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
228 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
229 * the trigger level defined in FCR is discarded. This applies to both transmit
230 * FIFO and receive FIFO trigger level setting.
231 *
232 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
233 * default state, that is, '00'.
234 */
235#define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
236#define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
237
238/* IOControl register bits (Only 750/760) */
239#define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */
240#define SC16IS7XX_IOCONTROL_GPIO_BIT (1 << 1) /* Enable GPIO[7:4] */
241#define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */
242
243/* EFCR register bits */
244#define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop
245 * mode (RS485) */
246#define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */
247#define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */
248#define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */
249#define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */
250#define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode
251 * 0 = rate upto 115.2 kbit/s
252 * - Only 750/760
253 * 1 = rate upto 1.152 Mbit/s
254 * - Only 760
255 */
256
257/* EFR register bits */
258#define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */
259#define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */
260#define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */
261#define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions
262 * and writing to IER[7:4],
263 * FCR[5:4], MCR[7:5]
264 */
265#define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */
266#define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2
267 *
268 * SWFLOW bits 3 & 2 table:
269 * 00 -> no transmitter flow
270 * control
271 * 01 -> transmitter generates
272 * XON2 and XOFF2
273 * 10 -> transmitter generates
274 * XON1 and XOFF1
275 * 11 -> transmitter generates
276 * XON1, XON2, XOFF1 and
277 * XOFF2
278 */
279#define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */
280#define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3
281 *
282 * SWFLOW bits 3 & 2 table:
283 * 00 -> no received flow
284 * control
285 * 01 -> receiver compares
286 * XON2 and XOFF2
287 * 10 -> receiver compares
288 * XON1 and XOFF1
289 * 11 -> receiver compares
290 * XON1, XON2, XOFF1 and
291 * XOFF2
292 */
293
294/* Misc definitions */
295#define SC16IS7XX_FIFO_SIZE (64)
296#define SC16IS7XX_REG_SHIFT 2
297
298struct sc16is7xx_devtype {
299 char name[10];
300 int nr_gpio;
301 int nr_uart;
302};
303
a0104085
JK		 304#define SC16IS7XX_RECONF_MD (1 << 0)
305
306struct sc16is7xx_one_config {
307 unsigned int flags;
308};
309
dfeae619
JR		 310struct sc16is7xx_one {
311 struct uart_port port;
9e6f4ca3 312 struct kthread_work tx_work;
a0104085
JK		 313 struct kthread_work reg_work;
314 struct sc16is7xx_one_config config;
dfeae619
JR		 315};
316
317struct sc16is7xx_port {
318 struct uart_driver uart;
319 struct sc16is7xx_devtype *devtype;
320 struct regmap *regmap;
dfeae619
JR		 321 struct clk *clk;
322#ifdef CONFIG_GPIOLIB
323 struct gpio_chip gpio;
324#endif
beb04a9f 325 unsigned char buf[SC16IS7XX_FIFO_SIZE];
9e6f4ca3
JK		 326 struct kthread_worker kworker;
327 struct task_struct *kworker_task;
328 struct kthread_work irq_work;
dfeae619
JR		 329 struct sc16is7xx_one p[0];
330};
331
9e6f4ca3 332#define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e)))
dfeae619
JR		 333#define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
334
335static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
336{
337 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
338 unsigned int val = 0;
339
340 regmap_read(s->regmap,
341 (reg << SC16IS7XX_REG_SHIFT) | port->line, &val);
342
343 return val;
344}
345
346static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
347{
348 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
349
350 regmap_write(s->regmap,
351 (reg << SC16IS7XX_REG_SHIFT) | port->line, val);
352}
353
354static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
355 u8 mask, u8 val)
356{
357 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
358
359 regmap_update_bits(s->regmap,
360 (reg << SC16IS7XX_REG_SHIFT) | port->line,
361 mask, val);
362}
363
364
365static void sc16is7xx_power(struct uart_port *port, int on)
366{
367 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
368 SC16IS7XX_IER_SLEEP_BIT,
369 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
370}
371
372static const struct sc16is7xx_devtype sc16is74x_devtype = {
373 .name = "SC16IS74X",
374 .nr_gpio = 0,
375 .nr_uart = 1,
376};
377
378static const struct sc16is7xx_devtype sc16is750_devtype = {
379 .name = "SC16IS750",
380 .nr_gpio = 8,
381 .nr_uart = 1,
382};
383
384static const struct sc16is7xx_devtype sc16is752_devtype = {
385 .name = "SC16IS752",
386 .nr_gpio = 8,
387 .nr_uart = 2,
388};
389
390static const struct sc16is7xx_devtype sc16is760_devtype = {
391 .name = "SC16IS760",
392 .nr_gpio = 8,
393 .nr_uart = 1,
394};
395
396static const struct sc16is7xx_devtype sc16is762_devtype = {
397 .name = "SC16IS762",
398 .nr_gpio = 8,
399 .nr_uart = 2,
400};
401
402static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
403{
404 switch (reg >> SC16IS7XX_REG_SHIFT) {
405 case SC16IS7XX_RHR_REG:
406 case SC16IS7XX_IIR_REG:
407 case SC16IS7XX_LSR_REG:
408 case SC16IS7XX_MSR_REG:
409 case SC16IS7XX_TXLVL_REG:
410 case SC16IS7XX_RXLVL_REG:
411 case SC16IS7XX_IOSTATE_REG:
412 return true;
413 default:
414 break;
415 }
416
417 return false;
418}
419
420static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
421{
422 switch (reg >> SC16IS7XX_REG_SHIFT) {
423 case SC16IS7XX_RHR_REG:
424 return true;
425 default:
426 break;
427 }
428
429 return false;
430}
431
432static int sc16is7xx_set_baud(struct uart_port *port, int baud)
433{
434 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
435 u8 lcr;
436 u8 prescaler = 0;
437 unsigned long clk = port->uartclk, div = clk / 16 / baud;
438
439 if (div > 0xffff) {
440 prescaler = SC16IS7XX_MCR_CLKSEL_BIT;
441 div /= 4;
442 }
443
444 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
445
446 /* Open the LCR divisors for configuration */
447 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
448 SC16IS7XX_LCR_CONF_MODE_B);
449
450 /* Enable enhanced features */
451 regcache_cache_bypass(s->regmap, true);
452 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
453 SC16IS7XX_EFR_ENABLE_BIT);
454 regcache_cache_bypass(s->regmap, false);
455
456 /* Put LCR back to the normal mode */
457 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
458
459 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
460 SC16IS7XX_MCR_CLKSEL_BIT,
461 prescaler);
462
463 /* Open the LCR divisors for configuration */
464 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
465 SC16IS7XX_LCR_CONF_MODE_A);
466
467 /* Write the new divisor */
468 regcache_cache_bypass(s->regmap, true);
469 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
470 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
471 regcache_cache_bypass(s->regmap, false);
472
473 /* Put LCR back to the normal mode */
474 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
475
476 return DIV_ROUND_CLOSEST(clk / 16, div);
477}
478
479static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
480 unsigned int iir)
481{
482 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
483 unsigned int lsr = 0, ch, flag, bytes_read, i;
dfeae619
JR		 484 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
485
beb04a9f 486 if (unlikely(rxlen >= sizeof(s->buf))) {
dfeae619
JR		 487 dev_warn_ratelimited(port->dev,
488 "Port %i: Possible RX FIFO overrun: %d\n",
489 port->line, rxlen);
490 port->icount.buf_overrun++;
491 /* Ensure sanity of RX level */
beb04a9f 492 rxlen = sizeof(s->buf);
dfeae619
JR		 493 }
494
495 while (rxlen) {
496 /* Only read lsr if there are possible errors in FIFO */
497 if (read_lsr) {
498 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
499 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
500 read_lsr = false; /* No errors left in FIFO */
501 } else
502 lsr = 0;
503
504 if (read_lsr) {
beb04a9f 505 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
dfeae619
JR		 506 bytes_read = 1;
507 } else {
508 regcache_cache_bypass(s->regmap, true);
509 regmap_raw_read(s->regmap, SC16IS7XX_RHR_REG,
beb04a9f 510 s->buf, rxlen);
dfeae619
JR		 511 regcache_cache_bypass(s->regmap, false);
512 bytes_read = rxlen;
513 }
514
515 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
516
517 port->icount.rx++;
518 flag = TTY_NORMAL;
519
520 if (unlikely(lsr)) {
521 if (lsr & SC16IS7XX_LSR_BI_BIT) {
522 port->icount.brk++;
523 if (uart_handle_break(port))
524 continue;
525 } else if (lsr & SC16IS7XX_LSR_PE_BIT)
526 port->icount.parity++;
527 else if (lsr & SC16IS7XX_LSR_FE_BIT)
528 port->icount.frame++;
529 else if (lsr & SC16IS7XX_LSR_OE_BIT)
530 port->icount.overrun++;
531
532 lsr &= port->read_status_mask;
533 if (lsr & SC16IS7XX_LSR_BI_BIT)
534 flag = TTY_BREAK;
535 else if (lsr & SC16IS7XX_LSR_PE_BIT)
536 flag = TTY_PARITY;
537 else if (lsr & SC16IS7XX_LSR_FE_BIT)
538 flag = TTY_FRAME;
539 else if (lsr & SC16IS7XX_LSR_OE_BIT)
540 flag = TTY_OVERRUN;
541 }
542
543 for (i = 0; i < bytes_read; ++i) {
beb04a9f 544 ch = s->buf[i];
dfeae619
JR		 545 if (uart_handle_sysrq_char(port, ch))
546 continue;
547
548 if (lsr & port->ignore_status_mask)
549 continue;
550
551 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
552 flag);
553 }
554 rxlen -= bytes_read;
555 }
556
557 tty_flip_buffer_push(&port->state->port);
558}
559
560static void sc16is7xx_handle_tx(struct uart_port *port)
561{
562 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
563 struct circ_buf *xmit = &port->state->xmit;
564 unsigned int txlen, to_send, i;
dfeae619
JR		 565
566 if (unlikely(port->x_char)) {
567 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
568 port->icount.tx++;
569 port->x_char = 0;
570 return;
571 }
572
573 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
574 return;
575
576 /* Get length of data pending in circular buffer */
577 to_send = uart_circ_chars_pending(xmit);
578 if (likely(to_send)) {
579 /* Limit to size of TX FIFO */
580 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
581 to_send = (to_send > txlen) ? txlen : to_send;
582
583 /* Add data to send */
584 port->icount.tx += to_send;
585
586 /* Convert to linear buffer */
587 for (i = 0; i < to_send; ++i) {
beb04a9f 588 s->buf[i] = xmit->buf[xmit->tail];
dfeae619
JR		 589 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
590 }
591 regcache_cache_bypass(s->regmap, true);
beb04a9f 592 regmap_raw_write(s->regmap, SC16IS7XX_THR_REG, s->buf, to_send);
dfeae619
JR		 593 regcache_cache_bypass(s->regmap, false);
594 }
595
596 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
597 uart_write_wakeup(port);
598}
599
600static void sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
601{
602 struct uart_port *port = &s->p[portno].port;
603
604 do {
605 unsigned int iir, msr, rxlen;
606
607 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
608 if (iir & SC16IS7XX_IIR_NO_INT_BIT)
609 break;
610
611 iir &= SC16IS7XX_IIR_ID_MASK;
612
613 switch (iir) {
614 case SC16IS7XX_IIR_RDI_SRC:
615 case SC16IS7XX_IIR_RLSE_SRC:
616 case SC16IS7XX_IIR_RTOI_SRC:
617 case SC16IS7XX_IIR_XOFFI_SRC:
618 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
619 if (rxlen)
620 sc16is7xx_handle_rx(port, rxlen, iir);
621 break;
622
623 case SC16IS7XX_IIR_CTSRTS_SRC:
624 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG);
625 uart_handle_cts_change(port,
626 !!(msr & SC16IS7XX_MSR_CTS_BIT));
627 break;
628 case SC16IS7XX_IIR_THRI_SRC:
dfeae619 629 sc16is7xx_handle_tx(port);
dfeae619
JR		 630 break;
631 default:
632 dev_err_ratelimited(port->dev,
633 "Port %i: Unexpected interrupt: %x",
634 port->line, iir);
635 break;
636 }
637 } while (1);
638}
639
9e6f4ca3 640static void sc16is7xx_ist(struct kthread_work *ws)
dfeae619 641{
9e6f4ca3 642 struct sc16is7xx_port *s = to_sc16is7xx_port(ws, irq_work);
dfeae619
JR		 643 int i;
644
645 for (i = 0; i < s->uart.nr; ++i)
646 sc16is7xx_port_irq(s, i);
9e6f4ca3
JK		 647}
648
649static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
650{
651 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
652
653 queue_kthread_work(&s->kworker, &s->irq_work);
dfeae619
JR		 654
655 return IRQ_HANDLED;
656}
657
9e6f4ca3 658static void sc16is7xx_tx_proc(struct kthread_work *ws)
dfeae619 659{
dbe5a40c 660 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port);
dfeae619 661
dbe5a40c
JK		 662 if ((port->rs485.flags & SER_RS485_ENABLED) &&
663 (port->rs485.delay_rts_before_send > 0))
664 msleep(port->rs485.delay_rts_before_send);
665
666 sc16is7xx_handle_tx(port);
dfeae619
JR		 667}
668
a0104085
JK		 669static void sc16is7xx_reg_proc(struct kthread_work *ws)
670{
671 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work);
672 struct sc16is7xx_one_config config;
673 unsigned long irqflags;
674
675 spin_lock_irqsave(&one->port.lock, irqflags);
676 config = one->config;
677 memset(&one->config, 0, sizeof(one->config));
678 spin_unlock_irqrestore(&one->port.lock, irqflags);
679
680 if (config.flags & SC16IS7XX_RECONF_MD)
681 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
682 SC16IS7XX_MCR_LOOP_BIT,
683 (one->port.mctrl & TIOCM_LOOP) ?
684 SC16IS7XX_MCR_LOOP_BIT : 0);
685}
686
dfeae619
JR		 687static void sc16is7xx_stop_tx(struct uart_port* port)
688{
dfeae619
JR		 689 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
690 SC16IS7XX_IER_THRI_BIT,
691 0);
692}
693
694static void sc16is7xx_stop_rx(struct uart_port* port)
695{
696 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
697
698 one->port.read_status_mask &= ~SC16IS7XX_LSR_DR_BIT;
699 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
700 SC16IS7XX_LSR_DR_BIT,
701 0);
702}
703
704static void sc16is7xx_start_tx(struct uart_port *port)
705{
9e6f4ca3 706 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
dfeae619
JR		 707 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
708
9e6f4ca3 709 queue_kthread_work(&s->kworker, &one->tx_work);
dfeae619
JR		 710}
711
712static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
713{
4ae82e5d 714 unsigned int lsr;
dfeae619 715
dfeae619
JR		 716 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
717
4ae82e5d 718 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;
dfeae619
JR		 719}
720
721static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
722{
723 /* DCD and DSR are not wired and CTS/RTS is handled automatically
724 * so just indicate DSR and CAR asserted
725 */
726 return TIOCM_DSR | TIOCM_CAR;
727}
728
dfeae619
JR		 729static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
730{
a0104085 731 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
dfeae619
JR		 732 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
733
a0104085
JK		 734 one->config.flags |= SC16IS7XX_RECONF_MD;
735 queue_kthread_work(&s->kworker, &one->reg_work);
dfeae619
JR		 736}
737
738static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
739{
740 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
741 SC16IS7XX_LCR_TXBREAK_BIT,
742 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
743}
744
745static void sc16is7xx_set_termios(struct uart_port *port,
746 struct ktermios *termios,
747 struct ktermios *old)
748{
749 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
750 unsigned int lcr, flow = 0;
751 int baud;
752
753 /* Mask termios capabilities we don't support */
754 termios->c_cflag &= ~CMSPAR;
755
756 /* Word size */
757 switch (termios->c_cflag & CSIZE) {
758 case CS5:
759 lcr = SC16IS7XX_LCR_WORD_LEN_5;
760 break;
761 case CS6:
762 lcr = SC16IS7XX_LCR_WORD_LEN_6;
763 break;
764 case CS7:
765 lcr = SC16IS7XX_LCR_WORD_LEN_7;
766 break;
767 case CS8:
768 lcr = SC16IS7XX_LCR_WORD_LEN_8;
769 break;
770 default:
771 lcr = SC16IS7XX_LCR_WORD_LEN_8;
772 termios->c_cflag &= ~CSIZE;
773 termios->c_cflag |= CS8;
774 break;
775 }
776
777 /* Parity */
778 if (termios->c_cflag & PARENB) {
779 lcr |= SC16IS7XX_LCR_PARITY_BIT;
780 if (!(termios->c_cflag & PARODD))
781 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
782 }
783
784 /* Stop bits */
785 if (termios->c_cflag & CSTOPB)
786 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
787
788 /* Set read status mask */
789 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
790 if (termios->c_iflag & INPCK)
791 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
792 SC16IS7XX_LSR_FE_BIT;
793 if (termios->c_iflag & (BRKINT | PARMRK))
794 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
795
796 /* Set status ignore mask */
797 port->ignore_status_mask = 0;
798 if (termios->c_iflag & IGNBRK)
799 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
800 if (!(termios->c_cflag & CREAD))
801 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
802
803 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
804 SC16IS7XX_LCR_CONF_MODE_B);
805
806 /* Configure flow control */
807 regcache_cache_bypass(s->regmap, true);
808 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
809 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
810 if (termios->c_cflag & CRTSCTS)
811 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
812 SC16IS7XX_EFR_AUTORTS_BIT;
813 if (termios->c_iflag & IXON)
814 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
815 if (termios->c_iflag & IXOFF)
816 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
817
818 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow);
819 regcache_cache_bypass(s->regmap, false);
820
821 /* Update LCR register */
822 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
823
824 /* Get baud rate generator configuration */
825 baud = uart_get_baud_rate(port, termios, old,
826 port->uartclk / 16 / 4 / 0xffff,
827 port->uartclk / 16);
828
829 /* Setup baudrate generator */
830 baud = sc16is7xx_set_baud(port, baud);
831
832 /* Update timeout according to new baud rate */
833 uart_update_timeout(port, termios->c_cflag, baud);
834}
835
b57d15fe 836static int sc16is7xx_config_rs485(struct uart_port *port,
f0e38115 837 struct serial_rs485 *rs485)
dfeae619 838{
f0e38115
JK		 839 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
840 SC16IS7XX_EFCR_RTS_INVERT_BIT;
841 u32 efcr = 0;
842
843 if (rs485->flags & SER_RS485_ENABLED) {
844 bool rts_during_rx, rts_during_tx;
845
846 rts_during_rx = rs485->flags & SER_RS485_RTS_AFTER_SEND;
847 rts_during_tx = rs485->flags & SER_RS485_RTS_ON_SEND;
848
849 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT;
850
851 if (!rts_during_rx && rts_during_tx)
852 /* default */;
853 else if (rts_during_rx && !rts_during_tx)
854 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
855 else
856 dev_err(port->dev,
857 "unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be set\n",
858 rts_during_tx, rts_during_rx);
5451bb29
JK		 859
860 /*
861 * RTS signal is handled by HW, it's timing can't be influenced.
862 * However, it's sometimes useful to delay TX even without RTS
863 * control therefore we try to handle .delay_rts_before_send.
864 */
865 if (rs485->delay_rts_after_send)
866 return -EINVAL;
f0e38115
JK		 867 }
868
869 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
870
b57d15fe 871 port->rs485 = *rs485;
dfeae619 872
b57d15fe 873 return 0;
dfeae619
JR		 874}
875
876static int sc16is7xx_startup(struct uart_port *port)
877{
878 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
879 unsigned int val;
880
881 sc16is7xx_power(port, 1);
882
883 /* Reset FIFOs*/
884 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
885 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
886 udelay(5);
887 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
888 SC16IS7XX_FCR_FIFO_BIT);
889
890 /* Enable EFR */
891 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
892 SC16IS7XX_LCR_CONF_MODE_B);
893
894 regcache_cache_bypass(s->regmap, true);
895
896 /* Enable write access to enhanced features and internal clock div */
897 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
898 SC16IS7XX_EFR_ENABLE_BIT);
899
900 /* Enable TCR/TLR */
901 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
902 SC16IS7XX_MCR_TCRTLR_BIT,
903 SC16IS7XX_MCR_TCRTLR_BIT);
904
905 /* Configure flow control levels */
906 /* Flow control halt level 48, resume level 24 */
907 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
908 SC16IS7XX_TCR_RX_RESUME(24) |
909 SC16IS7XX_TCR_RX_HALT(48));
910
911 regcache_cache_bypass(s->regmap, false);
912
913 /* Now, initialize the UART */
914 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
915
916 /* Enable the Rx and Tx FIFO */
917 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
918 SC16IS7XX_EFCR_RXDISABLE_BIT |
919 SC16IS7XX_EFCR_TXDISABLE_BIT,
920 0);
921
922 /* Enable RX, TX, CTS change interrupts */
923 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_THRI_BIT |
924 SC16IS7XX_IER_CTSI_BIT;
925 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
926
927 return 0;
928}
929
930static void sc16is7xx_shutdown(struct uart_port *port)
931{
9e6f4ca3
JK		 932 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
933
dfeae619
JR		 934 /* Disable all interrupts */
935 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
936 /* Disable TX/RX */
9764e7a0
JK		 937 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
938 SC16IS7XX_EFCR_RXDISABLE_BIT |
939 SC16IS7XX_EFCR_TXDISABLE_BIT,
940 SC16IS7XX_EFCR_RXDISABLE_BIT |
941 SC16IS7XX_EFCR_TXDISABLE_BIT);
dfeae619
JR		 942
943 sc16is7xx_power(port, 0);
9e6f4ca3
JK		 944
945 flush_kthread_worker(&s->kworker);
dfeae619
JR		 946}
947
948static const char *sc16is7xx_type(struct uart_port *port)
949{
950 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
951
952 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
953}
954
955static int sc16is7xx_request_port(struct uart_port *port)
956{
957 /* Do nothing */
958 return 0;
959}
960
961static void sc16is7xx_config_port(struct uart_port *port, int flags)
962{
963 if (flags & UART_CONFIG_TYPE)
964 port->type = PORT_SC16IS7XX;
965}
966
967static int sc16is7xx_verify_port(struct uart_port *port,
968 struct serial_struct *s)
969{
970 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
971 return -EINVAL;
972 if (s->irq != port->irq)
973 return -EINVAL;
974
975 return 0;
976}
977
978static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
979 unsigned int oldstate)
980{
981 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
982}
983
984static void sc16is7xx_null_void(struct uart_port *port)
985{
986 /* Do nothing */
987}
988
989static const struct uart_ops sc16is7xx_ops = {
990 .tx_empty = sc16is7xx_tx_empty,
991 .set_mctrl = sc16is7xx_set_mctrl,
992 .get_mctrl = sc16is7xx_get_mctrl,
993 .stop_tx = sc16is7xx_stop_tx,
994 .start_tx = sc16is7xx_start_tx,
995 .stop_rx = sc16is7xx_stop_rx,
dfeae619
JR		 996 .break_ctl = sc16is7xx_break_ctl,
997 .startup = sc16is7xx_startup,
998 .shutdown = sc16is7xx_shutdown,
999 .set_termios = sc16is7xx_set_termios,
1000 .type = sc16is7xx_type,
1001 .request_port = sc16is7xx_request_port,
1002 .release_port = sc16is7xx_null_void,
1003 .config_port = sc16is7xx_config_port,
1004 .verify_port = sc16is7xx_verify_port,
dfeae619
JR		 1005 .pm = sc16is7xx_pm,
1006};
1007
1008#ifdef CONFIG_GPIOLIB
1009static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
1010{
1011 unsigned int val;
1012 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1013 gpio);
1014 struct uart_port *port = &s->p[0].port;
1015
1016 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1017
1018 return !!(val & BIT(offset));
1019}
1020
1021static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
1022{
1023 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1024 gpio);
1025 struct uart_port *port = &s->p[0].port;
1026
1027 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1028 val ? BIT(offset) : 0);
1029}
1030
1031static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1032 unsigned offset)
1033{
1034 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1035 gpio);
1036 struct uart_port *port = &s->p[0].port;
1037
1038 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1039
1040 return 0;
1041}
1042
1043static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1044 unsigned offset, int val)
1045{
1046 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1047 gpio);
1048 struct uart_port *port = &s->p[0].port;
1049
1050 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1051 val ? BIT(offset) : 0);
1052 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1053 BIT(offset));
1054
1055 return 0;
1056}
1057#endif
1058
1059static int sc16is7xx_probe(struct device *dev,
1060 struct sc16is7xx_devtype *devtype,
1061 struct regmap *regmap, int irq, unsigned long flags)
1062{
9e6f4ca3 1063 struct sched_param sched_param = { .sched_priority = MAX_RT_PRIO / 2 };
dfeae619 1064 unsigned long freq, *pfreq = dev_get_platdata(dev);
dfeae619
JR		 1065 int i, ret;
1066 struct sc16is7xx_port *s;
1067
1068 if (IS_ERR(regmap))
1069 return PTR_ERR(regmap);
1070
1071 /* Alloc port structure */
1072 s = devm_kzalloc(dev, sizeof(*s) +
1073 sizeof(struct sc16is7xx_one) * devtype->nr_uart,
1074 GFP_KERNEL);
1075 if (!s) {
1076 dev_err(dev, "Error allocating port structure\n");
1077 return -ENOMEM;
1078 }
1079
dc824ebe
JR		 1080 s->clk = devm_clk_get(dev, NULL);
1081 if (IS_ERR(s->clk)) {
dfeae619
JR		 1082 if (pfreq)
1083 freq = *pfreq;
1084 else
dc824ebe 1085 return PTR_ERR(s->clk);
dfeae619 1086 } else {
0814e8d5 1087 clk_prepare_enable(s->clk);
dc824ebe 1088 freq = clk_get_rate(s->clk);
dfeae619
JR		 1089 }
1090
1091 s->regmap = regmap;
1092 s->devtype = devtype;
1093 dev_set_drvdata(dev, s);
1094
1095 /* Register UART driver */
1096 s->uart.owner = THIS_MODULE;
1097 s->uart.dev_name = "ttySC";
1098 s->uart.nr = devtype->nr_uart;
1099 ret = uart_register_driver(&s->uart);
1100 if (ret) {
1101 dev_err(dev, "Registering UART driver failed\n");
1102 goto out_clk;
1103 }
1104
9e6f4ca3
JK		 1105 init_kthread_worker(&s->kworker);
1106 init_kthread_work(&s->irq_work, sc16is7xx_ist);
1107 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,
1108 "sc16is7xx");
1109 if (IS_ERR(s->kworker_task)) {
1110 ret = PTR_ERR(s->kworker_task);
1111 goto out_uart;
1112 }
1113 sched_setscheduler(s->kworker_task, SCHED_FIFO, &sched_param);
1114
dfeae619
JR		 1115#ifdef CONFIG_GPIOLIB
1116 if (devtype->nr_gpio) {
1117 /* Setup GPIO cotroller */
1118 s->gpio.owner = THIS_MODULE;
1119 s->gpio.dev = dev;
1120 s->gpio.label = dev_name(dev);
1121 s->gpio.direction_input = sc16is7xx_gpio_direction_input;
1122 s->gpio.get = sc16is7xx_gpio_get;
1123 s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1124 s->gpio.set = sc16is7xx_gpio_set;
1125 s->gpio.base = -1;
1126 s->gpio.ngpio = devtype->nr_gpio;
1127 s->gpio.can_sleep = 1;
1128 ret = gpiochip_add(&s->gpio);
1129 if (ret)
9e6f4ca3 1130 goto out_thread;
dfeae619
JR		 1131 }
1132#endif
1133
dfeae619
JR		 1134 for (i = 0; i < devtype->nr_uart; ++i) {
1135 /* Initialize port data */
1136 s->p[i].port.line = i;
1137 s->p[i].port.dev = dev;
1138 s->p[i].port.irq = irq;
1139 s->p[i].port.type = PORT_SC16IS7XX;
1140 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE;
1141 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1142 s->p[i].port.iotype = UPIO_PORT;
1143 s->p[i].port.uartclk = freq;
b57d15fe 1144 s->p[i].port.rs485_config = sc16is7xx_config_rs485;
dfeae619
JR		 1145 s->p[i].port.ops = &sc16is7xx_ops;
1146 /* Disable all interrupts */
1147 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1148 /* Disable TX/RX */
1149 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1150 SC16IS7XX_EFCR_RXDISABLE_BIT |
1151 SC16IS7XX_EFCR_TXDISABLE_BIT);
a0104085 1152 /* Initialize kthread work structs */
9e6f4ca3 1153 init_kthread_work(&s->p[i].tx_work, sc16is7xx_tx_proc);
a0104085 1154 init_kthread_work(&s->p[i].reg_work, sc16is7xx_reg_proc);
dfeae619
JR		 1155 /* Register port */
1156 uart_add_one_port(&s->uart, &s->p[i].port);
1157 /* Go to suspend mode */
1158 sc16is7xx_power(&s->p[i].port, 0);
1159 }
1160
1161 /* Setup interrupt */
9e6f4ca3
JK		 1162 ret = devm_request_irq(dev, irq, sc16is7xx_irq,
1163 IRQF_ONESHOT | flags, dev_name(dev), s);
dfeae619
JR		 1164 if (!ret)
1165 return 0;
1166
11b03ea0
JK		 1167 for (i = 0; i < s->uart.nr; i++)
1168 uart_remove_one_port(&s->uart, &s->p[i].port);
1169
dfeae619
JR		 1170#ifdef CONFIG_GPIOLIB
1171 if (devtype->nr_gpio)
e27e2786 1172 gpiochip_remove(&s->gpio);
dfeae619 1173
9e6f4ca3 1174out_thread:
dfeae619 1175#endif
9e6f4ca3
JK		 1176 kthread_stop(s->kworker_task);
1177
1178out_uart:
dfeae619
JR		 1179 uart_unregister_driver(&s->uart);
1180
1181out_clk:
1182 if (!IS_ERR(s->clk))
1183 clk_disable_unprepare(s->clk);
1184
1185 return ret;
1186}
1187
1188static int sc16is7xx_remove(struct device *dev)
1189{
1190 struct sc16is7xx_port *s = dev_get_drvdata(dev);
e27e2786 1191 int i;
dfeae619
JR		 1192
1193#ifdef CONFIG_GPIOLIB
e27e2786
LW		 1194 if (s->devtype->nr_gpio)
1195 gpiochip_remove(&s->gpio);
dfeae619
JR		 1196#endif
1197
1198 for (i = 0; i < s->uart.nr; i++) {
dfeae619
JR		 1199 uart_remove_one_port(&s->uart, &s->p[i].port);
1200 sc16is7xx_power(&s->p[i].port, 0);
1201 }
1202
9e6f4ca3
JK		 1203 flush_kthread_worker(&s->kworker);
1204 kthread_stop(s->kworker_task);
1205
dfeae619
JR		 1206 uart_unregister_driver(&s->uart);
1207 if (!IS_ERR(s->clk))
1208 clk_disable_unprepare(s->clk);
1209
e27e2786 1210 return 0;
dfeae619
JR		 1211}
1212
1213static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1214 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },
1215 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },
1216 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },
1217 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },
1218 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },
1219 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },
1220 { }
1221};
1222MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1223
1224static struct regmap_config regcfg = {
1225 .reg_bits = 7,
1226 .pad_bits = 1,
1227 .val_bits = 8,
1228 .cache_type = REGCACHE_RBTREE,
1229 .volatile_reg = sc16is7xx_regmap_volatile,
1230 .precious_reg = sc16is7xx_regmap_precious,
1231};
1232
2c837a8a
RKKI		 1233#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1234static int sc16is7xx_spi_probe(struct spi_device *spi)
1235{
1236 struct sc16is7xx_devtype *devtype;
1237 unsigned long flags = 0;
1238 struct regmap *regmap;
1239 int ret;
1240
1241 /* Setup SPI bus */
1242 spi->bits_per_word = 8;
1243 /* only supports mode 0 on SC16IS762 */
1244 spi->mode = spi->mode ? : SPI_MODE_0;
1245 spi->max_speed_hz = spi->max_speed_hz ? : 15000000;
1246 ret = spi_setup(spi);
1247 if (ret)
1248 return ret;
1249
1250 if (spi->dev.of_node) {
1251 const struct of_device_id *of_id =
1252 of_match_device(sc16is7xx_dt_ids, &spi->dev);
1253
1254 devtype = (struct sc16is7xx_devtype *)of_id->data;
1255 } else {
1256 const struct spi_device_id *id_entry = spi_get_device_id(spi);
1257
1258 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data;
1259 flags = IRQF_TRIGGER_FALLING;
1260 }
1261
1262 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1263 (devtype->nr_uart - 1);
1264 regmap = devm_regmap_init_spi(spi, &regcfg);
1265
1266 return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq, flags);
1267}
1268
1269static int sc16is7xx_spi_remove(struct spi_device *spi)
1270{
1271 return sc16is7xx_remove(&spi->dev);
1272}
1273
1274static const struct spi_device_id sc16is7xx_spi_id_table[] = {
1275 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
4117a60c
JK		 1276 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1277 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
2c837a8a
RKKI		 1278 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1279 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1280 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1281 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1282 { }
1283};
1284
1285MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table);
1286
1287static struct spi_driver sc16is7xx_spi_uart_driver = {
1288 .driver = {
1289 .name = SC16IS7XX_NAME,
1290 .owner = THIS_MODULE,
1291 .of_match_table = of_match_ptr(sc16is7xx_dt_ids),
1292 },
1293 .probe = sc16is7xx_spi_probe,
1294 .remove = sc16is7xx_spi_remove,
1295 .id_table = sc16is7xx_spi_id_table,
1296};
1297
1298MODULE_ALIAS("spi:sc16is7xx");
1299#endif
1300
1301#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
dfeae619
JR		 1302static int sc16is7xx_i2c_probe(struct i2c_client *i2c,
1303 const struct i2c_device_id *id)
1304{
1305 struct sc16is7xx_devtype *devtype;
1306 unsigned long flags = 0;
1307 struct regmap *regmap;
1308
1309 if (i2c->dev.of_node) {
1310 const struct of_device_id *of_id =
1311 of_match_device(sc16is7xx_dt_ids, &i2c->dev);
1312
1313 devtype = (struct sc16is7xx_devtype *)of_id->data;
1314 } else {
1315 devtype = (struct sc16is7xx_devtype *)id->driver_data;
1316 flags = IRQF_TRIGGER_FALLING;
1317 }
1318
1319 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1320 (devtype->nr_uart - 1);
1321 regmap = devm_regmap_init_i2c(i2c, &regcfg);
1322
1323 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq, flags);
1324}
1325
1326static int sc16is7xx_i2c_remove(struct i2c_client *client)
1327{
1328 return sc16is7xx_remove(&client->dev);
1329}
1330
1331static const struct i2c_device_id sc16is7xx_i2c_id_table[] = {
1332 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
4117a60c
JK		 1333 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1334 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
dfeae619
JR		 1335 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1336 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1337 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1338 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1339 { }
1340};
1341MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table);
1342
1343static struct i2c_driver sc16is7xx_i2c_uart_driver = {
1344 .driver = {
1345 .name = SC16IS7XX_NAME,
1346 .owner = THIS_MODULE,
1347 .of_match_table = of_match_ptr(sc16is7xx_dt_ids),
1348 },
1349 .probe = sc16is7xx_i2c_probe,
1350 .remove = sc16is7xx_i2c_remove,
1351 .id_table = sc16is7xx_i2c_id_table,
1352};
2c837a8a 1353
dfeae619 1354MODULE_ALIAS("i2c:sc16is7xx");
2c837a8a
RKKI		 1355#endif
1356
1357static int __init sc16is7xx_init(void)
1358{
1359 int ret = 0;
1360#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1361 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver);
1362 if (ret < 0) {
1363 pr_err("failed to init sc16is7xx i2c --> %d\n", ret);
1364 return ret;
1365 }
1366#endif
1367
1368#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1369 ret = spi_register_driver(&sc16is7xx_spi_uart_driver);
1370 if (ret < 0) {
1371 pr_err("failed to init sc16is7xx spi --> %d\n", ret);
1372 return ret;
1373 }
1374#endif
1375 return ret;
1376}
1377module_init(sc16is7xx_init);
1378
1379static void __exit sc16is7xx_exit(void)
1380{
1381#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1382 i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1383#endif
1384
1385#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1386 spi_unregister_driver(&sc16is7xx_spi_uart_driver);
1387#endif
1388}
1389module_exit(sc16is7xx_exit);
dfeae619
JR		 1390
1391MODULE_LICENSE("GPL");
1392MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1393MODULE_DESCRIPTION("SC16IS7XX serial driver");
Linux kernel - Deliverables
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