Commit | Line | Data |
---|---|---|
72246da4 FB |
1 | /** |
2 | * core.c - DesignWare USB3 DRD Controller Core file | |
3 | * | |
4 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com | |
72246da4 FB |
5 | * |
6 | * Authors: Felipe Balbi <balbi@ti.com>, | |
7 | * Sebastian Andrzej Siewior <bigeasy@linutronix.de> | |
8 | * | |
5945f789 FB |
9 | * This program is free software: you can redistribute it and/or modify |
10 | * it under the terms of the GNU General Public License version 2 of | |
11 | * the License as published by the Free Software Foundation. | |
72246da4 | 12 | * |
5945f789 FB |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
72246da4 | 17 | * |
5945f789 FB |
18 | * You should have received a copy of the GNU General Public License |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
72246da4 FB |
20 | */ |
21 | ||
a72e658b | 22 | #include <linux/module.h> |
72246da4 FB |
23 | #include <linux/kernel.h> |
24 | #include <linux/slab.h> | |
25 | #include <linux/spinlock.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/pm_runtime.h> | |
28 | #include <linux/interrupt.h> | |
29 | #include <linux/ioport.h> | |
30 | #include <linux/io.h> | |
31 | #include <linux/list.h> | |
32 | #include <linux/delay.h> | |
33 | #include <linux/dma-mapping.h> | |
457e84b6 | 34 | #include <linux/of.h> |
72246da4 | 35 | |
51e1e7bc | 36 | #include <linux/usb/otg.h> |
72246da4 FB |
37 | #include <linux/usb/ch9.h> |
38 | #include <linux/usb/gadget.h> | |
39 | ||
6462cbd5 | 40 | #include "platform_data.h" |
72246da4 FB |
41 | #include "core.h" |
42 | #include "gadget.h" | |
43 | #include "io.h" | |
44 | ||
45 | #include "debug.h" | |
46 | ||
6c167fc9 FB |
47 | static char *maximum_speed = "super"; |
48 | module_param(maximum_speed, charp, 0); | |
49 | MODULE_PARM_DESC(maximum_speed, "Maximum supported speed."); | |
50 | ||
8300dd23 FB |
51 | /* -------------------------------------------------------------------------- */ |
52 | ||
3140e8cb SAS |
53 | void dwc3_set_mode(struct dwc3 *dwc, u32 mode) |
54 | { | |
55 | u32 reg; | |
56 | ||
57 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
58 | reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)); | |
59 | reg |= DWC3_GCTL_PRTCAPDIR(mode); | |
60 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
61 | } | |
8300dd23 | 62 | |
72246da4 FB |
63 | /** |
64 | * dwc3_core_soft_reset - Issues core soft reset and PHY reset | |
65 | * @dwc: pointer to our context structure | |
66 | */ | |
67 | static void dwc3_core_soft_reset(struct dwc3 *dwc) | |
68 | { | |
69 | u32 reg; | |
70 | ||
71 | /* Before Resetting PHY, put Core in Reset */ | |
72 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
73 | reg |= DWC3_GCTL_CORESOFTRESET; | |
74 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
75 | ||
76 | /* Assert USB3 PHY reset */ | |
77 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
78 | reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; | |
79 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); | |
80 | ||
81 | /* Assert USB2 PHY reset */ | |
82 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
83 | reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; | |
84 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
85 | ||
51e1e7bc FB |
86 | usb_phy_init(dwc->usb2_phy); |
87 | usb_phy_init(dwc->usb3_phy); | |
72246da4 FB |
88 | mdelay(100); |
89 | ||
90 | /* Clear USB3 PHY reset */ | |
91 | reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); | |
92 | reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; | |
93 | dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); | |
94 | ||
95 | /* Clear USB2 PHY reset */ | |
96 | reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); | |
97 | reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; | |
98 | dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); | |
99 | ||
45627ac6 PA |
100 | mdelay(100); |
101 | ||
72246da4 FB |
102 | /* After PHYs are stable we can take Core out of reset state */ |
103 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); | |
104 | reg &= ~DWC3_GCTL_CORESOFTRESET; | |
105 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); | |
106 | } | |
107 | ||
108 | /** | |
109 | * dwc3_free_one_event_buffer - Frees one event buffer | |
110 | * @dwc: Pointer to our controller context structure | |
111 | * @evt: Pointer to event buffer to be freed | |
112 | */ | |
113 | static void dwc3_free_one_event_buffer(struct dwc3 *dwc, | |
114 | struct dwc3_event_buffer *evt) | |
115 | { | |
116 | dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma); | |
72246da4 FB |
117 | } |
118 | ||
119 | /** | |
1d046793 | 120 | * dwc3_alloc_one_event_buffer - Allocates one event buffer structure |
72246da4 FB |
121 | * @dwc: Pointer to our controller context structure |
122 | * @length: size of the event buffer | |
123 | * | |
1d046793 | 124 | * Returns a pointer to the allocated event buffer structure on success |
72246da4 FB |
125 | * otherwise ERR_PTR(errno). |
126 | */ | |
67d0b500 FB |
127 | static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc, |
128 | unsigned length) | |
72246da4 FB |
129 | { |
130 | struct dwc3_event_buffer *evt; | |
131 | ||
380f0d28 | 132 | evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL); |
72246da4 FB |
133 | if (!evt) |
134 | return ERR_PTR(-ENOMEM); | |
135 | ||
136 | evt->dwc = dwc; | |
137 | evt->length = length; | |
138 | evt->buf = dma_alloc_coherent(dwc->dev, length, | |
139 | &evt->dma, GFP_KERNEL); | |
e32672f0 | 140 | if (!evt->buf) |
72246da4 | 141 | return ERR_PTR(-ENOMEM); |
72246da4 FB |
142 | |
143 | return evt; | |
144 | } | |
145 | ||
146 | /** | |
147 | * dwc3_free_event_buffers - frees all allocated event buffers | |
148 | * @dwc: Pointer to our controller context structure | |
149 | */ | |
150 | static void dwc3_free_event_buffers(struct dwc3 *dwc) | |
151 | { | |
152 | struct dwc3_event_buffer *evt; | |
153 | int i; | |
154 | ||
9f622b2a | 155 | for (i = 0; i < dwc->num_event_buffers; i++) { |
72246da4 | 156 | evt = dwc->ev_buffs[i]; |
64b6c8a7 | 157 | if (evt) |
72246da4 | 158 | dwc3_free_one_event_buffer(dwc, evt); |
72246da4 FB |
159 | } |
160 | } | |
161 | ||
162 | /** | |
163 | * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length | |
1d046793 | 164 | * @dwc: pointer to our controller context structure |
72246da4 FB |
165 | * @length: size of event buffer |
166 | * | |
1d046793 | 167 | * Returns 0 on success otherwise negative errno. In the error case, dwc |
72246da4 FB |
168 | * may contain some buffers allocated but not all which were requested. |
169 | */ | |
41ac7b3a | 170 | static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length) |
72246da4 | 171 | { |
9f622b2a | 172 | int num; |
72246da4 FB |
173 | int i; |
174 | ||
9f622b2a FB |
175 | num = DWC3_NUM_INT(dwc->hwparams.hwparams1); |
176 | dwc->num_event_buffers = num; | |
177 | ||
380f0d28 FB |
178 | dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num, |
179 | GFP_KERNEL); | |
457d3f21 FB |
180 | if (!dwc->ev_buffs) { |
181 | dev_err(dwc->dev, "can't allocate event buffers array\n"); | |
182 | return -ENOMEM; | |
183 | } | |
184 | ||
72246da4 FB |
185 | for (i = 0; i < num; i++) { |
186 | struct dwc3_event_buffer *evt; | |
187 | ||
188 | evt = dwc3_alloc_one_event_buffer(dwc, length); | |
189 | if (IS_ERR(evt)) { | |
190 | dev_err(dwc->dev, "can't allocate event buffer\n"); | |
191 | return PTR_ERR(evt); | |
192 | } | |
193 | dwc->ev_buffs[i] = evt; | |
194 | } | |
195 | ||
196 | return 0; | |
197 | } | |
198 | ||
199 | /** | |
200 | * dwc3_event_buffers_setup - setup our allocated event buffers | |
1d046793 | 201 | * @dwc: pointer to our controller context structure |
72246da4 FB |
202 | * |
203 | * Returns 0 on success otherwise negative errno. | |
204 | */ | |
7acd85e0 | 205 | static int dwc3_event_buffers_setup(struct dwc3 *dwc) |
72246da4 FB |
206 | { |
207 | struct dwc3_event_buffer *evt; | |
208 | int n; | |
209 | ||
9f622b2a | 210 | for (n = 0; n < dwc->num_event_buffers; n++) { |
72246da4 FB |
211 | evt = dwc->ev_buffs[n]; |
212 | dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n", | |
213 | evt->buf, (unsigned long long) evt->dma, | |
214 | evt->length); | |
215 | ||
7acd85e0 PZ |
216 | evt->lpos = 0; |
217 | ||
72246da4 FB |
218 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), |
219 | lower_32_bits(evt->dma)); | |
220 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), | |
221 | upper_32_bits(evt->dma)); | |
222 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), | |
223 | evt->length & 0xffff); | |
224 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); | |
225 | } | |
226 | ||
227 | return 0; | |
228 | } | |
229 | ||
230 | static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) | |
231 | { | |
232 | struct dwc3_event_buffer *evt; | |
233 | int n; | |
234 | ||
9f622b2a | 235 | for (n = 0; n < dwc->num_event_buffers; n++) { |
72246da4 | 236 | evt = dwc->ev_buffs[n]; |
7acd85e0 PZ |
237 | |
238 | evt->lpos = 0; | |
239 | ||
72246da4 FB |
240 | dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0); |
241 | dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0); | |
242 | dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0); | |
243 | dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0); | |
244 | } | |
245 | } | |
246 | ||
789451f6 FB |
247 | static void dwc3_core_num_eps(struct dwc3 *dwc) |
248 | { | |
249 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
250 | ||
251 | dwc->num_in_eps = DWC3_NUM_IN_EPS(parms); | |
252 | dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps; | |
253 | ||
254 | dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n", | |
255 | dwc->num_in_eps, dwc->num_out_eps); | |
256 | } | |
257 | ||
41ac7b3a | 258 | static void dwc3_cache_hwparams(struct dwc3 *dwc) |
26ceca97 FB |
259 | { |
260 | struct dwc3_hwparams *parms = &dwc->hwparams; | |
261 | ||
262 | parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); | |
263 | parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); | |
264 | parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); | |
265 | parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); | |
266 | parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); | |
267 | parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); | |
268 | parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); | |
269 | parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); | |
270 | parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); | |
271 | } | |
272 | ||
72246da4 FB |
273 | /** |
274 | * dwc3_core_init - Low-level initialization of DWC3 Core | |
275 | * @dwc: Pointer to our controller context structure | |
276 | * | |
277 | * Returns 0 on success otherwise negative errno. | |
278 | */ | |
41ac7b3a | 279 | static int dwc3_core_init(struct dwc3 *dwc) |
72246da4 FB |
280 | { |
281 | unsigned long timeout; | |
282 | u32 reg; | |
283 | int ret; | |
284 | ||
7650bd74 SAS |
285 | reg = dwc3_readl(dwc->regs, DWC3_GSNPSID); |
286 | /* This should read as U3 followed by revision number */ | |
287 | if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) { | |
288 | dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n"); | |
289 | ret = -ENODEV; | |
290 | goto err0; | |
291 | } | |
248b122b | 292 | dwc->revision = reg; |
7650bd74 | 293 | |
72246da4 FB |
294 | /* issue device SoftReset too */ |
295 | timeout = jiffies + msecs_to_jiffies(500); | |
296 | dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); | |
297 | do { | |
298 | reg = dwc3_readl(dwc->regs, DWC3_DCTL); | |
299 | if (!(reg & DWC3_DCTL_CSFTRST)) | |
300 | break; | |
301 | ||
302 | if (time_after(jiffies, timeout)) { | |
303 | dev_err(dwc->dev, "Reset Timed Out\n"); | |
304 | ret = -ETIMEDOUT; | |
305 | goto err0; | |
306 | } | |
307 | ||
308 | cpu_relax(); | |
309 | } while (true); | |
310 | ||
58a0f23f PA |
311 | dwc3_core_soft_reset(dwc); |
312 | ||
4878a028 | 313 | reg = dwc3_readl(dwc->regs, DWC3_GCTL); |
3e87c42a | 314 | reg &= ~DWC3_GCTL_SCALEDOWN_MASK; |
4878a028 SAS |
315 | reg &= ~DWC3_GCTL_DISSCRAMBLE; |
316 | ||
164d7731 | 317 | switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { |
4878a028 SAS |
318 | case DWC3_GHWPARAMS1_EN_PWROPT_CLK: |
319 | reg &= ~DWC3_GCTL_DSBLCLKGTNG; | |
320 | break; | |
321 | default: | |
322 | dev_dbg(dwc->dev, "No power optimization available\n"); | |
323 | } | |
324 | ||
325 | /* | |
326 | * WORKAROUND: DWC3 revisions <1.90a have a bug | |
1d046793 | 327 | * where the device can fail to connect at SuperSpeed |
4878a028 | 328 | * and falls back to high-speed mode which causes |
1d046793 | 329 | * the device to enter a Connect/Disconnect loop |
4878a028 SAS |
330 | */ |
331 | if (dwc->revision < DWC3_REVISION_190A) | |
332 | reg |= DWC3_GCTL_U2RSTECN; | |
333 | ||
789451f6 FB |
334 | dwc3_core_num_eps(dwc); |
335 | ||
4878a028 SAS |
336 | dwc3_writel(dwc->regs, DWC3_GCTL, reg); |
337 | ||
72246da4 FB |
338 | return 0; |
339 | ||
72246da4 FB |
340 | err0: |
341 | return ret; | |
342 | } | |
343 | ||
344 | static void dwc3_core_exit(struct dwc3 *dwc) | |
345 | { | |
01b8daf7 VG |
346 | usb_phy_shutdown(dwc->usb2_phy); |
347 | usb_phy_shutdown(dwc->usb3_phy); | |
72246da4 FB |
348 | } |
349 | ||
350 | #define DWC3_ALIGN_MASK (16 - 1) | |
351 | ||
41ac7b3a | 352 | static int dwc3_probe(struct platform_device *pdev) |
72246da4 | 353 | { |
6462cbd5 | 354 | struct dwc3_platform_data *pdata = pdev->dev.platform_data; |
457e84b6 | 355 | struct device_node *node = pdev->dev.of_node; |
72246da4 FB |
356 | struct resource *res; |
357 | struct dwc3 *dwc; | |
802ca850 | 358 | struct device *dev = &pdev->dev; |
0949e99b | 359 | |
72246da4 | 360 | int ret = -ENOMEM; |
0949e99b FB |
361 | |
362 | void __iomem *regs; | |
72246da4 FB |
363 | void *mem; |
364 | ||
0949e99b FB |
365 | u8 mode; |
366 | ||
802ca850 | 367 | mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL); |
72246da4 | 368 | if (!mem) { |
802ca850 CP |
369 | dev_err(dev, "not enough memory\n"); |
370 | return -ENOMEM; | |
72246da4 FB |
371 | } |
372 | dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1); | |
373 | dwc->mem = mem; | |
374 | ||
51249dca | 375 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
72246da4 | 376 | if (!res) { |
51249dca | 377 | dev_err(dev, "missing IRQ\n"); |
802ca850 | 378 | return -ENODEV; |
72246da4 | 379 | } |
066618bc KVA |
380 | dwc->xhci_resources[1].start = res->start; |
381 | dwc->xhci_resources[1].end = res->end; | |
382 | dwc->xhci_resources[1].flags = res->flags; | |
383 | dwc->xhci_resources[1].name = res->name; | |
72246da4 | 384 | |
51249dca IS |
385 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
386 | if (!res) { | |
387 | dev_err(dev, "missing memory resource\n"); | |
388 | return -ENODEV; | |
389 | } | |
066618bc | 390 | dwc->xhci_resources[0].start = res->start; |
51249dca IS |
391 | dwc->xhci_resources[0].end = dwc->xhci_resources[0].start + |
392 | DWC3_XHCI_REGS_END; | |
066618bc KVA |
393 | dwc->xhci_resources[0].flags = res->flags; |
394 | dwc->xhci_resources[0].name = res->name; | |
51249dca IS |
395 | |
396 | /* | |
397 | * Request memory region but exclude xHCI regs, | |
398 | * since it will be requested by the xhci-plat driver. | |
399 | */ | |
400 | res = devm_request_mem_region(dev, res->start + DWC3_GLOBALS_REGS_START, | |
401 | resource_size(res) - DWC3_GLOBALS_REGS_START, | |
802ca850 | 402 | dev_name(dev)); |
72246da4 | 403 | if (!res) { |
802ca850 CP |
404 | dev_err(dev, "can't request mem region\n"); |
405 | return -ENOMEM; | |
72246da4 FB |
406 | } |
407 | ||
b7e38aa6 | 408 | regs = devm_ioremap_nocache(dev, res->start, resource_size(res)); |
72246da4 | 409 | if (!regs) { |
802ca850 CP |
410 | dev_err(dev, "ioremap failed\n"); |
411 | return -ENOMEM; | |
72246da4 FB |
412 | } |
413 | ||
5088b6f5 KVA |
414 | if (node) { |
415 | dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0); | |
416 | dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1); | |
6462cbd5 FB |
417 | |
418 | dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize"); | |
5088b6f5 KVA |
419 | } else { |
420 | dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2); | |
421 | dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3); | |
6462cbd5 FB |
422 | |
423 | dwc->needs_fifo_resize = pdata->tx_fifo_resize; | |
5088b6f5 KVA |
424 | } |
425 | ||
d105e7f8 FB |
426 | if (IS_ERR(dwc->usb2_phy)) { |
427 | ret = PTR_ERR(dwc->usb2_phy); | |
428 | ||
429 | /* | |
430 | * if -ENXIO is returned, it means PHY layer wasn't | |
431 | * enabled, so it makes no sense to return -EPROBE_DEFER | |
432 | * in that case, since no PHY driver will ever probe. | |
433 | */ | |
434 | if (ret == -ENXIO) | |
435 | return ret; | |
436 | ||
51e1e7bc FB |
437 | dev_err(dev, "no usb2 phy configured\n"); |
438 | return -EPROBE_DEFER; | |
439 | } | |
440 | ||
d105e7f8 | 441 | if (IS_ERR(dwc->usb3_phy)) { |
315955d7 | 442 | ret = PTR_ERR(dwc->usb3_phy); |
d105e7f8 FB |
443 | |
444 | /* | |
445 | * if -ENXIO is returned, it means PHY layer wasn't | |
446 | * enabled, so it makes no sense to return -EPROBE_DEFER | |
447 | * in that case, since no PHY driver will ever probe. | |
448 | */ | |
449 | if (ret == -ENXIO) | |
450 | return ret; | |
451 | ||
51e1e7bc FB |
452 | dev_err(dev, "no usb3 phy configured\n"); |
453 | return -EPROBE_DEFER; | |
454 | } | |
455 | ||
8ba007a9 KVA |
456 | usb_phy_set_suspend(dwc->usb2_phy, 0); |
457 | usb_phy_set_suspend(dwc->usb3_phy, 0); | |
458 | ||
72246da4 FB |
459 | spin_lock_init(&dwc->lock); |
460 | platform_set_drvdata(pdev, dwc); | |
461 | ||
462 | dwc->regs = regs; | |
463 | dwc->regs_size = resource_size(res); | |
802ca850 | 464 | dwc->dev = dev; |
72246da4 | 465 | |
ddff14f1 KVA |
466 | dev->dma_mask = dev->parent->dma_mask; |
467 | dev->dma_parms = dev->parent->dma_parms; | |
468 | dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask); | |
469 | ||
6c167fc9 FB |
470 | if (!strncmp("super", maximum_speed, 5)) |
471 | dwc->maximum_speed = DWC3_DCFG_SUPERSPEED; | |
472 | else if (!strncmp("high", maximum_speed, 4)) | |
473 | dwc->maximum_speed = DWC3_DCFG_HIGHSPEED; | |
474 | else if (!strncmp("full", maximum_speed, 4)) | |
475 | dwc->maximum_speed = DWC3_DCFG_FULLSPEED1; | |
476 | else if (!strncmp("low", maximum_speed, 3)) | |
477 | dwc->maximum_speed = DWC3_DCFG_LOWSPEED; | |
478 | else | |
479 | dwc->maximum_speed = DWC3_DCFG_SUPERSPEED; | |
480 | ||
802ca850 CP |
481 | pm_runtime_enable(dev); |
482 | pm_runtime_get_sync(dev); | |
483 | pm_runtime_forbid(dev); | |
72246da4 | 484 | |
4fd24483 KVA |
485 | dwc3_cache_hwparams(dwc); |
486 | ||
3921426b FB |
487 | ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); |
488 | if (ret) { | |
489 | dev_err(dwc->dev, "failed to allocate event buffers\n"); | |
490 | ret = -ENOMEM; | |
491 | goto err0; | |
492 | } | |
493 | ||
72246da4 FB |
494 | ret = dwc3_core_init(dwc); |
495 | if (ret) { | |
802ca850 | 496 | dev_err(dev, "failed to initialize core\n"); |
3921426b | 497 | goto err0; |
72246da4 FB |
498 | } |
499 | ||
f122d33e FB |
500 | ret = dwc3_event_buffers_setup(dwc); |
501 | if (ret) { | |
502 | dev_err(dwc->dev, "failed to setup event buffers\n"); | |
503 | goto err1; | |
504 | } | |
505 | ||
cd051da2 VG |
506 | if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) |
507 | mode = DWC3_MODE_HOST; | |
508 | else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) | |
509 | mode = DWC3_MODE_DEVICE; | |
510 | else | |
511 | mode = DWC3_MODE_DRD; | |
0949e99b FB |
512 | |
513 | switch (mode) { | |
0949e99b | 514 | case DWC3_MODE_DEVICE: |
3140e8cb | 515 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); |
72246da4 FB |
516 | ret = dwc3_gadget_init(dwc); |
517 | if (ret) { | |
802ca850 | 518 | dev_err(dev, "failed to initialize gadget\n"); |
f122d33e | 519 | goto err2; |
72246da4 | 520 | } |
d07e8819 FB |
521 | break; |
522 | case DWC3_MODE_HOST: | |
3140e8cb | 523 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); |
d07e8819 FB |
524 | ret = dwc3_host_init(dwc); |
525 | if (ret) { | |
802ca850 | 526 | dev_err(dev, "failed to initialize host\n"); |
f122d33e | 527 | goto err2; |
d07e8819 FB |
528 | } |
529 | break; | |
530 | case DWC3_MODE_DRD: | |
3140e8cb | 531 | dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); |
d07e8819 FB |
532 | ret = dwc3_host_init(dwc); |
533 | if (ret) { | |
802ca850 | 534 | dev_err(dev, "failed to initialize host\n"); |
f122d33e | 535 | goto err2; |
d07e8819 FB |
536 | } |
537 | ||
72246da4 FB |
538 | ret = dwc3_gadget_init(dwc); |
539 | if (ret) { | |
802ca850 | 540 | dev_err(dev, "failed to initialize gadget\n"); |
f122d33e | 541 | goto err2; |
72246da4 | 542 | } |
0949e99b FB |
543 | break; |
544 | default: | |
802ca850 | 545 | dev_err(dev, "Unsupported mode of operation %d\n", mode); |
f122d33e | 546 | goto err2; |
72246da4 | 547 | } |
0949e99b | 548 | dwc->mode = mode; |
72246da4 FB |
549 | |
550 | ret = dwc3_debugfs_init(dwc); | |
551 | if (ret) { | |
802ca850 | 552 | dev_err(dev, "failed to initialize debugfs\n"); |
f122d33e | 553 | goto err3; |
72246da4 FB |
554 | } |
555 | ||
802ca850 | 556 | pm_runtime_allow(dev); |
72246da4 FB |
557 | |
558 | return 0; | |
559 | ||
f122d33e | 560 | err3: |
0949e99b | 561 | switch (mode) { |
0949e99b | 562 | case DWC3_MODE_DEVICE: |
72246da4 | 563 | dwc3_gadget_exit(dwc); |
0949e99b | 564 | break; |
d07e8819 FB |
565 | case DWC3_MODE_HOST: |
566 | dwc3_host_exit(dwc); | |
567 | break; | |
568 | case DWC3_MODE_DRD: | |
569 | dwc3_host_exit(dwc); | |
72246da4 | 570 | dwc3_gadget_exit(dwc); |
d07e8819 | 571 | break; |
0949e99b FB |
572 | default: |
573 | /* do nothing */ | |
574 | break; | |
575 | } | |
72246da4 | 576 | |
f122d33e FB |
577 | err2: |
578 | dwc3_event_buffers_cleanup(dwc); | |
579 | ||
72246da4 | 580 | err1: |
802ca850 | 581 | dwc3_core_exit(dwc); |
72246da4 | 582 | |
3921426b FB |
583 | err0: |
584 | dwc3_free_event_buffers(dwc); | |
585 | ||
72246da4 FB |
586 | return ret; |
587 | } | |
588 | ||
fb4e98ab | 589 | static int dwc3_remove(struct platform_device *pdev) |
72246da4 | 590 | { |
72246da4 | 591 | struct dwc3 *dwc = platform_get_drvdata(pdev); |
72246da4 | 592 | |
8ba007a9 KVA |
593 | usb_phy_set_suspend(dwc->usb2_phy, 1); |
594 | usb_phy_set_suspend(dwc->usb3_phy, 1); | |
595 | ||
72246da4 FB |
596 | pm_runtime_put(&pdev->dev); |
597 | pm_runtime_disable(&pdev->dev); | |
598 | ||
599 | dwc3_debugfs_exit(dwc); | |
600 | ||
0949e99b | 601 | switch (dwc->mode) { |
0949e99b | 602 | case DWC3_MODE_DEVICE: |
72246da4 | 603 | dwc3_gadget_exit(dwc); |
0949e99b | 604 | break; |
d07e8819 FB |
605 | case DWC3_MODE_HOST: |
606 | dwc3_host_exit(dwc); | |
607 | break; | |
608 | case DWC3_MODE_DRD: | |
609 | dwc3_host_exit(dwc); | |
72246da4 | 610 | dwc3_gadget_exit(dwc); |
d07e8819 | 611 | break; |
0949e99b FB |
612 | default: |
613 | /* do nothing */ | |
614 | break; | |
615 | } | |
72246da4 | 616 | |
f122d33e | 617 | dwc3_event_buffers_cleanup(dwc); |
d9b4330a | 618 | dwc3_free_event_buffers(dwc); |
72246da4 | 619 | dwc3_core_exit(dwc); |
72246da4 FB |
620 | |
621 | return 0; | |
622 | } | |
623 | ||
19fda7cd | 624 | #ifdef CONFIG_PM_SLEEP |
7415f17c FB |
625 | static int dwc3_prepare(struct device *dev) |
626 | { | |
627 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
628 | unsigned long flags; | |
629 | ||
630 | spin_lock_irqsave(&dwc->lock, flags); | |
631 | ||
632 | switch (dwc->mode) { | |
633 | case DWC3_MODE_DEVICE: | |
634 | case DWC3_MODE_DRD: | |
635 | dwc3_gadget_prepare(dwc); | |
636 | /* FALLTHROUGH */ | |
637 | case DWC3_MODE_HOST: | |
638 | default: | |
639 | dwc3_event_buffers_cleanup(dwc); | |
640 | break; | |
641 | } | |
642 | ||
643 | spin_unlock_irqrestore(&dwc->lock, flags); | |
644 | ||
645 | return 0; | |
646 | } | |
647 | ||
648 | static void dwc3_complete(struct device *dev) | |
649 | { | |
650 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
651 | unsigned long flags; | |
652 | ||
653 | spin_lock_irqsave(&dwc->lock, flags); | |
654 | ||
655 | switch (dwc->mode) { | |
656 | case DWC3_MODE_DEVICE: | |
657 | case DWC3_MODE_DRD: | |
658 | dwc3_gadget_complete(dwc); | |
659 | /* FALLTHROUGH */ | |
660 | case DWC3_MODE_HOST: | |
661 | default: | |
662 | dwc3_event_buffers_setup(dwc); | |
663 | break; | |
664 | } | |
665 | ||
666 | spin_unlock_irqrestore(&dwc->lock, flags); | |
667 | } | |
668 | ||
669 | static int dwc3_suspend(struct device *dev) | |
670 | { | |
671 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
672 | unsigned long flags; | |
673 | ||
674 | spin_lock_irqsave(&dwc->lock, flags); | |
675 | ||
676 | switch (dwc->mode) { | |
677 | case DWC3_MODE_DEVICE: | |
678 | case DWC3_MODE_DRD: | |
679 | dwc3_gadget_suspend(dwc); | |
680 | /* FALLTHROUGH */ | |
681 | case DWC3_MODE_HOST: | |
682 | default: | |
683 | /* do nothing */ | |
684 | break; | |
685 | } | |
686 | ||
687 | dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL); | |
688 | spin_unlock_irqrestore(&dwc->lock, flags); | |
689 | ||
690 | usb_phy_shutdown(dwc->usb3_phy); | |
691 | usb_phy_shutdown(dwc->usb2_phy); | |
692 | ||
693 | return 0; | |
694 | } | |
695 | ||
696 | static int dwc3_resume(struct device *dev) | |
697 | { | |
698 | struct dwc3 *dwc = dev_get_drvdata(dev); | |
699 | unsigned long flags; | |
700 | ||
701 | usb_phy_init(dwc->usb3_phy); | |
702 | usb_phy_init(dwc->usb2_phy); | |
703 | msleep(100); | |
704 | ||
705 | spin_lock_irqsave(&dwc->lock, flags); | |
706 | ||
707 | dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl); | |
708 | ||
709 | switch (dwc->mode) { | |
710 | case DWC3_MODE_DEVICE: | |
711 | case DWC3_MODE_DRD: | |
712 | dwc3_gadget_resume(dwc); | |
713 | /* FALLTHROUGH */ | |
714 | case DWC3_MODE_HOST: | |
715 | default: | |
716 | /* do nothing */ | |
717 | break; | |
718 | } | |
719 | ||
720 | spin_unlock_irqrestore(&dwc->lock, flags); | |
721 | ||
722 | pm_runtime_disable(dev); | |
723 | pm_runtime_set_active(dev); | |
724 | pm_runtime_enable(dev); | |
725 | ||
726 | return 0; | |
727 | } | |
728 | ||
729 | static const struct dev_pm_ops dwc3_dev_pm_ops = { | |
730 | .prepare = dwc3_prepare, | |
731 | .complete = dwc3_complete, | |
732 | ||
733 | SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) | |
734 | }; | |
735 | ||
736 | #define DWC3_PM_OPS &(dwc3_dev_pm_ops) | |
737 | #else | |
738 | #define DWC3_PM_OPS NULL | |
739 | #endif | |
740 | ||
5088b6f5 KVA |
741 | #ifdef CONFIG_OF |
742 | static const struct of_device_id of_dwc3_match[] = { | |
743 | { | |
744 | .compatible = "synopsys,dwc3" | |
745 | }, | |
746 | { }, | |
747 | }; | |
748 | MODULE_DEVICE_TABLE(of, of_dwc3_match); | |
749 | #endif | |
750 | ||
72246da4 FB |
751 | static struct platform_driver dwc3_driver = { |
752 | .probe = dwc3_probe, | |
7690417d | 753 | .remove = dwc3_remove, |
72246da4 FB |
754 | .driver = { |
755 | .name = "dwc3", | |
5088b6f5 | 756 | .of_match_table = of_match_ptr(of_dwc3_match), |
7415f17c | 757 | .pm = DWC3_PM_OPS, |
72246da4 | 758 | }, |
72246da4 FB |
759 | }; |
760 | ||
b1116dcc TK |
761 | module_platform_driver(dwc3_driver); |
762 | ||
7ae4fc4d | 763 | MODULE_ALIAS("platform:dwc3"); |
72246da4 | 764 | MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>"); |
5945f789 | 765 | MODULE_LICENSE("GPL v2"); |
72246da4 | 766 | MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); |