[deliverable/linux.git] / drivers / usb / dwc3 / core.c

/**
 * core.c - DesignWare USB3 DRD Controller Core file
 *
 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
 *
 * Authors: Felipe Balbi <balbi@ti.com>,
 *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions, and the following disclaimer,
 *    without modification.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The names of the above-listed copyright holders may not be used
 *    to endorse or promote products derived from this software without
 *    specific prior written permission.
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") version 2, as published by the Free
 * Software Foundation.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/list.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/of.h>

#include <linux/usb/otg.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>

#include "core.h"
#include "gadget.h"
#include "io.h"

#include "debug.h"

static char *maximum_speed = "super";
module_param(maximum_speed, charp, 0);
MODULE_PARM_DESC(maximum_speed, "Maximum supported speed.");

/* -------------------------------------------------------------------------- */

void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
{
	u32 reg;

	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
	reg |= DWC3_GCTL_PRTCAPDIR(mode);
	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
}

/**
 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 * @dwc: pointer to our context structure
 */
static void dwc3_core_soft_reset(struct dwc3 *dwc)
{
	u32		reg;

	/* Before Resetting PHY, put Core in Reset */
	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	reg |= DWC3_GCTL_CORESOFTRESET;
	dwc3_writel(dwc->regs, DWC3_GCTL, reg);

	/* Assert USB3 PHY reset */
	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
	reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);

	/* Assert USB2 PHY reset */
	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
	reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);

	usb_phy_init(dwc->usb2_phy);
	usb_phy_init(dwc->usb3_phy);
	mdelay(100);

	/* Clear USB3 PHY reset */
	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
	reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);

	/* Clear USB2 PHY reset */
	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
	reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);

	mdelay(100);

	/* After PHYs are stable we can take Core out of reset state */
	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	reg &= ~DWC3_GCTL_CORESOFTRESET;
	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
}

/**
 * dwc3_free_one_event_buffer - Frees one event buffer
 * @dwc: Pointer to our controller context structure
 * @evt: Pointer to event buffer to be freed
 */
static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
		struct dwc3_event_buffer *evt)
{
	dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
}

/**
 * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 * @dwc: Pointer to our controller context structure
 * @length: size of the event buffer
 *
 * Returns a pointer to the allocated event buffer structure on success
 * otherwise ERR_PTR(errno).
 */
static struct dwc3_event_buffer *__devinit
dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
{
	struct dwc3_event_buffer	*evt;

	evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
	if (!evt)
		return ERR_PTR(-ENOMEM);

	evt->dwc	= dwc;
	evt->length	= length;
	evt->buf	= dma_alloc_coherent(dwc->dev, length,
			&evt->dma, GFP_KERNEL);
	if (!evt->buf)
		return ERR_PTR(-ENOMEM);

	return evt;
}

/**
 * dwc3_free_event_buffers - frees all allocated event buffers
 * @dwc: Pointer to our controller context structure
 */
static void dwc3_free_event_buffers(struct dwc3 *dwc)
{
	struct dwc3_event_buffer	*evt;
	int i;

	for (i = 0; i < dwc->num_event_buffers; i++) {
		evt = dwc->ev_buffs[i];
		if (evt)
			dwc3_free_one_event_buffer(dwc, evt);
	}
}

/**
 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 * @dwc: pointer to our controller context structure
 * @length: size of event buffer
 *
 * Returns 0 on success otherwise negative errno. In the error case, dwc
 * may contain some buffers allocated but not all which were requested.
 */
static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
{
	int			num;
	int			i;

	num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
	dwc->num_event_buffers = num;

	dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
			GFP_KERNEL);
	if (!dwc->ev_buffs) {
		dev_err(dwc->dev, "can't allocate event buffers array\n");
		return -ENOMEM;
	}

	for (i = 0; i < num; i++) {
		struct dwc3_event_buffer	*evt;

		evt = dwc3_alloc_one_event_buffer(dwc, length);
		if (IS_ERR(evt)) {
			dev_err(dwc->dev, "can't allocate event buffer\n");
			return PTR_ERR(evt);
		}
		dwc->ev_buffs[i] = evt;
	}

	return 0;
}

/**
 * dwc3_event_buffers_setup - setup our allocated event buffers
 * @dwc: pointer to our controller context structure
 *
 * Returns 0 on success otherwise negative errno.
 */
static int dwc3_event_buffers_setup(struct dwc3 *dwc)
{
	struct dwc3_event_buffer	*evt;
	int				n;

	for (n = 0; n < dwc->num_event_buffers; n++) {
		evt = dwc->ev_buffs[n];
		dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
				evt->buf, (unsigned long long) evt->dma,
				evt->length);

		evt->lpos = 0;

		dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
				lower_32_bits(evt->dma));
		dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
				upper_32_bits(evt->dma));
		dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
				evt->length & 0xffff);
		dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
	}

	return 0;
}

static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
{
	struct dwc3_event_buffer	*evt;
	int				n;

	for (n = 0; n < dwc->num_event_buffers; n++) {
		evt = dwc->ev_buffs[n];

		evt->lpos = 0;

		dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
		dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
		dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
		dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
	}
}

static void __devinit dwc3_cache_hwparams(struct dwc3 *dwc)
{
	struct dwc3_hwparams	*parms = &dwc->hwparams;

	parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
	parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
	parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
	parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
	parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
	parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
	parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
	parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
	parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
}

/**
 * dwc3_core_init - Low-level initialization of DWC3 Core
 * @dwc: Pointer to our controller context structure
 *
 * Returns 0 on success otherwise negative errno.
 */
static int __devinit dwc3_core_init(struct dwc3 *dwc)
{
	unsigned long		timeout;
	u32			reg;
	int			ret;

	reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
	/* This should read as U3 followed by revision number */
	if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
		dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
		ret = -ENODEV;
		goto err0;
	}
	dwc->revision = reg;

	/* issue device SoftReset too */
	timeout = jiffies + msecs_to_jiffies(500);
	dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
	do {
		reg = dwc3_readl(dwc->regs, DWC3_DCTL);
		if (!(reg & DWC3_DCTL_CSFTRST))
			break;

		if (time_after(jiffies, timeout)) {
			dev_err(dwc->dev, "Reset Timed Out\n");
			ret = -ETIMEDOUT;
			goto err0;
		}

		cpu_relax();
	} while (true);

	dwc3_core_soft_reset(dwc);

	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
	reg &= ~DWC3_GCTL_DISSCRAMBLE;

	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
		reg &= ~DWC3_GCTL_DSBLCLKGTNG;
		break;
	default:
		dev_dbg(dwc->dev, "No power optimization available\n");
	}

	/*
	 * WORKAROUND: DWC3 revisions <1.90a have a bug
	 * where the device can fail to connect at SuperSpeed
	 * and falls back to high-speed mode which causes
	 * the device to enter a Connect/Disconnect loop
	 */
	if (dwc->revision < DWC3_REVISION_190A)
		reg |= DWC3_GCTL_U2RSTECN;

	dwc3_writel(dwc->regs, DWC3_GCTL, reg);

	ret = dwc3_event_buffers_setup(dwc);
	if (ret) {
		dev_err(dwc->dev, "failed to setup event buffers\n");
		goto err0;
	}

	return 0;

err0:
	return ret;
}

static void dwc3_core_exit(struct dwc3 *dwc)
{
	dwc3_event_buffers_cleanup(dwc);

	usb_phy_shutdown(dwc->usb2_phy);
	usb_phy_shutdown(dwc->usb3_phy);
}

#define DWC3_ALIGN_MASK		(16 - 1)

static int __devinit dwc3_probe(struct platform_device *pdev)
{
	struct device_node	*node = pdev->dev.of_node;
	struct resource		*res;
	struct dwc3		*dwc;
	struct device		*dev = &pdev->dev;

	int			ret = -ENOMEM;

	void __iomem		*regs;
	void			*mem;

	u8			mode;

	mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
	if (!mem) {
		dev_err(dev, "not enough memory\n");
		return -ENOMEM;
	}
	dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
	dwc->mem = mem;

	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (!res) {
		dev_err(dev, "missing IRQ\n");
		return -ENODEV;
	}
	dwc->xhci_resources[1].start = res->start;
	dwc->xhci_resources[1].end = res->end;
	dwc->xhci_resources[1].flags = res->flags;
	dwc->xhci_resources[1].name = res->name;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(dev, "missing memory resource\n");
		return -ENODEV;
	}
	dwc->xhci_resources[0].start = res->start;
	dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
					DWC3_XHCI_REGS_END;
	dwc->xhci_resources[0].flags = res->flags;
	dwc->xhci_resources[0].name = res->name;

	 /*
	  * Request memory region but exclude xHCI regs,
	  * since it will be requested by the xhci-plat driver.
	  */
	res = devm_request_mem_region(dev, res->start + DWC3_GLOBALS_REGS_START,
			resource_size(res) - DWC3_GLOBALS_REGS_START,
			dev_name(dev));
	if (!res) {
		dev_err(dev, "can't request mem region\n");
		return -ENOMEM;
	}

	regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
	if (!regs) {
		dev_err(dev, "ioremap failed\n");
		return -ENOMEM;
	}

	dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
	if (IS_ERR_OR_NULL(dwc->usb2_phy)) {
		dev_err(dev, "no usb2 phy configured\n");
		return -EPROBE_DEFER;
	}

	dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
	if (IS_ERR_OR_NULL(dwc->usb3_phy)) {
		dev_err(dev, "no usb3 phy configured\n");
		return -EPROBE_DEFER;
	}

	spin_lock_init(&dwc->lock);
	platform_set_drvdata(pdev, dwc);

	dwc->regs	= regs;
	dwc->regs_size	= resource_size(res);
	dwc->dev	= dev;

	if (!strncmp("super", maximum_speed, 5))
		dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
	else if (!strncmp("high", maximum_speed, 4))
		dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;
	else if (!strncmp("full", maximum_speed, 4))
		dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;
	else if (!strncmp("low", maximum_speed, 3))
		dwc->maximum_speed = DWC3_DCFG_LOWSPEED;
	else
		dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;

	if (of_get_property(node, "tx-fifo-resize", NULL))
		dwc->needs_fifo_resize = true;

	pm_runtime_enable(dev);
	pm_runtime_get_sync(dev);
	pm_runtime_forbid(dev);

	dwc3_cache_hwparams(dwc);

	ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
	if (ret) {
		dev_err(dwc->dev, "failed to allocate event buffers\n");
		ret = -ENOMEM;
		goto err0;
	}

	ret = dwc3_core_init(dwc);
	if (ret) {
		dev_err(dev, "failed to initialize core\n");
		goto err0;
	}

	mode = DWC3_MODE(dwc->hwparams.hwparams0);

	switch (mode) {
	case DWC3_MODE_DEVICE:
		dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
		ret = dwc3_gadget_init(dwc);
		if (ret) {
			dev_err(dev, "failed to initialize gadget\n");
			goto err1;
		}
		break;
	case DWC3_MODE_HOST:
		dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
		ret = dwc3_host_init(dwc);
		if (ret) {
			dev_err(dev, "failed to initialize host\n");
			goto err1;
		}
		break;
	case DWC3_MODE_DRD:
		dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
		ret = dwc3_host_init(dwc);
		if (ret) {
			dev_err(dev, "failed to initialize host\n");
			goto err1;
		}

		ret = dwc3_gadget_init(dwc);
		if (ret) {
			dev_err(dev, "failed to initialize gadget\n");
			goto err1;
		}
		break;
	default:
		dev_err(dev, "Unsupported mode of operation %d\n", mode);
		goto err1;
	}
	dwc->mode = mode;

	ret = dwc3_debugfs_init(dwc);
	if (ret) {
		dev_err(dev, "failed to initialize debugfs\n");
		goto err2;
	}

	pm_runtime_allow(dev);

	return 0;

err2:
	switch (mode) {
	case DWC3_MODE_DEVICE:
		dwc3_gadget_exit(dwc);
		break;
	case DWC3_MODE_HOST:
		dwc3_host_exit(dwc);
		break;
	case DWC3_MODE_DRD:
		dwc3_host_exit(dwc);
		dwc3_gadget_exit(dwc);
		break;
	default:
		/* do nothing */
		break;
	}

err1:
	dwc3_core_exit(dwc);

err0:
	dwc3_free_event_buffers(dwc);

	return ret;
}

static int __devexit dwc3_remove(struct platform_device *pdev)
{
	struct dwc3	*dwc = platform_get_drvdata(pdev);
	struct resource	*res;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	pm_runtime_put(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	dwc3_debugfs_exit(dwc);

	switch (dwc->mode) {
	case DWC3_MODE_DEVICE:
		dwc3_gadget_exit(dwc);
		break;
	case DWC3_MODE_HOST:
		dwc3_host_exit(dwc);
		break;
	case DWC3_MODE_DRD:
		dwc3_host_exit(dwc);
		dwc3_gadget_exit(dwc);
		break;
	default:
		/* do nothing */
		break;
	}

	dwc3_core_exit(dwc);

	return 0;
}

static struct platform_driver dwc3_driver = {
	.probe		= dwc3_probe,
	.remove		= dwc3_remove,
	.driver		= {
		.name	= "dwc3",
	},
};

module_platform_driver(dwc3_driver);

MODULE_ALIAS("platform:dwc3");
MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
Commit	Line	Data
72246da4 FB	1	/**
	2	* core.c - DesignWare USB3 DRD Controller Core file
	3	*
	4	* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4 FB	5	*
	6	* Authors: Felipe Balbi <balbi@ti.com>,
	7	* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
	8	*
	9	* Redistribution and use in source and binary forms, with or without
	10	* modification, are permitted provided that the following conditions
	11	* are met:
	12	* 1. Redistributions of source code must retain the above copyright
	13	* notice, this list of conditions, and the following disclaimer,
	14	* without modification.
	15	* 2. Redistributions in binary form must reproduce the above copyright
	16	* notice, this list of conditions and the following disclaimer in the
	17	* documentation and/or other materials provided with the distribution.
	18	* 3. The names of the above-listed copyright holders may not be used
	19	* to endorse or promote products derived from this software without
	20	* specific prior written permission.
	21	*
	22	* ALTERNATIVELY, this software may be distributed under the terms of the
	23	* GNU General Public License ("GPL") version 2, as published by the Free
	24	* Software Foundation.
	25	*
	26	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
	27	* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
	28	* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
	29	* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
	30	* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
	31	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
	32	* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
	33	* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
	34	* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
	35	* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	36	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	37	*/
	38
a72e658b	39	#include <linux/module.h>
72246da4 FB	40	#include <linux/kernel.h>
	41	#include <linux/slab.h>
	42	#include <linux/spinlock.h>
	43	#include <linux/platform_device.h>
	44	#include <linux/pm_runtime.h>
	45	#include <linux/interrupt.h>
	46	#include <linux/ioport.h>
	47	#include <linux/io.h>
	48	#include <linux/list.h>
	49	#include <linux/delay.h>
	50	#include <linux/dma-mapping.h>
457e84b6	51	#include <linux/of.h>
72246da4	52
51e1e7bc	53	#include <linux/usb/otg.h>
72246da4 FB	54	#include <linux/usb/ch9.h>
	55	#include <linux/usb/gadget.h>
	56
	57	#include "core.h"
	58	#include "gadget.h"
	59	#include "io.h"
	60
	61	#include "debug.h"
	62
6c167fc9 FB	63	static char *maximum_speed = "super";
	64	module_param(maximum_speed, charp, 0);
	65	MODULE_PARM_DESC(maximum_speed, "Maximum supported speed.");
	66
8300dd23 FB	67	/* -------------------------------------------------------------------------- */
8300dd23 FB	68
3140e8cb SAS	69	void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
	70	{
	71	u32 reg;
	72
	73	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	74	reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
	75	reg \|= DWC3_GCTL_PRTCAPDIR(mode);
	76	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
	77	}
8300dd23	78
72246da4 FB	79	/**
	80	* dwc3_core_soft_reset - Issues core soft reset and PHY reset
	81	* @dwc: pointer to our context structure
	82	*/
	83	static void dwc3_core_soft_reset(struct dwc3 *dwc)
	84	{
	85	u32 reg;
	86
	87	/* Before Resetting PHY, put Core in Reset */
	88	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	89	reg \|= DWC3_GCTL_CORESOFTRESET;
	90	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
	91
	92	/* Assert USB3 PHY reset */
	93	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
	94	reg \|= DWC3_GUSB3PIPECTL_PHYSOFTRST;
	95	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
	96
	97	/* Assert USB2 PHY reset */
	98	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
	99	reg \|= DWC3_GUSB2PHYCFG_PHYSOFTRST;
	100	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
	101
51e1e7bc FB	102	usb_phy_init(dwc->usb2_phy);
51e1e7bc FB	103	usb_phy_init(dwc->usb3_phy);
72246da4 FB	104	mdelay(100);
	105
	106	/* Clear USB3 PHY reset */
	107	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
	108	reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
	109	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
	110
	111	/* Clear USB2 PHY reset */
	112	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
	113	reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
	114	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
	115
45627ac6 PA	116	mdelay(100);
45627ac6 PA	117
72246da4 FB	118	/* After PHYs are stable we can take Core out of reset state */
	119	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	120	reg &= ~DWC3_GCTL_CORESOFTRESET;
	121	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
	122	}
	123
	124	/**
	125	* dwc3_free_one_event_buffer - Frees one event buffer
	126	* @dwc: Pointer to our controller context structure
	127	* @evt: Pointer to event buffer to be freed
	128	*/
	129	static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
	130	struct dwc3_event_buffer *evt)
	131	{
	132	dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
72246da4 FB	133	}
	134
	135	/**
1d046793	136	* dwc3_alloc_one_event_buffer - Allocates one event buffer structure
72246da4 FB	137	* @dwc: Pointer to our controller context structure
	138	* @length: size of the event buffer
	139	*
1d046793	140	* Returns a pointer to the allocated event buffer structure on success
72246da4 FB	141	* otherwise ERR_PTR(errno).
	142	*/
	143	static struct dwc3_event_buffer *__devinit
	144	dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
	145	{
	146	struct dwc3_event_buffer *evt;
	147
380f0d28	148	evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
72246da4 FB	149	if (!evt)
	150	return ERR_PTR(-ENOMEM);
	151
	152	evt->dwc = dwc;
	153	evt->length = length;
	154	evt->buf = dma_alloc_coherent(dwc->dev, length,
	155	&evt->dma, GFP_KERNEL);
e32672f0	156	if (!evt->buf)
72246da4	157	return ERR_PTR(-ENOMEM);
72246da4 FB	158
	159	return evt;
	160	}
	161
	162	/**
	163	* dwc3_free_event_buffers - frees all allocated event buffers
	164	* @dwc: Pointer to our controller context structure
	165	*/
	166	static void dwc3_free_event_buffers(struct dwc3 *dwc)
	167	{
	168	struct dwc3_event_buffer *evt;
	169	int i;
	170
9f622b2a	171	for (i = 0; i < dwc->num_event_buffers; i++) {
72246da4	172	evt = dwc->ev_buffs[i];
64b6c8a7	173	if (evt)
72246da4	174	dwc3_free_one_event_buffer(dwc, evt);
72246da4 FB	175	}
	176	}
	177
	178	/**
	179	* dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
1d046793	180	* @dwc: pointer to our controller context structure
72246da4 FB	181	* @length: size of event buffer
72246da4 FB	182	*
1d046793	183	* Returns 0 on success otherwise negative errno. In the error case, dwc
72246da4 FB	184	* may contain some buffers allocated but not all which were requested.
72246da4 FB	185	*/
9f622b2a	186	static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
72246da4	187	{
9f622b2a	188	int num;
72246da4 FB	189	int i;
72246da4 FB	190
9f622b2a FB	191	num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
	192	dwc->num_event_buffers = num;
	193
380f0d28 FB	194	dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(dwc->ev_buffs) num,
380f0d28 FB	195	GFP_KERNEL);
457d3f21 FB	196	if (!dwc->ev_buffs) {
	197	dev_err(dwc->dev, "can't allocate event buffers array\n");
	198	return -ENOMEM;
	199	}
	200
72246da4 FB	201	for (i = 0; i < num; i++) {
	202	struct dwc3_event_buffer *evt;
	203
	204	evt = dwc3_alloc_one_event_buffer(dwc, length);
	205	if (IS_ERR(evt)) {
	206	dev_err(dwc->dev, "can't allocate event buffer\n");
	207	return PTR_ERR(evt);
	208	}
	209	dwc->ev_buffs[i] = evt;
	210	}
	211
	212	return 0;
	213	}
	214
	215	/**
	216	* dwc3_event_buffers_setup - setup our allocated event buffers
1d046793	217	* @dwc: pointer to our controller context structure
72246da4 FB	218	*
	219	* Returns 0 on success otherwise negative errno.
	220	*/
7acd85e0	221	static int dwc3_event_buffers_setup(struct dwc3 *dwc)
72246da4 FB	222	{
	223	struct dwc3_event_buffer *evt;
	224	int n;
	225
9f622b2a	226	for (n = 0; n < dwc->num_event_buffers; n++) {
72246da4 FB	227	evt = dwc->ev_buffs[n];
	228	dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
	229	evt->buf, (unsigned long long) evt->dma,
	230	evt->length);
	231
7acd85e0 PZ	232	evt->lpos = 0;
7acd85e0 PZ	233
72246da4 FB	234	dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
	235	lower_32_bits(evt->dma));
	236	dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
	237	upper_32_bits(evt->dma));
	238	dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
	239	evt->length & 0xffff);
	240	dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
	241	}
	242
	243	return 0;
	244	}
	245
	246	static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
	247	{
	248	struct dwc3_event_buffer *evt;
	249	int n;
	250
9f622b2a	251	for (n = 0; n < dwc->num_event_buffers; n++) {
72246da4	252	evt = dwc->ev_buffs[n];
7acd85e0 PZ	253
	254	evt->lpos = 0;
	255
72246da4 FB	256	dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
	257	dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
	258	dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
	259	dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
	260	}
	261	}
	262
26ceca97 FB	263	static void __devinit dwc3_cache_hwparams(struct dwc3 *dwc)
	264	{
	265	struct dwc3_hwparams *parms = &dwc->hwparams;
	266
	267	parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
	268	parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
	269	parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
	270	parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
	271	parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
	272	parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
	273	parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
	274	parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
	275	parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
	276	}
	277
72246da4 FB	278	/**
	279	* dwc3_core_init - Low-level initialization of DWC3 Core
	280	* @dwc: Pointer to our controller context structure
	281	*
	282	* Returns 0 on success otherwise negative errno.
	283	*/
	284	static int __devinit dwc3_core_init(struct dwc3 *dwc)
	285	{
	286	unsigned long timeout;
	287	u32 reg;
	288	int ret;
	289
7650bd74 SAS	290	reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
	291	/* This should read as U3 followed by revision number */
	292	if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
	293	dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
	294	ret = -ENODEV;
	295	goto err0;
	296	}
248b122b	297	dwc->revision = reg;
7650bd74	298
72246da4 FB	299	/* issue device SoftReset too */
	300	timeout = jiffies + msecs_to_jiffies(500);
	301	dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
	302	do {
	303	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
	304	if (!(reg & DWC3_DCTL_CSFTRST))
	305	break;
	306
	307	if (time_after(jiffies, timeout)) {
	308	dev_err(dwc->dev, "Reset Timed Out\n");
	309	ret = -ETIMEDOUT;
	310	goto err0;
	311	}
	312
	313	cpu_relax();
	314	} while (true);
	315
58a0f23f PA	316	dwc3_core_soft_reset(dwc);
58a0f23f PA	317
4878a028	318	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
3e87c42a	319	reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
4878a028 SAS	320	reg &= ~DWC3_GCTL_DISSCRAMBLE;
4878a028 SAS	321
164d7731	322	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
4878a028 SAS	323	case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
	324	reg &= ~DWC3_GCTL_DSBLCLKGTNG;
	325	break;
	326	default:
	327	dev_dbg(dwc->dev, "No power optimization available\n");
	328	}
	329
	330	/*
	331	* WORKAROUND: DWC3 revisions <1.90a have a bug
1d046793	332	* where the device can fail to connect at SuperSpeed
4878a028	333	* and falls back to high-speed mode which causes
1d046793	334	* the device to enter a Connect/Disconnect loop
4878a028 SAS	335	*/
	336	if (dwc->revision < DWC3_REVISION_190A)
	337	reg \|= DWC3_GCTL_U2RSTECN;
	338
	339	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
	340
72246da4 FB	341	ret = dwc3_event_buffers_setup(dwc);
	342	if (ret) {
	343	dev_err(dwc->dev, "failed to setup event buffers\n");
3921426b	344	goto err0;
72246da4 FB	345	}
	346
	347	return 0;
	348
72246da4 FB	349	err0:
	350	return ret;
	351	}
	352
	353	static void dwc3_core_exit(struct dwc3 *dwc)
	354	{
	355	dwc3_event_buffers_cleanup(dwc);
01b8daf7 VG	356
	357	usb_phy_shutdown(dwc->usb2_phy);
	358	usb_phy_shutdown(dwc->usb3_phy);
72246da4 FB	359	}
	360
	361	#define DWC3_ALIGN_MASK (16 - 1)
	362
	363	static int __devinit dwc3_probe(struct platform_device *pdev)
	364	{
457e84b6	365	struct device_node *node = pdev->dev.of_node;
72246da4 FB	366	struct resource *res;
72246da4 FB	367	struct dwc3 *dwc;
802ca850	368	struct device *dev = &pdev->dev;
0949e99b	369
72246da4	370	int ret = -ENOMEM;
0949e99b FB	371
0949e99b FB	372	void __iomem *regs;
72246da4 FB	373	void *mem;
72246da4 FB	374
0949e99b FB	375	u8 mode;
0949e99b FB	376
802ca850	377	mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
72246da4	378	if (!mem) {
802ca850 CP	379	dev_err(dev, "not enough memory\n");
802ca850 CP	380	return -ENOMEM;
72246da4 FB	381	}
	382	dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
	383	dwc->mem = mem;
	384
51249dca	385	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
72246da4	386	if (!res) {
51249dca	387	dev_err(dev, "missing IRQ\n");
802ca850	388	return -ENODEV;
72246da4	389	}
066618bc KVA	390	dwc->xhci_resources[1].start = res->start;
	391	dwc->xhci_resources[1].end = res->end;
	392	dwc->xhci_resources[1].flags = res->flags;
	393	dwc->xhci_resources[1].name = res->name;
72246da4	394
51249dca IS	395	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	396	if (!res) {
	397	dev_err(dev, "missing memory resource\n");
	398	return -ENODEV;
	399	}
066618bc	400	dwc->xhci_resources[0].start = res->start;
51249dca IS	401	dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
51249dca IS	402	DWC3_XHCI_REGS_END;
066618bc KVA	403	dwc->xhci_resources[0].flags = res->flags;
066618bc KVA	404	dwc->xhci_resources[0].name = res->name;
51249dca IS	405
	406	/*
	407	* Request memory region but exclude xHCI regs,
	408	* since it will be requested by the xhci-plat driver.
	409	*/
	410	res = devm_request_mem_region(dev, res->start + DWC3_GLOBALS_REGS_START,
	411	resource_size(res) - DWC3_GLOBALS_REGS_START,
802ca850	412	dev_name(dev));
72246da4	413	if (!res) {
802ca850 CP	414	dev_err(dev, "can't request mem region\n");
802ca850 CP	415	return -ENOMEM;
72246da4 FB	416	}
72246da4 FB	417
b7e38aa6	418	regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
72246da4	419	if (!regs) {
802ca850 CP	420	dev_err(dev, "ioremap failed\n");
802ca850 CP	421	return -ENOMEM;
72246da4 FB	422	}
72246da4 FB	423
51e1e7bc FB	424	dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
	425	if (IS_ERR_OR_NULL(dwc->usb2_phy)) {
	426	dev_err(dev, "no usb2 phy configured\n");
	427	return -EPROBE_DEFER;
	428	}
	429
	430	dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
	431	if (IS_ERR_OR_NULL(dwc->usb3_phy)) {
	432	dev_err(dev, "no usb3 phy configured\n");
	433	return -EPROBE_DEFER;
	434	}
	435
72246da4 FB	436	spin_lock_init(&dwc->lock);
	437	platform_set_drvdata(pdev, dwc);
	438
	439	dwc->regs = regs;
	440	dwc->regs_size = resource_size(res);
802ca850	441	dwc->dev = dev;
72246da4	442
6c167fc9 FB	443	if (!strncmp("super", maximum_speed, 5))
	444	dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
	445	else if (!strncmp("high", maximum_speed, 4))
	446	dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;
	447	else if (!strncmp("full", maximum_speed, 4))
	448	dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;
	449	else if (!strncmp("low", maximum_speed, 3))
	450	dwc->maximum_speed = DWC3_DCFG_LOWSPEED;
	451	else
	452	dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
	453
457e84b6 FB	454	if (of_get_property(node, "tx-fifo-resize", NULL))
	455	dwc->needs_fifo_resize = true;
	456
802ca850 CP	457	pm_runtime_enable(dev);
	458	pm_runtime_get_sync(dev);
	459	pm_runtime_forbid(dev);
72246da4	460
4fd24483 KVA	461	dwc3_cache_hwparams(dwc);
4fd24483 KVA	462
3921426b FB	463	ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
	464	if (ret) {
	465	dev_err(dwc->dev, "failed to allocate event buffers\n");
	466	ret = -ENOMEM;
	467	goto err0;
	468	}
	469
72246da4 FB	470	ret = dwc3_core_init(dwc);
72246da4 FB	471	if (ret) {
802ca850	472	dev_err(dev, "failed to initialize core\n");
3921426b	473	goto err0;
72246da4 FB	474	}
72246da4 FB	475
0949e99b FB	476	mode = DWC3_MODE(dwc->hwparams.hwparams0);
	477
	478	switch (mode) {
0949e99b	479	case DWC3_MODE_DEVICE:
3140e8cb	480	dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
72246da4 FB	481	ret = dwc3_gadget_init(dwc);
72246da4 FB	482	if (ret) {
802ca850 CP	483	dev_err(dev, "failed to initialize gadget\n");
802ca850 CP	484	goto err1;
72246da4	485	}
d07e8819 FB	486	break;
d07e8819 FB	487	case DWC3_MODE_HOST:
3140e8cb	488	dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
d07e8819 FB	489	ret = dwc3_host_init(dwc);
d07e8819 FB	490	if (ret) {
802ca850 CP	491	dev_err(dev, "failed to initialize host\n");
802ca850 CP	492	goto err1;
d07e8819 FB	493	}
	494	break;
	495	case DWC3_MODE_DRD:
3140e8cb	496	dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
d07e8819 FB	497	ret = dwc3_host_init(dwc);
d07e8819 FB	498	if (ret) {
802ca850 CP	499	dev_err(dev, "failed to initialize host\n");
802ca850 CP	500	goto err1;
d07e8819 FB	501	}
d07e8819 FB	502
72246da4 FB	503	ret = dwc3_gadget_init(dwc);
72246da4 FB	504	if (ret) {
802ca850 CP	505	dev_err(dev, "failed to initialize gadget\n");
802ca850 CP	506	goto err1;
72246da4	507	}
0949e99b FB	508	break;
0949e99b FB	509	default:
802ca850 CP	510	dev_err(dev, "Unsupported mode of operation %d\n", mode);
802ca850 CP	511	goto err1;
72246da4	512	}
0949e99b	513	dwc->mode = mode;
72246da4 FB	514
	515	ret = dwc3_debugfs_init(dwc);
	516	if (ret) {
802ca850 CP	517	dev_err(dev, "failed to initialize debugfs\n");
802ca850 CP	518	goto err2;
72246da4 FB	519	}
72246da4 FB	520
802ca850	521	pm_runtime_allow(dev);
72246da4 FB	522
	523	return 0;
	524
802ca850	525	err2:
0949e99b	526	switch (mode) {
0949e99b	527	case DWC3_MODE_DEVICE:
72246da4	528	dwc3_gadget_exit(dwc);
0949e99b	529	break;
d07e8819 FB	530	case DWC3_MODE_HOST:
	531	dwc3_host_exit(dwc);
	532	break;
	533	case DWC3_MODE_DRD:
	534	dwc3_host_exit(dwc);
72246da4	535	dwc3_gadget_exit(dwc);
d07e8819	536	break;
0949e99b FB	537	default:
	538	/* do nothing */
	539	break;
	540	}
72246da4	541
72246da4	542	err1:
802ca850	543	dwc3_core_exit(dwc);
72246da4	544
3921426b FB	545	err0:
	546	dwc3_free_event_buffers(dwc);
	547
72246da4 FB	548	return ret;
	549	}
	550
	551	static int __devexit dwc3_remove(struct platform_device *pdev)
	552	{
72246da4 FB	553	struct dwc3 *dwc = platform_get_drvdata(pdev);
72246da4 FB	554	struct resource *res;
72246da4 FB	555
	556	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	557
	558	pm_runtime_put(&pdev->dev);
	559	pm_runtime_disable(&pdev->dev);
	560
	561	dwc3_debugfs_exit(dwc);
	562
0949e99b	563	switch (dwc->mode) {
0949e99b	564	case DWC3_MODE_DEVICE:
72246da4	565	dwc3_gadget_exit(dwc);
0949e99b	566	break;
d07e8819 FB	567	case DWC3_MODE_HOST:
	568	dwc3_host_exit(dwc);
	569	break;
	570	case DWC3_MODE_DRD:
	571	dwc3_host_exit(dwc);
72246da4	572	dwc3_gadget_exit(dwc);
d07e8819	573	break;
0949e99b FB	574	default:
	575	/* do nothing */
	576	break;
	577	}
72246da4 FB	578
72246da4 FB	579	dwc3_core_exit(dwc);
72246da4 FB	580
	581	return 0;
	582	}
	583
72246da4 FB	584	static struct platform_driver dwc3_driver = {
72246da4 FB	585	.probe = dwc3_probe,
7690417d	586	.remove = dwc3_remove,
72246da4 FB	587	.driver = {
	588	.name = "dwc3",
	589	},
72246da4 FB	590	};
72246da4 FB	591
b1116dcc TK	592	module_platform_driver(dwc3_driver);
b1116dcc TK	593
7ae4fc4d	594	MODULE_ALIAS("platform:dwc3");
72246da4 FB	595	MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
	596	MODULE_LICENSE("Dual BSD/GPL");
	597	MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");