[deliverable/linux.git] / drivers / usb / dwc3 / core.c

/**
 * core.c - DesignWare USB3 DRD Controller Core file
 *
 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
 *
 * Authors: Felipe Balbi <balbi@ti.com>,
 *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions, and the following disclaimer,
 *    without modification.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. The names of the above-listed copyright holders may not be used
 *    to endorse or promote products derived from this software without
 *    specific prior written permission.
 *
 * ALTERNATIVELY, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") version 2, as published by the Free
 * Software Foundation.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/list.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>

#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <linux/module.h>

#include "core.h"
#include "gadget.h"
#include "io.h"

#include "debug.h"

static char *maximum_speed = "super";
module_param(maximum_speed, charp, 0);
MODULE_PARM_DESC(maximum_speed, "Maximum supported speed.");

/**
 * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 * @dwc: pointer to our context structure
 */
static void dwc3_core_soft_reset(struct dwc3 *dwc)
{
	u32		reg;

	/* Before Resetting PHY, put Core in Reset */
	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	reg |= DWC3_GCTL_CORESOFTRESET;
	dwc3_writel(dwc->regs, DWC3_GCTL, reg);

	/* Assert USB3 PHY reset */
	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
	reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);

	/* Assert USB2 PHY reset */
	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
	reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);

	mdelay(100);

	/* Clear USB3 PHY reset */
	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
	reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);

	/* Clear USB2 PHY reset */
	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
	reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);

	/* After PHYs are stable we can take Core out of reset state */
	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	reg &= ~DWC3_GCTL_CORESOFTRESET;
	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
}

/**
 * dwc3_free_one_event_buffer - Frees one event buffer
 * @dwc: Pointer to our controller context structure
 * @evt: Pointer to event buffer to be freed
 */
static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
		struct dwc3_event_buffer *evt)
{
	dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
	kfree(evt);
}

/**
 * dwc3_alloc_one_event_buffer - Allocated one event buffer structure
 * @dwc: Pointer to our controller context structure
 * @length: size of the event buffer
 *
 * Returns a pointer to the allocated event buffer structure on succes
 * otherwise ERR_PTR(errno).
 */
static struct dwc3_event_buffer *__devinit
dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
{
	struct dwc3_event_buffer	*evt;

	evt = kzalloc(sizeof(*evt), GFP_KERNEL);
	if (!evt)
		return ERR_PTR(-ENOMEM);

	evt->dwc	= dwc;
	evt->length	= length;
	evt->buf	= dma_alloc_coherent(dwc->dev, length,
			&evt->dma, GFP_KERNEL);
	if (!evt->buf) {
		kfree(evt);
		return ERR_PTR(-ENOMEM);
	}

	return evt;
}

/**
 * dwc3_free_event_buffers - frees all allocated event buffers
 * @dwc: Pointer to our controller context structure
 */
static void dwc3_free_event_buffers(struct dwc3 *dwc)
{
	struct dwc3_event_buffer	*evt;
	int i;

	for (i = 0; i < dwc->num_event_buffers; i++) {
		evt = dwc->ev_buffs[i];
		if (evt) {
			dwc3_free_one_event_buffer(dwc, evt);
			dwc->ev_buffs[i] = NULL;
		}
	}
}

/**
 * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 * @dwc: Pointer to out controller context structure
 * @length: size of event buffer
 *
 * Returns 0 on success otherwise negative errno. In error the case, dwc
 * may contain some buffers allocated but not all which were requested.
 */
static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
{
	int			num;
	int			i;

	num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
	dwc->num_event_buffers = num;

	for (i = 0; i < num; i++) {
		struct dwc3_event_buffer	*evt;

		evt = dwc3_alloc_one_event_buffer(dwc, length);
		if (IS_ERR(evt)) {
			dev_err(dwc->dev, "can't allocate event buffer\n");
			return PTR_ERR(evt);
		}
		dwc->ev_buffs[i] = evt;
	}

	return 0;
}

/**
 * dwc3_event_buffers_setup - setup our allocated event buffers
 * @dwc: Pointer to out controller context structure
 *
 * Returns 0 on success otherwise negative errno.
 */
static int __devinit dwc3_event_buffers_setup(struct dwc3 *dwc)
{
	struct dwc3_event_buffer	*evt;
	int				n;

	for (n = 0; n < dwc->num_event_buffers; n++) {
		evt = dwc->ev_buffs[n];
		dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
				evt->buf, (unsigned long long) evt->dma,
				evt->length);

		dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
				lower_32_bits(evt->dma));
		dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
				upper_32_bits(evt->dma));
		dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
				evt->length & 0xffff);
		dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
	}

	return 0;
}

static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
{
	struct dwc3_event_buffer	*evt;
	int				n;

	for (n = 0; n < dwc->num_event_buffers; n++) {
		evt = dwc->ev_buffs[n];
		dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
		dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
		dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
		dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
	}
}

static void __devinit dwc3_cache_hwparams(struct dwc3 *dwc)
{
	struct dwc3_hwparams	*parms = &dwc->hwparams;

	parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
	parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
	parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
	parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
	parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
	parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
	parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
	parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
	parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
}

/**
 * dwc3_core_init - Low-level initialization of DWC3 Core
 * @dwc: Pointer to our controller context structure
 *
 * Returns 0 on success otherwise negative errno.
 */
static int __devinit dwc3_core_init(struct dwc3 *dwc)
{
	unsigned long		timeout;
	u32			reg;
	int			ret;

	reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
	/* This should read as U3 followed by revision number */
	if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
		dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
		ret = -ENODEV;
		goto err0;
	}
	dwc->revision = reg & DWC3_GSNPSREV_MASK;

	dwc3_core_soft_reset(dwc);

	/* issue device SoftReset too */
	timeout = jiffies + msecs_to_jiffies(500);
	dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
	do {
		reg = dwc3_readl(dwc->regs, DWC3_DCTL);
		if (!(reg & DWC3_DCTL_CSFTRST))
			break;

		if (time_after(jiffies, timeout)) {
			dev_err(dwc->dev, "Reset Timed Out\n");
			ret = -ETIMEDOUT;
			goto err0;
		}

		cpu_relax();
	} while (true);

	dwc3_cache_hwparams(dwc);

	ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
	if (ret) {
		dev_err(dwc->dev, "failed to allocate event buffers\n");
		ret = -ENOMEM;
		goto err1;
	}

	ret = dwc3_event_buffers_setup(dwc);
	if (ret) {
		dev_err(dwc->dev, "failed to setup event buffers\n");
		goto err1;
	}

	return 0;

err1:
	dwc3_free_event_buffers(dwc);

err0:
	return ret;
}

static void dwc3_core_exit(struct dwc3 *dwc)
{
	dwc3_event_buffers_cleanup(dwc);
	dwc3_free_event_buffers(dwc);
}

#define DWC3_ALIGN_MASK		(16 - 1)

static int __devinit dwc3_probe(struct platform_device *pdev)
{
	struct resource		*res;
	struct dwc3		*dwc;

	int			ret = -ENOMEM;
	int			irq;

	void __iomem		*regs;
	void			*mem;

	u8			mode;

	mem = kzalloc(sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
	if (!mem) {
		dev_err(&pdev->dev, "not enough memory\n");
		goto err0;
	}
	dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
	dwc->mem = mem;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&pdev->dev, "missing resource\n");
		goto err1;
	}

	dwc->res = res;

	res = request_mem_region(res->start, resource_size(res),
			dev_name(&pdev->dev));
	if (!res) {
		dev_err(&pdev->dev, "can't request mem region\n");
		goto err1;
	}

	regs = ioremap(res->start, resource_size(res));
	if (!regs) {
		dev_err(&pdev->dev, "ioremap failed\n");
		goto err2;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(&pdev->dev, "missing IRQ\n");
		goto err3;
	}

	spin_lock_init(&dwc->lock);
	platform_set_drvdata(pdev, dwc);

	dwc->regs	= regs;
	dwc->regs_size	= resource_size(res);
	dwc->dev	= &pdev->dev;
	dwc->irq	= irq;

	if (!strncmp("super", maximum_speed, 5))
		dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
	else if (!strncmp("high", maximum_speed, 4))
		dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;
	else if (!strncmp("full", maximum_speed, 4))
		dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;
	else if (!strncmp("low", maximum_speed, 3))
		dwc->maximum_speed = DWC3_DCFG_LOWSPEED;
	else
		dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;

	pm_runtime_enable(&pdev->dev);
	pm_runtime_get_sync(&pdev->dev);
	pm_runtime_forbid(&pdev->dev);

	ret = dwc3_core_init(dwc);
	if (ret) {
		dev_err(&pdev->dev, "failed to initialize core\n");
		goto err3;
	}

	mode = DWC3_MODE(dwc->hwparams.hwparams0);

	switch (mode) {
	case DWC3_MODE_DEVICE:
		ret = dwc3_gadget_init(dwc);
		if (ret) {
			dev_err(&pdev->dev, "failed to initialize gadget\n");
			goto err4;
		}
		break;
	case DWC3_MODE_HOST:
		ret = dwc3_host_init(dwc);
		if (ret) {
			dev_err(&pdev->dev, "failed to initialize host\n");
			goto err4;
		}
		break;
	case DWC3_MODE_DRD:
		ret = dwc3_host_init(dwc);
		if (ret) {
			dev_err(&pdev->dev, "failed to initialize host\n");
			goto err4;
		}

		ret = dwc3_gadget_init(dwc);
		if (ret) {
			dev_err(&pdev->dev, "failed to initialize gadget\n");
			goto err4;
		}
		break;
	default:
		dev_err(&pdev->dev, "Unsupported mode of operation %d\n", mode);
		goto err4;
	}
	dwc->mode = mode;

	ret = dwc3_debugfs_init(dwc);
	if (ret) {
		dev_err(&pdev->dev, "failed to initialize debugfs\n");
		goto err5;
	}

	pm_runtime_allow(&pdev->dev);

	return 0;

err5:
	switch (mode) {
	case DWC3_MODE_DEVICE:
		dwc3_gadget_exit(dwc);
		break;
	case DWC3_MODE_HOST:
		dwc3_host_exit(dwc);
		break;
	case DWC3_MODE_DRD:
		dwc3_host_exit(dwc);
		dwc3_gadget_exit(dwc);
		break;
	default:
		/* do nothing */
		break;
	}

err4:
	dwc3_core_exit(dwc);

err3:
	iounmap(regs);

err2:
	release_mem_region(res->start, resource_size(res));

err1:
	kfree(dwc->mem);

err0:
	return ret;
}

static int __devexit dwc3_remove(struct platform_device *pdev)
{
	struct dwc3	*dwc = platform_get_drvdata(pdev);
	struct resource	*res;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	pm_runtime_put(&pdev->dev);
	pm_runtime_disable(&pdev->dev);

	dwc3_debugfs_exit(dwc);

	switch (dwc->mode) {
	case DWC3_MODE_DEVICE:
		dwc3_gadget_exit(dwc);
		break;
	case DWC3_MODE_HOST:
		dwc3_host_exit(dwc);
		break;
	case DWC3_MODE_DRD:
		dwc3_host_exit(dwc);
		dwc3_gadget_exit(dwc);
		break;
	default:
		/* do nothing */
		break;
	}

	dwc3_core_exit(dwc);
	release_mem_region(res->start, resource_size(res));
	iounmap(dwc->regs);
	kfree(dwc->mem);

	return 0;
}

static struct platform_driver dwc3_driver = {
	.probe		= dwc3_probe,
	.remove		= __devexit_p(dwc3_remove),
	.driver		= {
		.name	= "dwc3",
	},
};

MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
MODULE_LICENSE("Dual BSD/GPL");
MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");

static int __devinit dwc3_init(void)
{
	return platform_driver_register(&dwc3_driver);
}
module_init(dwc3_init);

static void __exit dwc3_exit(void)
{
	platform_driver_unregister(&dwc3_driver);
}
module_exit(dwc3_exit);
Commit	Line	Data
72246da4 FB	1	/**
	2	* core.c - DesignWare USB3 DRD Controller Core file
	3	*
	4	* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4 FB	5	*
	6	* Authors: Felipe Balbi <balbi@ti.com>,
	7	* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
	8	*
	9	* Redistribution and use in source and binary forms, with or without
	10	* modification, are permitted provided that the following conditions
	11	* are met:
	12	* 1. Redistributions of source code must retain the above copyright
	13	* notice, this list of conditions, and the following disclaimer,
	14	* without modification.
	15	* 2. Redistributions in binary form must reproduce the above copyright
	16	* notice, this list of conditions and the following disclaimer in the
	17	* documentation and/or other materials provided with the distribution.
	18	* 3. The names of the above-listed copyright holders may not be used
	19	* to endorse or promote products derived from this software without
	20	* specific prior written permission.
	21	*
	22	* ALTERNATIVELY, this software may be distributed under the terms of the
	23	* GNU General Public License ("GPL") version 2, as published by the Free
	24	* Software Foundation.
	25	*
	26	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
	27	* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
	28	* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
	29	* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
	30	* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
	31	* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
	32	* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
	33	* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
	34	* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
	35	* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	36	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	37	*/
	38
a72e658b	39	#include <linux/module.h>
72246da4 FB	40	#include <linux/kernel.h>
	41	#include <linux/slab.h>
	42	#include <linux/spinlock.h>
	43	#include <linux/platform_device.h>
	44	#include <linux/pm_runtime.h>
	45	#include <linux/interrupt.h>
	46	#include <linux/ioport.h>
	47	#include <linux/io.h>
	48	#include <linux/list.h>
	49	#include <linux/delay.h>
	50	#include <linux/dma-mapping.h>
	51
	52	#include <linux/usb/ch9.h>
	53	#include <linux/usb/gadget.h>
2204fdee	54	#include <linux/module.h>
72246da4 FB	55
	56	#include "core.h"
	57	#include "gadget.h"
	58	#include "io.h"
	59
	60	#include "debug.h"
	61
6c167fc9 FB	62	static char *maximum_speed = "super";
	63	module_param(maximum_speed, charp, 0);
	64	MODULE_PARM_DESC(maximum_speed, "Maximum supported speed.");
	65
72246da4 FB	66	/**
	67	* dwc3_core_soft_reset - Issues core soft reset and PHY reset
	68	* @dwc: pointer to our context structure
	69	*/
	70	static void dwc3_core_soft_reset(struct dwc3 *dwc)
	71	{
	72	u32 reg;
	73
	74	/* Before Resetting PHY, put Core in Reset */
	75	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	76	reg \|= DWC3_GCTL_CORESOFTRESET;
	77	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
	78
	79	/* Assert USB3 PHY reset */
	80	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
	81	reg \|= DWC3_GUSB3PIPECTL_PHYSOFTRST;
	82	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
	83
	84	/* Assert USB2 PHY reset */
	85	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
	86	reg \|= DWC3_GUSB2PHYCFG_PHYSOFTRST;
	87	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
	88
	89	mdelay(100);
	90
	91	/* Clear USB3 PHY reset */
	92	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
	93	reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
	94	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
	95
	96	/* Clear USB2 PHY reset */
	97	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
	98	reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
	99	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
	100
	101	/* After PHYs are stable we can take Core out of reset state */
	102	reg = dwc3_readl(dwc->regs, DWC3_GCTL);
	103	reg &= ~DWC3_GCTL_CORESOFTRESET;
	104	dwc3_writel(dwc->regs, DWC3_GCTL, reg);
	105	}
	106
	107	/**
	108	* dwc3_free_one_event_buffer - Frees one event buffer
	109	* @dwc: Pointer to our controller context structure
	110	* @evt: Pointer to event buffer to be freed
	111	*/
	112	static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
	113	struct dwc3_event_buffer *evt)
	114	{
	115	dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
	116	kfree(evt);
	117	}
	118
	119	/**
	120	* dwc3_alloc_one_event_buffer - Allocated one event buffer structure
	121	* @dwc: Pointer to our controller context structure
	122	* @length: size of the event buffer
	123	*
	124	* Returns a pointer to the allocated event buffer structure on succes
	125	* otherwise ERR_PTR(errno).
	126	*/
	127	static struct dwc3_event_buffer *__devinit
	128	dwc3_alloc_one_event_buffer(struct dwc3 *dwc, unsigned length)
	129	{
130	struct dwc3_event_buffer *evt;
131
132	evt = kzalloc(sizeof(*evt), GFP_KERNEL);
133	if (!evt)
134	return ERR_PTR(-ENOMEM);
135
136	evt->dwc = dwc;
137	evt->length = length;
138	evt->buf = dma_alloc_coherent(dwc->dev, length,
139	&evt->dma, GFP_KERNEL);
140	if (!evt->buf) {
141	kfree(evt);
142	return ERR_PTR(-ENOMEM);
143	}
144
145	return evt;
146	}
147
148	/**
149	* dwc3_free_event_buffers - frees all allocated event buffers
150	* @dwc: Pointer to our controller context structure
151	*/
152	static void dwc3_free_event_buffers(struct dwc3 *dwc)
153	{
154	struct dwc3_event_buffer *evt;
155	int i;
156
9f622b2a	157	for (i = 0; i < dwc->num_event_buffers; i++) {
72246da4 FB	158	evt = dwc->ev_buffs[i];
	159	if (evt) {
	160	dwc3_free_one_event_buffer(dwc, evt);
	161	dwc->ev_buffs[i] = NULL;
	162	}
	163	}
	164	}
	165
	166	/**
	167	* dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
	168	* @dwc: Pointer to out controller context structure
72246da4 FB	169	* @length: size of event buffer
	170	*
	171	* Returns 0 on success otherwise negative errno. In error the case, dwc
	172	* may contain some buffers allocated but not all which were requested.
	173	*/
9f622b2a	174	static int __devinit dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
72246da4	175	{
9f622b2a	176	int num;
72246da4 FB	177	int i;
72246da4 FB	178
9f622b2a FB	179	num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
	180	dwc->num_event_buffers = num;
	181
72246da4 FB	182	for (i = 0; i < num; i++) {
	183	struct dwc3_event_buffer *evt;
	184
	185	evt = dwc3_alloc_one_event_buffer(dwc, length);
	186	if (IS_ERR(evt)) {
	187	dev_err(dwc->dev, "can't allocate event buffer\n");
	188	return PTR_ERR(evt);
	189	}
	190	dwc->ev_buffs[i] = evt;
	191	}
	192
	193	return 0;
	194	}
	195
	196	/**
	197	* dwc3_event_buffers_setup - setup our allocated event buffers
	198	* @dwc: Pointer to out controller context structure
	199	*
	200	* Returns 0 on success otherwise negative errno.
	201	*/
	202	static int __devinit dwc3_event_buffers_setup(struct dwc3 *dwc)
	203	{
	204	struct dwc3_event_buffer *evt;
	205	int n;
	206
9f622b2a	207	for (n = 0; n < dwc->num_event_buffers; n++) {
72246da4 FB	208	evt = dwc->ev_buffs[n];
	209	dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
	210	evt->buf, (unsigned long long) evt->dma,
	211	evt->length);
	212
	213	dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
	214	lower_32_bits(evt->dma));
	215	dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
	216	upper_32_bits(evt->dma));
	217	dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
	218	evt->length & 0xffff);
	219	dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
	220	}
	221
	222	return 0;
	223	}
	224
	225	static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
	226	{
	227	struct dwc3_event_buffer *evt;
	228	int n;
	229
9f622b2a	230	for (n = 0; n < dwc->num_event_buffers; n++) {
72246da4 FB	231	evt = dwc->ev_buffs[n];
	232	dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
	233	dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
	234	dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), 0);
	235	dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
	236	}
	237	}
	238
26ceca97 FB	239	static void __devinit dwc3_cache_hwparams(struct dwc3 *dwc)
	240	{
	241	struct dwc3_hwparams *parms = &dwc->hwparams;
	242
	243	parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
	244	parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
	245	parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
	246	parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
	247	parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
	248	parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
	249	parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
	250	parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
	251	parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
	252	}
	253
72246da4 FB	254	/**
	255	* dwc3_core_init - Low-level initialization of DWC3 Core
	256	* @dwc: Pointer to our controller context structure
	257	*
	258	* Returns 0 on success otherwise negative errno.
	259	*/
	260	static int __devinit dwc3_core_init(struct dwc3 *dwc)
	261	{
	262	unsigned long timeout;
	263	u32 reg;
	264	int ret;
	265
7650bd74 SAS	266	reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
	267	/* This should read as U3 followed by revision number */
	268	if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
	269	dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
	270	ret = -ENODEV;
	271	goto err0;
	272	}
	273	dwc->revision = reg & DWC3_GSNPSREV_MASK;
	274
72246da4 FB	275	dwc3_core_soft_reset(dwc);
	276
	277	/* issue device SoftReset too */
	278	timeout = jiffies + msecs_to_jiffies(500);
	279	dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
	280	do {
	281	reg = dwc3_readl(dwc->regs, DWC3_DCTL);
	282	if (!(reg & DWC3_DCTL_CSFTRST))
	283	break;
	284
	285	if (time_after(jiffies, timeout)) {
	286	dev_err(dwc->dev, "Reset Timed Out\n");
	287	ret = -ETIMEDOUT;
	288	goto err0;
	289	}
	290
	291	cpu_relax();
	292	} while (true);
	293
9f622b2a FB	294	dwc3_cache_hwparams(dwc);
	295
	296	ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
72246da4 FB	297	if (ret) {
	298	dev_err(dwc->dev, "failed to allocate event buffers\n");
	299	ret = -ENOMEM;
	300	goto err1;
	301	}
	302
	303	ret = dwc3_event_buffers_setup(dwc);
	304	if (ret) {
	305	dev_err(dwc->dev, "failed to setup event buffers\n");
	306	goto err1;
	307	}
	308
	309	return 0;
	310
	311	err1:
	312	dwc3_free_event_buffers(dwc);
	313
	314	err0:
	315	return ret;
	316	}
	317
	318	static void dwc3_core_exit(struct dwc3 *dwc)
	319	{
	320	dwc3_event_buffers_cleanup(dwc);
	321	dwc3_free_event_buffers(dwc);
	322	}
	323
	324	#define DWC3_ALIGN_MASK (16 - 1)
	325
	326	static int __devinit dwc3_probe(struct platform_device *pdev)
	327	{
72246da4 FB	328	struct resource *res;
72246da4 FB	329	struct dwc3 *dwc;
0949e99b	330
72246da4 FB	331	int ret = -ENOMEM;
72246da4 FB	332	int irq;
0949e99b FB	333
0949e99b FB	334	void __iomem *regs;
72246da4 FB	335	void *mem;
72246da4 FB	336
0949e99b FB	337	u8 mode;
0949e99b FB	338
72246da4 FB	339	mem = kzalloc(sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
	340	if (!mem) {
	341	dev_err(&pdev->dev, "not enough memory\n");
	342	goto err0;
	343	}
	344	dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
	345	dwc->mem = mem;
	346
	347	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	348	if (!res) {
	349	dev_err(&pdev->dev, "missing resource\n");
	350	goto err1;
	351	}
	352
d07e8819 FB	353	dwc->res = res;
d07e8819 FB	354
72246da4 FB	355	res = request_mem_region(res->start, resource_size(res),
	356	dev_name(&pdev->dev));
	357	if (!res) {
	358	dev_err(&pdev->dev, "can't request mem region\n");
	359	goto err1;
	360	}
	361
	362	regs = ioremap(res->start, resource_size(res));
	363	if (!regs) {
	364	dev_err(&pdev->dev, "ioremap failed\n");
	365	goto err2;
	366	}
	367
	368	irq = platform_get_irq(pdev, 0);
	369	if (irq < 0) {
	370	dev_err(&pdev->dev, "missing IRQ\n");
	371	goto err3;
	372	}
	373
	374	spin_lock_init(&dwc->lock);
	375	platform_set_drvdata(pdev, dwc);
	376
	377	dwc->regs = regs;
	378	dwc->regs_size = resource_size(res);
	379	dwc->dev = &pdev->dev;
	380	dwc->irq = irq;
	381
6c167fc9 FB	382	if (!strncmp("super", maximum_speed, 5))
	383	dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
	384	else if (!strncmp("high", maximum_speed, 4))
	385	dwc->maximum_speed = DWC3_DCFG_HIGHSPEED;
	386	else if (!strncmp("full", maximum_speed, 4))
	387	dwc->maximum_speed = DWC3_DCFG_FULLSPEED1;
	388	else if (!strncmp("low", maximum_speed, 3))
	389	dwc->maximum_speed = DWC3_DCFG_LOWSPEED;
	390	else
	391	dwc->maximum_speed = DWC3_DCFG_SUPERSPEED;
	392
72246da4 FB	393	pm_runtime_enable(&pdev->dev);
	394	pm_runtime_get_sync(&pdev->dev);
	395	pm_runtime_forbid(&pdev->dev);
	396
	397	ret = dwc3_core_init(dwc);
	398	if (ret) {
	399	dev_err(&pdev->dev, "failed to initialize core\n");
	400	goto err3;
	401	}
	402
0949e99b FB	403	mode = DWC3_MODE(dwc->hwparams.hwparams0);
	404
	405	switch (mode) {
0949e99b	406	case DWC3_MODE_DEVICE:
d07e8819 FB	407	ret = dwc3_gadget_init(dwc);
	408	if (ret) {
	409	dev_err(&pdev->dev, "failed to initialize gadget\n");
	410	goto err4;
	411	}
	412	break;
	413	case DWC3_MODE_HOST:
	414	ret = dwc3_host_init(dwc);
	415	if (ret) {
	416	dev_err(&pdev->dev, "failed to initialize host\n");
	417	goto err4;
	418	}
	419	break;
	420	case DWC3_MODE_DRD:
	421	ret = dwc3_host_init(dwc);
	422	if (ret) {
	423	dev_err(&pdev->dev, "failed to initialize host\n");
	424	goto err4;
	425	}
	426
72246da4 FB	427	ret = dwc3_gadget_init(dwc);
72246da4 FB	428	if (ret) {
0949e99b	429	dev_err(&pdev->dev, "failed to initialize gadget\n");
72246da4 FB	430	goto err4;
72246da4 FB	431	}
0949e99b FB	432	break;
	433	default:
	434	dev_err(&pdev->dev, "Unsupported mode of operation %d\n", mode);
	435	goto err4;
72246da4	436	}
0949e99b	437	dwc->mode = mode;
72246da4 FB	438
	439	ret = dwc3_debugfs_init(dwc);
	440	if (ret) {
	441	dev_err(&pdev->dev, "failed to initialize debugfs\n");
	442	goto err5;
	443	}
	444
	445	pm_runtime_allow(&pdev->dev);
	446
	447	return 0;
	448
	449	err5:
0949e99b	450	switch (mode) {
0949e99b	451	case DWC3_MODE_DEVICE:
72246da4	452	dwc3_gadget_exit(dwc);
0949e99b	453	break;
d07e8819 FB	454	case DWC3_MODE_HOST:
	455	dwc3_host_exit(dwc);
	456	break;
	457	case DWC3_MODE_DRD:
	458	dwc3_host_exit(dwc);
	459	dwc3_gadget_exit(dwc);
	460	break;
0949e99b FB	461	default:
	462	/* do nothing */
	463	break;
	464	}
72246da4 FB	465
	466	err4:
	467	dwc3_core_exit(dwc);
	468
	469	err3:
	470	iounmap(regs);
	471
	472	err2:
	473	release_mem_region(res->start, resource_size(res));
	474
	475	err1:
	476	kfree(dwc->mem);
	477
	478	err0:
	479	return ret;
	480	}
	481
	482	static int __devexit dwc3_remove(struct platform_device *pdev)
	483	{
72246da4 FB	484	struct dwc3 *dwc = platform_get_drvdata(pdev);
72246da4 FB	485	struct resource *res;
72246da4 FB	486
	487	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	488
	489	pm_runtime_put(&pdev->dev);
	490	pm_runtime_disable(&pdev->dev);
	491
	492	dwc3_debugfs_exit(dwc);
	493
0949e99b	494	switch (dwc->mode) {
0949e99b	495	case DWC3_MODE_DEVICE:
72246da4	496	dwc3_gadget_exit(dwc);
0949e99b	497	break;
d07e8819 FB	498	case DWC3_MODE_HOST:
	499	dwc3_host_exit(dwc);
	500	break;
	501	case DWC3_MODE_DRD:
	502	dwc3_host_exit(dwc);
	503	dwc3_gadget_exit(dwc);
	504	break;
0949e99b FB	505	default:
	506	/* do nothing */
	507	break;
	508	}
72246da4 FB	509
	510	dwc3_core_exit(dwc);
	511	release_mem_region(res->start, resource_size(res));
	512	iounmap(dwc->regs);
	513	kfree(dwc->mem);
	514
	515	return 0;
	516	}
	517
72246da4 FB	518	static struct platform_driver dwc3_driver = {
	519	.probe = dwc3_probe,
	520	.remove = __devexit_p(dwc3_remove),
	521	.driver = {
	522	.name = "dwc3",
	523	},
72246da4 FB	524	};
	525
	526	MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
	527	MODULE_LICENSE("Dual BSD/GPL");
	528	MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
	529
	530	static int __devinit dwc3_init(void)
	531	{
	532	return platform_driver_register(&dwc3_driver);
	533	}
	534	module_init(dwc3_init);
	535
	536	static void __exit dwc3_exit(void)
	537	{
	538	platform_driver_unregister(&dwc3_driver);
	539	}
	540	module_exit(dwc3_exit);