projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
usb: dwc3: gadget: extract unlocked dwc3_gadget_wakeup()
[deliverable/linux.git] / drivers / usb / dwc3 / gadget.c
CommitLineData
72246da4
FB		 1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
5945f789
FB		 9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
72246da4 12 *
5945f789
FB		 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
72246da4
FB		 17 */
18
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/list.h>
28#include <linux/dma-mapping.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32
80977dc9 33#include "debug.h"
72246da4
FB		 34#include "core.h"
35#include "gadget.h"
36#include "io.h"
37
04a9bfcd
FB		 38/**
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
42 *
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
45 * is passed
46 */
47int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
48{
49 u32 reg;
50
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
53
54 switch (mode) {
55 case TEST_J:
56 case TEST_K:
57 case TEST_SE0_NAK:
58 case TEST_PACKET:
59 case TEST_FORCE_EN:
60 reg |= mode << 1;
61 break;
62 default:
63 return -EINVAL;
64 }
65
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
67
68 return 0;
69}
70
911f1f88
PZ		 71/**
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
74 *
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
77 */
78int dwc3_gadget_get_link_state(struct dwc3 *dwc)
79{
80 u32 reg;
81
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
83
84 return DWC3_DSTS_USBLNKST(reg);
85}
86
8598bde7
FB		 87/**
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
91 *
92 * Caller should take care of locking. This function will
aee63e3c 93 * return 0 on success or -ETIMEDOUT.
8598bde7
FB		 94 */
95int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
96{
aee63e3c 97 int retries = 10000;
8598bde7
FB		 98 u32 reg;
99
802fde98
PZ		 100 /*
101 * Wait until device controller is ready. Only applies to 1.94a and
102 * later RTL.
103 */
104 if (dwc->revision >= DWC3_REVISION_194A) {
105 while (--retries) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
108 udelay(5);
109 else
110 break;
111 }
112
113 if (retries <= 0)
114 return -ETIMEDOUT;
115 }
116
8598bde7
FB		 117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
119
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
123
802fde98
PZ		 124 /*
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
127 */
128 if (dwc->revision >= DWC3_REVISION_194A)
129 return 0;
130
8598bde7 131 /* wait for a change in DSTS */
aed430e5 132 retries = 10000;
8598bde7
FB		 133 while (--retries) {
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
135
8598bde7
FB		 136 if (DWC3_DSTS_USBLNKST(reg) == state)
137 return 0;
138
aee63e3c 139 udelay(5);
8598bde7
FB		 140 }
141
73815280
FB		 142 dwc3_trace(trace_dwc3_gadget,
143 "link state change request timed out");
8598bde7
FB		 144
145 return -ETIMEDOUT;
146}
147
72246da4
FB		 148void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
149 int status)
150{
151 struct dwc3 *dwc = dep->dwc;
e5ba5ec8 152 int i;
72246da4 153
aa3342c8 154 if (req->started) {
e5ba5ec8
PA		 155 i = 0;
156 do {
eeb720fb 157 dep->busy_slot++;
e5ba5ec8
PA		 158 /*
159 * Skip LINK TRB. We can't use req->trb and check for
160 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
161 * just completed (not the LINK TRB).
162 */
163 if (((dep->busy_slot & DWC3_TRB_MASK) ==
164 DWC3_TRB_NUM- 1) &&
16e78db7 165 usb_endpoint_xfer_isoc(dep->endpoint.desc))
e5ba5ec8
PA		 166 dep->busy_slot++;
167 } while(++i < req->request.num_mapped_sgs);
aa3342c8 168 req->started = false;
72246da4
FB		 169 }
170 list_del(&req->list);
eeb720fb 171 req->trb = NULL;
72246da4
FB		 172
173 if (req->request.status == -EINPROGRESS)
174 req->request.status = status;
175
0416e494
PA		 176 if (dwc->ep0_bounced && dep->number == 0)
177 dwc->ep0_bounced = false;
178 else
179 usb_gadget_unmap_request(&dwc->gadget, &req->request,
180 req->direction);
72246da4 181
2c4cbe6e 182 trace_dwc3_gadget_giveback(req);
72246da4
FB		 183
184 spin_unlock(&dwc->lock);
304f7e5e 185 usb_gadget_giveback_request(&dep->endpoint, &req->request);
72246da4
FB		 186 spin_lock(&dwc->lock);
187}
188
3ece0ec4 189int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
b09bb642
FB		 190{
191 u32 timeout = 500;
192 u32 reg;
193
2c4cbe6e 194 trace_dwc3_gadget_generic_cmd(cmd, param);
427c3df6 195
b09bb642
FB		 196 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
197 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
198
199 do {
200 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
201 if (!(reg & DWC3_DGCMD_CMDACT)) {
73815280
FB		 202 dwc3_trace(trace_dwc3_gadget,
203 "Command Complete --> %d",
b09bb642 204 DWC3_DGCMD_STATUS(reg));
891b1dc0
SSB		 205 if (DWC3_DGCMD_STATUS(reg))
206 return -EINVAL;
b09bb642
FB		 207 return 0;
208 }
209
210 /*
211 * We can't sleep here, because it's also called from
212 * interrupt context.
213 */
214 timeout--;
73815280
FB		 215 if (!timeout) {
216 dwc3_trace(trace_dwc3_gadget,
217 "Command Timed Out");
b09bb642 218 return -ETIMEDOUT;
73815280 219 }
b09bb642
FB		 220 udelay(1);
221 } while (1);
222}
223
72246da4
FB		 224int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
225 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
226{
227 struct dwc3_ep *dep = dwc->eps[ep];
61d58242 228 u32 timeout = 500;
72246da4 229 u32 reg;
2b0f11df
FB		 230
231 int susphy = false;
c0ca324d 232 int ret = -EINVAL;
72246da4 233
2c4cbe6e 234 trace_dwc3_gadget_ep_cmd(dep, cmd, params);
72246da4 235
2b0f11df
FB		 236 /*
237 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
238 * we're issuing an endpoint command, we must check if
239 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
240 *
241 * We will also set SUSPHY bit to what it was before returning as stated
242 * by the same section on Synopsys databook.
243 */
244 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
245 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
246 susphy = true;
247 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
248 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
249 }
250
dc1c70a7
FB		 251 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
252 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
253 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
72246da4
FB		 254
255 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
256 do {
257 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
258 if (!(reg & DWC3_DEPCMD_CMDACT)) {
73815280
FB		 259 dwc3_trace(trace_dwc3_gadget,
260 "Command Complete --> %d",
164f6e14 261 DWC3_DEPCMD_STATUS(reg));
76e838c9 262 if (DWC3_DEPCMD_STATUS(reg))
c0ca324d
FB		 263 break;
264 ret = 0;
265 break;
72246da4
FB		 266 }
267
268 /*
72246da4
FB		 269 * We can't sleep here, because it is also called from
270 * interrupt context.
271 */
272 timeout--;
73815280
FB		 273 if (!timeout) {
274 dwc3_trace(trace_dwc3_gadget,
275 "Command Timed Out");
c0ca324d
FB		 276 ret = -ETIMEDOUT;
277 break;
73815280 278 }
72246da4 279
61d58242 280 udelay(1);
72246da4 281 } while (1);
c0ca324d 282
2b0f11df
FB		 283 if (unlikely(susphy)) {
284 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
285 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
286 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
287 }
288
c0ca324d 289 return ret;
72246da4
FB		 290}
291
292static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
f6bafc6a 293 struct dwc3_trb *trb)
72246da4 294{
c439ef87 295 u32 offset = (char *) trb - (char *) dep->trb_pool;
72246da4
FB		 296
297 return dep->trb_pool_dma + offset;
298}
299
300static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
301{
302 struct dwc3 *dwc = dep->dwc;
303
304 if (dep->trb_pool)
305 return 0;
306
72246da4
FB		 307 dep->trb_pool = dma_alloc_coherent(dwc->dev,
308 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
309 &dep->trb_pool_dma, GFP_KERNEL);
310 if (!dep->trb_pool) {
311 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
312 dep->name);
313 return -ENOMEM;
314 }
315
316 return 0;
317}
318
319static void dwc3_free_trb_pool(struct dwc3_ep *dep)
320{
321 struct dwc3 *dwc = dep->dwc;
322
323 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
324 dep->trb_pool, dep->trb_pool_dma);
325
326 dep->trb_pool = NULL;
327 dep->trb_pool_dma = 0;
328}
329
c4509601
JY		 330static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
331
332/**
333 * dwc3_gadget_start_config - Configure EP resources
334 * @dwc: pointer to our controller context structure
335 * @dep: endpoint that is being enabled
336 *
337 * The assignment of transfer resources cannot perfectly follow the
338 * data book due to the fact that the controller driver does not have
339 * all knowledge of the configuration in advance. It is given this
340 * information piecemeal by the composite gadget framework after every
341 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
342 * programming model in this scenario can cause errors. For two
343 * reasons:
344 *
345 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
346 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
347 * multiple interfaces.
348 *
349 * 2) The databook does not mention doing more DEPXFERCFG for new
350 * endpoint on alt setting (8.1.6).
351 *
352 * The following simplified method is used instead:
353 *
354 * All hardware endpoints can be assigned a transfer resource and this
355 * setting will stay persistent until either a core reset or
356 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
357 * do DEPXFERCFG for every hardware endpoint as well. We are
358 * guaranteed that there are as many transfer resources as endpoints.
359 *
360 * This function is called for each endpoint when it is being enabled
361 * but is triggered only when called for EP0-out, which always happens
362 * first, and which should only happen in one of the above conditions.
363 */
72246da4
FB		 364static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
365{
366 struct dwc3_gadget_ep_cmd_params params;
367 u32 cmd;
c4509601
JY		 368 int i;
369 int ret;
370
371 if (dep->number)
372 return 0;
72246da4
FB		 373
374 memset(&params, 0x00, sizeof(params));
c4509601 375 cmd = DWC3_DEPCMD_DEPSTARTCFG;
72246da4 376
c4509601
JY		 377 ret = dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
378 if (ret)
379 return ret;
380
381 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
382 struct dwc3_ep *dep = dwc->eps[i];
72246da4 383
c4509601
JY		 384 if (!dep)
385 continue;
386
387 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
388 if (ret)
389 return ret;
72246da4
FB		 390 }
391
392 return 0;
393}
394
395static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
c90bfaec 396 const struct usb_endpoint_descriptor *desc,
4b345c9a 397 const struct usb_ss_ep_comp_descriptor *comp_desc,
265b70a7 398 bool ignore, bool restore)
72246da4
FB		 399{
400 struct dwc3_gadget_ep_cmd_params params;
401
402 memset(&params, 0x00, sizeof(params));
403
dc1c70a7 404 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
d2e9a13a
CP		 405 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
406
407 /* Burst size is only needed in SuperSpeed mode */
ee5cd41c 408 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
d2e9a13a
CP		 409 u32 burst = dep->endpoint.maxburst - 1;
410
411 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
412 }
72246da4 413
4b345c9a
FB		 414 if (ignore)
415 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
416
265b70a7
PZ		 417 if (restore) {
418 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
419 params.param2 |= dep->saved_state;
420 }
421
dc1c70a7
FB		 422 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
423 | DWC3_DEPCFG_XFER_NOT_READY_EN;
72246da4 424
18b7ede5 425 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
dc1c70a7
FB		 426 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
427 | DWC3_DEPCFG_STREAM_EVENT_EN;
879631aa
FB		 428 dep->stream_capable = true;
429 }
430
0b93a4c8 431 if (!usb_endpoint_xfer_control(desc))
dc1c70a7 432 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
72246da4
FB		 433
434 /*
435 * We are doing 1:1 mapping for endpoints, meaning
436 * Physical Endpoints 2 maps to Logical Endpoint 2 and
437 * so on. We consider the direction bit as part of the physical
438 * endpoint number. So USB endpoint 0x81 is 0x03.
439 */
dc1c70a7 440 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
72246da4
FB		 441
442 /*
443 * We must use the lower 16 TX FIFOs even though
444 * HW might have more
445 */
446 if (dep->direction)
dc1c70a7 447 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
72246da4
FB		 448
449 if (desc->bInterval) {
dc1c70a7 450 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
72246da4
FB		 451 dep->interval = 1 << (desc->bInterval - 1);
452 }
453
454 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
455 DWC3_DEPCMD_SETEPCONFIG, &params);
456}
457
458static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
459{
460 struct dwc3_gadget_ep_cmd_params params;
461
462 memset(&params, 0x00, sizeof(params));
463
dc1c70a7 464 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
72246da4
FB		 465
466 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
467 DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
468}
469
470/**
471 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
472 * @dep: endpoint to be initialized
473 * @desc: USB Endpoint Descriptor
474 *
475 * Caller should take care of locking
476 */
477static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
c90bfaec 478 const struct usb_endpoint_descriptor *desc,
4b345c9a 479 const struct usb_ss_ep_comp_descriptor *comp_desc,
265b70a7 480 bool ignore, bool restore)
72246da4
FB		 481{
482 struct dwc3 *dwc = dep->dwc;
483 u32 reg;
b09e99ee 484 int ret;
72246da4 485
73815280 486 dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
ff62d6b6 487
72246da4
FB		 488 if (!(dep->flags & DWC3_EP_ENABLED)) {
489 ret = dwc3_gadget_start_config(dwc, dep);
490 if (ret)
491 return ret;
492 }
493
265b70a7
PZ		 494 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
495 restore);
72246da4
FB		 496 if (ret)
497 return ret;
498
499 if (!(dep->flags & DWC3_EP_ENABLED)) {
f6bafc6a
FB		 500 struct dwc3_trb *trb_st_hw;
501 struct dwc3_trb *trb_link;
72246da4 502
16e78db7 503 dep->endpoint.desc = desc;
c90bfaec 504 dep->comp_desc = comp_desc;
72246da4
FB		 505 dep->type = usb_endpoint_type(desc);
506 dep->flags |= DWC3_EP_ENABLED;
507
508 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
509 reg |= DWC3_DALEPENA_EP(dep->number);
510 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
511
512 if (!usb_endpoint_xfer_isoc(desc))
e901aa15 513 goto out;
72246da4 514
1d046793 515 /* Link TRB for ISOC. The HWO bit is never reset */
72246da4
FB		 516 trb_st_hw = &dep->trb_pool[0];
517
f6bafc6a 518 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
1200a82a 519 memset(trb_link, 0, sizeof(*trb_link));
72246da4 520
f6bafc6a
FB		 521 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
522 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
523 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
524 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
72246da4
FB		 525 }
526
e901aa15 527out:
aa739974
FB		 528 switch (usb_endpoint_type(desc)) {
529 case USB_ENDPOINT_XFER_CONTROL:
e901aa15 530 /* don't change name */
aa739974
FB		 531 break;
532 case USB_ENDPOINT_XFER_ISOC:
533 strlcat(dep->name, "-isoc", sizeof(dep->name));
534 break;
535 case USB_ENDPOINT_XFER_BULK:
536 strlcat(dep->name, "-bulk", sizeof(dep->name));
537 break;
538 case USB_ENDPOINT_XFER_INT:
539 strlcat(dep->name, "-int", sizeof(dep->name));
540 break;
541 default:
542 dev_err(dwc->dev, "invalid endpoint transfer type\n");
543 }
544
72246da4
FB		 545 return 0;
546}
547
b992e681 548static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
624407f9 549static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
72246da4
FB		 550{
551 struct dwc3_request *req;
552
aa3342c8 553 if (!list_empty(&dep->started_list)) {
b992e681 554 dwc3_stop_active_transfer(dwc, dep->number, true);
624407f9 555
57911504 556 /* - giveback all requests to gadget driver */
aa3342c8
FB		 557 while (!list_empty(&dep->started_list)) {
558 req = next_request(&dep->started_list);
1591633e
PA		 559
560 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
561 }
ea53b882
FB		 562 }
563
aa3342c8
FB		 564 while (!list_empty(&dep->pending_list)) {
565 req = next_request(&dep->pending_list);
72246da4 566
624407f9 567 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
72246da4 568 }
72246da4
FB		 569}
570
571/**
572 * __dwc3_gadget_ep_disable - Disables a HW endpoint
573 * @dep: the endpoint to disable
574 *
624407f9
SAS		 575 * This function also removes requests which are currently processed ny the
576 * hardware and those which are not yet scheduled.
577 * Caller should take care of locking.
72246da4 578 */
72246da4
FB		 579static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
580{
581 struct dwc3 *dwc = dep->dwc;
582 u32 reg;
583
7eaeac5c
FB		 584 dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
585
624407f9 586 dwc3_remove_requests(dwc, dep);
72246da4 587
687ef981
FB		 588 /* make sure HW endpoint isn't stalled */
589 if (dep->flags & DWC3_EP_STALL)
7a608559 590 __dwc3_gadget_ep_set_halt(dep, 0, false);
687ef981 591
72246da4
FB		 592 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
593 reg &= ~DWC3_DALEPENA_EP(dep->number);
594 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
595
879631aa 596 dep->stream_capable = false;
f9c56cdd 597 dep->endpoint.desc = NULL;
c90bfaec 598 dep->comp_desc = NULL;
72246da4 599 dep->type = 0;
879631aa 600 dep->flags = 0;
72246da4 601
aa739974
FB		 602 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
603 dep->number >> 1,
604 (dep->number & 1) ? "in" : "out");
605
72246da4
FB		 606 return 0;
607}
608
609/* -------------------------------------------------------------------------- */
610
611static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
612 const struct usb_endpoint_descriptor *desc)
613{
614 return -EINVAL;
615}
616
617static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
618{
619 return -EINVAL;
620}
621
622/* -------------------------------------------------------------------------- */
623
624static int dwc3_gadget_ep_enable(struct usb_ep *ep,
625 const struct usb_endpoint_descriptor *desc)
626{
627 struct dwc3_ep *dep;
628 struct dwc3 *dwc;
629 unsigned long flags;
630 int ret;
631
632 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
633 pr_debug("dwc3: invalid parameters\n");
634 return -EINVAL;
635 }
636
637 if (!desc->wMaxPacketSize) {
638 pr_debug("dwc3: missing wMaxPacketSize\n");
639 return -EINVAL;
640 }
641
642 dep = to_dwc3_ep(ep);
643 dwc = dep->dwc;
644
95ca961c
FB		 645 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
646 "%s is already enabled\n",
647 dep->name))
c6f83f38 648 return 0;
c6f83f38 649
72246da4 650 spin_lock_irqsave(&dwc->lock, flags);
265b70a7 651 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
72246da4
FB		 652 spin_unlock_irqrestore(&dwc->lock, flags);
653
654 return ret;
655}
656
657static int dwc3_gadget_ep_disable(struct usb_ep *ep)
658{
659 struct dwc3_ep *dep;
660 struct dwc3 *dwc;
661 unsigned long flags;
662 int ret;
663
664 if (!ep) {
665 pr_debug("dwc3: invalid parameters\n");
666 return -EINVAL;
667 }
668
669 dep = to_dwc3_ep(ep);
670 dwc = dep->dwc;
671
95ca961c
FB		 672 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
673 "%s is already disabled\n",
674 dep->name))
72246da4 675 return 0;
72246da4 676
72246da4
FB		 677 spin_lock_irqsave(&dwc->lock, flags);
678 ret = __dwc3_gadget_ep_disable(dep);
679 spin_unlock_irqrestore(&dwc->lock, flags);
680
681 return ret;
682}
683
684static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
685 gfp_t gfp_flags)
686{
687 struct dwc3_request *req;
688 struct dwc3_ep *dep = to_dwc3_ep(ep);
72246da4
FB		 689
690 req = kzalloc(sizeof(*req), gfp_flags);
734d5a53 691 if (!req)
72246da4 692 return NULL;
72246da4
FB		 693
694 req->epnum = dep->number;
695 req->dep = dep;
72246da4 696
2c4cbe6e
FB		 697 trace_dwc3_alloc_request(req);
698
72246da4
FB		 699 return &req->request;
700}
701
702static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
703 struct usb_request *request)
704{
705 struct dwc3_request *req = to_dwc3_request(request);
706
2c4cbe6e 707 trace_dwc3_free_request(req);
72246da4
FB		 708 kfree(req);
709}
710
c71fc37c
FB		 711/**
712 * dwc3_prepare_one_trb - setup one TRB from one request
713 * @dep: endpoint for which this request is prepared
714 * @req: dwc3_request pointer
715 */
68e823e2 716static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
eeb720fb 717 struct dwc3_request *req, dma_addr_t dma,
e5ba5ec8 718 unsigned length, unsigned last, unsigned chain, unsigned node)
c71fc37c 719{
f6bafc6a 720 struct dwc3_trb *trb;
c71fc37c 721
73815280 722 dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
eeb720fb
FB		 723 dep->name, req, (unsigned long long) dma,
724 length, last ? " last" : "",
725 chain ? " chain" : "");
726
915e202a
PA		 727
728 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
c71fc37c 729
eeb720fb 730 if (!req->trb) {
aa3342c8 731 dwc3_gadget_move_started_request(req);
f6bafc6a
FB		 732 req->trb = trb;
733 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
e5ba5ec8 734 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
eeb720fb 735 }
c71fc37c 736
e5ba5ec8 737 dep->free_slot++;
5cd8c48d
ZJC		 738 /* Skip the LINK-TRB on ISOC */
739 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
740 usb_endpoint_xfer_isoc(dep->endpoint.desc))
741 dep->free_slot++;
e5ba5ec8 742
f6bafc6a
FB		 743 trb->size = DWC3_TRB_SIZE_LENGTH(length);
744 trb->bpl = lower_32_bits(dma);
745 trb->bph = upper_32_bits(dma);
c71fc37c 746
16e78db7 747 switch (usb_endpoint_type(dep->endpoint.desc)) {
c71fc37c 748 case USB_ENDPOINT_XFER_CONTROL:
f6bafc6a 749 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
c71fc37c
FB		 750 break;
751
752 case USB_ENDPOINT_XFER_ISOC:
e5ba5ec8
PA		 753 if (!node)
754 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
755 else
756 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
ca4d44ea
FB		 757
758 /* always enable Interrupt on Missed ISOC */
759 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
c71fc37c
FB		 760 break;
761
762 case USB_ENDPOINT_XFER_BULK:
763 case USB_ENDPOINT_XFER_INT:
f6bafc6a 764 trb->ctrl = DWC3_TRBCTL_NORMAL;
c71fc37c
FB		 765 break;
766 default:
767 /*
768 * This is only possible with faulty memory because we
769 * checked it already :)
770 */
771 BUG();
772 }
773
ca4d44ea
FB		 774 /* always enable Continue on Short Packet */
775 trb->ctrl |= DWC3_TRB_CTRL_CSP;
f3af3651 776
ca4d44ea
FB		 777 if (!req->request.no_interrupt)
778 trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI;
779
780 if (last)
e5ba5ec8 781 trb->ctrl |= DWC3_TRB_CTRL_LST;
c71fc37c 782
e5ba5ec8
PA		 783 if (chain)
784 trb->ctrl |= DWC3_TRB_CTRL_CHN;
785
16e78db7 786 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
f6bafc6a 787 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
c71fc37c 788
f6bafc6a 789 trb->ctrl |= DWC3_TRB_CTRL_HWO;
2c4cbe6e
FB		 790
791 trace_dwc3_prepare_trb(dep, trb);
c71fc37c
FB		 792}
793
72246da4
FB		 794/*
795 * dwc3_prepare_trbs - setup TRBs from requests
796 * @dep: endpoint for which requests are being prepared
797 * @starting: true if the endpoint is idle and no requests are queued.
798 *
1d046793
PZ		 799 * The function goes through the requests list and sets up TRBs for the
800 * transfers. The function returns once there are no more TRBs available or
801 * it runs out of requests.
72246da4 802 */
68e823e2 803static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
72246da4 804{
68e823e2 805 struct dwc3_request *req, *n;
72246da4 806 u32 trbs_left;
8d62cd65 807 u32 max;
c71fc37c 808 unsigned int last_one = 0;
72246da4
FB		 809
810 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
811
812 /* the first request must not be queued */
813 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
c71fc37c 814
8d62cd65 815 /* Can't wrap around on a non-isoc EP since there's no link TRB */
16e78db7 816 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8d62cd65
PZ		 817 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
818 if (trbs_left > max)
819 trbs_left = max;
820 }
821
72246da4 822 /*
1d046793
PZ		 823 * If busy & slot are equal than it is either full or empty. If we are
824 * starting to process requests then we are empty. Otherwise we are
72246da4
FB		 825 * full and don't do anything
826 */
827 if (!trbs_left) {
828 if (!starting)
68e823e2 829 return;
72246da4
FB		 830 trbs_left = DWC3_TRB_NUM;
831 /*
832 * In case we start from scratch, we queue the ISOC requests
833 * starting from slot 1. This is done because we use ring
834 * buffer and have no LST bit to stop us. Instead, we place
1d046793 835 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
72246da4
FB		 836 * after the first request so we start at slot 1 and have
837 * 7 requests proceed before we hit the first IOC.
838 * Other transfer types don't use the ring buffer and are
839 * processed from the first TRB until the last one. Since we
840 * don't wrap around we have to start at the beginning.
841 */
16e78db7 842 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 843 dep->busy_slot = 1;
844 dep->free_slot = 1;
845 } else {
846 dep->busy_slot = 0;
847 dep->free_slot = 0;
848 }
849 }
850
851 /* The last TRB is a link TRB, not used for xfer */
16e78db7 852 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
68e823e2 853 return;
72246da4 854
aa3342c8 855 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
eeb720fb
FB		 856 unsigned length;
857 dma_addr_t dma;
e5ba5ec8 858 last_one = false;
72246da4 859
eeb720fb
FB		 860 if (req->request.num_mapped_sgs > 0) {
861 struct usb_request *request = &req->request;
862 struct scatterlist *sg = request->sg;
863 struct scatterlist *s;
864 int i;
72246da4 865
eeb720fb
FB		 866 for_each_sg(sg, s, request->num_mapped_sgs, i) {
867 unsigned chain = true;
72246da4 868
eeb720fb
FB		 869 length = sg_dma_len(s);
870 dma = sg_dma_address(s);
72246da4 871
1d046793
PZ		 872 if (i == (request->num_mapped_sgs - 1) ||
873 sg_is_last(s)) {
aa3342c8 874 if (list_empty(&dep->pending_list))
e5ba5ec8 875 last_one = true;
eeb720fb
FB		 876 chain = false;
877 }
72246da4 878
eeb720fb
FB		 879 trbs_left--;
880 if (!trbs_left)
881 last_one = true;
72246da4 882
eeb720fb
FB		 883 if (last_one)
884 chain = false;
72246da4 885
eeb720fb 886 dwc3_prepare_one_trb(dep, req, dma, length,
e5ba5ec8 887 last_one, chain, i);
72246da4 888
eeb720fb
FB		 889 if (last_one)
890 break;
891 }
39e60635
AV		 892
893 if (last_one)
894 break;
72246da4 895 } else {
eeb720fb
FB		 896 dma = req->request.dma;
897 length = req->request.length;
898 trbs_left--;
72246da4 899
eeb720fb
FB		 900 if (!trbs_left)
901 last_one = 1;
879631aa 902
eeb720fb 903 /* Is this the last request? */
aa3342c8 904 if (list_is_last(&req->list, &dep->pending_list))
eeb720fb 905 last_one = 1;
72246da4 906
eeb720fb 907 dwc3_prepare_one_trb(dep, req, dma, length,
e5ba5ec8 908 last_one, false, 0);
72246da4 909
eeb720fb
FB		 910 if (last_one)
911 break;
72246da4 912 }
72246da4 913 }
72246da4
FB		 914}
915
916static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
917 int start_new)
918{
919 struct dwc3_gadget_ep_cmd_params params;
920 struct dwc3_request *req;
921 struct dwc3 *dwc = dep->dwc;
922 int ret;
923 u32 cmd;
924
925 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
73815280 926 dwc3_trace(trace_dwc3_gadget, "%s: endpoint busy", dep->name);
72246da4
FB		 927 return -EBUSY;
928 }
72246da4
FB		 929
930 /*
931 * If we are getting here after a short-out-packet we don't enqueue any
932 * new requests as we try to set the IOC bit only on the last request.
933 */
934 if (start_new) {
aa3342c8 935 if (list_empty(&dep->started_list))
72246da4
FB		 936 dwc3_prepare_trbs(dep, start_new);
937
938 /* req points to the first request which will be sent */
aa3342c8 939 req = next_request(&dep->started_list);
72246da4 940 } else {
68e823e2
FB		 941 dwc3_prepare_trbs(dep, start_new);
942
72246da4 943 /*
1d046793 944 * req points to the first request where HWO changed from 0 to 1
72246da4 945 */
aa3342c8 946 req = next_request(&dep->started_list);
72246da4
FB		 947 }
948 if (!req) {
949 dep->flags |= DWC3_EP_PENDING_REQUEST;
950 return 0;
951 }
952
953 memset(&params, 0, sizeof(params));
72246da4 954
1877d6c9
PA		 955 if (start_new) {
956 params.param0 = upper_32_bits(req->trb_dma);
957 params.param1 = lower_32_bits(req->trb_dma);
72246da4 958 cmd = DWC3_DEPCMD_STARTTRANSFER;
1877d6c9 959 } else {
72246da4 960 cmd = DWC3_DEPCMD_UPDATETRANSFER;
1877d6c9 961 }
72246da4
FB		 962
963 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
964 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
965 if (ret < 0) {
72246da4
FB		 966 /*
967 * FIXME we need to iterate over the list of requests
968 * here and stop, unmap, free and del each of the linked
1d046793 969 * requests instead of what we do now.
72246da4 970 */
0fc9a1be
FB		 971 usb_gadget_unmap_request(&dwc->gadget, &req->request,
972 req->direction);
72246da4
FB		 973 list_del(&req->list);
974 return ret;
975 }
976
977 dep->flags |= DWC3_EP_BUSY;
25b8ff68 978
f898ae09 979 if (start_new) {
b4996a86 980 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
f898ae09 981 dep->number);
b4996a86 982 WARN_ON_ONCE(!dep->resource_index);
f898ae09 983 }
25b8ff68 984
72246da4
FB		 985 return 0;
986}
987
d6d6ec7b
PA		 988static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
989 struct dwc3_ep *dep, u32 cur_uf)
990{
991 u32 uf;
992
aa3342c8 993 if (list_empty(&dep->pending_list)) {
73815280
FB		 994 dwc3_trace(trace_dwc3_gadget,
995 "ISOC ep %s run out for requests",
996 dep->name);
f4a53c55 997 dep->flags |= DWC3_EP_PENDING_REQUEST;
d6d6ec7b
PA		 998 return;
999 }
1000
1001 /* 4 micro frames in the future */
1002 uf = cur_uf + dep->interval * 4;
1003
1004 __dwc3_gadget_kick_transfer(dep, uf, 1);
1005}
1006
1007static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1008 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1009{
1010 u32 cur_uf, mask;
1011
1012 mask = ~(dep->interval - 1);
1013 cur_uf = event->parameters & mask;
1014
1015 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1016}
1017
72246da4
FB		 1018static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1019{
0fc9a1be
FB		 1020 struct dwc3 *dwc = dep->dwc;
1021 int ret;
1022
bb423984 1023 if (!dep->endpoint.desc) {
ec5e795c
FB		 1024 dwc3_trace(trace_dwc3_gadget,
1025 "trying to queue request %p to disabled %s\n",
bb423984
FB		 1026 &req->request, dep->endpoint.name);
1027 return -ESHUTDOWN;
1028 }
1029
1030 if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1031 &req->request, req->dep->name)) {
ec5e795c
FB		 1032 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n",
1033 &req->request, req->dep->name);
bb423984
FB		 1034 return -EINVAL;
1035 }
1036
72246da4
FB		 1037 req->request.actual = 0;
1038 req->request.status = -EINPROGRESS;
1039 req->direction = dep->direction;
1040 req->epnum = dep->number;
1041
fe84f522
FB		 1042 trace_dwc3_ep_queue(req);
1043
72246da4
FB		 1044 /*
1045 * We only add to our list of requests now and
1046 * start consuming the list once we get XferNotReady
1047 * IRQ.
1048 *
1049 * That way, we avoid doing anything that we don't need
1050 * to do now and defer it until the point we receive a
1051 * particular token from the Host side.
1052 *
1053 * This will also avoid Host cancelling URBs due to too
1d046793 1054 * many NAKs.
72246da4 1055 */
0fc9a1be
FB		 1056 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1057 dep->direction);
1058 if (ret)
1059 return ret;
1060
aa3342c8 1061 list_add_tail(&req->list, &dep->pending_list);
72246da4 1062
1d6a3918
FB		 1063 /*
1064 * If there are no pending requests and the endpoint isn't already
1065 * busy, we will just start the request straight away.
1066 *
1067 * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1068 * little bit faster.
1069 */
1070 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
62e345ae 1071 !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1d6a3918
FB		 1072 !(dep->flags & DWC3_EP_BUSY)) {
1073 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
a8f32817 1074 goto out;
1d6a3918
FB		 1075 }
1076
72246da4 1077 /*
b511e5e7 1078 * There are a few special cases:
72246da4 1079 *
f898ae09
PZ		 1080 * 1. XferNotReady with empty list of requests. We need to kick the
1081 * transfer here in that situation, otherwise we will be NAKing
1082 * forever. If we get XferNotReady before gadget driver has a
1083 * chance to queue a request, we will ACK the IRQ but won't be
1084 * able to receive the data until the next request is queued.
1085 * The following code is handling exactly that.
72246da4 1086 *
72246da4
FB		 1087 */
1088 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
f4a53c55
PA		 1089 /*
1090 * If xfernotready is already elapsed and it is a case
1091 * of isoc transfer, then issue END TRANSFER, so that
1092 * you can receive xfernotready again and can have
1093 * notion of current microframe.
1094 */
1095 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
aa3342c8 1096 if (list_empty(&dep->started_list)) {
b992e681 1097 dwc3_stop_active_transfer(dwc, dep->number, true);
cdc359dd
PA		 1098 dep->flags = DWC3_EP_ENABLED;
1099 }
f4a53c55
PA		 1100 return 0;
1101 }
1102
b511e5e7 1103 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
89185916
FB		 1104 if (!ret)
1105 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1106
a8f32817 1107 goto out;
b511e5e7 1108 }
72246da4 1109
b511e5e7
FB		 1110 /*
1111 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1112 * kick the transfer here after queuing a request, otherwise the
1113 * core may not see the modified TRB(s).
1114 */
1115 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
79c9046e
PA		 1116 (dep->flags & DWC3_EP_BUSY) &&
1117 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
b4996a86
FB		 1118 WARN_ON_ONCE(!dep->resource_index);
1119 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
b511e5e7 1120 false);
a8f32817 1121 goto out;
a0925324 1122 }
72246da4 1123
b997ada5
FB		 1124 /*
1125 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1126 * right away, otherwise host will not know we have streams to be
1127 * handled.
1128 */
a8f32817 1129 if (dep->stream_capable)
b997ada5 1130 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
b997ada5 1131
a8f32817
FB		 1132out:
1133 if (ret && ret != -EBUSY)
ec5e795c
FB		 1134 dwc3_trace(trace_dwc3_gadget,
1135 "%s: failed to kick transfers\n",
a8f32817
FB		 1136 dep->name);
1137 if (ret == -EBUSY)
1138 ret = 0;
1139
1140 return ret;
72246da4
FB		 1141}
1142
04c03d10
FB		 1143static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1144 struct usb_request *request)
1145{
1146 dwc3_gadget_ep_free_request(ep, request);
1147}
1148
1149static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1150{
1151 struct dwc3_request *req;
1152 struct usb_request *request;
1153 struct usb_ep *ep = &dep->endpoint;
1154
1155 dwc3_trace(trace_dwc3_gadget, "queueing ZLP\n");
1156 request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1157 if (!request)
1158 return -ENOMEM;
1159
1160 request->length = 0;
1161 request->buf = dwc->zlp_buf;
1162 request->complete = __dwc3_gadget_ep_zlp_complete;
1163
1164 req = to_dwc3_request(request);
1165
1166 return __dwc3_gadget_ep_queue(dep, req);
1167}
1168
72246da4
FB		 1169static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1170 gfp_t gfp_flags)
1171{
1172 struct dwc3_request *req = to_dwc3_request(request);
1173 struct dwc3_ep *dep = to_dwc3_ep(ep);
1174 struct dwc3 *dwc = dep->dwc;
1175
1176 unsigned long flags;
1177
1178 int ret;
1179
fdee4eba 1180 spin_lock_irqsave(&dwc->lock, flags);
72246da4 1181 ret = __dwc3_gadget_ep_queue(dep, req);
04c03d10
FB		 1182
1183 /*
1184 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1185 * setting request->zero, instead of doing magic, we will just queue an
1186 * extra usb_request ourselves so that it gets handled the same way as
1187 * any other request.
1188 */
d9261898
JY		 1189 if (ret == 0 && request->zero && request->length &&
1190 (request->length % ep->maxpacket == 0))
04c03d10
FB		 1191 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1192
72246da4
FB		 1193 spin_unlock_irqrestore(&dwc->lock, flags);
1194
1195 return ret;
1196}
1197
1198static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1199 struct usb_request *request)
1200{
1201 struct dwc3_request *req = to_dwc3_request(request);
1202 struct dwc3_request *r = NULL;
1203
1204 struct dwc3_ep *dep = to_dwc3_ep(ep);
1205 struct dwc3 *dwc = dep->dwc;
1206
1207 unsigned long flags;
1208 int ret = 0;
1209
2c4cbe6e
FB		 1210 trace_dwc3_ep_dequeue(req);
1211
72246da4
FB		 1212 spin_lock_irqsave(&dwc->lock, flags);
1213
aa3342c8 1214 list_for_each_entry(r, &dep->pending_list, list) {
72246da4
FB		 1215 if (r == req)
1216 break;
1217 }
1218
1219 if (r != req) {
aa3342c8 1220 list_for_each_entry(r, &dep->started_list, list) {
72246da4
FB		 1221 if (r == req)
1222 break;
1223 }
1224 if (r == req) {
1225 /* wait until it is processed */
b992e681 1226 dwc3_stop_active_transfer(dwc, dep->number, true);
e8d4e8be 1227 goto out1;
72246da4
FB		 1228 }
1229 dev_err(dwc->dev, "request %p was not queued to %s\n",
1230 request, ep->name);
1231 ret = -EINVAL;
1232 goto out0;
1233 }
1234
e8d4e8be 1235out1:
72246da4
FB		 1236 /* giveback the request */
1237 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1238
1239out0:
1240 spin_unlock_irqrestore(&dwc->lock, flags);
1241
1242 return ret;
1243}
1244
7a608559 1245int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
72246da4
FB		 1246{
1247 struct dwc3_gadget_ep_cmd_params params;
1248 struct dwc3 *dwc = dep->dwc;
1249 int ret;
1250
5ad02fb8
FB		 1251 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1252 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1253 return -EINVAL;
1254 }
1255
72246da4
FB		 1256 memset(&params, 0x00, sizeof(params));
1257
1258 if (value) {
7a608559 1259 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
aa3342c8
FB		 1260 (!list_empty(&dep->started_list) ||
1261 !list_empty(&dep->pending_list)))) {
ec5e795c
FB		 1262 dwc3_trace(trace_dwc3_gadget,
1263 "%s: pending request, cannot halt\n",
7a608559
FB		 1264 dep->name);
1265 return -EAGAIN;
1266 }
1267
72246da4
FB		 1268 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1269 DWC3_DEPCMD_SETSTALL, &params);
1270 if (ret)
3f89204b 1271 dev_err(dwc->dev, "failed to set STALL on %s\n",
72246da4
FB		 1272 dep->name);
1273 else
1274 dep->flags |= DWC3_EP_STALL;
1275 } else {
1276 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1277 DWC3_DEPCMD_CLEARSTALL, &params);
1278 if (ret)
3f89204b 1279 dev_err(dwc->dev, "failed to clear STALL on %s\n",
72246da4
FB		 1280 dep->name);
1281 else
a535d81c 1282 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
72246da4 1283 }
5275455a 1284
72246da4
FB		 1285 return ret;
1286}
1287
1288static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1289{
1290 struct dwc3_ep *dep = to_dwc3_ep(ep);
1291 struct dwc3 *dwc = dep->dwc;
1292
1293 unsigned long flags;
1294
1295 int ret;
1296
1297 spin_lock_irqsave(&dwc->lock, flags);
7a608559 1298 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
72246da4
FB		 1299 spin_unlock_irqrestore(&dwc->lock, flags);
1300
1301 return ret;
1302}
1303
1304static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1305{
1306 struct dwc3_ep *dep = to_dwc3_ep(ep);
249a4569
PZ		 1307 struct dwc3 *dwc = dep->dwc;
1308 unsigned long flags;
95aa4e8d 1309 int ret;
72246da4 1310
249a4569 1311 spin_lock_irqsave(&dwc->lock, flags);
72246da4
FB		 1312 dep->flags |= DWC3_EP_WEDGE;
1313
08f0d966 1314 if (dep->number == 0 || dep->number == 1)
95aa4e8d 1315 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
08f0d966 1316 else
7a608559 1317 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
95aa4e8d
FB		 1318 spin_unlock_irqrestore(&dwc->lock, flags);
1319
1320 return ret;
72246da4
FB		 1321}
1322
1323/* -------------------------------------------------------------------------- */
1324
1325static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1326 .bLength = USB_DT_ENDPOINT_SIZE,
1327 .bDescriptorType = USB_DT_ENDPOINT,
1328 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1329};
1330
1331static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1332 .enable = dwc3_gadget_ep0_enable,
1333 .disable = dwc3_gadget_ep0_disable,
1334 .alloc_request = dwc3_gadget_ep_alloc_request,
1335 .free_request = dwc3_gadget_ep_free_request,
1336 .queue = dwc3_gadget_ep0_queue,
1337 .dequeue = dwc3_gadget_ep_dequeue,
08f0d966 1338 .set_halt = dwc3_gadget_ep0_set_halt,
72246da4
FB		 1339 .set_wedge = dwc3_gadget_ep_set_wedge,
1340};
1341
1342static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1343 .enable = dwc3_gadget_ep_enable,
1344 .disable = dwc3_gadget_ep_disable,
1345 .alloc_request = dwc3_gadget_ep_alloc_request,
1346 .free_request = dwc3_gadget_ep_free_request,
1347 .queue = dwc3_gadget_ep_queue,
1348 .dequeue = dwc3_gadget_ep_dequeue,
1349 .set_halt = dwc3_gadget_ep_set_halt,
1350 .set_wedge = dwc3_gadget_ep_set_wedge,
1351};
1352
1353/* -------------------------------------------------------------------------- */
1354
1355static int dwc3_gadget_get_frame(struct usb_gadget *g)
1356{
1357 struct dwc3 *dwc = gadget_to_dwc(g);
1358 u32 reg;
1359
1360 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1361 return DWC3_DSTS_SOFFN(reg);
1362}
1363
218ef7b6 1364static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
72246da4 1365{
72246da4 1366 unsigned long timeout;
72246da4 1367
218ef7b6 1368 int ret;
72246da4
FB		 1369 u32 reg;
1370
72246da4
FB		 1371 u8 link_state;
1372 u8 speed;
1373
72246da4
FB		 1374 /*
1375 * According to the Databook Remote wakeup request should
1376 * be issued only when the device is in early suspend state.
1377 *
1378 * We can check that via USB Link State bits in DSTS register.
1379 */
1380 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1381
1382 speed = reg & DWC3_DSTS_CONNECTSPD;
ee5cd41c
JY		 1383 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1384 (speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
ec5e795c 1385 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n");
218ef7b6 1386 return -EINVAL;
72246da4
FB		 1387 }
1388
1389 link_state = DWC3_DSTS_USBLNKST(reg);
1390
1391 switch (link_state) {
1392 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1393 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1394 break;
1395 default:
ec5e795c
FB		 1396 dwc3_trace(trace_dwc3_gadget,
1397 "can't wakeup from '%s'\n",
1398 dwc3_gadget_link_string(link_state));
218ef7b6 1399 return -EINVAL;
72246da4
FB		 1400 }
1401
8598bde7
FB		 1402 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1403 if (ret < 0) {
1404 dev_err(dwc->dev, "failed to put link in Recovery\n");
218ef7b6 1405 return ret;
8598bde7 1406 }
72246da4 1407
802fde98
PZ		 1408 /* Recent versions do this automatically */
1409 if (dwc->revision < DWC3_REVISION_194A) {
1410 /* write zeroes to Link Change Request */
fcc023c7 1411 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
802fde98
PZ		 1412 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1413 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1414 }
72246da4 1415
1d046793 1416 /* poll until Link State changes to ON */
72246da4
FB		 1417 timeout = jiffies + msecs_to_jiffies(100);
1418
1d046793 1419 while (!time_after(jiffies, timeout)) {
72246da4
FB		 1420 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1421
1422 /* in HS, means ON */
1423 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1424 break;
1425 }
1426
1427 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1428 dev_err(dwc->dev, "failed to send remote wakeup\n");
218ef7b6 1429 return -EINVAL;
72246da4
FB		 1430 }
1431
218ef7b6
FB		 1432 return 0;
1433}
1434
1435static int dwc3_gadget_wakeup(struct usb_gadget *g)
1436{
1437 struct dwc3 *dwc = gadget_to_dwc(g);
1438 unsigned long flags;
1439 int ret;
1440
1441 spin_lock_irqsave(&dwc->lock, flags);
1442 ret = __dwc3_gadget_wakeup(dwc);
72246da4
FB		 1443 spin_unlock_irqrestore(&dwc->lock, flags);
1444
1445 return ret;
1446}
1447
1448static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1449 int is_selfpowered)
1450{
1451 struct dwc3 *dwc = gadget_to_dwc(g);
249a4569 1452 unsigned long flags;
72246da4 1453
249a4569 1454 spin_lock_irqsave(&dwc->lock, flags);
bcdea503 1455 g->is_selfpowered = !!is_selfpowered;
249a4569 1456 spin_unlock_irqrestore(&dwc->lock, flags);
72246da4
FB		 1457
1458 return 0;
1459}
1460
7b2a0368 1461static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
72246da4
FB		 1462{
1463 u32 reg;
61d58242 1464 u32 timeout = 500;
72246da4
FB		 1465
1466 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
8db7ed15 1467 if (is_on) {
802fde98
PZ		 1468 if (dwc->revision <= DWC3_REVISION_187A) {
1469 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1470 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1471 }
1472
1473 if (dwc->revision >= DWC3_REVISION_194A)
1474 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1475 reg |= DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1476
1477 if (dwc->has_hibernation)
1478 reg |= DWC3_DCTL_KEEP_CONNECT;
1479
9fcb3bd8 1480 dwc->pullups_connected = true;
8db7ed15 1481 } else {
72246da4 1482 reg &= ~DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1483
1484 if (dwc->has_hibernation && !suspend)
1485 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1486
9fcb3bd8 1487 dwc->pullups_connected = false;
8db7ed15 1488 }
72246da4
FB		 1489
1490 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1491
1492 do {
1493 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1494 if (is_on) {
1495 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1496 break;
1497 } else {
1498 if (reg & DWC3_DSTS_DEVCTRLHLT)
1499 break;
1500 }
72246da4
FB		 1501 timeout--;
1502 if (!timeout)
6f17f74b 1503 return -ETIMEDOUT;
61d58242 1504 udelay(1);
72246da4
FB		 1505 } while (1);
1506
73815280 1507 dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
72246da4
FB		 1508 dwc->gadget_driver
1509 ? dwc->gadget_driver->function : "no-function",
1510 is_on ? "connect" : "disconnect");
6f17f74b
PA		 1511
1512 return 0;
72246da4
FB		 1513}
1514
1515static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1516{
1517 struct dwc3 *dwc = gadget_to_dwc(g);
1518 unsigned long flags;
6f17f74b 1519 int ret;
72246da4
FB		 1520
1521 is_on = !!is_on;
1522
1523 spin_lock_irqsave(&dwc->lock, flags);
7b2a0368 1524 ret = dwc3_gadget_run_stop(dwc, is_on, false);
72246da4
FB		 1525 spin_unlock_irqrestore(&dwc->lock, flags);
1526
6f17f74b 1527 return ret;
72246da4
FB		 1528}
1529
8698e2ac
FB		 1530static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1531{
1532 u32 reg;
1533
1534 /* Enable all but Start and End of Frame IRQs */
1535 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1536 DWC3_DEVTEN_EVNTOVERFLOWEN |
1537 DWC3_DEVTEN_CMDCMPLTEN |
1538 DWC3_DEVTEN_ERRTICERREN |
1539 DWC3_DEVTEN_WKUPEVTEN |
1540 DWC3_DEVTEN_ULSTCNGEN |
1541 DWC3_DEVTEN_CONNECTDONEEN |
1542 DWC3_DEVTEN_USBRSTEN |
1543 DWC3_DEVTEN_DISCONNEVTEN);
1544
1545 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1546}
1547
1548static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1549{
1550 /* mask all interrupts */
1551 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1552}
1553
1554static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
b15a762f 1555static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
8698e2ac 1556
72246da4
FB		 1557static int dwc3_gadget_start(struct usb_gadget *g,
1558 struct usb_gadget_driver *driver)
1559{
1560 struct dwc3 *dwc = gadget_to_dwc(g);
1561 struct dwc3_ep *dep;
1562 unsigned long flags;
1563 int ret = 0;
8698e2ac 1564 int irq;
72246da4
FB		 1565 u32 reg;
1566
b0d7ffd4
FB		 1567 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1568 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
dea520a4 1569 IRQF_SHARED, "dwc3", dwc->ev_buf);
b0d7ffd4
FB		 1570 if (ret) {
1571 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1572 irq, ret);
1573 goto err0;
1574 }
1575
72246da4
FB		 1576 spin_lock_irqsave(&dwc->lock, flags);
1577
1578 if (dwc->gadget_driver) {
1579 dev_err(dwc->dev, "%s is already bound to %s\n",
1580 dwc->gadget.name,
1581 dwc->gadget_driver->driver.name);
1582 ret = -EBUSY;
b0d7ffd4 1583 goto err1;
72246da4
FB		 1584 }
1585
1586 dwc->gadget_driver = driver;
72246da4 1587
72246da4
FB		 1588 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1589 reg &= ~(DWC3_DCFG_SPEED_MASK);
07e7f47b
FB		 1590
1591 /**
1592 * WORKAROUND: DWC3 revision < 2.20a have an issue
1593 * which would cause metastability state on Run/Stop
1594 * bit if we try to force the IP to USB2-only mode.
1595 *
1596 * Because of that, we cannot configure the IP to any
1597 * speed other than the SuperSpeed
1598 *
1599 * Refers to:
1600 *
1601 * STAR#9000525659: Clock Domain Crossing on DCTL in
1602 * USB 2.0 Mode
1603 */
f7e846f0 1604 if (dwc->revision < DWC3_REVISION_220A) {
07e7f47b 1605 reg |= DWC3_DCFG_SUPERSPEED;
f7e846f0
FB		 1606 } else {
1607 switch (dwc->maximum_speed) {
1608 case USB_SPEED_LOW:
1609 reg |= DWC3_DSTS_LOWSPEED;
1610 break;
1611 case USB_SPEED_FULL:
1612 reg |= DWC3_DSTS_FULLSPEED1;
1613 break;
1614 case USB_SPEED_HIGH:
1615 reg |= DWC3_DSTS_HIGHSPEED;
1616 break;
7580862b
JY		 1617 case USB_SPEED_SUPER_PLUS:
1618 reg |= DWC3_DSTS_SUPERSPEED_PLUS;
1619 break;
f7e846f0 1620 default:
77966eb8
JY		 1621 dev_err(dwc->dev, "invalid dwc->maximum_speed (%d)\n",
1622 dwc->maximum_speed);
1623 /* fall through */
1624 case USB_SPEED_SUPER:
1625 reg |= DWC3_DCFG_SUPERSPEED;
1626 break;
f7e846f0
FB		 1627 }
1628 }
72246da4
FB		 1629 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1630
1631 /* Start with SuperSpeed Default */
1632 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1633
1634 dep = dwc->eps[0];
265b70a7
PZ		 1635 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1636 false);
72246da4
FB		 1637 if (ret) {
1638 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
b0d7ffd4 1639 goto err2;
72246da4
FB		 1640 }
1641
1642 dep = dwc->eps[1];
265b70a7
PZ		 1643 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1644 false);
72246da4
FB		 1645 if (ret) {
1646 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
b0d7ffd4 1647 goto err3;
72246da4
FB		 1648 }
1649
1650 /* begin to receive SETUP packets */
c7fcdeb2 1651 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 1652 dwc3_ep0_out_start(dwc);
1653
8698e2ac
FB		 1654 dwc3_gadget_enable_irq(dwc);
1655
72246da4
FB		 1656 spin_unlock_irqrestore(&dwc->lock, flags);
1657
1658 return 0;
1659
b0d7ffd4 1660err3:
72246da4
FB		 1661 __dwc3_gadget_ep_disable(dwc->eps[0]);
1662
b0d7ffd4 1663err2:
cdcedd69 1664 dwc->gadget_driver = NULL;
b0d7ffd4
FB		 1665
1666err1:
72246da4
FB		 1667 spin_unlock_irqrestore(&dwc->lock, flags);
1668
dea520a4 1669 free_irq(irq, dwc->ev_buf);
b0d7ffd4
FB		 1670
1671err0:
72246da4
FB		 1672 return ret;
1673}
1674
22835b80 1675static int dwc3_gadget_stop(struct usb_gadget *g)
72246da4
FB		 1676{
1677 struct dwc3 *dwc = gadget_to_dwc(g);
1678 unsigned long flags;
8698e2ac 1679 int irq;
72246da4
FB		 1680
1681 spin_lock_irqsave(&dwc->lock, flags);
1682
8698e2ac 1683 dwc3_gadget_disable_irq(dwc);
72246da4
FB		 1684 __dwc3_gadget_ep_disable(dwc->eps[0]);
1685 __dwc3_gadget_ep_disable(dwc->eps[1]);
1686
1687 dwc->gadget_driver = NULL;
72246da4
FB		 1688
1689 spin_unlock_irqrestore(&dwc->lock, flags);
1690
b0d7ffd4 1691 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
dea520a4 1692 free_irq(irq, dwc->ev_buf);
b0d7ffd4 1693
72246da4
FB		 1694 return 0;
1695}
802fde98 1696
72246da4
FB		 1697static const struct usb_gadget_ops dwc3_gadget_ops = {
1698 .get_frame = dwc3_gadget_get_frame,
1699 .wakeup = dwc3_gadget_wakeup,
1700 .set_selfpowered = dwc3_gadget_set_selfpowered,
1701 .pullup = dwc3_gadget_pullup,
1702 .udc_start = dwc3_gadget_start,
1703 .udc_stop = dwc3_gadget_stop,
1704};
1705
1706/* -------------------------------------------------------------------------- */
1707
6a1e3ef4
FB		 1708static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1709 u8 num, u32 direction)
72246da4
FB		 1710{
1711 struct dwc3_ep *dep;
6a1e3ef4 1712 u8 i;
72246da4 1713
6a1e3ef4
FB		 1714 for (i = 0; i < num; i++) {
1715 u8 epnum = (i << 1) | (!!direction);
72246da4 1716
72246da4 1717 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
734d5a53 1718 if (!dep)
72246da4 1719 return -ENOMEM;
72246da4
FB		 1720
1721 dep->dwc = dwc;
1722 dep->number = epnum;
9aa62ae4 1723 dep->direction = !!direction;
72246da4
FB		 1724 dwc->eps[epnum] = dep;
1725
1726 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1727 (epnum & 1) ? "in" : "out");
6a1e3ef4 1728
72246da4 1729 dep->endpoint.name = dep->name;
72246da4 1730
73815280 1731 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
653df35e 1732
72246da4 1733 if (epnum == 0 || epnum == 1) {
e117e742 1734 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
6048e4c6 1735 dep->endpoint.maxburst = 1;
72246da4
FB		 1736 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1737 if (!epnum)
1738 dwc->gadget.ep0 = &dep->endpoint;
1739 } else {
1740 int ret;
1741
e117e742 1742 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
12d36c16 1743 dep->endpoint.max_streams = 15;
72246da4
FB		 1744 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1745 list_add_tail(&dep->endpoint.ep_list,
1746 &dwc->gadget.ep_list);
1747
1748 ret = dwc3_alloc_trb_pool(dep);
25b8ff68 1749 if (ret)
72246da4 1750 return ret;
72246da4 1751 }
25b8ff68 1752
a474d3b7
RB		 1753 if (epnum == 0 || epnum == 1) {
1754 dep->endpoint.caps.type_control = true;
1755 } else {
1756 dep->endpoint.caps.type_iso = true;
1757 dep->endpoint.caps.type_bulk = true;
1758 dep->endpoint.caps.type_int = true;
1759 }
1760
1761 dep->endpoint.caps.dir_in = !!direction;
1762 dep->endpoint.caps.dir_out = !direction;
1763
aa3342c8
FB		 1764 INIT_LIST_HEAD(&dep->pending_list);
1765 INIT_LIST_HEAD(&dep->started_list);
72246da4
FB		 1766 }
1767
1768 return 0;
1769}
1770
6a1e3ef4
FB		 1771static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1772{
1773 int ret;
1774
1775 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1776
1777 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1778 if (ret < 0) {
73815280
FB		 1779 dwc3_trace(trace_dwc3_gadget,
1780 "failed to allocate OUT endpoints");
6a1e3ef4
FB		 1781 return ret;
1782 }
1783
1784 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1785 if (ret < 0) {
73815280
FB		 1786 dwc3_trace(trace_dwc3_gadget,
1787 "failed to allocate IN endpoints");
6a1e3ef4
FB		 1788 return ret;
1789 }
1790
1791 return 0;
1792}
1793
72246da4
FB		 1794static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1795{
1796 struct dwc3_ep *dep;
1797 u8 epnum;
1798
1799 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1800 dep = dwc->eps[epnum];
6a1e3ef4
FB		 1801 if (!dep)
1802 continue;
5bf8fae3
GC		 1803 /*
1804 * Physical endpoints 0 and 1 are special; they form the
1805 * bi-directional USB endpoint 0.
1806 *
1807 * For those two physical endpoints, we don't allocate a TRB
1808 * pool nor do we add them the endpoints list. Due to that, we
1809 * shouldn't do these two operations otherwise we would end up
1810 * with all sorts of bugs when removing dwc3.ko.
1811 */
1812 if (epnum != 0 && epnum != 1) {
1813 dwc3_free_trb_pool(dep);
72246da4 1814 list_del(&dep->endpoint.ep_list);
5bf8fae3 1815 }
72246da4
FB		 1816
1817 kfree(dep);
1818 }
1819}
1820
72246da4 1821/* -------------------------------------------------------------------------- */
e5caff68 1822
e5ba5ec8
PA		 1823static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1824 struct dwc3_request *req, struct dwc3_trb *trb,
72246da4
FB		 1825 const struct dwc3_event_depevt *event, int status)
1826{
72246da4
FB		 1827 unsigned int count;
1828 unsigned int s_pkt = 0;
d6d6ec7b 1829 unsigned int trb_status;
72246da4 1830
2c4cbe6e
FB		 1831 trace_dwc3_complete_trb(dep, trb);
1832
e5ba5ec8
PA		 1833 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1834 /*
1835 * We continue despite the error. There is not much we
1836 * can do. If we don't clean it up we loop forever. If
1837 * we skip the TRB then it gets overwritten after a
1838 * while since we use them in a ring buffer. A BUG()
1839 * would help. Lets hope that if this occurs, someone
1840 * fixes the root cause instead of looking away :)
1841 */
1842 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1843 dep->name, trb);
1844 count = trb->size & DWC3_TRB_SIZE_MASK;
1845
1846 if (dep->direction) {
1847 if (count) {
1848 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1849 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
ec5e795c
FB		 1850 dwc3_trace(trace_dwc3_gadget,
1851 "%s: incomplete IN transfer\n",
e5ba5ec8
PA		 1852 dep->name);
1853 /*
1854 * If missed isoc occurred and there is
1855 * no request queued then issue END
1856 * TRANSFER, so that core generates
1857 * next xfernotready and we will issue
1858 * a fresh START TRANSFER.
1859 * If there are still queued request
1860 * then wait, do not issue either END
1861 * or UPDATE TRANSFER, just attach next
aa3342c8 1862 * request in pending_list during
e5ba5ec8
PA		 1863 * giveback.If any future queued request
1864 * is successfully transferred then we
1865 * will issue UPDATE TRANSFER for all
aa3342c8 1866 * request in the pending_list.
e5ba5ec8
PA		 1867 */
1868 dep->flags |= DWC3_EP_MISSED_ISOC;
1869 } else {
1870 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1871 dep->name);
1872 status = -ECONNRESET;
1873 }
1874 } else {
1875 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1876 }
1877 } else {
1878 if (count && (event->status & DEPEVT_STATUS_SHORT))
1879 s_pkt = 1;
1880 }
1881
1882 /*
1883 * We assume here we will always receive the entire data block
1884 * which we should receive. Meaning, if we program RX to
1885 * receive 4K but we receive only 2K, we assume that's all we
1886 * should receive and we simply bounce the request back to the
1887 * gadget driver for further processing.
1888 */
1889 req->request.actual += req->request.length - count;
1890 if (s_pkt)
1891 return 1;
1892 if ((event->status & DEPEVT_STATUS_LST) &&
1893 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1894 DWC3_TRB_CTRL_HWO)))
1895 return 1;
1896 if ((event->status & DEPEVT_STATUS_IOC) &&
1897 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1898 return 1;
1899 return 0;
1900}
1901
1902static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1903 const struct dwc3_event_depevt *event, int status)
1904{
1905 struct dwc3_request *req;
1906 struct dwc3_trb *trb;
1907 unsigned int slot;
1908 unsigned int i;
1909 int ret;
1910
72246da4 1911 do {
aa3342c8 1912 req = next_request(&dep->started_list);
ac7bdcc1 1913 if (WARN_ON_ONCE(!req))
d115d705 1914 return 1;
ac7bdcc1 1915
d115d705
VS		 1916 i = 0;
1917 do {
1918 slot = req->start_slot + i;
1919 if ((slot == DWC3_TRB_NUM - 1) &&
e5ba5ec8 1920 usb_endpoint_xfer_isoc(dep->endpoint.desc))
d115d705
VS		 1921 slot++;
1922 slot %= DWC3_TRB_NUM;
1923 trb = &dep->trb_pool[slot];
1924
1925 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1926 event, status);
1927 if (ret)
1928 break;
1929 } while (++i < req->request.num_mapped_sgs);
1930
1931 dwc3_gadget_giveback(dep, req, status);
e5ba5ec8
PA		 1932
1933 if (ret)
72246da4 1934 break;
d115d705 1935 } while (1);
72246da4 1936
cdc359dd 1937 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
aa3342c8
FB		 1938 list_empty(&dep->started_list)) {
1939 if (list_empty(&dep->pending_list)) {
cdc359dd
PA		 1940 /*
1941 * If there is no entry in request list then do
1942 * not issue END TRANSFER now. Just set PENDING
1943 * flag, so that END TRANSFER is issued when an
1944 * entry is added into request list.
1945 */
1946 dep->flags = DWC3_EP_PENDING_REQUEST;
1947 } else {
b992e681 1948 dwc3_stop_active_transfer(dwc, dep->number, true);
cdc359dd
PA		 1949 dep->flags = DWC3_EP_ENABLED;
1950 }
7efea86c
PA		 1951 return 1;
1952 }
1953
72246da4
FB		 1954 return 1;
1955}
1956
1957static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
029d97ff 1958 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
72246da4
FB		 1959{
1960 unsigned status = 0;
1961 int clean_busy;
e18b7975
FB		 1962 u32 is_xfer_complete;
1963
1964 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
72246da4
FB		 1965
1966 if (event->status & DEPEVT_STATUS_BUSERR)
1967 status = -ECONNRESET;
1968
1d046793 1969 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
e18b7975
FB		 1970 if (clean_busy && (is_xfer_complete ||
1971 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
72246da4 1972 dep->flags &= ~DWC3_EP_BUSY;
fae2b904
FB		 1973
1974 /*
1975 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1976 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1977 */
1978 if (dwc->revision < DWC3_REVISION_183A) {
1979 u32 reg;
1980 int i;
1981
1982 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
348e026f 1983 dep = dwc->eps[i];
fae2b904
FB		 1984
1985 if (!(dep->flags & DWC3_EP_ENABLED))
1986 continue;
1987
aa3342c8 1988 if (!list_empty(&dep->started_list))
fae2b904
FB		 1989 return;
1990 }
1991
1992 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1993 reg |= dwc->u1u2;
1994 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1995
1996 dwc->u1u2 = 0;
1997 }
8a1a9c9e 1998
e6e709b7 1999 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8a1a9c9e
FB		 2000 int ret;
2001
e6e709b7 2002 ret = __dwc3_gadget_kick_transfer(dep, 0, is_xfer_complete);
8a1a9c9e
FB		 2003 if (!ret || ret == -EBUSY)
2004 return;
2005 }
72246da4
FB		 2006}
2007
72246da4
FB		 2008static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2009 const struct dwc3_event_depevt *event)
2010{
2011 struct dwc3_ep *dep;
2012 u8 epnum = event->endpoint_number;
2013
2014 dep = dwc->eps[epnum];
2015
3336abb5
FB		 2016 if (!(dep->flags & DWC3_EP_ENABLED))
2017 return;
2018
72246da4
FB		 2019 if (epnum == 0 || epnum == 1) {
2020 dwc3_ep0_interrupt(dwc, event);
2021 return;
2022 }
2023
2024 switch (event->endpoint_event) {
2025 case DWC3_DEPEVT_XFERCOMPLETE:
b4996a86 2026 dep->resource_index = 0;
c2df85ca 2027
16e78db7 2028 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
ec5e795c
FB		 2029 dwc3_trace(trace_dwc3_gadget,
2030 "%s is an Isochronous endpoint\n",
72246da4
FB		 2031 dep->name);
2032 return;
2033 }
2034
029d97ff 2035 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2036 break;
2037 case DWC3_DEPEVT_XFERINPROGRESS:
029d97ff 2038 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2039 break;
2040 case DWC3_DEPEVT_XFERNOTREADY:
16e78db7 2041 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 2042 dwc3_gadget_start_isoc(dwc, dep, event);
2043 } else {
6bb4fe12 2044 int active;
72246da4
FB		 2045 int ret;
2046
6bb4fe12
FB		 2047 active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2048
73815280 2049 dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
6bb4fe12 2050 dep->name, active ? "Transfer Active"
72246da4
FB		 2051 : "Transfer Not Active");
2052
6bb4fe12 2053 ret = __dwc3_gadget_kick_transfer(dep, 0, !active);
72246da4
FB		 2054 if (!ret || ret == -EBUSY)
2055 return;
2056
ec5e795c
FB		 2057 dwc3_trace(trace_dwc3_gadget,
2058 "%s: failed to kick transfers\n",
72246da4
FB		 2059 dep->name);
2060 }
2061
879631aa
FB		 2062 break;
2063 case DWC3_DEPEVT_STREAMEVT:
16e78db7 2064 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
879631aa
FB		 2065 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2066 dep->name);
2067 return;
2068 }
2069
2070 switch (event->status) {
2071 case DEPEVT_STREAMEVT_FOUND:
73815280
FB		 2072 dwc3_trace(trace_dwc3_gadget,
2073 "Stream %d found and started",
879631aa
FB		 2074 event->parameters);
2075
2076 break;
2077 case DEPEVT_STREAMEVT_NOTFOUND:
2078 /* FALLTHROUGH */
2079 default:
ec5e795c
FB		 2080 dwc3_trace(trace_dwc3_gadget,
2081 "unable to find suitable stream\n");
879631aa 2082 }
72246da4
FB		 2083 break;
2084 case DWC3_DEPEVT_RXTXFIFOEVT:
ec5e795c 2085 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name);
72246da4 2086 break;
72246da4 2087 case DWC3_DEPEVT_EPCMDCMPLT:
73815280 2088 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
72246da4
FB		 2089 break;
2090 }
2091}
2092
2093static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2094{
2095 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2096 spin_unlock(&dwc->lock);
2097 dwc->gadget_driver->disconnect(&dwc->gadget);
2098 spin_lock(&dwc->lock);
2099 }
2100}
2101
bc5ba2e0
FB		 2102static void dwc3_suspend_gadget(struct dwc3 *dwc)
2103{
73a30bfc 2104 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
bc5ba2e0
FB		 2105 spin_unlock(&dwc->lock);
2106 dwc->gadget_driver->suspend(&dwc->gadget);
2107 spin_lock(&dwc->lock);
2108 }
2109}
2110
2111static void dwc3_resume_gadget(struct dwc3 *dwc)
2112{
73a30bfc 2113 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
bc5ba2e0
FB		 2114 spin_unlock(&dwc->lock);
2115 dwc->gadget_driver->resume(&dwc->gadget);
5c7b3b02 2116 spin_lock(&dwc->lock);
8e74475b
FB		 2117 }
2118}
2119
2120static void dwc3_reset_gadget(struct dwc3 *dwc)
2121{
2122 if (!dwc->gadget_driver)
2123 return;
2124
2125 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2126 spin_unlock(&dwc->lock);
2127 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
bc5ba2e0
FB		 2128 spin_lock(&dwc->lock);
2129 }
2130}
2131
b992e681 2132static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
72246da4
FB		 2133{
2134 struct dwc3_ep *dep;
2135 struct dwc3_gadget_ep_cmd_params params;
2136 u32 cmd;
2137 int ret;
2138
2139 dep = dwc->eps[epnum];
2140
b4996a86 2141 if (!dep->resource_index)
3daf74d7
PA		 2142 return;
2143
57911504
PA		 2144 /*
2145 * NOTICE: We are violating what the Databook says about the
2146 * EndTransfer command. Ideally we would _always_ wait for the
2147 * EndTransfer Command Completion IRQ, but that's causing too
2148 * much trouble synchronizing between us and gadget driver.
2149 *
2150 * We have discussed this with the IP Provider and it was
2151 * suggested to giveback all requests here, but give HW some
2152 * extra time to synchronize with the interconnect. We're using
dc93b41a 2153 * an arbitrary 100us delay for that.
57911504
PA		 2154 *
2155 * Note also that a similar handling was tested by Synopsys
2156 * (thanks a lot Paul) and nothing bad has come out of it.
2157 * In short, what we're doing is:
2158 *
2159 * - Issue EndTransfer WITH CMDIOC bit set
2160 * - Wait 100us
2161 */
2162
3daf74d7 2163 cmd = DWC3_DEPCMD_ENDTRANSFER;
b992e681
PZ		 2164 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2165 cmd |= DWC3_DEPCMD_CMDIOC;
b4996a86 2166 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3daf74d7
PA		 2167 memset(&params, 0, sizeof(params));
2168 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
2169 WARN_ON_ONCE(ret);
b4996a86 2170 dep->resource_index = 0;
041d81f4 2171 dep->flags &= ~DWC3_EP_BUSY;
57911504 2172 udelay(100);
72246da4
FB		 2173}
2174
2175static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2176{
2177 u32 epnum;
2178
2179 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2180 struct dwc3_ep *dep;
2181
2182 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2183 if (!dep)
2184 continue;
2185
72246da4
FB		 2186 if (!(dep->flags & DWC3_EP_ENABLED))
2187 continue;
2188
624407f9 2189 dwc3_remove_requests(dwc, dep);
72246da4
FB		 2190 }
2191}
2192
2193static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2194{
2195 u32 epnum;
2196
2197 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2198 struct dwc3_ep *dep;
2199 struct dwc3_gadget_ep_cmd_params params;
2200 int ret;
2201
2202 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2203 if (!dep)
2204 continue;
72246da4
FB		 2205
2206 if (!(dep->flags & DWC3_EP_STALL))
2207 continue;
2208
2209 dep->flags &= ~DWC3_EP_STALL;
2210
2211 memset(&params, 0, sizeof(params));
2212 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2213 DWC3_DEPCMD_CLEARSTALL, &params);
2214 WARN_ON_ONCE(ret);
2215 }
2216}
2217
2218static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2219{
c4430a26
FB		 2220 int reg;
2221
72246da4
FB		 2222 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2223 reg &= ~DWC3_DCTL_INITU1ENA;
2224 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2225
2226 reg &= ~DWC3_DCTL_INITU2ENA;
2227 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 2228
72246da4
FB		 2229 dwc3_disconnect_gadget(dwc);
2230
2231 dwc->gadget.speed = USB_SPEED_UNKNOWN;
df62df56 2232 dwc->setup_packet_pending = false;
06a374ed 2233 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
72246da4
FB		 2234}
2235
72246da4
FB		 2236static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2237{
2238 u32 reg;
2239
df62df56
FB		 2240 /*
2241 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2242 * would cause a missing Disconnect Event if there's a
2243 * pending Setup Packet in the FIFO.
2244 *
2245 * There's no suggested workaround on the official Bug
2246 * report, which states that "unless the driver/application
2247 * is doing any special handling of a disconnect event,
2248 * there is no functional issue".
2249 *
2250 * Unfortunately, it turns out that we _do_ some special
2251 * handling of a disconnect event, namely complete all
2252 * pending transfers, notify gadget driver of the
2253 * disconnection, and so on.
2254 *
2255 * Our suggested workaround is to follow the Disconnect
2256 * Event steps here, instead, based on a setup_packet_pending
b5d335e5
FB		 2257 * flag. Such flag gets set whenever we have a SETUP_PENDING
2258 * status for EP0 TRBs and gets cleared on XferComplete for the
df62df56
FB		 2259 * same endpoint.
2260 *
2261 * Refers to:
2262 *
2263 * STAR#9000466709: RTL: Device : Disconnect event not
2264 * generated if setup packet pending in FIFO
2265 */
2266 if (dwc->revision < DWC3_REVISION_188A) {
2267 if (dwc->setup_packet_pending)
2268 dwc3_gadget_disconnect_interrupt(dwc);
2269 }
2270
8e74475b 2271 dwc3_reset_gadget(dwc);
72246da4
FB		 2272
2273 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2274 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2275 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3b637367 2276 dwc->test_mode = false;
72246da4
FB		 2277
2278 dwc3_stop_active_transfers(dwc);
2279 dwc3_clear_stall_all_ep(dwc);
2280
2281 /* Reset device address to zero */
2282 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2283 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2284 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
72246da4
FB		 2285}
2286
2287static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2288{
2289 u32 reg;
2290 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2291
2292 /*
2293 * We change the clock only at SS but I dunno why I would want to do
2294 * this. Maybe it becomes part of the power saving plan.
2295 */
2296
ee5cd41c
JY		 2297 if ((speed != DWC3_DSTS_SUPERSPEED) &&
2298 (speed != DWC3_DSTS_SUPERSPEED_PLUS))
72246da4
FB		 2299 return;
2300
2301 /*
2302 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2303 * each time on Connect Done.
2304 */
2305 if (!usb30_clock)
2306 return;
2307
2308 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2309 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2310 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2311}
2312
72246da4
FB		 2313static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2314{
72246da4
FB		 2315 struct dwc3_ep *dep;
2316 int ret;
2317 u32 reg;
2318 u8 speed;
2319
72246da4
FB		 2320 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2321 speed = reg & DWC3_DSTS_CONNECTSPD;
2322 dwc->speed = speed;
2323
2324 dwc3_update_ram_clk_sel(dwc, speed);
2325
2326 switch (speed) {
7580862b
JY		 2327 case DWC3_DCFG_SUPERSPEED_PLUS:
2328 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2329 dwc->gadget.ep0->maxpacket = 512;
2330 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2331 break;
72246da4 2332 case DWC3_DCFG_SUPERSPEED:
05870c5b
FB		 2333 /*
2334 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2335 * would cause a missing USB3 Reset event.
2336 *
2337 * In such situations, we should force a USB3 Reset
2338 * event by calling our dwc3_gadget_reset_interrupt()
2339 * routine.
2340 *
2341 * Refers to:
2342 *
2343 * STAR#9000483510: RTL: SS : USB3 reset event may
2344 * not be generated always when the link enters poll
2345 */
2346 if (dwc->revision < DWC3_REVISION_190A)
2347 dwc3_gadget_reset_interrupt(dwc);
2348
72246da4
FB		 2349 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2350 dwc->gadget.ep0->maxpacket = 512;
2351 dwc->gadget.speed = USB_SPEED_SUPER;
2352 break;
2353 case DWC3_DCFG_HIGHSPEED:
2354 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2355 dwc->gadget.ep0->maxpacket = 64;
2356 dwc->gadget.speed = USB_SPEED_HIGH;
2357 break;
2358 case DWC3_DCFG_FULLSPEED2:
2359 case DWC3_DCFG_FULLSPEED1:
2360 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2361 dwc->gadget.ep0->maxpacket = 64;
2362 dwc->gadget.speed = USB_SPEED_FULL;
2363 break;
2364 case DWC3_DCFG_LOWSPEED:
2365 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2366 dwc->gadget.ep0->maxpacket = 8;
2367 dwc->gadget.speed = USB_SPEED_LOW;
2368 break;
2369 }
2370
2b758350
PA		 2371 /* Enable USB2 LPM Capability */
2372
ee5cd41c
JY		 2373 if ((dwc->revision > DWC3_REVISION_194A) &&
2374 (speed != DWC3_DCFG_SUPERSPEED) &&
2375 (speed != DWC3_DCFG_SUPERSPEED_PLUS)) {
2b758350
PA		 2376 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2377 reg |= DWC3_DCFG_LPM_CAP;
2378 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2379
2380 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2381 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2382
460d098c 2383 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2b758350 2384
80caf7d2
HR		 2385 /*
2386 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2387 * DCFG.LPMCap is set, core responses with an ACK and the
2388 * BESL value in the LPM token is less than or equal to LPM
2389 * NYET threshold.
2390 */
2391 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2392 && dwc->has_lpm_erratum,
2393 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2394
2395 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2396 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2397
356363bf
FB		 2398 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2399 } else {
2400 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2401 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2b758350
PA		 2402 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2403 }
2404
72246da4 2405 dep = dwc->eps[0];
265b70a7
PZ		 2406 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2407 false);
72246da4
FB		 2408 if (ret) {
2409 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2410 return;
2411 }
2412
2413 dep = dwc->eps[1];
265b70a7
PZ		 2414 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2415 false);
72246da4
FB		 2416 if (ret) {
2417 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2418 return;
2419 }
2420
2421 /*
2422 * Configure PHY via GUSB3PIPECTLn if required.
2423 *
2424 * Update GTXFIFOSIZn
2425 *
2426 * In both cases reset values should be sufficient.
2427 */
2428}
2429
2430static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2431{
72246da4
FB		 2432 /*
2433 * TODO take core out of low power mode when that's
2434 * implemented.
2435 */
2436
ad14d4e0
JL		 2437 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2438 spin_unlock(&dwc->lock);
2439 dwc->gadget_driver->resume(&dwc->gadget);
2440 spin_lock(&dwc->lock);
2441 }
72246da4
FB		 2442}
2443
2444static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2445 unsigned int evtinfo)
2446{
fae2b904 2447 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
0b0cc1cd
FB		 2448 unsigned int pwropt;
2449
2450 /*
2451 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2452 * Hibernation mode enabled which would show up when device detects
2453 * host-initiated U3 exit.
2454 *
2455 * In that case, device will generate a Link State Change Interrupt
2456 * from U3 to RESUME which is only necessary if Hibernation is
2457 * configured in.
2458 *
2459 * There are no functional changes due to such spurious event and we
2460 * just need to ignore it.
2461 *
2462 * Refers to:
2463 *
2464 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2465 * operational mode
2466 */
2467 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2468 if ((dwc->revision < DWC3_REVISION_250A) &&
2469 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2470 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2471 (next == DWC3_LINK_STATE_RESUME)) {
73815280
FB		 2472 dwc3_trace(trace_dwc3_gadget,
2473 "ignoring transition U3 -> Resume");
0b0cc1cd
FB		 2474 return;
2475 }
2476 }
fae2b904
FB		 2477
2478 /*
2479 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2480 * on the link partner, the USB session might do multiple entry/exit
2481 * of low power states before a transfer takes place.
2482 *
2483 * Due to this problem, we might experience lower throughput. The
2484 * suggested workaround is to disable DCTL[12:9] bits if we're
2485 * transitioning from U1/U2 to U0 and enable those bits again
2486 * after a transfer completes and there are no pending transfers
2487 * on any of the enabled endpoints.
2488 *
2489 * This is the first half of that workaround.
2490 *
2491 * Refers to:
2492 *
2493 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2494 * core send LGO_Ux entering U0
2495 */
2496 if (dwc->revision < DWC3_REVISION_183A) {
2497 if (next == DWC3_LINK_STATE_U0) {
2498 u32 u1u2;
2499 u32 reg;
2500
2501 switch (dwc->link_state) {
2502 case DWC3_LINK_STATE_U1:
2503 case DWC3_LINK_STATE_U2:
2504 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2505 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2506 | DWC3_DCTL_ACCEPTU2ENA
2507 | DWC3_DCTL_INITU1ENA
2508 | DWC3_DCTL_ACCEPTU1ENA);
2509
2510 if (!dwc->u1u2)
2511 dwc->u1u2 = reg & u1u2;
2512
2513 reg &= ~u1u2;
2514
2515 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2516 break;
2517 default:
2518 /* do nothing */
2519 break;
2520 }
2521 }
2522 }
2523
bc5ba2e0
FB		 2524 switch (next) {
2525 case DWC3_LINK_STATE_U1:
2526 if (dwc->speed == USB_SPEED_SUPER)
2527 dwc3_suspend_gadget(dwc);
2528 break;
2529 case DWC3_LINK_STATE_U2:
2530 case DWC3_LINK_STATE_U3:
2531 dwc3_suspend_gadget(dwc);
2532 break;
2533 case DWC3_LINK_STATE_RESUME:
2534 dwc3_resume_gadget(dwc);
2535 break;
2536 default:
2537 /* do nothing */
2538 break;
2539 }
2540
e57ebc1d 2541 dwc->link_state = next;
72246da4
FB		 2542}
2543
e1dadd3b
FB		 2544static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2545 unsigned int evtinfo)
2546{
2547 unsigned int is_ss = evtinfo & BIT(4);
2548
2549 /**
2550 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2551 * have a known issue which can cause USB CV TD.9.23 to fail
2552 * randomly.
2553 *
2554 * Because of this issue, core could generate bogus hibernation
2555 * events which SW needs to ignore.
2556 *
2557 * Refers to:
2558 *
2559 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2560 * Device Fallback from SuperSpeed
2561 */
2562 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2563 return;
2564
2565 /* enter hibernation here */
2566}
2567
72246da4
FB		 2568static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2569 const struct dwc3_event_devt *event)
2570{
2571 switch (event->type) {
2572 case DWC3_DEVICE_EVENT_DISCONNECT:
2573 dwc3_gadget_disconnect_interrupt(dwc);
2574 break;
2575 case DWC3_DEVICE_EVENT_RESET:
2576 dwc3_gadget_reset_interrupt(dwc);
2577 break;
2578 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2579 dwc3_gadget_conndone_interrupt(dwc);
2580 break;
2581 case DWC3_DEVICE_EVENT_WAKEUP:
2582 dwc3_gadget_wakeup_interrupt(dwc);
2583 break;
e1dadd3b
FB		 2584 case DWC3_DEVICE_EVENT_HIBER_REQ:
2585 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2586 "unexpected hibernation event\n"))
2587 break;
2588
2589 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2590 break;
72246da4
FB		 2591 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2592 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2593 break;
2594 case DWC3_DEVICE_EVENT_EOPF:
73815280 2595 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
72246da4
FB		 2596 break;
2597 case DWC3_DEVICE_EVENT_SOF:
73815280 2598 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
72246da4
FB		 2599 break;
2600 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
73815280 2601 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
72246da4
FB		 2602 break;
2603 case DWC3_DEVICE_EVENT_CMD_CMPL:
73815280 2604 dwc3_trace(trace_dwc3_gadget, "Command Complete");
72246da4
FB		 2605 break;
2606 case DWC3_DEVICE_EVENT_OVERFLOW:
73815280 2607 dwc3_trace(trace_dwc3_gadget, "Overflow");
72246da4
FB		 2608 break;
2609 default:
e9f2aa87 2610 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
72246da4
FB		 2611 }
2612}
2613
2614static void dwc3_process_event_entry(struct dwc3 *dwc,
2615 const union dwc3_event *event)
2616{
2c4cbe6e
FB		 2617 trace_dwc3_event(event->raw);
2618
72246da4
FB		 2619 /* Endpoint IRQ, handle it and return early */
2620 if (event->type.is_devspec == 0) {
2621 /* depevt */
2622 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2623 }
2624
2625 switch (event->type.type) {
2626 case DWC3_EVENT_TYPE_DEV:
2627 dwc3_gadget_interrupt(dwc, &event->devt);
2628 break;
2629 /* REVISIT what to do with Carkit and I2C events ? */
2630 default:
2631 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2632 }
2633}
2634
dea520a4 2635static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
b15a762f 2636{
dea520a4 2637 struct dwc3 *dwc = evt->dwc;
b15a762f 2638 irqreturn_t ret = IRQ_NONE;
f42f2447 2639 int left;
e8adfc30 2640 u32 reg;
b15a762f 2641
f42f2447 2642 left = evt->count;
b15a762f 2643
f42f2447
FB		 2644 if (!(evt->flags & DWC3_EVENT_PENDING))
2645 return IRQ_NONE;
b15a762f 2646
f42f2447
FB		 2647 while (left > 0) {
2648 union dwc3_event event;
b15a762f 2649
f42f2447 2650 event.raw = *(u32 *) (evt->buf + evt->lpos);
b15a762f 2651
f42f2447 2652 dwc3_process_event_entry(dwc, &event);
b15a762f 2653
f42f2447
FB		 2654 /*
2655 * FIXME we wrap around correctly to the next entry as
2656 * almost all entries are 4 bytes in size. There is one
2657 * entry which has 12 bytes which is a regular entry
2658 * followed by 8 bytes data. ATM I don't know how
2659 * things are organized if we get next to the a
2660 * boundary so I worry about that once we try to handle
2661 * that.
2662 */
2663 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2664 left -= 4;
b15a762f 2665
660e9bde 2666 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4);
f42f2447 2667 }
b15a762f 2668
f42f2447
FB		 2669 evt->count = 0;
2670 evt->flags &= ~DWC3_EVENT_PENDING;
2671 ret = IRQ_HANDLED;
b15a762f 2672
f42f2447 2673 /* Unmask interrupt */
660e9bde 2674 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
f42f2447 2675 reg &= ~DWC3_GEVNTSIZ_INTMASK;
660e9bde 2676 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
b15a762f 2677
f42f2447
FB		 2678 return ret;
2679}
e8adfc30 2680
dea520a4 2681static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
f42f2447 2682{
dea520a4
FB		 2683 struct dwc3_event_buffer *evt = _evt;
2684 struct dwc3 *dwc = evt->dwc;
e5f68b4a 2685 unsigned long flags;
f42f2447 2686 irqreturn_t ret = IRQ_NONE;
f42f2447 2687
e5f68b4a 2688 spin_lock_irqsave(&dwc->lock, flags);
dea520a4 2689 ret = dwc3_process_event_buf(evt);
e5f68b4a 2690 spin_unlock_irqrestore(&dwc->lock, flags);
b15a762f
FB		 2691
2692 return ret;
2693}
2694
dea520a4 2695static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
72246da4 2696{
dea520a4 2697 struct dwc3 *dwc = evt->dwc;
72246da4 2698 u32 count;
e8adfc30 2699 u32 reg;
72246da4 2700
660e9bde 2701 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
72246da4
FB		 2702 count &= DWC3_GEVNTCOUNT_MASK;
2703 if (!count)
2704 return IRQ_NONE;
2705
b15a762f
FB		 2706 evt->count = count;
2707 evt->flags |= DWC3_EVENT_PENDING;
72246da4 2708
e8adfc30 2709 /* Mask interrupt */
660e9bde 2710 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
e8adfc30 2711 reg |= DWC3_GEVNTSIZ_INTMASK;
660e9bde 2712 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
e8adfc30 2713
b15a762f 2714 return IRQ_WAKE_THREAD;
72246da4
FB		 2715}
2716
dea520a4 2717static irqreturn_t dwc3_interrupt(int irq, void *_evt)
72246da4 2718{
dea520a4 2719 struct dwc3_event_buffer *evt = _evt;
72246da4 2720
dea520a4 2721 return dwc3_check_event_buf(evt);
72246da4
FB		 2722}
2723
2724/**
2725 * dwc3_gadget_init - Initializes gadget related registers
1d046793 2726 * @dwc: pointer to our controller context structure
72246da4
FB		 2727 *
2728 * Returns 0 on success otherwise negative errno.
2729 */
41ac7b3a 2730int dwc3_gadget_init(struct dwc3 *dwc)
72246da4 2731{
72246da4 2732 int ret;
72246da4
FB		 2733
2734 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2735 &dwc->ctrl_req_addr, GFP_KERNEL);
2736 if (!dwc->ctrl_req) {
2737 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2738 ret = -ENOMEM;
2739 goto err0;
2740 }
2741
2abd9d5f 2742 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
72246da4
FB		 2743 &dwc->ep0_trb_addr, GFP_KERNEL);
2744 if (!dwc->ep0_trb) {
2745 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2746 ret = -ENOMEM;
2747 goto err1;
2748 }
2749
3ef35faf 2750 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
72246da4 2751 if (!dwc->setup_buf) {
72246da4
FB		 2752 ret = -ENOMEM;
2753 goto err2;
2754 }
2755
5812b1c2 2756 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
3ef35faf
FB		 2757 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2758 GFP_KERNEL);
5812b1c2
FB		 2759 if (!dwc->ep0_bounce) {
2760 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2761 ret = -ENOMEM;
2762 goto err3;
2763 }
2764
04c03d10
FB		 2765 dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2766 if (!dwc->zlp_buf) {
2767 ret = -ENOMEM;
2768 goto err4;
2769 }
2770
72246da4 2771 dwc->gadget.ops = &dwc3_gadget_ops;
72246da4 2772 dwc->gadget.speed = USB_SPEED_UNKNOWN;
eeb720fb 2773 dwc->gadget.sg_supported = true;
72246da4 2774 dwc->gadget.name = "dwc3-gadget";
6a4290cc 2775 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
72246da4 2776
b9e51b2b
BM		 2777 /*
2778 * FIXME We might be setting max_speed to <SUPER, however versions
2779 * <2.20a of dwc3 have an issue with metastability (documented
2780 * elsewhere in this driver) which tells us we can't set max speed to
2781 * anything lower than SUPER.
2782 *
2783 * Because gadget.max_speed is only used by composite.c and function
2784 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2785 * to happen so we avoid sending SuperSpeed Capability descriptor
2786 * together with our BOS descriptor as that could confuse host into
2787 * thinking we can handle super speed.
2788 *
2789 * Note that, in fact, we won't even support GetBOS requests when speed
2790 * is less than super speed because we don't have means, yet, to tell
2791 * composite.c that we are USB 2.0 + LPM ECN.
2792 */
2793 if (dwc->revision < DWC3_REVISION_220A)
2794 dwc3_trace(trace_dwc3_gadget,
2795 "Changing max_speed on rev %08x\n",
2796 dwc->revision);
2797
2798 dwc->gadget.max_speed = dwc->maximum_speed;
2799
a4b9d94b
DC		 2800 /*
2801 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2802 * on ep out.
2803 */
2804 dwc->gadget.quirk_ep_out_aligned_size = true;
2805
72246da4
FB		 2806 /*
2807 * REVISIT: Here we should clear all pending IRQs to be
2808 * sure we're starting from a well known location.
2809 */
2810
2811 ret = dwc3_gadget_init_endpoints(dwc);
2812 if (ret)
04c03d10 2813 goto err5;
72246da4 2814
72246da4
FB		 2815 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2816 if (ret) {
2817 dev_err(dwc->dev, "failed to register udc\n");
04c03d10 2818 goto err5;
72246da4
FB		 2819 }
2820
2821 return 0;
2822
04c03d10
FB		 2823err5:
2824 kfree(dwc->zlp_buf);
2825
5812b1c2 2826err4:
e1f80467 2827 dwc3_gadget_free_endpoints(dwc);
3ef35faf
FB		 2828 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2829 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 2830
72246da4 2831err3:
0fc9a1be 2832 kfree(dwc->setup_buf);
72246da4
FB		 2833
2834err2:
2835 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2836 dwc->ep0_trb, dwc->ep0_trb_addr);
2837
2838err1:
2839 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2840 dwc->ctrl_req, dwc->ctrl_req_addr);
2841
2842err0:
2843 return ret;
2844}
2845
7415f17c
FB		 2846/* -------------------------------------------------------------------------- */
2847
72246da4
FB		 2848void dwc3_gadget_exit(struct dwc3 *dwc)
2849{
72246da4 2850 usb_del_gadget_udc(&dwc->gadget);
72246da4 2851
72246da4
FB		 2852 dwc3_gadget_free_endpoints(dwc);
2853
3ef35faf
FB		 2854 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2855 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 2856
0fc9a1be 2857 kfree(dwc->setup_buf);
04c03d10 2858 kfree(dwc->zlp_buf);
72246da4
FB		 2859
2860 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2861 dwc->ep0_trb, dwc->ep0_trb_addr);
2862
2863 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2864 dwc->ctrl_req, dwc->ctrl_req_addr);
72246da4 2865}
7415f17c 2866
0b0231aa 2867int dwc3_gadget_suspend(struct dwc3 *dwc)
7415f17c 2868{
7b2a0368 2869 if (dwc->pullups_connected) {
7415f17c 2870 dwc3_gadget_disable_irq(dwc);
7b2a0368
FB		 2871 dwc3_gadget_run_stop(dwc, true, true);
2872 }
7415f17c 2873
7415f17c
FB		 2874 __dwc3_gadget_ep_disable(dwc->eps[0]);
2875 __dwc3_gadget_ep_disable(dwc->eps[1]);
2876
2877 dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2878
2879 return 0;
2880}
2881
2882int dwc3_gadget_resume(struct dwc3 *dwc)
2883{
2884 struct dwc3_ep *dep;
2885 int ret;
2886
2887 /* Start with SuperSpeed Default */
2888 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2889
2890 dep = dwc->eps[0];
265b70a7
PZ		 2891 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2892 false);
7415f17c
FB		 2893 if (ret)
2894 goto err0;
2895
2896 dep = dwc->eps[1];
265b70a7
PZ		 2897 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2898 false);
7415f17c
FB		 2899 if (ret)
2900 goto err1;
2901
2902 /* begin to receive SETUP packets */
2903 dwc->ep0state = EP0_SETUP_PHASE;
2904 dwc3_ep0_out_start(dwc);
2905
2906 dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2907
0b0231aa
FB		 2908 if (dwc->pullups_connected) {
2909 dwc3_gadget_enable_irq(dwc);
2910 dwc3_gadget_run_stop(dwc, true, false);
2911 }
2912
7415f17c
FB		 2913 return 0;
2914
2915err1:
2916 __dwc3_gadget_ep_disable(dwc->eps[0]);
2917
2918err0:
2919 return ret;
2920}
Linux kernel - Deliverables
This page took 0.621571 seconds and 5 git commands to generate.