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usb: dwc3: move generic dwc3 code from gadget into core
[deliverable/linux.git] / drivers / usb / dwc3 / gadget.c
CommitLineData
72246da4
FB		 1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#include <linux/kernel.h>
40#include <linux/delay.h>
41#include <linux/slab.h>
42#include <linux/spinlock.h>
43#include <linux/platform_device.h>
44#include <linux/pm_runtime.h>
45#include <linux/interrupt.h>
46#include <linux/io.h>
47#include <linux/list.h>
48#include <linux/dma-mapping.h>
49
50#include <linux/usb/ch9.h>
51#include <linux/usb/gadget.h>
52
53#include "core.h"
54#include "gadget.h"
55#include "io.h"
56
57#define DMA_ADDR_INVALID (~(dma_addr_t)0)
58
59void dwc3_map_buffer_to_dma(struct dwc3_request *req)
60{
61 struct dwc3 *dwc = req->dep->dwc;
62
78c58a53
SAS		 63 if (req->request.length == 0) {
64 /* req->request.dma = dwc->setup_buf_addr; */
65 return;
66 }
67
72246da4
FB		 68 if (req->request.dma == DMA_ADDR_INVALID) {
69 req->request.dma = dma_map_single(dwc->dev, req->request.buf,
70 req->request.length, req->direction
71 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
72 req->mapped = true;
72246da4
FB		 73 }
74}
75
76void dwc3_unmap_buffer_from_dma(struct dwc3_request *req)
77{
78 struct dwc3 *dwc = req->dep->dwc;
79
78c58a53
SAS		 80 if (req->request.length == 0) {
81 req->request.dma = DMA_ADDR_INVALID;
82 return;
83 }
84
72246da4
FB		 85 if (req->mapped) {
86 dma_unmap_single(dwc->dev, req->request.dma,
87 req->request.length, req->direction
88 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
89 req->mapped = 0;
f198ead2 90 req->request.dma = DMA_ADDR_INVALID;
72246da4
FB		 91 }
92}
93
94void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
95 int status)
96{
97 struct dwc3 *dwc = dep->dwc;
98
99 if (req->queued) {
100 dep->busy_slot++;
101 /*
102 * Skip LINK TRB. We can't use req->trb and check for
103 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
104 * completed (not the LINK TRB).
105 */
106 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
107 usb_endpoint_xfer_isoc(dep->desc))
108 dep->busy_slot++;
109 }
110 list_del(&req->list);
111
112 if (req->request.status == -EINPROGRESS)
113 req->request.status = status;
114
115 dwc3_unmap_buffer_from_dma(req);
116
117 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
118 req, dep->name, req->request.actual,
119 req->request.length, status);
120
121 spin_unlock(&dwc->lock);
122 req->request.complete(&req->dep->endpoint, &req->request);
123 spin_lock(&dwc->lock);
124}
125
126static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
127{
128 switch (cmd) {
129 case DWC3_DEPCMD_DEPSTARTCFG:
130 return "Start New Configuration";
131 case DWC3_DEPCMD_ENDTRANSFER:
132 return "End Transfer";
133 case DWC3_DEPCMD_UPDATETRANSFER:
134 return "Update Transfer";
135 case DWC3_DEPCMD_STARTTRANSFER:
136 return "Start Transfer";
137 case DWC3_DEPCMD_CLEARSTALL:
138 return "Clear Stall";
139 case DWC3_DEPCMD_SETSTALL:
140 return "Set Stall";
141 case DWC3_DEPCMD_GETSEQNUMBER:
142 return "Get Data Sequence Number";
143 case DWC3_DEPCMD_SETTRANSFRESOURCE:
144 return "Set Endpoint Transfer Resource";
145 case DWC3_DEPCMD_SETEPCONFIG:
146 return "Set Endpoint Configuration";
147 default:
148 return "UNKNOWN command";
149 }
150}
151
152int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
153 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
154{
155 struct dwc3_ep *dep = dwc->eps[ep];
61d58242 156 u32 timeout = 500;
72246da4
FB		 157 u32 reg;
158
159 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
160 dep->name,
dc1c70a7
FB		 161 dwc3_gadget_ep_cmd_string(cmd), params->param0,
162 params->param1, params->param2);
72246da4 163
dc1c70a7
FB		 164 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
165 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
166 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
72246da4
FB		 167
168 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
169 do {
170 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
171 if (!(reg & DWC3_DEPCMD_CMDACT)) {
164f6e14
FB		 172 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
173 DWC3_DEPCMD_STATUS(reg));
72246da4
FB		 174 return 0;
175 }
176
177 /*
72246da4
FB		 178 * We can't sleep here, because it is also called from
179 * interrupt context.
180 */
181 timeout--;
182 if (!timeout)
183 return -ETIMEDOUT;
184
61d58242 185 udelay(1);
72246da4
FB		 186 } while (1);
187}
188
189static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
190 struct dwc3_trb_hw *trb)
191{
c439ef87 192 u32 offset = (char *) trb - (char *) dep->trb_pool;
72246da4
FB		 193
194 return dep->trb_pool_dma + offset;
195}
196
197static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
198{
199 struct dwc3 *dwc = dep->dwc;
200
201 if (dep->trb_pool)
202 return 0;
203
204 if (dep->number == 0 || dep->number == 1)
205 return 0;
206
207 dep->trb_pool = dma_alloc_coherent(dwc->dev,
208 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
209 &dep->trb_pool_dma, GFP_KERNEL);
210 if (!dep->trb_pool) {
211 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
212 dep->name);
213 return -ENOMEM;
214 }
215
216 return 0;
217}
218
219static void dwc3_free_trb_pool(struct dwc3_ep *dep)
220{
221 struct dwc3 *dwc = dep->dwc;
222
223 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
224 dep->trb_pool, dep->trb_pool_dma);
225
226 dep->trb_pool = NULL;
227 dep->trb_pool_dma = 0;
228}
229
230static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
231{
232 struct dwc3_gadget_ep_cmd_params params;
233 u32 cmd;
234
235 memset(&params, 0x00, sizeof(params));
236
237 if (dep->number != 1) {
238 cmd = DWC3_DEPCMD_DEPSTARTCFG;
239 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
b23c8439
PZ		 240 if (dep->number > 1) {
241 if (dwc->start_config_issued)
242 return 0;
243 dwc->start_config_issued = true;
72246da4 244 cmd |= DWC3_DEPCMD_PARAM(2);
b23c8439 245 }
72246da4
FB		 246
247 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
248 }
249
250 return 0;
251}
252
253static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
254 const struct usb_endpoint_descriptor *desc)
255{
256 struct dwc3_gadget_ep_cmd_params params;
257
258 memset(&params, 0x00, sizeof(params));
259
dc1c70a7
FB		 260 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
261 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc))
262 | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst);
72246da4 263
dc1c70a7
FB		 264 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
265 | DWC3_DEPCFG_XFER_NOT_READY_EN;
72246da4 266
879631aa 267 if (usb_endpoint_xfer_bulk(desc) && dep->endpoint.max_streams) {
dc1c70a7
FB		 268 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
269 | DWC3_DEPCFG_STREAM_EVENT_EN;
879631aa
FB		 270 dep->stream_capable = true;
271 }
272
72246da4 273 if (usb_endpoint_xfer_isoc(desc))
dc1c70a7 274 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
72246da4
FB		 275
276 /*
277 * We are doing 1:1 mapping for endpoints, meaning
278 * Physical Endpoints 2 maps to Logical Endpoint 2 and
279 * so on. We consider the direction bit as part of the physical
280 * endpoint number. So USB endpoint 0x81 is 0x03.
281 */
dc1c70a7 282 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
72246da4
FB		 283
284 /*
285 * We must use the lower 16 TX FIFOs even though
286 * HW might have more
287 */
288 if (dep->direction)
dc1c70a7 289 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
72246da4
FB		 290
291 if (desc->bInterval) {
dc1c70a7 292 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
72246da4
FB		 293 dep->interval = 1 << (desc->bInterval - 1);
294 }
295
296 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
297 DWC3_DEPCMD_SETEPCONFIG, &params);
298}
299
300static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
301{
302 struct dwc3_gadget_ep_cmd_params params;
303
304 memset(&params, 0x00, sizeof(params));
305
dc1c70a7 306 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
72246da4
FB		 307
308 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
309 DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
310}
311
312/**
313 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
314 * @dep: endpoint to be initialized
315 * @desc: USB Endpoint Descriptor
316 *
317 * Caller should take care of locking
318 */
319static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
320 const struct usb_endpoint_descriptor *desc)
321{
322 struct dwc3 *dwc = dep->dwc;
323 u32 reg;
324 int ret = -ENOMEM;
325
326 if (!(dep->flags & DWC3_EP_ENABLED)) {
327 ret = dwc3_gadget_start_config(dwc, dep);
328 if (ret)
329 return ret;
330 }
331
332 ret = dwc3_gadget_set_ep_config(dwc, dep, desc);
333 if (ret)
334 return ret;
335
336 if (!(dep->flags & DWC3_EP_ENABLED)) {
337 struct dwc3_trb_hw *trb_st_hw;
338 struct dwc3_trb_hw *trb_link_hw;
339 struct dwc3_trb trb_link;
340
341 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
342 if (ret)
343 return ret;
344
345 dep->desc = desc;
346 dep->type = usb_endpoint_type(desc);
347 dep->flags |= DWC3_EP_ENABLED;
348
349 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
350 reg |= DWC3_DALEPENA_EP(dep->number);
351 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
352
353 if (!usb_endpoint_xfer_isoc(desc))
354 return 0;
355
356 memset(&trb_link, 0, sizeof(trb_link));
357
358 /* Link TRB for ISOC. The HWO but is never reset */
359 trb_st_hw = &dep->trb_pool[0];
360
361 trb_link.bplh = dwc3_trb_dma_offset(dep, trb_st_hw);
362 trb_link.trbctl = DWC3_TRBCTL_LINK_TRB;
363 trb_link.hwo = true;
364
365 trb_link_hw = &dep->trb_pool[DWC3_TRB_NUM - 1];
366 dwc3_trb_to_hw(&trb_link, trb_link_hw);
367 }
368
369 return 0;
370}
371
624407f9
SAS		 372static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
373static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
72246da4
FB		 374{
375 struct dwc3_request *req;
376
624407f9
SAS		 377 if (!list_empty(&dep->req_queued))
378 dwc3_stop_active_transfer(dwc, dep->number);
379
72246da4
FB		 380 while (!list_empty(&dep->request_list)) {
381 req = next_request(&dep->request_list);
382
624407f9 383 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
72246da4 384 }
72246da4
FB		 385}
386
387/**
388 * __dwc3_gadget_ep_disable - Disables a HW endpoint
389 * @dep: the endpoint to disable
390 *
624407f9
SAS		 391 * This function also removes requests which are currently processed ny the
392 * hardware and those which are not yet scheduled.
393 * Caller should take care of locking.
72246da4 394 */
72246da4
FB		 395static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
396{
397 struct dwc3 *dwc = dep->dwc;
398 u32 reg;
399
624407f9 400 dwc3_remove_requests(dwc, dep);
72246da4
FB		 401
402 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
403 reg &= ~DWC3_DALEPENA_EP(dep->number);
404 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
405
879631aa 406 dep->stream_capable = false;
72246da4
FB		 407 dep->desc = NULL;
408 dep->type = 0;
879631aa 409 dep->flags = 0;
72246da4
FB		 410
411 return 0;
412}
413
414/* -------------------------------------------------------------------------- */
415
416static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
417 const struct usb_endpoint_descriptor *desc)
418{
419 return -EINVAL;
420}
421
422static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
423{
424 return -EINVAL;
425}
426
427/* -------------------------------------------------------------------------- */
428
429static int dwc3_gadget_ep_enable(struct usb_ep *ep,
430 const struct usb_endpoint_descriptor *desc)
431{
432 struct dwc3_ep *dep;
433 struct dwc3 *dwc;
434 unsigned long flags;
435 int ret;
436
437 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
438 pr_debug("dwc3: invalid parameters\n");
439 return -EINVAL;
440 }
441
442 if (!desc->wMaxPacketSize) {
443 pr_debug("dwc3: missing wMaxPacketSize\n");
444 return -EINVAL;
445 }
446
447 dep = to_dwc3_ep(ep);
448 dwc = dep->dwc;
449
450 switch (usb_endpoint_type(desc)) {
451 case USB_ENDPOINT_XFER_CONTROL:
452 strncat(dep->name, "-control", sizeof(dep->name));
453 break;
454 case USB_ENDPOINT_XFER_ISOC:
455 strncat(dep->name, "-isoc", sizeof(dep->name));
456 break;
457 case USB_ENDPOINT_XFER_BULK:
458 strncat(dep->name, "-bulk", sizeof(dep->name));
459 break;
460 case USB_ENDPOINT_XFER_INT:
461 strncat(dep->name, "-int", sizeof(dep->name));
462 break;
463 default:
464 dev_err(dwc->dev, "invalid endpoint transfer type\n");
465 }
466
467 if (dep->flags & DWC3_EP_ENABLED) {
468 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
469 dep->name);
470 return 0;
471 }
472
473 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
474
475 spin_lock_irqsave(&dwc->lock, flags);
476 ret = __dwc3_gadget_ep_enable(dep, desc);
477 spin_unlock_irqrestore(&dwc->lock, flags);
478
479 return ret;
480}
481
482static int dwc3_gadget_ep_disable(struct usb_ep *ep)
483{
484 struct dwc3_ep *dep;
485 struct dwc3 *dwc;
486 unsigned long flags;
487 int ret;
488
489 if (!ep) {
490 pr_debug("dwc3: invalid parameters\n");
491 return -EINVAL;
492 }
493
494 dep = to_dwc3_ep(ep);
495 dwc = dep->dwc;
496
497 if (!(dep->flags & DWC3_EP_ENABLED)) {
498 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
499 dep->name);
500 return 0;
501 }
502
503 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
504 dep->number >> 1,
505 (dep->number & 1) ? "in" : "out");
506
507 spin_lock_irqsave(&dwc->lock, flags);
508 ret = __dwc3_gadget_ep_disable(dep);
509 spin_unlock_irqrestore(&dwc->lock, flags);
510
511 return ret;
512}
513
514static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
515 gfp_t gfp_flags)
516{
517 struct dwc3_request *req;
518 struct dwc3_ep *dep = to_dwc3_ep(ep);
519 struct dwc3 *dwc = dep->dwc;
520
521 req = kzalloc(sizeof(*req), gfp_flags);
522 if (!req) {
523 dev_err(dwc->dev, "not enough memory\n");
524 return NULL;
525 }
526
527 req->epnum = dep->number;
528 req->dep = dep;
529 req->request.dma = DMA_ADDR_INVALID;
530
531 return &req->request;
532}
533
534static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
535 struct usb_request *request)
536{
537 struct dwc3_request *req = to_dwc3_request(request);
538
539 kfree(req);
540}
541
542/*
543 * dwc3_prepare_trbs - setup TRBs from requests
544 * @dep: endpoint for which requests are being prepared
545 * @starting: true if the endpoint is idle and no requests are queued.
546 *
547 * The functions goes through the requests list and setups TRBs for the
548 * transfers. The functions returns once there are not more TRBs available or
549 * it run out of requests.
550 */
551static struct dwc3_request *dwc3_prepare_trbs(struct dwc3_ep *dep,
552 bool starting)
553{
554 struct dwc3_request *req, *n, *ret = NULL;
555 struct dwc3_trb_hw *trb_hw;
556 struct dwc3_trb trb;
557 u32 trbs_left;
558
559 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
560
561 /* the first request must not be queued */
562 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
563 /*
564 * if busy & slot are equal than it is either full or empty. If we are
565 * starting to proceed requests then we are empty. Otherwise we ar
566 * full and don't do anything
567 */
568 if (!trbs_left) {
569 if (!starting)
570 return NULL;
571 trbs_left = DWC3_TRB_NUM;
572 /*
573 * In case we start from scratch, we queue the ISOC requests
574 * starting from slot 1. This is done because we use ring
575 * buffer and have no LST bit to stop us. Instead, we place
576 * IOC bit TRB_NUM/4. We try to avoid to having an interrupt
577 * after the first request so we start at slot 1 and have
578 * 7 requests proceed before we hit the first IOC.
579 * Other transfer types don't use the ring buffer and are
580 * processed from the first TRB until the last one. Since we
581 * don't wrap around we have to start at the beginning.
582 */
583 if (usb_endpoint_xfer_isoc(dep->desc)) {
584 dep->busy_slot = 1;
585 dep->free_slot = 1;
586 } else {
587 dep->busy_slot = 0;
588 dep->free_slot = 0;
589 }
590 }
591
592 /* The last TRB is a link TRB, not used for xfer */
593 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->desc))
594 return NULL;
595
596 list_for_each_entry_safe(req, n, &dep->request_list, list) {
597 unsigned int last_one = 0;
598 unsigned int cur_slot;
599
600 trb_hw = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
601 cur_slot = dep->free_slot;
602 dep->free_slot++;
603
604 /* Skip the LINK-TRB on ISOC */
605 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
606 usb_endpoint_xfer_isoc(dep->desc))
607 continue;
608
609 dwc3_gadget_move_request_queued(req);
610 memset(&trb, 0, sizeof(trb));
611 trbs_left--;
612
613 /* Is our TRB pool empty? */
614 if (!trbs_left)
615 last_one = 1;
616 /* Is this the last request? */
617 if (list_empty(&dep->request_list))
618 last_one = 1;
619
620 /*
621 * FIXME we shouldn't need to set LST bit always but we are
622 * facing some weird problem with the Hardware where it doesn't
623 * complete even though it has been previously started.
624 *
625 * While we're debugging the problem, as a workaround to
626 * multiple TRBs handling, use only one TRB at a time.
627 */
628 last_one = 1;
629
630 req->trb = trb_hw;
631 if (!ret)
632 ret = req;
633
634 trb.bplh = req->request.dma;
635
636 if (usb_endpoint_xfer_isoc(dep->desc)) {
637 trb.isp_imi = true;
638 trb.csp = true;
639 } else {
640 trb.lst = last_one;
641 }
642
879631aa
FB		 643 if (usb_endpoint_xfer_bulk(dep->desc) && dep->stream_capable)
644 trb.sid_sofn = req->request.stream_id;
645
72246da4
FB		 646 switch (usb_endpoint_type(dep->desc)) {
647 case USB_ENDPOINT_XFER_CONTROL:
648 trb.trbctl = DWC3_TRBCTL_CONTROL_SETUP;
649 break;
650
651 case USB_ENDPOINT_XFER_ISOC:
5a18999e 652 trb.trbctl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
72246da4
FB		 653
654 /* IOC every DWC3_TRB_NUM / 4 so we can refill */
655 if (!(cur_slot % (DWC3_TRB_NUM / 4)))
656 trb.ioc = last_one;
657 break;
658
659 case USB_ENDPOINT_XFER_BULK:
660 case USB_ENDPOINT_XFER_INT:
661 trb.trbctl = DWC3_TRBCTL_NORMAL;
662 break;
663 default:
664 /*
665 * This is only possible with faulty memory because we
666 * checked it already :)
667 */
668 BUG();
669 }
670
671 trb.length = req->request.length;
672 trb.hwo = true;
673
674 dwc3_trb_to_hw(&trb, trb_hw);
675 req->trb_dma = dwc3_trb_dma_offset(dep, trb_hw);
676
677 if (last_one)
678 break;
679 }
680
681 return ret;
682}
683
684static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
685 int start_new)
686{
687 struct dwc3_gadget_ep_cmd_params params;
688 struct dwc3_request *req;
689 struct dwc3 *dwc = dep->dwc;
690 int ret;
691 u32 cmd;
692
693 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
694 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
695 return -EBUSY;
696 }
697 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
698
699 /*
700 * If we are getting here after a short-out-packet we don't enqueue any
701 * new requests as we try to set the IOC bit only on the last request.
702 */
703 if (start_new) {
704 if (list_empty(&dep->req_queued))
705 dwc3_prepare_trbs(dep, start_new);
706
707 /* req points to the first request which will be sent */
708 req = next_request(&dep->req_queued);
709 } else {
710 /*
711 * req points to the first request where HWO changed
712 * from 0 to 1
713 */
714 req = dwc3_prepare_trbs(dep, start_new);
715 }
716 if (!req) {
717 dep->flags |= DWC3_EP_PENDING_REQUEST;
718 return 0;
719 }
720
721 memset(&params, 0, sizeof(params));
dc1c70a7
FB		 722 params.param0 = upper_32_bits(req->trb_dma);
723 params.param1 = lower_32_bits(req->trb_dma);
72246da4
FB		 724
725 if (start_new)
726 cmd = DWC3_DEPCMD_STARTTRANSFER;
727 else
728 cmd = DWC3_DEPCMD_UPDATETRANSFER;
729
730 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
731 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
732 if (ret < 0) {
733 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
734
735 /*
736 * FIXME we need to iterate over the list of requests
737 * here and stop, unmap, free and del each of the linked
738 * requests instead of we do now.
739 */
740 dwc3_unmap_buffer_from_dma(req);
741 list_del(&req->list);
742 return ret;
743 }
744
745 dep->flags |= DWC3_EP_BUSY;
746 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
747 dep->number);
748 if (!dep->res_trans_idx)
749 printk_once(KERN_ERR "%s() res_trans_idx is invalid\n", __func__);
750 return 0;
751}
752
753static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
754{
755 req->request.actual = 0;
756 req->request.status = -EINPROGRESS;
757 req->direction = dep->direction;
758 req->epnum = dep->number;
759
760 /*
761 * We only add to our list of requests now and
762 * start consuming the list once we get XferNotReady
763 * IRQ.
764 *
765 * That way, we avoid doing anything that we don't need
766 * to do now and defer it until the point we receive a
767 * particular token from the Host side.
768 *
769 * This will also avoid Host cancelling URBs due to too
770 * many NACKs.
771 */
772 dwc3_map_buffer_to_dma(req);
773 list_add_tail(&req->list, &dep->request_list);
774
775 /*
776 * There is one special case: XferNotReady with
777 * empty list of requests. We need to kick the
778 * transfer here in that situation, otherwise
779 * we will be NAKing forever.
780 *
781 * If we get XferNotReady before gadget driver
782 * has a chance to queue a request, we will ACK
783 * the IRQ but won't be able to receive the data
784 * until the next request is queued. The following
785 * code is handling exactly that.
786 */
787 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
788 int ret;
789 int start_trans;
790
791 start_trans = 1;
792 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
793 dep->flags & DWC3_EP_BUSY)
794 start_trans = 0;
795
796 ret = __dwc3_gadget_kick_transfer(dep, 0, start_trans);
797 if (ret && ret != -EBUSY) {
798 struct dwc3 *dwc = dep->dwc;
799
800 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
801 dep->name);
802 }
803 };
804
805 return 0;
806}
807
808static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
809 gfp_t gfp_flags)
810{
811 struct dwc3_request *req = to_dwc3_request(request);
812 struct dwc3_ep *dep = to_dwc3_ep(ep);
813 struct dwc3 *dwc = dep->dwc;
814
815 unsigned long flags;
816
817 int ret;
818
819 if (!dep->desc) {
820 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
821 request, ep->name);
822 return -ESHUTDOWN;
823 }
824
825 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
826 request, ep->name, request->length);
827
828 spin_lock_irqsave(&dwc->lock, flags);
829 ret = __dwc3_gadget_ep_queue(dep, req);
830 spin_unlock_irqrestore(&dwc->lock, flags);
831
832 return ret;
833}
834
835static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
836 struct usb_request *request)
837{
838 struct dwc3_request *req = to_dwc3_request(request);
839 struct dwc3_request *r = NULL;
840
841 struct dwc3_ep *dep = to_dwc3_ep(ep);
842 struct dwc3 *dwc = dep->dwc;
843
844 unsigned long flags;
845 int ret = 0;
846
847 spin_lock_irqsave(&dwc->lock, flags);
848
849 list_for_each_entry(r, &dep->request_list, list) {
850 if (r == req)
851 break;
852 }
853
854 if (r != req) {
855 list_for_each_entry(r, &dep->req_queued, list) {
856 if (r == req)
857 break;
858 }
859 if (r == req) {
860 /* wait until it is processed */
861 dwc3_stop_active_transfer(dwc, dep->number);
862 goto out0;
863 }
864 dev_err(dwc->dev, "request %p was not queued to %s\n",
865 request, ep->name);
866 ret = -EINVAL;
867 goto out0;
868 }
869
870 /* giveback the request */
871 dwc3_gadget_giveback(dep, req, -ECONNRESET);
872
873out0:
874 spin_unlock_irqrestore(&dwc->lock, flags);
875
876 return ret;
877}
878
879int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
880{
881 struct dwc3_gadget_ep_cmd_params params;
882 struct dwc3 *dwc = dep->dwc;
883 int ret;
884
885 memset(&params, 0x00, sizeof(params));
886
887 if (value) {
0b7836a9
FB		 888 if (dep->number == 0 || dep->number == 1) {
889 /*
890 * Whenever EP0 is stalled, we will restart
891 * the state machine, thus moving back to
892 * Setup Phase
893 */
894 dwc->ep0state = EP0_SETUP_PHASE;
895 }
72246da4
FB		 896
897 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
898 DWC3_DEPCMD_SETSTALL, &params);
899 if (ret)
900 dev_err(dwc->dev, "failed to %s STALL on %s\n",
901 value ? "set" : "clear",
902 dep->name);
903 else
904 dep->flags |= DWC3_EP_STALL;
905 } else {
5275455a
PZ		 906 if (dep->flags & DWC3_EP_WEDGE)
907 return 0;
908
72246da4
FB		 909 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
910 DWC3_DEPCMD_CLEARSTALL, &params);
911 if (ret)
912 dev_err(dwc->dev, "failed to %s STALL on %s\n",
913 value ? "set" : "clear",
914 dep->name);
915 else
916 dep->flags &= ~DWC3_EP_STALL;
917 }
5275455a 918
72246da4
FB		 919 return ret;
920}
921
922static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
923{
924 struct dwc3_ep *dep = to_dwc3_ep(ep);
925 struct dwc3 *dwc = dep->dwc;
926
927 unsigned long flags;
928
929 int ret;
930
931 spin_lock_irqsave(&dwc->lock, flags);
932
933 if (usb_endpoint_xfer_isoc(dep->desc)) {
934 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
935 ret = -EINVAL;
936 goto out;
937 }
938
939 ret = __dwc3_gadget_ep_set_halt(dep, value);
940out:
941 spin_unlock_irqrestore(&dwc->lock, flags);
942
943 return ret;
944}
945
946static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
947{
948 struct dwc3_ep *dep = to_dwc3_ep(ep);
949
950 dep->flags |= DWC3_EP_WEDGE;
951
5275455a 952 return dwc3_gadget_ep_set_halt(ep, 1);
72246da4
FB		 953}
954
955/* -------------------------------------------------------------------------- */
956
957static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
958 .bLength = USB_DT_ENDPOINT_SIZE,
959 .bDescriptorType = USB_DT_ENDPOINT,
960 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
961};
962
963static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
964 .enable = dwc3_gadget_ep0_enable,
965 .disable = dwc3_gadget_ep0_disable,
966 .alloc_request = dwc3_gadget_ep_alloc_request,
967 .free_request = dwc3_gadget_ep_free_request,
968 .queue = dwc3_gadget_ep0_queue,
969 .dequeue = dwc3_gadget_ep_dequeue,
970 .set_halt = dwc3_gadget_ep_set_halt,
971 .set_wedge = dwc3_gadget_ep_set_wedge,
972};
973
974static const struct usb_ep_ops dwc3_gadget_ep_ops = {
975 .enable = dwc3_gadget_ep_enable,
976 .disable = dwc3_gadget_ep_disable,
977 .alloc_request = dwc3_gadget_ep_alloc_request,
978 .free_request = dwc3_gadget_ep_free_request,
979 .queue = dwc3_gadget_ep_queue,
980 .dequeue = dwc3_gadget_ep_dequeue,
981 .set_halt = dwc3_gadget_ep_set_halt,
982 .set_wedge = dwc3_gadget_ep_set_wedge,
983};
984
985/* -------------------------------------------------------------------------- */
986
987static int dwc3_gadget_get_frame(struct usb_gadget *g)
988{
989 struct dwc3 *dwc = gadget_to_dwc(g);
990 u32 reg;
991
992 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
993 return DWC3_DSTS_SOFFN(reg);
994}
995
996static int dwc3_gadget_wakeup(struct usb_gadget *g)
997{
998 struct dwc3 *dwc = gadget_to_dwc(g);
999
1000 unsigned long timeout;
1001 unsigned long flags;
1002
1003 u32 reg;
1004
1005 int ret = 0;
1006
1007 u8 link_state;
1008 u8 speed;
1009
1010 spin_lock_irqsave(&dwc->lock, flags);
1011
1012 /*
1013 * According to the Databook Remote wakeup request should
1014 * be issued only when the device is in early suspend state.
1015 *
1016 * We can check that via USB Link State bits in DSTS register.
1017 */
1018 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1019
1020 speed = reg & DWC3_DSTS_CONNECTSPD;
1021 if (speed == DWC3_DSTS_SUPERSPEED) {
1022 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1023 ret = -EINVAL;
1024 goto out;
1025 }
1026
1027 link_state = DWC3_DSTS_USBLNKST(reg);
1028
1029 switch (link_state) {
1030 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1031 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1032 break;
1033 default:
1034 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1035 link_state);
1036 ret = -EINVAL;
1037 goto out;
1038 }
1039
1040 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1041
1042 /*
1043 * Switch link state to Recovery. In HS/FS/LS this means
1044 * RemoteWakeup Request
1045 */
1046 reg |= DWC3_DCTL_ULSTCHNG_RECOVERY;
1047 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1048
1049 /* wait for at least 2000us */
1050 usleep_range(2000, 2500);
1051
1052 /* write zeroes to Link Change Request */
1053 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1054 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1055
1056 /* pool until Link State change to ON */
1057 timeout = jiffies + msecs_to_jiffies(100);
1058
1059 while (!(time_after(jiffies, timeout))) {
1060 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1061
1062 /* in HS, means ON */
1063 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1064 break;
1065 }
1066
1067 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1068 dev_err(dwc->dev, "failed to send remote wakeup\n");
1069 ret = -EINVAL;
1070 }
1071
1072out:
1073 spin_unlock_irqrestore(&dwc->lock, flags);
1074
1075 return ret;
1076}
1077
1078static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1079 int is_selfpowered)
1080{
1081 struct dwc3 *dwc = gadget_to_dwc(g);
1082
1083 dwc->is_selfpowered = !!is_selfpowered;
1084
1085 return 0;
1086}
1087
1088static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1089{
1090 u32 reg;
61d58242 1091 u32 timeout = 500;
72246da4
FB		 1092
1093 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1094 if (is_on)
1095 reg |= DWC3_DCTL_RUN_STOP;
1096 else
1097 reg &= ~DWC3_DCTL_RUN_STOP;
1098
1099 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1100
1101 do {
1102 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1103 if (is_on) {
1104 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1105 break;
1106 } else {
1107 if (reg & DWC3_DSTS_DEVCTRLHLT)
1108 break;
1109 }
72246da4
FB		 1110 timeout--;
1111 if (!timeout)
1112 break;
61d58242 1113 udelay(1);
72246da4
FB		 1114 } while (1);
1115
1116 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1117 dwc->gadget_driver
1118 ? dwc->gadget_driver->function : "no-function",
1119 is_on ? "connect" : "disconnect");
1120}
1121
1122static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1123{
1124 struct dwc3 *dwc = gadget_to_dwc(g);
1125 unsigned long flags;
1126
1127 is_on = !!is_on;
1128
1129 spin_lock_irqsave(&dwc->lock, flags);
1130 dwc3_gadget_run_stop(dwc, is_on);
1131 spin_unlock_irqrestore(&dwc->lock, flags);
1132
1133 return 0;
1134}
1135
1136static int dwc3_gadget_start(struct usb_gadget *g,
1137 struct usb_gadget_driver *driver)
1138{
1139 struct dwc3 *dwc = gadget_to_dwc(g);
1140 struct dwc3_ep *dep;
1141 unsigned long flags;
1142 int ret = 0;
1143 u32 reg;
1144
1145 spin_lock_irqsave(&dwc->lock, flags);
1146
1147 if (dwc->gadget_driver) {
1148 dev_err(dwc->dev, "%s is already bound to %s\n",
1149 dwc->gadget.name,
1150 dwc->gadget_driver->driver.name);
1151 ret = -EBUSY;
1152 goto err0;
1153 }
1154
1155 dwc->gadget_driver = driver;
1156 dwc->gadget.dev.driver = &driver->driver;
1157
72246da4
FB		 1158 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1159 reg &= ~(DWC3_DCFG_SPEED_MASK);
6c167fc9 1160 reg |= dwc->maximum_speed;
72246da4
FB		 1161 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1162
b23c8439
PZ		 1163 dwc->start_config_issued = false;
1164
72246da4
FB		 1165 /* Start with SuperSpeed Default */
1166 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1167
1168 dep = dwc->eps[0];
1169 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1170 if (ret) {
1171 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1172 goto err0;
1173 }
1174
1175 dep = dwc->eps[1];
1176 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1177 if (ret) {
1178 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1179 goto err1;
1180 }
1181
1182 /* begin to receive SETUP packets */
c7fcdeb2 1183 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 1184 dwc3_ep0_out_start(dwc);
1185
1186 spin_unlock_irqrestore(&dwc->lock, flags);
1187
1188 return 0;
1189
1190err1:
1191 __dwc3_gadget_ep_disable(dwc->eps[0]);
1192
1193err0:
1194 spin_unlock_irqrestore(&dwc->lock, flags);
1195
1196 return ret;
1197}
1198
1199static int dwc3_gadget_stop(struct usb_gadget *g,
1200 struct usb_gadget_driver *driver)
1201{
1202 struct dwc3 *dwc = gadget_to_dwc(g);
1203 unsigned long flags;
1204
1205 spin_lock_irqsave(&dwc->lock, flags);
1206
1207 __dwc3_gadget_ep_disable(dwc->eps[0]);
1208 __dwc3_gadget_ep_disable(dwc->eps[1]);
1209
1210 dwc->gadget_driver = NULL;
1211 dwc->gadget.dev.driver = NULL;
1212
1213 spin_unlock_irqrestore(&dwc->lock, flags);
1214
1215 return 0;
1216}
1217static const struct usb_gadget_ops dwc3_gadget_ops = {
1218 .get_frame = dwc3_gadget_get_frame,
1219 .wakeup = dwc3_gadget_wakeup,
1220 .set_selfpowered = dwc3_gadget_set_selfpowered,
1221 .pullup = dwc3_gadget_pullup,
1222 .udc_start = dwc3_gadget_start,
1223 .udc_stop = dwc3_gadget_stop,
1224};
1225
1226/* -------------------------------------------------------------------------- */
1227
1228static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1229{
1230 struct dwc3_ep *dep;
1231 u8 epnum;
1232
1233 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1234
1235 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1236 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1237 if (!dep) {
1238 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1239 epnum);
1240 return -ENOMEM;
1241 }
1242
1243 dep->dwc = dwc;
1244 dep->number = epnum;
1245 dwc->eps[epnum] = dep;
1246
1247 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1248 (epnum & 1) ? "in" : "out");
1249 dep->endpoint.name = dep->name;
1250 dep->direction = (epnum & 1);
1251
1252 if (epnum == 0 || epnum == 1) {
1253 dep->endpoint.maxpacket = 512;
1254 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1255 if (!epnum)
1256 dwc->gadget.ep0 = &dep->endpoint;
1257 } else {
1258 int ret;
1259
1260 dep->endpoint.maxpacket = 1024;
12d36c16 1261 dep->endpoint.max_streams = 15;
72246da4
FB		 1262 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1263 list_add_tail(&dep->endpoint.ep_list,
1264 &dwc->gadget.ep_list);
1265
1266 ret = dwc3_alloc_trb_pool(dep);
1267 if (ret) {
1268 dev_err(dwc->dev, "%s: failed to allocate TRB pool\n", dep->name);
1269 return ret;
1270 }
1271 }
1272 INIT_LIST_HEAD(&dep->request_list);
1273 INIT_LIST_HEAD(&dep->req_queued);
1274 }
1275
1276 return 0;
1277}
1278
1279static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1280{
1281 struct dwc3_ep *dep;
1282 u8 epnum;
1283
1284 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1285 dep = dwc->eps[epnum];
1286 dwc3_free_trb_pool(dep);
1287
1288 if (epnum != 0 && epnum != 1)
1289 list_del(&dep->endpoint.ep_list);
1290
1291 kfree(dep);
1292 }
1293}
1294
1295static void dwc3_gadget_release(struct device *dev)
1296{
1297 dev_dbg(dev, "%s\n", __func__);
1298}
1299
1300/* -------------------------------------------------------------------------- */
1301static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1302 const struct dwc3_event_depevt *event, int status)
1303{
1304 struct dwc3_request *req;
1305 struct dwc3_trb trb;
1306 unsigned int count;
1307 unsigned int s_pkt = 0;
1308
1309 do {
1310 req = next_request(&dep->req_queued);
1311 if (!req)
1312 break;
1313
1314 dwc3_trb_to_nat(req->trb, &trb);
1315
0d2f4758
SAS		 1316 if (trb.hwo && status != -ESHUTDOWN)
1317 /*
1318 * We continue despite the error. There is not much we
1319 * can do. If we don't clean in up we loop for ever. If
1320 * we skip the TRB than it gets overwritten reused after
1321 * a while since we use them in a ring buffer. a BUG()
1322 * would help. Lets hope that if this occures, someone
1323 * fixes the root cause instead of looking away :)
1324 */
72246da4
FB		 1325 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1326 dep->name, req->trb);
72246da4
FB		 1327 count = trb.length;
1328
1329 if (dep->direction) {
1330 if (count) {
1331 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1332 dep->name);
1333 status = -ECONNRESET;
1334 }
1335 } else {
1336 if (count && (event->status & DEPEVT_STATUS_SHORT))
1337 s_pkt = 1;
1338 }
1339
1340 /*
1341 * We assume here we will always receive the entire data block
1342 * which we should receive. Meaning, if we program RX to
1343 * receive 4K but we receive only 2K, we assume that's all we
1344 * should receive and we simply bounce the request back to the
1345 * gadget driver for further processing.
1346 */
1347 req->request.actual += req->request.length - count;
1348 dwc3_gadget_giveback(dep, req, status);
1349 if (s_pkt)
1350 break;
1351 if ((event->status & DEPEVT_STATUS_LST) && trb.lst)
1352 break;
1353 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc)
1354 break;
1355 } while (1);
1356
1357 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc)
1358 return 0;
1359 return 1;
1360}
1361
1362static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1363 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1364 int start_new)
1365{
1366 unsigned status = 0;
1367 int clean_busy;
1368
1369 if (event->status & DEPEVT_STATUS_BUSERR)
1370 status = -ECONNRESET;
1371
1372 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
a1ae9be5 1373 if (clean_busy) {
72246da4 1374 dep->flags &= ~DWC3_EP_BUSY;
a1ae9be5
SAS		 1375 dep->res_trans_idx = 0;
1376 }
72246da4
FB		 1377}
1378
1379static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1380 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1381{
1382 u32 uf;
1383
1384 if (list_empty(&dep->request_list)) {
1385 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1386 dep->name);
1387 return;
1388 }
1389
1390 if (event->parameters) {
1391 u32 mask;
1392
1393 mask = ~(dep->interval - 1);
1394 uf = event->parameters & mask;
1395 /* 4 micro frames in the future */
1396 uf += dep->interval * 4;
1397 } else {
1398 uf = 0;
1399 }
1400
1401 __dwc3_gadget_kick_transfer(dep, uf, 1);
1402}
1403
1404static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep,
1405 const struct dwc3_event_depevt *event)
1406{
1407 struct dwc3 *dwc = dep->dwc;
1408 struct dwc3_event_depevt mod_ev = *event;
1409
1410 /*
1411 * We were asked to remove one requests. It is possible that this
1412 * request and a few other were started together and have the same
1413 * transfer index. Since we stopped the complete endpoint we don't
1414 * know how many requests were already completed (and not yet)
1415 * reported and how could be done (later). We purge them all until
1416 * the end of the list.
1417 */
1418 mod_ev.status = DEPEVT_STATUS_LST;
1419 dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN);
1420 dep->flags &= ~DWC3_EP_BUSY;
1421 /* pending requets are ignored and are queued on XferNotReady */
72246da4
FB		 1422}
1423
1424static void dwc3_ep_cmd_compl(struct dwc3_ep *dep,
1425 const struct dwc3_event_depevt *event)
1426{
1427 u32 param = event->parameters;
1428 u32 cmd_type = (param >> 8) & ((1 << 5) - 1);
1429
1430 switch (cmd_type) {
1431 case DWC3_DEPCMD_ENDTRANSFER:
1432 dwc3_process_ep_cmd_complete(dep, event);
1433 break;
1434 case DWC3_DEPCMD_STARTTRANSFER:
1435 dep->res_trans_idx = param & 0x7f;
1436 break;
1437 default:
1438 printk(KERN_ERR "%s() unknown /unexpected type: %d\n",
1439 __func__, cmd_type);
1440 break;
1441 };
1442}
1443
1444static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1445 const struct dwc3_event_depevt *event)
1446{
1447 struct dwc3_ep *dep;
1448 u8 epnum = event->endpoint_number;
1449
1450 dep = dwc->eps[epnum];
1451
1452 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1453 dwc3_ep_event_string(event->endpoint_event));
1454
1455 if (epnum == 0 || epnum == 1) {
1456 dwc3_ep0_interrupt(dwc, event);
1457 return;
1458 }
1459
1460 switch (event->endpoint_event) {
1461 case DWC3_DEPEVT_XFERCOMPLETE:
1462 if (usb_endpoint_xfer_isoc(dep->desc)) {
1463 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1464 dep->name);
1465 return;
1466 }
1467
1468 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1469 break;
1470 case DWC3_DEPEVT_XFERINPROGRESS:
1471 if (!usb_endpoint_xfer_isoc(dep->desc)) {
1472 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1473 dep->name);
1474 return;
1475 }
1476
1477 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1478 break;
1479 case DWC3_DEPEVT_XFERNOTREADY:
1480 if (usb_endpoint_xfer_isoc(dep->desc)) {
1481 dwc3_gadget_start_isoc(dwc, dep, event);
1482 } else {
1483 int ret;
1484
1485 dev_vdbg(dwc->dev, "%s: reason %s\n",
1486 dep->name, event->status
1487 ? "Transfer Active"
1488 : "Transfer Not Active");
1489
1490 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1491 if (!ret || ret == -EBUSY)
1492 return;
1493
1494 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1495 dep->name);
1496 }
1497
879631aa
FB		 1498 break;
1499 case DWC3_DEPEVT_STREAMEVT:
1500 if (!usb_endpoint_xfer_bulk(dep->desc)) {
1501 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1502 dep->name);
1503 return;
1504 }
1505
1506 switch (event->status) {
1507 case DEPEVT_STREAMEVT_FOUND:
1508 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1509 event->parameters);
1510
1511 break;
1512 case DEPEVT_STREAMEVT_NOTFOUND:
1513 /* FALLTHROUGH */
1514 default:
1515 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1516 }
72246da4
FB		 1517 break;
1518 case DWC3_DEPEVT_RXTXFIFOEVT:
1519 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1520 break;
72246da4
FB		 1521 case DWC3_DEPEVT_EPCMDCMPLT:
1522 dwc3_ep_cmd_compl(dep, event);
1523 break;
1524 }
1525}
1526
1527static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1528{
1529 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1530 spin_unlock(&dwc->lock);
1531 dwc->gadget_driver->disconnect(&dwc->gadget);
1532 spin_lock(&dwc->lock);
1533 }
1534}
1535
1536static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
1537{
1538 struct dwc3_ep *dep;
1539 struct dwc3_gadget_ep_cmd_params params;
1540 u32 cmd;
1541 int ret;
1542
1543 dep = dwc->eps[epnum];
1544
624407f9 1545 WARN_ON(!dep->res_trans_idx);
72246da4
FB		 1546 if (dep->res_trans_idx) {
1547 cmd = DWC3_DEPCMD_ENDTRANSFER;
1548 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
1549 cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx);
1550 memset(&params, 0, sizeof(params));
1551 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1552 WARN_ON_ONCE(ret);
a1ae9be5 1553 dep->res_trans_idx = 0;
72246da4
FB		 1554 }
1555}
1556
1557static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1558{
1559 u32 epnum;
1560
1561 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1562 struct dwc3_ep *dep;
1563
1564 dep = dwc->eps[epnum];
1565 if (!(dep->flags & DWC3_EP_ENABLED))
1566 continue;
1567
624407f9 1568 dwc3_remove_requests(dwc, dep);
72246da4
FB		 1569 }
1570}
1571
1572static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
1573{
1574 u32 epnum;
1575
1576 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1577 struct dwc3_ep *dep;
1578 struct dwc3_gadget_ep_cmd_params params;
1579 int ret;
1580
1581 dep = dwc->eps[epnum];
1582
1583 if (!(dep->flags & DWC3_EP_STALL))
1584 continue;
1585
1586 dep->flags &= ~DWC3_EP_STALL;
1587
1588 memset(&params, 0, sizeof(params));
1589 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1590 DWC3_DEPCMD_CLEARSTALL, &params);
1591 WARN_ON_ONCE(ret);
1592 }
1593}
1594
1595static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
1596{
1597 dev_vdbg(dwc->dev, "%s\n", __func__);
1598#if 0
1599 XXX
1600 U1/U2 is powersave optimization. Skip it for now. Anyway we need to
1601 enable it before we can disable it.
1602
1603 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1604 reg &= ~DWC3_DCTL_INITU1ENA;
1605 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1606
1607 reg &= ~DWC3_DCTL_INITU2ENA;
1608 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1609#endif
1610
1611 dwc3_stop_active_transfers(dwc);
1612 dwc3_disconnect_gadget(dwc);
b23c8439 1613 dwc->start_config_issued = false;
72246da4
FB		 1614
1615 dwc->gadget.speed = USB_SPEED_UNKNOWN;
1616}
1617
1618static void dwc3_gadget_usb3_phy_power(struct dwc3 *dwc, int on)
1619{
1620 u32 reg;
1621
1622 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1623
1624 if (on)
1625 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
1626 else
1627 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1628
1629 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1630}
1631
1632static void dwc3_gadget_usb2_phy_power(struct dwc3 *dwc, int on)
1633{
1634 u32 reg;
1635
1636 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1637
1638 if (on)
1639 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1640 else
1641 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1642
1643 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1644}
1645
1646static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
1647{
1648 u32 reg;
1649
1650 dev_vdbg(dwc->dev, "%s\n", __func__);
1651
1652 /* Enable PHYs */
1653 dwc3_gadget_usb2_phy_power(dwc, true);
1654 dwc3_gadget_usb3_phy_power(dwc, true);
1655
1656 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
1657 dwc3_disconnect_gadget(dwc);
1658
1659 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1660 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
1661 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1662
1663 dwc3_stop_active_transfers(dwc);
1664 dwc3_clear_stall_all_ep(dwc);
b23c8439 1665 dwc->start_config_issued = false;
72246da4
FB		 1666
1667 /* Reset device address to zero */
1668 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1669 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
1670 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
72246da4
FB		 1671}
1672
1673static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
1674{
1675 u32 reg;
1676 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
1677
1678 /*
1679 * We change the clock only at SS but I dunno why I would want to do
1680 * this. Maybe it becomes part of the power saving plan.
1681 */
1682
1683 if (speed != DWC3_DSTS_SUPERSPEED)
1684 return;
1685
1686 /*
1687 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
1688 * each time on Connect Done.
1689 */
1690 if (!usb30_clock)
1691 return;
1692
1693 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1694 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
1695 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1696}
1697
1698static void dwc3_gadget_disable_phy(struct dwc3 *dwc, u8 speed)
1699{
1700 switch (speed) {
1701 case USB_SPEED_SUPER:
1702 dwc3_gadget_usb2_phy_power(dwc, false);
1703 break;
1704 case USB_SPEED_HIGH:
1705 case USB_SPEED_FULL:
1706 case USB_SPEED_LOW:
1707 dwc3_gadget_usb3_phy_power(dwc, false);
1708 break;
1709 }
1710}
1711
1712static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
1713{
1714 struct dwc3_gadget_ep_cmd_params params;
1715 struct dwc3_ep *dep;
1716 int ret;
1717 u32 reg;
1718 u8 speed;
1719
1720 dev_vdbg(dwc->dev, "%s\n", __func__);
1721
1722 memset(&params, 0x00, sizeof(params));
1723
72246da4
FB		 1724 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1725 speed = reg & DWC3_DSTS_CONNECTSPD;
1726 dwc->speed = speed;
1727
1728 dwc3_update_ram_clk_sel(dwc, speed);
1729
1730 switch (speed) {
1731 case DWC3_DCFG_SUPERSPEED:
1732 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1733 dwc->gadget.ep0->maxpacket = 512;
1734 dwc->gadget.speed = USB_SPEED_SUPER;
1735 break;
1736 case DWC3_DCFG_HIGHSPEED:
1737 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
1738 dwc->gadget.ep0->maxpacket = 64;
1739 dwc->gadget.speed = USB_SPEED_HIGH;
1740 break;
1741 case DWC3_DCFG_FULLSPEED2:
1742 case DWC3_DCFG_FULLSPEED1:
1743 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
1744 dwc->gadget.ep0->maxpacket = 64;
1745 dwc->gadget.speed = USB_SPEED_FULL;
1746 break;
1747 case DWC3_DCFG_LOWSPEED:
1748 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
1749 dwc->gadget.ep0->maxpacket = 8;
1750 dwc->gadget.speed = USB_SPEED_LOW;
1751 break;
1752 }
1753
1754 /* Disable unneded PHY */
1755 dwc3_gadget_disable_phy(dwc, dwc->gadget.speed);
1756
1757 dep = dwc->eps[0];
1758 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1759 if (ret) {
1760 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1761 return;
1762 }
1763
1764 dep = dwc->eps[1];
1765 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1766 if (ret) {
1767 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1768 return;
1769 }
1770
1771 /*
1772 * Configure PHY via GUSB3PIPECTLn if required.
1773 *
1774 * Update GTXFIFOSIZn
1775 *
1776 * In both cases reset values should be sufficient.
1777 */
1778}
1779
1780static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
1781{
1782 dev_vdbg(dwc->dev, "%s\n", __func__);
1783
1784 /*
1785 * TODO take core out of low power mode when that's
1786 * implemented.
1787 */
1788
1789 dwc->gadget_driver->resume(&dwc->gadget);
1790}
1791
1792static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
1793 unsigned int evtinfo)
1794{
72246da4
FB		 1795 /* The fith bit says SuperSpeed yes or no. */
1796 dwc->link_state = evtinfo & DWC3_LINK_STATE_MASK;
019ac832
FB		 1797
1798 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
72246da4
FB		 1799}
1800
1801static void dwc3_gadget_interrupt(struct dwc3 *dwc,
1802 const struct dwc3_event_devt *event)
1803{
1804 switch (event->type) {
1805 case DWC3_DEVICE_EVENT_DISCONNECT:
1806 dwc3_gadget_disconnect_interrupt(dwc);
1807 break;
1808 case DWC3_DEVICE_EVENT_RESET:
1809 dwc3_gadget_reset_interrupt(dwc);
1810 break;
1811 case DWC3_DEVICE_EVENT_CONNECT_DONE:
1812 dwc3_gadget_conndone_interrupt(dwc);
1813 break;
1814 case DWC3_DEVICE_EVENT_WAKEUP:
1815 dwc3_gadget_wakeup_interrupt(dwc);
1816 break;
1817 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
1818 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
1819 break;
1820 case DWC3_DEVICE_EVENT_EOPF:
1821 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
1822 break;
1823 case DWC3_DEVICE_EVENT_SOF:
1824 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
1825 break;
1826 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
1827 dev_vdbg(dwc->dev, "Erratic Error\n");
1828 break;
1829 case DWC3_DEVICE_EVENT_CMD_CMPL:
1830 dev_vdbg(dwc->dev, "Command Complete\n");
1831 break;
1832 case DWC3_DEVICE_EVENT_OVERFLOW:
1833 dev_vdbg(dwc->dev, "Overflow\n");
1834 break;
1835 default:
1836 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
1837 }
1838}
1839
1840static void dwc3_process_event_entry(struct dwc3 *dwc,
1841 const union dwc3_event *event)
1842{
1843 /* Endpoint IRQ, handle it and return early */
1844 if (event->type.is_devspec == 0) {
1845 /* depevt */
1846 return dwc3_endpoint_interrupt(dwc, &event->depevt);
1847 }
1848
1849 switch (event->type.type) {
1850 case DWC3_EVENT_TYPE_DEV:
1851 dwc3_gadget_interrupt(dwc, &event->devt);
1852 break;
1853 /* REVISIT what to do with Carkit and I2C events ? */
1854 default:
1855 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
1856 }
1857}
1858
1859static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
1860{
1861 struct dwc3_event_buffer *evt;
1862 int left;
1863 u32 count;
1864
1865 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
1866 count &= DWC3_GEVNTCOUNT_MASK;
1867 if (!count)
1868 return IRQ_NONE;
1869
1870 evt = dwc->ev_buffs[buf];
1871 left = count;
1872
1873 while (left > 0) {
1874 union dwc3_event event;
1875
1876 memcpy(&event.raw, (evt->buf + evt->lpos), sizeof(event.raw));
1877 dwc3_process_event_entry(dwc, &event);
1878 /*
1879 * XXX we wrap around correctly to the next entry as almost all
1880 * entries are 4 bytes in size. There is one entry which has 12
1881 * bytes which is a regular entry followed by 8 bytes data. ATM
1882 * I don't know how things are organized if were get next to the
1883 * a boundary so I worry about that once we try to handle that.
1884 */
1885 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
1886 left -= 4;
1887
1888 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
1889 }
1890
1891 return IRQ_HANDLED;
1892}
1893
1894static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
1895{
1896 struct dwc3 *dwc = _dwc;
1897 int i;
1898 irqreturn_t ret = IRQ_NONE;
1899
1900 spin_lock(&dwc->lock);
1901
9f622b2a 1902 for (i = 0; i < dwc->num_event_buffers; i++) {
72246da4
FB		 1903 irqreturn_t status;
1904
1905 status = dwc3_process_event_buf(dwc, i);
1906 if (status == IRQ_HANDLED)
1907 ret = status;
1908 }
1909
1910 spin_unlock(&dwc->lock);
1911
1912 return ret;
1913}
1914
1915/**
1916 * dwc3_gadget_init - Initializes gadget related registers
1917 * @dwc: Pointer to out controller context structure
1918 *
1919 * Returns 0 on success otherwise negative errno.
1920 */
1921int __devinit dwc3_gadget_init(struct dwc3 *dwc)
1922{
1923 u32 reg;
1924 int ret;
1925 int irq;
1926
1927 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
1928 &dwc->ctrl_req_addr, GFP_KERNEL);
1929 if (!dwc->ctrl_req) {
1930 dev_err(dwc->dev, "failed to allocate ctrl request\n");
1931 ret = -ENOMEM;
1932 goto err0;
1933 }
1934
1935 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
1936 &dwc->ep0_trb_addr, GFP_KERNEL);
1937 if (!dwc->ep0_trb) {
1938 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
1939 ret = -ENOMEM;
1940 goto err1;
1941 }
1942
1943 dwc->setup_buf = dma_alloc_coherent(dwc->dev,
1944 sizeof(*dwc->setup_buf) * 2,
1945 &dwc->setup_buf_addr, GFP_KERNEL);
1946 if (!dwc->setup_buf) {
1947 dev_err(dwc->dev, "failed to allocate setup buffer\n");
1948 ret = -ENOMEM;
1949 goto err2;
1950 }
1951
5812b1c2
FB		 1952 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
1953 512, &dwc->ep0_bounce_addr, GFP_KERNEL);
1954 if (!dwc->ep0_bounce) {
1955 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
1956 ret = -ENOMEM;
1957 goto err3;
1958 }
1959
72246da4
FB		 1960 dev_set_name(&dwc->gadget.dev, "gadget");
1961
1962 dwc->gadget.ops = &dwc3_gadget_ops;
1963 dwc->gadget.is_dualspeed = true;
1964 dwc->gadget.speed = USB_SPEED_UNKNOWN;
1965 dwc->gadget.dev.parent = dwc->dev;
1966
1967 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
1968
1969 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms;
1970 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask;
1971 dwc->gadget.dev.release = dwc3_gadget_release;
1972 dwc->gadget.name = "dwc3-gadget";
1973
1974 /*
1975 * REVISIT: Here we should clear all pending IRQs to be
1976 * sure we're starting from a well known location.
1977 */
1978
1979 ret = dwc3_gadget_init_endpoints(dwc);
1980 if (ret)
5812b1c2 1981 goto err4;
72246da4
FB		 1982
1983 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1984
1985 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
1986 "dwc3", dwc);
1987 if (ret) {
1988 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1989 irq, ret);
5812b1c2 1990 goto err5;
72246da4
FB		 1991 }
1992
1993 /* Enable all but Start and End of Frame IRQs */
1994 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1995 DWC3_DEVTEN_EVNTOVERFLOWEN |
1996 DWC3_DEVTEN_CMDCMPLTEN |
1997 DWC3_DEVTEN_ERRTICERREN |
1998 DWC3_DEVTEN_WKUPEVTEN |
1999 DWC3_DEVTEN_ULSTCNGEN |
2000 DWC3_DEVTEN_CONNECTDONEEN |
2001 DWC3_DEVTEN_USBRSTEN |
2002 DWC3_DEVTEN_DISCONNEVTEN);
2003 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2004
2005 ret = device_register(&dwc->gadget.dev);
2006 if (ret) {
2007 dev_err(dwc->dev, "failed to register gadget device\n");
2008 put_device(&dwc->gadget.dev);
5812b1c2 2009 goto err6;
72246da4
FB		 2010 }
2011
2012 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2013 if (ret) {
2014 dev_err(dwc->dev, "failed to register udc\n");
5812b1c2 2015 goto err7;
72246da4
FB		 2016 }
2017
2018 return 0;
2019
5812b1c2 2020err7:
72246da4
FB		 2021 device_unregister(&dwc->gadget.dev);
2022
5812b1c2 2023err6:
72246da4
FB		 2024 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2025 free_irq(irq, dwc);
2026
5812b1c2 2027err5:
72246da4
FB		 2028 dwc3_gadget_free_endpoints(dwc);
2029
5812b1c2
FB		 2030err4:
2031 dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce,
2032 dwc->ep0_bounce_addr);
2033
72246da4
FB		 2034err3:
2035 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
2036 dwc->setup_buf, dwc->setup_buf_addr);
2037
2038err2:
2039 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2040 dwc->ep0_trb, dwc->ep0_trb_addr);
2041
2042err1:
2043 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2044 dwc->ctrl_req, dwc->ctrl_req_addr);
2045
2046err0:
2047 return ret;
2048}
2049
2050void dwc3_gadget_exit(struct dwc3 *dwc)
2051{
2052 int irq;
72246da4
FB		 2053
2054 usb_del_gadget_udc(&dwc->gadget);
2055 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2056
2057 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2058 free_irq(irq, dwc);
2059
72246da4
FB		 2060 dwc3_gadget_free_endpoints(dwc);
2061
5812b1c2
FB		 2062 dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce,
2063 dwc->ep0_bounce_addr);
2064
72246da4
FB		 2065 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
2066 dwc->setup_buf, dwc->setup_buf_addr);
2067
2068 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2069 dwc->ep0_trb, dwc->ep0_trb_addr);
2070
2071 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2072 dwc->ctrl_req, dwc->ctrl_req_addr);
2073
2074 device_unregister(&dwc->gadget.dev);
2075}
Linux kernel - Deliverables
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