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usb: musb: sunxi: support module autoloading
[deliverable/linux.git] / drivers / usb / dwc3 / gadget.c
CommitLineData
72246da4
FB		 1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
5945f789
FB		 9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
72246da4 12 *
5945f789
FB		 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
72246da4
FB		 17 */
18
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/list.h>
28#include <linux/dma-mapping.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32
80977dc9 33#include "debug.h"
72246da4
FB		 34#include "core.h"
35#include "gadget.h"
36#include "io.h"
37
04a9bfcd
FB		 38/**
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
42 *
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
45 * is passed
46 */
47int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
48{
49 u32 reg;
50
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
53
54 switch (mode) {
55 case TEST_J:
56 case TEST_K:
57 case TEST_SE0_NAK:
58 case TEST_PACKET:
59 case TEST_FORCE_EN:
60 reg |= mode << 1;
61 break;
62 default:
63 return -EINVAL;
64 }
65
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
67
68 return 0;
69}
70
911f1f88
PZ		 71/**
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
74 *
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
77 */
78int dwc3_gadget_get_link_state(struct dwc3 *dwc)
79{
80 u32 reg;
81
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
83
84 return DWC3_DSTS_USBLNKST(reg);
85}
86
8598bde7
FB		 87/**
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
91 *
92 * Caller should take care of locking. This function will
aee63e3c 93 * return 0 on success or -ETIMEDOUT.
8598bde7
FB		 94 */
95int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
96{
aee63e3c 97 int retries = 10000;
8598bde7
FB		 98 u32 reg;
99
802fde98
PZ		 100 /*
101 * Wait until device controller is ready. Only applies to 1.94a and
102 * later RTL.
103 */
104 if (dwc->revision >= DWC3_REVISION_194A) {
105 while (--retries) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
108 udelay(5);
109 else
110 break;
111 }
112
113 if (retries <= 0)
114 return -ETIMEDOUT;
115 }
116
8598bde7
FB		 117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
119
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
123
802fde98
PZ		 124 /*
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
127 */
128 if (dwc->revision >= DWC3_REVISION_194A)
129 return 0;
130
8598bde7 131 /* wait for a change in DSTS */
aed430e5 132 retries = 10000;
8598bde7
FB		 133 while (--retries) {
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
135
8598bde7
FB		 136 if (DWC3_DSTS_USBLNKST(reg) == state)
137 return 0;
138
aee63e3c 139 udelay(5);
8598bde7
FB		 140 }
141
73815280
FB		 142 dwc3_trace(trace_dwc3_gadget,
143 "link state change request timed out");
8598bde7
FB		 144
145 return -ETIMEDOUT;
146}
147
457e84b6
FB		 148/**
149 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
150 * @dwc: pointer to our context structure
151 *
152 * This function will a best effort FIFO allocation in order
153 * to improve FIFO usage and throughput, while still allowing
154 * us to enable as many endpoints as possible.
155 *
156 * Keep in mind that this operation will be highly dependent
157 * on the configured size for RAM1 - which contains TxFifo -,
158 * the amount of endpoints enabled on coreConsultant tool, and
159 * the width of the Master Bus.
160 *
161 * In the ideal world, we would always be able to satisfy the
162 * following equation:
163 *
164 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
165 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
166 *
167 * Unfortunately, due to many variables that's not always the case.
168 */
169int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
170{
171 int last_fifo_depth = 0;
172 int ram1_depth;
173 int fifo_size;
174 int mdwidth;
175 int num;
176
177 if (!dwc->needs_fifo_resize)
178 return 0;
179
180 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
181 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
182
183 /* MDWIDTH is represented in bits, we need it in bytes */
184 mdwidth >>= 3;
185
186 /*
187 * FIXME For now we will only allocate 1 wMaxPacketSize space
188 * for each enabled endpoint, later patches will come to
189 * improve this algorithm so that we better use the internal
190 * FIFO space
191 */
32702e96
JP		 192 for (num = 0; num < dwc->num_in_eps; num++) {
193 /* bit0 indicates direction; 1 means IN ep */
194 struct dwc3_ep *dep = dwc->eps[(num << 1) | 1];
2e81c36a 195 int mult = 1;
457e84b6
FB		 196 int tmp;
197
457e84b6
FB		 198 if (!(dep->flags & DWC3_EP_ENABLED))
199 continue;
200
16e78db7
IS		 201 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
202 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
2e81c36a
FB		 203 mult = 3;
204
205 /*
206 * REVISIT: the following assumes we will always have enough
207 * space available on the FIFO RAM for all possible use cases.
208 * Make sure that's true somehow and change FIFO allocation
209 * accordingly.
210 *
211 * If we have Bulk or Isochronous endpoints, we want
212 * them to be able to be very, very fast. So we're giving
213 * those endpoints a fifo_size which is enough for 3 full
214 * packets
215 */
216 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
457e84b6
FB		 217 tmp += mdwidth;
218
219 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
2e81c36a 220
457e84b6
FB		 221 fifo_size |= (last_fifo_depth << 16);
222
73815280 223 dwc3_trace(trace_dwc3_gadget, "%s: Fifo Addr %04x Size %d",
457e84b6
FB		 224 dep->name, last_fifo_depth, fifo_size & 0xffff);
225
32702e96 226 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
457e84b6
FB		 227
228 last_fifo_depth += (fifo_size & 0xffff);
229 }
230
231 return 0;
232}
233
72246da4
FB		 234void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
235 int status)
236{
237 struct dwc3 *dwc = dep->dwc;
e5ba5ec8 238 int i;
72246da4
FB		 239
240 if (req->queued) {
e5ba5ec8
PA		 241 i = 0;
242 do {
eeb720fb 243 dep->busy_slot++;
e5ba5ec8
PA		 244 /*
245 * Skip LINK TRB. We can't use req->trb and check for
246 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
247 * just completed (not the LINK TRB).
248 */
249 if (((dep->busy_slot & DWC3_TRB_MASK) ==
250 DWC3_TRB_NUM- 1) &&
16e78db7 251 usb_endpoint_xfer_isoc(dep->endpoint.desc))
e5ba5ec8
PA		 252 dep->busy_slot++;
253 } while(++i < req->request.num_mapped_sgs);
c9fda7d6 254 req->queued = false;
72246da4
FB		 255 }
256 list_del(&req->list);
eeb720fb 257 req->trb = NULL;
72246da4
FB		 258
259 if (req->request.status == -EINPROGRESS)
260 req->request.status = status;
261
0416e494
PA		 262 if (dwc->ep0_bounced && dep->number == 0)
263 dwc->ep0_bounced = false;
264 else
265 usb_gadget_unmap_request(&dwc->gadget, &req->request,
266 req->direction);
72246da4 267
2c4cbe6e 268 trace_dwc3_gadget_giveback(req);
72246da4
FB		 269
270 spin_unlock(&dwc->lock);
304f7e5e 271 usb_gadget_giveback_request(&dep->endpoint, &req->request);
72246da4
FB		 272 spin_lock(&dwc->lock);
273}
274
3ece0ec4 275int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
b09bb642
FB		 276{
277 u32 timeout = 500;
278 u32 reg;
279
2c4cbe6e 280 trace_dwc3_gadget_generic_cmd(cmd, param);
427c3df6 281
b09bb642
FB		 282 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
283 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
284
285 do {
286 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
287 if (!(reg & DWC3_DGCMD_CMDACT)) {
73815280
FB		 288 dwc3_trace(trace_dwc3_gadget,
289 "Command Complete --> %d",
b09bb642 290 DWC3_DGCMD_STATUS(reg));
891b1dc0
SSB		 291 if (DWC3_DGCMD_STATUS(reg))
292 return -EINVAL;
b09bb642
FB		 293 return 0;
294 }
295
296 /*
297 * We can't sleep here, because it's also called from
298 * interrupt context.
299 */
300 timeout--;
73815280
FB		 301 if (!timeout) {
302 dwc3_trace(trace_dwc3_gadget,
303 "Command Timed Out");
b09bb642 304 return -ETIMEDOUT;
73815280 305 }
b09bb642
FB		 306 udelay(1);
307 } while (1);
308}
309
72246da4
FB		 310int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
311 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
312{
313 struct dwc3_ep *dep = dwc->eps[ep];
61d58242 314 u32 timeout = 500;
72246da4
FB		 315 u32 reg;
316
2c4cbe6e 317 trace_dwc3_gadget_ep_cmd(dep, cmd, params);
72246da4 318
dc1c70a7
FB		 319 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
320 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
321 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
72246da4
FB		 322
323 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
324 do {
325 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
326 if (!(reg & DWC3_DEPCMD_CMDACT)) {
73815280
FB		 327 dwc3_trace(trace_dwc3_gadget,
328 "Command Complete --> %d",
164f6e14 329 DWC3_DEPCMD_STATUS(reg));
76e838c9
SSB		 330 if (DWC3_DEPCMD_STATUS(reg))
331 return -EINVAL;
72246da4
FB		 332 return 0;
333 }
334
335 /*
72246da4
FB		 336 * We can't sleep here, because it is also called from
337 * interrupt context.
338 */
339 timeout--;
73815280
FB		 340 if (!timeout) {
341 dwc3_trace(trace_dwc3_gadget,
342 "Command Timed Out");
72246da4 343 return -ETIMEDOUT;
73815280 344 }
72246da4 345
61d58242 346 udelay(1);
72246da4
FB		 347 } while (1);
348}
349
350static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
f6bafc6a 351 struct dwc3_trb *trb)
72246da4 352{
c439ef87 353 u32 offset = (char *) trb - (char *) dep->trb_pool;
72246da4
FB		 354
355 return dep->trb_pool_dma + offset;
356}
357
358static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
359{
360 struct dwc3 *dwc = dep->dwc;
361
362 if (dep->trb_pool)
363 return 0;
364
72246da4
FB		 365 dep->trb_pool = dma_alloc_coherent(dwc->dev,
366 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
367 &dep->trb_pool_dma, GFP_KERNEL);
368 if (!dep->trb_pool) {
369 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
370 dep->name);
371 return -ENOMEM;
372 }
373
374 return 0;
375}
376
377static void dwc3_free_trb_pool(struct dwc3_ep *dep)
378{
379 struct dwc3 *dwc = dep->dwc;
380
381 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
382 dep->trb_pool, dep->trb_pool_dma);
383
384 dep->trb_pool = NULL;
385 dep->trb_pool_dma = 0;
386}
387
c4509601
JY		 388static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
389
390/**
391 * dwc3_gadget_start_config - Configure EP resources
392 * @dwc: pointer to our controller context structure
393 * @dep: endpoint that is being enabled
394 *
395 * The assignment of transfer resources cannot perfectly follow the
396 * data book due to the fact that the controller driver does not have
397 * all knowledge of the configuration in advance. It is given this
398 * information piecemeal by the composite gadget framework after every
399 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
400 * programming model in this scenario can cause errors. For two
401 * reasons:
402 *
403 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
404 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
405 * multiple interfaces.
406 *
407 * 2) The databook does not mention doing more DEPXFERCFG for new
408 * endpoint on alt setting (8.1.6).
409 *
410 * The following simplified method is used instead:
411 *
412 * All hardware endpoints can be assigned a transfer resource and this
413 * setting will stay persistent until either a core reset or
414 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
415 * do DEPXFERCFG for every hardware endpoint as well. We are
416 * guaranteed that there are as many transfer resources as endpoints.
417 *
418 * This function is called for each endpoint when it is being enabled
419 * but is triggered only when called for EP0-out, which always happens
420 * first, and which should only happen in one of the above conditions.
421 */
72246da4
FB		 422static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
423{
424 struct dwc3_gadget_ep_cmd_params params;
425 u32 cmd;
c4509601
JY		 426 int i;
427 int ret;
428
429 if (dep->number)
430 return 0;
72246da4
FB		 431
432 memset(&params, 0x00, sizeof(params));
c4509601 433 cmd = DWC3_DEPCMD_DEPSTARTCFG;
72246da4 434
c4509601
JY		 435 ret = dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
436 if (ret)
437 return ret;
438
439 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
440 struct dwc3_ep *dep = dwc->eps[i];
72246da4 441
c4509601
JY		 442 if (!dep)
443 continue;
444
445 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
446 if (ret)
447 return ret;
72246da4
FB		 448 }
449
450 return 0;
451}
452
453static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
c90bfaec 454 const struct usb_endpoint_descriptor *desc,
4b345c9a 455 const struct usb_ss_ep_comp_descriptor *comp_desc,
265b70a7 456 bool ignore, bool restore)
72246da4
FB		 457{
458 struct dwc3_gadget_ep_cmd_params params;
459
460 memset(&params, 0x00, sizeof(params));
461
dc1c70a7 462 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
d2e9a13a
CP		 463 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
464
465 /* Burst size is only needed in SuperSpeed mode */
ee5cd41c 466 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
d2e9a13a
CP		 467 u32 burst = dep->endpoint.maxburst - 1;
468
469 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
470 }
72246da4 471
4b345c9a
FB		 472 if (ignore)
473 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
474
265b70a7
PZ		 475 if (restore) {
476 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
477 params.param2 |= dep->saved_state;
478 }
479
dc1c70a7
FB		 480 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
481 | DWC3_DEPCFG_XFER_NOT_READY_EN;
72246da4 482
18b7ede5 483 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
dc1c70a7
FB		 484 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
485 | DWC3_DEPCFG_STREAM_EVENT_EN;
879631aa
FB		 486 dep->stream_capable = true;
487 }
488
0b93a4c8 489 if (!usb_endpoint_xfer_control(desc))
dc1c70a7 490 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
72246da4
FB		 491
492 /*
493 * We are doing 1:1 mapping for endpoints, meaning
494 * Physical Endpoints 2 maps to Logical Endpoint 2 and
495 * so on. We consider the direction bit as part of the physical
496 * endpoint number. So USB endpoint 0x81 is 0x03.
497 */
dc1c70a7 498 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
72246da4
FB		 499
500 /*
501 * We must use the lower 16 TX FIFOs even though
502 * HW might have more
503 */
504 if (dep->direction)
dc1c70a7 505 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
72246da4
FB		 506
507 if (desc->bInterval) {
dc1c70a7 508 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
72246da4
FB		 509 dep->interval = 1 << (desc->bInterval - 1);
510 }
511
512 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
513 DWC3_DEPCMD_SETEPCONFIG, &params);
514}
515
516static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
517{
518 struct dwc3_gadget_ep_cmd_params params;
519
520 memset(&params, 0x00, sizeof(params));
521
dc1c70a7 522 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
72246da4
FB		 523
524 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
525 DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
526}
527
528/**
529 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
530 * @dep: endpoint to be initialized
531 * @desc: USB Endpoint Descriptor
532 *
533 * Caller should take care of locking
534 */
535static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
c90bfaec 536 const struct usb_endpoint_descriptor *desc,
4b345c9a 537 const struct usb_ss_ep_comp_descriptor *comp_desc,
265b70a7 538 bool ignore, bool restore)
72246da4
FB		 539{
540 struct dwc3 *dwc = dep->dwc;
541 u32 reg;
b09e99ee 542 int ret;
72246da4 543
73815280 544 dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
ff62d6b6 545
72246da4
FB		 546 if (!(dep->flags & DWC3_EP_ENABLED)) {
547 ret = dwc3_gadget_start_config(dwc, dep);
548 if (ret)
549 return ret;
550 }
551
265b70a7
PZ		 552 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
553 restore);
72246da4
FB		 554 if (ret)
555 return ret;
556
557 if (!(dep->flags & DWC3_EP_ENABLED)) {
f6bafc6a
FB		 558 struct dwc3_trb *trb_st_hw;
559 struct dwc3_trb *trb_link;
72246da4 560
16e78db7 561 dep->endpoint.desc = desc;
c90bfaec 562 dep->comp_desc = comp_desc;
72246da4
FB		 563 dep->type = usb_endpoint_type(desc);
564 dep->flags |= DWC3_EP_ENABLED;
565
566 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
567 reg |= DWC3_DALEPENA_EP(dep->number);
568 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
569
570 if (!usb_endpoint_xfer_isoc(desc))
571 return 0;
572
1d046793 573 /* Link TRB for ISOC. The HWO bit is never reset */
72246da4
FB		 574 trb_st_hw = &dep->trb_pool[0];
575
f6bafc6a 576 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
1200a82a 577 memset(trb_link, 0, sizeof(*trb_link));
72246da4 578
f6bafc6a
FB		 579 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
580 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
581 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
582 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
72246da4
FB		 583 }
584
aa739974
FB		 585 switch (usb_endpoint_type(desc)) {
586 case USB_ENDPOINT_XFER_CONTROL:
587 strlcat(dep->name, "-control", sizeof(dep->name));
588 break;
589 case USB_ENDPOINT_XFER_ISOC:
590 strlcat(dep->name, "-isoc", sizeof(dep->name));
591 break;
592 case USB_ENDPOINT_XFER_BULK:
593 strlcat(dep->name, "-bulk", sizeof(dep->name));
594 break;
595 case USB_ENDPOINT_XFER_INT:
596 strlcat(dep->name, "-int", sizeof(dep->name));
597 break;
598 default:
599 dev_err(dwc->dev, "invalid endpoint transfer type\n");
600 }
601
72246da4
FB		 602 return 0;
603}
604
b992e681 605static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
624407f9 606static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
72246da4
FB		 607{
608 struct dwc3_request *req;
609
ea53b882 610 if (!list_empty(&dep->req_queued)) {
b992e681 611 dwc3_stop_active_transfer(dwc, dep->number, true);
624407f9 612
57911504 613 /* - giveback all requests to gadget driver */
1591633e
PA		 614 while (!list_empty(&dep->req_queued)) {
615 req = next_request(&dep->req_queued);
616
617 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
618 }
ea53b882
FB		 619 }
620
72246da4
FB		 621 while (!list_empty(&dep->request_list)) {
622 req = next_request(&dep->request_list);
623
624407f9 624 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
72246da4 625 }
72246da4
FB		 626}
627
628/**
629 * __dwc3_gadget_ep_disable - Disables a HW endpoint
630 * @dep: the endpoint to disable
631 *
624407f9
SAS		 632 * This function also removes requests which are currently processed ny the
633 * hardware and those which are not yet scheduled.
634 * Caller should take care of locking.
72246da4 635 */
72246da4
FB		 636static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
637{
638 struct dwc3 *dwc = dep->dwc;
639 u32 reg;
640
7eaeac5c
FB		 641 dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
642
624407f9 643 dwc3_remove_requests(dwc, dep);
72246da4 644
687ef981
FB		 645 /* make sure HW endpoint isn't stalled */
646 if (dep->flags & DWC3_EP_STALL)
7a608559 647 __dwc3_gadget_ep_set_halt(dep, 0, false);
687ef981 648
72246da4
FB		 649 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
650 reg &= ~DWC3_DALEPENA_EP(dep->number);
651 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
652
879631aa 653 dep->stream_capable = false;
f9c56cdd 654 dep->endpoint.desc = NULL;
c90bfaec 655 dep->comp_desc = NULL;
72246da4 656 dep->type = 0;
879631aa 657 dep->flags = 0;
72246da4 658
aa739974
FB		 659 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
660 dep->number >> 1,
661 (dep->number & 1) ? "in" : "out");
662
72246da4
FB		 663 return 0;
664}
665
666/* -------------------------------------------------------------------------- */
667
668static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
669 const struct usb_endpoint_descriptor *desc)
670{
671 return -EINVAL;
672}
673
674static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
675{
676 return -EINVAL;
677}
678
679/* -------------------------------------------------------------------------- */
680
681static int dwc3_gadget_ep_enable(struct usb_ep *ep,
682 const struct usb_endpoint_descriptor *desc)
683{
684 struct dwc3_ep *dep;
685 struct dwc3 *dwc;
686 unsigned long flags;
687 int ret;
688
689 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
690 pr_debug("dwc3: invalid parameters\n");
691 return -EINVAL;
692 }
693
694 if (!desc->wMaxPacketSize) {
695 pr_debug("dwc3: missing wMaxPacketSize\n");
696 return -EINVAL;
697 }
698
699 dep = to_dwc3_ep(ep);
700 dwc = dep->dwc;
701
95ca961c
FB		 702 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
703 "%s is already enabled\n",
704 dep->name))
c6f83f38 705 return 0;
c6f83f38 706
72246da4 707 spin_lock_irqsave(&dwc->lock, flags);
265b70a7 708 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
72246da4
FB		 709 spin_unlock_irqrestore(&dwc->lock, flags);
710
711 return ret;
712}
713
714static int dwc3_gadget_ep_disable(struct usb_ep *ep)
715{
716 struct dwc3_ep *dep;
717 struct dwc3 *dwc;
718 unsigned long flags;
719 int ret;
720
721 if (!ep) {
722 pr_debug("dwc3: invalid parameters\n");
723 return -EINVAL;
724 }
725
726 dep = to_dwc3_ep(ep);
727 dwc = dep->dwc;
728
95ca961c
FB		 729 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
730 "%s is already disabled\n",
731 dep->name))
72246da4 732 return 0;
72246da4 733
72246da4
FB		 734 spin_lock_irqsave(&dwc->lock, flags);
735 ret = __dwc3_gadget_ep_disable(dep);
736 spin_unlock_irqrestore(&dwc->lock, flags);
737
738 return ret;
739}
740
741static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
742 gfp_t gfp_flags)
743{
744 struct dwc3_request *req;
745 struct dwc3_ep *dep = to_dwc3_ep(ep);
72246da4
FB		 746
747 req = kzalloc(sizeof(*req), gfp_flags);
734d5a53 748 if (!req)
72246da4 749 return NULL;
72246da4
FB		 750
751 req->epnum = dep->number;
752 req->dep = dep;
72246da4 753
2c4cbe6e
FB		 754 trace_dwc3_alloc_request(req);
755
72246da4
FB		 756 return &req->request;
757}
758
759static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
760 struct usb_request *request)
761{
762 struct dwc3_request *req = to_dwc3_request(request);
763
2c4cbe6e 764 trace_dwc3_free_request(req);
72246da4
FB		 765 kfree(req);
766}
767
c71fc37c
FB		 768/**
769 * dwc3_prepare_one_trb - setup one TRB from one request
770 * @dep: endpoint for which this request is prepared
771 * @req: dwc3_request pointer
772 */
68e823e2 773static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
eeb720fb 774 struct dwc3_request *req, dma_addr_t dma,
e5ba5ec8 775 unsigned length, unsigned last, unsigned chain, unsigned node)
c71fc37c 776{
f6bafc6a 777 struct dwc3_trb *trb;
c71fc37c 778
73815280 779 dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
eeb720fb
FB		 780 dep->name, req, (unsigned long long) dma,
781 length, last ? " last" : "",
782 chain ? " chain" : "");
783
915e202a
PA		 784
785 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
c71fc37c 786
eeb720fb
FB		 787 if (!req->trb) {
788 dwc3_gadget_move_request_queued(req);
f6bafc6a
FB		 789 req->trb = trb;
790 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
e5ba5ec8 791 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
eeb720fb 792 }
c71fc37c 793
e5ba5ec8 794 dep->free_slot++;
5cd8c48d
ZJC		 795 /* Skip the LINK-TRB on ISOC */
796 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
797 usb_endpoint_xfer_isoc(dep->endpoint.desc))
798 dep->free_slot++;
e5ba5ec8 799
f6bafc6a
FB		 800 trb->size = DWC3_TRB_SIZE_LENGTH(length);
801 trb->bpl = lower_32_bits(dma);
802 trb->bph = upper_32_bits(dma);
c71fc37c 803
16e78db7 804 switch (usb_endpoint_type(dep->endpoint.desc)) {
c71fc37c 805 case USB_ENDPOINT_XFER_CONTROL:
f6bafc6a 806 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
c71fc37c
FB		 807 break;
808
809 case USB_ENDPOINT_XFER_ISOC:
e5ba5ec8
PA		 810 if (!node)
811 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
812 else
813 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
c71fc37c
FB		 814 break;
815
816 case USB_ENDPOINT_XFER_BULK:
817 case USB_ENDPOINT_XFER_INT:
f6bafc6a 818 trb->ctrl = DWC3_TRBCTL_NORMAL;
c71fc37c
FB		 819 break;
820 default:
821 /*
822 * This is only possible with faulty memory because we
823 * checked it already :)
824 */
825 BUG();
826 }
827
f3af3651
FB		 828 if (!req->request.no_interrupt && !chain)
829 trb->ctrl |= DWC3_TRB_CTRL_IOC;
830
16e78db7 831 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
f6bafc6a
FB		 832 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
833 trb->ctrl |= DWC3_TRB_CTRL_CSP;
e5ba5ec8
PA		 834 } else if (last) {
835 trb->ctrl |= DWC3_TRB_CTRL_LST;
f6bafc6a 836 }
c71fc37c 837
e5ba5ec8
PA		 838 if (chain)
839 trb->ctrl |= DWC3_TRB_CTRL_CHN;
840
16e78db7 841 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
f6bafc6a 842 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
c71fc37c 843
f6bafc6a 844 trb->ctrl |= DWC3_TRB_CTRL_HWO;
2c4cbe6e
FB		 845
846 trace_dwc3_prepare_trb(dep, trb);
c71fc37c
FB		 847}
848
72246da4
FB		 849/*
850 * dwc3_prepare_trbs - setup TRBs from requests
851 * @dep: endpoint for which requests are being prepared
852 * @starting: true if the endpoint is idle and no requests are queued.
853 *
1d046793
PZ		 854 * The function goes through the requests list and sets up TRBs for the
855 * transfers. The function returns once there are no more TRBs available or
856 * it runs out of requests.
72246da4 857 */
68e823e2 858static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
72246da4 859{
68e823e2 860 struct dwc3_request *req, *n;
72246da4 861 u32 trbs_left;
8d62cd65 862 u32 max;
c71fc37c 863 unsigned int last_one = 0;
72246da4
FB		 864
865 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
866
867 /* the first request must not be queued */
868 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
c71fc37c 869
8d62cd65 870 /* Can't wrap around on a non-isoc EP since there's no link TRB */
16e78db7 871 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8d62cd65
PZ		 872 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
873 if (trbs_left > max)
874 trbs_left = max;
875 }
876
72246da4 877 /*
1d046793
PZ		 878 * If busy & slot are equal than it is either full or empty. If we are
879 * starting to process requests then we are empty. Otherwise we are
72246da4
FB		 880 * full and don't do anything
881 */
882 if (!trbs_left) {
883 if (!starting)
68e823e2 884 return;
72246da4
FB		 885 trbs_left = DWC3_TRB_NUM;
886 /*
887 * In case we start from scratch, we queue the ISOC requests
888 * starting from slot 1. This is done because we use ring
889 * buffer and have no LST bit to stop us. Instead, we place
1d046793 890 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
72246da4
FB		 891 * after the first request so we start at slot 1 and have
892 * 7 requests proceed before we hit the first IOC.
893 * Other transfer types don't use the ring buffer and are
894 * processed from the first TRB until the last one. Since we
895 * don't wrap around we have to start at the beginning.
896 */
16e78db7 897 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 898 dep->busy_slot = 1;
899 dep->free_slot = 1;
900 } else {
901 dep->busy_slot = 0;
902 dep->free_slot = 0;
903 }
904 }
905
906 /* The last TRB is a link TRB, not used for xfer */
16e78db7 907 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
68e823e2 908 return;
72246da4
FB		 909
910 list_for_each_entry_safe(req, n, &dep->request_list, list) {
eeb720fb
FB		 911 unsigned length;
912 dma_addr_t dma;
e5ba5ec8 913 last_one = false;
72246da4 914
eeb720fb
FB		 915 if (req->request.num_mapped_sgs > 0) {
916 struct usb_request *request = &req->request;
917 struct scatterlist *sg = request->sg;
918 struct scatterlist *s;
919 int i;
72246da4 920
eeb720fb
FB		 921 for_each_sg(sg, s, request->num_mapped_sgs, i) {
922 unsigned chain = true;
72246da4 923
eeb720fb
FB		 924 length = sg_dma_len(s);
925 dma = sg_dma_address(s);
72246da4 926
1d046793
PZ		 927 if (i == (request->num_mapped_sgs - 1) ||
928 sg_is_last(s)) {
ec512fb8 929 if (list_empty(&dep->request_list))
e5ba5ec8 930 last_one = true;
eeb720fb
FB		 931 chain = false;
932 }
72246da4 933
eeb720fb
FB		 934 trbs_left--;
935 if (!trbs_left)
936 last_one = true;
72246da4 937
eeb720fb
FB		 938 if (last_one)
939 chain = false;
72246da4 940
eeb720fb 941 dwc3_prepare_one_trb(dep, req, dma, length,
e5ba5ec8 942 last_one, chain, i);
72246da4 943
eeb720fb
FB		 944 if (last_one)
945 break;
946 }
39e60635
AV		 947
948 if (last_one)
949 break;
72246da4 950 } else {
eeb720fb
FB		 951 dma = req->request.dma;
952 length = req->request.length;
953 trbs_left--;
72246da4 954
eeb720fb
FB		 955 if (!trbs_left)
956 last_one = 1;
879631aa 957
eeb720fb
FB		 958 /* Is this the last request? */
959 if (list_is_last(&req->list, &dep->request_list))
960 last_one = 1;
72246da4 961
eeb720fb 962 dwc3_prepare_one_trb(dep, req, dma, length,
e5ba5ec8 963 last_one, false, 0);
72246da4 964
eeb720fb
FB		 965 if (last_one)
966 break;
72246da4 967 }
72246da4 968 }
72246da4
FB		 969}
970
971static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
972 int start_new)
973{
974 struct dwc3_gadget_ep_cmd_params params;
975 struct dwc3_request *req;
976 struct dwc3 *dwc = dep->dwc;
977 int ret;
978 u32 cmd;
979
980 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
73815280 981 dwc3_trace(trace_dwc3_gadget, "%s: endpoint busy", dep->name);
72246da4
FB		 982 return -EBUSY;
983 }
72246da4
FB		 984
985 /*
986 * If we are getting here after a short-out-packet we don't enqueue any
987 * new requests as we try to set the IOC bit only on the last request.
988 */
989 if (start_new) {
990 if (list_empty(&dep->req_queued))
991 dwc3_prepare_trbs(dep, start_new);
992
993 /* req points to the first request which will be sent */
994 req = next_request(&dep->req_queued);
995 } else {
68e823e2
FB		 996 dwc3_prepare_trbs(dep, start_new);
997
72246da4 998 /*
1d046793 999 * req points to the first request where HWO changed from 0 to 1
72246da4 1000 */
68e823e2 1001 req = next_request(&dep->req_queued);
72246da4
FB		 1002 }
1003 if (!req) {
1004 dep->flags |= DWC3_EP_PENDING_REQUEST;
1005 return 0;
1006 }
1007
1008 memset(&params, 0, sizeof(params));
72246da4 1009
1877d6c9
PA		 1010 if (start_new) {
1011 params.param0 = upper_32_bits(req->trb_dma);
1012 params.param1 = lower_32_bits(req->trb_dma);
72246da4 1013 cmd = DWC3_DEPCMD_STARTTRANSFER;
1877d6c9 1014 } else {
72246da4 1015 cmd = DWC3_DEPCMD_UPDATETRANSFER;
1877d6c9 1016 }
72246da4
FB		 1017
1018 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
1019 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1020 if (ret < 0) {
72246da4
FB		 1021 /*
1022 * FIXME we need to iterate over the list of requests
1023 * here and stop, unmap, free and del each of the linked
1d046793 1024 * requests instead of what we do now.
72246da4 1025 */
0fc9a1be
FB		 1026 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1027 req->direction);
72246da4
FB		 1028 list_del(&req->list);
1029 return ret;
1030 }
1031
1032 dep->flags |= DWC3_EP_BUSY;
25b8ff68 1033
f898ae09 1034 if (start_new) {
b4996a86 1035 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
f898ae09 1036 dep->number);
b4996a86 1037 WARN_ON_ONCE(!dep->resource_index);
f898ae09 1038 }
25b8ff68 1039
72246da4
FB		 1040 return 0;
1041}
1042
d6d6ec7b
PA		 1043static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1044 struct dwc3_ep *dep, u32 cur_uf)
1045{
1046 u32 uf;
1047
1048 if (list_empty(&dep->request_list)) {
73815280
FB		 1049 dwc3_trace(trace_dwc3_gadget,
1050 "ISOC ep %s run out for requests",
1051 dep->name);
f4a53c55 1052 dep->flags |= DWC3_EP_PENDING_REQUEST;
d6d6ec7b
PA		 1053 return;
1054 }
1055
1056 /* 4 micro frames in the future */
1057 uf = cur_uf + dep->interval * 4;
1058
1059 __dwc3_gadget_kick_transfer(dep, uf, 1);
1060}
1061
1062static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1063 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1064{
1065 u32 cur_uf, mask;
1066
1067 mask = ~(dep->interval - 1);
1068 cur_uf = event->parameters & mask;
1069
1070 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1071}
1072
72246da4
FB		 1073static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1074{
0fc9a1be
FB		 1075 struct dwc3 *dwc = dep->dwc;
1076 int ret;
1077
bb423984 1078 if (!dep->endpoint.desc) {
ec5e795c
FB		 1079 dwc3_trace(trace_dwc3_gadget,
1080 "trying to queue request %p to disabled %s\n",
bb423984
FB		 1081 &req->request, dep->endpoint.name);
1082 return -ESHUTDOWN;
1083 }
1084
1085 if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1086 &req->request, req->dep->name)) {
ec5e795c
FB		 1087 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n",
1088 &req->request, req->dep->name);
bb423984
FB		 1089 return -EINVAL;
1090 }
1091
72246da4
FB		 1092 req->request.actual = 0;
1093 req->request.status = -EINPROGRESS;
1094 req->direction = dep->direction;
1095 req->epnum = dep->number;
1096
fe84f522
FB		 1097 trace_dwc3_ep_queue(req);
1098
72246da4
FB		 1099 /*
1100 * We only add to our list of requests now and
1101 * start consuming the list once we get XferNotReady
1102 * IRQ.
1103 *
1104 * That way, we avoid doing anything that we don't need
1105 * to do now and defer it until the point we receive a
1106 * particular token from the Host side.
1107 *
1108 * This will also avoid Host cancelling URBs due to too
1d046793 1109 * many NAKs.
72246da4 1110 */
0fc9a1be
FB		 1111 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1112 dep->direction);
1113 if (ret)
1114 return ret;
1115
72246da4
FB		 1116 list_add_tail(&req->list, &dep->request_list);
1117
1d6a3918
FB		 1118 /*
1119 * If there are no pending requests and the endpoint isn't already
1120 * busy, we will just start the request straight away.
1121 *
1122 * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1123 * little bit faster.
1124 */
1125 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
62e345ae 1126 !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1d6a3918
FB		 1127 !(dep->flags & DWC3_EP_BUSY)) {
1128 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
a8f32817 1129 goto out;
1d6a3918
FB		 1130 }
1131
72246da4 1132 /*
b511e5e7 1133 * There are a few special cases:
72246da4 1134 *
f898ae09
PZ		 1135 * 1. XferNotReady with empty list of requests. We need to kick the
1136 * transfer here in that situation, otherwise we will be NAKing
1137 * forever. If we get XferNotReady before gadget driver has a
1138 * chance to queue a request, we will ACK the IRQ but won't be
1139 * able to receive the data until the next request is queued.
1140 * The following code is handling exactly that.
72246da4 1141 *
72246da4
FB		 1142 */
1143 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
f4a53c55
PA		 1144 /*
1145 * If xfernotready is already elapsed and it is a case
1146 * of isoc transfer, then issue END TRANSFER, so that
1147 * you can receive xfernotready again and can have
1148 * notion of current microframe.
1149 */
1150 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
cdc359dd 1151 if (list_empty(&dep->req_queued)) {
b992e681 1152 dwc3_stop_active_transfer(dwc, dep->number, true);
cdc359dd
PA		 1153 dep->flags = DWC3_EP_ENABLED;
1154 }
f4a53c55
PA		 1155 return 0;
1156 }
1157
b511e5e7 1158 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
89185916
FB		 1159 if (!ret)
1160 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1161
a8f32817 1162 goto out;
b511e5e7 1163 }
72246da4 1164
b511e5e7
FB		 1165 /*
1166 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1167 * kick the transfer here after queuing a request, otherwise the
1168 * core may not see the modified TRB(s).
1169 */
1170 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
79c9046e
PA		 1171 (dep->flags & DWC3_EP_BUSY) &&
1172 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
b4996a86
FB		 1173 WARN_ON_ONCE(!dep->resource_index);
1174 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
b511e5e7 1175 false);
a8f32817 1176 goto out;
a0925324 1177 }
72246da4 1178
b997ada5
FB		 1179 /*
1180 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1181 * right away, otherwise host will not know we have streams to be
1182 * handled.
1183 */
a8f32817 1184 if (dep->stream_capable)
b997ada5 1185 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
b997ada5 1186
a8f32817
FB		 1187out:
1188 if (ret && ret != -EBUSY)
ec5e795c
FB		 1189 dwc3_trace(trace_dwc3_gadget,
1190 "%s: failed to kick transfers\n",
a8f32817
FB		 1191 dep->name);
1192 if (ret == -EBUSY)
1193 ret = 0;
1194
1195 return ret;
72246da4
FB		 1196}
1197
04c03d10
FB		 1198static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1199 struct usb_request *request)
1200{
1201 dwc3_gadget_ep_free_request(ep, request);
1202}
1203
1204static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1205{
1206 struct dwc3_request *req;
1207 struct usb_request *request;
1208 struct usb_ep *ep = &dep->endpoint;
1209
1210 dwc3_trace(trace_dwc3_gadget, "queueing ZLP\n");
1211 request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1212 if (!request)
1213 return -ENOMEM;
1214
1215 request->length = 0;
1216 request->buf = dwc->zlp_buf;
1217 request->complete = __dwc3_gadget_ep_zlp_complete;
1218
1219 req = to_dwc3_request(request);
1220
1221 return __dwc3_gadget_ep_queue(dep, req);
1222}
1223
72246da4
FB		 1224static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1225 gfp_t gfp_flags)
1226{
1227 struct dwc3_request *req = to_dwc3_request(request);
1228 struct dwc3_ep *dep = to_dwc3_ep(ep);
1229 struct dwc3 *dwc = dep->dwc;
1230
1231 unsigned long flags;
1232
1233 int ret;
1234
fdee4eba 1235 spin_lock_irqsave(&dwc->lock, flags);
72246da4 1236 ret = __dwc3_gadget_ep_queue(dep, req);
04c03d10
FB		 1237
1238 /*
1239 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1240 * setting request->zero, instead of doing magic, we will just queue an
1241 * extra usb_request ourselves so that it gets handled the same way as
1242 * any other request.
1243 */
d9261898
JY		 1244 if (ret == 0 && request->zero && request->length &&
1245 (request->length % ep->maxpacket == 0))
04c03d10
FB		 1246 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1247
72246da4
FB		 1248 spin_unlock_irqrestore(&dwc->lock, flags);
1249
1250 return ret;
1251}
1252
1253static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1254 struct usb_request *request)
1255{
1256 struct dwc3_request *req = to_dwc3_request(request);
1257 struct dwc3_request *r = NULL;
1258
1259 struct dwc3_ep *dep = to_dwc3_ep(ep);
1260 struct dwc3 *dwc = dep->dwc;
1261
1262 unsigned long flags;
1263 int ret = 0;
1264
2c4cbe6e
FB		 1265 trace_dwc3_ep_dequeue(req);
1266
72246da4
FB		 1267 spin_lock_irqsave(&dwc->lock, flags);
1268
1269 list_for_each_entry(r, &dep->request_list, list) {
1270 if (r == req)
1271 break;
1272 }
1273
1274 if (r != req) {
1275 list_for_each_entry(r, &dep->req_queued, list) {
1276 if (r == req)
1277 break;
1278 }
1279 if (r == req) {
1280 /* wait until it is processed */
b992e681 1281 dwc3_stop_active_transfer(dwc, dep->number, true);
e8d4e8be 1282 goto out1;
72246da4
FB		 1283 }
1284 dev_err(dwc->dev, "request %p was not queued to %s\n",
1285 request, ep->name);
1286 ret = -EINVAL;
1287 goto out0;
1288 }
1289
e8d4e8be 1290out1:
72246da4
FB		 1291 /* giveback the request */
1292 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1293
1294out0:
1295 spin_unlock_irqrestore(&dwc->lock, flags);
1296
1297 return ret;
1298}
1299
7a608559 1300int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
72246da4
FB		 1301{
1302 struct dwc3_gadget_ep_cmd_params params;
1303 struct dwc3 *dwc = dep->dwc;
1304 int ret;
1305
5ad02fb8
FB		 1306 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1307 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1308 return -EINVAL;
1309 }
1310
72246da4
FB		 1311 memset(&params, 0x00, sizeof(params));
1312
1313 if (value) {
7a608559
FB		 1314 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1315 (!list_empty(&dep->req_queued) ||
1316 !list_empty(&dep->request_list)))) {
ec5e795c
FB		 1317 dwc3_trace(trace_dwc3_gadget,
1318 "%s: pending request, cannot halt\n",
7a608559
FB		 1319 dep->name);
1320 return -EAGAIN;
1321 }
1322
72246da4
FB		 1323 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1324 DWC3_DEPCMD_SETSTALL, &params);
1325 if (ret)
3f89204b 1326 dev_err(dwc->dev, "failed to set STALL on %s\n",
72246da4
FB		 1327 dep->name);
1328 else
1329 dep->flags |= DWC3_EP_STALL;
1330 } else {
1331 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1332 DWC3_DEPCMD_CLEARSTALL, &params);
1333 if (ret)
3f89204b 1334 dev_err(dwc->dev, "failed to clear STALL on %s\n",
72246da4
FB		 1335 dep->name);
1336 else
a535d81c 1337 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
72246da4 1338 }
5275455a 1339
72246da4
FB		 1340 return ret;
1341}
1342
1343static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1344{
1345 struct dwc3_ep *dep = to_dwc3_ep(ep);
1346 struct dwc3 *dwc = dep->dwc;
1347
1348 unsigned long flags;
1349
1350 int ret;
1351
1352 spin_lock_irqsave(&dwc->lock, flags);
7a608559 1353 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
72246da4
FB		 1354 spin_unlock_irqrestore(&dwc->lock, flags);
1355
1356 return ret;
1357}
1358
1359static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1360{
1361 struct dwc3_ep *dep = to_dwc3_ep(ep);
249a4569
PZ		 1362 struct dwc3 *dwc = dep->dwc;
1363 unsigned long flags;
95aa4e8d 1364 int ret;
72246da4 1365
249a4569 1366 spin_lock_irqsave(&dwc->lock, flags);
72246da4
FB		 1367 dep->flags |= DWC3_EP_WEDGE;
1368
08f0d966 1369 if (dep->number == 0 || dep->number == 1)
95aa4e8d 1370 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
08f0d966 1371 else
7a608559 1372 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
95aa4e8d
FB		 1373 spin_unlock_irqrestore(&dwc->lock, flags);
1374
1375 return ret;
72246da4
FB		 1376}
1377
1378/* -------------------------------------------------------------------------- */
1379
1380static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1381 .bLength = USB_DT_ENDPOINT_SIZE,
1382 .bDescriptorType = USB_DT_ENDPOINT,
1383 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1384};
1385
1386static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1387 .enable = dwc3_gadget_ep0_enable,
1388 .disable = dwc3_gadget_ep0_disable,
1389 .alloc_request = dwc3_gadget_ep_alloc_request,
1390 .free_request = dwc3_gadget_ep_free_request,
1391 .queue = dwc3_gadget_ep0_queue,
1392 .dequeue = dwc3_gadget_ep_dequeue,
08f0d966 1393 .set_halt = dwc3_gadget_ep0_set_halt,
72246da4
FB		 1394 .set_wedge = dwc3_gadget_ep_set_wedge,
1395};
1396
1397static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1398 .enable = dwc3_gadget_ep_enable,
1399 .disable = dwc3_gadget_ep_disable,
1400 .alloc_request = dwc3_gadget_ep_alloc_request,
1401 .free_request = dwc3_gadget_ep_free_request,
1402 .queue = dwc3_gadget_ep_queue,
1403 .dequeue = dwc3_gadget_ep_dequeue,
1404 .set_halt = dwc3_gadget_ep_set_halt,
1405 .set_wedge = dwc3_gadget_ep_set_wedge,
1406};
1407
1408/* -------------------------------------------------------------------------- */
1409
1410static int dwc3_gadget_get_frame(struct usb_gadget *g)
1411{
1412 struct dwc3 *dwc = gadget_to_dwc(g);
1413 u32 reg;
1414
1415 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1416 return DWC3_DSTS_SOFFN(reg);
1417}
1418
1419static int dwc3_gadget_wakeup(struct usb_gadget *g)
1420{
1421 struct dwc3 *dwc = gadget_to_dwc(g);
1422
1423 unsigned long timeout;
1424 unsigned long flags;
1425
1426 u32 reg;
1427
1428 int ret = 0;
1429
1430 u8 link_state;
1431 u8 speed;
1432
1433 spin_lock_irqsave(&dwc->lock, flags);
1434
1435 /*
1436 * According to the Databook Remote wakeup request should
1437 * be issued only when the device is in early suspend state.
1438 *
1439 * We can check that via USB Link State bits in DSTS register.
1440 */
1441 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1442
1443 speed = reg & DWC3_DSTS_CONNECTSPD;
ee5cd41c
JY		 1444 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1445 (speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
ec5e795c 1446 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n");
72246da4
FB		 1447 ret = -EINVAL;
1448 goto out;
1449 }
1450
1451 link_state = DWC3_DSTS_USBLNKST(reg);
1452
1453 switch (link_state) {
1454 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1455 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1456 break;
1457 default:
ec5e795c
FB		 1458 dwc3_trace(trace_dwc3_gadget,
1459 "can't wakeup from '%s'\n",
1460 dwc3_gadget_link_string(link_state));
72246da4
FB		 1461 ret = -EINVAL;
1462 goto out;
1463 }
1464
8598bde7
FB		 1465 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1466 if (ret < 0) {
1467 dev_err(dwc->dev, "failed to put link in Recovery\n");
1468 goto out;
1469 }
72246da4 1470
802fde98
PZ		 1471 /* Recent versions do this automatically */
1472 if (dwc->revision < DWC3_REVISION_194A) {
1473 /* write zeroes to Link Change Request */
fcc023c7 1474 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
802fde98
PZ		 1475 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1476 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1477 }
72246da4 1478
1d046793 1479 /* poll until Link State changes to ON */
72246da4
FB		 1480 timeout = jiffies + msecs_to_jiffies(100);
1481
1d046793 1482 while (!time_after(jiffies, timeout)) {
72246da4
FB		 1483 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1484
1485 /* in HS, means ON */
1486 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1487 break;
1488 }
1489
1490 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1491 dev_err(dwc->dev, "failed to send remote wakeup\n");
1492 ret = -EINVAL;
1493 }
1494
1495out:
1496 spin_unlock_irqrestore(&dwc->lock, flags);
1497
1498 return ret;
1499}
1500
1501static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1502 int is_selfpowered)
1503{
1504 struct dwc3 *dwc = gadget_to_dwc(g);
249a4569 1505 unsigned long flags;
72246da4 1506
249a4569 1507 spin_lock_irqsave(&dwc->lock, flags);
bcdea503 1508 g->is_selfpowered = !!is_selfpowered;
249a4569 1509 spin_unlock_irqrestore(&dwc->lock, flags);
72246da4
FB		 1510
1511 return 0;
1512}
1513
7b2a0368 1514static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
72246da4
FB		 1515{
1516 u32 reg;
61d58242 1517 u32 timeout = 500;
72246da4
FB		 1518
1519 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
8db7ed15 1520 if (is_on) {
802fde98
PZ		 1521 if (dwc->revision <= DWC3_REVISION_187A) {
1522 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1523 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1524 }
1525
1526 if (dwc->revision >= DWC3_REVISION_194A)
1527 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1528 reg |= DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1529
1530 if (dwc->has_hibernation)
1531 reg |= DWC3_DCTL_KEEP_CONNECT;
1532
9fcb3bd8 1533 dwc->pullups_connected = true;
8db7ed15 1534 } else {
72246da4 1535 reg &= ~DWC3_DCTL_RUN_STOP;
7b2a0368
FB		 1536
1537 if (dwc->has_hibernation && !suspend)
1538 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1539
9fcb3bd8 1540 dwc->pullups_connected = false;
8db7ed15 1541 }
72246da4
FB		 1542
1543 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1544
1545 do {
1546 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1547 if (is_on) {
1548 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1549 break;
1550 } else {
1551 if (reg & DWC3_DSTS_DEVCTRLHLT)
1552 break;
1553 }
72246da4
FB		 1554 timeout--;
1555 if (!timeout)
6f17f74b 1556 return -ETIMEDOUT;
61d58242 1557 udelay(1);
72246da4
FB		 1558 } while (1);
1559
73815280 1560 dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
72246da4
FB		 1561 dwc->gadget_driver
1562 ? dwc->gadget_driver->function : "no-function",
1563 is_on ? "connect" : "disconnect");
6f17f74b
PA		 1564
1565 return 0;
72246da4
FB		 1566}
1567
1568static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1569{
1570 struct dwc3 *dwc = gadget_to_dwc(g);
1571 unsigned long flags;
6f17f74b 1572 int ret;
72246da4
FB		 1573
1574 is_on = !!is_on;
1575
1576 spin_lock_irqsave(&dwc->lock, flags);
7b2a0368 1577 ret = dwc3_gadget_run_stop(dwc, is_on, false);
72246da4
FB		 1578 spin_unlock_irqrestore(&dwc->lock, flags);
1579
6f17f74b 1580 return ret;
72246da4
FB		 1581}
1582
8698e2ac
FB		 1583static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1584{
1585 u32 reg;
1586
1587 /* Enable all but Start and End of Frame IRQs */
1588 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1589 DWC3_DEVTEN_EVNTOVERFLOWEN |
1590 DWC3_DEVTEN_CMDCMPLTEN |
1591 DWC3_DEVTEN_ERRTICERREN |
1592 DWC3_DEVTEN_WKUPEVTEN |
1593 DWC3_DEVTEN_ULSTCNGEN |
1594 DWC3_DEVTEN_CONNECTDONEEN |
1595 DWC3_DEVTEN_USBRSTEN |
1596 DWC3_DEVTEN_DISCONNEVTEN);
1597
1598 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1599}
1600
1601static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1602{
1603 /* mask all interrupts */
1604 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1605}
1606
1607static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
b15a762f 1608static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
8698e2ac 1609
72246da4
FB		 1610static int dwc3_gadget_start(struct usb_gadget *g,
1611 struct usb_gadget_driver *driver)
1612{
1613 struct dwc3 *dwc = gadget_to_dwc(g);
1614 struct dwc3_ep *dep;
1615 unsigned long flags;
1616 int ret = 0;
8698e2ac 1617 int irq;
72246da4
FB		 1618 u32 reg;
1619
b0d7ffd4
FB		 1620 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1621 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
e8adfc30 1622 IRQF_SHARED, "dwc3", dwc);
b0d7ffd4
FB		 1623 if (ret) {
1624 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1625 irq, ret);
1626 goto err0;
1627 }
1628
72246da4
FB		 1629 spin_lock_irqsave(&dwc->lock, flags);
1630
1631 if (dwc->gadget_driver) {
1632 dev_err(dwc->dev, "%s is already bound to %s\n",
1633 dwc->gadget.name,
1634 dwc->gadget_driver->driver.name);
1635 ret = -EBUSY;
b0d7ffd4 1636 goto err1;
72246da4
FB		 1637 }
1638
1639 dwc->gadget_driver = driver;
72246da4 1640
72246da4
FB		 1641 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1642 reg &= ~(DWC3_DCFG_SPEED_MASK);
07e7f47b
FB		 1643
1644 /**
1645 * WORKAROUND: DWC3 revision < 2.20a have an issue
1646 * which would cause metastability state on Run/Stop
1647 * bit if we try to force the IP to USB2-only mode.
1648 *
1649 * Because of that, we cannot configure the IP to any
1650 * speed other than the SuperSpeed
1651 *
1652 * Refers to:
1653 *
1654 * STAR#9000525659: Clock Domain Crossing on DCTL in
1655 * USB 2.0 Mode
1656 */
f7e846f0 1657 if (dwc->revision < DWC3_REVISION_220A) {
07e7f47b 1658 reg |= DWC3_DCFG_SUPERSPEED;
f7e846f0
FB		 1659 } else {
1660 switch (dwc->maximum_speed) {
1661 case USB_SPEED_LOW:
1662 reg |= DWC3_DSTS_LOWSPEED;
1663 break;
1664 case USB_SPEED_FULL:
1665 reg |= DWC3_DSTS_FULLSPEED1;
1666 break;
1667 case USB_SPEED_HIGH:
1668 reg |= DWC3_DSTS_HIGHSPEED;
1669 break;
7580862b
JY		 1670 case USB_SPEED_SUPER_PLUS:
1671 reg |= DWC3_DSTS_SUPERSPEED_PLUS;
1672 break;
f7e846f0
FB		 1673 case USB_SPEED_SUPER: /* FALLTHROUGH */
1674 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1675 default:
1676 reg |= DWC3_DSTS_SUPERSPEED;
1677 }
1678 }
72246da4
FB		 1679 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1680
1681 /* Start with SuperSpeed Default */
1682 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1683
1684 dep = dwc->eps[0];
265b70a7
PZ		 1685 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1686 false);
72246da4
FB		 1687 if (ret) {
1688 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
b0d7ffd4 1689 goto err2;
72246da4
FB		 1690 }
1691
1692 dep = dwc->eps[1];
265b70a7
PZ		 1693 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1694 false);
72246da4
FB		 1695 if (ret) {
1696 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
b0d7ffd4 1697 goto err3;
72246da4
FB		 1698 }
1699
1700 /* begin to receive SETUP packets */
c7fcdeb2 1701 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 1702 dwc3_ep0_out_start(dwc);
1703
8698e2ac
FB		 1704 dwc3_gadget_enable_irq(dwc);
1705
72246da4
FB		 1706 spin_unlock_irqrestore(&dwc->lock, flags);
1707
1708 return 0;
1709
b0d7ffd4 1710err3:
72246da4
FB		 1711 __dwc3_gadget_ep_disable(dwc->eps[0]);
1712
b0d7ffd4 1713err2:
cdcedd69 1714 dwc->gadget_driver = NULL;
b0d7ffd4
FB		 1715
1716err1:
72246da4
FB		 1717 spin_unlock_irqrestore(&dwc->lock, flags);
1718
b0d7ffd4
FB		 1719 free_irq(irq, dwc);
1720
1721err0:
72246da4
FB		 1722 return ret;
1723}
1724
22835b80 1725static int dwc3_gadget_stop(struct usb_gadget *g)
72246da4
FB		 1726{
1727 struct dwc3 *dwc = gadget_to_dwc(g);
1728 unsigned long flags;
8698e2ac 1729 int irq;
72246da4
FB		 1730
1731 spin_lock_irqsave(&dwc->lock, flags);
1732
8698e2ac 1733 dwc3_gadget_disable_irq(dwc);
72246da4
FB		 1734 __dwc3_gadget_ep_disable(dwc->eps[0]);
1735 __dwc3_gadget_ep_disable(dwc->eps[1]);
1736
1737 dwc->gadget_driver = NULL;
72246da4
FB		 1738
1739 spin_unlock_irqrestore(&dwc->lock, flags);
1740
b0d7ffd4
FB		 1741 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1742 free_irq(irq, dwc);
1743
72246da4
FB		 1744 return 0;
1745}
802fde98 1746
72246da4
FB		 1747static const struct usb_gadget_ops dwc3_gadget_ops = {
1748 .get_frame = dwc3_gadget_get_frame,
1749 .wakeup = dwc3_gadget_wakeup,
1750 .set_selfpowered = dwc3_gadget_set_selfpowered,
1751 .pullup = dwc3_gadget_pullup,
1752 .udc_start = dwc3_gadget_start,
1753 .udc_stop = dwc3_gadget_stop,
1754};
1755
1756/* -------------------------------------------------------------------------- */
1757
6a1e3ef4
FB		 1758static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1759 u8 num, u32 direction)
72246da4
FB		 1760{
1761 struct dwc3_ep *dep;
6a1e3ef4 1762 u8 i;
72246da4 1763
6a1e3ef4
FB		 1764 for (i = 0; i < num; i++) {
1765 u8 epnum = (i << 1) | (!!direction);
72246da4 1766
72246da4 1767 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
734d5a53 1768 if (!dep)
72246da4 1769 return -ENOMEM;
72246da4
FB		 1770
1771 dep->dwc = dwc;
1772 dep->number = epnum;
9aa62ae4 1773 dep->direction = !!direction;
72246da4
FB		 1774 dwc->eps[epnum] = dep;
1775
1776 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1777 (epnum & 1) ? "in" : "out");
6a1e3ef4 1778
72246da4 1779 dep->endpoint.name = dep->name;
72246da4 1780
73815280 1781 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
653df35e 1782
72246da4 1783 if (epnum == 0 || epnum == 1) {
e117e742 1784 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
6048e4c6 1785 dep->endpoint.maxburst = 1;
72246da4
FB		 1786 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1787 if (!epnum)
1788 dwc->gadget.ep0 = &dep->endpoint;
1789 } else {
1790 int ret;
1791
e117e742 1792 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
12d36c16 1793 dep->endpoint.max_streams = 15;
72246da4
FB		 1794 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1795 list_add_tail(&dep->endpoint.ep_list,
1796 &dwc->gadget.ep_list);
1797
1798 ret = dwc3_alloc_trb_pool(dep);
25b8ff68 1799 if (ret)
72246da4 1800 return ret;
72246da4 1801 }
25b8ff68 1802
a474d3b7
RB		 1803 if (epnum == 0 || epnum == 1) {
1804 dep->endpoint.caps.type_control = true;
1805 } else {
1806 dep->endpoint.caps.type_iso = true;
1807 dep->endpoint.caps.type_bulk = true;
1808 dep->endpoint.caps.type_int = true;
1809 }
1810
1811 dep->endpoint.caps.dir_in = !!direction;
1812 dep->endpoint.caps.dir_out = !direction;
1813
72246da4
FB		 1814 INIT_LIST_HEAD(&dep->request_list);
1815 INIT_LIST_HEAD(&dep->req_queued);
1816 }
1817
1818 return 0;
1819}
1820
6a1e3ef4
FB		 1821static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1822{
1823 int ret;
1824
1825 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1826
1827 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1828 if (ret < 0) {
73815280
FB		 1829 dwc3_trace(trace_dwc3_gadget,
1830 "failed to allocate OUT endpoints");
6a1e3ef4
FB		 1831 return ret;
1832 }
1833
1834 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1835 if (ret < 0) {
73815280
FB		 1836 dwc3_trace(trace_dwc3_gadget,
1837 "failed to allocate IN endpoints");
6a1e3ef4
FB		 1838 return ret;
1839 }
1840
1841 return 0;
1842}
1843
72246da4
FB		 1844static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1845{
1846 struct dwc3_ep *dep;
1847 u8 epnum;
1848
1849 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1850 dep = dwc->eps[epnum];
6a1e3ef4
FB		 1851 if (!dep)
1852 continue;
5bf8fae3
GC		 1853 /*
1854 * Physical endpoints 0 and 1 are special; they form the
1855 * bi-directional USB endpoint 0.
1856 *
1857 * For those two physical endpoints, we don't allocate a TRB
1858 * pool nor do we add them the endpoints list. Due to that, we
1859 * shouldn't do these two operations otherwise we would end up
1860 * with all sorts of bugs when removing dwc3.ko.
1861 */
1862 if (epnum != 0 && epnum != 1) {
1863 dwc3_free_trb_pool(dep);
72246da4 1864 list_del(&dep->endpoint.ep_list);
5bf8fae3 1865 }
72246da4
FB		 1866
1867 kfree(dep);
1868 }
1869}
1870
72246da4 1871/* -------------------------------------------------------------------------- */
e5caff68 1872
e5ba5ec8
PA		 1873static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1874 struct dwc3_request *req, struct dwc3_trb *trb,
72246da4
FB		 1875 const struct dwc3_event_depevt *event, int status)
1876{
72246da4
FB		 1877 unsigned int count;
1878 unsigned int s_pkt = 0;
d6d6ec7b 1879 unsigned int trb_status;
72246da4 1880
2c4cbe6e
FB		 1881 trace_dwc3_complete_trb(dep, trb);
1882
e5ba5ec8
PA		 1883 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1884 /*
1885 * We continue despite the error. There is not much we
1886 * can do. If we don't clean it up we loop forever. If
1887 * we skip the TRB then it gets overwritten after a
1888 * while since we use them in a ring buffer. A BUG()
1889 * would help. Lets hope that if this occurs, someone
1890 * fixes the root cause instead of looking away :)
1891 */
1892 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1893 dep->name, trb);
1894 count = trb->size & DWC3_TRB_SIZE_MASK;
1895
1896 if (dep->direction) {
1897 if (count) {
1898 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1899 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
ec5e795c
FB		 1900 dwc3_trace(trace_dwc3_gadget,
1901 "%s: incomplete IN transfer\n",
e5ba5ec8
PA		 1902 dep->name);
1903 /*
1904 * If missed isoc occurred and there is
1905 * no request queued then issue END
1906 * TRANSFER, so that core generates
1907 * next xfernotready and we will issue
1908 * a fresh START TRANSFER.
1909 * If there are still queued request
1910 * then wait, do not issue either END
1911 * or UPDATE TRANSFER, just attach next
1912 * request in request_list during
1913 * giveback.If any future queued request
1914 * is successfully transferred then we
1915 * will issue UPDATE TRANSFER for all
1916 * request in the request_list.
1917 */
1918 dep->flags |= DWC3_EP_MISSED_ISOC;
1919 } else {
1920 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1921 dep->name);
1922 status = -ECONNRESET;
1923 }
1924 } else {
1925 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1926 }
1927 } else {
1928 if (count && (event->status & DEPEVT_STATUS_SHORT))
1929 s_pkt = 1;
1930 }
1931
1932 /*
1933 * We assume here we will always receive the entire data block
1934 * which we should receive. Meaning, if we program RX to
1935 * receive 4K but we receive only 2K, we assume that's all we
1936 * should receive and we simply bounce the request back to the
1937 * gadget driver for further processing.
1938 */
1939 req->request.actual += req->request.length - count;
1940 if (s_pkt)
1941 return 1;
1942 if ((event->status & DEPEVT_STATUS_LST) &&
1943 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1944 DWC3_TRB_CTRL_HWO)))
1945 return 1;
1946 if ((event->status & DEPEVT_STATUS_IOC) &&
1947 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1948 return 1;
1949 return 0;
1950}
1951
1952static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1953 const struct dwc3_event_depevt *event, int status)
1954{
1955 struct dwc3_request *req;
1956 struct dwc3_trb *trb;
1957 unsigned int slot;
1958 unsigned int i;
1959 int ret;
1960
72246da4 1961 do {
d115d705 1962 req = next_request(&dep->req_queued);
ac7bdcc1 1963 if (WARN_ON_ONCE(!req))
d115d705 1964 return 1;
ac7bdcc1 1965
d115d705
VS		 1966 i = 0;
1967 do {
1968 slot = req->start_slot + i;
1969 if ((slot == DWC3_TRB_NUM - 1) &&
e5ba5ec8 1970 usb_endpoint_xfer_isoc(dep->endpoint.desc))
d115d705
VS		 1971 slot++;
1972 slot %= DWC3_TRB_NUM;
1973 trb = &dep->trb_pool[slot];
1974
1975 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1976 event, status);
1977 if (ret)
1978 break;
1979 } while (++i < req->request.num_mapped_sgs);
1980
1981 dwc3_gadget_giveback(dep, req, status);
e5ba5ec8
PA		 1982
1983 if (ret)
72246da4 1984 break;
d115d705 1985 } while (1);
72246da4 1986
cdc359dd
PA		 1987 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1988 list_empty(&dep->req_queued)) {
1989 if (list_empty(&dep->request_list)) {
1990 /*
1991 * If there is no entry in request list then do
1992 * not issue END TRANSFER now. Just set PENDING
1993 * flag, so that END TRANSFER is issued when an
1994 * entry is added into request list.
1995 */
1996 dep->flags = DWC3_EP_PENDING_REQUEST;
1997 } else {
b992e681 1998 dwc3_stop_active_transfer(dwc, dep->number, true);
cdc359dd
PA		 1999 dep->flags = DWC3_EP_ENABLED;
2000 }
7efea86c
PA		 2001 return 1;
2002 }
2003
72246da4
FB		 2004 return 1;
2005}
2006
2007static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
029d97ff 2008 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
72246da4
FB		 2009{
2010 unsigned status = 0;
2011 int clean_busy;
e18b7975
FB		 2012 u32 is_xfer_complete;
2013
2014 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
72246da4
FB		 2015
2016 if (event->status & DEPEVT_STATUS_BUSERR)
2017 status = -ECONNRESET;
2018
1d046793 2019 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
e18b7975
FB		 2020 if (clean_busy && (is_xfer_complete ||
2021 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
72246da4 2022 dep->flags &= ~DWC3_EP_BUSY;
fae2b904
FB		 2023
2024 /*
2025 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2026 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2027 */
2028 if (dwc->revision < DWC3_REVISION_183A) {
2029 u32 reg;
2030 int i;
2031
2032 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
348e026f 2033 dep = dwc->eps[i];
fae2b904
FB		 2034
2035 if (!(dep->flags & DWC3_EP_ENABLED))
2036 continue;
2037
2038 if (!list_empty(&dep->req_queued))
2039 return;
2040 }
2041
2042 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2043 reg |= dwc->u1u2;
2044 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2045
2046 dwc->u1u2 = 0;
2047 }
8a1a9c9e 2048
e6e709b7 2049 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
8a1a9c9e
FB		 2050 int ret;
2051
e6e709b7 2052 ret = __dwc3_gadget_kick_transfer(dep, 0, is_xfer_complete);
8a1a9c9e
FB		 2053 if (!ret || ret == -EBUSY)
2054 return;
2055 }
72246da4
FB		 2056}
2057
72246da4
FB		 2058static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2059 const struct dwc3_event_depevt *event)
2060{
2061 struct dwc3_ep *dep;
2062 u8 epnum = event->endpoint_number;
2063
2064 dep = dwc->eps[epnum];
2065
3336abb5
FB		 2066 if (!(dep->flags & DWC3_EP_ENABLED))
2067 return;
2068
72246da4
FB		 2069 if (epnum == 0 || epnum == 1) {
2070 dwc3_ep0_interrupt(dwc, event);
2071 return;
2072 }
2073
2074 switch (event->endpoint_event) {
2075 case DWC3_DEPEVT_XFERCOMPLETE:
b4996a86 2076 dep->resource_index = 0;
c2df85ca 2077
16e78db7 2078 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
ec5e795c
FB		 2079 dwc3_trace(trace_dwc3_gadget,
2080 "%s is an Isochronous endpoint\n",
72246da4
FB		 2081 dep->name);
2082 return;
2083 }
2084
029d97ff 2085 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2086 break;
2087 case DWC3_DEPEVT_XFERINPROGRESS:
029d97ff 2088 dwc3_endpoint_transfer_complete(dwc, dep, event);
72246da4
FB		 2089 break;
2090 case DWC3_DEPEVT_XFERNOTREADY:
16e78db7 2091 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
72246da4
FB		 2092 dwc3_gadget_start_isoc(dwc, dep, event);
2093 } else {
6bb4fe12 2094 int active;
72246da4
FB		 2095 int ret;
2096
6bb4fe12
FB		 2097 active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2098
73815280 2099 dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
6bb4fe12 2100 dep->name, active ? "Transfer Active"
72246da4
FB		 2101 : "Transfer Not Active");
2102
6bb4fe12 2103 ret = __dwc3_gadget_kick_transfer(dep, 0, !active);
72246da4
FB		 2104 if (!ret || ret == -EBUSY)
2105 return;
2106
ec5e795c
FB		 2107 dwc3_trace(trace_dwc3_gadget,
2108 "%s: failed to kick transfers\n",
72246da4
FB		 2109 dep->name);
2110 }
2111
879631aa
FB		 2112 break;
2113 case DWC3_DEPEVT_STREAMEVT:
16e78db7 2114 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
879631aa
FB		 2115 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2116 dep->name);
2117 return;
2118 }
2119
2120 switch (event->status) {
2121 case DEPEVT_STREAMEVT_FOUND:
73815280
FB		 2122 dwc3_trace(trace_dwc3_gadget,
2123 "Stream %d found and started",
879631aa
FB		 2124 event->parameters);
2125
2126 break;
2127 case DEPEVT_STREAMEVT_NOTFOUND:
2128 /* FALLTHROUGH */
2129 default:
ec5e795c
FB		 2130 dwc3_trace(trace_dwc3_gadget,
2131 "unable to find suitable stream\n");
879631aa 2132 }
72246da4
FB		 2133 break;
2134 case DWC3_DEPEVT_RXTXFIFOEVT:
ec5e795c 2135 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name);
72246da4 2136 break;
72246da4 2137 case DWC3_DEPEVT_EPCMDCMPLT:
73815280 2138 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
72246da4
FB		 2139 break;
2140 }
2141}
2142
2143static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2144{
2145 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2146 spin_unlock(&dwc->lock);
2147 dwc->gadget_driver->disconnect(&dwc->gadget);
2148 spin_lock(&dwc->lock);
2149 }
2150}
2151
bc5ba2e0
FB		 2152static void dwc3_suspend_gadget(struct dwc3 *dwc)
2153{
73a30bfc 2154 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
bc5ba2e0
FB		 2155 spin_unlock(&dwc->lock);
2156 dwc->gadget_driver->suspend(&dwc->gadget);
2157 spin_lock(&dwc->lock);
2158 }
2159}
2160
2161static void dwc3_resume_gadget(struct dwc3 *dwc)
2162{
73a30bfc 2163 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
bc5ba2e0
FB		 2164 spin_unlock(&dwc->lock);
2165 dwc->gadget_driver->resume(&dwc->gadget);
5c7b3b02 2166 spin_lock(&dwc->lock);
8e74475b
FB		 2167 }
2168}
2169
2170static void dwc3_reset_gadget(struct dwc3 *dwc)
2171{
2172 if (!dwc->gadget_driver)
2173 return;
2174
2175 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2176 spin_unlock(&dwc->lock);
2177 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
bc5ba2e0
FB		 2178 spin_lock(&dwc->lock);
2179 }
2180}
2181
b992e681 2182static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
72246da4
FB		 2183{
2184 struct dwc3_ep *dep;
2185 struct dwc3_gadget_ep_cmd_params params;
2186 u32 cmd;
2187 int ret;
2188
2189 dep = dwc->eps[epnum];
2190
b4996a86 2191 if (!dep->resource_index)
3daf74d7
PA		 2192 return;
2193
57911504
PA		 2194 /*
2195 * NOTICE: We are violating what the Databook says about the
2196 * EndTransfer command. Ideally we would _always_ wait for the
2197 * EndTransfer Command Completion IRQ, but that's causing too
2198 * much trouble synchronizing between us and gadget driver.
2199 *
2200 * We have discussed this with the IP Provider and it was
2201 * suggested to giveback all requests here, but give HW some
2202 * extra time to synchronize with the interconnect. We're using
dc93b41a 2203 * an arbitrary 100us delay for that.
57911504
PA		 2204 *
2205 * Note also that a similar handling was tested by Synopsys
2206 * (thanks a lot Paul) and nothing bad has come out of it.
2207 * In short, what we're doing is:
2208 *
2209 * - Issue EndTransfer WITH CMDIOC bit set
2210 * - Wait 100us
2211 */
2212
3daf74d7 2213 cmd = DWC3_DEPCMD_ENDTRANSFER;
b992e681
PZ		 2214 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2215 cmd |= DWC3_DEPCMD_CMDIOC;
b4996a86 2216 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
3daf74d7
PA		 2217 memset(&params, 0, sizeof(params));
2218 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
2219 WARN_ON_ONCE(ret);
b4996a86 2220 dep->resource_index = 0;
041d81f4 2221 dep->flags &= ~DWC3_EP_BUSY;
57911504 2222 udelay(100);
72246da4
FB		 2223}
2224
2225static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2226{
2227 u32 epnum;
2228
2229 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2230 struct dwc3_ep *dep;
2231
2232 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2233 if (!dep)
2234 continue;
2235
72246da4
FB		 2236 if (!(dep->flags & DWC3_EP_ENABLED))
2237 continue;
2238
624407f9 2239 dwc3_remove_requests(dwc, dep);
72246da4
FB		 2240 }
2241}
2242
2243static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2244{
2245 u32 epnum;
2246
2247 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2248 struct dwc3_ep *dep;
2249 struct dwc3_gadget_ep_cmd_params params;
2250 int ret;
2251
2252 dep = dwc->eps[epnum];
6a1e3ef4
FB		 2253 if (!dep)
2254 continue;
72246da4
FB		 2255
2256 if (!(dep->flags & DWC3_EP_STALL))
2257 continue;
2258
2259 dep->flags &= ~DWC3_EP_STALL;
2260
2261 memset(&params, 0, sizeof(params));
2262 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2263 DWC3_DEPCMD_CLEARSTALL, &params);
2264 WARN_ON_ONCE(ret);
2265 }
2266}
2267
2268static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2269{
c4430a26
FB		 2270 int reg;
2271
72246da4
FB		 2272 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2273 reg &= ~DWC3_DCTL_INITU1ENA;
2274 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2275
2276 reg &= ~DWC3_DCTL_INITU2ENA;
2277 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72246da4 2278
72246da4
FB		 2279 dwc3_disconnect_gadget(dwc);
2280
2281 dwc->gadget.speed = USB_SPEED_UNKNOWN;
df62df56 2282 dwc->setup_packet_pending = false;
06a374ed 2283 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
72246da4
FB		 2284}
2285
72246da4
FB		 2286static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2287{
2288 u32 reg;
2289
df62df56
FB		 2290 /*
2291 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2292 * would cause a missing Disconnect Event if there's a
2293 * pending Setup Packet in the FIFO.
2294 *
2295 * There's no suggested workaround on the official Bug
2296 * report, which states that "unless the driver/application
2297 * is doing any special handling of a disconnect event,
2298 * there is no functional issue".
2299 *
2300 * Unfortunately, it turns out that we _do_ some special
2301 * handling of a disconnect event, namely complete all
2302 * pending transfers, notify gadget driver of the
2303 * disconnection, and so on.
2304 *
2305 * Our suggested workaround is to follow the Disconnect
2306 * Event steps here, instead, based on a setup_packet_pending
b5d335e5
FB		 2307 * flag. Such flag gets set whenever we have a SETUP_PENDING
2308 * status for EP0 TRBs and gets cleared on XferComplete for the
df62df56
FB		 2309 * same endpoint.
2310 *
2311 * Refers to:
2312 *
2313 * STAR#9000466709: RTL: Device : Disconnect event not
2314 * generated if setup packet pending in FIFO
2315 */
2316 if (dwc->revision < DWC3_REVISION_188A) {
2317 if (dwc->setup_packet_pending)
2318 dwc3_gadget_disconnect_interrupt(dwc);
2319 }
2320
8e74475b 2321 dwc3_reset_gadget(dwc);
72246da4
FB		 2322
2323 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2324 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2325 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3b637367 2326 dwc->test_mode = false;
72246da4
FB		 2327
2328 dwc3_stop_active_transfers(dwc);
2329 dwc3_clear_stall_all_ep(dwc);
2330
2331 /* Reset device address to zero */
2332 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2333 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2334 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
72246da4
FB		 2335}
2336
2337static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2338{
2339 u32 reg;
2340 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2341
2342 /*
2343 * We change the clock only at SS but I dunno why I would want to do
2344 * this. Maybe it becomes part of the power saving plan.
2345 */
2346
ee5cd41c
JY		 2347 if ((speed != DWC3_DSTS_SUPERSPEED) &&
2348 (speed != DWC3_DSTS_SUPERSPEED_PLUS))
72246da4
FB		 2349 return;
2350
2351 /*
2352 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2353 * each time on Connect Done.
2354 */
2355 if (!usb30_clock)
2356 return;
2357
2358 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2359 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2360 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2361}
2362
72246da4
FB		 2363static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2364{
72246da4
FB		 2365 struct dwc3_ep *dep;
2366 int ret;
2367 u32 reg;
2368 u8 speed;
2369
72246da4
FB		 2370 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2371 speed = reg & DWC3_DSTS_CONNECTSPD;
2372 dwc->speed = speed;
2373
2374 dwc3_update_ram_clk_sel(dwc, speed);
2375
2376 switch (speed) {
7580862b
JY		 2377 case DWC3_DCFG_SUPERSPEED_PLUS:
2378 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2379 dwc->gadget.ep0->maxpacket = 512;
2380 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2381 break;
72246da4 2382 case DWC3_DCFG_SUPERSPEED:
05870c5b
FB		 2383 /*
2384 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2385 * would cause a missing USB3 Reset event.
2386 *
2387 * In such situations, we should force a USB3 Reset
2388 * event by calling our dwc3_gadget_reset_interrupt()
2389 * routine.
2390 *
2391 * Refers to:
2392 *
2393 * STAR#9000483510: RTL: SS : USB3 reset event may
2394 * not be generated always when the link enters poll
2395 */
2396 if (dwc->revision < DWC3_REVISION_190A)
2397 dwc3_gadget_reset_interrupt(dwc);
2398
72246da4
FB		 2399 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2400 dwc->gadget.ep0->maxpacket = 512;
2401 dwc->gadget.speed = USB_SPEED_SUPER;
2402 break;
2403 case DWC3_DCFG_HIGHSPEED:
2404 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2405 dwc->gadget.ep0->maxpacket = 64;
2406 dwc->gadget.speed = USB_SPEED_HIGH;
2407 break;
2408 case DWC3_DCFG_FULLSPEED2:
2409 case DWC3_DCFG_FULLSPEED1:
2410 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2411 dwc->gadget.ep0->maxpacket = 64;
2412 dwc->gadget.speed = USB_SPEED_FULL;
2413 break;
2414 case DWC3_DCFG_LOWSPEED:
2415 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2416 dwc->gadget.ep0->maxpacket = 8;
2417 dwc->gadget.speed = USB_SPEED_LOW;
2418 break;
2419 }
2420
2b758350
PA		 2421 /* Enable USB2 LPM Capability */
2422
ee5cd41c
JY		 2423 if ((dwc->revision > DWC3_REVISION_194A) &&
2424 (speed != DWC3_DCFG_SUPERSPEED) &&
2425 (speed != DWC3_DCFG_SUPERSPEED_PLUS)) {
2b758350
PA		 2426 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2427 reg |= DWC3_DCFG_LPM_CAP;
2428 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2429
2430 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2431 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2432
460d098c 2433 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2b758350 2434
80caf7d2
HR		 2435 /*
2436 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2437 * DCFG.LPMCap is set, core responses with an ACK and the
2438 * BESL value in the LPM token is less than or equal to LPM
2439 * NYET threshold.
2440 */
2441 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2442 && dwc->has_lpm_erratum,
2443 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2444
2445 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2446 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2447
356363bf
FB		 2448 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2449 } else {
2450 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2451 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2b758350
PA		 2452 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2453 }
2454
72246da4 2455 dep = dwc->eps[0];
265b70a7
PZ		 2456 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2457 false);
72246da4
FB		 2458 if (ret) {
2459 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2460 return;
2461 }
2462
2463 dep = dwc->eps[1];
265b70a7
PZ		 2464 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2465 false);
72246da4
FB		 2466 if (ret) {
2467 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2468 return;
2469 }
2470
2471 /*
2472 * Configure PHY via GUSB3PIPECTLn if required.
2473 *
2474 * Update GTXFIFOSIZn
2475 *
2476 * In both cases reset values should be sufficient.
2477 */
2478}
2479
2480static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2481{
72246da4
FB		 2482 /*
2483 * TODO take core out of low power mode when that's
2484 * implemented.
2485 */
2486
2487 dwc->gadget_driver->resume(&dwc->gadget);
2488}
2489
2490static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2491 unsigned int evtinfo)
2492{
fae2b904 2493 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
0b0cc1cd
FB		 2494 unsigned int pwropt;
2495
2496 /*
2497 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2498 * Hibernation mode enabled which would show up when device detects
2499 * host-initiated U3 exit.
2500 *
2501 * In that case, device will generate a Link State Change Interrupt
2502 * from U3 to RESUME which is only necessary if Hibernation is
2503 * configured in.
2504 *
2505 * There are no functional changes due to such spurious event and we
2506 * just need to ignore it.
2507 *
2508 * Refers to:
2509 *
2510 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2511 * operational mode
2512 */
2513 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2514 if ((dwc->revision < DWC3_REVISION_250A) &&
2515 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2516 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2517 (next == DWC3_LINK_STATE_RESUME)) {
73815280
FB		 2518 dwc3_trace(trace_dwc3_gadget,
2519 "ignoring transition U3 -> Resume");
0b0cc1cd
FB		 2520 return;
2521 }
2522 }
fae2b904
FB		 2523
2524 /*
2525 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2526 * on the link partner, the USB session might do multiple entry/exit
2527 * of low power states before a transfer takes place.
2528 *
2529 * Due to this problem, we might experience lower throughput. The
2530 * suggested workaround is to disable DCTL[12:9] bits if we're
2531 * transitioning from U1/U2 to U0 and enable those bits again
2532 * after a transfer completes and there are no pending transfers
2533 * on any of the enabled endpoints.
2534 *
2535 * This is the first half of that workaround.
2536 *
2537 * Refers to:
2538 *
2539 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2540 * core send LGO_Ux entering U0
2541 */
2542 if (dwc->revision < DWC3_REVISION_183A) {
2543 if (next == DWC3_LINK_STATE_U0) {
2544 u32 u1u2;
2545 u32 reg;
2546
2547 switch (dwc->link_state) {
2548 case DWC3_LINK_STATE_U1:
2549 case DWC3_LINK_STATE_U2:
2550 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2551 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2552 | DWC3_DCTL_ACCEPTU2ENA
2553 | DWC3_DCTL_INITU1ENA
2554 | DWC3_DCTL_ACCEPTU1ENA);
2555
2556 if (!dwc->u1u2)
2557 dwc->u1u2 = reg & u1u2;
2558
2559 reg &= ~u1u2;
2560
2561 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2562 break;
2563 default:
2564 /* do nothing */
2565 break;
2566 }
2567 }
2568 }
2569
bc5ba2e0
FB		 2570 switch (next) {
2571 case DWC3_LINK_STATE_U1:
2572 if (dwc->speed == USB_SPEED_SUPER)
2573 dwc3_suspend_gadget(dwc);
2574 break;
2575 case DWC3_LINK_STATE_U2:
2576 case DWC3_LINK_STATE_U3:
2577 dwc3_suspend_gadget(dwc);
2578 break;
2579 case DWC3_LINK_STATE_RESUME:
2580 dwc3_resume_gadget(dwc);
2581 break;
2582 default:
2583 /* do nothing */
2584 break;
2585 }
2586
e57ebc1d 2587 dwc->link_state = next;
72246da4
FB		 2588}
2589
e1dadd3b
FB		 2590static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2591 unsigned int evtinfo)
2592{
2593 unsigned int is_ss = evtinfo & BIT(4);
2594
2595 /**
2596 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2597 * have a known issue which can cause USB CV TD.9.23 to fail
2598 * randomly.
2599 *
2600 * Because of this issue, core could generate bogus hibernation
2601 * events which SW needs to ignore.
2602 *
2603 * Refers to:
2604 *
2605 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2606 * Device Fallback from SuperSpeed
2607 */
2608 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2609 return;
2610
2611 /* enter hibernation here */
2612}
2613
72246da4
FB		 2614static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2615 const struct dwc3_event_devt *event)
2616{
2617 switch (event->type) {
2618 case DWC3_DEVICE_EVENT_DISCONNECT:
2619 dwc3_gadget_disconnect_interrupt(dwc);
2620 break;
2621 case DWC3_DEVICE_EVENT_RESET:
2622 dwc3_gadget_reset_interrupt(dwc);
2623 break;
2624 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2625 dwc3_gadget_conndone_interrupt(dwc);
2626 break;
2627 case DWC3_DEVICE_EVENT_WAKEUP:
2628 dwc3_gadget_wakeup_interrupt(dwc);
2629 break;
e1dadd3b
FB		 2630 case DWC3_DEVICE_EVENT_HIBER_REQ:
2631 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2632 "unexpected hibernation event\n"))
2633 break;
2634
2635 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2636 break;
72246da4
FB		 2637 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2638 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2639 break;
2640 case DWC3_DEVICE_EVENT_EOPF:
73815280 2641 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
72246da4
FB		 2642 break;
2643 case DWC3_DEVICE_EVENT_SOF:
73815280 2644 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
72246da4
FB		 2645 break;
2646 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
73815280 2647 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
72246da4
FB		 2648 break;
2649 case DWC3_DEVICE_EVENT_CMD_CMPL:
73815280 2650 dwc3_trace(trace_dwc3_gadget, "Command Complete");
72246da4
FB		 2651 break;
2652 case DWC3_DEVICE_EVENT_OVERFLOW:
73815280 2653 dwc3_trace(trace_dwc3_gadget, "Overflow");
72246da4
FB		 2654 break;
2655 default:
e9f2aa87 2656 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
72246da4
FB		 2657 }
2658}
2659
2660static void dwc3_process_event_entry(struct dwc3 *dwc,
2661 const union dwc3_event *event)
2662{
2c4cbe6e
FB		 2663 trace_dwc3_event(event->raw);
2664
72246da4
FB		 2665 /* Endpoint IRQ, handle it and return early */
2666 if (event->type.is_devspec == 0) {
2667 /* depevt */
2668 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2669 }
2670
2671 switch (event->type.type) {
2672 case DWC3_EVENT_TYPE_DEV:
2673 dwc3_gadget_interrupt(dwc, &event->devt);
2674 break;
2675 /* REVISIT what to do with Carkit and I2C events ? */
2676 default:
2677 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2678 }
2679}
2680
f42f2447 2681static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
b15a762f 2682{
f42f2447 2683 struct dwc3_event_buffer *evt;
b15a762f 2684 irqreturn_t ret = IRQ_NONE;
f42f2447 2685 int left;
e8adfc30 2686 u32 reg;
b15a762f 2687
f42f2447
FB		 2688 evt = dwc->ev_buffs[buf];
2689 left = evt->count;
b15a762f 2690
f42f2447
FB		 2691 if (!(evt->flags & DWC3_EVENT_PENDING))
2692 return IRQ_NONE;
b15a762f 2693
f42f2447
FB		 2694 while (left > 0) {
2695 union dwc3_event event;
b15a762f 2696
f42f2447 2697 event.raw = *(u32 *) (evt->buf + evt->lpos);
b15a762f 2698
f42f2447 2699 dwc3_process_event_entry(dwc, &event);
b15a762f 2700
f42f2447
FB		 2701 /*
2702 * FIXME we wrap around correctly to the next entry as
2703 * almost all entries are 4 bytes in size. There is one
2704 * entry which has 12 bytes which is a regular entry
2705 * followed by 8 bytes data. ATM I don't know how
2706 * things are organized if we get next to the a
2707 * boundary so I worry about that once we try to handle
2708 * that.
2709 */
2710 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2711 left -= 4;
b15a762f 2712
f42f2447
FB		 2713 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2714 }
b15a762f 2715
f42f2447
FB		 2716 evt->count = 0;
2717 evt->flags &= ~DWC3_EVENT_PENDING;
2718 ret = IRQ_HANDLED;
b15a762f 2719
f42f2447
FB		 2720 /* Unmask interrupt */
2721 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2722 reg &= ~DWC3_GEVNTSIZ_INTMASK;
2723 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
b15a762f 2724
f42f2447
FB		 2725 return ret;
2726}
e8adfc30 2727
f42f2447
FB		 2728static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2729{
2730 struct dwc3 *dwc = _dwc;
e5f68b4a 2731 unsigned long flags;
f42f2447
FB		 2732 irqreturn_t ret = IRQ_NONE;
2733 int i;
2734
e5f68b4a 2735 spin_lock_irqsave(&dwc->lock, flags);
f42f2447
FB		 2736
2737 for (i = 0; i < dwc->num_event_buffers; i++)
2738 ret |= dwc3_process_event_buf(dwc, i);
b15a762f 2739
e5f68b4a 2740 spin_unlock_irqrestore(&dwc->lock, flags);
b15a762f
FB		 2741
2742 return ret;
2743}
2744
7f97aa98 2745static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
72246da4
FB		 2746{
2747 struct dwc3_event_buffer *evt;
72246da4 2748 u32 count;
e8adfc30 2749 u32 reg;
72246da4 2750
b15a762f
FB		 2751 evt = dwc->ev_buffs[buf];
2752
72246da4
FB		 2753 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2754 count &= DWC3_GEVNTCOUNT_MASK;
2755 if (!count)
2756 return IRQ_NONE;
2757
b15a762f
FB		 2758 evt->count = count;
2759 evt->flags |= DWC3_EVENT_PENDING;
72246da4 2760
e8adfc30
FB		 2761 /* Mask interrupt */
2762 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2763 reg |= DWC3_GEVNTSIZ_INTMASK;
2764 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2765
b15a762f 2766 return IRQ_WAKE_THREAD;
72246da4
FB		 2767}
2768
2769static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2770{
2771 struct dwc3 *dwc = _dwc;
2772 int i;
2773 irqreturn_t ret = IRQ_NONE;
2774
9f622b2a 2775 for (i = 0; i < dwc->num_event_buffers; i++) {
72246da4
FB		 2776 irqreturn_t status;
2777
7f97aa98 2778 status = dwc3_check_event_buf(dwc, i);
b15a762f 2779 if (status == IRQ_WAKE_THREAD)
72246da4
FB		 2780 ret = status;
2781 }
2782
72246da4
FB		 2783 return ret;
2784}
2785
2786/**
2787 * dwc3_gadget_init - Initializes gadget related registers
1d046793 2788 * @dwc: pointer to our controller context structure
72246da4
FB		 2789 *
2790 * Returns 0 on success otherwise negative errno.
2791 */
41ac7b3a 2792int dwc3_gadget_init(struct dwc3 *dwc)
72246da4 2793{
72246da4 2794 int ret;
72246da4
FB		 2795
2796 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2797 &dwc->ctrl_req_addr, GFP_KERNEL);
2798 if (!dwc->ctrl_req) {
2799 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2800 ret = -ENOMEM;
2801 goto err0;
2802 }
2803
2abd9d5f 2804 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
72246da4
FB		 2805 &dwc->ep0_trb_addr, GFP_KERNEL);
2806 if (!dwc->ep0_trb) {
2807 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2808 ret = -ENOMEM;
2809 goto err1;
2810 }
2811
3ef35faf 2812 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
72246da4 2813 if (!dwc->setup_buf) {
72246da4
FB		 2814 ret = -ENOMEM;
2815 goto err2;
2816 }
2817
5812b1c2 2818 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
3ef35faf
FB		 2819 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2820 GFP_KERNEL);
5812b1c2
FB		 2821 if (!dwc->ep0_bounce) {
2822 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2823 ret = -ENOMEM;
2824 goto err3;
2825 }
2826
04c03d10
FB		 2827 dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2828 if (!dwc->zlp_buf) {
2829 ret = -ENOMEM;
2830 goto err4;
2831 }
2832
72246da4 2833 dwc->gadget.ops = &dwc3_gadget_ops;
72246da4 2834 dwc->gadget.speed = USB_SPEED_UNKNOWN;
eeb720fb 2835 dwc->gadget.sg_supported = true;
72246da4 2836 dwc->gadget.name = "dwc3-gadget";
6a4290cc 2837 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
72246da4 2838
b9e51b2b
BM		 2839 /*
2840 * FIXME We might be setting max_speed to <SUPER, however versions
2841 * <2.20a of dwc3 have an issue with metastability (documented
2842 * elsewhere in this driver) which tells us we can't set max speed to
2843 * anything lower than SUPER.
2844 *
2845 * Because gadget.max_speed is only used by composite.c and function
2846 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2847 * to happen so we avoid sending SuperSpeed Capability descriptor
2848 * together with our BOS descriptor as that could confuse host into
2849 * thinking we can handle super speed.
2850 *
2851 * Note that, in fact, we won't even support GetBOS requests when speed
2852 * is less than super speed because we don't have means, yet, to tell
2853 * composite.c that we are USB 2.0 + LPM ECN.
2854 */
2855 if (dwc->revision < DWC3_REVISION_220A)
2856 dwc3_trace(trace_dwc3_gadget,
2857 "Changing max_speed on rev %08x\n",
2858 dwc->revision);
2859
2860 dwc->gadget.max_speed = dwc->maximum_speed;
2861
a4b9d94b
DC		 2862 /*
2863 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2864 * on ep out.
2865 */
2866 dwc->gadget.quirk_ep_out_aligned_size = true;
2867
72246da4
FB		 2868 /*
2869 * REVISIT: Here we should clear all pending IRQs to be
2870 * sure we're starting from a well known location.
2871 */
2872
2873 ret = dwc3_gadget_init_endpoints(dwc);
2874 if (ret)
04c03d10 2875 goto err5;
72246da4 2876
72246da4
FB		 2877 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2878 if (ret) {
2879 dev_err(dwc->dev, "failed to register udc\n");
04c03d10 2880 goto err5;
72246da4
FB		 2881 }
2882
2883 return 0;
2884
04c03d10
FB		 2885err5:
2886 kfree(dwc->zlp_buf);
2887
5812b1c2 2888err4:
e1f80467 2889 dwc3_gadget_free_endpoints(dwc);
3ef35faf
FB		 2890 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2891 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 2892
72246da4 2893err3:
0fc9a1be 2894 kfree(dwc->setup_buf);
72246da4
FB		 2895
2896err2:
2897 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2898 dwc->ep0_trb, dwc->ep0_trb_addr);
2899
2900err1:
2901 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2902 dwc->ctrl_req, dwc->ctrl_req_addr);
2903
2904err0:
2905 return ret;
2906}
2907
7415f17c
FB		 2908/* -------------------------------------------------------------------------- */
2909
72246da4
FB		 2910void dwc3_gadget_exit(struct dwc3 *dwc)
2911{
72246da4 2912 usb_del_gadget_udc(&dwc->gadget);
72246da4 2913
72246da4
FB		 2914 dwc3_gadget_free_endpoints(dwc);
2915
3ef35faf
FB		 2916 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2917 dwc->ep0_bounce, dwc->ep0_bounce_addr);
5812b1c2 2918
0fc9a1be 2919 kfree(dwc->setup_buf);
04c03d10 2920 kfree(dwc->zlp_buf);
72246da4
FB		 2921
2922 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2923 dwc->ep0_trb, dwc->ep0_trb_addr);
2924
2925 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2926 dwc->ctrl_req, dwc->ctrl_req_addr);
72246da4 2927}
7415f17c 2928
0b0231aa 2929int dwc3_gadget_suspend(struct dwc3 *dwc)
7415f17c 2930{
7b2a0368 2931 if (dwc->pullups_connected) {
7415f17c 2932 dwc3_gadget_disable_irq(dwc);
7b2a0368
FB		 2933 dwc3_gadget_run_stop(dwc, true, true);
2934 }
7415f17c 2935
7415f17c
FB		 2936 __dwc3_gadget_ep_disable(dwc->eps[0]);
2937 __dwc3_gadget_ep_disable(dwc->eps[1]);
2938
2939 dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2940
2941 return 0;
2942}
2943
2944int dwc3_gadget_resume(struct dwc3 *dwc)
2945{
2946 struct dwc3_ep *dep;
2947 int ret;
2948
2949 /* Start with SuperSpeed Default */
2950 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2951
2952 dep = dwc->eps[0];
265b70a7
PZ		 2953 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2954 false);
7415f17c
FB		 2955 if (ret)
2956 goto err0;
2957
2958 dep = dwc->eps[1];
265b70a7
PZ		 2959 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2960 false);
7415f17c
FB		 2961 if (ret)
2962 goto err1;
2963
2964 /* begin to receive SETUP packets */
2965 dwc->ep0state = EP0_SETUP_PHASE;
2966 dwc3_ep0_out_start(dwc);
2967
2968 dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2969
0b0231aa
FB		 2970 if (dwc->pullups_connected) {
2971 dwc3_gadget_enable_irq(dwc);
2972 dwc3_gadget_run_stop(dwc, true, false);
2973 }
2974
7415f17c
FB		 2975 return 0;
2976
2977err1:
2978 __dwc3_gadget_ep_disable(dwc->eps[0]);
2979
2980err0:
2981 return ret;
2982}
Linux kernel - Deliverables
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