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usb: dwc3: gadget: add support for Bursts
[deliverable/linux.git] / drivers / usb / dwc3 / gadget.c
CommitLineData
72246da4
FB		 1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
72246da4
FB		 5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 */
38
39#include <linux/kernel.h>
40#include <linux/delay.h>
41#include <linux/slab.h>
42#include <linux/spinlock.h>
43#include <linux/platform_device.h>
44#include <linux/pm_runtime.h>
45#include <linux/interrupt.h>
46#include <linux/io.h>
47#include <linux/list.h>
48#include <linux/dma-mapping.h>
49
50#include <linux/usb/ch9.h>
51#include <linux/usb/gadget.h>
52
53#include "core.h"
54#include "gadget.h"
55#include "io.h"
56
57#define DMA_ADDR_INVALID (~(dma_addr_t)0)
58
59void dwc3_map_buffer_to_dma(struct dwc3_request *req)
60{
61 struct dwc3 *dwc = req->dep->dwc;
62
78c58a53
SAS		 63 if (req->request.length == 0) {
64 /* req->request.dma = dwc->setup_buf_addr; */
65 return;
66 }
67
72246da4
FB		 68 if (req->request.dma == DMA_ADDR_INVALID) {
69 req->request.dma = dma_map_single(dwc->dev, req->request.buf,
70 req->request.length, req->direction
71 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
72 req->mapped = true;
72246da4
FB		 73 }
74}
75
76void dwc3_unmap_buffer_from_dma(struct dwc3_request *req)
77{
78 struct dwc3 *dwc = req->dep->dwc;
79
78c58a53
SAS		 80 if (req->request.length == 0) {
81 req->request.dma = DMA_ADDR_INVALID;
82 return;
83 }
84
72246da4
FB		 85 if (req->mapped) {
86 dma_unmap_single(dwc->dev, req->request.dma,
87 req->request.length, req->direction
88 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
89 req->mapped = 0;
f198ead2 90 req->request.dma = DMA_ADDR_INVALID;
72246da4
FB		 91 }
92}
93
94void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
95 int status)
96{
97 struct dwc3 *dwc = dep->dwc;
98
99 if (req->queued) {
100 dep->busy_slot++;
101 /*
102 * Skip LINK TRB. We can't use req->trb and check for
103 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
104 * completed (not the LINK TRB).
105 */
106 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
107 usb_endpoint_xfer_isoc(dep->desc))
108 dep->busy_slot++;
109 }
110 list_del(&req->list);
111
112 if (req->request.status == -EINPROGRESS)
113 req->request.status = status;
114
115 dwc3_unmap_buffer_from_dma(req);
116
117 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
118 req, dep->name, req->request.actual,
119 req->request.length, status);
120
121 spin_unlock(&dwc->lock);
122 req->request.complete(&req->dep->endpoint, &req->request);
123 spin_lock(&dwc->lock);
124}
125
126static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
127{
128 switch (cmd) {
129 case DWC3_DEPCMD_DEPSTARTCFG:
130 return "Start New Configuration";
131 case DWC3_DEPCMD_ENDTRANSFER:
132 return "End Transfer";
133 case DWC3_DEPCMD_UPDATETRANSFER:
134 return "Update Transfer";
135 case DWC3_DEPCMD_STARTTRANSFER:
136 return "Start Transfer";
137 case DWC3_DEPCMD_CLEARSTALL:
138 return "Clear Stall";
139 case DWC3_DEPCMD_SETSTALL:
140 return "Set Stall";
141 case DWC3_DEPCMD_GETSEQNUMBER:
142 return "Get Data Sequence Number";
143 case DWC3_DEPCMD_SETTRANSFRESOURCE:
144 return "Set Endpoint Transfer Resource";
145 case DWC3_DEPCMD_SETEPCONFIG:
146 return "Set Endpoint Configuration";
147 default:
148 return "UNKNOWN command";
149 }
150}
151
152int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
153 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
154{
155 struct dwc3_ep *dep = dwc->eps[ep];
61d58242 156 u32 timeout = 500;
72246da4
FB		 157 u32 reg;
158
159 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
160 dep->name,
161 dwc3_gadget_ep_cmd_string(cmd), params->param0.raw,
162 params->param1.raw, params->param2.raw);
163
164 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0.raw);
165 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1.raw);
166 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2.raw);
167
168 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
169 do {
170 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
171 if (!(reg & DWC3_DEPCMD_CMDACT)) {
164f6e14
FB		 172 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
173 DWC3_DEPCMD_STATUS(reg));
72246da4
FB		 174 return 0;
175 }
176
177 /*
72246da4
FB		 178 * We can't sleep here, because it is also called from
179 * interrupt context.
180 */
181 timeout--;
182 if (!timeout)
183 return -ETIMEDOUT;
184
61d58242 185 udelay(1);
72246da4
FB		 186 } while (1);
187}
188
189static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
190 struct dwc3_trb_hw *trb)
191{
c439ef87 192 u32 offset = (char *) trb - (char *) dep->trb_pool;
72246da4
FB		 193
194 return dep->trb_pool_dma + offset;
195}
196
197static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
198{
199 struct dwc3 *dwc = dep->dwc;
200
201 if (dep->trb_pool)
202 return 0;
203
204 if (dep->number == 0 || dep->number == 1)
205 return 0;
206
207 dep->trb_pool = dma_alloc_coherent(dwc->dev,
208 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
209 &dep->trb_pool_dma, GFP_KERNEL);
210 if (!dep->trb_pool) {
211 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
212 dep->name);
213 return -ENOMEM;
214 }
215
216 return 0;
217}
218
219static void dwc3_free_trb_pool(struct dwc3_ep *dep)
220{
221 struct dwc3 *dwc = dep->dwc;
222
223 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
224 dep->trb_pool, dep->trb_pool_dma);
225
226 dep->trb_pool = NULL;
227 dep->trb_pool_dma = 0;
228}
229
230static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
231{
232 struct dwc3_gadget_ep_cmd_params params;
233 u32 cmd;
234
235 memset(&params, 0x00, sizeof(params));
236
237 if (dep->number != 1) {
238 cmd = DWC3_DEPCMD_DEPSTARTCFG;
239 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
b23c8439
PZ		 240 if (dep->number > 1) {
241 if (dwc->start_config_issued)
242 return 0;
243 dwc->start_config_issued = true;
72246da4 244 cmd |= DWC3_DEPCMD_PARAM(2);
b23c8439 245 }
72246da4
FB		 246
247 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
248 }
249
250 return 0;
251}
252
253static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
254 const struct usb_endpoint_descriptor *desc)
255{
256 struct dwc3_gadget_ep_cmd_params params;
257
258 memset(&params, 0x00, sizeof(params));
259
260 params.param0.depcfg.ep_type = usb_endpoint_type(desc);
29cc8897 261 params.param0.depcfg.max_packet_size = usb_endpoint_maxp(desc);
a4af9008 262 params.param0.depcfg.burst_size = dep->endpoint.maxburst;
72246da4
FB		 263
264 params.param1.depcfg.xfer_complete_enable = true;
265 params.param1.depcfg.xfer_not_ready_enable = true;
266
267 if (usb_endpoint_xfer_isoc(desc))
268 params.param1.depcfg.xfer_in_progress_enable = true;
269
270 /*
271 * We are doing 1:1 mapping for endpoints, meaning
272 * Physical Endpoints 2 maps to Logical Endpoint 2 and
273 * so on. We consider the direction bit as part of the physical
274 * endpoint number. So USB endpoint 0x81 is 0x03.
275 */
276 params.param1.depcfg.ep_number = dep->number;
277
278 /*
279 * We must use the lower 16 TX FIFOs even though
280 * HW might have more
281 */
282 if (dep->direction)
283 params.param0.depcfg.fifo_number = dep->number >> 1;
284
285 if (desc->bInterval) {
286 params.param1.depcfg.binterval_m1 = desc->bInterval - 1;
287 dep->interval = 1 << (desc->bInterval - 1);
288 }
289
290 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
291 DWC3_DEPCMD_SETEPCONFIG, &params);
292}
293
294static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
295{
296 struct dwc3_gadget_ep_cmd_params params;
297
298 memset(&params, 0x00, sizeof(params));
299
300 params.param0.depxfercfg.number_xfer_resources = 1;
301
302 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
303 DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
304}
305
306/**
307 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
308 * @dep: endpoint to be initialized
309 * @desc: USB Endpoint Descriptor
310 *
311 * Caller should take care of locking
312 */
313static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
314 const struct usb_endpoint_descriptor *desc)
315{
316 struct dwc3 *dwc = dep->dwc;
317 u32 reg;
318 int ret = -ENOMEM;
319
320 if (!(dep->flags & DWC3_EP_ENABLED)) {
321 ret = dwc3_gadget_start_config(dwc, dep);
322 if (ret)
323 return ret;
324 }
325
326 ret = dwc3_gadget_set_ep_config(dwc, dep, desc);
327 if (ret)
328 return ret;
329
330 if (!(dep->flags & DWC3_EP_ENABLED)) {
331 struct dwc3_trb_hw *trb_st_hw;
332 struct dwc3_trb_hw *trb_link_hw;
333 struct dwc3_trb trb_link;
334
335 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
336 if (ret)
337 return ret;
338
339 dep->desc = desc;
340 dep->type = usb_endpoint_type(desc);
341 dep->flags |= DWC3_EP_ENABLED;
342
343 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
344 reg |= DWC3_DALEPENA_EP(dep->number);
345 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
346
347 if (!usb_endpoint_xfer_isoc(desc))
348 return 0;
349
350 memset(&trb_link, 0, sizeof(trb_link));
351
352 /* Link TRB for ISOC. The HWO but is never reset */
353 trb_st_hw = &dep->trb_pool[0];
354
355 trb_link.bplh = dwc3_trb_dma_offset(dep, trb_st_hw);
356 trb_link.trbctl = DWC3_TRBCTL_LINK_TRB;
357 trb_link.hwo = true;
358
359 trb_link_hw = &dep->trb_pool[DWC3_TRB_NUM - 1];
360 dwc3_trb_to_hw(&trb_link, trb_link_hw);
361 }
362
363 return 0;
364}
365
624407f9
SAS		 366static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
367static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
72246da4
FB		 368{
369 struct dwc3_request *req;
370
624407f9
SAS		 371 if (!list_empty(&dep->req_queued))
372 dwc3_stop_active_transfer(dwc, dep->number);
373
72246da4
FB		 374 while (!list_empty(&dep->request_list)) {
375 req = next_request(&dep->request_list);
376
624407f9 377 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
72246da4 378 }
72246da4
FB		 379}
380
381/**
382 * __dwc3_gadget_ep_disable - Disables a HW endpoint
383 * @dep: the endpoint to disable
384 *
624407f9
SAS		 385 * This function also removes requests which are currently processed ny the
386 * hardware and those which are not yet scheduled.
387 * Caller should take care of locking.
72246da4 388 */
72246da4
FB		 389static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
390{
391 struct dwc3 *dwc = dep->dwc;
392 u32 reg;
393
394 dep->flags &= ~DWC3_EP_ENABLED;
624407f9 395 dwc3_remove_requests(dwc, dep);
72246da4
FB		 396
397 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
398 reg &= ~DWC3_DALEPENA_EP(dep->number);
399 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
400
401 dep->desc = NULL;
402 dep->type = 0;
403
404 return 0;
405}
406
407/* -------------------------------------------------------------------------- */
408
409static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
410 const struct usb_endpoint_descriptor *desc)
411{
412 return -EINVAL;
413}
414
415static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
416{
417 return -EINVAL;
418}
419
420/* -------------------------------------------------------------------------- */
421
422static int dwc3_gadget_ep_enable(struct usb_ep *ep,
423 const struct usb_endpoint_descriptor *desc)
424{
425 struct dwc3_ep *dep;
426 struct dwc3 *dwc;
427 unsigned long flags;
428 int ret;
429
430 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
431 pr_debug("dwc3: invalid parameters\n");
432 return -EINVAL;
433 }
434
435 if (!desc->wMaxPacketSize) {
436 pr_debug("dwc3: missing wMaxPacketSize\n");
437 return -EINVAL;
438 }
439
440 dep = to_dwc3_ep(ep);
441 dwc = dep->dwc;
442
443 switch (usb_endpoint_type(desc)) {
444 case USB_ENDPOINT_XFER_CONTROL:
445 strncat(dep->name, "-control", sizeof(dep->name));
446 break;
447 case USB_ENDPOINT_XFER_ISOC:
448 strncat(dep->name, "-isoc", sizeof(dep->name));
449 break;
450 case USB_ENDPOINT_XFER_BULK:
451 strncat(dep->name, "-bulk", sizeof(dep->name));
452 break;
453 case USB_ENDPOINT_XFER_INT:
454 strncat(dep->name, "-int", sizeof(dep->name));
455 break;
456 default:
457 dev_err(dwc->dev, "invalid endpoint transfer type\n");
458 }
459
460 if (dep->flags & DWC3_EP_ENABLED) {
461 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
462 dep->name);
463 return 0;
464 }
465
466 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
467
468 spin_lock_irqsave(&dwc->lock, flags);
469 ret = __dwc3_gadget_ep_enable(dep, desc);
470 spin_unlock_irqrestore(&dwc->lock, flags);
471
472 return ret;
473}
474
475static int dwc3_gadget_ep_disable(struct usb_ep *ep)
476{
477 struct dwc3_ep *dep;
478 struct dwc3 *dwc;
479 unsigned long flags;
480 int ret;
481
482 if (!ep) {
483 pr_debug("dwc3: invalid parameters\n");
484 return -EINVAL;
485 }
486
487 dep = to_dwc3_ep(ep);
488 dwc = dep->dwc;
489
490 if (!(dep->flags & DWC3_EP_ENABLED)) {
491 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
492 dep->name);
493 return 0;
494 }
495
496 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
497 dep->number >> 1,
498 (dep->number & 1) ? "in" : "out");
499
500 spin_lock_irqsave(&dwc->lock, flags);
501 ret = __dwc3_gadget_ep_disable(dep);
502 spin_unlock_irqrestore(&dwc->lock, flags);
503
504 return ret;
505}
506
507static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
508 gfp_t gfp_flags)
509{
510 struct dwc3_request *req;
511 struct dwc3_ep *dep = to_dwc3_ep(ep);
512 struct dwc3 *dwc = dep->dwc;
513
514 req = kzalloc(sizeof(*req), gfp_flags);
515 if (!req) {
516 dev_err(dwc->dev, "not enough memory\n");
517 return NULL;
518 }
519
520 req->epnum = dep->number;
521 req->dep = dep;
522 req->request.dma = DMA_ADDR_INVALID;
523
524 return &req->request;
525}
526
527static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
528 struct usb_request *request)
529{
530 struct dwc3_request *req = to_dwc3_request(request);
531
532 kfree(req);
533}
534
535/*
536 * dwc3_prepare_trbs - setup TRBs from requests
537 * @dep: endpoint for which requests are being prepared
538 * @starting: true if the endpoint is idle and no requests are queued.
539 *
540 * The functions goes through the requests list and setups TRBs for the
541 * transfers. The functions returns once there are not more TRBs available or
542 * it run out of requests.
543 */
544static struct dwc3_request *dwc3_prepare_trbs(struct dwc3_ep *dep,
545 bool starting)
546{
547 struct dwc3_request *req, *n, *ret = NULL;
548 struct dwc3_trb_hw *trb_hw;
549 struct dwc3_trb trb;
550 u32 trbs_left;
551
552 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
553
554 /* the first request must not be queued */
555 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
556 /*
557 * if busy & slot are equal than it is either full or empty. If we are
558 * starting to proceed requests then we are empty. Otherwise we ar
559 * full and don't do anything
560 */
561 if (!trbs_left) {
562 if (!starting)
563 return NULL;
564 trbs_left = DWC3_TRB_NUM;
565 /*
566 * In case we start from scratch, we queue the ISOC requests
567 * starting from slot 1. This is done because we use ring
568 * buffer and have no LST bit to stop us. Instead, we place
569 * IOC bit TRB_NUM/4. We try to avoid to having an interrupt
570 * after the first request so we start at slot 1 and have
571 * 7 requests proceed before we hit the first IOC.
572 * Other transfer types don't use the ring buffer and are
573 * processed from the first TRB until the last one. Since we
574 * don't wrap around we have to start at the beginning.
575 */
576 if (usb_endpoint_xfer_isoc(dep->desc)) {
577 dep->busy_slot = 1;
578 dep->free_slot = 1;
579 } else {
580 dep->busy_slot = 0;
581 dep->free_slot = 0;
582 }
583 }
584
585 /* The last TRB is a link TRB, not used for xfer */
586 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->desc))
587 return NULL;
588
589 list_for_each_entry_safe(req, n, &dep->request_list, list) {
590 unsigned int last_one = 0;
591 unsigned int cur_slot;
592
593 trb_hw = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
594 cur_slot = dep->free_slot;
595 dep->free_slot++;
596
597 /* Skip the LINK-TRB on ISOC */
598 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
599 usb_endpoint_xfer_isoc(dep->desc))
600 continue;
601
602 dwc3_gadget_move_request_queued(req);
603 memset(&trb, 0, sizeof(trb));
604 trbs_left--;
605
606 /* Is our TRB pool empty? */
607 if (!trbs_left)
608 last_one = 1;
609 /* Is this the last request? */
610 if (list_empty(&dep->request_list))
611 last_one = 1;
612
613 /*
614 * FIXME we shouldn't need to set LST bit always but we are
615 * facing some weird problem with the Hardware where it doesn't
616 * complete even though it has been previously started.
617 *
618 * While we're debugging the problem, as a workaround to
619 * multiple TRBs handling, use only one TRB at a time.
620 */
621 last_one = 1;
622
623 req->trb = trb_hw;
624 if (!ret)
625 ret = req;
626
627 trb.bplh = req->request.dma;
628
629 if (usb_endpoint_xfer_isoc(dep->desc)) {
630 trb.isp_imi = true;
631 trb.csp = true;
632 } else {
633 trb.lst = last_one;
634 }
635
636 switch (usb_endpoint_type(dep->desc)) {
637 case USB_ENDPOINT_XFER_CONTROL:
638 trb.trbctl = DWC3_TRBCTL_CONTROL_SETUP;
639 break;
640
641 case USB_ENDPOINT_XFER_ISOC:
5a18999e 642 trb.trbctl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
72246da4
FB		 643
644 /* IOC every DWC3_TRB_NUM / 4 so we can refill */
645 if (!(cur_slot % (DWC3_TRB_NUM / 4)))
646 trb.ioc = last_one;
647 break;
648
649 case USB_ENDPOINT_XFER_BULK:
650 case USB_ENDPOINT_XFER_INT:
651 trb.trbctl = DWC3_TRBCTL_NORMAL;
652 break;
653 default:
654 /*
655 * This is only possible with faulty memory because we
656 * checked it already :)
657 */
658 BUG();
659 }
660
661 trb.length = req->request.length;
662 trb.hwo = true;
663
664 dwc3_trb_to_hw(&trb, trb_hw);
665 req->trb_dma = dwc3_trb_dma_offset(dep, trb_hw);
666
667 if (last_one)
668 break;
669 }
670
671 return ret;
672}
673
674static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
675 int start_new)
676{
677 struct dwc3_gadget_ep_cmd_params params;
678 struct dwc3_request *req;
679 struct dwc3 *dwc = dep->dwc;
680 int ret;
681 u32 cmd;
682
683 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
684 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
685 return -EBUSY;
686 }
687 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
688
689 /*
690 * If we are getting here after a short-out-packet we don't enqueue any
691 * new requests as we try to set the IOC bit only on the last request.
692 */
693 if (start_new) {
694 if (list_empty(&dep->req_queued))
695 dwc3_prepare_trbs(dep, start_new);
696
697 /* req points to the first request which will be sent */
698 req = next_request(&dep->req_queued);
699 } else {
700 /*
701 * req points to the first request where HWO changed
702 * from 0 to 1
703 */
704 req = dwc3_prepare_trbs(dep, start_new);
705 }
706 if (!req) {
707 dep->flags |= DWC3_EP_PENDING_REQUEST;
708 return 0;
709 }
710
711 memset(&params, 0, sizeof(params));
712 params.param0.depstrtxfer.transfer_desc_addr_high =
713 upper_32_bits(req->trb_dma);
714 params.param1.depstrtxfer.transfer_desc_addr_low =
715 lower_32_bits(req->trb_dma);
716
717 if (start_new)
718 cmd = DWC3_DEPCMD_STARTTRANSFER;
719 else
720 cmd = DWC3_DEPCMD_UPDATETRANSFER;
721
722 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
723 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
724 if (ret < 0) {
725 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
726
727 /*
728 * FIXME we need to iterate over the list of requests
729 * here and stop, unmap, free and del each of the linked
730 * requests instead of we do now.
731 */
732 dwc3_unmap_buffer_from_dma(req);
733 list_del(&req->list);
734 return ret;
735 }
736
737 dep->flags |= DWC3_EP_BUSY;
738 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
739 dep->number);
740 if (!dep->res_trans_idx)
741 printk_once(KERN_ERR "%s() res_trans_idx is invalid\n", __func__);
742 return 0;
743}
744
745static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
746{
747 req->request.actual = 0;
748 req->request.status = -EINPROGRESS;
749 req->direction = dep->direction;
750 req->epnum = dep->number;
751
752 /*
753 * We only add to our list of requests now and
754 * start consuming the list once we get XferNotReady
755 * IRQ.
756 *
757 * That way, we avoid doing anything that we don't need
758 * to do now and defer it until the point we receive a
759 * particular token from the Host side.
760 *
761 * This will also avoid Host cancelling URBs due to too
762 * many NACKs.
763 */
764 dwc3_map_buffer_to_dma(req);
765 list_add_tail(&req->list, &dep->request_list);
766
767 /*
768 * There is one special case: XferNotReady with
769 * empty list of requests. We need to kick the
770 * transfer here in that situation, otherwise
771 * we will be NAKing forever.
772 *
773 * If we get XferNotReady before gadget driver
774 * has a chance to queue a request, we will ACK
775 * the IRQ but won't be able to receive the data
776 * until the next request is queued. The following
777 * code is handling exactly that.
778 */
779 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
780 int ret;
781 int start_trans;
782
783 start_trans = 1;
784 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
785 dep->flags & DWC3_EP_BUSY)
786 start_trans = 0;
787
788 ret = __dwc3_gadget_kick_transfer(dep, 0, start_trans);
789 if (ret && ret != -EBUSY) {
790 struct dwc3 *dwc = dep->dwc;
791
792 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
793 dep->name);
794 }
795 };
796
797 return 0;
798}
799
800static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
801 gfp_t gfp_flags)
802{
803 struct dwc3_request *req = to_dwc3_request(request);
804 struct dwc3_ep *dep = to_dwc3_ep(ep);
805 struct dwc3 *dwc = dep->dwc;
806
807 unsigned long flags;
808
809 int ret;
810
811 if (!dep->desc) {
812 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
813 request, ep->name);
814 return -ESHUTDOWN;
815 }
816
817 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
818 request, ep->name, request->length);
819
820 spin_lock_irqsave(&dwc->lock, flags);
821 ret = __dwc3_gadget_ep_queue(dep, req);
822 spin_unlock_irqrestore(&dwc->lock, flags);
823
824 return ret;
825}
826
827static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
828 struct usb_request *request)
829{
830 struct dwc3_request *req = to_dwc3_request(request);
831 struct dwc3_request *r = NULL;
832
833 struct dwc3_ep *dep = to_dwc3_ep(ep);
834 struct dwc3 *dwc = dep->dwc;
835
836 unsigned long flags;
837 int ret = 0;
838
839 spin_lock_irqsave(&dwc->lock, flags);
840
841 list_for_each_entry(r, &dep->request_list, list) {
842 if (r == req)
843 break;
844 }
845
846 if (r != req) {
847 list_for_each_entry(r, &dep->req_queued, list) {
848 if (r == req)
849 break;
850 }
851 if (r == req) {
852 /* wait until it is processed */
853 dwc3_stop_active_transfer(dwc, dep->number);
854 goto out0;
855 }
856 dev_err(dwc->dev, "request %p was not queued to %s\n",
857 request, ep->name);
858 ret = -EINVAL;
859 goto out0;
860 }
861
862 /* giveback the request */
863 dwc3_gadget_giveback(dep, req, -ECONNRESET);
864
865out0:
866 spin_unlock_irqrestore(&dwc->lock, flags);
867
868 return ret;
869}
870
871int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
872{
873 struct dwc3_gadget_ep_cmd_params params;
874 struct dwc3 *dwc = dep->dwc;
875 int ret;
876
877 memset(&params, 0x00, sizeof(params));
878
879 if (value) {
0b7836a9
FB		 880 if (dep->number == 0 || dep->number == 1) {
881 /*
882 * Whenever EP0 is stalled, we will restart
883 * the state machine, thus moving back to
884 * Setup Phase
885 */
886 dwc->ep0state = EP0_SETUP_PHASE;
887 }
72246da4
FB		 888
889 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
890 DWC3_DEPCMD_SETSTALL, &params);
891 if (ret)
892 dev_err(dwc->dev, "failed to %s STALL on %s\n",
893 value ? "set" : "clear",
894 dep->name);
895 else
896 dep->flags |= DWC3_EP_STALL;
897 } else {
5275455a
PZ		 898 if (dep->flags & DWC3_EP_WEDGE)
899 return 0;
900
72246da4
FB		 901 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
902 DWC3_DEPCMD_CLEARSTALL, &params);
903 if (ret)
904 dev_err(dwc->dev, "failed to %s STALL on %s\n",
905 value ? "set" : "clear",
906 dep->name);
907 else
908 dep->flags &= ~DWC3_EP_STALL;
909 }
5275455a 910
72246da4
FB		 911 return ret;
912}
913
914static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
915{
916 struct dwc3_ep *dep = to_dwc3_ep(ep);
917 struct dwc3 *dwc = dep->dwc;
918
919 unsigned long flags;
920
921 int ret;
922
923 spin_lock_irqsave(&dwc->lock, flags);
924
925 if (usb_endpoint_xfer_isoc(dep->desc)) {
926 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
927 ret = -EINVAL;
928 goto out;
929 }
930
931 ret = __dwc3_gadget_ep_set_halt(dep, value);
932out:
933 spin_unlock_irqrestore(&dwc->lock, flags);
934
935 return ret;
936}
937
938static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
939{
940 struct dwc3_ep *dep = to_dwc3_ep(ep);
941
942 dep->flags |= DWC3_EP_WEDGE;
943
5275455a 944 return dwc3_gadget_ep_set_halt(ep, 1);
72246da4
FB		 945}
946
947/* -------------------------------------------------------------------------- */
948
949static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
950 .bLength = USB_DT_ENDPOINT_SIZE,
951 .bDescriptorType = USB_DT_ENDPOINT,
952 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
953};
954
955static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
956 .enable = dwc3_gadget_ep0_enable,
957 .disable = dwc3_gadget_ep0_disable,
958 .alloc_request = dwc3_gadget_ep_alloc_request,
959 .free_request = dwc3_gadget_ep_free_request,
960 .queue = dwc3_gadget_ep0_queue,
961 .dequeue = dwc3_gadget_ep_dequeue,
962 .set_halt = dwc3_gadget_ep_set_halt,
963 .set_wedge = dwc3_gadget_ep_set_wedge,
964};
965
966static const struct usb_ep_ops dwc3_gadget_ep_ops = {
967 .enable = dwc3_gadget_ep_enable,
968 .disable = dwc3_gadget_ep_disable,
969 .alloc_request = dwc3_gadget_ep_alloc_request,
970 .free_request = dwc3_gadget_ep_free_request,
971 .queue = dwc3_gadget_ep_queue,
972 .dequeue = dwc3_gadget_ep_dequeue,
973 .set_halt = dwc3_gadget_ep_set_halt,
974 .set_wedge = dwc3_gadget_ep_set_wedge,
975};
976
977/* -------------------------------------------------------------------------- */
978
979static int dwc3_gadget_get_frame(struct usb_gadget *g)
980{
981 struct dwc3 *dwc = gadget_to_dwc(g);
982 u32 reg;
983
984 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
985 return DWC3_DSTS_SOFFN(reg);
986}
987
988static int dwc3_gadget_wakeup(struct usb_gadget *g)
989{
990 struct dwc3 *dwc = gadget_to_dwc(g);
991
992 unsigned long timeout;
993 unsigned long flags;
994
995 u32 reg;
996
997 int ret = 0;
998
999 u8 link_state;
1000 u8 speed;
1001
1002 spin_lock_irqsave(&dwc->lock, flags);
1003
1004 /*
1005 * According to the Databook Remote wakeup request should
1006 * be issued only when the device is in early suspend state.
1007 *
1008 * We can check that via USB Link State bits in DSTS register.
1009 */
1010 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1011
1012 speed = reg & DWC3_DSTS_CONNECTSPD;
1013 if (speed == DWC3_DSTS_SUPERSPEED) {
1014 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1015 ret = -EINVAL;
1016 goto out;
1017 }
1018
1019 link_state = DWC3_DSTS_USBLNKST(reg);
1020
1021 switch (link_state) {
1022 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1023 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1024 break;
1025 default:
1026 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1027 link_state);
1028 ret = -EINVAL;
1029 goto out;
1030 }
1031
1032 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1033
1034 /*
1035 * Switch link state to Recovery. In HS/FS/LS this means
1036 * RemoteWakeup Request
1037 */
1038 reg |= DWC3_DCTL_ULSTCHNG_RECOVERY;
1039 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1040
1041 /* wait for at least 2000us */
1042 usleep_range(2000, 2500);
1043
1044 /* write zeroes to Link Change Request */
1045 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1046 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1047
1048 /* pool until Link State change to ON */
1049 timeout = jiffies + msecs_to_jiffies(100);
1050
1051 while (!(time_after(jiffies, timeout))) {
1052 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1053
1054 /* in HS, means ON */
1055 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1056 break;
1057 }
1058
1059 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1060 dev_err(dwc->dev, "failed to send remote wakeup\n");
1061 ret = -EINVAL;
1062 }
1063
1064out:
1065 spin_unlock_irqrestore(&dwc->lock, flags);
1066
1067 return ret;
1068}
1069
1070static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1071 int is_selfpowered)
1072{
1073 struct dwc3 *dwc = gadget_to_dwc(g);
1074
1075 dwc->is_selfpowered = !!is_selfpowered;
1076
1077 return 0;
1078}
1079
1080static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1081{
1082 u32 reg;
61d58242 1083 u32 timeout = 500;
72246da4
FB		 1084
1085 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1086 if (is_on)
1087 reg |= DWC3_DCTL_RUN_STOP;
1088 else
1089 reg &= ~DWC3_DCTL_RUN_STOP;
1090
1091 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1092
1093 do {
1094 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1095 if (is_on) {
1096 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1097 break;
1098 } else {
1099 if (reg & DWC3_DSTS_DEVCTRLHLT)
1100 break;
1101 }
72246da4
FB		 1102 timeout--;
1103 if (!timeout)
1104 break;
61d58242 1105 udelay(1);
72246da4
FB		 1106 } while (1);
1107
1108 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1109 dwc->gadget_driver
1110 ? dwc->gadget_driver->function : "no-function",
1111 is_on ? "connect" : "disconnect");
1112}
1113
1114static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1115{
1116 struct dwc3 *dwc = gadget_to_dwc(g);
1117 unsigned long flags;
1118
1119 is_on = !!is_on;
1120
1121 spin_lock_irqsave(&dwc->lock, flags);
1122 dwc3_gadget_run_stop(dwc, is_on);
1123 spin_unlock_irqrestore(&dwc->lock, flags);
1124
1125 return 0;
1126}
1127
1128static int dwc3_gadget_start(struct usb_gadget *g,
1129 struct usb_gadget_driver *driver)
1130{
1131 struct dwc3 *dwc = gadget_to_dwc(g);
1132 struct dwc3_ep *dep;
1133 unsigned long flags;
1134 int ret = 0;
1135 u32 reg;
1136
1137 spin_lock_irqsave(&dwc->lock, flags);
1138
1139 if (dwc->gadget_driver) {
1140 dev_err(dwc->dev, "%s is already bound to %s\n",
1141 dwc->gadget.name,
1142 dwc->gadget_driver->driver.name);
1143 ret = -EBUSY;
1144 goto err0;
1145 }
1146
1147 dwc->gadget_driver = driver;
1148 dwc->gadget.dev.driver = &driver->driver;
1149
1150 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1151
771f184e
FB		 1152 reg &= ~DWC3_GCTL_SCALEDOWN(3);
1153 reg &= ~DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG);
72246da4 1154 reg &= ~DWC3_GCTL_DISSCRAMBLE;
771f184e 1155 reg |= DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_DEVICE);
72246da4
FB		 1156
1157 /*
1158 * WORKAROUND: DWC3 revisions <1.90a have a bug
1159 * when The device fails to connect at SuperSpeed
1160 * and falls back to high-speed mode which causes
1161 * the device to enter in a Connect/Disconnect loop
1162 */
1163 if (dwc->revision < DWC3_REVISION_190A)
1164 reg |= DWC3_GCTL_U2RSTECN;
1165
1166 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1167
1168 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1169 reg &= ~(DWC3_DCFG_SPEED_MASK);
1170 reg |= DWC3_DCFG_SUPERSPEED;
1171 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1172
b23c8439
PZ		 1173 dwc->start_config_issued = false;
1174
72246da4
FB		 1175 /* Start with SuperSpeed Default */
1176 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1177
1178 dep = dwc->eps[0];
1179 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1180 if (ret) {
1181 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1182 goto err0;
1183 }
1184
1185 dep = dwc->eps[1];
1186 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1187 if (ret) {
1188 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1189 goto err1;
1190 }
1191
1192 /* begin to receive SETUP packets */
c7fcdeb2 1193 dwc->ep0state = EP0_SETUP_PHASE;
72246da4
FB		 1194 dwc3_ep0_out_start(dwc);
1195
1196 spin_unlock_irqrestore(&dwc->lock, flags);
1197
1198 return 0;
1199
1200err1:
1201 __dwc3_gadget_ep_disable(dwc->eps[0]);
1202
1203err0:
1204 spin_unlock_irqrestore(&dwc->lock, flags);
1205
1206 return ret;
1207}
1208
1209static int dwc3_gadget_stop(struct usb_gadget *g,
1210 struct usb_gadget_driver *driver)
1211{
1212 struct dwc3 *dwc = gadget_to_dwc(g);
1213 unsigned long flags;
1214
1215 spin_lock_irqsave(&dwc->lock, flags);
1216
1217 __dwc3_gadget_ep_disable(dwc->eps[0]);
1218 __dwc3_gadget_ep_disable(dwc->eps[1]);
1219
1220 dwc->gadget_driver = NULL;
1221 dwc->gadget.dev.driver = NULL;
1222
1223 spin_unlock_irqrestore(&dwc->lock, flags);
1224
1225 return 0;
1226}
1227static const struct usb_gadget_ops dwc3_gadget_ops = {
1228 .get_frame = dwc3_gadget_get_frame,
1229 .wakeup = dwc3_gadget_wakeup,
1230 .set_selfpowered = dwc3_gadget_set_selfpowered,
1231 .pullup = dwc3_gadget_pullup,
1232 .udc_start = dwc3_gadget_start,
1233 .udc_stop = dwc3_gadget_stop,
1234};
1235
1236/* -------------------------------------------------------------------------- */
1237
1238static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1239{
1240 struct dwc3_ep *dep;
1241 u8 epnum;
1242
1243 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1244
1245 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1246 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1247 if (!dep) {
1248 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1249 epnum);
1250 return -ENOMEM;
1251 }
1252
1253 dep->dwc = dwc;
1254 dep->number = epnum;
1255 dwc->eps[epnum] = dep;
1256
1257 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1258 (epnum & 1) ? "in" : "out");
1259 dep->endpoint.name = dep->name;
1260 dep->direction = (epnum & 1);
1261
1262 if (epnum == 0 || epnum == 1) {
1263 dep->endpoint.maxpacket = 512;
1264 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1265 if (!epnum)
1266 dwc->gadget.ep0 = &dep->endpoint;
1267 } else {
1268 int ret;
1269
1270 dep->endpoint.maxpacket = 1024;
1271 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1272 list_add_tail(&dep->endpoint.ep_list,
1273 &dwc->gadget.ep_list);
1274
1275 ret = dwc3_alloc_trb_pool(dep);
1276 if (ret) {
1277 dev_err(dwc->dev, "%s: failed to allocate TRB pool\n", dep->name);
1278 return ret;
1279 }
1280 }
1281 INIT_LIST_HEAD(&dep->request_list);
1282 INIT_LIST_HEAD(&dep->req_queued);
1283 }
1284
1285 return 0;
1286}
1287
1288static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1289{
1290 struct dwc3_ep *dep;
1291 u8 epnum;
1292
1293 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1294 dep = dwc->eps[epnum];
1295 dwc3_free_trb_pool(dep);
1296
1297 if (epnum != 0 && epnum != 1)
1298 list_del(&dep->endpoint.ep_list);
1299
1300 kfree(dep);
1301 }
1302}
1303
1304static void dwc3_gadget_release(struct device *dev)
1305{
1306 dev_dbg(dev, "%s\n", __func__);
1307}
1308
1309/* -------------------------------------------------------------------------- */
1310static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1311 const struct dwc3_event_depevt *event, int status)
1312{
1313 struct dwc3_request *req;
1314 struct dwc3_trb trb;
1315 unsigned int count;
1316 unsigned int s_pkt = 0;
1317
1318 do {
1319 req = next_request(&dep->req_queued);
1320 if (!req)
1321 break;
1322
1323 dwc3_trb_to_nat(req->trb, &trb);
1324
0d2f4758
SAS		 1325 if (trb.hwo && status != -ESHUTDOWN)
1326 /*
1327 * We continue despite the error. There is not much we
1328 * can do. If we don't clean in up we loop for ever. If
1329 * we skip the TRB than it gets overwritten reused after
1330 * a while since we use them in a ring buffer. a BUG()
1331 * would help. Lets hope that if this occures, someone
1332 * fixes the root cause instead of looking away :)
1333 */
72246da4
FB		 1334 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1335 dep->name, req->trb);
72246da4
FB		 1336 count = trb.length;
1337
1338 if (dep->direction) {
1339 if (count) {
1340 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1341 dep->name);
1342 status = -ECONNRESET;
1343 }
1344 } else {
1345 if (count && (event->status & DEPEVT_STATUS_SHORT))
1346 s_pkt = 1;
1347 }
1348
1349 /*
1350 * We assume here we will always receive the entire data block
1351 * which we should receive. Meaning, if we program RX to
1352 * receive 4K but we receive only 2K, we assume that's all we
1353 * should receive and we simply bounce the request back to the
1354 * gadget driver for further processing.
1355 */
1356 req->request.actual += req->request.length - count;
1357 dwc3_gadget_giveback(dep, req, status);
1358 if (s_pkt)
1359 break;
1360 if ((event->status & DEPEVT_STATUS_LST) && trb.lst)
1361 break;
1362 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc)
1363 break;
1364 } while (1);
1365
1366 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc)
1367 return 0;
1368 return 1;
1369}
1370
1371static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1372 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1373 int start_new)
1374{
1375 unsigned status = 0;
1376 int clean_busy;
1377
1378 if (event->status & DEPEVT_STATUS_BUSERR)
1379 status = -ECONNRESET;
1380
1381 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
a1ae9be5 1382 if (clean_busy) {
72246da4 1383 dep->flags &= ~DWC3_EP_BUSY;
a1ae9be5
SAS		 1384 dep->res_trans_idx = 0;
1385 }
72246da4
FB		 1386}
1387
1388static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1389 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1390{
1391 u32 uf;
1392
1393 if (list_empty(&dep->request_list)) {
1394 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1395 dep->name);
1396 return;
1397 }
1398
1399 if (event->parameters) {
1400 u32 mask;
1401
1402 mask = ~(dep->interval - 1);
1403 uf = event->parameters & mask;
1404 /* 4 micro frames in the future */
1405 uf += dep->interval * 4;
1406 } else {
1407 uf = 0;
1408 }
1409
1410 __dwc3_gadget_kick_transfer(dep, uf, 1);
1411}
1412
1413static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep,
1414 const struct dwc3_event_depevt *event)
1415{
1416 struct dwc3 *dwc = dep->dwc;
1417 struct dwc3_event_depevt mod_ev = *event;
1418
1419 /*
1420 * We were asked to remove one requests. It is possible that this
1421 * request and a few other were started together and have the same
1422 * transfer index. Since we stopped the complete endpoint we don't
1423 * know how many requests were already completed (and not yet)
1424 * reported and how could be done (later). We purge them all until
1425 * the end of the list.
1426 */
1427 mod_ev.status = DEPEVT_STATUS_LST;
1428 dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN);
1429 dep->flags &= ~DWC3_EP_BUSY;
1430 /* pending requets are ignored and are queued on XferNotReady */
72246da4
FB		 1431}
1432
1433static void dwc3_ep_cmd_compl(struct dwc3_ep *dep,
1434 const struct dwc3_event_depevt *event)
1435{
1436 u32 param = event->parameters;
1437 u32 cmd_type = (param >> 8) & ((1 << 5) - 1);
1438
1439 switch (cmd_type) {
1440 case DWC3_DEPCMD_ENDTRANSFER:
1441 dwc3_process_ep_cmd_complete(dep, event);
1442 break;
1443 case DWC3_DEPCMD_STARTTRANSFER:
1444 dep->res_trans_idx = param & 0x7f;
1445 break;
1446 default:
1447 printk(KERN_ERR "%s() unknown /unexpected type: %d\n",
1448 __func__, cmd_type);
1449 break;
1450 };
1451}
1452
1453static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1454 const struct dwc3_event_depevt *event)
1455{
1456 struct dwc3_ep *dep;
1457 u8 epnum = event->endpoint_number;
1458
1459 dep = dwc->eps[epnum];
1460
1461 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1462 dwc3_ep_event_string(event->endpoint_event));
1463
1464 if (epnum == 0 || epnum == 1) {
1465 dwc3_ep0_interrupt(dwc, event);
1466 return;
1467 }
1468
1469 switch (event->endpoint_event) {
1470 case DWC3_DEPEVT_XFERCOMPLETE:
1471 if (usb_endpoint_xfer_isoc(dep->desc)) {
1472 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1473 dep->name);
1474 return;
1475 }
1476
1477 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1478 break;
1479 case DWC3_DEPEVT_XFERINPROGRESS:
1480 if (!usb_endpoint_xfer_isoc(dep->desc)) {
1481 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1482 dep->name);
1483 return;
1484 }
1485
1486 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1487 break;
1488 case DWC3_DEPEVT_XFERNOTREADY:
1489 if (usb_endpoint_xfer_isoc(dep->desc)) {
1490 dwc3_gadget_start_isoc(dwc, dep, event);
1491 } else {
1492 int ret;
1493
1494 dev_vdbg(dwc->dev, "%s: reason %s\n",
1495 dep->name, event->status
1496 ? "Transfer Active"
1497 : "Transfer Not Active");
1498
1499 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1500 if (!ret || ret == -EBUSY)
1501 return;
1502
1503 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1504 dep->name);
1505 }
1506
1507 break;
1508 case DWC3_DEPEVT_RXTXFIFOEVT:
1509 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1510 break;
1511 case DWC3_DEPEVT_STREAMEVT:
1512 dev_dbg(dwc->dev, "%s Stream Event\n", dep->name);
1513 break;
1514 case DWC3_DEPEVT_EPCMDCMPLT:
1515 dwc3_ep_cmd_compl(dep, event);
1516 break;
1517 }
1518}
1519
1520static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1521{
1522 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1523 spin_unlock(&dwc->lock);
1524 dwc->gadget_driver->disconnect(&dwc->gadget);
1525 spin_lock(&dwc->lock);
1526 }
1527}
1528
1529static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
1530{
1531 struct dwc3_ep *dep;
1532 struct dwc3_gadget_ep_cmd_params params;
1533 u32 cmd;
1534 int ret;
1535
1536 dep = dwc->eps[epnum];
1537
624407f9 1538 WARN_ON(!dep->res_trans_idx);
72246da4
FB		 1539 if (dep->res_trans_idx) {
1540 cmd = DWC3_DEPCMD_ENDTRANSFER;
1541 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
1542 cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx);
1543 memset(&params, 0, sizeof(params));
1544 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1545 WARN_ON_ONCE(ret);
a1ae9be5 1546 dep->res_trans_idx = 0;
72246da4
FB		 1547 }
1548}
1549
1550static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1551{
1552 u32 epnum;
1553
1554 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1555 struct dwc3_ep *dep;
1556
1557 dep = dwc->eps[epnum];
1558 if (!(dep->flags & DWC3_EP_ENABLED))
1559 continue;
1560
624407f9 1561 dwc3_remove_requests(dwc, dep);
72246da4
FB		 1562 }
1563}
1564
1565static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
1566{
1567 u32 epnum;
1568
1569 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1570 struct dwc3_ep *dep;
1571 struct dwc3_gadget_ep_cmd_params params;
1572 int ret;
1573
1574 dep = dwc->eps[epnum];
1575
1576 if (!(dep->flags & DWC3_EP_STALL))
1577 continue;
1578
1579 dep->flags &= ~DWC3_EP_STALL;
1580
1581 memset(&params, 0, sizeof(params));
1582 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1583 DWC3_DEPCMD_CLEARSTALL, &params);
1584 WARN_ON_ONCE(ret);
1585 }
1586}
1587
1588static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
1589{
1590 dev_vdbg(dwc->dev, "%s\n", __func__);
1591#if 0
1592 XXX
1593 U1/U2 is powersave optimization. Skip it for now. Anyway we need to
1594 enable it before we can disable it.
1595
1596 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1597 reg &= ~DWC3_DCTL_INITU1ENA;
1598 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1599
1600 reg &= ~DWC3_DCTL_INITU2ENA;
1601 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1602#endif
1603
1604 dwc3_stop_active_transfers(dwc);
1605 dwc3_disconnect_gadget(dwc);
b23c8439 1606 dwc->start_config_issued = false;
72246da4
FB		 1607
1608 dwc->gadget.speed = USB_SPEED_UNKNOWN;
1609}
1610
1611static void dwc3_gadget_usb3_phy_power(struct dwc3 *dwc, int on)
1612{
1613 u32 reg;
1614
1615 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1616
1617 if (on)
1618 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
1619 else
1620 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1621
1622 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1623}
1624
1625static void dwc3_gadget_usb2_phy_power(struct dwc3 *dwc, int on)
1626{
1627 u32 reg;
1628
1629 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1630
1631 if (on)
1632 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1633 else
1634 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1635
1636 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1637}
1638
1639static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
1640{
1641 u32 reg;
1642
1643 dev_vdbg(dwc->dev, "%s\n", __func__);
1644
1645 /* Enable PHYs */
1646 dwc3_gadget_usb2_phy_power(dwc, true);
1647 dwc3_gadget_usb3_phy_power(dwc, true);
1648
1649 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
1650 dwc3_disconnect_gadget(dwc);
1651
1652 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1653 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
1654 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1655
1656 dwc3_stop_active_transfers(dwc);
1657 dwc3_clear_stall_all_ep(dwc);
b23c8439 1658 dwc->start_config_issued = false;
72246da4
FB		 1659
1660 /* Reset device address to zero */
1661 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1662 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
1663 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
72246da4
FB		 1664}
1665
1666static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
1667{
1668 u32 reg;
1669 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
1670
1671 /*
1672 * We change the clock only at SS but I dunno why I would want to do
1673 * this. Maybe it becomes part of the power saving plan.
1674 */
1675
1676 if (speed != DWC3_DSTS_SUPERSPEED)
1677 return;
1678
1679 /*
1680 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
1681 * each time on Connect Done.
1682 */
1683 if (!usb30_clock)
1684 return;
1685
1686 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1687 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
1688 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1689}
1690
1691static void dwc3_gadget_disable_phy(struct dwc3 *dwc, u8 speed)
1692{
1693 switch (speed) {
1694 case USB_SPEED_SUPER:
1695 dwc3_gadget_usb2_phy_power(dwc, false);
1696 break;
1697 case USB_SPEED_HIGH:
1698 case USB_SPEED_FULL:
1699 case USB_SPEED_LOW:
1700 dwc3_gadget_usb3_phy_power(dwc, false);
1701 break;
1702 }
1703}
1704
1705static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
1706{
1707 struct dwc3_gadget_ep_cmd_params params;
1708 struct dwc3_ep *dep;
1709 int ret;
1710 u32 reg;
1711 u8 speed;
1712
1713 dev_vdbg(dwc->dev, "%s\n", __func__);
1714
1715 memset(&params, 0x00, sizeof(params));
1716
72246da4
FB		 1717 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1718 speed = reg & DWC3_DSTS_CONNECTSPD;
1719 dwc->speed = speed;
1720
1721 dwc3_update_ram_clk_sel(dwc, speed);
1722
1723 switch (speed) {
1724 case DWC3_DCFG_SUPERSPEED:
1725 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1726 dwc->gadget.ep0->maxpacket = 512;
1727 dwc->gadget.speed = USB_SPEED_SUPER;
1728 break;
1729 case DWC3_DCFG_HIGHSPEED:
1730 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
1731 dwc->gadget.ep0->maxpacket = 64;
1732 dwc->gadget.speed = USB_SPEED_HIGH;
1733 break;
1734 case DWC3_DCFG_FULLSPEED2:
1735 case DWC3_DCFG_FULLSPEED1:
1736 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
1737 dwc->gadget.ep0->maxpacket = 64;
1738 dwc->gadget.speed = USB_SPEED_FULL;
1739 break;
1740 case DWC3_DCFG_LOWSPEED:
1741 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
1742 dwc->gadget.ep0->maxpacket = 8;
1743 dwc->gadget.speed = USB_SPEED_LOW;
1744 break;
1745 }
1746
1747 /* Disable unneded PHY */
1748 dwc3_gadget_disable_phy(dwc, dwc->gadget.speed);
1749
1750 dep = dwc->eps[0];
1751 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1752 if (ret) {
1753 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1754 return;
1755 }
1756
1757 dep = dwc->eps[1];
1758 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1759 if (ret) {
1760 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1761 return;
1762 }
1763
1764 /*
1765 * Configure PHY via GUSB3PIPECTLn if required.
1766 *
1767 * Update GTXFIFOSIZn
1768 *
1769 * In both cases reset values should be sufficient.
1770 */
1771}
1772
1773static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
1774{
1775 dev_vdbg(dwc->dev, "%s\n", __func__);
1776
1777 /*
1778 * TODO take core out of low power mode when that's
1779 * implemented.
1780 */
1781
1782 dwc->gadget_driver->resume(&dwc->gadget);
1783}
1784
1785static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
1786 unsigned int evtinfo)
1787{
72246da4
FB		 1788 /* The fith bit says SuperSpeed yes or no. */
1789 dwc->link_state = evtinfo & DWC3_LINK_STATE_MASK;
019ac832
FB		 1790
1791 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
72246da4
FB		 1792}
1793
1794static void dwc3_gadget_interrupt(struct dwc3 *dwc,
1795 const struct dwc3_event_devt *event)
1796{
1797 switch (event->type) {
1798 case DWC3_DEVICE_EVENT_DISCONNECT:
1799 dwc3_gadget_disconnect_interrupt(dwc);
1800 break;
1801 case DWC3_DEVICE_EVENT_RESET:
1802 dwc3_gadget_reset_interrupt(dwc);
1803 break;
1804 case DWC3_DEVICE_EVENT_CONNECT_DONE:
1805 dwc3_gadget_conndone_interrupt(dwc);
1806 break;
1807 case DWC3_DEVICE_EVENT_WAKEUP:
1808 dwc3_gadget_wakeup_interrupt(dwc);
1809 break;
1810 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
1811 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
1812 break;
1813 case DWC3_DEVICE_EVENT_EOPF:
1814 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
1815 break;
1816 case DWC3_DEVICE_EVENT_SOF:
1817 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
1818 break;
1819 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
1820 dev_vdbg(dwc->dev, "Erratic Error\n");
1821 break;
1822 case DWC3_DEVICE_EVENT_CMD_CMPL:
1823 dev_vdbg(dwc->dev, "Command Complete\n");
1824 break;
1825 case DWC3_DEVICE_EVENT_OVERFLOW:
1826 dev_vdbg(dwc->dev, "Overflow\n");
1827 break;
1828 default:
1829 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
1830 }
1831}
1832
1833static void dwc3_process_event_entry(struct dwc3 *dwc,
1834 const union dwc3_event *event)
1835{
1836 /* Endpoint IRQ, handle it and return early */
1837 if (event->type.is_devspec == 0) {
1838 /* depevt */
1839 return dwc3_endpoint_interrupt(dwc, &event->depevt);
1840 }
1841
1842 switch (event->type.type) {
1843 case DWC3_EVENT_TYPE_DEV:
1844 dwc3_gadget_interrupt(dwc, &event->devt);
1845 break;
1846 /* REVISIT what to do with Carkit and I2C events ? */
1847 default:
1848 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
1849 }
1850}
1851
1852static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
1853{
1854 struct dwc3_event_buffer *evt;
1855 int left;
1856 u32 count;
1857
1858 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
1859 count &= DWC3_GEVNTCOUNT_MASK;
1860 if (!count)
1861 return IRQ_NONE;
1862
1863 evt = dwc->ev_buffs[buf];
1864 left = count;
1865
1866 while (left > 0) {
1867 union dwc3_event event;
1868
1869 memcpy(&event.raw, (evt->buf + evt->lpos), sizeof(event.raw));
1870 dwc3_process_event_entry(dwc, &event);
1871 /*
1872 * XXX we wrap around correctly to the next entry as almost all
1873 * entries are 4 bytes in size. There is one entry which has 12
1874 * bytes which is a regular entry followed by 8 bytes data. ATM
1875 * I don't know how things are organized if were get next to the
1876 * a boundary so I worry about that once we try to handle that.
1877 */
1878 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
1879 left -= 4;
1880
1881 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
1882 }
1883
1884 return IRQ_HANDLED;
1885}
1886
1887static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
1888{
1889 struct dwc3 *dwc = _dwc;
1890 int i;
1891 irqreturn_t ret = IRQ_NONE;
1892
1893 spin_lock(&dwc->lock);
1894
1895 for (i = 0; i < DWC3_EVENT_BUFFERS_NUM; i++) {
1896 irqreturn_t status;
1897
1898 status = dwc3_process_event_buf(dwc, i);
1899 if (status == IRQ_HANDLED)
1900 ret = status;
1901 }
1902
1903 spin_unlock(&dwc->lock);
1904
1905 return ret;
1906}
1907
1908/**
1909 * dwc3_gadget_init - Initializes gadget related registers
1910 * @dwc: Pointer to out controller context structure
1911 *
1912 * Returns 0 on success otherwise negative errno.
1913 */
1914int __devinit dwc3_gadget_init(struct dwc3 *dwc)
1915{
1916 u32 reg;
1917 int ret;
1918 int irq;
1919
1920 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
1921 &dwc->ctrl_req_addr, GFP_KERNEL);
1922 if (!dwc->ctrl_req) {
1923 dev_err(dwc->dev, "failed to allocate ctrl request\n");
1924 ret = -ENOMEM;
1925 goto err0;
1926 }
1927
1928 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
1929 &dwc->ep0_trb_addr, GFP_KERNEL);
1930 if (!dwc->ep0_trb) {
1931 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
1932 ret = -ENOMEM;
1933 goto err1;
1934 }
1935
1936 dwc->setup_buf = dma_alloc_coherent(dwc->dev,
1937 sizeof(*dwc->setup_buf) * 2,
1938 &dwc->setup_buf_addr, GFP_KERNEL);
1939 if (!dwc->setup_buf) {
1940 dev_err(dwc->dev, "failed to allocate setup buffer\n");
1941 ret = -ENOMEM;
1942 goto err2;
1943 }
1944
5812b1c2
FB		 1945 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
1946 512, &dwc->ep0_bounce_addr, GFP_KERNEL);
1947 if (!dwc->ep0_bounce) {
1948 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
1949 ret = -ENOMEM;
1950 goto err3;
1951 }
1952
72246da4
FB		 1953 dev_set_name(&dwc->gadget.dev, "gadget");
1954
1955 dwc->gadget.ops = &dwc3_gadget_ops;
1956 dwc->gadget.is_dualspeed = true;
1957 dwc->gadget.speed = USB_SPEED_UNKNOWN;
1958 dwc->gadget.dev.parent = dwc->dev;
1959
1960 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
1961
1962 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms;
1963 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask;
1964 dwc->gadget.dev.release = dwc3_gadget_release;
1965 dwc->gadget.name = "dwc3-gadget";
1966
1967 /*
1968 * REVISIT: Here we should clear all pending IRQs to be
1969 * sure we're starting from a well known location.
1970 */
1971
1972 ret = dwc3_gadget_init_endpoints(dwc);
1973 if (ret)
5812b1c2 1974 goto err4;
72246da4
FB		 1975
1976 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1977
1978 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
1979 "dwc3", dwc);
1980 if (ret) {
1981 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1982 irq, ret);
5812b1c2 1983 goto err5;
72246da4
FB		 1984 }
1985
1986 /* Enable all but Start and End of Frame IRQs */
1987 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1988 DWC3_DEVTEN_EVNTOVERFLOWEN |
1989 DWC3_DEVTEN_CMDCMPLTEN |
1990 DWC3_DEVTEN_ERRTICERREN |
1991 DWC3_DEVTEN_WKUPEVTEN |
1992 DWC3_DEVTEN_ULSTCNGEN |
1993 DWC3_DEVTEN_CONNECTDONEEN |
1994 DWC3_DEVTEN_USBRSTEN |
1995 DWC3_DEVTEN_DISCONNEVTEN);
1996 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1997
1998 ret = device_register(&dwc->gadget.dev);
1999 if (ret) {
2000 dev_err(dwc->dev, "failed to register gadget device\n");
2001 put_device(&dwc->gadget.dev);
5812b1c2 2002 goto err6;
72246da4
FB		 2003 }
2004
2005 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2006 if (ret) {
2007 dev_err(dwc->dev, "failed to register udc\n");
5812b1c2 2008 goto err7;
72246da4
FB		 2009 }
2010
2011 return 0;
2012
5812b1c2 2013err7:
72246da4
FB		 2014 device_unregister(&dwc->gadget.dev);
2015
5812b1c2 2016err6:
72246da4
FB		 2017 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2018 free_irq(irq, dwc);
2019
5812b1c2 2020err5:
72246da4
FB		 2021 dwc3_gadget_free_endpoints(dwc);
2022
5812b1c2
FB		 2023err4:
2024 dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce,
2025 dwc->ep0_bounce_addr);
2026
72246da4
FB		 2027err3:
2028 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
2029 dwc->setup_buf, dwc->setup_buf_addr);
2030
2031err2:
2032 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2033 dwc->ep0_trb, dwc->ep0_trb_addr);
2034
2035err1:
2036 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2037 dwc->ctrl_req, dwc->ctrl_req_addr);
2038
2039err0:
2040 return ret;
2041}
2042
2043void dwc3_gadget_exit(struct dwc3 *dwc)
2044{
2045 int irq;
2046 int i;
2047
2048 usb_del_gadget_udc(&dwc->gadget);
2049 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2050
2051 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2052 free_irq(irq, dwc);
2053
2054 for (i = 0; i < ARRAY_SIZE(dwc->eps); i++)
2055 __dwc3_gadget_ep_disable(dwc->eps[i]);
2056
2057 dwc3_gadget_free_endpoints(dwc);
2058
5812b1c2
FB		 2059 dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce,
2060 dwc->ep0_bounce_addr);
2061
72246da4
FB		 2062 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
2063 dwc->setup_buf, dwc->setup_buf_addr);
2064
2065 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2066 dwc->ep0_trb, dwc->ep0_trb_addr);
2067
2068 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2069 dwc->ctrl_req, dwc->ctrl_req_addr);
2070
2071 device_unregister(&dwc->gadget.dev);
2072}
Linux kernel - Deliverables
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