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USB: xhci: Set route string for all devices.
[deliverable/linux.git] / drivers / usb / host / xhci-mem.c
CommitLineData
66d4eadd
SS		 1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#include <linux/usb.h>
0ebbab37 24#include <linux/pci.h>
527c6d7f 25#include <linux/dmapool.h>
66d4eadd
SS		 26
27#include "xhci.h"
28
0ebbab37
SS		 29/*
30 * Allocates a generic ring segment from the ring pool, sets the dma address,
31 * initializes the segment to zero, and sets the private next pointer to NULL.
32 *
33 * Section 4.11.1.1:
34 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
35 */
36static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci, gfp_t flags)
37{
38 struct xhci_segment *seg;
39 dma_addr_t dma;
40
41 seg = kzalloc(sizeof *seg, flags);
42 if (!seg)
43 return 0;
700e2052 44 xhci_dbg(xhci, "Allocating priv segment structure at %p\n", seg);
0ebbab37
SS		 45
46 seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
47 if (!seg->trbs) {
48 kfree(seg);
49 return 0;
50 }
700e2052
GKH		 51 xhci_dbg(xhci, "// Allocating segment at %p (virtual) 0x%llx (DMA)\n",
52 seg->trbs, (unsigned long long)dma);
0ebbab37
SS		 53
54 memset(seg->trbs, 0, SEGMENT_SIZE);
55 seg->dma = dma;
56 seg->next = NULL;
57
58 return seg;
59}
60
61static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
62{
63 if (!seg)
64 return;
65 if (seg->trbs) {
700e2052
GKH		 66 xhci_dbg(xhci, "Freeing DMA segment at %p (virtual) 0x%llx (DMA)\n",
67 seg->trbs, (unsigned long long)seg->dma);
0ebbab37
SS		 68 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
69 seg->trbs = NULL;
70 }
700e2052 71 xhci_dbg(xhci, "Freeing priv segment structure at %p\n", seg);
0ebbab37
SS		 72 kfree(seg);
73}
74
75/*
76 * Make the prev segment point to the next segment.
77 *
78 * Change the last TRB in the prev segment to be a Link TRB which points to the
79 * DMA address of the next segment. The caller needs to set any Link TRB
80 * related flags, such as End TRB, Toggle Cycle, and no snoop.
81 */
82static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
83 struct xhci_segment *next, bool link_trbs)
84{
85 u32 val;
86
87 if (!prev || !next)
88 return;
89 prev->next = next;
90 if (link_trbs) {
8e595a5d 91 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr = next->dma;
0ebbab37
SS		 92
93 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
94 val = prev->trbs[TRBS_PER_SEGMENT-1].link.control;
95 val &= ~TRB_TYPE_BITMASK;
96 val |= TRB_TYPE(TRB_LINK);
b0567b3f
SS		 97 /* Always set the chain bit with 0.95 hardware */
98 if (xhci_link_trb_quirk(xhci))
99 val |= TRB_CHAIN;
0ebbab37
SS		 100 prev->trbs[TRBS_PER_SEGMENT-1].link.control = val;
101 }
700e2052
GKH		 102 xhci_dbg(xhci, "Linking segment 0x%llx to segment 0x%llx (DMA)\n",
103 (unsigned long long)prev->dma,
104 (unsigned long long)next->dma);
0ebbab37
SS		 105}
106
107/* XXX: Do we need the hcd structure in all these functions? */
f94e0186 108void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
0ebbab37
SS		 109{
110 struct xhci_segment *seg;
111 struct xhci_segment *first_seg;
112
113 if (!ring || !ring->first_seg)
114 return;
115 first_seg = ring->first_seg;
116 seg = first_seg->next;
700e2052 117 xhci_dbg(xhci, "Freeing ring at %p\n", ring);
0ebbab37
SS		 118 while (seg != first_seg) {
119 struct xhci_segment *next = seg->next;
120 xhci_segment_free(xhci, seg);
121 seg = next;
122 }
123 xhci_segment_free(xhci, first_seg);
124 ring->first_seg = NULL;
125 kfree(ring);
126}
127
128/**
129 * Create a new ring with zero or more segments.
130 *
131 * Link each segment together into a ring.
132 * Set the end flag and the cycle toggle bit on the last segment.
133 * See section 4.9.1 and figures 15 and 16.
134 */
135static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
136 unsigned int num_segs, bool link_trbs, gfp_t flags)
137{
138 struct xhci_ring *ring;
139 struct xhci_segment *prev;
140
141 ring = kzalloc(sizeof *(ring), flags);
700e2052 142 xhci_dbg(xhci, "Allocating ring at %p\n", ring);
0ebbab37
SS		 143 if (!ring)
144 return 0;
145
d0e96f5a 146 INIT_LIST_HEAD(&ring->td_list);
0ebbab37
SS		 147 if (num_segs == 0)
148 return ring;
149
150 ring->first_seg = xhci_segment_alloc(xhci, flags);
151 if (!ring->first_seg)
152 goto fail;
153 num_segs--;
154
155 prev = ring->first_seg;
156 while (num_segs > 0) {
157 struct xhci_segment *next;
158
159 next = xhci_segment_alloc(xhci, flags);
160 if (!next)
161 goto fail;
162 xhci_link_segments(xhci, prev, next, link_trbs);
163
164 prev = next;
165 num_segs--;
166 }
167 xhci_link_segments(xhci, prev, ring->first_seg, link_trbs);
168
169 if (link_trbs) {
170 /* See section 4.9.2.1 and 6.4.4.1 */
171 prev->trbs[TRBS_PER_SEGMENT-1].link.control |= (LINK_TOGGLE);
172 xhci_dbg(xhci, "Wrote link toggle flag to"
700e2052
GKH		 173 " segment %p (virtual), 0x%llx (DMA)\n",
174 prev, (unsigned long long)prev->dma);
0ebbab37
SS		 175 }
176 /* The ring is empty, so the enqueue pointer == dequeue pointer */
177 ring->enqueue = ring->first_seg->trbs;
7f84eef0 178 ring->enq_seg = ring->first_seg;
0ebbab37 179 ring->dequeue = ring->enqueue;
7f84eef0 180 ring->deq_seg = ring->first_seg;
0ebbab37
SS		 181 /* The ring is initialized to 0. The producer must write 1 to the cycle
182 * bit to handover ownership of the TRB, so PCS = 1. The consumer must
183 * compare CCS to the cycle bit to check ownership, so CCS = 1.
184 */
185 ring->cycle_state = 1;
186
187 return ring;
188
189fail:
190 xhci_ring_free(xhci, ring);
191 return 0;
192}
193
d115b048
JY		 194#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
195
196struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
197 int type, gfp_t flags)
198{
199 struct xhci_container_ctx *ctx = kzalloc(sizeof(*ctx), flags);
200 if (!ctx)
201 return NULL;
202
203 BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
204 ctx->type = type;
205 ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
206 if (type == XHCI_CTX_TYPE_INPUT)
207 ctx->size += CTX_SIZE(xhci->hcc_params);
208
209 ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma);
210 memset(ctx->bytes, 0, ctx->size);
211 return ctx;
212}
213
214void xhci_free_container_ctx(struct xhci_hcd *xhci,
215 struct xhci_container_ctx *ctx)
216{
217 dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
218 kfree(ctx);
219}
220
221struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
222 struct xhci_container_ctx *ctx)
223{
224 BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
225 return (struct xhci_input_control_ctx *)ctx->bytes;
226}
227
228struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
229 struct xhci_container_ctx *ctx)
230{
231 if (ctx->type == XHCI_CTX_TYPE_DEVICE)
232 return (struct xhci_slot_ctx *)ctx->bytes;
233
234 return (struct xhci_slot_ctx *)
235 (ctx->bytes + CTX_SIZE(xhci->hcc_params));
236}
237
238struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
239 struct xhci_container_ctx *ctx,
240 unsigned int ep_index)
241{
242 /* increment ep index by offset of start of ep ctx array */
243 ep_index++;
244 if (ctx->type == XHCI_CTX_TYPE_INPUT)
245 ep_index++;
246
247 return (struct xhci_ep_ctx *)
248 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
249}
250
d0e96f5a 251/* All the xhci_tds in the ring's TD list should be freed at this point */
3ffbba95
SS		 252void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
253{
254 struct xhci_virt_device *dev;
255 int i;
256
257 /* Slot ID 0 is reserved */
258 if (slot_id == 0 || !xhci->devs[slot_id])
259 return;
260
261 dev = xhci->devs[slot_id];
8e595a5d 262 xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
3ffbba95
SS		 263 if (!dev)
264 return;
265
266 for (i = 0; i < 31; ++i)
63a0d9ab
SS		 267 if (dev->eps[i].ring)
268 xhci_ring_free(xhci, dev->eps[i].ring);
3ffbba95
SS		 269
270 if (dev->in_ctx)
d115b048 271 xhci_free_container_ctx(xhci, dev->in_ctx);
3ffbba95 272 if (dev->out_ctx)
d115b048
JY		 273 xhci_free_container_ctx(xhci, dev->out_ctx);
274
3ffbba95
SS		 275 kfree(xhci->devs[slot_id]);
276 xhci->devs[slot_id] = 0;
277}
278
279int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
280 struct usb_device *udev, gfp_t flags)
281{
3ffbba95 282 struct xhci_virt_device *dev;
63a0d9ab 283 int i;
3ffbba95
SS		 284
285 /* Slot ID 0 is reserved */
286 if (slot_id == 0 || xhci->devs[slot_id]) {
287 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
288 return 0;
289 }
290
291 xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
292 if (!xhci->devs[slot_id])
293 return 0;
294 dev = xhci->devs[slot_id];
295
d115b048
JY		 296 /* Allocate the (output) device context that will be used in the HC. */
297 dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
3ffbba95
SS		 298 if (!dev->out_ctx)
299 goto fail;
d115b048 300
700e2052 301 xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
d115b048 302 (unsigned long long)dev->out_ctx->dma);
3ffbba95
SS		 303
304 /* Allocate the (input) device context for address device command */
d115b048 305 dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
3ffbba95
SS		 306 if (!dev->in_ctx)
307 goto fail;
d115b048 308
700e2052 309 xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
d115b048 310 (unsigned long long)dev->in_ctx->dma);
3ffbba95 311
63a0d9ab
SS		 312 /* Initialize the cancellation list for each endpoint */
313 for (i = 0; i < 31; i++)
314 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
315
3ffbba95 316 /* Allocate endpoint 0 ring */
63a0d9ab
SS		 317 dev->eps[0].ring = xhci_ring_alloc(xhci, 1, true, flags);
318 if (!dev->eps[0].ring)
3ffbba95
SS		 319 goto fail;
320
f94e0186 321 init_completion(&dev->cmd_completion);
913a8a34 322 INIT_LIST_HEAD(&dev->cmd_list);
f94e0186 323
28c2d2ef 324 /* Point to output device context in dcbaa. */
d115b048 325 xhci->dcbaa->dev_context_ptrs[slot_id] = dev->out_ctx->dma;
700e2052 326 xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
3ffbba95 327 slot_id,
8e595a5d 328 &xhci->dcbaa->dev_context_ptrs[slot_id],
28c2d2ef 329 (unsigned long long) xhci->dcbaa->dev_context_ptrs[slot_id]);
3ffbba95
SS		 330
331 return 1;
332fail:
333 xhci_free_virt_device(xhci, slot_id);
334 return 0;
335}
336
337/* Setup an xHCI virtual device for a Set Address command */
338int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
339{
340 struct xhci_virt_device *dev;
341 struct xhci_ep_ctx *ep0_ctx;
342 struct usb_device *top_dev;
d115b048
JY		 343 struct xhci_slot_ctx *slot_ctx;
344 struct xhci_input_control_ctx *ctrl_ctx;
3ffbba95
SS		 345
346 dev = xhci->devs[udev->slot_id];
347 /* Slot ID 0 is reserved */
348 if (udev->slot_id == 0 || !dev) {
349 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
350 udev->slot_id);
351 return -EINVAL;
352 }
d115b048
JY		 353 ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
354 ctrl_ctx = xhci_get_input_control_ctx(xhci, dev->in_ctx);
355 slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
3ffbba95
SS		 356
357 /* 2) New slot context and endpoint 0 context are valid*/
d115b048 358 ctrl_ctx->add_flags = SLOT_FLAG | EP0_FLAG;
3ffbba95
SS		 359
360 /* 3) Only the control endpoint is valid - one endpoint context */
d115b048 361 slot_ctx->dev_info |= LAST_CTX(1);
3ffbba95 362
4a0cd967 363 slot_ctx->dev_info |= (u32) udev->route;
3ffbba95
SS		 364 switch (udev->speed) {
365 case USB_SPEED_SUPER:
d115b048 366 slot_ctx->dev_info |= (u32) SLOT_SPEED_SS;
3ffbba95
SS		 367 break;
368 case USB_SPEED_HIGH:
d115b048 369 slot_ctx->dev_info |= (u32) SLOT_SPEED_HS;
3ffbba95
SS		 370 break;
371 case USB_SPEED_FULL:
d115b048 372 slot_ctx->dev_info |= (u32) SLOT_SPEED_FS;
3ffbba95
SS		 373 break;
374 case USB_SPEED_LOW:
d115b048 375 slot_ctx->dev_info |= (u32) SLOT_SPEED_LS;
3ffbba95
SS		 376 break;
377 case USB_SPEED_VARIABLE:
378 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
379 return -EINVAL;
380 break;
381 default:
382 /* Speed was set earlier, this shouldn't happen. */
383 BUG();
384 }
385 /* Find the root hub port this device is under */
386 for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
387 top_dev = top_dev->parent)
388 /* Found device below root hub */;
d115b048 389 slot_ctx->dev_info2 |= (u32) ROOT_HUB_PORT(top_dev->portnum);
3ffbba95
SS		 390 xhci_dbg(xhci, "Set root hub portnum to %d\n", top_dev->portnum);
391
392 /* Is this a LS/FS device under a HS hub? */
393 /*
394 * FIXME: I don't think this is right, where does the TT info for the
395 * roothub or parent hub come from?
396 */
397 if ((udev->speed == USB_SPEED_LOW || udev->speed == USB_SPEED_FULL) &&
398 udev->tt) {
d115b048
JY		 399 slot_ctx->tt_info = udev->tt->hub->slot_id;
400 slot_ctx->tt_info |= udev->ttport << 8;
3ffbba95 401 }
700e2052 402 xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
3ffbba95
SS		 403 xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
404
405 /* Step 4 - ring already allocated */
406 /* Step 5 */
407 ep0_ctx->ep_info2 = EP_TYPE(CTRL_EP);
408 /*
3ffbba95
SS		 409 * XXX: Not sure about wireless USB devices.
410 */
47aded8a
SS		 411 switch (udev->speed) {
412 case USB_SPEED_SUPER:
3ffbba95 413 ep0_ctx->ep_info2 |= MAX_PACKET(512);
47aded8a
SS		 414 break;
415 case USB_SPEED_HIGH:
416 /* USB core guesses at a 64-byte max packet first for FS devices */
417 case USB_SPEED_FULL:
418 ep0_ctx->ep_info2 |= MAX_PACKET(64);
419 break;
420 case USB_SPEED_LOW:
3ffbba95 421 ep0_ctx->ep_info2 |= MAX_PACKET(8);
47aded8a
SS		 422 break;
423 case USB_SPEED_VARIABLE:
424 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
425 return -EINVAL;
426 break;
427 default:
428 /* New speed? */
429 BUG();
430 }
3ffbba95
SS		 431 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
432 ep0_ctx->ep_info2 |= MAX_BURST(0);
433 ep0_ctx->ep_info2 |= ERROR_COUNT(3);
434
8e595a5d 435 ep0_ctx->deq =
63a0d9ab
SS		 436 dev->eps[0].ring->first_seg->dma;
437 ep0_ctx->deq |= dev->eps[0].ring->cycle_state;
3ffbba95
SS		 438
439 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
440
441 return 0;
442}
443
f94e0186
SS		 444/* Return the polling or NAK interval.
445 *
446 * The polling interval is expressed in "microframes". If xHCI's Interval field
447 * is set to N, it will service the endpoint every 2^(Interval)*125us.
448 *
449 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
450 * is set to 0.
451 */
452static inline unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
453 struct usb_host_endpoint *ep)
454{
455 unsigned int interval = 0;
456
457 switch (udev->speed) {
458 case USB_SPEED_HIGH:
459 /* Max NAK rate */
460 if (usb_endpoint_xfer_control(&ep->desc) ||
461 usb_endpoint_xfer_bulk(&ep->desc))
462 interval = ep->desc.bInterval;
463 /* Fall through - SS and HS isoc/int have same decoding */
464 case USB_SPEED_SUPER:
465 if (usb_endpoint_xfer_int(&ep->desc) ||
466 usb_endpoint_xfer_isoc(&ep->desc)) {
467 if (ep->desc.bInterval == 0)
468 interval = 0;
469 else
470 interval = ep->desc.bInterval - 1;
471 if (interval > 15)
472 interval = 15;
473 if (interval != ep->desc.bInterval + 1)
474 dev_warn(&udev->dev, "ep %#x - rounding interval to %d microframes\n",
475 ep->desc.bEndpointAddress, 1 << interval);
476 }
477 break;
478 /* Convert bInterval (in 1-255 frames) to microframes and round down to
479 * nearest power of 2.
480 */
481 case USB_SPEED_FULL:
482 case USB_SPEED_LOW:
483 if (usb_endpoint_xfer_int(&ep->desc) ||
484 usb_endpoint_xfer_isoc(&ep->desc)) {
485 interval = fls(8*ep->desc.bInterval) - 1;
486 if (interval > 10)
487 interval = 10;
488 if (interval < 3)
489 interval = 3;
490 if ((1 << interval) != 8*ep->desc.bInterval)
491 dev_warn(&udev->dev, "ep %#x - rounding interval to %d microframes\n",
492 ep->desc.bEndpointAddress, 1 << interval);
493 }
494 break;
495 default:
496 BUG();
497 }
498 return EP_INTERVAL(interval);
499}
500
501static inline u32 xhci_get_endpoint_type(struct usb_device *udev,
502 struct usb_host_endpoint *ep)
503{
504 int in;
505 u32 type;
506
507 in = usb_endpoint_dir_in(&ep->desc);
508 if (usb_endpoint_xfer_control(&ep->desc)) {
509 type = EP_TYPE(CTRL_EP);
510 } else if (usb_endpoint_xfer_bulk(&ep->desc)) {
511 if (in)
512 type = EP_TYPE(BULK_IN_EP);
513 else
514 type = EP_TYPE(BULK_OUT_EP);
515 } else if (usb_endpoint_xfer_isoc(&ep->desc)) {
516 if (in)
517 type = EP_TYPE(ISOC_IN_EP);
518 else
519 type = EP_TYPE(ISOC_OUT_EP);
520 } else if (usb_endpoint_xfer_int(&ep->desc)) {
521 if (in)
522 type = EP_TYPE(INT_IN_EP);
523 else
524 type = EP_TYPE(INT_OUT_EP);
525 } else {
526 BUG();
527 }
528 return type;
529}
530
531int xhci_endpoint_init(struct xhci_hcd *xhci,
532 struct xhci_virt_device *virt_dev,
533 struct usb_device *udev,
f88ba78d
SS		 534 struct usb_host_endpoint *ep,
535 gfp_t mem_flags)
f94e0186
SS		 536{
537 unsigned int ep_index;
538 struct xhci_ep_ctx *ep_ctx;
539 struct xhci_ring *ep_ring;
540 unsigned int max_packet;
541 unsigned int max_burst;
542
543 ep_index = xhci_get_endpoint_index(&ep->desc);
d115b048 544 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
f94e0186
SS		 545
546 /* Set up the endpoint ring */
63a0d9ab
SS		 547 virt_dev->eps[ep_index].new_ring =
548 xhci_ring_alloc(xhci, 1, true, mem_flags);
549 if (!virt_dev->eps[ep_index].new_ring)
f94e0186 550 return -ENOMEM;
63a0d9ab 551 ep_ring = virt_dev->eps[ep_index].new_ring;
8e595a5d 552 ep_ctx->deq = ep_ring->first_seg->dma | ep_ring->cycle_state;
f94e0186
SS		 553
554 ep_ctx->ep_info = xhci_get_endpoint_interval(udev, ep);
555
556 /* FIXME dig Mult and streams info out of ep companion desc */
557
47692d17
SS		 558 /* Allow 3 retries for everything but isoc;
559 * error count = 0 means infinite retries.
560 */
f94e0186
SS		 561 if (!usb_endpoint_xfer_isoc(&ep->desc))
562 ep_ctx->ep_info2 = ERROR_COUNT(3);
563 else
47692d17 564 ep_ctx->ep_info2 = ERROR_COUNT(1);
f94e0186
SS		 565
566 ep_ctx->ep_info2 |= xhci_get_endpoint_type(udev, ep);
567
568 /* Set the max packet size and max burst */
569 switch (udev->speed) {
570 case USB_SPEED_SUPER:
571 max_packet = ep->desc.wMaxPacketSize;
572 ep_ctx->ep_info2 |= MAX_PACKET(max_packet);
b10de142 573 /* dig out max burst from ep companion desc */
b7d6d998
SS		 574 if (!ep->ss_ep_comp) {
575 xhci_warn(xhci, "WARN no SS endpoint companion descriptor.\n");
576 max_packet = 0;
577 } else {
578 max_packet = ep->ss_ep_comp->desc.bMaxBurst;
579 }
b10de142 580 ep_ctx->ep_info2 |= MAX_BURST(max_packet);
f94e0186
SS		 581 break;
582 case USB_SPEED_HIGH:
583 /* bits 11:12 specify the number of additional transaction
584 * opportunities per microframe (USB 2.0, section 9.6.6)
585 */
586 if (usb_endpoint_xfer_isoc(&ep->desc) ||
587 usb_endpoint_xfer_int(&ep->desc)) {
588 max_burst = (ep->desc.wMaxPacketSize & 0x1800) >> 11;
589 ep_ctx->ep_info2 |= MAX_BURST(max_burst);
590 }
591 /* Fall through */
592 case USB_SPEED_FULL:
593 case USB_SPEED_LOW:
594 max_packet = ep->desc.wMaxPacketSize & 0x3ff;
595 ep_ctx->ep_info2 |= MAX_PACKET(max_packet);
596 break;
597 default:
598 BUG();
599 }
600 /* FIXME Debug endpoint context */
601 return 0;
602}
603
604void xhci_endpoint_zero(struct xhci_hcd *xhci,
605 struct xhci_virt_device *virt_dev,
606 struct usb_host_endpoint *ep)
607{
608 unsigned int ep_index;
609 struct xhci_ep_ctx *ep_ctx;
610
611 ep_index = xhci_get_endpoint_index(&ep->desc);
d115b048 612 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
f94e0186
SS		 613
614 ep_ctx->ep_info = 0;
615 ep_ctx->ep_info2 = 0;
8e595a5d 616 ep_ctx->deq = 0;
f94e0186
SS		 617 ep_ctx->tx_info = 0;
618 /* Don't free the endpoint ring until the set interface or configuration
619 * request succeeds.
620 */
621}
622
f2217e8e
SS		 623/* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
624 * Useful when you want to change one particular aspect of the endpoint and then
625 * issue a configure endpoint command.
626 */
627void xhci_endpoint_copy(struct xhci_hcd *xhci,
913a8a34
SS		 628 struct xhci_container_ctx *in_ctx,
629 struct xhci_container_ctx *out_ctx,
630 unsigned int ep_index)
f2217e8e
SS		 631{
632 struct xhci_ep_ctx *out_ep_ctx;
633 struct xhci_ep_ctx *in_ep_ctx;
634
913a8a34
SS		 635 out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
636 in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
f2217e8e
SS		 637
638 in_ep_ctx->ep_info = out_ep_ctx->ep_info;
639 in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
640 in_ep_ctx->deq = out_ep_ctx->deq;
641 in_ep_ctx->tx_info = out_ep_ctx->tx_info;
642}
643
644/* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
645 * Useful when you want to change one particular aspect of the endpoint and then
646 * issue a configure endpoint command. Only the context entries field matters,
647 * but we'll copy the whole thing anyway.
648 */
913a8a34
SS		 649void xhci_slot_copy(struct xhci_hcd *xhci,
650 struct xhci_container_ctx *in_ctx,
651 struct xhci_container_ctx *out_ctx)
f2217e8e
SS		 652{
653 struct xhci_slot_ctx *in_slot_ctx;
654 struct xhci_slot_ctx *out_slot_ctx;
655
913a8a34
SS		 656 in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
657 out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
f2217e8e
SS		 658
659 in_slot_ctx->dev_info = out_slot_ctx->dev_info;
660 in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
661 in_slot_ctx->tt_info = out_slot_ctx->tt_info;
662 in_slot_ctx->dev_state = out_slot_ctx->dev_state;
663}
664
254c80a3
JY		 665/* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
666static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
667{
668 int i;
669 struct device *dev = xhci_to_hcd(xhci)->self.controller;
670 int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
671
672 xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp);
673
674 if (!num_sp)
675 return 0;
676
677 xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
678 if (!xhci->scratchpad)
679 goto fail_sp;
680
681 xhci->scratchpad->sp_array =
682 pci_alloc_consistent(to_pci_dev(dev),
683 num_sp * sizeof(u64),
684 &xhci->scratchpad->sp_dma);
685 if (!xhci->scratchpad->sp_array)
686 goto fail_sp2;
687
688 xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
689 if (!xhci->scratchpad->sp_buffers)
690 goto fail_sp3;
691
692 xhci->scratchpad->sp_dma_buffers =
693 kzalloc(sizeof(dma_addr_t) * num_sp, flags);
694
695 if (!xhci->scratchpad->sp_dma_buffers)
696 goto fail_sp4;
697
698 xhci->dcbaa->dev_context_ptrs[0] = xhci->scratchpad->sp_dma;
699 for (i = 0; i < num_sp; i++) {
700 dma_addr_t dma;
701 void *buf = pci_alloc_consistent(to_pci_dev(dev),
702 xhci->page_size, &dma);
703 if (!buf)
704 goto fail_sp5;
705
706 xhci->scratchpad->sp_array[i] = dma;
707 xhci->scratchpad->sp_buffers[i] = buf;
708 xhci->scratchpad->sp_dma_buffers[i] = dma;
709 }
710
711 return 0;
712
713 fail_sp5:
714 for (i = i - 1; i >= 0; i--) {
715 pci_free_consistent(to_pci_dev(dev), xhci->page_size,
716 xhci->scratchpad->sp_buffers[i],
717 xhci->scratchpad->sp_dma_buffers[i]);
718 }
719 kfree(xhci->scratchpad->sp_dma_buffers);
720
721 fail_sp4:
722 kfree(xhci->scratchpad->sp_buffers);
723
724 fail_sp3:
725 pci_free_consistent(to_pci_dev(dev), num_sp * sizeof(u64),
726 xhci->scratchpad->sp_array,
727 xhci->scratchpad->sp_dma);
728
729 fail_sp2:
730 kfree(xhci->scratchpad);
731 xhci->scratchpad = NULL;
732
733 fail_sp:
734 return -ENOMEM;
735}
736
737static void scratchpad_free(struct xhci_hcd *xhci)
738{
739 int num_sp;
740 int i;
741 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
742
743 if (!xhci->scratchpad)
744 return;
745
746 num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
747
748 for (i = 0; i < num_sp; i++) {
749 pci_free_consistent(pdev, xhci->page_size,
750 xhci->scratchpad->sp_buffers[i],
751 xhci->scratchpad->sp_dma_buffers[i]);
752 }
753 kfree(xhci->scratchpad->sp_dma_buffers);
754 kfree(xhci->scratchpad->sp_buffers);
755 pci_free_consistent(pdev, num_sp * sizeof(u64),
756 xhci->scratchpad->sp_array,
757 xhci->scratchpad->sp_dma);
758 kfree(xhci->scratchpad);
759 xhci->scratchpad = NULL;
760}
761
913a8a34
SS		 762struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
763 bool allocate_completion, gfp_t mem_flags)
764{
765 struct xhci_command *command;
766
767 command = kzalloc(sizeof(*command), mem_flags);
768 if (!command)
769 return NULL;
770
771 command->in_ctx =
772 xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, mem_flags);
773 if (!command->in_ctx)
774 return NULL;
775
776 if (allocate_completion) {
777 command->completion =
778 kzalloc(sizeof(struct completion), mem_flags);
779 if (!command->completion) {
780 xhci_free_container_ctx(xhci, command->in_ctx);
781 return NULL;
782 }
783 init_completion(command->completion);
784 }
785
786 command->status = 0;
787 INIT_LIST_HEAD(&command->cmd_list);
788 return command;
789}
790
791void xhci_free_command(struct xhci_hcd *xhci,
792 struct xhci_command *command)
793{
794 xhci_free_container_ctx(xhci,
795 command->in_ctx);
796 kfree(command->completion);
797 kfree(command);
798}
799
66d4eadd
SS		 800void xhci_mem_cleanup(struct xhci_hcd *xhci)
801{
0ebbab37
SS		 802 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
803 int size;
3ffbba95 804 int i;
0ebbab37
SS		 805
806 /* Free the Event Ring Segment Table and the actual Event Ring */
807 xhci_writel(xhci, 0, &xhci->ir_set->erst_size);
8e595a5d
SS		 808 xhci_write_64(xhci, 0, &xhci->ir_set->erst_base);
809 xhci_write_64(xhci, 0, &xhci->ir_set->erst_dequeue);
0ebbab37
SS		 810 size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
811 if (xhci->erst.entries)
812 pci_free_consistent(pdev, size,
813 xhci->erst.entries, xhci->erst.erst_dma_addr);
814 xhci->erst.entries = NULL;
815 xhci_dbg(xhci, "Freed ERST\n");
816 if (xhci->event_ring)
817 xhci_ring_free(xhci, xhci->event_ring);
818 xhci->event_ring = NULL;
819 xhci_dbg(xhci, "Freed event ring\n");
820
8e595a5d 821 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
0ebbab37
SS		 822 if (xhci->cmd_ring)
823 xhci_ring_free(xhci, xhci->cmd_ring);
824 xhci->cmd_ring = NULL;
825 xhci_dbg(xhci, "Freed command ring\n");
3ffbba95
SS		 826
827 for (i = 1; i < MAX_HC_SLOTS; ++i)
828 xhci_free_virt_device(xhci, i);
829
0ebbab37
SS		 830 if (xhci->segment_pool)
831 dma_pool_destroy(xhci->segment_pool);
832 xhci->segment_pool = NULL;
833 xhci_dbg(xhci, "Freed segment pool\n");
3ffbba95
SS		 834
835 if (xhci->device_pool)
836 dma_pool_destroy(xhci->device_pool);
837 xhci->device_pool = NULL;
838 xhci_dbg(xhci, "Freed device context pool\n");
839
8e595a5d 840 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
a74588f9
SS		 841 if (xhci->dcbaa)
842 pci_free_consistent(pdev, sizeof(*xhci->dcbaa),
843 xhci->dcbaa, xhci->dcbaa->dma);
844 xhci->dcbaa = NULL;
3ffbba95 845
66d4eadd
SS		 846 xhci->page_size = 0;
847 xhci->page_shift = 0;
254c80a3 848 scratchpad_free(xhci);
66d4eadd
SS		 849}
850
851int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
852{
0ebbab37
SS		 853 dma_addr_t dma;
854 struct device *dev = xhci_to_hcd(xhci)->self.controller;
66d4eadd 855 unsigned int val, val2;
8e595a5d 856 u64 val_64;
0ebbab37 857 struct xhci_segment *seg;
66d4eadd
SS		 858 u32 page_size;
859 int i;
860
861 page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
862 xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
863 for (i = 0; i < 16; i++) {
864 if ((0x1 & page_size) != 0)
865 break;
866 page_size = page_size >> 1;
867 }
868 if (i < 16)
869 xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024);
870 else
871 xhci_warn(xhci, "WARN: no supported page size\n");
872 /* Use 4K pages, since that's common and the minimum the HC supports */
873 xhci->page_shift = 12;
874 xhci->page_size = 1 << xhci->page_shift;
875 xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024);
876
877 /*
878 * Program the Number of Device Slots Enabled field in the CONFIG
879 * register with the max value of slots the HC can handle.
880 */
881 val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1));
882 xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n",
883 (unsigned int) val);
884 val2 = xhci_readl(xhci, &xhci->op_regs->config_reg);
885 val |= (val2 & ~HCS_SLOTS_MASK);
886 xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n",
887 (unsigned int) val);
888 xhci_writel(xhci, val, &xhci->op_regs->config_reg);
889
a74588f9
SS		 890 /*
891 * Section 5.4.8 - doorbell array must be
892 * "physically contiguous and 64-byte (cache line) aligned".
893 */
894 xhci->dcbaa = pci_alloc_consistent(to_pci_dev(dev),
895 sizeof(*xhci->dcbaa), &dma);
896 if (!xhci->dcbaa)
897 goto fail;
898 memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
899 xhci->dcbaa->dma = dma;
700e2052
GKH		 900 xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
901 (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
8e595a5d 902 xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
a74588f9 903
0ebbab37
SS		 904 /*
905 * Initialize the ring segment pool. The ring must be a contiguous
906 * structure comprised of TRBs. The TRBs must be 16 byte aligned,
907 * however, the command ring segment needs 64-byte aligned segments,
908 * so we pick the greater alignment need.
909 */
910 xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
911 SEGMENT_SIZE, 64, xhci->page_size);
d115b048 912
3ffbba95 913 /* See Table 46 and Note on Figure 55 */
3ffbba95 914 xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
d115b048 915 2112, 64, xhci->page_size);
3ffbba95 916 if (!xhci->segment_pool || !xhci->device_pool)
0ebbab37
SS		 917 goto fail;
918
919 /* Set up the command ring to have one segments for now. */
920 xhci->cmd_ring = xhci_ring_alloc(xhci, 1, true, flags);
921 if (!xhci->cmd_ring)
922 goto fail;
700e2052
GKH		 923 xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
924 xhci_dbg(xhci, "First segment DMA is 0x%llx\n",
925 (unsigned long long)xhci->cmd_ring->first_seg->dma);
0ebbab37
SS		 926
927 /* Set the address in the Command Ring Control register */
8e595a5d
SS		 928 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
929 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
930 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
0ebbab37 931 xhci->cmd_ring->cycle_state;
8e595a5d
SS		 932 xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val);
933 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
0ebbab37
SS		 934 xhci_dbg_cmd_ptrs(xhci);
935
936 val = xhci_readl(xhci, &xhci->cap_regs->db_off);
937 val &= DBOFF_MASK;
938 xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
939 " from cap regs base addr\n", val);
940 xhci->dba = (void *) xhci->cap_regs + val;
941 xhci_dbg_regs(xhci);
942 xhci_print_run_regs(xhci);
943 /* Set ir_set to interrupt register set 0 */
944 xhci->ir_set = (void *) xhci->run_regs->ir_set;
945
946 /*
947 * Event ring setup: Allocate a normal ring, but also setup
948 * the event ring segment table (ERST). Section 4.9.3.
949 */
950 xhci_dbg(xhci, "// Allocating event ring\n");
951 xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, false, flags);
952 if (!xhci->event_ring)
953 goto fail;
954
955 xhci->erst.entries = pci_alloc_consistent(to_pci_dev(dev),
956 sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS, &dma);
957 if (!xhci->erst.entries)
958 goto fail;
700e2052
GKH		 959 xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n",
960 (unsigned long long)dma);
0ebbab37
SS		 961
962 memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
963 xhci->erst.num_entries = ERST_NUM_SEGS;
964 xhci->erst.erst_dma_addr = dma;
700e2052 965 xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
0ebbab37 966 xhci->erst.num_entries,
700e2052
GKH		 967 xhci->erst.entries,
968 (unsigned long long)xhci->erst.erst_dma_addr);
0ebbab37
SS		 969
970 /* set ring base address and size for each segment table entry */
971 for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
972 struct xhci_erst_entry *entry = &xhci->erst.entries[val];
8e595a5d 973 entry->seg_addr = seg->dma;
0ebbab37
SS		 974 entry->seg_size = TRBS_PER_SEGMENT;
975 entry->rsvd = 0;
976 seg = seg->next;
977 }
978
979 /* set ERST count with the number of entries in the segment table */
980 val = xhci_readl(xhci, &xhci->ir_set->erst_size);
981 val &= ERST_SIZE_MASK;
982 val |= ERST_NUM_SEGS;
983 xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
984 val);
985 xhci_writel(xhci, val, &xhci->ir_set->erst_size);
986
987 xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
988 /* set the segment table base address */
700e2052
GKH		 989 xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n",
990 (unsigned long long)xhci->erst.erst_dma_addr);
8e595a5d
SS		 991 val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
992 val_64 &= ERST_PTR_MASK;
993 val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
994 xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
0ebbab37
SS		 995
996 /* Set the event ring dequeue address */
23e3be11 997 xhci_set_hc_event_deq(xhci);
0ebbab37
SS		 998 xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
999 xhci_print_ir_set(xhci, xhci->ir_set, 0);
1000
1001 /*
1002 * XXX: Might need to set the Interrupter Moderation Register to
1003 * something other than the default (~1ms minimum between interrupts).
1004 * See section 5.5.1.2.
1005 */
3ffbba95
SS		 1006 init_completion(&xhci->addr_dev);
1007 for (i = 0; i < MAX_HC_SLOTS; ++i)
1008 xhci->devs[i] = 0;
66d4eadd 1009
254c80a3
JY		 1010 if (scratchpad_alloc(xhci, flags))
1011 goto fail;
1012
66d4eadd 1013 return 0;
254c80a3 1014
66d4eadd
SS		 1015fail:
1016 xhci_warn(xhci, "Couldn't initialize memory\n");
1017 xhci_mem_cleanup(xhci);
1018 return -ENOMEM;
1019}
Linux kernel - Deliverables
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