xHCI: add XHCI_RESET_ON_RESUME quirk for VIA xHCI host
[deliverable/linux.git] / drivers / usb / host / xhci-ring.c
CommitLineData
7f84eef0
SS
1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23/*
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
29 *
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
41 *
42 * Cycle bit rules:
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
47 *
48 * Producer rules:
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
52 * cycle state).
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
56 *
57 * Consumer rules:
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
65 */
66
8a96c052 67#include <linux/scatterlist.h>
5a0e3ad6 68#include <linux/slab.h>
7f84eef0
SS
69#include "xhci.h"
70
be88fe4f
AX
71static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
72 struct xhci_virt_device *virt_dev,
73 struct xhci_event_cmd *event);
74
7f84eef0
SS
75/*
76 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
77 * address of the TRB.
78 */
23e3be11 79dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
7f84eef0
SS
80 union xhci_trb *trb)
81{
6071d836 82 unsigned long segment_offset;
7f84eef0 83
6071d836 84 if (!seg || !trb || trb < seg->trbs)
7f84eef0 85 return 0;
6071d836
SS
86 /* offset in TRBs */
87 segment_offset = trb - seg->trbs;
88 if (segment_offset > TRBS_PER_SEGMENT)
7f84eef0 89 return 0;
6071d836 90 return seg->dma + (segment_offset * sizeof(*trb));
7f84eef0
SS
91}
92
93/* Does this link TRB point to the first segment in a ring,
94 * or was the previous TRB the last TRB on the last segment in the ERST?
95 */
575688e1 96static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
7f84eef0
SS
97 struct xhci_segment *seg, union xhci_trb *trb)
98{
99 if (ring == xhci->event_ring)
100 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
101 (seg->next == xhci->event_ring->first_seg);
102 else
28ccd296 103 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
7f84eef0
SS
104}
105
106/* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
107 * segment? I.e. would the updated event TRB pointer step off the end of the
108 * event seg?
109 */
575688e1 110static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
7f84eef0
SS
111 struct xhci_segment *seg, union xhci_trb *trb)
112{
113 if (ring == xhci->event_ring)
114 return trb == &seg->trbs[TRBS_PER_SEGMENT];
115 else
f5960b69 116 return TRB_TYPE_LINK_LE32(trb->link.control);
7f84eef0
SS
117}
118
575688e1 119static int enqueue_is_link_trb(struct xhci_ring *ring)
6c12db90
JY
120{
121 struct xhci_link_trb *link = &ring->enqueue->link;
f5960b69 122 return TRB_TYPE_LINK_LE32(link->control);
6c12db90
JY
123}
124
ae636747
SS
125/* Updates trb to point to the next TRB in the ring, and updates seg if the next
126 * TRB is in a new segment. This does not skip over link TRBs, and it does not
127 * effect the ring dequeue or enqueue pointers.
128 */
129static void next_trb(struct xhci_hcd *xhci,
130 struct xhci_ring *ring,
131 struct xhci_segment **seg,
132 union xhci_trb **trb)
133{
134 if (last_trb(xhci, ring, *seg, *trb)) {
135 *seg = (*seg)->next;
136 *trb = ((*seg)->trbs);
137 } else {
a1669b2c 138 (*trb)++;
ae636747
SS
139 }
140}
141
7f84eef0
SS
142/*
143 * See Cycle bit rules. SW is the consumer for the event ring only.
144 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
145 */
3b72fca0 146static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
7f84eef0 147{
b008df60 148 union xhci_trb *next;
66e49d87 149 unsigned long long addr;
7f84eef0
SS
150
151 ring->deq_updates++;
b008df60
AX
152
153 /* If this is not event ring, there is one more usable TRB */
154 if (ring->type != TYPE_EVENT &&
155 !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
156 ring->num_trbs_free++;
157 next = ++(ring->dequeue);
158
7f84eef0
SS
159 /* Update the dequeue pointer further if that was a link TRB or we're at
160 * the end of an event ring segment (which doesn't have link TRBS)
161 */
162 while (last_trb(xhci, ring, ring->deq_seg, next)) {
3b72fca0
AX
163 if (ring->type == TYPE_EVENT && last_trb_on_last_seg(xhci,
164 ring, ring->deq_seg, next)) {
7f84eef0 165 ring->cycle_state = (ring->cycle_state ? 0 : 1);
7f84eef0
SS
166 }
167 ring->deq_seg = ring->deq_seg->next;
168 ring->dequeue = ring->deq_seg->trbs;
169 next = ring->dequeue;
170 }
66e49d87 171 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
7f84eef0
SS
172}
173
174/*
175 * See Cycle bit rules. SW is the consumer for the event ring only.
176 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
177 *
178 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
179 * chain bit is set), then set the chain bit in all the following link TRBs.
180 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
181 * have their chain bit cleared (so that each Link TRB is a separate TD).
182 *
183 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
b0567b3f
SS
184 * set, but other sections talk about dealing with the chain bit set. This was
185 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
186 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
6cc30d85
SS
187 *
188 * @more_trbs_coming: Will you enqueue more TRBs before calling
189 * prepare_transfer()?
7f84eef0 190 */
6cc30d85 191static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
3b72fca0 192 bool more_trbs_coming)
7f84eef0
SS
193{
194 u32 chain;
195 union xhci_trb *next;
66e49d87 196 unsigned long long addr;
7f84eef0 197
28ccd296 198 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
b008df60
AX
199 /* If this is not event ring, there is one less usable TRB */
200 if (ring->type != TYPE_EVENT &&
201 !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
202 ring->num_trbs_free--;
7f84eef0
SS
203 next = ++(ring->enqueue);
204
205 ring->enq_updates++;
206 /* Update the dequeue pointer further if that was a link TRB or we're at
207 * the end of an event ring segment (which doesn't have link TRBS)
208 */
209 while (last_trb(xhci, ring, ring->enq_seg, next)) {
3b72fca0
AX
210 if (ring->type != TYPE_EVENT) {
211 /*
212 * If the caller doesn't plan on enqueueing more
213 * TDs before ringing the doorbell, then we
214 * don't want to give the link TRB to the
215 * hardware just yet. We'll give the link TRB
216 * back in prepare_ring() just before we enqueue
217 * the TD at the top of the ring.
218 */
219 if (!chain && !more_trbs_coming)
220 break;
6cc30d85 221
3b72fca0
AX
222 /* If we're not dealing with 0.95 hardware or
223 * isoc rings on AMD 0.96 host,
224 * carry over the chain bit of the previous TRB
225 * (which may mean the chain bit is cleared).
226 */
227 if (!(ring->type == TYPE_ISOC &&
228 (xhci->quirks & XHCI_AMD_0x96_HOST))
7e393a83 229 && !xhci_link_trb_quirk(xhci)) {
3b72fca0
AX
230 next->link.control &=
231 cpu_to_le32(~TRB_CHAIN);
232 next->link.control |=
233 cpu_to_le32(chain);
7f84eef0 234 }
3b72fca0
AX
235 /* Give this link TRB to the hardware */
236 wmb();
237 next->link.control ^= cpu_to_le32(TRB_CYCLE);
238
7f84eef0
SS
239 /* Toggle the cycle bit after the last ring segment. */
240 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
241 ring->cycle_state = (ring->cycle_state ? 0 : 1);
7f84eef0
SS
242 }
243 }
244 ring->enq_seg = ring->enq_seg->next;
245 ring->enqueue = ring->enq_seg->trbs;
246 next = ring->enqueue;
247 }
66e49d87 248 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
7f84eef0
SS
249}
250
251/*
085deb16
AX
252 * Check to see if there's room to enqueue num_trbs on the ring and make sure
253 * enqueue pointer will not advance into dequeue segment. See rules above.
7f84eef0 254 */
b008df60 255static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
7f84eef0
SS
256 unsigned int num_trbs)
257{
085deb16 258 int num_trbs_in_deq_seg;
b008df60 259
085deb16
AX
260 if (ring->num_trbs_free < num_trbs)
261 return 0;
262
263 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
264 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
265 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
266 return 0;
267 }
268
269 return 1;
7f84eef0
SS
270}
271
7f84eef0 272/* Ring the host controller doorbell after placing a command on the ring */
23e3be11 273void xhci_ring_cmd_db(struct xhci_hcd *xhci)
7f84eef0 274{
7f84eef0 275 xhci_dbg(xhci, "// Ding dong!\n");
50d64676 276 xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
7f84eef0
SS
277 /* Flush PCI posted writes */
278 xhci_readl(xhci, &xhci->dba->doorbell[0]);
279}
280
be88fe4f 281void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
ae636747 282 unsigned int slot_id,
e9df17eb
SS
283 unsigned int ep_index,
284 unsigned int stream_id)
ae636747 285{
28ccd296 286 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
50d64676
MW
287 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
288 unsigned int ep_state = ep->ep_state;
ae636747 289
ae636747 290 /* Don't ring the doorbell for this endpoint if there are pending
50d64676 291 * cancellations because we don't want to interrupt processing.
8df75f42
SS
292 * We don't want to restart any stream rings if there's a set dequeue
293 * pointer command pending because the device can choose to start any
294 * stream once the endpoint is on the HW schedule.
295 * FIXME - check all the stream rings for pending cancellations.
ae636747 296 */
50d64676
MW
297 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
298 (ep_state & EP_HALTED))
299 return;
300 xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
301 /* The CPU has better things to do at this point than wait for a
302 * write-posting flush. It'll get there soon enough.
303 */
ae636747
SS
304}
305
e9df17eb
SS
306/* Ring the doorbell for any rings with pending URBs */
307static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
308 unsigned int slot_id,
309 unsigned int ep_index)
310{
311 unsigned int stream_id;
312 struct xhci_virt_ep *ep;
313
314 ep = &xhci->devs[slot_id]->eps[ep_index];
315
316 /* A ring has pending URBs if its TD list is not empty */
317 if (!(ep->ep_state & EP_HAS_STREAMS)) {
318 if (!(list_empty(&ep->ring->td_list)))
be88fe4f 319 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
e9df17eb
SS
320 return;
321 }
322
323 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
324 stream_id++) {
325 struct xhci_stream_info *stream_info = ep->stream_info;
326 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
be88fe4f
AX
327 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
328 stream_id);
e9df17eb
SS
329 }
330}
331
ae636747
SS
332/*
333 * Find the segment that trb is in. Start searching in start_seg.
334 * If we must move past a segment that has a link TRB with a toggle cycle state
335 * bit set, then we will toggle the value pointed at by cycle_state.
336 */
337static struct xhci_segment *find_trb_seg(
338 struct xhci_segment *start_seg,
339 union xhci_trb *trb, int *cycle_state)
340{
341 struct xhci_segment *cur_seg = start_seg;
342 struct xhci_generic_trb *generic_trb;
343
344 while (cur_seg->trbs > trb ||
345 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
346 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
f5960b69 347 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
ba0a4d9a 348 *cycle_state ^= 0x1;
ae636747
SS
349 cur_seg = cur_seg->next;
350 if (cur_seg == start_seg)
351 /* Looped over the entire list. Oops! */
326b4810 352 return NULL;
ae636747
SS
353 }
354 return cur_seg;
355}
356
021bff91
SS
357
358static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
359 unsigned int slot_id, unsigned int ep_index,
360 unsigned int stream_id)
361{
362 struct xhci_virt_ep *ep;
363
364 ep = &xhci->devs[slot_id]->eps[ep_index];
365 /* Common case: no streams */
366 if (!(ep->ep_state & EP_HAS_STREAMS))
367 return ep->ring;
368
369 if (stream_id == 0) {
370 xhci_warn(xhci,
371 "WARN: Slot ID %u, ep index %u has streams, "
372 "but URB has no stream ID.\n",
373 slot_id, ep_index);
374 return NULL;
375 }
376
377 if (stream_id < ep->stream_info->num_streams)
378 return ep->stream_info->stream_rings[stream_id];
379
380 xhci_warn(xhci,
381 "WARN: Slot ID %u, ep index %u has "
382 "stream IDs 1 to %u allocated, "
383 "but stream ID %u is requested.\n",
384 slot_id, ep_index,
385 ep->stream_info->num_streams - 1,
386 stream_id);
387 return NULL;
388}
389
390/* Get the right ring for the given URB.
391 * If the endpoint supports streams, boundary check the URB's stream ID.
392 * If the endpoint doesn't support streams, return the singular endpoint ring.
393 */
394static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
395 struct urb *urb)
396{
397 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
398 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
399}
400
ae636747
SS
401/*
402 * Move the xHC's endpoint ring dequeue pointer past cur_td.
403 * Record the new state of the xHC's endpoint ring dequeue segment,
404 * dequeue pointer, and new consumer cycle state in state.
405 * Update our internal representation of the ring's dequeue pointer.
406 *
407 * We do this in three jumps:
408 * - First we update our new ring state to be the same as when the xHC stopped.
409 * - Then we traverse the ring to find the segment that contains
410 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
411 * any link TRBs with the toggle cycle bit set.
412 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
413 * if we've moved it past a link TRB with the toggle cycle bit set.
28ccd296
ME
414 *
415 * Some of the uses of xhci_generic_trb are grotty, but if they're done
416 * with correct __le32 accesses they should work fine. Only users of this are
417 * in here.
ae636747 418 */
c92bcfa7 419void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
ae636747 420 unsigned int slot_id, unsigned int ep_index,
e9df17eb
SS
421 unsigned int stream_id, struct xhci_td *cur_td,
422 struct xhci_dequeue_state *state)
ae636747
SS
423{
424 struct xhci_virt_device *dev = xhci->devs[slot_id];
e9df17eb 425 struct xhci_ring *ep_ring;
ae636747 426 struct xhci_generic_trb *trb;
d115b048 427 struct xhci_ep_ctx *ep_ctx;
c92bcfa7 428 dma_addr_t addr;
ae636747 429
e9df17eb
SS
430 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
431 ep_index, stream_id);
432 if (!ep_ring) {
433 xhci_warn(xhci, "WARN can't find new dequeue state "
434 "for invalid stream ID %u.\n",
435 stream_id);
436 return;
437 }
ae636747 438 state->new_cycle_state = 0;
c92bcfa7 439 xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
ae636747 440 state->new_deq_seg = find_trb_seg(cur_td->start_seg,
63a0d9ab 441 dev->eps[ep_index].stopped_trb,
ae636747 442 &state->new_cycle_state);
68e41c5d
PZ
443 if (!state->new_deq_seg) {
444 WARN_ON(1);
445 return;
446 }
447
ae636747 448 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
c92bcfa7 449 xhci_dbg(xhci, "Finding endpoint context\n");
d115b048 450 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
28ccd296 451 state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
ae636747
SS
452
453 state->new_deq_ptr = cur_td->last_trb;
c92bcfa7 454 xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
ae636747
SS
455 state->new_deq_seg = find_trb_seg(state->new_deq_seg,
456 state->new_deq_ptr,
457 &state->new_cycle_state);
68e41c5d
PZ
458 if (!state->new_deq_seg) {
459 WARN_ON(1);
460 return;
461 }
ae636747
SS
462
463 trb = &state->new_deq_ptr->generic;
f5960b69
ME
464 if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
465 (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
ba0a4d9a 466 state->new_cycle_state ^= 0x1;
ae636747
SS
467 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
468
01a1fdb9
SS
469 /*
470 * If there is only one segment in a ring, find_trb_seg()'s while loop
471 * will not run, and it will return before it has a chance to see if it
472 * needs to toggle the cycle bit. It can't tell if the stalled transfer
473 * ended just before the link TRB on a one-segment ring, or if the TD
474 * wrapped around the top of the ring, because it doesn't have the TD in
475 * question. Look for the one-segment case where stalled TRB's address
476 * is greater than the new dequeue pointer address.
477 */
478 if (ep_ring->first_seg == ep_ring->first_seg->next &&
479 state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
480 state->new_cycle_state ^= 0x1;
481 xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
482
ae636747 483 /* Don't update the ring cycle state for the producer (us). */
c92bcfa7
SS
484 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
485 state->new_deq_seg);
486 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
487 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
488 (unsigned long long) addr);
ae636747
SS
489}
490
522989a2
SS
491/* flip_cycle means flip the cycle bit of all but the first and last TRB.
492 * (The last TRB actually points to the ring enqueue pointer, which is not part
493 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
494 */
23e3be11 495static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
522989a2 496 struct xhci_td *cur_td, bool flip_cycle)
ae636747
SS
497{
498 struct xhci_segment *cur_seg;
499 union xhci_trb *cur_trb;
500
501 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
502 true;
503 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
f5960b69 504 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
ae636747
SS
505 /* Unchain any chained Link TRBs, but
506 * leave the pointers intact.
507 */
28ccd296 508 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
522989a2
SS
509 /* Flip the cycle bit (link TRBs can't be the first
510 * or last TRB).
511 */
512 if (flip_cycle)
513 cur_trb->generic.field[3] ^=
514 cpu_to_le32(TRB_CYCLE);
ae636747 515 xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
700e2052
GKH
516 xhci_dbg(xhci, "Address = %p (0x%llx dma); "
517 "in seg %p (0x%llx dma)\n",
518 cur_trb,
23e3be11 519 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
700e2052
GKH
520 cur_seg,
521 (unsigned long long)cur_seg->dma);
ae636747
SS
522 } else {
523 cur_trb->generic.field[0] = 0;
524 cur_trb->generic.field[1] = 0;
525 cur_trb->generic.field[2] = 0;
526 /* Preserve only the cycle bit of this TRB */
28ccd296 527 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
522989a2
SS
528 /* Flip the cycle bit except on the first or last TRB */
529 if (flip_cycle && cur_trb != cur_td->first_trb &&
530 cur_trb != cur_td->last_trb)
531 cur_trb->generic.field[3] ^=
532 cpu_to_le32(TRB_CYCLE);
28ccd296
ME
533 cur_trb->generic.field[3] |= cpu_to_le32(
534 TRB_TYPE(TRB_TR_NOOP));
79688acf
SS
535 xhci_dbg(xhci, "TRB to noop at offset 0x%llx\n",
536 (unsigned long long)
537 xhci_trb_virt_to_dma(cur_seg, cur_trb));
ae636747
SS
538 }
539 if (cur_trb == cur_td->last_trb)
540 break;
541 }
542}
543
544static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
e9df17eb
SS
545 unsigned int ep_index, unsigned int stream_id,
546 struct xhci_segment *deq_seg,
ae636747
SS
547 union xhci_trb *deq_ptr, u32 cycle_state);
548
c92bcfa7 549void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
63a0d9ab 550 unsigned int slot_id, unsigned int ep_index,
e9df17eb 551 unsigned int stream_id,
63a0d9ab 552 struct xhci_dequeue_state *deq_state)
c92bcfa7 553{
63a0d9ab
SS
554 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
555
c92bcfa7
SS
556 xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
557 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
558 deq_state->new_deq_seg,
559 (unsigned long long)deq_state->new_deq_seg->dma,
560 deq_state->new_deq_ptr,
561 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
562 deq_state->new_cycle_state);
e9df17eb 563 queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
c92bcfa7
SS
564 deq_state->new_deq_seg,
565 deq_state->new_deq_ptr,
566 (u32) deq_state->new_cycle_state);
567 /* Stop the TD queueing code from ringing the doorbell until
568 * this command completes. The HC won't set the dequeue pointer
569 * if the ring is running, and ringing the doorbell starts the
570 * ring running.
571 */
63a0d9ab 572 ep->ep_state |= SET_DEQ_PENDING;
c92bcfa7
SS
573}
574
575688e1 575static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
6f5165cf
SS
576 struct xhci_virt_ep *ep)
577{
578 ep->ep_state &= ~EP_HALT_PENDING;
579 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
580 * timer is running on another CPU, we don't decrement stop_cmds_pending
581 * (since we didn't successfully stop the watchdog timer).
582 */
583 if (del_timer(&ep->stop_cmd_timer))
584 ep->stop_cmds_pending--;
585}
586
587/* Must be called with xhci->lock held in interrupt context */
588static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
589 struct xhci_td *cur_td, int status, char *adjective)
590{
214f76f7 591 struct usb_hcd *hcd;
8e51adcc
AX
592 struct urb *urb;
593 struct urb_priv *urb_priv;
6f5165cf 594
8e51adcc
AX
595 urb = cur_td->urb;
596 urb_priv = urb->hcpriv;
597 urb_priv->td_cnt++;
214f76f7 598 hcd = bus_to_hcd(urb->dev->bus);
6f5165cf 599
8e51adcc
AX
600 /* Only giveback urb when this is the last td in urb */
601 if (urb_priv->td_cnt == urb_priv->length) {
c41136b0
AX
602 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
603 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
604 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
605 if (xhci->quirks & XHCI_AMD_PLL_FIX)
606 usb_amd_quirk_pll_enable();
607 }
608 }
8e51adcc 609 usb_hcd_unlink_urb_from_ep(hcd, urb);
8e51adcc
AX
610
611 spin_unlock(&xhci->lock);
612 usb_hcd_giveback_urb(hcd, urb, status);
613 xhci_urb_free_priv(xhci, urb_priv);
614 spin_lock(&xhci->lock);
8e51adcc 615 }
6f5165cf
SS
616}
617
ae636747
SS
618/*
619 * When we get a command completion for a Stop Endpoint Command, we need to
620 * unlink any cancelled TDs from the ring. There are two ways to do that:
621 *
622 * 1. If the HW was in the middle of processing the TD that needs to be
623 * cancelled, then we must move the ring's dequeue pointer past the last TRB
624 * in the TD with a Set Dequeue Pointer Command.
625 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
626 * bit cleared) so that the HW will skip over them.
627 */
628static void handle_stopped_endpoint(struct xhci_hcd *xhci,
be88fe4f 629 union xhci_trb *trb, struct xhci_event_cmd *event)
ae636747
SS
630{
631 unsigned int slot_id;
632 unsigned int ep_index;
be88fe4f 633 struct xhci_virt_device *virt_dev;
ae636747 634 struct xhci_ring *ep_ring;
63a0d9ab 635 struct xhci_virt_ep *ep;
ae636747 636 struct list_head *entry;
326b4810 637 struct xhci_td *cur_td = NULL;
ae636747
SS
638 struct xhci_td *last_unlinked_td;
639
c92bcfa7 640 struct xhci_dequeue_state deq_state;
ae636747 641
be88fe4f 642 if (unlikely(TRB_TO_SUSPEND_PORT(
28ccd296 643 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
be88fe4f 644 slot_id = TRB_TO_SLOT_ID(
28ccd296 645 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
be88fe4f
AX
646 virt_dev = xhci->devs[slot_id];
647 if (virt_dev)
648 handle_cmd_in_cmd_wait_list(xhci, virt_dev,
649 event);
650 else
651 xhci_warn(xhci, "Stop endpoint command "
652 "completion for disabled slot %u\n",
653 slot_id);
654 return;
655 }
656
ae636747 657 memset(&deq_state, 0, sizeof(deq_state));
28ccd296
ME
658 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
659 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
63a0d9ab 660 ep = &xhci->devs[slot_id]->eps[ep_index];
ae636747 661
678539cf 662 if (list_empty(&ep->cancelled_td_list)) {
6f5165cf 663 xhci_stop_watchdog_timer_in_irq(xhci, ep);
0714a57c
SS
664 ep->stopped_td = NULL;
665 ep->stopped_trb = NULL;
e9df17eb 666 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
ae636747 667 return;
678539cf 668 }
ae636747
SS
669
670 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
671 * We have the xHCI lock, so nothing can modify this list until we drop
672 * it. We're also in the event handler, so we can't get re-interrupted
673 * if another Stop Endpoint command completes
674 */
63a0d9ab 675 list_for_each(entry, &ep->cancelled_td_list) {
ae636747 676 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
79688acf
SS
677 xhci_dbg(xhci, "Removing canceled TD starting at 0x%llx (dma).\n",
678 (unsigned long long)xhci_trb_virt_to_dma(
679 cur_td->start_seg, cur_td->first_trb));
e9df17eb
SS
680 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
681 if (!ep_ring) {
682 /* This shouldn't happen unless a driver is mucking
683 * with the stream ID after submission. This will
684 * leave the TD on the hardware ring, and the hardware
685 * will try to execute it, and may access a buffer
686 * that has already been freed. In the best case, the
687 * hardware will execute it, and the event handler will
688 * ignore the completion event for that TD, since it was
689 * removed from the td_list for that endpoint. In
690 * short, don't muck with the stream ID after
691 * submission.
692 */
693 xhci_warn(xhci, "WARN Cancelled URB %p "
694 "has invalid stream ID %u.\n",
695 cur_td->urb,
696 cur_td->urb->stream_id);
697 goto remove_finished_td;
698 }
ae636747
SS
699 /*
700 * If we stopped on the TD we need to cancel, then we have to
701 * move the xHC endpoint ring dequeue pointer past this TD.
702 */
63a0d9ab 703 if (cur_td == ep->stopped_td)
e9df17eb
SS
704 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
705 cur_td->urb->stream_id,
706 cur_td, &deq_state);
ae636747 707 else
522989a2 708 td_to_noop(xhci, ep_ring, cur_td, false);
e9df17eb 709remove_finished_td:
ae636747
SS
710 /*
711 * The event handler won't see a completion for this TD anymore,
712 * so remove it from the endpoint ring's TD list. Keep it in
713 * the cancelled TD list for URB completion later.
714 */
585df1d9 715 list_del_init(&cur_td->td_list);
ae636747
SS
716 }
717 last_unlinked_td = cur_td;
6f5165cf 718 xhci_stop_watchdog_timer_in_irq(xhci, ep);
ae636747
SS
719
720 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
721 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
63a0d9ab 722 xhci_queue_new_dequeue_state(xhci,
e9df17eb
SS
723 slot_id, ep_index,
724 ep->stopped_td->urb->stream_id,
725 &deq_state);
ac9d8fe7 726 xhci_ring_cmd_db(xhci);
ae636747 727 } else {
e9df17eb
SS
728 /* Otherwise ring the doorbell(s) to restart queued transfers */
729 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
ae636747 730 }
1624ae1c
SS
731 ep->stopped_td = NULL;
732 ep->stopped_trb = NULL;
ae636747
SS
733
734 /*
735 * Drop the lock and complete the URBs in the cancelled TD list.
736 * New TDs to be cancelled might be added to the end of the list before
737 * we can complete all the URBs for the TDs we already unlinked.
738 * So stop when we've completed the URB for the last TD we unlinked.
739 */
740 do {
63a0d9ab 741 cur_td = list_entry(ep->cancelled_td_list.next,
ae636747 742 struct xhci_td, cancelled_td_list);
585df1d9 743 list_del_init(&cur_td->cancelled_td_list);
ae636747
SS
744
745 /* Clean up the cancelled URB */
ae636747
SS
746 /* Doesn't matter what we pass for status, since the core will
747 * just overwrite it (because the URB has been unlinked).
748 */
6f5165cf 749 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
ae636747 750
6f5165cf
SS
751 /* Stop processing the cancelled list if the watchdog timer is
752 * running.
753 */
754 if (xhci->xhc_state & XHCI_STATE_DYING)
755 return;
ae636747
SS
756 } while (cur_td != last_unlinked_td);
757
758 /* Return to the event handler with xhci->lock re-acquired */
759}
760
6f5165cf
SS
761/* Watchdog timer function for when a stop endpoint command fails to complete.
762 * In this case, we assume the host controller is broken or dying or dead. The
763 * host may still be completing some other events, so we have to be careful to
764 * let the event ring handler and the URB dequeueing/enqueueing functions know
765 * through xhci->state.
766 *
767 * The timer may also fire if the host takes a very long time to respond to the
768 * command, and the stop endpoint command completion handler cannot delete the
769 * timer before the timer function is called. Another endpoint cancellation may
770 * sneak in before the timer function can grab the lock, and that may queue
771 * another stop endpoint command and add the timer back. So we cannot use a
772 * simple flag to say whether there is a pending stop endpoint command for a
773 * particular endpoint.
774 *
775 * Instead we use a combination of that flag and a counter for the number of
776 * pending stop endpoint commands. If the timer is the tail end of the last
777 * stop endpoint command, and the endpoint's command is still pending, we assume
778 * the host is dying.
779 */
780void xhci_stop_endpoint_command_watchdog(unsigned long arg)
781{
782 struct xhci_hcd *xhci;
783 struct xhci_virt_ep *ep;
784 struct xhci_virt_ep *temp_ep;
785 struct xhci_ring *ring;
786 struct xhci_td *cur_td;
787 int ret, i, j;
f43d6231 788 unsigned long flags;
6f5165cf
SS
789
790 ep = (struct xhci_virt_ep *) arg;
791 xhci = ep->xhci;
792
f43d6231 793 spin_lock_irqsave(&xhci->lock, flags);
6f5165cf
SS
794
795 ep->stop_cmds_pending--;
796 if (xhci->xhc_state & XHCI_STATE_DYING) {
797 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
798 "xHCI as DYING, exiting.\n");
f43d6231 799 spin_unlock_irqrestore(&xhci->lock, flags);
6f5165cf
SS
800 return;
801 }
802 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
803 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
804 "exiting.\n");
f43d6231 805 spin_unlock_irqrestore(&xhci->lock, flags);
6f5165cf
SS
806 return;
807 }
808
809 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
810 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
811 /* Oops, HC is dead or dying or at least not responding to the stop
812 * endpoint command.
813 */
814 xhci->xhc_state |= XHCI_STATE_DYING;
815 /* Disable interrupts from the host controller and start halting it */
816 xhci_quiesce(xhci);
f43d6231 817 spin_unlock_irqrestore(&xhci->lock, flags);
6f5165cf
SS
818
819 ret = xhci_halt(xhci);
820
f43d6231 821 spin_lock_irqsave(&xhci->lock, flags);
6f5165cf
SS
822 if (ret < 0) {
823 /* This is bad; the host is not responding to commands and it's
824 * not allowing itself to be halted. At least interrupts are
ac04e6ff 825 * disabled. If we call usb_hc_died(), it will attempt to
6f5165cf
SS
826 * disconnect all device drivers under this host. Those
827 * disconnect() methods will wait for all URBs to be unlinked,
828 * so we must complete them.
829 */
830 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
831 xhci_warn(xhci, "Completing active URBs anyway.\n");
832 /* We could turn all TDs on the rings to no-ops. This won't
833 * help if the host has cached part of the ring, and is slow if
834 * we want to preserve the cycle bit. Skip it and hope the host
835 * doesn't touch the memory.
836 */
837 }
838 for (i = 0; i < MAX_HC_SLOTS; i++) {
839 if (!xhci->devs[i])
840 continue;
841 for (j = 0; j < 31; j++) {
842 temp_ep = &xhci->devs[i]->eps[j];
843 ring = temp_ep->ring;
844 if (!ring)
845 continue;
846 xhci_dbg(xhci, "Killing URBs for slot ID %u, "
847 "ep index %u\n", i, j);
848 while (!list_empty(&ring->td_list)) {
849 cur_td = list_first_entry(&ring->td_list,
850 struct xhci_td,
851 td_list);
585df1d9 852 list_del_init(&cur_td->td_list);
6f5165cf 853 if (!list_empty(&cur_td->cancelled_td_list))
585df1d9 854 list_del_init(&cur_td->cancelled_td_list);
6f5165cf
SS
855 xhci_giveback_urb_in_irq(xhci, cur_td,
856 -ESHUTDOWN, "killed");
857 }
858 while (!list_empty(&temp_ep->cancelled_td_list)) {
859 cur_td = list_first_entry(
860 &temp_ep->cancelled_td_list,
861 struct xhci_td,
862 cancelled_td_list);
585df1d9 863 list_del_init(&cur_td->cancelled_td_list);
6f5165cf
SS
864 xhci_giveback_urb_in_irq(xhci, cur_td,
865 -ESHUTDOWN, "killed");
866 }
867 }
868 }
f43d6231 869 spin_unlock_irqrestore(&xhci->lock, flags);
6f5165cf 870 xhci_dbg(xhci, "Calling usb_hc_died()\n");
f6ff0ac8 871 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
6f5165cf
SS
872 xhci_dbg(xhci, "xHCI host controller is dead.\n");
873}
874
b008df60
AX
875
876static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
877 struct xhci_virt_device *dev,
878 struct xhci_ring *ep_ring,
879 unsigned int ep_index)
880{
881 union xhci_trb *dequeue_temp;
882 int num_trbs_free_temp;
883 bool revert = false;
884
885 num_trbs_free_temp = ep_ring->num_trbs_free;
886 dequeue_temp = ep_ring->dequeue;
887
888 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
889 /* We have more usable TRBs */
890 ep_ring->num_trbs_free++;
891 ep_ring->dequeue++;
892 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
893 ep_ring->dequeue)) {
894 if (ep_ring->dequeue ==
895 dev->eps[ep_index].queued_deq_ptr)
896 break;
897 ep_ring->deq_seg = ep_ring->deq_seg->next;
898 ep_ring->dequeue = ep_ring->deq_seg->trbs;
899 }
900 if (ep_ring->dequeue == dequeue_temp) {
901 revert = true;
902 break;
903 }
904 }
905
906 if (revert) {
907 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
908 ep_ring->num_trbs_free = num_trbs_free_temp;
909 }
910}
911
ae636747
SS
912/*
913 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
914 * we need to clear the set deq pending flag in the endpoint ring state, so that
915 * the TD queueing code can ring the doorbell again. We also need to ring the
916 * endpoint doorbell to restart the ring, but only if there aren't more
917 * cancellations pending.
918 */
919static void handle_set_deq_completion(struct xhci_hcd *xhci,
920 struct xhci_event_cmd *event,
921 union xhci_trb *trb)
922{
923 unsigned int slot_id;
924 unsigned int ep_index;
e9df17eb 925 unsigned int stream_id;
ae636747
SS
926 struct xhci_ring *ep_ring;
927 struct xhci_virt_device *dev;
d115b048
JY
928 struct xhci_ep_ctx *ep_ctx;
929 struct xhci_slot_ctx *slot_ctx;
ae636747 930
28ccd296
ME
931 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
932 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
933 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
ae636747 934 dev = xhci->devs[slot_id];
e9df17eb
SS
935
936 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
937 if (!ep_ring) {
938 xhci_warn(xhci, "WARN Set TR deq ptr command for "
939 "freed stream ID %u\n",
940 stream_id);
941 /* XXX: Harmless??? */
942 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
943 return;
944 }
945
d115b048
JY
946 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
947 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
ae636747 948
28ccd296 949 if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
ae636747
SS
950 unsigned int ep_state;
951 unsigned int slot_state;
952
28ccd296 953 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
ae636747
SS
954 case COMP_TRB_ERR:
955 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
956 "of stream ID configuration\n");
957 break;
958 case COMP_CTX_STATE:
959 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
960 "to incorrect slot or ep state.\n");
28ccd296 961 ep_state = le32_to_cpu(ep_ctx->ep_info);
ae636747 962 ep_state &= EP_STATE_MASK;
28ccd296 963 slot_state = le32_to_cpu(slot_ctx->dev_state);
ae636747
SS
964 slot_state = GET_SLOT_STATE(slot_state);
965 xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
966 slot_state, ep_state);
967 break;
968 case COMP_EBADSLT:
969 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
970 "slot %u was not enabled.\n", slot_id);
971 break;
972 default:
973 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
974 "completion code of %u.\n",
28ccd296 975 GET_COMP_CODE(le32_to_cpu(event->status)));
ae636747
SS
976 break;
977 }
978 /* OK what do we do now? The endpoint state is hosed, and we
979 * should never get to this point if the synchronization between
980 * queueing, and endpoint state are correct. This might happen
981 * if the device gets disconnected after we've finished
982 * cancelling URBs, which might not be an error...
983 */
984 } else {
8e595a5d 985 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
28ccd296 986 le64_to_cpu(ep_ctx->deq));
bf161e85 987 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
28ccd296
ME
988 dev->eps[ep_index].queued_deq_ptr) ==
989 (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
bf161e85
SS
990 /* Update the ring's dequeue segment and dequeue pointer
991 * to reflect the new position.
992 */
b008df60
AX
993 update_ring_for_set_deq_completion(xhci, dev,
994 ep_ring, ep_index);
bf161e85
SS
995 } else {
996 xhci_warn(xhci, "Mismatch between completed Set TR Deq "
997 "Ptr command & xHCI internal state.\n");
998 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
999 dev->eps[ep_index].queued_deq_seg,
1000 dev->eps[ep_index].queued_deq_ptr);
1001 }
ae636747
SS
1002 }
1003
63a0d9ab 1004 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
bf161e85
SS
1005 dev->eps[ep_index].queued_deq_seg = NULL;
1006 dev->eps[ep_index].queued_deq_ptr = NULL;
e9df17eb
SS
1007 /* Restart any rings with pending URBs */
1008 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
ae636747
SS
1009}
1010
a1587d97
SS
1011static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1012 struct xhci_event_cmd *event,
1013 union xhci_trb *trb)
1014{
1015 int slot_id;
1016 unsigned int ep_index;
1017
28ccd296
ME
1018 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1019 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
a1587d97
SS
1020 /* This command will only fail if the endpoint wasn't halted,
1021 * but we don't care.
1022 */
1023 xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
f5960b69 1024 GET_COMP_CODE(le32_to_cpu(event->status)));
a1587d97 1025
ac9d8fe7
SS
1026 /* HW with the reset endpoint quirk needs to have a configure endpoint
1027 * command complete before the endpoint can be used. Queue that here
1028 * because the HW can't handle two commands being queued in a row.
1029 */
1030 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1031 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1032 xhci_queue_configure_endpoint(xhci,
913a8a34
SS
1033 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1034 false);
ac9d8fe7
SS
1035 xhci_ring_cmd_db(xhci);
1036 } else {
e9df17eb 1037 /* Clear our internal halted state and restart the ring(s) */
63a0d9ab 1038 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
e9df17eb 1039 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
ac9d8fe7 1040 }
a1587d97 1041}
ae636747 1042
a50c8aa9
SS
1043/* Check to see if a command in the device's command queue matches this one.
1044 * Signal the completion or free the command, and return 1. Return 0 if the
1045 * completed command isn't at the head of the command list.
1046 */
1047static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1048 struct xhci_virt_device *virt_dev,
1049 struct xhci_event_cmd *event)
1050{
1051 struct xhci_command *command;
1052
1053 if (list_empty(&virt_dev->cmd_list))
1054 return 0;
1055
1056 command = list_entry(virt_dev->cmd_list.next,
1057 struct xhci_command, cmd_list);
1058 if (xhci->cmd_ring->dequeue != command->command_trb)
1059 return 0;
1060
28ccd296 1061 command->status = GET_COMP_CODE(le32_to_cpu(event->status));
a50c8aa9
SS
1062 list_del(&command->cmd_list);
1063 if (command->completion)
1064 complete(command->completion);
1065 else
1066 xhci_free_command(xhci, command);
1067 return 1;
1068}
1069
7f84eef0
SS
1070static void handle_cmd_completion(struct xhci_hcd *xhci,
1071 struct xhci_event_cmd *event)
1072{
28ccd296 1073 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
7f84eef0
SS
1074 u64 cmd_dma;
1075 dma_addr_t cmd_dequeue_dma;
ac9d8fe7 1076 struct xhci_input_control_ctx *ctrl_ctx;
913a8a34 1077 struct xhci_virt_device *virt_dev;
ac9d8fe7
SS
1078 unsigned int ep_index;
1079 struct xhci_ring *ep_ring;
1080 unsigned int ep_state;
7f84eef0 1081
28ccd296 1082 cmd_dma = le64_to_cpu(event->cmd_trb);
23e3be11 1083 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
7f84eef0
SS
1084 xhci->cmd_ring->dequeue);
1085 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1086 if (cmd_dequeue_dma == 0) {
1087 xhci->error_bitmask |= 1 << 4;
1088 return;
1089 }
1090 /* Does the DMA address match our internal dequeue pointer address? */
1091 if (cmd_dma != (u64) cmd_dequeue_dma) {
1092 xhci->error_bitmask |= 1 << 5;
1093 return;
1094 }
28ccd296
ME
1095 switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1096 & TRB_TYPE_BITMASK) {
3ffbba95 1097 case TRB_TYPE(TRB_ENABLE_SLOT):
28ccd296 1098 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
3ffbba95
SS
1099 xhci->slot_id = slot_id;
1100 else
1101 xhci->slot_id = 0;
1102 complete(&xhci->addr_dev);
1103 break;
1104 case TRB_TYPE(TRB_DISABLE_SLOT):
2cf95c18
SS
1105 if (xhci->devs[slot_id]) {
1106 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1107 /* Delete default control endpoint resources */
1108 xhci_free_device_endpoint_resources(xhci,
1109 xhci->devs[slot_id], true);
3ffbba95 1110 xhci_free_virt_device(xhci, slot_id);
2cf95c18 1111 }
3ffbba95 1112 break;
f94e0186 1113 case TRB_TYPE(TRB_CONFIG_EP):
913a8a34 1114 virt_dev = xhci->devs[slot_id];
a50c8aa9 1115 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
913a8a34 1116 break;
ac9d8fe7
SS
1117 /*
1118 * Configure endpoint commands can come from the USB core
1119 * configuration or alt setting changes, or because the HW
1120 * needed an extra configure endpoint command after a reset
8df75f42
SS
1121 * endpoint command or streams were being configured.
1122 * If the command was for a halted endpoint, the xHCI driver
1123 * is not waiting on the configure endpoint command.
ac9d8fe7
SS
1124 */
1125 ctrl_ctx = xhci_get_input_control_ctx(xhci,
913a8a34 1126 virt_dev->in_ctx);
ac9d8fe7 1127 /* Input ctx add_flags are the endpoint index plus one */
28ccd296 1128 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
06df5729 1129 /* A usb_set_interface() call directly after clearing a halted
e9df17eb
SS
1130 * condition may race on this quirky hardware. Not worth
1131 * worrying about, since this is prototype hardware. Not sure
1132 * if this will work for streams, but streams support was
1133 * untested on this prototype.
06df5729 1134 */
ac9d8fe7 1135 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
06df5729 1136 ep_index != (unsigned int) -1 &&
28ccd296
ME
1137 le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1138 le32_to_cpu(ctrl_ctx->drop_flags)) {
06df5729
SS
1139 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1140 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1141 if (!(ep_state & EP_HALTED))
1142 goto bandwidth_change;
1143 xhci_dbg(xhci, "Completed config ep cmd - "
1144 "last ep index = %d, state = %d\n",
1145 ep_index, ep_state);
e9df17eb 1146 /* Clear internal halted state and restart ring(s) */
63a0d9ab 1147 xhci->devs[slot_id]->eps[ep_index].ep_state &=
ac9d8fe7 1148 ~EP_HALTED;
e9df17eb 1149 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
06df5729 1150 break;
ac9d8fe7 1151 }
06df5729
SS
1152bandwidth_change:
1153 xhci_dbg(xhci, "Completed config ep cmd\n");
1154 xhci->devs[slot_id]->cmd_status =
28ccd296 1155 GET_COMP_CODE(le32_to_cpu(event->status));
06df5729 1156 complete(&xhci->devs[slot_id]->cmd_completion);
f94e0186 1157 break;
2d3f1fac 1158 case TRB_TYPE(TRB_EVAL_CONTEXT):
ac1c1b7f
SS
1159 virt_dev = xhci->devs[slot_id];
1160 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1161 break;
28ccd296 1162 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
2d3f1fac
SS
1163 complete(&xhci->devs[slot_id]->cmd_completion);
1164 break;
3ffbba95 1165 case TRB_TYPE(TRB_ADDR_DEV):
28ccd296 1166 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
3ffbba95
SS
1167 complete(&xhci->addr_dev);
1168 break;
ae636747 1169 case TRB_TYPE(TRB_STOP_RING):
be88fe4f 1170 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
ae636747
SS
1171 break;
1172 case TRB_TYPE(TRB_SET_DEQ):
1173 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1174 break;
7f84eef0 1175 case TRB_TYPE(TRB_CMD_NOOP):
7f84eef0 1176 break;
a1587d97
SS
1177 case TRB_TYPE(TRB_RESET_EP):
1178 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1179 break;
2a8f82c4
SS
1180 case TRB_TYPE(TRB_RESET_DEV):
1181 xhci_dbg(xhci, "Completed reset device command.\n");
1182 slot_id = TRB_TO_SLOT_ID(
28ccd296 1183 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
2a8f82c4
SS
1184 virt_dev = xhci->devs[slot_id];
1185 if (virt_dev)
1186 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1187 else
1188 xhci_warn(xhci, "Reset device command completion "
1189 "for disabled slot %u\n", slot_id);
1190 break;
0238634d
SS
1191 case TRB_TYPE(TRB_NEC_GET_FW):
1192 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1193 xhci->error_bitmask |= 1 << 6;
1194 break;
1195 }
1196 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
28ccd296
ME
1197 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1198 NEC_FW_MINOR(le32_to_cpu(event->status)));
0238634d 1199 break;
7f84eef0
SS
1200 default:
1201 /* Skip over unknown commands on the event ring */
1202 xhci->error_bitmask |= 1 << 6;
1203 break;
1204 }
3b72fca0 1205 inc_deq(xhci, xhci->cmd_ring);
7f84eef0
SS
1206}
1207
0238634d
SS
1208static void handle_vendor_event(struct xhci_hcd *xhci,
1209 union xhci_trb *event)
1210{
1211 u32 trb_type;
1212
28ccd296 1213 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
0238634d
SS
1214 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1215 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1216 handle_cmd_completion(xhci, &event->event_cmd);
1217}
1218
f6ff0ac8
SS
1219/* @port_id: the one-based port ID from the hardware (indexed from array of all
1220 * port registers -- USB 3.0 and USB 2.0).
1221 *
1222 * Returns a zero-based port number, which is suitable for indexing into each of
1223 * the split roothubs' port arrays and bus state arrays.
d0cd5d48 1224 * Add one to it in order to call xhci_find_slot_id_by_port.
f6ff0ac8
SS
1225 */
1226static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1227 struct xhci_hcd *xhci, u32 port_id)
1228{
1229 unsigned int i;
1230 unsigned int num_similar_speed_ports = 0;
1231
1232 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1233 * and usb2_ports are 0-based indexes. Count the number of similar
1234 * speed ports, up to 1 port before this port.
1235 */
1236 for (i = 0; i < (port_id - 1); i++) {
1237 u8 port_speed = xhci->port_array[i];
1238
1239 /*
1240 * Skip ports that don't have known speeds, or have duplicate
1241 * Extended Capabilities port speed entries.
1242 */
22e04870 1243 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
f6ff0ac8
SS
1244 continue;
1245
1246 /*
1247 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1248 * 1.1 ports are under the USB 2.0 hub. If the port speed
1249 * matches the device speed, it's a similar speed port.
1250 */
1251 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1252 num_similar_speed_ports++;
1253 }
1254 return num_similar_speed_ports;
1255}
1256
623bef9e
SS
1257static void handle_device_notification(struct xhci_hcd *xhci,
1258 union xhci_trb *event)
1259{
1260 u32 slot_id;
4ee823b8 1261 struct usb_device *udev;
623bef9e
SS
1262
1263 slot_id = TRB_TO_SLOT_ID(event->generic.field[3]);
4ee823b8 1264 if (!xhci->devs[slot_id]) {
623bef9e
SS
1265 xhci_warn(xhci, "Device Notification event for "
1266 "unused slot %u\n", slot_id);
4ee823b8
SS
1267 return;
1268 }
1269
1270 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1271 slot_id);
1272 udev = xhci->devs[slot_id]->udev;
1273 if (udev && udev->parent)
1274 usb_wakeup_notification(udev->parent, udev->portnum);
623bef9e
SS
1275}
1276
0f2a7930
SS
1277static void handle_port_status(struct xhci_hcd *xhci,
1278 union xhci_trb *event)
1279{
f6ff0ac8 1280 struct usb_hcd *hcd;
0f2a7930 1281 u32 port_id;
56192531 1282 u32 temp, temp1;
518e848e 1283 int max_ports;
56192531 1284 int slot_id;
5308a91b 1285 unsigned int faked_port_index;
f6ff0ac8 1286 u8 major_revision;
20b67cf5 1287 struct xhci_bus_state *bus_state;
28ccd296 1288 __le32 __iomem **port_array;
386139d7 1289 bool bogus_port_status = false;
0f2a7930
SS
1290
1291 /* Port status change events always have a successful completion code */
28ccd296 1292 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
0f2a7930
SS
1293 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1294 xhci->error_bitmask |= 1 << 8;
1295 }
28ccd296 1296 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
0f2a7930
SS
1297 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1298
518e848e
SS
1299 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1300 if ((port_id <= 0) || (port_id > max_ports)) {
56192531 1301 xhci_warn(xhci, "Invalid port id %d\n", port_id);
386139d7 1302 bogus_port_status = true;
56192531
AX
1303 goto cleanup;
1304 }
1305
f6ff0ac8
SS
1306 /* Figure out which usb_hcd this port is attached to:
1307 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1308 */
1309 major_revision = xhci->port_array[port_id - 1];
1310 if (major_revision == 0) {
1311 xhci_warn(xhci, "Event for port %u not in "
1312 "Extended Capabilities, ignoring.\n",
1313 port_id);
386139d7 1314 bogus_port_status = true;
f6ff0ac8 1315 goto cleanup;
5308a91b 1316 }
22e04870 1317 if (major_revision == DUPLICATE_ENTRY) {
f6ff0ac8
SS
1318 xhci_warn(xhci, "Event for port %u duplicated in"
1319 "Extended Capabilities, ignoring.\n",
1320 port_id);
386139d7 1321 bogus_port_status = true;
f6ff0ac8
SS
1322 goto cleanup;
1323 }
1324
1325 /*
1326 * Hardware port IDs reported by a Port Status Change Event include USB
1327 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1328 * resume event, but we first need to translate the hardware port ID
1329 * into the index into the ports on the correct split roothub, and the
1330 * correct bus_state structure.
1331 */
1332 /* Find the right roothub. */
1333 hcd = xhci_to_hcd(xhci);
1334 if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1335 hcd = xhci->shared_hcd;
1336 bus_state = &xhci->bus_state[hcd_index(hcd)];
1337 if (hcd->speed == HCD_USB3)
1338 port_array = xhci->usb3_ports;
1339 else
1340 port_array = xhci->usb2_ports;
1341 /* Find the faked port hub number */
1342 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1343 port_id);
5308a91b 1344
5308a91b 1345 temp = xhci_readl(xhci, port_array[faked_port_index]);
7111ebc9 1346 if (hcd->state == HC_STATE_SUSPENDED) {
56192531
AX
1347 xhci_dbg(xhci, "resume root hub\n");
1348 usb_hcd_resume_root_hub(hcd);
1349 }
1350
1351 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1352 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1353
1354 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1355 if (!(temp1 & CMD_RUN)) {
1356 xhci_warn(xhci, "xHC is not running.\n");
1357 goto cleanup;
1358 }
1359
1360 if (DEV_SUPERSPEED(temp)) {
d93814cf 1361 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
4ee823b8
SS
1362 /* Set a flag to say the port signaled remote wakeup,
1363 * so we can tell the difference between the end of
1364 * device and host initiated resume.
1365 */
1366 bus_state->port_remote_wakeup |= 1 << faked_port_index;
d93814cf
SS
1367 xhci_test_and_clear_bit(xhci, port_array,
1368 faked_port_index, PORT_PLC);
c9682dff
AX
1369 xhci_set_link_state(xhci, port_array, faked_port_index,
1370 XDEV_U0);
d93814cf
SS
1371 /* Need to wait until the next link state change
1372 * indicates the device is actually in U0.
1373 */
1374 bogus_port_status = true;
1375 goto cleanup;
56192531
AX
1376 } else {
1377 xhci_dbg(xhci, "resume HS port %d\n", port_id);
f6ff0ac8 1378 bus_state->resume_done[faked_port_index] = jiffies +
56192531
AX
1379 msecs_to_jiffies(20);
1380 mod_timer(&hcd->rh_timer,
f6ff0ac8 1381 bus_state->resume_done[faked_port_index]);
56192531
AX
1382 /* Do the rest in GetPortStatus */
1383 }
1384 }
d93814cf
SS
1385
1386 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1387 DEV_SUPERSPEED(temp)) {
1388 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
4ee823b8
SS
1389 /* We've just brought the device into U0 through either the
1390 * Resume state after a device remote wakeup, or through the
1391 * U3Exit state after a host-initiated resume. If it's a device
1392 * initiated remote wake, don't pass up the link state change,
1393 * so the roothub behavior is consistent with external
1394 * USB 3.0 hub behavior.
1395 */
d93814cf
SS
1396 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1397 faked_port_index + 1);
1398 if (slot_id && xhci->devs[slot_id])
1399 xhci_ring_device(xhci, slot_id);
4ee823b8
SS
1400 if (bus_state->port_remote_wakeup && (1 << faked_port_index)) {
1401 bus_state->port_remote_wakeup &=
1402 ~(1 << faked_port_index);
1403 xhci_test_and_clear_bit(xhci, port_array,
1404 faked_port_index, PORT_PLC);
1405 usb_wakeup_notification(hcd->self.root_hub,
1406 faked_port_index + 1);
1407 bogus_port_status = true;
1408 goto cleanup;
1409 }
d93814cf 1410 }
56192531 1411
6fd45621
AX
1412 if (hcd->speed != HCD_USB3)
1413 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1414 PORT_PLC);
1415
56192531 1416cleanup:
0f2a7930 1417 /* Update event ring dequeue pointer before dropping the lock */
3b72fca0 1418 inc_deq(xhci, xhci->event_ring);
0f2a7930 1419
386139d7
SS
1420 /* Don't make the USB core poll the roothub if we got a bad port status
1421 * change event. Besides, at that point we can't tell which roothub
1422 * (USB 2.0 or USB 3.0) to kick.
1423 */
1424 if (bogus_port_status)
1425 return;
1426
0f2a7930
SS
1427 spin_unlock(&xhci->lock);
1428 /* Pass this up to the core */
f6ff0ac8 1429 usb_hcd_poll_rh_status(hcd);
0f2a7930
SS
1430 spin_lock(&xhci->lock);
1431}
1432
d0e96f5a
SS
1433/*
1434 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1435 * at end_trb, which may be in another segment. If the suspect DMA address is a
1436 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1437 * returns 0.
1438 */
6648f29d 1439struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
d0e96f5a
SS
1440 union xhci_trb *start_trb,
1441 union xhci_trb *end_trb,
1442 dma_addr_t suspect_dma)
1443{
1444 dma_addr_t start_dma;
1445 dma_addr_t end_seg_dma;
1446 dma_addr_t end_trb_dma;
1447 struct xhci_segment *cur_seg;
1448
23e3be11 1449 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
d0e96f5a
SS
1450 cur_seg = start_seg;
1451
1452 do {
2fa88daa 1453 if (start_dma == 0)
326b4810 1454 return NULL;
ae636747 1455 /* We may get an event for a Link TRB in the middle of a TD */
23e3be11 1456 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
2fa88daa 1457 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
d0e96f5a 1458 /* If the end TRB isn't in this segment, this is set to 0 */
23e3be11 1459 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
d0e96f5a
SS
1460
1461 if (end_trb_dma > 0) {
1462 /* The end TRB is in this segment, so suspect should be here */
1463 if (start_dma <= end_trb_dma) {
1464 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1465 return cur_seg;
1466 } else {
1467 /* Case for one segment with
1468 * a TD wrapped around to the top
1469 */
1470 if ((suspect_dma >= start_dma &&
1471 suspect_dma <= end_seg_dma) ||
1472 (suspect_dma >= cur_seg->dma &&
1473 suspect_dma <= end_trb_dma))
1474 return cur_seg;
1475 }
326b4810 1476 return NULL;
d0e96f5a
SS
1477 } else {
1478 /* Might still be somewhere in this segment */
1479 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1480 return cur_seg;
1481 }
1482 cur_seg = cur_seg->next;
23e3be11 1483 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
2fa88daa 1484 } while (cur_seg != start_seg);
d0e96f5a 1485
326b4810 1486 return NULL;
d0e96f5a
SS
1487}
1488
bcef3fd5
SS
1489static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1490 unsigned int slot_id, unsigned int ep_index,
e9df17eb 1491 unsigned int stream_id,
bcef3fd5
SS
1492 struct xhci_td *td, union xhci_trb *event_trb)
1493{
1494 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1495 ep->ep_state |= EP_HALTED;
1496 ep->stopped_td = td;
1497 ep->stopped_trb = event_trb;
e9df17eb 1498 ep->stopped_stream = stream_id;
1624ae1c 1499
bcef3fd5
SS
1500 xhci_queue_reset_ep(xhci, slot_id, ep_index);
1501 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1624ae1c
SS
1502
1503 ep->stopped_td = NULL;
1504 ep->stopped_trb = NULL;
5e5cf6fc 1505 ep->stopped_stream = 0;
1624ae1c 1506
bcef3fd5
SS
1507 xhci_ring_cmd_db(xhci);
1508}
1509
1510/* Check if an error has halted the endpoint ring. The class driver will
1511 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1512 * However, a babble and other errors also halt the endpoint ring, and the class
1513 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1514 * Ring Dequeue Pointer command manually.
1515 */
1516static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1517 struct xhci_ep_ctx *ep_ctx,
1518 unsigned int trb_comp_code)
1519{
1520 /* TRB completion codes that may require a manual halt cleanup */
1521 if (trb_comp_code == COMP_TX_ERR ||
1522 trb_comp_code == COMP_BABBLE ||
1523 trb_comp_code == COMP_SPLIT_ERR)
1524 /* The 0.96 spec says a babbling control endpoint
1525 * is not halted. The 0.96 spec says it is. Some HW
1526 * claims to be 0.95 compliant, but it halts the control
1527 * endpoint anyway. Check if a babble halted the
1528 * endpoint.
1529 */
f5960b69
ME
1530 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1531 cpu_to_le32(EP_STATE_HALTED))
bcef3fd5
SS
1532 return 1;
1533
1534 return 0;
1535}
1536
b45b5069
SS
1537int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1538{
1539 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1540 /* Vendor defined "informational" completion code,
1541 * treat as not-an-error.
1542 */
1543 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1544 trb_comp_code);
1545 xhci_dbg(xhci, "Treating code as success.\n");
1546 return 1;
1547 }
1548 return 0;
1549}
1550
4422da61
AX
1551/*
1552 * Finish the td processing, remove the td from td list;
1553 * Return 1 if the urb can be given back.
1554 */
1555static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1556 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1557 struct xhci_virt_ep *ep, int *status, bool skip)
1558{
1559 struct xhci_virt_device *xdev;
1560 struct xhci_ring *ep_ring;
1561 unsigned int slot_id;
1562 int ep_index;
1563 struct urb *urb = NULL;
1564 struct xhci_ep_ctx *ep_ctx;
1565 int ret = 0;
8e51adcc 1566 struct urb_priv *urb_priv;
4422da61
AX
1567 u32 trb_comp_code;
1568
28ccd296 1569 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
4422da61 1570 xdev = xhci->devs[slot_id];
28ccd296
ME
1571 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1572 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
4422da61 1573 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
28ccd296 1574 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
4422da61
AX
1575
1576 if (skip)
1577 goto td_cleanup;
1578
1579 if (trb_comp_code == COMP_STOP_INVAL ||
1580 trb_comp_code == COMP_STOP) {
1581 /* The Endpoint Stop Command completion will take care of any
1582 * stopped TDs. A stopped TD may be restarted, so don't update
1583 * the ring dequeue pointer or take this TD off any lists yet.
1584 */
1585 ep->stopped_td = td;
1586 ep->stopped_trb = event_trb;
1587 return 0;
1588 } else {
1589 if (trb_comp_code == COMP_STALL) {
1590 /* The transfer is completed from the driver's
1591 * perspective, but we need to issue a set dequeue
1592 * command for this stalled endpoint to move the dequeue
1593 * pointer past the TD. We can't do that here because
1594 * the halt condition must be cleared first. Let the
1595 * USB class driver clear the stall later.
1596 */
1597 ep->stopped_td = td;
1598 ep->stopped_trb = event_trb;
1599 ep->stopped_stream = ep_ring->stream_id;
1600 } else if (xhci_requires_manual_halt_cleanup(xhci,
1601 ep_ctx, trb_comp_code)) {
1602 /* Other types of errors halt the endpoint, but the
1603 * class driver doesn't call usb_reset_endpoint() unless
1604 * the error is -EPIPE. Clear the halted status in the
1605 * xHCI hardware manually.
1606 */
1607 xhci_cleanup_halted_endpoint(xhci,
1608 slot_id, ep_index, ep_ring->stream_id,
1609 td, event_trb);
1610 } else {
1611 /* Update ring dequeue pointer */
1612 while (ep_ring->dequeue != td->last_trb)
3b72fca0
AX
1613 inc_deq(xhci, ep_ring);
1614 inc_deq(xhci, ep_ring);
4422da61
AX
1615 }
1616
1617td_cleanup:
1618 /* Clean up the endpoint's TD list */
1619 urb = td->urb;
8e51adcc 1620 urb_priv = urb->hcpriv;
4422da61
AX
1621
1622 /* Do one last check of the actual transfer length.
1623 * If the host controller said we transferred more data than
1624 * the buffer length, urb->actual_length will be a very big
1625 * number (since it's unsigned). Play it safe and say we didn't
1626 * transfer anything.
1627 */
1628 if (urb->actual_length > urb->transfer_buffer_length) {
1629 xhci_warn(xhci, "URB transfer length is wrong, "
1630 "xHC issue? req. len = %u, "
1631 "act. len = %u\n",
1632 urb->transfer_buffer_length,
1633 urb->actual_length);
1634 urb->actual_length = 0;
1635 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1636 *status = -EREMOTEIO;
1637 else
1638 *status = 0;
1639 }
585df1d9 1640 list_del_init(&td->td_list);
4422da61
AX
1641 /* Was this TD slated to be cancelled but completed anyway? */
1642 if (!list_empty(&td->cancelled_td_list))
585df1d9 1643 list_del_init(&td->cancelled_td_list);
4422da61 1644
8e51adcc
AX
1645 urb_priv->td_cnt++;
1646 /* Giveback the urb when all the tds are completed */
c41136b0 1647 if (urb_priv->td_cnt == urb_priv->length) {
8e51adcc 1648 ret = 1;
c41136b0
AX
1649 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1650 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1651 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1652 == 0) {
1653 if (xhci->quirks & XHCI_AMD_PLL_FIX)
1654 usb_amd_quirk_pll_enable();
1655 }
1656 }
1657 }
4422da61
AX
1658 }
1659
1660 return ret;
1661}
1662
8af56be1
AX
1663/*
1664 * Process control tds, update urb status and actual_length.
1665 */
1666static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1667 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1668 struct xhci_virt_ep *ep, int *status)
1669{
1670 struct xhci_virt_device *xdev;
1671 struct xhci_ring *ep_ring;
1672 unsigned int slot_id;
1673 int ep_index;
1674 struct xhci_ep_ctx *ep_ctx;
1675 u32 trb_comp_code;
1676
28ccd296 1677 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
8af56be1 1678 xdev = xhci->devs[slot_id];
28ccd296
ME
1679 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1680 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
8af56be1 1681 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
28ccd296 1682 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
8af56be1 1683
8af56be1
AX
1684 switch (trb_comp_code) {
1685 case COMP_SUCCESS:
1686 if (event_trb == ep_ring->dequeue) {
1687 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1688 "without IOC set??\n");
1689 *status = -ESHUTDOWN;
1690 } else if (event_trb != td->last_trb) {
1691 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1692 "without IOC set??\n");
1693 *status = -ESHUTDOWN;
1694 } else {
8af56be1
AX
1695 *status = 0;
1696 }
1697 break;
1698 case COMP_SHORT_TX:
8af56be1
AX
1699 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1700 *status = -EREMOTEIO;
1701 else
1702 *status = 0;
1703 break;
3abeca99
SS
1704 case COMP_STOP_INVAL:
1705 case COMP_STOP:
1706 return finish_td(xhci, td, event_trb, event, ep, status, false);
8af56be1
AX
1707 default:
1708 if (!xhci_requires_manual_halt_cleanup(xhci,
1709 ep_ctx, trb_comp_code))
1710 break;
1711 xhci_dbg(xhci, "TRB error code %u, "
1712 "halted endpoint index = %u\n",
1713 trb_comp_code, ep_index);
1714 /* else fall through */
1715 case COMP_STALL:
1716 /* Did we transfer part of the data (middle) phase? */
1717 if (event_trb != ep_ring->dequeue &&
1718 event_trb != td->last_trb)
1719 td->urb->actual_length =
1720 td->urb->transfer_buffer_length
28ccd296 1721 - TRB_LEN(le32_to_cpu(event->transfer_len));
8af56be1
AX
1722 else
1723 td->urb->actual_length = 0;
1724
1725 xhci_cleanup_halted_endpoint(xhci,
1726 slot_id, ep_index, 0, td, event_trb);
1727 return finish_td(xhci, td, event_trb, event, ep, status, true);
1728 }
1729 /*
1730 * Did we transfer any data, despite the errors that might have
1731 * happened? I.e. did we get past the setup stage?
1732 */
1733 if (event_trb != ep_ring->dequeue) {
1734 /* The event was for the status stage */
1735 if (event_trb == td->last_trb) {
1736 if (td->urb->actual_length != 0) {
1737 /* Don't overwrite a previously set error code
1738 */
1739 if ((*status == -EINPROGRESS || *status == 0) &&
1740 (td->urb->transfer_flags
1741 & URB_SHORT_NOT_OK))
1742 /* Did we already see a short data
1743 * stage? */
1744 *status = -EREMOTEIO;
1745 } else {
1746 td->urb->actual_length =
1747 td->urb->transfer_buffer_length;
1748 }
1749 } else {
1750 /* Maybe the event was for the data stage? */
3abeca99
SS
1751 td->urb->actual_length =
1752 td->urb->transfer_buffer_length -
1753 TRB_LEN(le32_to_cpu(event->transfer_len));
1754 xhci_dbg(xhci, "Waiting for status "
1755 "stage event\n");
1756 return 0;
8af56be1
AX
1757 }
1758 }
1759
1760 return finish_td(xhci, td, event_trb, event, ep, status, false);
1761}
1762
04e51901
AX
1763/*
1764 * Process isochronous tds, update urb packet status and actual_length.
1765 */
1766static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1767 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1768 struct xhci_virt_ep *ep, int *status)
1769{
1770 struct xhci_ring *ep_ring;
1771 struct urb_priv *urb_priv;
1772 int idx;
1773 int len = 0;
04e51901
AX
1774 union xhci_trb *cur_trb;
1775 struct xhci_segment *cur_seg;
926008c9 1776 struct usb_iso_packet_descriptor *frame;
04e51901 1777 u32 trb_comp_code;
926008c9 1778 bool skip_td = false;
04e51901 1779
28ccd296
ME
1780 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1781 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
04e51901
AX
1782 urb_priv = td->urb->hcpriv;
1783 idx = urb_priv->td_cnt;
926008c9 1784 frame = &td->urb->iso_frame_desc[idx];
04e51901 1785
926008c9
DT
1786 /* handle completion code */
1787 switch (trb_comp_code) {
1788 case COMP_SUCCESS:
1789 frame->status = 0;
926008c9
DT
1790 break;
1791 case COMP_SHORT_TX:
1792 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
1793 -EREMOTEIO : 0;
1794 break;
1795 case COMP_BW_OVER:
1796 frame->status = -ECOMM;
1797 skip_td = true;
1798 break;
1799 case COMP_BUFF_OVER:
1800 case COMP_BABBLE:
1801 frame->status = -EOVERFLOW;
1802 skip_td = true;
1803 break;
f6ba6fe2 1804 case COMP_DEV_ERR:
926008c9
DT
1805 case COMP_STALL:
1806 frame->status = -EPROTO;
1807 skip_td = true;
1808 break;
1809 case COMP_STOP:
1810 case COMP_STOP_INVAL:
1811 break;
1812 default:
1813 frame->status = -1;
1814 break;
04e51901
AX
1815 }
1816
926008c9
DT
1817 if (trb_comp_code == COMP_SUCCESS || skip_td) {
1818 frame->actual_length = frame->length;
1819 td->urb->actual_length += frame->length;
04e51901
AX
1820 } else {
1821 for (cur_trb = ep_ring->dequeue,
1822 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
1823 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
f5960b69
ME
1824 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1825 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
28ccd296 1826 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
04e51901 1827 }
28ccd296
ME
1828 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1829 TRB_LEN(le32_to_cpu(event->transfer_len));
04e51901
AX
1830
1831 if (trb_comp_code != COMP_STOP_INVAL) {
926008c9 1832 frame->actual_length = len;
04e51901
AX
1833 td->urb->actual_length += len;
1834 }
1835 }
1836
04e51901
AX
1837 return finish_td(xhci, td, event_trb, event, ep, status, false);
1838}
1839
926008c9
DT
1840static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1841 struct xhci_transfer_event *event,
1842 struct xhci_virt_ep *ep, int *status)
1843{
1844 struct xhci_ring *ep_ring;
1845 struct urb_priv *urb_priv;
1846 struct usb_iso_packet_descriptor *frame;
1847 int idx;
1848
f6975314 1849 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
926008c9
DT
1850 urb_priv = td->urb->hcpriv;
1851 idx = urb_priv->td_cnt;
1852 frame = &td->urb->iso_frame_desc[idx];
1853
b3df3f9c 1854 /* The transfer is partly done. */
926008c9
DT
1855 frame->status = -EXDEV;
1856
1857 /* calc actual length */
1858 frame->actual_length = 0;
1859
1860 /* Update ring dequeue pointer */
1861 while (ep_ring->dequeue != td->last_trb)
3b72fca0
AX
1862 inc_deq(xhci, ep_ring);
1863 inc_deq(xhci, ep_ring);
926008c9
DT
1864
1865 return finish_td(xhci, td, NULL, event, ep, status, true);
1866}
1867
22405ed2
AX
1868/*
1869 * Process bulk and interrupt tds, update urb status and actual_length.
1870 */
1871static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1872 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1873 struct xhci_virt_ep *ep, int *status)
1874{
1875 struct xhci_ring *ep_ring;
1876 union xhci_trb *cur_trb;
1877 struct xhci_segment *cur_seg;
1878 u32 trb_comp_code;
1879
28ccd296
ME
1880 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1881 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
22405ed2
AX
1882
1883 switch (trb_comp_code) {
1884 case COMP_SUCCESS:
1885 /* Double check that the HW transferred everything. */
1886 if (event_trb != td->last_trb) {
1887 xhci_warn(xhci, "WARN Successful completion "
1888 "on short TX\n");
1889 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1890 *status = -EREMOTEIO;
1891 else
1892 *status = 0;
1893 } else {
22405ed2
AX
1894 *status = 0;
1895 }
1896 break;
1897 case COMP_SHORT_TX:
1898 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1899 *status = -EREMOTEIO;
1900 else
1901 *status = 0;
1902 break;
1903 default:
1904 /* Others already handled above */
1905 break;
1906 }
f444ff27
SS
1907 if (trb_comp_code == COMP_SHORT_TX)
1908 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
1909 "%d bytes untransferred\n",
1910 td->urb->ep->desc.bEndpointAddress,
1911 td->urb->transfer_buffer_length,
1912 TRB_LEN(le32_to_cpu(event->transfer_len)));
22405ed2
AX
1913 /* Fast path - was this the last TRB in the TD for this URB? */
1914 if (event_trb == td->last_trb) {
28ccd296 1915 if (TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
22405ed2
AX
1916 td->urb->actual_length =
1917 td->urb->transfer_buffer_length -
28ccd296 1918 TRB_LEN(le32_to_cpu(event->transfer_len));
22405ed2
AX
1919 if (td->urb->transfer_buffer_length <
1920 td->urb->actual_length) {
1921 xhci_warn(xhci, "HC gave bad length "
1922 "of %d bytes left\n",
28ccd296 1923 TRB_LEN(le32_to_cpu(event->transfer_len)));
22405ed2
AX
1924 td->urb->actual_length = 0;
1925 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1926 *status = -EREMOTEIO;
1927 else
1928 *status = 0;
1929 }
1930 /* Don't overwrite a previously set error code */
1931 if (*status == -EINPROGRESS) {
1932 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1933 *status = -EREMOTEIO;
1934 else
1935 *status = 0;
1936 }
1937 } else {
1938 td->urb->actual_length =
1939 td->urb->transfer_buffer_length;
1940 /* Ignore a short packet completion if the
1941 * untransferred length was zero.
1942 */
1943 if (*status == -EREMOTEIO)
1944 *status = 0;
1945 }
1946 } else {
1947 /* Slow path - walk the list, starting from the dequeue
1948 * pointer, to get the actual length transferred.
1949 */
1950 td->urb->actual_length = 0;
1951 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1952 cur_trb != event_trb;
1953 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
f5960b69
ME
1954 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1955 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
22405ed2 1956 td->urb->actual_length +=
28ccd296 1957 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
22405ed2
AX
1958 }
1959 /* If the ring didn't stop on a Link or No-op TRB, add
1960 * in the actual bytes transferred from the Normal TRB
1961 */
1962 if (trb_comp_code != COMP_STOP_INVAL)
1963 td->urb->actual_length +=
28ccd296
ME
1964 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1965 TRB_LEN(le32_to_cpu(event->transfer_len));
22405ed2
AX
1966 }
1967
1968 return finish_td(xhci, td, event_trb, event, ep, status, false);
1969}
1970
d0e96f5a
SS
1971/*
1972 * If this function returns an error condition, it means it got a Transfer
1973 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1974 * At this point, the host controller is probably hosed and should be reset.
1975 */
1976static int handle_tx_event(struct xhci_hcd *xhci,
1977 struct xhci_transfer_event *event)
1978{
1979 struct xhci_virt_device *xdev;
63a0d9ab 1980 struct xhci_virt_ep *ep;
d0e96f5a 1981 struct xhci_ring *ep_ring;
82d1009f 1982 unsigned int slot_id;
d0e96f5a 1983 int ep_index;
326b4810 1984 struct xhci_td *td = NULL;
d0e96f5a
SS
1985 dma_addr_t event_dma;
1986 struct xhci_segment *event_seg;
1987 union xhci_trb *event_trb;
326b4810 1988 struct urb *urb = NULL;
d0e96f5a 1989 int status = -EINPROGRESS;
8e51adcc 1990 struct urb_priv *urb_priv;
d115b048 1991 struct xhci_ep_ctx *ep_ctx;
c2d7b49f 1992 struct list_head *tmp;
66d1eebc 1993 u32 trb_comp_code;
4422da61 1994 int ret = 0;
c2d7b49f 1995 int td_num = 0;
d0e96f5a 1996
28ccd296 1997 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
82d1009f 1998 xdev = xhci->devs[slot_id];
d0e96f5a
SS
1999 if (!xdev) {
2000 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
9258c0b2 2001 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
e910b440
SS
2002 (unsigned long long) xhci_trb_virt_to_dma(
2003 xhci->event_ring->deq_seg,
9258c0b2
SS
2004 xhci->event_ring->dequeue),
2005 lower_32_bits(le64_to_cpu(event->buffer)),
2006 upper_32_bits(le64_to_cpu(event->buffer)),
2007 le32_to_cpu(event->transfer_len),
2008 le32_to_cpu(event->flags));
2009 xhci_dbg(xhci, "Event ring:\n");
2010 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
d0e96f5a
SS
2011 return -ENODEV;
2012 }
2013
2014 /* Endpoint ID is 1 based, our index is zero based */
28ccd296 2015 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
63a0d9ab 2016 ep = &xdev->eps[ep_index];
28ccd296 2017 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
d115b048 2018 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
986a92d4 2019 if (!ep_ring ||
28ccd296
ME
2020 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2021 EP_STATE_DISABLED) {
e9df17eb
SS
2022 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2023 "or incorrect stream ring\n");
9258c0b2 2024 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
e910b440
SS
2025 (unsigned long long) xhci_trb_virt_to_dma(
2026 xhci->event_ring->deq_seg,
9258c0b2
SS
2027 xhci->event_ring->dequeue),
2028 lower_32_bits(le64_to_cpu(event->buffer)),
2029 upper_32_bits(le64_to_cpu(event->buffer)),
2030 le32_to_cpu(event->transfer_len),
2031 le32_to_cpu(event->flags));
2032 xhci_dbg(xhci, "Event ring:\n");
2033 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
d0e96f5a
SS
2034 return -ENODEV;
2035 }
2036
c2d7b49f
AX
2037 /* Count current td numbers if ep->skip is set */
2038 if (ep->skip) {
2039 list_for_each(tmp, &ep_ring->td_list)
2040 td_num++;
2041 }
2042
28ccd296
ME
2043 event_dma = le64_to_cpu(event->buffer);
2044 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
986a92d4 2045 /* Look for common error cases */
66d1eebc 2046 switch (trb_comp_code) {
b10de142
SS
2047 /* Skip codes that require special handling depending on
2048 * transfer type
2049 */
2050 case COMP_SUCCESS:
2051 case COMP_SHORT_TX:
2052 break;
ae636747
SS
2053 case COMP_STOP:
2054 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2055 break;
2056 case COMP_STOP_INVAL:
2057 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2058 break;
b10de142 2059 case COMP_STALL:
2a9227a5 2060 xhci_dbg(xhci, "Stalled endpoint\n");
63a0d9ab 2061 ep->ep_state |= EP_HALTED;
b10de142
SS
2062 status = -EPIPE;
2063 break;
2064 case COMP_TRB_ERR:
2065 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2066 status = -EILSEQ;
2067 break;
ec74e403 2068 case COMP_SPLIT_ERR:
b10de142 2069 case COMP_TX_ERR:
2a9227a5 2070 xhci_dbg(xhci, "Transfer error on endpoint\n");
b10de142
SS
2071 status = -EPROTO;
2072 break;
4a73143c 2073 case COMP_BABBLE:
2a9227a5 2074 xhci_dbg(xhci, "Babble error on endpoint\n");
4a73143c
SS
2075 status = -EOVERFLOW;
2076 break;
b10de142
SS
2077 case COMP_DB_ERR:
2078 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2079 status = -ENOSR;
2080 break;
986a92d4
AX
2081 case COMP_BW_OVER:
2082 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2083 break;
2084 case COMP_BUFF_OVER:
2085 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2086 break;
2087 case COMP_UNDERRUN:
2088 /*
2089 * When the Isoch ring is empty, the xHC will generate
2090 * a Ring Overrun Event for IN Isoch endpoint or Ring
2091 * Underrun Event for OUT Isoch endpoint.
2092 */
2093 xhci_dbg(xhci, "underrun event on endpoint\n");
2094 if (!list_empty(&ep_ring->td_list))
2095 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2096 "still with TDs queued?\n",
28ccd296
ME
2097 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2098 ep_index);
986a92d4
AX
2099 goto cleanup;
2100 case COMP_OVERRUN:
2101 xhci_dbg(xhci, "overrun event on endpoint\n");
2102 if (!list_empty(&ep_ring->td_list))
2103 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2104 "still with TDs queued?\n",
28ccd296
ME
2105 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2106 ep_index);
986a92d4 2107 goto cleanup;
f6ba6fe2
AH
2108 case COMP_DEV_ERR:
2109 xhci_warn(xhci, "WARN: detect an incompatible device");
2110 status = -EPROTO;
2111 break;
d18240db
AX
2112 case COMP_MISSED_INT:
2113 /*
2114 * When encounter missed service error, one or more isoc tds
2115 * may be missed by xHC.
2116 * Set skip flag of the ep_ring; Complete the missed tds as
2117 * short transfer when process the ep_ring next time.
2118 */
2119 ep->skip = true;
2120 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2121 goto cleanup;
b10de142 2122 default:
b45b5069 2123 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
5ad6a529
SS
2124 status = 0;
2125 break;
2126 }
986a92d4
AX
2127 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2128 "busted\n");
2129 goto cleanup;
2130 }
2131
d18240db
AX
2132 do {
2133 /* This TRB should be in the TD at the head of this ring's
2134 * TD list.
2135 */
2136 if (list_empty(&ep_ring->td_list)) {
2137 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
2138 "with no TDs queued?\n",
28ccd296
ME
2139 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2140 ep_index);
d18240db 2141 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
f5960b69
ME
2142 (le32_to_cpu(event->flags) &
2143 TRB_TYPE_BITMASK)>>10);
d18240db
AX
2144 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2145 if (ep->skip) {
2146 ep->skip = false;
2147 xhci_dbg(xhci, "td_list is empty while skip "
2148 "flag set. Clear skip flag.\n");
2149 }
2150 ret = 0;
2151 goto cleanup;
2152 }
986a92d4 2153
c2d7b49f
AX
2154 /* We've skipped all the TDs on the ep ring when ep->skip set */
2155 if (ep->skip && td_num == 0) {
2156 ep->skip = false;
2157 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2158 "Clear skip flag.\n");
2159 ret = 0;
2160 goto cleanup;
2161 }
2162
d18240db 2163 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
c2d7b49f
AX
2164 if (ep->skip)
2165 td_num--;
926008c9 2166
d18240db
AX
2167 /* Is this a TRB in the currently executing TD? */
2168 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2169 td->last_trb, event_dma);
e1cf486d
AH
2170
2171 /*
2172 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2173 * is not in the current TD pointed by ep_ring->dequeue because
2174 * that the hardware dequeue pointer still at the previous TRB
2175 * of the current TD. The previous TRB maybe a Link TD or the
2176 * last TRB of the previous TD. The command completion handle
2177 * will take care the rest.
2178 */
2179 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2180 ret = 0;
2181 goto cleanup;
2182 }
2183
926008c9
DT
2184 if (!event_seg) {
2185 if (!ep->skip ||
2186 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
ad808333
SS
2187 /* Some host controllers give a spurious
2188 * successful event after a short transfer.
2189 * Ignore it.
2190 */
2191 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2192 ep_ring->last_td_was_short) {
2193 ep_ring->last_td_was_short = false;
2194 ret = 0;
2195 goto cleanup;
2196 }
926008c9
DT
2197 /* HC is busted, give up! */
2198 xhci_err(xhci,
2199 "ERROR Transfer event TRB DMA ptr not "
2200 "part of current TD\n");
2201 return -ESHUTDOWN;
2202 }
2203
2204 ret = skip_isoc_td(xhci, td, event, ep, &status);
2205 goto cleanup;
2206 }
ad808333
SS
2207 if (trb_comp_code == COMP_SHORT_TX)
2208 ep_ring->last_td_was_short = true;
2209 else
2210 ep_ring->last_td_was_short = false;
926008c9
DT
2211
2212 if (ep->skip) {
d18240db
AX
2213 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2214 ep->skip = false;
2215 }
678539cf 2216
926008c9
DT
2217 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2218 sizeof(*event_trb)];
2219 /*
2220 * No-op TRB should not trigger interrupts.
2221 * If event_trb is a no-op TRB, it means the
2222 * corresponding TD has been cancelled. Just ignore
2223 * the TD.
2224 */
f5960b69 2225 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
926008c9
DT
2226 xhci_dbg(xhci,
2227 "event_trb is a no-op TRB. Skip it\n");
2228 goto cleanup;
d18240db 2229 }
4422da61 2230
d18240db
AX
2231 /* Now update the urb's actual_length and give back to
2232 * the core
82d1009f 2233 */
d18240db
AX
2234 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2235 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2236 &status);
04e51901
AX
2237 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2238 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2239 &status);
d18240db
AX
2240 else
2241 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2242 ep, &status);
2243
2244cleanup:
2245 /*
2246 * Do not update event ring dequeue pointer if ep->skip is set.
2247 * Will roll back to continue process missed tds.
2248 */
2249 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
3b72fca0 2250 inc_deq(xhci, xhci->event_ring);
d18240db
AX
2251 }
2252
2253 if (ret) {
2254 urb = td->urb;
8e51adcc 2255 urb_priv = urb->hcpriv;
d18240db
AX
2256 /* Leave the TD around for the reset endpoint function
2257 * to use(but only if it's not a control endpoint,
2258 * since we already queued the Set TR dequeue pointer
2259 * command for stalled control endpoints).
2260 */
2261 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2262 (trb_comp_code != COMP_STALL &&
2263 trb_comp_code != COMP_BABBLE))
8e51adcc 2264 xhci_urb_free_priv(xhci, urb_priv);
d18240db 2265
214f76f7 2266 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
f444ff27
SS
2267 if ((urb->actual_length != urb->transfer_buffer_length &&
2268 (urb->transfer_flags &
2269 URB_SHORT_NOT_OK)) ||
fd984d24
SS
2270 (status != 0 &&
2271 !usb_endpoint_xfer_isoc(&urb->ep->desc)))
f444ff27
SS
2272 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2273 "expected = %x, status = %d\n",
2274 urb, urb->actual_length,
2275 urb->transfer_buffer_length,
2276 status);
d18240db 2277 spin_unlock(&xhci->lock);
b3df3f9c
SS
2278 /* EHCI, UHCI, and OHCI always unconditionally set the
2279 * urb->status of an isochronous endpoint to 0.
2280 */
2281 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2282 status = 0;
214f76f7 2283 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
d18240db
AX
2284 spin_lock(&xhci->lock);
2285 }
2286
2287 /*
2288 * If ep->skip is set, it means there are missed tds on the
2289 * endpoint ring need to take care of.
2290 * Process them as short transfer until reach the td pointed by
2291 * the event.
2292 */
2293 } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2294
d0e96f5a
SS
2295 return 0;
2296}
2297
0f2a7930
SS
2298/*
2299 * This function handles all OS-owned events on the event ring. It may drop
2300 * xhci->lock between event processing (e.g. to pass up port status changes).
9dee9a21
ME
2301 * Returns >0 for "possibly more events to process" (caller should call again),
2302 * otherwise 0 if done. In future, <0 returns should indicate error code.
0f2a7930 2303 */
9dee9a21 2304static int xhci_handle_event(struct xhci_hcd *xhci)
7f84eef0
SS
2305{
2306 union xhci_trb *event;
0f2a7930 2307 int update_ptrs = 1;
d0e96f5a 2308 int ret;
7f84eef0
SS
2309
2310 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2311 xhci->error_bitmask |= 1 << 1;
9dee9a21 2312 return 0;
7f84eef0
SS
2313 }
2314
2315 event = xhci->event_ring->dequeue;
2316 /* Does the HC or OS own the TRB? */
28ccd296
ME
2317 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2318 xhci->event_ring->cycle_state) {
7f84eef0 2319 xhci->error_bitmask |= 1 << 2;
9dee9a21 2320 return 0;
7f84eef0
SS
2321 }
2322
92a3da41
ME
2323 /*
2324 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2325 * speculative reads of the event's flags/data below.
2326 */
2327 rmb();
0f2a7930 2328 /* FIXME: Handle more event types. */
28ccd296 2329 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
7f84eef0
SS
2330 case TRB_TYPE(TRB_COMPLETION):
2331 handle_cmd_completion(xhci, &event->event_cmd);
2332 break;
0f2a7930
SS
2333 case TRB_TYPE(TRB_PORT_STATUS):
2334 handle_port_status(xhci, event);
2335 update_ptrs = 0;
2336 break;
d0e96f5a
SS
2337 case TRB_TYPE(TRB_TRANSFER):
2338 ret = handle_tx_event(xhci, &event->trans_event);
2339 if (ret < 0)
2340 xhci->error_bitmask |= 1 << 9;
2341 else
2342 update_ptrs = 0;
2343 break;
623bef9e
SS
2344 case TRB_TYPE(TRB_DEV_NOTE):
2345 handle_device_notification(xhci, event);
2346 break;
7f84eef0 2347 default:
28ccd296
ME
2348 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2349 TRB_TYPE(48))
0238634d
SS
2350 handle_vendor_event(xhci, event);
2351 else
2352 xhci->error_bitmask |= 1 << 3;
7f84eef0 2353 }
6f5165cf
SS
2354 /* Any of the above functions may drop and re-acquire the lock, so check
2355 * to make sure a watchdog timer didn't mark the host as non-responsive.
2356 */
2357 if (xhci->xhc_state & XHCI_STATE_DYING) {
2358 xhci_dbg(xhci, "xHCI host dying, returning from "
2359 "event handler.\n");
9dee9a21 2360 return 0;
6f5165cf 2361 }
7f84eef0 2362
c06d68b8
SS
2363 if (update_ptrs)
2364 /* Update SW event ring dequeue pointer */
3b72fca0 2365 inc_deq(xhci, xhci->event_ring);
c06d68b8 2366
9dee9a21
ME
2367 /* Are there more items on the event ring? Caller will call us again to
2368 * check.
2369 */
2370 return 1;
7f84eef0 2371}
9032cd52
SS
2372
2373/*
2374 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2375 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2376 * indicators of an event TRB error, but we check the status *first* to be safe.
2377 */
2378irqreturn_t xhci_irq(struct usb_hcd *hcd)
2379{
2380 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
c21599a3 2381 u32 status;
9032cd52 2382 union xhci_trb *trb;
bda53145 2383 u64 temp_64;
c06d68b8
SS
2384 union xhci_trb *event_ring_deq;
2385 dma_addr_t deq;
9032cd52
SS
2386
2387 spin_lock(&xhci->lock);
2388 trb = xhci->event_ring->dequeue;
2389 /* Check if the xHC generated the interrupt, or the irq is shared */
27e0dd4d 2390 status = xhci_readl(xhci, &xhci->op_regs->status);
c21599a3 2391 if (status == 0xffffffff)
9032cd52
SS
2392 goto hw_died;
2393
c21599a3 2394 if (!(status & STS_EINT)) {
9032cd52 2395 spin_unlock(&xhci->lock);
9032cd52
SS
2396 return IRQ_NONE;
2397 }
27e0dd4d 2398 if (status & STS_FATAL) {
9032cd52
SS
2399 xhci_warn(xhci, "WARNING: Host System Error\n");
2400 xhci_halt(xhci);
2401hw_died:
9032cd52
SS
2402 spin_unlock(&xhci->lock);
2403 return -ESHUTDOWN;
2404 }
2405
bda53145
SS
2406 /*
2407 * Clear the op reg interrupt status first,
2408 * so we can receive interrupts from other MSI-X interrupters.
2409 * Write 1 to clear the interrupt status.
2410 */
27e0dd4d
SS
2411 status |= STS_EINT;
2412 xhci_writel(xhci, status, &xhci->op_regs->status);
bda53145
SS
2413 /* FIXME when MSI-X is supported and there are multiple vectors */
2414 /* Clear the MSI-X event interrupt status */
2415
cd70469d 2416 if (hcd->irq) {
c21599a3
SS
2417 u32 irq_pending;
2418 /* Acknowledge the PCI interrupt */
2419 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
4e833c0b 2420 irq_pending |= IMAN_IP;
c21599a3
SS
2421 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2422 }
bda53145 2423
c06d68b8 2424 if (xhci->xhc_state & XHCI_STATE_DYING) {
bda53145
SS
2425 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2426 "Shouldn't IRQs be disabled?\n");
c06d68b8
SS
2427 /* Clear the event handler busy flag (RW1C);
2428 * the event ring should be empty.
bda53145 2429 */
c06d68b8
SS
2430 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2431 xhci_write_64(xhci, temp_64 | ERST_EHB,
2432 &xhci->ir_set->erst_dequeue);
2433 spin_unlock(&xhci->lock);
2434
2435 return IRQ_HANDLED;
2436 }
2437
2438 event_ring_deq = xhci->event_ring->dequeue;
2439 /* FIXME this should be a delayed service routine
2440 * that clears the EHB.
2441 */
9dee9a21 2442 while (xhci_handle_event(xhci) > 0) {}
bda53145 2443
bda53145 2444 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
c06d68b8
SS
2445 /* If necessary, update the HW's version of the event ring deq ptr. */
2446 if (event_ring_deq != xhci->event_ring->dequeue) {
2447 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2448 xhci->event_ring->dequeue);
2449 if (deq == 0)
2450 xhci_warn(xhci, "WARN something wrong with SW event "
2451 "ring dequeue ptr.\n");
2452 /* Update HC event ring dequeue pointer */
2453 temp_64 &= ERST_PTR_MASK;
2454 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2455 }
2456
2457 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2458 temp_64 |= ERST_EHB;
2459 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2460
9032cd52
SS
2461 spin_unlock(&xhci->lock);
2462
2463 return IRQ_HANDLED;
2464}
2465
2466irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2467{
968b822c 2468 return xhci_irq(hcd);
9032cd52 2469}
7f84eef0 2470
d0e96f5a
SS
2471/**** Endpoint Ring Operations ****/
2472
7f84eef0
SS
2473/*
2474 * Generic function for queueing a TRB on a ring.
2475 * The caller must have checked to make sure there's room on the ring.
6cc30d85
SS
2476 *
2477 * @more_trbs_coming: Will you enqueue more TRBs before calling
2478 * prepare_transfer()?
7f84eef0
SS
2479 */
2480static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
3b72fca0 2481 bool more_trbs_coming,
7f84eef0
SS
2482 u32 field1, u32 field2, u32 field3, u32 field4)
2483{
2484 struct xhci_generic_trb *trb;
2485
2486 trb = &ring->enqueue->generic;
28ccd296
ME
2487 trb->field[0] = cpu_to_le32(field1);
2488 trb->field[1] = cpu_to_le32(field2);
2489 trb->field[2] = cpu_to_le32(field3);
2490 trb->field[3] = cpu_to_le32(field4);
3b72fca0 2491 inc_enq(xhci, ring, more_trbs_coming);
7f84eef0
SS
2492}
2493
d0e96f5a
SS
2494/*
2495 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2496 * FIXME allocate segments if the ring is full.
2497 */
2498static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
3b72fca0 2499 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
d0e96f5a 2500{
8dfec614
AX
2501 unsigned int num_trbs_needed;
2502
d0e96f5a 2503 /* Make sure the endpoint has been added to xHC schedule */
d0e96f5a
SS
2504 switch (ep_state) {
2505 case EP_STATE_DISABLED:
2506 /*
2507 * USB core changed config/interfaces without notifying us,
2508 * or hardware is reporting the wrong state.
2509 */
2510 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2511 return -ENOENT;
d0e96f5a 2512 case EP_STATE_ERROR:
c92bcfa7 2513 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
d0e96f5a
SS
2514 /* FIXME event handling code for error needs to clear it */
2515 /* XXX not sure if this should be -ENOENT or not */
2516 return -EINVAL;
c92bcfa7
SS
2517 case EP_STATE_HALTED:
2518 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
d0e96f5a
SS
2519 case EP_STATE_STOPPED:
2520 case EP_STATE_RUNNING:
2521 break;
2522 default:
2523 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2524 /*
2525 * FIXME issue Configure Endpoint command to try to get the HC
2526 * back into a known state.
2527 */
2528 return -EINVAL;
2529 }
8dfec614
AX
2530
2531 while (1) {
2532 if (room_on_ring(xhci, ep_ring, num_trbs))
2533 break;
2534
2535 if (ep_ring == xhci->cmd_ring) {
2536 xhci_err(xhci, "Do not support expand command ring\n");
2537 return -ENOMEM;
2538 }
2539
8dfec614
AX
2540 xhci_dbg(xhci, "ERROR no room on ep ring, "
2541 "try ring expansion\n");
2542 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2543 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2544 mem_flags)) {
2545 xhci_err(xhci, "Ring expansion failed\n");
2546 return -ENOMEM;
2547 }
2548 };
6c12db90
JY
2549
2550 if (enqueue_is_link_trb(ep_ring)) {
2551 struct xhci_ring *ring = ep_ring;
2552 union xhci_trb *next;
6c12db90 2553
6c12db90
JY
2554 next = ring->enqueue;
2555
2556 while (last_trb(xhci, ring, ring->enq_seg, next)) {
7e393a83
AX
2557 /* If we're not dealing with 0.95 hardware or isoc rings
2558 * on AMD 0.96 host, clear the chain bit.
6c12db90 2559 */
3b72fca0
AX
2560 if (!xhci_link_trb_quirk(xhci) &&
2561 !(ring->type == TYPE_ISOC &&
2562 (xhci->quirks & XHCI_AMD_0x96_HOST)))
28ccd296 2563 next->link.control &= cpu_to_le32(~TRB_CHAIN);
6c12db90 2564 else
28ccd296 2565 next->link.control |= cpu_to_le32(TRB_CHAIN);
6c12db90
JY
2566
2567 wmb();
f5960b69 2568 next->link.control ^= cpu_to_le32(TRB_CYCLE);
6c12db90
JY
2569
2570 /* Toggle the cycle bit after the last ring segment. */
2571 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2572 ring->cycle_state = (ring->cycle_state ? 0 : 1);
6c12db90
JY
2573 }
2574 ring->enq_seg = ring->enq_seg->next;
2575 ring->enqueue = ring->enq_seg->trbs;
2576 next = ring->enqueue;
2577 }
2578 }
2579
d0e96f5a
SS
2580 return 0;
2581}
2582
23e3be11 2583static int prepare_transfer(struct xhci_hcd *xhci,
d0e96f5a
SS
2584 struct xhci_virt_device *xdev,
2585 unsigned int ep_index,
e9df17eb 2586 unsigned int stream_id,
d0e96f5a
SS
2587 unsigned int num_trbs,
2588 struct urb *urb,
8e51adcc 2589 unsigned int td_index,
d0e96f5a
SS
2590 gfp_t mem_flags)
2591{
2592 int ret;
8e51adcc
AX
2593 struct urb_priv *urb_priv;
2594 struct xhci_td *td;
e9df17eb 2595 struct xhci_ring *ep_ring;
d115b048 2596 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
e9df17eb
SS
2597
2598 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2599 if (!ep_ring) {
2600 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2601 stream_id);
2602 return -EINVAL;
2603 }
2604
2605 ret = prepare_ring(xhci, ep_ring,
28ccd296 2606 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3b72fca0 2607 num_trbs, mem_flags);
d0e96f5a
SS
2608 if (ret)
2609 return ret;
d0e96f5a 2610
8e51adcc
AX
2611 urb_priv = urb->hcpriv;
2612 td = urb_priv->td[td_index];
2613
2614 INIT_LIST_HEAD(&td->td_list);
2615 INIT_LIST_HEAD(&td->cancelled_td_list);
2616
2617 if (td_index == 0) {
214f76f7 2618 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
d13565c1 2619 if (unlikely(ret))
8e51adcc 2620 return ret;
d0e96f5a
SS
2621 }
2622
8e51adcc 2623 td->urb = urb;
d0e96f5a 2624 /* Add this TD to the tail of the endpoint ring's TD list */
8e51adcc
AX
2625 list_add_tail(&td->td_list, &ep_ring->td_list);
2626 td->start_seg = ep_ring->enq_seg;
2627 td->first_trb = ep_ring->enqueue;
2628
2629 urb_priv->td[td_index] = td;
d0e96f5a
SS
2630
2631 return 0;
2632}
2633
23e3be11 2634static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
8a96c052
SS
2635{
2636 int num_sgs, num_trbs, running_total, temp, i;
2637 struct scatterlist *sg;
2638
2639 sg = NULL;
bc677d5b 2640 num_sgs = urb->num_mapped_sgs;
8a96c052
SS
2641 temp = urb->transfer_buffer_length;
2642
8a96c052 2643 num_trbs = 0;
910f8d0c 2644 for_each_sg(urb->sg, sg, num_sgs, i) {
8a96c052
SS
2645 unsigned int len = sg_dma_len(sg);
2646
2647 /* Scatter gather list entries may cross 64KB boundaries */
2648 running_total = TRB_MAX_BUFF_SIZE -
a2490187 2649 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
5807795b 2650 running_total &= TRB_MAX_BUFF_SIZE - 1;
8a96c052
SS
2651 if (running_total != 0)
2652 num_trbs++;
2653
2654 /* How many more 64KB chunks to transfer, how many more TRBs? */
bcd2fde0 2655 while (running_total < sg_dma_len(sg) && running_total < temp) {
8a96c052
SS
2656 num_trbs++;
2657 running_total += TRB_MAX_BUFF_SIZE;
2658 }
8a96c052
SS
2659 len = min_t(int, len, temp);
2660 temp -= len;
2661 if (temp == 0)
2662 break;
2663 }
8a96c052
SS
2664 return num_trbs;
2665}
2666
23e3be11 2667static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
8a96c052
SS
2668{
2669 if (num_trbs != 0)
a2490187 2670 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
8a96c052
SS
2671 "TRBs, %d left\n", __func__,
2672 urb->ep->desc.bEndpointAddress, num_trbs);
2673 if (running_total != urb->transfer_buffer_length)
a2490187 2674 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
8a96c052
SS
2675 "queued %#x (%d), asked for %#x (%d)\n",
2676 __func__,
2677 urb->ep->desc.bEndpointAddress,
2678 running_total, running_total,
2679 urb->transfer_buffer_length,
2680 urb->transfer_buffer_length);
2681}
2682
23e3be11 2683static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
e9df17eb 2684 unsigned int ep_index, unsigned int stream_id, int start_cycle,
e1eab2e0 2685 struct xhci_generic_trb *start_trb)
8a96c052 2686{
8a96c052
SS
2687 /*
2688 * Pass all the TRBs to the hardware at once and make sure this write
2689 * isn't reordered.
2690 */
2691 wmb();
50f7b52a 2692 if (start_cycle)
28ccd296 2693 start_trb->field[3] |= cpu_to_le32(start_cycle);
50f7b52a 2694 else
28ccd296 2695 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
be88fe4f 2696 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
8a96c052
SS
2697}
2698
624defa1
SS
2699/*
2700 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
2701 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
2702 * (comprised of sg list entries) can take several service intervals to
2703 * transmit.
2704 */
2705int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2706 struct urb *urb, int slot_id, unsigned int ep_index)
2707{
2708 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2709 xhci->devs[slot_id]->out_ctx, ep_index);
2710 int xhci_interval;
2711 int ep_interval;
2712
28ccd296 2713 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
624defa1
SS
2714 ep_interval = urb->interval;
2715 /* Convert to microframes */
2716 if (urb->dev->speed == USB_SPEED_LOW ||
2717 urb->dev->speed == USB_SPEED_FULL)
2718 ep_interval *= 8;
2719 /* FIXME change this to a warning and a suggestion to use the new API
2720 * to set the polling interval (once the API is added).
2721 */
2722 if (xhci_interval != ep_interval) {
7961acd7 2723 if (printk_ratelimit())
624defa1
SS
2724 dev_dbg(&urb->dev->dev, "Driver uses different interval"
2725 " (%d microframe%s) than xHCI "
2726 "(%d microframe%s)\n",
2727 ep_interval,
2728 ep_interval == 1 ? "" : "s",
2729 xhci_interval,
2730 xhci_interval == 1 ? "" : "s");
2731 urb->interval = xhci_interval;
2732 /* Convert back to frames for LS/FS devices */
2733 if (urb->dev->speed == USB_SPEED_LOW ||
2734 urb->dev->speed == USB_SPEED_FULL)
2735 urb->interval /= 8;
2736 }
2737 return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2738}
2739
04dd950d
SS
2740/*
2741 * The TD size is the number of bytes remaining in the TD (including this TRB),
2742 * right shifted by 10.
2743 * It must fit in bits 21:17, so it can't be bigger than 31.
2744 */
2745static u32 xhci_td_remainder(unsigned int remainder)
2746{
2747 u32 max = (1 << (21 - 17 + 1)) - 1;
2748
2749 if ((remainder >> 10) >= max)
2750 return max << 17;
2751 else
2752 return (remainder >> 10) << 17;
2753}
2754
4da6e6f2
SS
2755/*
2756 * For xHCI 1.0 host controllers, TD size is the number of packets remaining in
2757 * the TD (*not* including this TRB).
2758 *
2759 * Total TD packet count = total_packet_count =
2760 * roundup(TD size in bytes / wMaxPacketSize)
2761 *
2762 * Packets transferred up to and including this TRB = packets_transferred =
2763 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
2764 *
2765 * TD size = total_packet_count - packets_transferred
2766 *
2767 * It must fit in bits 21:17, so it can't be bigger than 31.
2768 */
2769
2770static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
2771 unsigned int total_packet_count, struct urb *urb)
2772{
2773 int packets_transferred;
2774
48df4a6f
SS
2775 /* One TRB with a zero-length data packet. */
2776 if (running_total == 0 && trb_buff_len == 0)
2777 return 0;
2778
4da6e6f2
SS
2779 /* All the TRB queueing functions don't count the current TRB in
2780 * running_total.
2781 */
2782 packets_transferred = (running_total + trb_buff_len) /
29cc8897 2783 usb_endpoint_maxp(&urb->ep->desc);
4da6e6f2
SS
2784
2785 return xhci_td_remainder(total_packet_count - packets_transferred);
2786}
2787
23e3be11 2788static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
8a96c052
SS
2789 struct urb *urb, int slot_id, unsigned int ep_index)
2790{
2791 struct xhci_ring *ep_ring;
2792 unsigned int num_trbs;
8e51adcc 2793 struct urb_priv *urb_priv;
8a96c052
SS
2794 struct xhci_td *td;
2795 struct scatterlist *sg;
2796 int num_sgs;
2797 int trb_buff_len, this_sg_len, running_total;
4da6e6f2 2798 unsigned int total_packet_count;
8a96c052
SS
2799 bool first_trb;
2800 u64 addr;
6cc30d85 2801 bool more_trbs_coming;
8a96c052
SS
2802
2803 struct xhci_generic_trb *start_trb;
2804 int start_cycle;
2805
e9df17eb
SS
2806 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2807 if (!ep_ring)
2808 return -EINVAL;
2809
8a96c052 2810 num_trbs = count_sg_trbs_needed(xhci, urb);
bc677d5b 2811 num_sgs = urb->num_mapped_sgs;
4da6e6f2 2812 total_packet_count = roundup(urb->transfer_buffer_length,
29cc8897 2813 usb_endpoint_maxp(&urb->ep->desc));
8a96c052 2814
23e3be11 2815 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
e9df17eb 2816 ep_index, urb->stream_id,
3b72fca0 2817 num_trbs, urb, 0, mem_flags);
8a96c052
SS
2818 if (trb_buff_len < 0)
2819 return trb_buff_len;
8e51adcc
AX
2820
2821 urb_priv = urb->hcpriv;
2822 td = urb_priv->td[0];
2823
8a96c052
SS
2824 /*
2825 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2826 * until we've finished creating all the other TRBs. The ring's cycle
2827 * state may change as we enqueue the other TRBs, so save it too.
2828 */
2829 start_trb = &ep_ring->enqueue->generic;
2830 start_cycle = ep_ring->cycle_state;
2831
2832 running_total = 0;
2833 /*
2834 * How much data is in the first TRB?
2835 *
2836 * There are three forces at work for TRB buffer pointers and lengths:
2837 * 1. We don't want to walk off the end of this sg-list entry buffer.
2838 * 2. The transfer length that the driver requested may be smaller than
2839 * the amount of memory allocated for this scatter-gather list.
2840 * 3. TRBs buffers can't cross 64KB boundaries.
2841 */
910f8d0c 2842 sg = urb->sg;
8a96c052
SS
2843 addr = (u64) sg_dma_address(sg);
2844 this_sg_len = sg_dma_len(sg);
a2490187 2845 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
8a96c052
SS
2846 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2847 if (trb_buff_len > urb->transfer_buffer_length)
2848 trb_buff_len = urb->transfer_buffer_length;
8a96c052
SS
2849
2850 first_trb = true;
2851 /* Queue the first TRB, even if it's zero-length */
2852 do {
2853 u32 field = 0;
f9dc68fe 2854 u32 length_field = 0;
04dd950d 2855 u32 remainder = 0;
8a96c052
SS
2856
2857 /* Don't change the cycle bit of the first TRB until later */
50f7b52a 2858 if (first_trb) {
8a96c052 2859 first_trb = false;
50f7b52a
AX
2860 if (start_cycle == 0)
2861 field |= 0x1;
2862 } else
8a96c052
SS
2863 field |= ep_ring->cycle_state;
2864
2865 /* Chain all the TRBs together; clear the chain bit in the last
2866 * TRB to indicate it's the last TRB in the chain.
2867 */
2868 if (num_trbs > 1) {
2869 field |= TRB_CHAIN;
2870 } else {
2871 /* FIXME - add check for ZERO_PACKET flag before this */
2872 td->last_trb = ep_ring->enqueue;
2873 field |= TRB_IOC;
2874 }
af8b9e63
SS
2875
2876 /* Only set interrupt on short packet for IN endpoints */
2877 if (usb_urb_dir_in(urb))
2878 field |= TRB_ISP;
2879
8a96c052 2880 if (TRB_MAX_BUFF_SIZE -
a2490187 2881 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
8a96c052
SS
2882 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2883 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2884 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2885 (unsigned int) addr + trb_buff_len);
2886 }
4da6e6f2
SS
2887
2888 /* Set the TRB length, TD size, and interrupter fields. */
2889 if (xhci->hci_version < 0x100) {
2890 remainder = xhci_td_remainder(
2891 urb->transfer_buffer_length -
2892 running_total);
2893 } else {
2894 remainder = xhci_v1_0_td_remainder(running_total,
2895 trb_buff_len, total_packet_count, urb);
2896 }
f9dc68fe 2897 length_field = TRB_LEN(trb_buff_len) |
04dd950d 2898 remainder |
f9dc68fe 2899 TRB_INTR_TARGET(0);
4da6e6f2 2900
6cc30d85
SS
2901 if (num_trbs > 1)
2902 more_trbs_coming = true;
2903 else
2904 more_trbs_coming = false;
3b72fca0 2905 queue_trb(xhci, ep_ring, more_trbs_coming,
8e595a5d
SS
2906 lower_32_bits(addr),
2907 upper_32_bits(addr),
f9dc68fe 2908 length_field,
af8b9e63 2909 field | TRB_TYPE(TRB_NORMAL));
8a96c052
SS
2910 --num_trbs;
2911 running_total += trb_buff_len;
2912
2913 /* Calculate length for next transfer --
2914 * Are we done queueing all the TRBs for this sg entry?
2915 */
2916 this_sg_len -= trb_buff_len;
2917 if (this_sg_len == 0) {
2918 --num_sgs;
2919 if (num_sgs == 0)
2920 break;
2921 sg = sg_next(sg);
2922 addr = (u64) sg_dma_address(sg);
2923 this_sg_len = sg_dma_len(sg);
2924 } else {
2925 addr += trb_buff_len;
2926 }
2927
2928 trb_buff_len = TRB_MAX_BUFF_SIZE -
a2490187 2929 (addr & (TRB_MAX_BUFF_SIZE - 1));
8a96c052
SS
2930 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2931 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2932 trb_buff_len =
2933 urb->transfer_buffer_length - running_total;
2934 } while (running_total < urb->transfer_buffer_length);
2935
2936 check_trb_math(urb, num_trbs, running_total);
e9df17eb 2937 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
e1eab2e0 2938 start_cycle, start_trb);
8a96c052
SS
2939 return 0;
2940}
2941
b10de142 2942/* This is very similar to what ehci-q.c qtd_fill() does */
23e3be11 2943int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
b10de142
SS
2944 struct urb *urb, int slot_id, unsigned int ep_index)
2945{
2946 struct xhci_ring *ep_ring;
8e51adcc 2947 struct urb_priv *urb_priv;
b10de142
SS
2948 struct xhci_td *td;
2949 int num_trbs;
2950 struct xhci_generic_trb *start_trb;
2951 bool first_trb;
6cc30d85 2952 bool more_trbs_coming;
b10de142 2953 int start_cycle;
f9dc68fe 2954 u32 field, length_field;
b10de142
SS
2955
2956 int running_total, trb_buff_len, ret;
4da6e6f2 2957 unsigned int total_packet_count;
b10de142
SS
2958 u64 addr;
2959
ff9c895f 2960 if (urb->num_sgs)
8a96c052
SS
2961 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2962
e9df17eb
SS
2963 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2964 if (!ep_ring)
2965 return -EINVAL;
b10de142
SS
2966
2967 num_trbs = 0;
2968 /* How much data is (potentially) left before the 64KB boundary? */
2969 running_total = TRB_MAX_BUFF_SIZE -
a2490187 2970 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
5807795b 2971 running_total &= TRB_MAX_BUFF_SIZE - 1;
b10de142
SS
2972
2973 /* If there's some data on this 64KB chunk, or we have to send a
2974 * zero-length transfer, we need at least one TRB
2975 */
2976 if (running_total != 0 || urb->transfer_buffer_length == 0)
2977 num_trbs++;
2978 /* How many more 64KB chunks to transfer, how many more TRBs? */
2979 while (running_total < urb->transfer_buffer_length) {
2980 num_trbs++;
2981 running_total += TRB_MAX_BUFF_SIZE;
2982 }
2983 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2984
e9df17eb
SS
2985 ret = prepare_transfer(xhci, xhci->devs[slot_id],
2986 ep_index, urb->stream_id,
3b72fca0 2987 num_trbs, urb, 0, mem_flags);
b10de142
SS
2988 if (ret < 0)
2989 return ret;
2990
8e51adcc
AX
2991 urb_priv = urb->hcpriv;
2992 td = urb_priv->td[0];
2993
b10de142
SS
2994 /*
2995 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2996 * until we've finished creating all the other TRBs. The ring's cycle
2997 * state may change as we enqueue the other TRBs, so save it too.
2998 */
2999 start_trb = &ep_ring->enqueue->generic;
3000 start_cycle = ep_ring->cycle_state;
3001
3002 running_total = 0;
4da6e6f2 3003 total_packet_count = roundup(urb->transfer_buffer_length,
29cc8897 3004 usb_endpoint_maxp(&urb->ep->desc));
b10de142
SS
3005 /* How much data is in the first TRB? */
3006 addr = (u64) urb->transfer_dma;
3007 trb_buff_len = TRB_MAX_BUFF_SIZE -
a2490187
PZ
3008 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3009 if (trb_buff_len > urb->transfer_buffer_length)
b10de142
SS
3010 trb_buff_len = urb->transfer_buffer_length;
3011
3012 first_trb = true;
3013
3014 /* Queue the first TRB, even if it's zero-length */
3015 do {
04dd950d 3016 u32 remainder = 0;
b10de142
SS
3017 field = 0;
3018
3019 /* Don't change the cycle bit of the first TRB until later */
50f7b52a 3020 if (first_trb) {
b10de142 3021 first_trb = false;
50f7b52a
AX
3022 if (start_cycle == 0)
3023 field |= 0x1;
3024 } else
b10de142
SS
3025 field |= ep_ring->cycle_state;
3026
3027 /* Chain all the TRBs together; clear the chain bit in the last
3028 * TRB to indicate it's the last TRB in the chain.
3029 */
3030 if (num_trbs > 1) {
3031 field |= TRB_CHAIN;
3032 } else {
3033 /* FIXME - add check for ZERO_PACKET flag before this */
3034 td->last_trb = ep_ring->enqueue;
3035 field |= TRB_IOC;
3036 }
af8b9e63
SS
3037
3038 /* Only set interrupt on short packet for IN endpoints */
3039 if (usb_urb_dir_in(urb))
3040 field |= TRB_ISP;
3041
4da6e6f2
SS
3042 /* Set the TRB length, TD size, and interrupter fields. */
3043 if (xhci->hci_version < 0x100) {
3044 remainder = xhci_td_remainder(
3045 urb->transfer_buffer_length -
3046 running_total);
3047 } else {
3048 remainder = xhci_v1_0_td_remainder(running_total,
3049 trb_buff_len, total_packet_count, urb);
3050 }
f9dc68fe 3051 length_field = TRB_LEN(trb_buff_len) |
04dd950d 3052 remainder |
f9dc68fe 3053 TRB_INTR_TARGET(0);
4da6e6f2 3054
6cc30d85
SS
3055 if (num_trbs > 1)
3056 more_trbs_coming = true;
3057 else
3058 more_trbs_coming = false;
3b72fca0 3059 queue_trb(xhci, ep_ring, more_trbs_coming,
8e595a5d
SS
3060 lower_32_bits(addr),
3061 upper_32_bits(addr),
f9dc68fe 3062 length_field,
af8b9e63 3063 field | TRB_TYPE(TRB_NORMAL));
b10de142
SS
3064 --num_trbs;
3065 running_total += trb_buff_len;
3066
3067 /* Calculate length for next transfer */
3068 addr += trb_buff_len;
3069 trb_buff_len = urb->transfer_buffer_length - running_total;
3070 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3071 trb_buff_len = TRB_MAX_BUFF_SIZE;
3072 } while (running_total < urb->transfer_buffer_length);
3073
8a96c052 3074 check_trb_math(urb, num_trbs, running_total);
e9df17eb 3075 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
e1eab2e0 3076 start_cycle, start_trb);
b10de142
SS
3077 return 0;
3078}
3079
d0e96f5a 3080/* Caller must have locked xhci->lock */
23e3be11 3081int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
d0e96f5a
SS
3082 struct urb *urb, int slot_id, unsigned int ep_index)
3083{
3084 struct xhci_ring *ep_ring;
3085 int num_trbs;
3086 int ret;
3087 struct usb_ctrlrequest *setup;
3088 struct xhci_generic_trb *start_trb;
3089 int start_cycle;
f9dc68fe 3090 u32 field, length_field;
8e51adcc 3091 struct urb_priv *urb_priv;
d0e96f5a
SS
3092 struct xhci_td *td;
3093
e9df17eb
SS
3094 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3095 if (!ep_ring)
3096 return -EINVAL;
d0e96f5a
SS
3097
3098 /*
3099 * Need to copy setup packet into setup TRB, so we can't use the setup
3100 * DMA address.
3101 */
3102 if (!urb->setup_packet)
3103 return -EINVAL;
3104
d0e96f5a
SS
3105 /* 1 TRB for setup, 1 for status */
3106 num_trbs = 2;
3107 /*
3108 * Don't need to check if we need additional event data and normal TRBs,
3109 * since data in control transfers will never get bigger than 16MB
3110 * XXX: can we get a buffer that crosses 64KB boundaries?
3111 */
3112 if (urb->transfer_buffer_length > 0)
3113 num_trbs++;
e9df17eb
SS
3114 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3115 ep_index, urb->stream_id,
3b72fca0 3116 num_trbs, urb, 0, mem_flags);
d0e96f5a
SS
3117 if (ret < 0)
3118 return ret;
3119
8e51adcc
AX
3120 urb_priv = urb->hcpriv;
3121 td = urb_priv->td[0];
3122
d0e96f5a
SS
3123 /*
3124 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3125 * until we've finished creating all the other TRBs. The ring's cycle
3126 * state may change as we enqueue the other TRBs, so save it too.
3127 */
3128 start_trb = &ep_ring->enqueue->generic;
3129 start_cycle = ep_ring->cycle_state;
3130
3131 /* Queue setup TRB - see section 6.4.1.2.1 */
3132 /* FIXME better way to translate setup_packet into two u32 fields? */
3133 setup = (struct usb_ctrlrequest *) urb->setup_packet;
50f7b52a
AX
3134 field = 0;
3135 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3136 if (start_cycle == 0)
3137 field |= 0x1;
b83cdc8f
AX
3138
3139 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3140 if (xhci->hci_version == 0x100) {
3141 if (urb->transfer_buffer_length > 0) {
3142 if (setup->bRequestType & USB_DIR_IN)
3143 field |= TRB_TX_TYPE(TRB_DATA_IN);
3144 else
3145 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3146 }
3147 }
3148
3b72fca0 3149 queue_trb(xhci, ep_ring, true,
28ccd296
ME
3150 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3151 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3152 TRB_LEN(8) | TRB_INTR_TARGET(0),
3153 /* Immediate data in pointer */
3154 field);
d0e96f5a
SS
3155
3156 /* If there's data, queue data TRBs */
af8b9e63
SS
3157 /* Only set interrupt on short packet for IN endpoints */
3158 if (usb_urb_dir_in(urb))
3159 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3160 else
3161 field = TRB_TYPE(TRB_DATA);
3162
f9dc68fe 3163 length_field = TRB_LEN(urb->transfer_buffer_length) |
04dd950d 3164 xhci_td_remainder(urb->transfer_buffer_length) |
f9dc68fe 3165 TRB_INTR_TARGET(0);
d0e96f5a
SS
3166 if (urb->transfer_buffer_length > 0) {
3167 if (setup->bRequestType & USB_DIR_IN)
3168 field |= TRB_DIR_IN;
3b72fca0 3169 queue_trb(xhci, ep_ring, true,
d0e96f5a
SS
3170 lower_32_bits(urb->transfer_dma),
3171 upper_32_bits(urb->transfer_dma),
f9dc68fe 3172 length_field,
af8b9e63 3173 field | ep_ring->cycle_state);
d0e96f5a
SS
3174 }
3175
3176 /* Save the DMA address of the last TRB in the TD */
3177 td->last_trb = ep_ring->enqueue;
3178
3179 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3180 /* If the device sent data, the status stage is an OUT transfer */
3181 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3182 field = 0;
3183 else
3184 field = TRB_DIR_IN;
3b72fca0 3185 queue_trb(xhci, ep_ring, false,
d0e96f5a
SS
3186 0,
3187 0,
3188 TRB_INTR_TARGET(0),
3189 /* Event on completion */
3190 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3191
e9df17eb 3192 giveback_first_trb(xhci, slot_id, ep_index, 0,
e1eab2e0 3193 start_cycle, start_trb);
d0e96f5a
SS
3194 return 0;
3195}
3196
04e51901
AX
3197static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3198 struct urb *urb, int i)
3199{
3200 int num_trbs = 0;
48df4a6f 3201 u64 addr, td_len;
04e51901
AX
3202
3203 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3204 td_len = urb->iso_frame_desc[i].length;
3205
48df4a6f
SS
3206 num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3207 TRB_MAX_BUFF_SIZE);
3208 if (num_trbs == 0)
04e51901 3209 num_trbs++;
04e51901
AX
3210
3211 return num_trbs;
3212}
3213
5cd43e33
SS
3214/*
3215 * The transfer burst count field of the isochronous TRB defines the number of
3216 * bursts that are required to move all packets in this TD. Only SuperSpeed
3217 * devices can burst up to bMaxBurst number of packets per service interval.
3218 * This field is zero based, meaning a value of zero in the field means one
3219 * burst. Basically, for everything but SuperSpeed devices, this field will be
3220 * zero. Only xHCI 1.0 host controllers support this field.
3221 */
3222static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3223 struct usb_device *udev,
3224 struct urb *urb, unsigned int total_packet_count)
3225{
3226 unsigned int max_burst;
3227
3228 if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3229 return 0;
3230
3231 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3232 return roundup(total_packet_count, max_burst + 1) - 1;
3233}
3234
b61d378f
SS
3235/*
3236 * Returns the number of packets in the last "burst" of packets. This field is
3237 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3238 * the last burst packet count is equal to the total number of packets in the
3239 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3240 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3241 * contain 1 to (bMaxBurst + 1) packets.
3242 */
3243static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3244 struct usb_device *udev,
3245 struct urb *urb, unsigned int total_packet_count)
3246{
3247 unsigned int max_burst;
3248 unsigned int residue;
3249
3250 if (xhci->hci_version < 0x100)
3251 return 0;
3252
3253 switch (udev->speed) {
3254 case USB_SPEED_SUPER:
3255 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3256 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3257 residue = total_packet_count % (max_burst + 1);
3258 /* If residue is zero, the last burst contains (max_burst + 1)
3259 * number of packets, but the TLBPC field is zero-based.
3260 */
3261 if (residue == 0)
3262 return max_burst;
3263 return residue - 1;
3264 default:
3265 if (total_packet_count == 0)
3266 return 0;
3267 return total_packet_count - 1;
3268 }
3269}
3270
04e51901
AX
3271/* This is for isoc transfer */
3272static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3273 struct urb *urb, int slot_id, unsigned int ep_index)
3274{
3275 struct xhci_ring *ep_ring;
3276 struct urb_priv *urb_priv;
3277 struct xhci_td *td;
3278 int num_tds, trbs_per_td;
3279 struct xhci_generic_trb *start_trb;
3280 bool first_trb;
3281 int start_cycle;
3282 u32 field, length_field;
3283 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3284 u64 start_addr, addr;
3285 int i, j;
47cbf692 3286 bool more_trbs_coming;
04e51901
AX
3287
3288 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3289
3290 num_tds = urb->number_of_packets;
3291 if (num_tds < 1) {
3292 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3293 return -EINVAL;
3294 }
3295
04e51901
AX
3296 start_addr = (u64) urb->transfer_dma;
3297 start_trb = &ep_ring->enqueue->generic;
3298 start_cycle = ep_ring->cycle_state;
3299
522989a2 3300 urb_priv = urb->hcpriv;
04e51901
AX
3301 /* Queue the first TRB, even if it's zero-length */
3302 for (i = 0; i < num_tds; i++) {
4da6e6f2 3303 unsigned int total_packet_count;
5cd43e33 3304 unsigned int burst_count;
b61d378f 3305 unsigned int residue;
04e51901 3306
4da6e6f2 3307 first_trb = true;
04e51901
AX
3308 running_total = 0;
3309 addr = start_addr + urb->iso_frame_desc[i].offset;
3310 td_len = urb->iso_frame_desc[i].length;
3311 td_remain_len = td_len;
4da6e6f2 3312 total_packet_count = roundup(td_len,
29cc8897 3313 usb_endpoint_maxp(&urb->ep->desc));
48df4a6f
SS
3314 /* A zero-length transfer still involves at least one packet. */
3315 if (total_packet_count == 0)
3316 total_packet_count++;
5cd43e33
SS
3317 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3318 total_packet_count);
b61d378f
SS
3319 residue = xhci_get_last_burst_packet_count(xhci,
3320 urb->dev, urb, total_packet_count);
04e51901
AX
3321
3322 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3323
3324 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3b72fca0 3325 urb->stream_id, trbs_per_td, urb, i, mem_flags);
522989a2
SS
3326 if (ret < 0) {
3327 if (i == 0)
3328 return ret;
3329 goto cleanup;
3330 }
04e51901 3331
04e51901 3332 td = urb_priv->td[i];
04e51901
AX
3333 for (j = 0; j < trbs_per_td; j++) {
3334 u32 remainder = 0;
b61d378f 3335 field = TRB_TBC(burst_count) | TRB_TLBPC(residue);
04e51901
AX
3336
3337 if (first_trb) {
3338 /* Queue the isoc TRB */
3339 field |= TRB_TYPE(TRB_ISOC);
3340 /* Assume URB_ISO_ASAP is set */
3341 field |= TRB_SIA;
50f7b52a
AX
3342 if (i == 0) {
3343 if (start_cycle == 0)
3344 field |= 0x1;
3345 } else
04e51901
AX
3346 field |= ep_ring->cycle_state;
3347 first_trb = false;
3348 } else {
3349 /* Queue other normal TRBs */
3350 field |= TRB_TYPE(TRB_NORMAL);
3351 field |= ep_ring->cycle_state;
3352 }
3353
af8b9e63
SS
3354 /* Only set interrupt on short packet for IN EPs */
3355 if (usb_urb_dir_in(urb))
3356 field |= TRB_ISP;
3357
04e51901
AX
3358 /* Chain all the TRBs together; clear the chain bit in
3359 * the last TRB to indicate it's the last TRB in the
3360 * chain.
3361 */
3362 if (j < trbs_per_td - 1) {
3363 field |= TRB_CHAIN;
47cbf692 3364 more_trbs_coming = true;
04e51901
AX
3365 } else {
3366 td->last_trb = ep_ring->enqueue;
3367 field |= TRB_IOC;
ad106f29
AX
3368 if (xhci->hci_version == 0x100) {
3369 /* Set BEI bit except for the last td */
3370 if (i < num_tds - 1)
3371 field |= TRB_BEI;
3372 }
47cbf692 3373 more_trbs_coming = false;
04e51901
AX
3374 }
3375
3376 /* Calculate TRB length */
3377 trb_buff_len = TRB_MAX_BUFF_SIZE -
3378 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3379 if (trb_buff_len > td_remain_len)
3380 trb_buff_len = td_remain_len;
3381
4da6e6f2
SS
3382 /* Set the TRB length, TD size, & interrupter fields. */
3383 if (xhci->hci_version < 0x100) {
3384 remainder = xhci_td_remainder(
3385 td_len - running_total);
3386 } else {
3387 remainder = xhci_v1_0_td_remainder(
3388 running_total, trb_buff_len,
3389 total_packet_count, urb);
3390 }
04e51901
AX
3391 length_field = TRB_LEN(trb_buff_len) |
3392 remainder |
3393 TRB_INTR_TARGET(0);
4da6e6f2 3394
3b72fca0 3395 queue_trb(xhci, ep_ring, more_trbs_coming,
04e51901
AX
3396 lower_32_bits(addr),
3397 upper_32_bits(addr),
3398 length_field,
af8b9e63 3399 field);
04e51901
AX
3400 running_total += trb_buff_len;
3401
3402 addr += trb_buff_len;
3403 td_remain_len -= trb_buff_len;
3404 }
3405
3406 /* Check TD length */
3407 if (running_total != td_len) {
3408 xhci_err(xhci, "ISOC TD length unmatch\n");
cf840551
AX
3409 ret = -EINVAL;
3410 goto cleanup;
04e51901
AX
3411 }
3412 }
3413
c41136b0
AX
3414 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3415 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3416 usb_amd_quirk_pll_disable();
3417 }
3418 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3419
e1eab2e0
AX
3420 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3421 start_cycle, start_trb);
04e51901 3422 return 0;
522989a2
SS
3423cleanup:
3424 /* Clean up a partially enqueued isoc transfer. */
3425
3426 for (i--; i >= 0; i--)
585df1d9 3427 list_del_init(&urb_priv->td[i]->td_list);
522989a2
SS
3428
3429 /* Use the first TD as a temporary variable to turn the TDs we've queued
3430 * into No-ops with a software-owned cycle bit. That way the hardware
3431 * won't accidentally start executing bogus TDs when we partially
3432 * overwrite them. td->first_trb and td->start_seg are already set.
3433 */
3434 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3435 /* Every TRB except the first & last will have its cycle bit flipped. */
3436 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3437
3438 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3439 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3440 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3441 ep_ring->cycle_state = start_cycle;
b008df60 3442 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
522989a2
SS
3443 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3444 return ret;
04e51901
AX
3445}
3446
3447/*
3448 * Check transfer ring to guarantee there is enough room for the urb.
3449 * Update ISO URB start_frame and interval.
3450 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3451 * update the urb->start_frame by now.
3452 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3453 */
3454int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3455 struct urb *urb, int slot_id, unsigned int ep_index)
3456{
3457 struct xhci_virt_device *xdev;
3458 struct xhci_ring *ep_ring;
3459 struct xhci_ep_ctx *ep_ctx;
3460 int start_frame;
3461 int xhci_interval;
3462 int ep_interval;
3463 int num_tds, num_trbs, i;
3464 int ret;
3465
3466 xdev = xhci->devs[slot_id];
3467 ep_ring = xdev->eps[ep_index].ring;
3468 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3469
3470 num_trbs = 0;
3471 num_tds = urb->number_of_packets;
3472 for (i = 0; i < num_tds; i++)
3473 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3474
3475 /* Check the ring to guarantee there is enough room for the whole urb.
3476 * Do not insert any td of the urb to the ring if the check failed.
3477 */
28ccd296 3478 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3b72fca0 3479 num_trbs, mem_flags);
04e51901
AX
3480 if (ret)
3481 return ret;
3482
3483 start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3484 start_frame &= 0x3fff;
3485
3486 urb->start_frame = start_frame;
3487 if (urb->dev->speed == USB_SPEED_LOW ||
3488 urb->dev->speed == USB_SPEED_FULL)
3489 urb->start_frame >>= 3;
3490
28ccd296 3491 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
04e51901
AX
3492 ep_interval = urb->interval;
3493 /* Convert to microframes */
3494 if (urb->dev->speed == USB_SPEED_LOW ||
3495 urb->dev->speed == USB_SPEED_FULL)
3496 ep_interval *= 8;
3497 /* FIXME change this to a warning and a suggestion to use the new API
3498 * to set the polling interval (once the API is added).
3499 */
3500 if (xhci_interval != ep_interval) {
7961acd7 3501 if (printk_ratelimit())
04e51901
AX
3502 dev_dbg(&urb->dev->dev, "Driver uses different interval"
3503 " (%d microframe%s) than xHCI "
3504 "(%d microframe%s)\n",
3505 ep_interval,
3506 ep_interval == 1 ? "" : "s",
3507 xhci_interval,
3508 xhci_interval == 1 ? "" : "s");
3509 urb->interval = xhci_interval;
3510 /* Convert back to frames for LS/FS devices */
3511 if (urb->dev->speed == USB_SPEED_LOW ||
3512 urb->dev->speed == USB_SPEED_FULL)
3513 urb->interval /= 8;
3514 }
b008df60
AX
3515 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3516
04e51901
AX
3517 return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3518}
3519
d0e96f5a
SS
3520/**** Command Ring Operations ****/
3521
913a8a34
SS
3522/* Generic function for queueing a command TRB on the command ring.
3523 * Check to make sure there's room on the command ring for one command TRB.
3524 * Also check that there's room reserved for commands that must not fail.
3525 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3526 * then only check for the number of reserved spots.
3527 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3528 * because the command event handler may want to resubmit a failed command.
3529 */
3530static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3531 u32 field3, u32 field4, bool command_must_succeed)
7f84eef0 3532{
913a8a34 3533 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
d1dc908a
SS
3534 int ret;
3535
913a8a34
SS
3536 if (!command_must_succeed)
3537 reserved_trbs++;
3538
d1dc908a 3539 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3b72fca0 3540 reserved_trbs, GFP_ATOMIC);
d1dc908a
SS
3541 if (ret < 0) {
3542 xhci_err(xhci, "ERR: No room for command on command ring\n");
913a8a34
SS
3543 if (command_must_succeed)
3544 xhci_err(xhci, "ERR: Reserved TRB counting for "
3545 "unfailable commands failed.\n");
d1dc908a 3546 return ret;
7f84eef0 3547 }
3b72fca0
AX
3548 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3549 field4 | xhci->cmd_ring->cycle_state);
7f84eef0
SS
3550 return 0;
3551}
3552
3ffbba95 3553/* Queue a slot enable or disable request on the command ring */
23e3be11 3554int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3ffbba95
SS
3555{
3556 return queue_command(xhci, 0, 0, 0,
913a8a34 3557 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3ffbba95
SS
3558}
3559
3560/* Queue an address device command TRB */
23e3be11
SS
3561int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3562 u32 slot_id)
3ffbba95 3563{
8e595a5d
SS
3564 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3565 upper_32_bits(in_ctx_ptr), 0,
913a8a34 3566 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
2a8f82c4
SS
3567 false);
3568}
3569
0238634d
SS
3570int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3571 u32 field1, u32 field2, u32 field3, u32 field4)
3572{
3573 return queue_command(xhci, field1, field2, field3, field4, false);
3574}
3575
2a8f82c4
SS
3576/* Queue a reset device command TRB */
3577int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3578{
3579 return queue_command(xhci, 0, 0, 0,
3580 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
913a8a34 3581 false);
3ffbba95 3582}
f94e0186
SS
3583
3584/* Queue a configure endpoint command TRB */
23e3be11 3585int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
913a8a34 3586 u32 slot_id, bool command_must_succeed)
f94e0186 3587{
8e595a5d
SS
3588 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3589 upper_32_bits(in_ctx_ptr), 0,
913a8a34
SS
3590 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3591 command_must_succeed);
f94e0186 3592}
ae636747 3593
f2217e8e
SS
3594/* Queue an evaluate context command TRB */
3595int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3596 u32 slot_id)
3597{
3598 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3599 upper_32_bits(in_ctx_ptr), 0,
913a8a34
SS
3600 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3601 false);
f2217e8e
SS
3602}
3603
be88fe4f
AX
3604/*
3605 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3606 * activity on an endpoint that is about to be suspended.
3607 */
23e3be11 3608int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
be88fe4f 3609 unsigned int ep_index, int suspend)
ae636747
SS
3610{
3611 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3612 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3613 u32 type = TRB_TYPE(TRB_STOP_RING);
be88fe4f 3614 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
ae636747
SS
3615
3616 return queue_command(xhci, 0, 0, 0,
be88fe4f 3617 trb_slot_id | trb_ep_index | type | trb_suspend, false);
ae636747
SS
3618}
3619
3620/* Set Transfer Ring Dequeue Pointer command.
3621 * This should not be used for endpoints that have streams enabled.
3622 */
3623static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
e9df17eb
SS
3624 unsigned int ep_index, unsigned int stream_id,
3625 struct xhci_segment *deq_seg,
ae636747
SS
3626 union xhci_trb *deq_ptr, u32 cycle_state)
3627{
3628 dma_addr_t addr;
3629 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3630 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
e9df17eb 3631 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
ae636747 3632 u32 type = TRB_TYPE(TRB_SET_DEQ);
bf161e85 3633 struct xhci_virt_ep *ep;
ae636747 3634
23e3be11 3635 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
c92bcfa7 3636 if (addr == 0) {
ae636747 3637 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
700e2052
GKH
3638 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3639 deq_seg, deq_ptr);
c92bcfa7
SS
3640 return 0;
3641 }
bf161e85
SS
3642 ep = &xhci->devs[slot_id]->eps[ep_index];
3643 if ((ep->ep_state & SET_DEQ_PENDING)) {
3644 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3645 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3646 return 0;
3647 }
3648 ep->queued_deq_seg = deq_seg;
3649 ep->queued_deq_ptr = deq_ptr;
8e595a5d 3650 return queue_command(xhci, lower_32_bits(addr) | cycle_state,
e9df17eb 3651 upper_32_bits(addr), trb_stream_id,
913a8a34 3652 trb_slot_id | trb_ep_index | type, false);
ae636747 3653}
a1587d97
SS
3654
3655int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3656 unsigned int ep_index)
3657{
3658 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3659 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3660 u32 type = TRB_TYPE(TRB_RESET_EP);
3661
913a8a34
SS
3662 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3663 false);
a1587d97 3664}
This page took 0.438821 seconds and 5 git commands to generate.