Merge branches 'acpi-soc', 'acpi-misc', 'acpi-pci' and 'device-properties'
[deliverable/linux.git] / drivers / video / fbdev / atmel_lcdfb.c
CommitLineData
14340586
NF
1/*
2 * Driver for AT91/AT32 LCD Controller
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive for
8 * more details.
9 */
10
11#include <linux/kernel.h>
12#include <linux/platform_device.h>
13#include <linux/dma-mapping.h>
14#include <linux/interrupt.h>
15#include <linux/clk.h>
16#include <linux/fb.h>
17#include <linux/init.h>
18#include <linux/delay.h>
a9a84c37 19#include <linux/backlight.h>
5a0e3ad6 20#include <linux/gfp.h>
355b200b 21#include <linux/module.h>
b985172b
JCPV
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/of_gpio.h>
8af2c286 25#include <video/of_display_timing.h>
2d605456 26#include <linux/regulator/consumer.h>
b985172b 27#include <video/videomode.h>
14340586 28
60e8972d 29#include <asm/gpio.h>
14340586
NF
30
31#include <video/atmel_lcdc.h>
32
8af2c286
JCPV
33struct atmel_lcdfb_config {
34 bool have_alt_pixclock;
35 bool have_hozval;
36 bool have_intensity_bit;
37};
38
39 /* LCD Controller info data structure, stored in device platform_data */
40struct atmel_lcdfb_info {
41 spinlock_t lock;
42 struct fb_info *info;
43 void __iomem *mmio;
44 int irq_base;
45 struct work_struct task;
46
47 unsigned int smem_len;
48 struct platform_device *pdev;
49 struct clk *bus_clk;
50 struct clk *lcdc_clk;
51
52 struct backlight_device *backlight;
53 u8 bl_power;
54 u8 saved_lcdcon;
55
56 u32 pseudo_palette[16];
57 bool have_intensity_bit;
58
59 struct atmel_lcdfb_pdata pdata;
60
61 struct atmel_lcdfb_config *config;
2d605456 62 struct regulator *reg_lcd;
8af2c286
JCPV
63};
64
b985172b
JCPV
65struct atmel_lcdfb_power_ctrl_gpio {
66 int gpio;
67 int active_low;
68
69 struct list_head list;
70};
71
14340586
NF
72#define lcdc_readl(sinfo, reg) __raw_readl((sinfo)->mmio+(reg))
73#define lcdc_writel(sinfo, reg, val) __raw_writel((val), (sinfo)->mmio+(reg))
74
75/* configurable parameters */
76#define ATMEL_LCDC_CVAL_DEFAULT 0xc8
53b7479b
NF
77#define ATMEL_LCDC_DMA_BURST_LEN 8 /* words */
78#define ATMEL_LCDC_FIFO_SIZE 512 /* words */
14340586 79
bbd44f6b
JH
80static struct atmel_lcdfb_config at91sam9261_config = {
81 .have_hozval = true,
82 .have_intensity_bit = true,
83};
84
85static struct atmel_lcdfb_config at91sam9263_config = {
86 .have_intensity_bit = true,
87};
88
89static struct atmel_lcdfb_config at91sam9g10_config = {
90 .have_hozval = true,
91};
92
93static struct atmel_lcdfb_config at91sam9g45_config = {
94 .have_alt_pixclock = true,
95};
96
97static struct atmel_lcdfb_config at91sam9g45es_config = {
98};
99
100static struct atmel_lcdfb_config at91sam9rl_config = {
101 .have_intensity_bit = true,
102};
103
104static struct atmel_lcdfb_config at32ap_config = {
105 .have_hozval = true,
106};
107
108static const struct platform_device_id atmel_lcdfb_devtypes[] = {
109 {
110 .name = "at91sam9261-lcdfb",
111 .driver_data = (unsigned long)&at91sam9261_config,
112 }, {
113 .name = "at91sam9263-lcdfb",
114 .driver_data = (unsigned long)&at91sam9263_config,
115 }, {
116 .name = "at91sam9g10-lcdfb",
117 .driver_data = (unsigned long)&at91sam9g10_config,
118 }, {
119 .name = "at91sam9g45-lcdfb",
120 .driver_data = (unsigned long)&at91sam9g45_config,
121 }, {
122 .name = "at91sam9g45es-lcdfb",
123 .driver_data = (unsigned long)&at91sam9g45es_config,
124 }, {
125 .name = "at91sam9rl-lcdfb",
126 .driver_data = (unsigned long)&at91sam9rl_config,
127 }, {
128 .name = "at32ap-lcdfb",
129 .driver_data = (unsigned long)&at32ap_config,
130 }, {
131 /* terminator */
132 }
133};
5a0973f3 134MODULE_DEVICE_TABLE(platform, atmel_lcdfb_devtypes);
bbd44f6b
JH
135
136static struct atmel_lcdfb_config *
137atmel_lcdfb_get_config(struct platform_device *pdev)
138{
139 unsigned long data;
140
141 data = platform_get_device_id(pdev)->driver_data;
142
143 return (struct atmel_lcdfb_config *)data;
144}
145
14340586 146#if defined(CONFIG_ARCH_AT91)
e730d8b0
HS
147#define ATMEL_LCDFB_FBINFO_DEFAULT (FBINFO_DEFAULT \
148 | FBINFO_PARTIAL_PAN_OK \
149 | FBINFO_HWACCEL_YPAN)
14340586
NF
150
151static inline void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
b3e9c129
LP
152 struct fb_var_screeninfo *var,
153 struct fb_info *info)
14340586
NF
154{
155
156}
157#elif defined(CONFIG_AVR32)
158#define ATMEL_LCDFB_FBINFO_DEFAULT (FBINFO_DEFAULT \
159 | FBINFO_PARTIAL_PAN_OK \
160 | FBINFO_HWACCEL_XPAN \
161 | FBINFO_HWACCEL_YPAN)
162
163static void atmel_lcdfb_update_dma2d(struct atmel_lcdfb_info *sinfo,
b3e9c129
LP
164 struct fb_var_screeninfo *var,
165 struct fb_info *info)
14340586
NF
166{
167 u32 dma2dcfg;
168 u32 pixeloff;
169
b3e9c129 170 pixeloff = (var->xoffset * info->var.bits_per_pixel) & 0x1f;
14340586 171
b3e9c129
LP
172 dma2dcfg = (info->var.xres_virtual - info->var.xres)
173 * info->var.bits_per_pixel / 8;
14340586
NF
174 dma2dcfg |= pixeloff << ATMEL_LCDC_PIXELOFF_OFFSET;
175 lcdc_writel(sinfo, ATMEL_LCDC_DMA2DCFG, dma2dcfg);
176
177 /* Update configuration */
178 lcdc_writel(sinfo, ATMEL_LCDC_DMACON,
179 lcdc_readl(sinfo, ATMEL_LCDC_DMACON)
180 | ATMEL_LCDC_DMAUPDT);
181}
182#endif
183
7cdcdb69 184static u32 contrast_ctr = ATMEL_LCDC_PS_DIV8
a9a84c37
DB
185 | ATMEL_LCDC_POL_POSITIVE
186 | ATMEL_LCDC_ENA_PWMENABLE;
187
188#ifdef CONFIG_BACKLIGHT_ATMEL_LCDC
189
190/* some bl->props field just changed */
191static int atmel_bl_update_status(struct backlight_device *bl)
192{
193 struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
194 int power = sinfo->bl_power;
195 int brightness = bl->props.brightness;
196
197 /* REVISIT there may be a meaningful difference between
198 * fb_blank and power ... there seem to be some cases
199 * this doesn't handle correctly.
200 */
201 if (bl->props.fb_blank != sinfo->bl_power)
202 power = bl->props.fb_blank;
203 else if (bl->props.power != sinfo->bl_power)
204 power = bl->props.power;
205
206 if (brightness < 0 && power == FB_BLANK_UNBLANK)
207 brightness = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
208 else if (power != FB_BLANK_UNBLANK)
209 brightness = 0;
210
211 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, brightness);
acfdc2e1
AS
212 if (contrast_ctr & ATMEL_LCDC_POL_POSITIVE)
213 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR,
a9a84c37 214 brightness ? contrast_ctr : 0);
acfdc2e1
AS
215 else
216 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr);
a9a84c37
DB
217
218 bl->props.fb_blank = bl->props.power = sinfo->bl_power = power;
219
220 return 0;
221}
222
223static int atmel_bl_get_brightness(struct backlight_device *bl)
224{
225 struct atmel_lcdfb_info *sinfo = bl_get_data(bl);
226
227 return lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_VAL);
228}
229
acc2472e 230static const struct backlight_ops atmel_lcdc_bl_ops = {
a9a84c37
DB
231 .update_status = atmel_bl_update_status,
232 .get_brightness = atmel_bl_get_brightness,
233};
234
235static void init_backlight(struct atmel_lcdfb_info *sinfo)
236{
a19a6ee6 237 struct backlight_properties props;
a9a84c37
DB
238 struct backlight_device *bl;
239
240 sinfo->bl_power = FB_BLANK_UNBLANK;
241
242 if (sinfo->backlight)
243 return;
244
a19a6ee6 245 memset(&props, 0, sizeof(struct backlight_properties));
bb7ca747 246 props.type = BACKLIGHT_RAW;
a19a6ee6
MG
247 props.max_brightness = 0xff;
248 bl = backlight_device_register("backlight", &sinfo->pdev->dev, sinfo,
249 &atmel_lcdc_bl_ops, &props);
cf7b9a1e 250 if (IS_ERR(bl)) {
a9a84c37
DB
251 dev_err(&sinfo->pdev->dev, "error %ld on backlight register\n",
252 PTR_ERR(bl));
253 return;
254 }
255 sinfo->backlight = bl;
256
257 bl->props.power = FB_BLANK_UNBLANK;
258 bl->props.fb_blank = FB_BLANK_UNBLANK;
a9a84c37
DB
259 bl->props.brightness = atmel_bl_get_brightness(bl);
260}
261
262static void exit_backlight(struct atmel_lcdfb_info *sinfo)
263{
56c21b53
RG
264 if (!sinfo->backlight)
265 return;
266
267 if (sinfo->backlight->ops) {
268 sinfo->backlight->props.power = FB_BLANK_POWERDOWN;
269 sinfo->backlight->ops->update_status(sinfo->backlight);
270 }
271 backlight_device_unregister(sinfo->backlight);
a9a84c37
DB
272}
273
274#else
275
276static void init_backlight(struct atmel_lcdfb_info *sinfo)
277{
278 dev_warn(&sinfo->pdev->dev, "backlight control is not available\n");
279}
280
281static void exit_backlight(struct atmel_lcdfb_info *sinfo)
282{
283}
284
285#endif
286
287static void init_contrast(struct atmel_lcdfb_info *sinfo)
288{
8af2c286
JCPV
289 struct atmel_lcdfb_pdata *pdata = &sinfo->pdata;
290
7cdcdb69 291 /* contrast pwm can be 'inverted' */
8af2c286 292 if (pdata->lcdcon_pol_negative)
d7aa64c3 293 contrast_ctr &= ~(ATMEL_LCDC_POL_POSITIVE);
7cdcdb69 294
a9a84c37
DB
295 /* have some default contrast/backlight settings */
296 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, contrast_ctr);
297 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
298
8af2c286 299 if (pdata->lcdcon_is_backlight)
a9a84c37
DB
300 init_backlight(sinfo);
301}
302
42110e91
JCPV
303static inline void atmel_lcdfb_power_control(struct atmel_lcdfb_info *sinfo, int on)
304{
2d605456 305 int ret;
42110e91
JCPV
306 struct atmel_lcdfb_pdata *pdata = &sinfo->pdata;
307
308 if (pdata->atmel_lcdfb_power_control)
ce3b64f5 309 pdata->atmel_lcdfb_power_control(pdata, on);
2d605456
AS
310 else if (sinfo->reg_lcd) {
311 if (on) {
312 ret = regulator_enable(sinfo->reg_lcd);
313 if (ret)
314 dev_err(&sinfo->pdev->dev,
315 "lcd regulator enable failed: %d\n", ret);
316 } else {
317 ret = regulator_disable(sinfo->reg_lcd);
318 if (ret)
319 dev_err(&sinfo->pdev->dev,
320 "lcd regulator disable failed: %d\n", ret);
321 }
322 }
42110e91 323}
14340586
NF
324
325static struct fb_fix_screeninfo atmel_lcdfb_fix __initdata = {
326 .type = FB_TYPE_PACKED_PIXELS,
327 .visual = FB_VISUAL_TRUECOLOR,
328 .xpanstep = 0,
e730d8b0 329 .ypanstep = 1,
14340586
NF
330 .ywrapstep = 0,
331 .accel = FB_ACCEL_NONE,
332};
333
934a50bd
JH
334static unsigned long compute_hozval(struct atmel_lcdfb_info *sinfo,
335 unsigned long xres)
250a269d 336{
934a50bd 337 unsigned long lcdcon2;
250a269d
NF
338 unsigned long value;
339
bbd44f6b 340 if (!sinfo->config->have_hozval)
250a269d
NF
341 return xres;
342
934a50bd 343 lcdcon2 = lcdc_readl(sinfo, ATMEL_LCDC_LCDCON2);
250a269d
NF
344 value = xres;
345 if ((lcdcon2 & ATMEL_LCDC_DISTYPE) != ATMEL_LCDC_DISTYPE_TFT) {
346 /* STN display */
347 if ((lcdcon2 & ATMEL_LCDC_DISTYPE) == ATMEL_LCDC_DISTYPE_STNCOLOR) {
348 value *= 3;
349 }
350 if ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_4
351 || ( (lcdcon2 & ATMEL_LCDC_IFWIDTH) == ATMEL_LCDC_IFWIDTH_8
352 && (lcdcon2 & ATMEL_LCDC_SCANMOD) == ATMEL_LCDC_SCANMOD_DUAL ))
353 value = DIV_ROUND_UP(value, 4);
354 else
355 value = DIV_ROUND_UP(value, 8);
356 }
357
358 return value;
359}
14340586 360
3aa04f1b
HS
361static void atmel_lcdfb_stop_nowait(struct atmel_lcdfb_info *sinfo)
362{
8af2c286
JCPV
363 struct atmel_lcdfb_pdata *pdata = &sinfo->pdata;
364
3aa04f1b
HS
365 /* Turn off the LCD controller and the DMA controller */
366 lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
8af2c286 367 pdata->guard_time << ATMEL_LCDC_GUARDT_OFFSET);
3aa04f1b
HS
368
369 /* Wait for the LCDC core to become idle */
370 while (lcdc_readl(sinfo, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
371 msleep(10);
372
373 lcdc_writel(sinfo, ATMEL_LCDC_DMACON, 0);
374}
375
376static void atmel_lcdfb_stop(struct atmel_lcdfb_info *sinfo)
377{
378 atmel_lcdfb_stop_nowait(sinfo);
379
380 /* Wait for DMA engine to become idle... */
381 while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
382 msleep(10);
383}
384
385static void atmel_lcdfb_start(struct atmel_lcdfb_info *sinfo)
386{
8af2c286
JCPV
387 struct atmel_lcdfb_pdata *pdata = &sinfo->pdata;
388
389 lcdc_writel(sinfo, ATMEL_LCDC_DMACON, pdata->default_dmacon);
3aa04f1b 390 lcdc_writel(sinfo, ATMEL_LCDC_PWRCON,
8af2c286 391 (pdata->guard_time << ATMEL_LCDC_GUARDT_OFFSET)
3aa04f1b
HS
392 | ATMEL_LCDC_PWR);
393}
394
14340586
NF
395static void atmel_lcdfb_update_dma(struct fb_info *info,
396 struct fb_var_screeninfo *var)
397{
398 struct atmel_lcdfb_info *sinfo = info->par;
399 struct fb_fix_screeninfo *fix = &info->fix;
400 unsigned long dma_addr;
401
402 dma_addr = (fix->smem_start + var->yoffset * fix->line_length
b3e9c129 403 + var->xoffset * info->var.bits_per_pixel / 8);
14340586
NF
404
405 dma_addr &= ~3UL;
406
407 /* Set framebuffer DMA base address and pixel offset */
408 lcdc_writel(sinfo, ATMEL_LCDC_DMABADDR1, dma_addr);
409
b3e9c129 410 atmel_lcdfb_update_dma2d(sinfo, var, info);
14340586
NF
411}
412
413static inline void atmel_lcdfb_free_video_memory(struct atmel_lcdfb_info *sinfo)
414{
415 struct fb_info *info = sinfo->info;
416
f6e45661
LR
417 dma_free_wc(info->device, info->fix.smem_len, info->screen_base,
418 info->fix.smem_start);
14340586
NF
419}
420
421/**
422 * atmel_lcdfb_alloc_video_memory - Allocate framebuffer memory
423 * @sinfo: the frame buffer to allocate memory for
1d01e835
KH
424 *
425 * This function is called only from the atmel_lcdfb_probe()
426 * so no locking by fb_info->mm_lock around smem_len setting is needed.
14340586
NF
427 */
428static int atmel_lcdfb_alloc_video_memory(struct atmel_lcdfb_info *sinfo)
429{
430 struct fb_info *info = sinfo->info;
431 struct fb_var_screeninfo *var = &info->var;
ea757aca 432 unsigned int smem_len;
14340586 433
ea757aca
HS
434 smem_len = (var->xres_virtual * var->yres_virtual
435 * ((var->bits_per_pixel + 7) / 8));
436 info->fix.smem_len = max(smem_len, sinfo->smem_len);
14340586 437
f6e45661
LR
438 info->screen_base = dma_alloc_wc(info->device, info->fix.smem_len,
439 (dma_addr_t *)&info->fix.smem_start,
440 GFP_KERNEL);
14340586
NF
441
442 if (!info->screen_base) {
443 return -ENOMEM;
444 }
445
01d3a5e7
HS
446 memset(info->screen_base, 0, info->fix.smem_len);
447
14340586
NF
448 return 0;
449}
450
968910bd
NF
451static const struct fb_videomode *atmel_lcdfb_choose_mode(struct fb_var_screeninfo *var,
452 struct fb_info *info)
453{
454 struct fb_videomode varfbmode;
455 const struct fb_videomode *fbmode = NULL;
456
457 fb_var_to_videomode(&varfbmode, var);
458 fbmode = fb_find_nearest_mode(&varfbmode, &info->modelist);
459 if (fbmode)
460 fb_videomode_to_var(var, fbmode);
461 return fbmode;
462}
463
464
14340586
NF
465/**
466 * atmel_lcdfb_check_var - Validates a var passed in.
467 * @var: frame buffer variable screen structure
468 * @info: frame buffer structure that represents a single frame buffer
469 *
470 * Checks to see if the hardware supports the state requested by
471 * var passed in. This function does not alter the hardware
472 * state!!! This means the data stored in struct fb_info and
473 * struct atmel_lcdfb_info do not change. This includes the var
474 * inside of struct fb_info. Do NOT change these. This function
475 * can be called on its own if we intent to only test a mode and
476 * not actually set it. The stuff in modedb.c is a example of
477 * this. If the var passed in is slightly off by what the
478 * hardware can support then we alter the var PASSED in to what
479 * we can do. If the hardware doesn't support mode change a
480 * -EINVAL will be returned by the upper layers. You don't need
481 * to implement this function then. If you hardware doesn't
482 * support changing the resolution then this function is not
483 * needed. In this case the driver would just provide a var that
484 * represents the static state the screen is in.
485 *
486 * Returns negative errno on error, or zero on success.
487 */
488static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var,
489 struct fb_info *info)
490{
491 struct device *dev = info->device;
492 struct atmel_lcdfb_info *sinfo = info->par;
8af2c286 493 struct atmel_lcdfb_pdata *pdata = &sinfo->pdata;
14340586
NF
494 unsigned long clk_value_khz;
495
496 clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
497
498 dev_dbg(dev, "%s:\n", __func__);
968910bd
NF
499
500 if (!(var->pixclock && var->bits_per_pixel)) {
501 /* choose a suitable mode if possible */
502 if (!atmel_lcdfb_choose_mode(var, info)) {
503 dev_err(dev, "needed value not specified\n");
504 return -EINVAL;
505 }
506 }
507
14340586
NF
508 dev_dbg(dev, " resolution: %ux%u\n", var->xres, var->yres);
509 dev_dbg(dev, " pixclk: %lu KHz\n", PICOS2KHZ(var->pixclock));
510 dev_dbg(dev, " bpp: %u\n", var->bits_per_pixel);
511 dev_dbg(dev, " clk: %lu KHz\n", clk_value_khz);
512
97b9a5a2 513 if (PICOS2KHZ(var->pixclock) > clk_value_khz) {
14340586
NF
514 dev_err(dev, "%lu KHz pixel clock is too fast\n", PICOS2KHZ(var->pixclock));
515 return -EINVAL;
516 }
517
968910bd
NF
518 /* Do not allow to have real resoulution larger than virtual */
519 if (var->xres > var->xres_virtual)
520 var->xres_virtual = var->xres;
521
522 if (var->yres > var->yres_virtual)
523 var->yres_virtual = var->yres;
524
14340586
NF
525 /* Force same alignment for each line */
526 var->xres = (var->xres + 3) & ~3UL;
527 var->xres_virtual = (var->xres_virtual + 3) & ~3UL;
528
529 var->red.msb_right = var->green.msb_right = var->blue.msb_right = 0;
530 var->transp.msb_right = 0;
531 var->transp.offset = var->transp.length = 0;
532 var->xoffset = var->yoffset = 0;
533
f928ac0a
SG
534 if (info->fix.smem_len) {
535 unsigned int smem_len = (var->xres_virtual * var->yres_virtual
536 * ((var->bits_per_pixel + 7) / 8));
65ac057b
RG
537 if (smem_len > info->fix.smem_len) {
538 dev_err(dev, "Frame buffer is too small (%u) for screen size (need at least %u)\n",
539 info->fix.smem_len, smem_len);
f928ac0a 540 return -EINVAL;
65ac057b 541 }
f928ac0a
SG
542 }
543
162b3a08
HS
544 /* Saturate vertical and horizontal timings at maximum values */
545 var->vsync_len = min_t(u32, var->vsync_len,
546 (ATMEL_LCDC_VPW >> ATMEL_LCDC_VPW_OFFSET) + 1);
547 var->upper_margin = min_t(u32, var->upper_margin,
548 ATMEL_LCDC_VBP >> ATMEL_LCDC_VBP_OFFSET);
549 var->lower_margin = min_t(u32, var->lower_margin,
550 ATMEL_LCDC_VFP);
551 var->right_margin = min_t(u32, var->right_margin,
6b3cbe40 552 (ATMEL_LCDC_HFP >> ATMEL_LCDC_HFP_OFFSET) + 1);
162b3a08
HS
553 var->hsync_len = min_t(u32, var->hsync_len,
554 (ATMEL_LCDC_HPW >> ATMEL_LCDC_HPW_OFFSET) + 1);
555 var->left_margin = min_t(u32, var->left_margin,
556 ATMEL_LCDC_HBP + 1);
557
558 /* Some parameters can't be zero */
559 var->vsync_len = max_t(u32, var->vsync_len, 1);
560 var->right_margin = max_t(u32, var->right_margin, 1);
561 var->hsync_len = max_t(u32, var->hsync_len, 1);
562 var->left_margin = max_t(u32, var->left_margin, 1);
563
14340586 564 switch (var->bits_per_pixel) {
250a269d 565 case 1:
14340586
NF
566 case 2:
567 case 4:
568 case 8:
569 var->red.offset = var->green.offset = var->blue.offset = 0;
570 var->red.length = var->green.length = var->blue.length
571 = var->bits_per_pixel;
572 break;
14340586 573 case 16:
a79eac71 574 /* Older SOCs use IBGR:555 rather than BGR:565. */
bbd44f6b 575 if (sinfo->config->have_intensity_bit)
a79eac71
JH
576 var->green.length = 5;
577 else
578 var->green.length = 6;
579
8af2c286 580 if (pdata->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
a79eac71
JH
581 /* RGB:5X5 mode */
582 var->red.offset = var->green.length + 5;
fd085801 583 var->blue.offset = 0;
fd085801 584 } else {
a79eac71 585 /* BGR:5X5 mode */
fd085801 586 var->red.offset = 0;
a79eac71 587 var->blue.offset = var->green.length + 5;
fd085801 588 }
14340586 589 var->green.offset = 5;
fd085801 590 var->red.length = var->blue.length = 5;
14340586 591 break;
14340586 592 case 32:
4440e0e1
HS
593 var->transp.offset = 24;
594 var->transp.length = 8;
595 /* fall through */
596 case 24:
8af2c286 597 if (pdata->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
fd085801
NF
598 /* RGB:888 mode */
599 var->red.offset = 16;
600 var->blue.offset = 0;
601 } else {
602 /* BGR:888 mode */
603 var->red.offset = 0;
604 var->blue.offset = 16;
605 }
14340586 606 var->green.offset = 8;
14340586
NF
607 var->red.length = var->green.length = var->blue.length = 8;
608 break;
609 default:
610 dev_err(dev, "color depth %d not supported\n",
611 var->bits_per_pixel);
612 return -EINVAL;
613 }
614
615 return 0;
616}
617
d22579b8
NF
618/*
619 * LCD reset sequence
620 */
621static void atmel_lcdfb_reset(struct atmel_lcdfb_info *sinfo)
622{
623 might_sleep();
624
3aa04f1b
HS
625 atmel_lcdfb_stop(sinfo);
626 atmel_lcdfb_start(sinfo);
d22579b8
NF
627}
628
14340586
NF
629/**
630 * atmel_lcdfb_set_par - Alters the hardware state.
631 * @info: frame buffer structure that represents a single frame buffer
632 *
633 * Using the fb_var_screeninfo in fb_info we set the resolution
634 * of the this particular framebuffer. This function alters the
635 * par AND the fb_fix_screeninfo stored in fb_info. It doesn't
636 * not alter var in fb_info since we are using that data. This
637 * means we depend on the data in var inside fb_info to be
638 * supported by the hardware. atmel_lcdfb_check_var is always called
639 * before atmel_lcdfb_set_par to ensure this. Again if you can't
640 * change the resolution you don't need this function.
641 *
642 */
643static int atmel_lcdfb_set_par(struct fb_info *info)
644{
645 struct atmel_lcdfb_info *sinfo = info->par;
8af2c286 646 struct atmel_lcdfb_pdata *pdata = &sinfo->pdata;
250a269d 647 unsigned long hozval_linesz;
14340586
NF
648 unsigned long value;
649 unsigned long clk_value_khz;
250a269d 650 unsigned long bits_per_line;
431861cf 651 unsigned long pix_factor = 2;
14340586 652
d22579b8
NF
653 might_sleep();
654
14340586
NF
655 dev_dbg(info->device, "%s:\n", __func__);
656 dev_dbg(info->device, " * resolution: %ux%u (%ux%u virtual)\n",
657 info->var.xres, info->var.yres,
658 info->var.xres_virtual, info->var.yres_virtual);
659
3aa04f1b 660 atmel_lcdfb_stop_nowait(sinfo);
14340586 661
250a269d
NF
662 if (info->var.bits_per_pixel == 1)
663 info->fix.visual = FB_VISUAL_MONO01;
664 else if (info->var.bits_per_pixel <= 8)
14340586
NF
665 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
666 else
667 info->fix.visual = FB_VISUAL_TRUECOLOR;
668
250a269d
NF
669 bits_per_line = info->var.xres_virtual * info->var.bits_per_pixel;
670 info->fix.line_length = DIV_ROUND_UP(bits_per_line, 8);
14340586
NF
671
672 /* Re-initialize the DMA engine... */
673 dev_dbg(info->device, " * update DMA engine\n");
674 atmel_lcdfb_update_dma(info, &info->var);
675
676 /* ...set frame size and burst length = 8 words (?) */
677 value = (info->var.yres * info->var.xres * info->var.bits_per_pixel) / 32;
678 value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
679 lcdc_writel(sinfo, ATMEL_LCDC_DMAFRMCFG, value);
680
681 /* Now, the LCDC core... */
682
683 /* Set pixel clock */
bbd44f6b 684 if (sinfo->config->have_alt_pixclock)
431861cf
NF
685 pix_factor = 1;
686
14340586
NF
687 clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000;
688
250a269d 689 value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock));
14340586 690
431861cf 691 if (value < pix_factor) {
14340586
NF
692 dev_notice(info->device, "Bypassing pixel clock divider\n");
693 lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
250a269d 694 } else {
431861cf 695 value = (value / pix_factor) - 1;
baf6332a
NF
696 dev_dbg(info->device, " * programming CLKVAL = 0x%08lx\n",
697 value);
698 lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1,
699 value << ATMEL_LCDC_CLKVAL_OFFSET);
431861cf
NF
700 info->var.pixclock =
701 KHZ2PICOS(clk_value_khz / (pix_factor * (value + 1)));
250a269d
NF
702 dev_dbg(info->device, " updated pixclk: %lu KHz\n",
703 PICOS2KHZ(info->var.pixclock));
704 }
705
14340586
NF
706
707 /* Initialize control register 2 */
8af2c286 708 value = pdata->default_lcdcon2;
14340586
NF
709
710 if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT))
711 value |= ATMEL_LCDC_INVLINE_INVERTED;
712 if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT))
713 value |= ATMEL_LCDC_INVFRAME_INVERTED;
714
715 switch (info->var.bits_per_pixel) {
716 case 1: value |= ATMEL_LCDC_PIXELSIZE_1; break;
717 case 2: value |= ATMEL_LCDC_PIXELSIZE_2; break;
718 case 4: value |= ATMEL_LCDC_PIXELSIZE_4; break;
719 case 8: value |= ATMEL_LCDC_PIXELSIZE_8; break;
720 case 15: /* fall through */
721 case 16: value |= ATMEL_LCDC_PIXELSIZE_16; break;
722 case 24: value |= ATMEL_LCDC_PIXELSIZE_24; break;
723 case 32: value |= ATMEL_LCDC_PIXELSIZE_32; break;
724 default: BUG(); break;
725 }
726 dev_dbg(info->device, " * LCDCON2 = %08lx\n", value);
727 lcdc_writel(sinfo, ATMEL_LCDC_LCDCON2, value);
728
729 /* Vertical timing */
730 value = (info->var.vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
731 value |= info->var.upper_margin << ATMEL_LCDC_VBP_OFFSET;
732 value |= info->var.lower_margin;
733 dev_dbg(info->device, " * LCDTIM1 = %08lx\n", value);
734 lcdc_writel(sinfo, ATMEL_LCDC_TIM1, value);
735
736 /* Horizontal timing */
6b3cbe40 737 value = (info->var.right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
14340586
NF
738 value |= (info->var.hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
739 value |= (info->var.left_margin - 1);
740 dev_dbg(info->device, " * LCDTIM2 = %08lx\n", value);
741 lcdc_writel(sinfo, ATMEL_LCDC_TIM2, value);
742
250a269d 743 /* Horizontal value (aka line size) */
934a50bd 744 hozval_linesz = compute_hozval(sinfo, info->var.xres);
250a269d 745
14340586 746 /* Display size */
250a269d 747 value = (hozval_linesz - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
14340586 748 value |= info->var.yres - 1;
250a269d 749 dev_dbg(info->device, " * LCDFRMCFG = %08lx\n", value);
14340586
NF
750 lcdc_writel(sinfo, ATMEL_LCDC_LCDFRMCFG, value);
751
752 /* FIFO Threshold: Use formula from data sheet */
753 value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
754 lcdc_writel(sinfo, ATMEL_LCDC_FIFO, value);
755
756 /* Toggle LCD_MODE every frame */
757 lcdc_writel(sinfo, ATMEL_LCDC_MVAL, 0);
758
759 /* Disable all interrupts */
760 lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
d22579b8
NF
761 /* Enable FIFO & DMA errors */
762 lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
14340586 763
14340586
NF
764 /* ...wait for DMA engine to become idle... */
765 while (lcdc_readl(sinfo, ATMEL_LCDC_DMACON) & ATMEL_LCDC_DMABUSY)
766 msleep(10);
767
3aa04f1b 768 atmel_lcdfb_start(sinfo);
14340586
NF
769
770 dev_dbg(info->device, " * DONE\n");
771
772 return 0;
773}
774
775static inline unsigned int chan_to_field(unsigned int chan, const struct fb_bitfield *bf)
776{
777 chan &= 0xffff;
778 chan >>= 16 - bf->length;
779 return chan << bf->offset;
780}
781
782/**
783 * atmel_lcdfb_setcolreg - Optional function. Sets a color register.
784 * @regno: Which register in the CLUT we are programming
785 * @red: The red value which can be up to 16 bits wide
786 * @green: The green value which can be up to 16 bits wide
787 * @blue: The blue value which can be up to 16 bits wide.
788 * @transp: If supported the alpha value which can be up to 16 bits wide.
789 * @info: frame buffer info structure
790 *
791 * Set a single color register. The values supplied have a 16 bit
792 * magnitude which needs to be scaled in this function for the hardware.
793 * Things to take into consideration are how many color registers, if
794 * any, are supported with the current color visual. With truecolor mode
25985edc 795 * no color palettes are supported. Here a pseudo palette is created
14340586
NF
796 * which we store the value in pseudo_palette in struct fb_info. For
797 * pseudocolor mode we have a limited color palette. To deal with this
798 * we can program what color is displayed for a particular pixel value.
799 * DirectColor is similar in that we can program each color field. If
800 * we have a static colormap we don't need to implement this function.
801 *
802 * Returns negative errno on error, or zero on success. In an
803 * ideal world, this would have been the case, but as it turns
804 * out, the other drivers return 1 on failure, so that's what
805 * we're going to do.
806 */
807static int atmel_lcdfb_setcolreg(unsigned int regno, unsigned int red,
808 unsigned int green, unsigned int blue,
809 unsigned int transp, struct fb_info *info)
810{
811 struct atmel_lcdfb_info *sinfo = info->par;
8af2c286 812 struct atmel_lcdfb_pdata *pdata = &sinfo->pdata;
14340586
NF
813 unsigned int val;
814 u32 *pal;
815 int ret = 1;
816
817 if (info->var.grayscale)
818 red = green = blue = (19595 * red + 38470 * green
819 + 7471 * blue) >> 16;
820
821 switch (info->fix.visual) {
822 case FB_VISUAL_TRUECOLOR:
823 if (regno < 16) {
824 pal = info->pseudo_palette;
825
826 val = chan_to_field(red, &info->var.red);
827 val |= chan_to_field(green, &info->var.green);
828 val |= chan_to_field(blue, &info->var.blue);
829
830 pal[regno] = val;
831 ret = 0;
832 }
833 break;
834
835 case FB_VISUAL_PSEUDOCOLOR:
836 if (regno < 256) {
bbd44f6b 837 if (sinfo->config->have_intensity_bit) {
5d67b89c
PK
838 /* old style I+BGR:555 */
839 val = ((red >> 11) & 0x001f);
840 val |= ((green >> 6) & 0x03e0);
841 val |= ((blue >> 1) & 0x7c00);
842
843 /*
844 * TODO: intensity bit. Maybe something like
845 * ~(red[10] ^ green[10] ^ blue[10]) & 1
846 */
847 } else {
848 /* new style BGR:565 / RGB:565 */
8af2c286 849 if (pdata->lcd_wiring_mode == ATMEL_LCDC_WIRING_RGB) {
5d67b89c
PK
850 val = ((blue >> 11) & 0x001f);
851 val |= ((red >> 0) & 0xf800);
852 } else {
853 val = ((red >> 11) & 0x001f);
854 val |= ((blue >> 0) & 0xf800);
855 }
856
857 val |= ((green >> 5) & 0x07e0);
858 }
14340586
NF
859
860 lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
861 ret = 0;
862 }
863 break;
250a269d
NF
864
865 case FB_VISUAL_MONO01:
866 if (regno < 2) {
867 val = (regno == 0) ? 0x00 : 0x1F;
868 lcdc_writel(sinfo, ATMEL_LCDC_LUT(regno), val);
869 ret = 0;
870 }
871 break;
872
14340586
NF
873 }
874
875 return ret;
876}
877
878static int atmel_lcdfb_pan_display(struct fb_var_screeninfo *var,
879 struct fb_info *info)
880{
881 dev_dbg(info->device, "%s\n", __func__);
882
883 atmel_lcdfb_update_dma(info, var);
884
885 return 0;
886}
887
bed7bddb
AB
888static int atmel_lcdfb_blank(int blank_mode, struct fb_info *info)
889{
890 struct atmel_lcdfb_info *sinfo = info->par;
891
892 switch (blank_mode) {
893 case FB_BLANK_UNBLANK:
894 case FB_BLANK_NORMAL:
895 atmel_lcdfb_start(sinfo);
896 break;
897 case FB_BLANK_VSYNC_SUSPEND:
898 case FB_BLANK_HSYNC_SUSPEND:
899 break;
900 case FB_BLANK_POWERDOWN:
901 atmel_lcdfb_stop(sinfo);
902 break;
903 default:
904 return -EINVAL;
905 }
906
907 /* let fbcon do a soft blank for us */
908 return ((blank_mode == FB_BLANK_NORMAL) ? 1 : 0);
909}
910
14340586
NF
911static struct fb_ops atmel_lcdfb_ops = {
912 .owner = THIS_MODULE,
913 .fb_check_var = atmel_lcdfb_check_var,
914 .fb_set_par = atmel_lcdfb_set_par,
915 .fb_setcolreg = atmel_lcdfb_setcolreg,
bed7bddb 916 .fb_blank = atmel_lcdfb_blank,
14340586
NF
917 .fb_pan_display = atmel_lcdfb_pan_display,
918 .fb_fillrect = cfb_fillrect,
919 .fb_copyarea = cfb_copyarea,
920 .fb_imageblit = cfb_imageblit,
921};
922
923static irqreturn_t atmel_lcdfb_interrupt(int irq, void *dev_id)
924{
925 struct fb_info *info = dev_id;
926 struct atmel_lcdfb_info *sinfo = info->par;
927 u32 status;
928
929 status = lcdc_readl(sinfo, ATMEL_LCDC_ISR);
d22579b8
NF
930 if (status & ATMEL_LCDC_UFLWI) {
931 dev_warn(info->device, "FIFO underflow %#x\n", status);
932 /* reset DMA and FIFO to avoid screen shifting */
933 schedule_work(&sinfo->task);
934 }
935 lcdc_writel(sinfo, ATMEL_LCDC_ICR, status);
14340586
NF
936 return IRQ_HANDLED;
937}
938
d22579b8
NF
939/*
940 * LCD controller task (to reset the LCD)
941 */
942static void atmel_lcdfb_task(struct work_struct *work)
943{
944 struct atmel_lcdfb_info *sinfo =
945 container_of(work, struct atmel_lcdfb_info, task);
946
947 atmel_lcdfb_reset(sinfo);
948}
949
14340586
NF
950static int __init atmel_lcdfb_init_fbinfo(struct atmel_lcdfb_info *sinfo)
951{
952 struct fb_info *info = sinfo->info;
953 int ret = 0;
954
14340586
NF
955 info->var.activate |= FB_ACTIVATE_FORCE | FB_ACTIVATE_NOW;
956
957 dev_info(info->device,
958 "%luKiB frame buffer at %08lx (mapped at %p)\n",
959 (unsigned long)info->fix.smem_len / 1024,
960 (unsigned long)info->fix.smem_start,
961 info->screen_base);
962
963 /* Allocate colormap */
964 ret = fb_alloc_cmap(&info->cmap, 256, 0);
965 if (ret < 0)
966 dev_err(info->device, "Alloc color map failed\n");
967
968 return ret;
969}
970
971static void atmel_lcdfb_start_clock(struct atmel_lcdfb_info *sinfo)
972{
6e665fb3
BB
973 clk_prepare_enable(sinfo->bus_clk);
974 clk_prepare_enable(sinfo->lcdc_clk);
14340586
NF
975}
976
977static void atmel_lcdfb_stop_clock(struct atmel_lcdfb_info *sinfo)
978{
6e665fb3
BB
979 clk_disable_unprepare(sinfo->bus_clk);
980 clk_disable_unprepare(sinfo->lcdc_clk);
14340586
NF
981}
982
b985172b
JCPV
983#ifdef CONFIG_OF
984static const struct of_device_id atmel_lcdfb_dt_ids[] = {
985 { .compatible = "atmel,at91sam9261-lcdc" , .data = &at91sam9261_config, },
986 { .compatible = "atmel,at91sam9263-lcdc" , .data = &at91sam9263_config, },
987 { .compatible = "atmel,at91sam9g10-lcdc" , .data = &at91sam9g10_config, },
988 { .compatible = "atmel,at91sam9g45-lcdc" , .data = &at91sam9g45_config, },
989 { .compatible = "atmel,at91sam9g45es-lcdc" , .data = &at91sam9g45es_config, },
990 { .compatible = "atmel,at91sam9rl-lcdc" , .data = &at91sam9rl_config, },
991 { .compatible = "atmel,at32ap-lcdc" , .data = &at32ap_config, },
992 { /* sentinel */ }
993};
994
995MODULE_DEVICE_TABLE(of, atmel_lcdfb_dt_ids);
996
997static const char *atmel_lcdfb_wiring_modes[] = {
998 [ATMEL_LCDC_WIRING_BGR] = "BRG",
999 [ATMEL_LCDC_WIRING_RGB] = "RGB",
1000};
1001
cb73b40e 1002static int atmel_lcdfb_get_of_wiring_modes(struct device_node *np)
b985172b
JCPV
1003{
1004 const char *mode;
1005 int err, i;
1006
1007 err = of_property_read_string(np, "atmel,lcd-wiring-mode", &mode);
1008 if (err < 0)
1009 return ATMEL_LCDC_WIRING_BGR;
1010
1011 for (i = 0; i < ARRAY_SIZE(atmel_lcdfb_wiring_modes); i++)
1012 if (!strcasecmp(mode, atmel_lcdfb_wiring_modes[i]))
1013 return i;
1014
1015 return -ENODEV;
1016}
1017
1018static void atmel_lcdfb_power_control_gpio(struct atmel_lcdfb_pdata *pdata, int on)
1019{
1020 struct atmel_lcdfb_power_ctrl_gpio *og;
1021
1022 list_for_each_entry(og, &pdata->pwr_gpios, list)
1023 gpio_set_value(og->gpio, on);
1024}
1025
1026static int atmel_lcdfb_of_init(struct atmel_lcdfb_info *sinfo)
1027{
1028 struct fb_info *info = sinfo->info;
1029 struct atmel_lcdfb_pdata *pdata = &sinfo->pdata;
1030 struct fb_var_screeninfo *var = &info->var;
1031 struct device *dev = &sinfo->pdev->dev;
1032 struct device_node *np =dev->of_node;
1033 struct device_node *display_np;
1034 struct device_node *timings_np;
1035 struct display_timings *timings;
1036 enum of_gpio_flags flags;
1037 struct atmel_lcdfb_power_ctrl_gpio *og;
1038 bool is_gpio_power = false;
1039 int ret = -ENOENT;
1040 int i, gpio;
1041
1042 sinfo->config = (struct atmel_lcdfb_config*)
1043 of_match_device(atmel_lcdfb_dt_ids, dev)->data;
1044
1045 display_np = of_parse_phandle(np, "display", 0);
1046 if (!display_np) {
1047 dev_err(dev, "failed to find display phandle\n");
1048 return -ENOENT;
1049 }
1050
1051 ret = of_property_read_u32(display_np, "bits-per-pixel", &var->bits_per_pixel);
1052 if (ret < 0) {
1053 dev_err(dev, "failed to get property bits-per-pixel\n");
1054 goto put_display_node;
1055 }
1056
1057 ret = of_property_read_u32(display_np, "atmel,guard-time", &pdata->guard_time);
1058 if (ret < 0) {
1059 dev_err(dev, "failed to get property atmel,guard-time\n");
1060 goto put_display_node;
1061 }
1062
1063 ret = of_property_read_u32(display_np, "atmel,lcdcon2", &pdata->default_lcdcon2);
1064 if (ret < 0) {
1065 dev_err(dev, "failed to get property atmel,lcdcon2\n");
1066 goto put_display_node;
1067 }
1068
1069 ret = of_property_read_u32(display_np, "atmel,dmacon", &pdata->default_dmacon);
1070 if (ret < 0) {
1071 dev_err(dev, "failed to get property bits-per-pixel\n");
1072 goto put_display_node;
1073 }
1074
4bc8cad5 1075 INIT_LIST_HEAD(&pdata->pwr_gpios);
b985172b
JCPV
1076 ret = -ENOMEM;
1077 for (i = 0; i < of_gpio_named_count(display_np, "atmel,power-control-gpio"); i++) {
1078 gpio = of_get_named_gpio_flags(display_np, "atmel,power-control-gpio",
1079 i, &flags);
1080 if (gpio < 0)
1081 continue;
1082
1083 og = devm_kzalloc(dev, sizeof(*og), GFP_KERNEL);
1084 if (!og)
1085 goto put_display_node;
1086
1087 og->gpio = gpio;
1088 og->active_low = flags & OF_GPIO_ACTIVE_LOW;
1089 is_gpio_power = true;
1090 ret = devm_gpio_request(dev, gpio, "lcd-power-control-gpio");
1091 if (ret) {
1092 dev_err(dev, "request gpio %d failed\n", gpio);
1093 goto put_display_node;
1094 }
1095
1096 ret = gpio_direction_output(gpio, og->active_low);
1097 if (ret) {
1098 dev_err(dev, "set direction output gpio %d failed\n", gpio);
1099 goto put_display_node;
1100 }
4bc8cad5 1101 list_add(&og->list, &pdata->pwr_gpios);
b985172b
JCPV
1102 }
1103
1104 if (is_gpio_power)
1105 pdata->atmel_lcdfb_power_control = atmel_lcdfb_power_control_gpio;
1106
1107 ret = atmel_lcdfb_get_of_wiring_modes(display_np);
1108 if (ret < 0) {
1109 dev_err(dev, "invalid atmel,lcd-wiring-mode\n");
1110 goto put_display_node;
1111 }
1112 pdata->lcd_wiring_mode = ret;
1113
1114 pdata->lcdcon_is_backlight = of_property_read_bool(display_np, "atmel,lcdcon-backlight");
d7aa64c3 1115 pdata->lcdcon_pol_negative = of_property_read_bool(display_np, "atmel,lcdcon-backlight-inverted");
b985172b
JCPV
1116
1117 timings = of_get_display_timings(display_np);
1118 if (!timings) {
1119 dev_err(dev, "failed to get display timings\n");
6c131850 1120 ret = -EINVAL;
b985172b
JCPV
1121 goto put_display_node;
1122 }
1123
1124 timings_np = of_find_node_by_name(display_np, "display-timings");
1125 if (!timings_np) {
1126 dev_err(dev, "failed to find display-timings node\n");
6c131850 1127 ret = -ENODEV;
b985172b
JCPV
1128 goto put_display_node;
1129 }
1130
1131 for (i = 0; i < of_get_child_count(timings_np); i++) {
1132 struct videomode vm;
1133 struct fb_videomode fb_vm;
1134
1135 ret = videomode_from_timings(timings, &vm, i);
1136 if (ret < 0)
1137 goto put_timings_node;
1138 ret = fb_videomode_from_videomode(&vm, &fb_vm);
1139 if (ret < 0)
1140 goto put_timings_node;
1141
1142 fb_add_videomode(&fb_vm, &info->modelist);
1143 }
1144
1145 return 0;
1146
1147put_timings_node:
1148 of_node_put(timings_np);
1149put_display_node:
1150 of_node_put(display_np);
1151 return ret;
1152}
1153#else
1154static int atmel_lcdfb_of_init(struct atmel_lcdfb_info *sinfo)
1155{
1156 return 0;
1157}
1158#endif
14340586
NF
1159
1160static int __init atmel_lcdfb_probe(struct platform_device *pdev)
1161{
1162 struct device *dev = &pdev->dev;
1163 struct fb_info *info;
1164 struct atmel_lcdfb_info *sinfo;
b985172b 1165 struct atmel_lcdfb_pdata *pdata = NULL;
14340586
NF
1166 struct resource *regs = NULL;
1167 struct resource *map = NULL;
b985172b 1168 struct fb_modelist *modelist;
14340586
NF
1169 int ret;
1170
1171 dev_dbg(dev, "%s BEGIN\n", __func__);
1172
1173 ret = -ENOMEM;
1174 info = framebuffer_alloc(sizeof(struct atmel_lcdfb_info), dev);
1175 if (!info) {
1176 dev_err(dev, "cannot allocate memory\n");
1177 goto out;
1178 }
1179
1180 sinfo = info->par;
b985172b
JCPV
1181 sinfo->pdev = pdev;
1182 sinfo->info = info;
1183
1184 INIT_LIST_HEAD(&info->modelist);
1185
1186 if (pdev->dev.of_node) {
1187 ret = atmel_lcdfb_of_init(sinfo);
1188 if (ret)
1189 goto free_info;
1190 } else if (dev_get_platdata(dev)) {
1191 struct fb_monspecs *monspecs;
1192 int i;
14340586 1193
8af2c286 1194 pdata = dev_get_platdata(dev);
b985172b 1195 monspecs = pdata->default_monspecs;
8af2c286 1196 sinfo->pdata = *pdata;
b985172b
JCPV
1197
1198 for (i = 0; i < monspecs->modedb_len; i++)
1199 fb_add_videomode(&monspecs->modedb[i], &info->modelist);
1200
1201 sinfo->config = atmel_lcdfb_get_config(pdev);
1202
1203 info->var.bits_per_pixel = pdata->default_bpp ? pdata->default_bpp : 16;
1204 memcpy(&info->monspecs, pdata->default_monspecs, sizeof(info->monspecs));
14340586
NF
1205 } else {
1206 dev_err(dev, "cannot get default configuration\n");
1207 goto free_info;
1208 }
b985172b 1209
bbd44f6b
JH
1210 if (!sinfo->config)
1211 goto free_info;
14340586 1212
2d605456
AS
1213 sinfo->reg_lcd = devm_regulator_get(&pdev->dev, "lcd");
1214 if (IS_ERR(sinfo->reg_lcd))
1215 sinfo->reg_lcd = NULL;
1216
14340586
NF
1217 info->flags = ATMEL_LCDFB_FBINFO_DEFAULT;
1218 info->pseudo_palette = sinfo->pseudo_palette;
1219 info->fbops = &atmel_lcdfb_ops;
1220
14340586 1221 info->fix = atmel_lcdfb_fix;
b7e4ab50 1222 strcpy(info->fix.id, sinfo->pdev->name);
14340586
NF
1223
1224 /* Enable LCDC Clocks */
557b7d5d
JH
1225 sinfo->bus_clk = clk_get(dev, "hclk");
1226 if (IS_ERR(sinfo->bus_clk)) {
1227 ret = PTR_ERR(sinfo->bus_clk);
1228 goto free_info;
14340586
NF
1229 }
1230 sinfo->lcdc_clk = clk_get(dev, "lcdc_clk");
1231 if (IS_ERR(sinfo->lcdc_clk)) {
1232 ret = PTR_ERR(sinfo->lcdc_clk);
1233 goto put_bus_clk;
1234 }
1235 atmel_lcdfb_start_clock(sinfo);
1236
b985172b
JCPV
1237 modelist = list_first_entry(&info->modelist,
1238 struct fb_modelist, list);
1239 fb_videomode_to_var(&info->var, &modelist->mode);
14340586 1240
b985172b 1241 atmel_lcdfb_check_var(&info->var, info);
14340586
NF
1242
1243 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1244 if (!regs) {
1245 dev_err(dev, "resources unusable\n");
1246 ret = -ENXIO;
1247 goto stop_clk;
1248 }
1249
1250 sinfo->irq_base = platform_get_irq(pdev, 0);
1251 if (sinfo->irq_base < 0) {
1252 dev_err(dev, "unable to get irq\n");
1253 ret = sinfo->irq_base;
1254 goto stop_clk;
1255 }
1256
1257 /* Initialize video memory */
1258 map = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1259 if (map) {
1260 /* use a pre-allocated memory buffer */
1261 info->fix.smem_start = map->start;
28f65c11 1262 info->fix.smem_len = resource_size(map);
14340586
NF
1263 if (!request_mem_region(info->fix.smem_start,
1264 info->fix.smem_len, pdev->name)) {
1265 ret = -EBUSY;
1266 goto stop_clk;
1267 }
1268
1e43a203
LR
1269 info->screen_base = ioremap_wc(info->fix.smem_start,
1270 info->fix.smem_len);
130320bf
PST
1271 if (!info->screen_base) {
1272 ret = -ENOMEM;
14340586 1273 goto release_intmem;
130320bf 1274 }
01d3a5e7
HS
1275
1276 /*
1277 * Don't clear the framebuffer -- someone may have set
1278 * up a splash image.
1279 */
14340586 1280 } else {
ff0c2642 1281 /* allocate memory buffer */
14340586
NF
1282 ret = atmel_lcdfb_alloc_video_memory(sinfo);
1283 if (ret < 0) {
1284 dev_err(dev, "cannot allocate framebuffer: %d\n", ret);
1285 goto stop_clk;
1286 }
1287 }
1288
1289 /* LCDC registers */
1290 info->fix.mmio_start = regs->start;
28f65c11 1291 info->fix.mmio_len = resource_size(regs);
14340586
NF
1292
1293 if (!request_mem_region(info->fix.mmio_start,
1294 info->fix.mmio_len, pdev->name)) {
1295 ret = -EBUSY;
1296 goto free_fb;
1297 }
1298
1299 sinfo->mmio = ioremap(info->fix.mmio_start, info->fix.mmio_len);
1300 if (!sinfo->mmio) {
1301 dev_err(dev, "cannot map LCDC registers\n");
130320bf 1302 ret = -ENOMEM;
14340586
NF
1303 goto release_mem;
1304 }
1305
a9a84c37
DB
1306 /* Initialize PWM for contrast or backlight ("off") */
1307 init_contrast(sinfo);
1308
14340586
NF
1309 /* interrupt */
1310 ret = request_irq(sinfo->irq_base, atmel_lcdfb_interrupt, 0, pdev->name, info);
1311 if (ret) {
1312 dev_err(dev, "request_irq failed: %d\n", ret);
1313 goto unmap_mmio;
1314 }
1315
d22579b8
NF
1316 /* Some operations on the LCDC might sleep and
1317 * require a preemptible task context */
1318 INIT_WORK(&sinfo->task, atmel_lcdfb_task);
1319
14340586
NF
1320 ret = atmel_lcdfb_init_fbinfo(sinfo);
1321 if (ret < 0) {
1322 dev_err(dev, "init fbinfo failed: %d\n", ret);
1323 goto unregister_irqs;
1324 }
1325
7d3477d8
AT
1326 ret = atmel_lcdfb_set_par(info);
1327 if (ret < 0) {
1328 dev_err(dev, "set par failed: %d\n", ret);
1329 goto unregister_irqs;
1330 }
1331
14340586
NF
1332 dev_set_drvdata(dev, info);
1333
1334 /*
1335 * Tell the world that we're ready to go
1336 */
1337 ret = register_framebuffer(info);
1338 if (ret < 0) {
1339 dev_err(dev, "failed to register framebuffer device: %d\n", ret);
b985172b 1340 goto reset_drvdata;
14340586
NF
1341 }
1342
1343 /* Power up the LCDC screen */
42110e91 1344 atmel_lcdfb_power_control(sinfo, 1);
14340586 1345
93f6ced9 1346 dev_info(dev, "fb%d: Atmel LCDC at 0x%08lx (mapped at %p), irq %d\n",
14340586
NF
1347 info->node, info->fix.mmio_start, sinfo->mmio, sinfo->irq_base);
1348
1349 return 0;
1350
b985172b
JCPV
1351reset_drvdata:
1352 dev_set_drvdata(dev, NULL);
14340586
NF
1353 fb_dealloc_cmap(&info->cmap);
1354unregister_irqs:
d22579b8 1355 cancel_work_sync(&sinfo->task);
14340586
NF
1356 free_irq(sinfo->irq_base, info);
1357unmap_mmio:
a9a84c37 1358 exit_backlight(sinfo);
14340586
NF
1359 iounmap(sinfo->mmio);
1360release_mem:
1361 release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
1362free_fb:
1363 if (map)
1364 iounmap(info->screen_base);
1365 else
1366 atmel_lcdfb_free_video_memory(sinfo);
1367
1368release_intmem:
1369 if (map)
1370 release_mem_region(info->fix.smem_start, info->fix.smem_len);
1371stop_clk:
1372 atmel_lcdfb_stop_clock(sinfo);
1373 clk_put(sinfo->lcdc_clk);
1374put_bus_clk:
557b7d5d 1375 clk_put(sinfo->bus_clk);
14340586
NF
1376free_info:
1377 framebuffer_release(info);
1378out:
1379 dev_dbg(dev, "%s FAILED\n", __func__);
1380 return ret;
1381}
1382
1383static int __exit atmel_lcdfb_remove(struct platform_device *pdev)
1384{
1385 struct device *dev = &pdev->dev;
1386 struct fb_info *info = dev_get_drvdata(dev);
34a35bdd 1387 struct atmel_lcdfb_info *sinfo;
8af2c286 1388 struct atmel_lcdfb_pdata *pdata;
14340586 1389
34a35bdd 1390 if (!info || !info->par)
14340586 1391 return 0;
34a35bdd 1392 sinfo = info->par;
8af2c286 1393 pdata = &sinfo->pdata;
14340586 1394
d22579b8 1395 cancel_work_sync(&sinfo->task);
a9a84c37 1396 exit_backlight(sinfo);
42110e91 1397 atmel_lcdfb_power_control(sinfo, 0);
14340586
NF
1398 unregister_framebuffer(info);
1399 atmel_lcdfb_stop_clock(sinfo);
1400 clk_put(sinfo->lcdc_clk);
557b7d5d 1401 clk_put(sinfo->bus_clk);
14340586
NF
1402 fb_dealloc_cmap(&info->cmap);
1403 free_irq(sinfo->irq_base, info);
1404 iounmap(sinfo->mmio);
1405 release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
1406 if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) {
1407 iounmap(info->screen_base);
1408 release_mem_region(info->fix.smem_start, info->fix.smem_len);
1409 } else {
1410 atmel_lcdfb_free_video_memory(sinfo);
1411 }
1412
14340586
NF
1413 framebuffer_release(info);
1414
1415 return 0;
1416}
1417
cf19a37e
DB
1418#ifdef CONFIG_PM
1419
1420static int atmel_lcdfb_suspend(struct platform_device *pdev, pm_message_t mesg)
1421{
1422 struct fb_info *info = platform_get_drvdata(pdev);
1423 struct atmel_lcdfb_info *sinfo = info->par;
1424
3aa04f1b
HS
1425 /*
1426 * We don't want to handle interrupts while the clock is
1427 * stopped. It may take forever.
1428 */
1429 lcdc_writel(sinfo, ATMEL_LCDC_IDR, ~0UL);
1430
9f106503 1431 sinfo->saved_lcdcon = lcdc_readl(sinfo, ATMEL_LCDC_CONTRAST_CTR);
cf19a37e 1432 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, 0);
42110e91 1433 atmel_lcdfb_power_control(sinfo, 0);
3aa04f1b 1434 atmel_lcdfb_stop(sinfo);
cf19a37e 1435 atmel_lcdfb_stop_clock(sinfo);
3aa04f1b 1436
cf19a37e
DB
1437 return 0;
1438}
1439
1440static int atmel_lcdfb_resume(struct platform_device *pdev)
1441{
1442 struct fb_info *info = platform_get_drvdata(pdev);
1443 struct atmel_lcdfb_info *sinfo = info->par;
1444
1445 atmel_lcdfb_start_clock(sinfo);
3aa04f1b 1446 atmel_lcdfb_start(sinfo);
42110e91 1447 atmel_lcdfb_power_control(sinfo, 1);
cf19a37e 1448 lcdc_writel(sinfo, ATMEL_LCDC_CONTRAST_CTR, sinfo->saved_lcdcon);
3aa04f1b
HS
1449
1450 /* Enable FIFO & DMA errors */
1451 lcdc_writel(sinfo, ATMEL_LCDC_IER, ATMEL_LCDC_UFLWI
1452 | ATMEL_LCDC_OWRI | ATMEL_LCDC_MERI);
1453
cf19a37e
DB
1454 return 0;
1455}
1456
1457#else
1458#define atmel_lcdfb_suspend NULL
1459#define atmel_lcdfb_resume NULL
1460#endif
1461
14340586
NF
1462static struct platform_driver atmel_lcdfb_driver = {
1463 .remove = __exit_p(atmel_lcdfb_remove),
cf19a37e
DB
1464 .suspend = atmel_lcdfb_suspend,
1465 .resume = atmel_lcdfb_resume,
bbd44f6b 1466 .id_table = atmel_lcdfb_devtypes,
14340586
NF
1467 .driver = {
1468 .name = "atmel_lcdfb",
b985172b 1469 .of_match_table = of_match_ptr(atmel_lcdfb_dt_ids),
14340586
NF
1470 },
1471};
1472
3ccbf89f 1473module_platform_driver_probe(atmel_lcdfb_driver, atmel_lcdfb_probe);
14340586
NF
1474
1475MODULE_DESCRIPTION("AT91/AT32 LCD Controller framebuffer driver");
8f4c79ce 1476MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>");
14340586 1477MODULE_LICENSE("GPL");
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