[deliverable/linux.git] / drivers / watchdog / sp5100_tco.c

/*
 *	sp5100_tco :	TCO timer driver for sp5100 chipsets
 *
 *	(c) Copyright 2009 Google Inc., All Rights Reserved.
 *
 *	Based on i8xx_tco.c:
 *	(c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights
 *	Reserved.
 *				http://www.kernelconcepts.de
 *
 *	This program is free software; you can redistribute it and/or
 *	modify it under the terms of the GNU General Public License
 *	as published by the Free Software Foundation; either version
 *	2 of the License, or (at your option) any later version.
 *
 *	See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide",
 *	    AMD Publication 45482 "AMD SB800-Series Southbridges Register
 *	                                                      Reference Guide"
 */

/*
 *	Includes, defines, variables, module parameters, ...
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/init.h>
#include <linux/fs.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <linux/uaccess.h>
#include <linux/io.h>

#include "sp5100_tco.h"

/* Module and version information */
#define TCO_VERSION "0.05"
#define TCO_MODULE_NAME "SP5100 TCO timer"
#define TCO_DRIVER_NAME   TCO_MODULE_NAME ", v" TCO_VERSION

/* internal variables */
static u32 tcobase_phys;
static u32 tco_wdt_fired;
static void __iomem *tcobase;
static unsigned int pm_iobase;
static DEFINE_SPINLOCK(tco_lock);	/* Guards the hardware */
static unsigned long timer_alive;
static char tco_expect_close;
static struct pci_dev *sp5100_tco_pci;

/* the watchdog platform device */
static struct platform_device *sp5100_tco_platform_device;

/* module parameters */

#define WATCHDOG_HEARTBEAT 60	/* 60 sec default heartbeat. */
static int heartbeat = WATCHDOG_HEARTBEAT;  /* in seconds */
module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default="
		 __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started."
		" (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

/*
 * Some TCO specific functions
 */
static void tco_timer_start(void)
{
	u32 val;
	unsigned long flags;

	spin_lock_irqsave(&tco_lock, flags);
	val = readl(SP5100_WDT_CONTROL(tcobase));
	val |= SP5100_WDT_START_STOP_BIT;
	writel(val, SP5100_WDT_CONTROL(tcobase));
	spin_unlock_irqrestore(&tco_lock, flags);
}

static void tco_timer_stop(void)
{
	u32 val;
	unsigned long flags;

	spin_lock_irqsave(&tco_lock, flags);
	val = readl(SP5100_WDT_CONTROL(tcobase));
	val &= ~SP5100_WDT_START_STOP_BIT;
	writel(val, SP5100_WDT_CONTROL(tcobase));
	spin_unlock_irqrestore(&tco_lock, flags);
}

static void tco_timer_keepalive(void)
{
	u32 val;
	unsigned long flags;

	spin_lock_irqsave(&tco_lock, flags);
	val = readl(SP5100_WDT_CONTROL(tcobase));
	val |= SP5100_WDT_TRIGGER_BIT;
	writel(val, SP5100_WDT_CONTROL(tcobase));
	spin_unlock_irqrestore(&tco_lock, flags);
}

static int tco_timer_set_heartbeat(int t)
{
	unsigned long flags;

	if (t < 0 || t > 0xffff)
		return -EINVAL;

	/* Write new heartbeat to watchdog */
	spin_lock_irqsave(&tco_lock, flags);
	writel(t, SP5100_WDT_COUNT(tcobase));
	spin_unlock_irqrestore(&tco_lock, flags);

	heartbeat = t;
	return 0;
}

static void tco_timer_enable(void)
{
	int val;

	if (sp5100_tco_pci->revision >= 0x40) {
		/* For SB800 or later */
		/* Set the Watchdog timer resolution to 1 sec */
		outb(SB800_PM_WATCHDOG_CONFIG, SB800_IO_PM_INDEX_REG);
		val = inb(SB800_IO_PM_DATA_REG);
		val |= SB800_PM_WATCHDOG_SECOND_RES;
		outb(val, SB800_IO_PM_DATA_REG);

		/* Enable watchdog decode bit and watchdog timer */
		outb(SB800_PM_WATCHDOG_CONTROL, SB800_IO_PM_INDEX_REG);
		val = inb(SB800_IO_PM_DATA_REG);
		val |= SB800_PCI_WATCHDOG_DECODE_EN;
		val &= ~SB800_PM_WATCHDOG_DISABLE;
		outb(val, SB800_IO_PM_DATA_REG);
	} else {
		/* For SP5100 or SB7x0 */
		/* Enable watchdog decode bit */
		pci_read_config_dword(sp5100_tco_pci,
				      SP5100_PCI_WATCHDOG_MISC_REG,
				      &val);

		val |= SP5100_PCI_WATCHDOG_DECODE_EN;

		pci_write_config_dword(sp5100_tco_pci,
				       SP5100_PCI_WATCHDOG_MISC_REG,
				       val);

		/* Enable Watchdog timer and set the resolution to 1 sec */
		outb(SP5100_PM_WATCHDOG_CONTROL, SP5100_IO_PM_INDEX_REG);
		val = inb(SP5100_IO_PM_DATA_REG);
		val |= SP5100_PM_WATCHDOG_SECOND_RES;
		val &= ~SP5100_PM_WATCHDOG_DISABLE;
		outb(val, SP5100_IO_PM_DATA_REG);
	}
}

/*
 *	/dev/watchdog handling
 */

static int sp5100_tco_open(struct inode *inode, struct file *file)
{
	/* /dev/watchdog can only be opened once */
	if (test_and_set_bit(0, &timer_alive))
		return -EBUSY;

	/* Reload and activate timer */
	tco_timer_start();
	tco_timer_keepalive();
	return nonseekable_open(inode, file);
}

static int sp5100_tco_release(struct inode *inode, struct file *file)
{
	/* Shut off the timer. */
	if (tco_expect_close == 42) {
		tco_timer_stop();
	} else {
		pr_crit("Unexpected close, not stopping watchdog!\n");
		tco_timer_keepalive();
	}
	clear_bit(0, &timer_alive);
	tco_expect_close = 0;
	return 0;
}

static ssize_t sp5100_tco_write(struct file *file, const char __user *data,
				size_t len, loff_t *ppos)
{
	/* See if we got the magic character 'V' and reload the timer */
	if (len) {
		if (!nowayout) {
			size_t i;

			/* note: just in case someone wrote the magic character
			 * five months ago... */
			tco_expect_close = 0;

			/* scan to see whether or not we got the magic character
			 */
			for (i = 0; i != len; i++) {
				char c;
				if (get_user(c, data + i))
					return -EFAULT;
				if (c == 'V')
					tco_expect_close = 42;
			}
		}

		/* someone wrote to us, we should reload the timer */
		tco_timer_keepalive();
	}
	return len;
}

static long sp5100_tco_ioctl(struct file *file, unsigned int cmd,
			     unsigned long arg)
{
	int new_options, retval = -EINVAL;
	int new_heartbeat;
	void __user *argp = (void __user *)arg;
	int __user *p = argp;
	static const struct watchdog_info ident = {
		.options =		WDIOF_SETTIMEOUT |
					WDIOF_KEEPALIVEPING |
					WDIOF_MAGICCLOSE,
		.firmware_version =	0,
		.identity =		TCO_MODULE_NAME,
	};

	switch (cmd) {
	case WDIOC_GETSUPPORT:
		return copy_to_user(argp, &ident,
			sizeof(ident)) ? -EFAULT : 0;
	case WDIOC_GETSTATUS:
	case WDIOC_GETBOOTSTATUS:
		return put_user(0, p);
	case WDIOC_SETOPTIONS:
		if (get_user(new_options, p))
			return -EFAULT;
		if (new_options & WDIOS_DISABLECARD) {
			tco_timer_stop();
			retval = 0;
		}
		if (new_options & WDIOS_ENABLECARD) {
			tco_timer_start();
			tco_timer_keepalive();
			retval = 0;
		}
		return retval;
	case WDIOC_KEEPALIVE:
		tco_timer_keepalive();
		return 0;
	case WDIOC_SETTIMEOUT:
		if (get_user(new_heartbeat, p))
			return -EFAULT;
		if (tco_timer_set_heartbeat(new_heartbeat))
			return -EINVAL;
		tco_timer_keepalive();
		/* Fall through */
	case WDIOC_GETTIMEOUT:
		return put_user(heartbeat, p);
	default:
		return -ENOTTY;
	}
}

/*
 * Kernel Interfaces
 */

static const struct file_operations sp5100_tco_fops = {
	.owner =		THIS_MODULE,
	.llseek =		no_llseek,
	.write =		sp5100_tco_write,
	.unlocked_ioctl =	sp5100_tco_ioctl,
	.open =			sp5100_tco_open,
	.release =		sp5100_tco_release,
};

static struct miscdevice sp5100_tco_miscdev = {
	.minor =	WATCHDOG_MINOR,
	.name =		"watchdog",
	.fops =		&sp5100_tco_fops,
};

/*
 * Data for PCI driver interface
 *
 * This data only exists for exporting the supported
 * PCI ids via MODULE_DEVICE_TABLE.  We do not actually
 * register a pci_driver, because someone else might
 * want to register another driver on the same PCI id.
 */
static const struct pci_device_id sp5100_tco_pci_tbl[] = {
	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_ANY_ID,
	  PCI_ANY_ID, },
	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, PCI_ANY_ID,
	  PCI_ANY_ID, },
	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
	  PCI_ANY_ID, },
	{ 0, },			/* End of list */
};
MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl);

/*
 * Init & exit routines
 */
static unsigned char sp5100_tco_setupdevice(void)
{
	struct pci_dev *dev = NULL;
	const char *dev_name = NULL;
	u32 val;
	u32 index_reg, data_reg, base_addr;

	/* Match the PCI device */
	for_each_pci_dev(dev) {
		if (pci_match_id(sp5100_tco_pci_tbl, dev) != NULL) {
			sp5100_tco_pci = dev;
			break;
		}
	}

	if (!sp5100_tco_pci)
		return 0;

	pr_info("PCI Vendor ID: 0x%x, Device ID: 0x%x, Revision ID: 0x%x\n",
		sp5100_tco_pci->vendor, sp5100_tco_pci->device,
		sp5100_tco_pci->revision);

	/*
	 * Determine type of southbridge chipset.
	 */
	if (sp5100_tco_pci->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
	    sp5100_tco_pci->revision < 0x40) {
		dev_name = SP5100_DEVNAME;
		index_reg = SP5100_IO_PM_INDEX_REG;
		data_reg = SP5100_IO_PM_DATA_REG;
		base_addr = SP5100_PM_WATCHDOG_BASE;
	} else {
		dev_name = SB800_DEVNAME;
		index_reg = SB800_IO_PM_INDEX_REG;
		data_reg = SB800_IO_PM_DATA_REG;
		base_addr = SB800_PM_WATCHDOG_BASE;
	}

	/* Request the IO ports used by this driver */
	pm_iobase = SP5100_IO_PM_INDEX_REG;
	if (!request_region(pm_iobase, SP5100_PM_IOPORTS_SIZE, dev_name)) {
		pr_err("I/O address 0x%04x already in use\n", pm_iobase);
		goto exit;
	}

	/*
	 * First, Find the watchdog timer MMIO address from indirect I/O.
	 */
	outb(base_addr+3, index_reg);
	val = inb(data_reg);
	outb(base_addr+2, index_reg);
	val = val << 8 | inb(data_reg);
	outb(base_addr+1, index_reg);
	val = val << 8 | inb(data_reg);
	outb(base_addr+0, index_reg);
	/* Low three bits of BASE are reserved */
	val = val << 8 | (inb(data_reg) & 0xf8);

	pr_debug("Got 0x%04x from indirect I/O\n", val);

	/* Check MMIO address conflict */
	if (request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE,
								dev_name))
		goto setup_wdt;
	else
		pr_debug("MMIO address 0x%04x already in use\n", val);

	/*
	 * Secondly, Find the watchdog timer MMIO address
	 * from SBResource_MMIO register.
	 */
	if (sp5100_tco_pci->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
	    sp5100_tco_pci->revision < 0x40) {
		/* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
		pci_read_config_dword(sp5100_tco_pci,
				      SP5100_SB_RESOURCE_MMIO_BASE, &val);
	} else {
		/* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
		outb(SB800_PM_ACPI_MMIO_EN+3, SB800_IO_PM_INDEX_REG);
		val = inb(SB800_IO_PM_DATA_REG);
		outb(SB800_PM_ACPI_MMIO_EN+2, SB800_IO_PM_INDEX_REG);
		val = val << 8 | inb(SB800_IO_PM_DATA_REG);
		outb(SB800_PM_ACPI_MMIO_EN+1, SB800_IO_PM_INDEX_REG);
		val = val << 8 | inb(SB800_IO_PM_DATA_REG);
		outb(SB800_PM_ACPI_MMIO_EN+0, SB800_IO_PM_INDEX_REG);
		val = val << 8 | inb(SB800_IO_PM_DATA_REG);
	}

	/* The SBResource_MMIO is enabled and mapped memory space? */
	if ((val & (SB800_ACPI_MMIO_DECODE_EN | SB800_ACPI_MMIO_SEL)) ==
						  SB800_ACPI_MMIO_DECODE_EN) {
		/* Clear unnecessary the low twelve bits */
		val &= ~0xFFF;
		/* Add the Watchdog Timer offset to base address. */
		val += SB800_PM_WDT_MMIO_OFFSET;
		/* Check MMIO address conflict */
		if (request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE,
								   dev_name)) {
			pr_debug("Got 0x%04x from SBResource_MMIO register\n",
				val);
			goto setup_wdt;
		} else
			pr_debug("MMIO address 0x%04x already in use\n", val);
	} else
		pr_debug("SBResource_MMIO is disabled(0x%04x)\n", val);

	pr_notice("failed to find MMIO address, giving up.\n");
	goto  unreg_region;

setup_wdt:
	tcobase_phys = val;

	tcobase = ioremap(val, SP5100_WDT_MEM_MAP_SIZE);
	if (!tcobase) {
		pr_err("failed to get tcobase address\n");
		goto unreg_mem_region;
	}

	pr_info("Using 0x%04x for watchdog MMIO address\n", val);

	/* Setup the watchdog timer */
	tco_timer_enable();

	/* Check that the watchdog action is set to reset the system */
	val = readl(SP5100_WDT_CONTROL(tcobase));
	/*
	 * Save WatchDogFired status, because WatchDogFired flag is
	 * cleared here.
	 */
	tco_wdt_fired = val & SP5100_PM_WATCHDOG_FIRED;
	val &= ~SP5100_PM_WATCHDOG_ACTION_RESET;
	writel(val, SP5100_WDT_CONTROL(tcobase));

	/* Set a reasonable heartbeat before we stop the timer */
	tco_timer_set_heartbeat(heartbeat);

	/*
	 * Stop the TCO before we change anything so we don't race with
	 * a zeroed timer.
	 */
	tco_timer_stop();

	/* Done */
	return 1;

unreg_mem_region:
	release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE);
unreg_region:
	release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE);
exit:
	return 0;
}

static int sp5100_tco_init(struct platform_device *dev)
{
	int ret;

	/*
	 * Check whether or not the hardware watchdog is there. If found, then
	 * set it up.
	 */
	if (!sp5100_tco_setupdevice())
		return -ENODEV;

	/* Check to see if last reboot was due to watchdog timeout */
	pr_info("Last reboot was %striggered by watchdog.\n",
		tco_wdt_fired ? "" : "not ");

	/*
	 * Check that the heartbeat value is within it's range.
	 * If not, reset to the default.
	 */
	if (tco_timer_set_heartbeat(heartbeat)) {
		heartbeat = WATCHDOG_HEARTBEAT;
		tco_timer_set_heartbeat(heartbeat);
	}

	ret = misc_register(&sp5100_tco_miscdev);
	if (ret != 0) {
		pr_err("cannot register miscdev on minor=%d (err=%d)\n",
		       WATCHDOG_MINOR, ret);
		goto exit;
	}

	clear_bit(0, &timer_alive);

	/* Show module parameters */
	pr_info("initialized (0x%p). heartbeat=%d sec (nowayout=%d)\n",
		tcobase, heartbeat, nowayout);

	return 0;

exit:
	iounmap(tcobase);
	release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE);
	release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE);
	return ret;
}

static void sp5100_tco_cleanup(void)
{
	/* Stop the timer before we leave */
	if (!nowayout)
		tco_timer_stop();

	/* Deregister */
	misc_deregister(&sp5100_tco_miscdev);
	iounmap(tcobase);
	release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE);
	release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE);
}

static int sp5100_tco_remove(struct platform_device *dev)
{
	if (tcobase)
		sp5100_tco_cleanup();
	return 0;
}

static void sp5100_tco_shutdown(struct platform_device *dev)
{
	tco_timer_stop();
}

static struct platform_driver sp5100_tco_driver = {
	.probe		= sp5100_tco_init,
	.remove		= sp5100_tco_remove,
	.shutdown	= sp5100_tco_shutdown,
	.driver		= {
		.name	= TCO_MODULE_NAME,
	},
};

static int __init sp5100_tco_init_module(void)
{
	int err;

	pr_info("SP5100/SB800 TCO WatchDog Timer Driver v%s\n", TCO_VERSION);

	err = platform_driver_register(&sp5100_tco_driver);
	if (err)
		return err;

	sp5100_tco_platform_device = platform_device_register_simple(
					TCO_MODULE_NAME, -1, NULL, 0);
	if (IS_ERR(sp5100_tco_platform_device)) {
		err = PTR_ERR(sp5100_tco_platform_device);
		goto unreg_platform_driver;
	}

	return 0;

unreg_platform_driver:
	platform_driver_unregister(&sp5100_tco_driver);
	return err;
}

static void __exit sp5100_tco_cleanup_module(void)
{
	platform_device_unregister(sp5100_tco_platform_device);
	platform_driver_unregister(&sp5100_tco_driver);
	pr_info("SP5100/SB800 TCO Watchdog Module Unloaded\n");
}

module_init(sp5100_tco_init_module);
module_exit(sp5100_tco_cleanup_module);

MODULE_AUTHOR("Priyanka Gupta");
MODULE_DESCRIPTION("TCO timer driver for SP5100/SB800 chipset");
MODULE_LICENSE("GPL");
Commit	Line	Data
15e28bf1 PG	1	/*
	2	* sp5100_tco : TCO timer driver for sp5100 chipsets
	3	*
	4	* (c) Copyright 2009 Google Inc., All Rights Reserved.
	5	*
	6	* Based on i8xx_tco.c:
	7	* (c) Copyright 2000 kernel concepts <nils@kernelconcepts.de>, All Rights
	8	* Reserved.
	9	* http://www.kernelconcepts.de
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License
	13	* as published by the Free Software Foundation; either version
	14	* 2 of the License, or (at your option) any later version.
	15	*
740fbddf TT	16	* See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide",
	17	* AMD Publication 45482 "AMD SB800-Series Southbridges Register
	18	* Reference Guide"
15e28bf1 PG	19	*/
	20
	21	/*
	22	* Includes, defines, variables, module parameters, ...
	23	*/
	24
27c766aa JP	25	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27c766aa JP	26
15e28bf1 PG	27	#include <linux/module.h>
	28	#include <linux/moduleparam.h>
	29	#include <linux/types.h>
	30	#include <linux/miscdevice.h>
	31	#include <linux/watchdog.h>
	32	#include <linux/init.h>
	33	#include <linux/fs.h>
	34	#include <linux/pci.h>
	35	#include <linux/ioport.h>
	36	#include <linux/platform_device.h>
	37	#include <linux/uaccess.h>
	38	#include <linux/io.h>
	39
	40	#include "sp5100_tco.h"
	41
	42	/* Module and version information */
18e43212	43	#define TCO_VERSION "0.05"
15e28bf1 PG	44	#define TCO_MODULE_NAME "SP5100 TCO timer"
15e28bf1 PG	45	#define TCO_DRIVER_NAME TCO_MODULE_NAME ", v" TCO_VERSION
15e28bf1 PG	46
15e28bf1 PG	47	/* internal variables */
90d241ed	48	static u32 tcobase_phys;
740fbddf	49	static u32 tco_wdt_fired;
15e28bf1 PG	50	static void __iomem *tcobase;
	51	static unsigned int pm_iobase;
	52	static DEFINE_SPINLOCK(tco_lock); /* Guards the hardware */
	53	static unsigned long timer_alive;
	54	static char tco_expect_close;
	55	static struct pci_dev *sp5100_tco_pci;
	56
	57	/* the watchdog platform device */
	58	static struct platform_device *sp5100_tco_platform_device;
	59
	60	/* module parameters */
	61
	62	#define WATCHDOG_HEARTBEAT 60 /* 60 sec default heartbeat. */
	63	static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
	64	module_param(heartbeat, int, 0);
	65	MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default="
	66	__MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
	67
86a1e189 WVS	68	static bool nowayout = WATCHDOG_NOWAYOUT;
86a1e189 WVS	69	module_param(nowayout, bool, 0);
740fbddf	70	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started."
15e28bf1 PG	71	" (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	72
	73	/*
	74	* Some TCO specific functions
	75	*/
	76	static void tco_timer_start(void)
	77	{
	78	u32 val;
	79	unsigned long flags;
	80
	81	spin_lock_irqsave(&tco_lock, flags);
	82	val = readl(SP5100_WDT_CONTROL(tcobase));
	83	val \|= SP5100_WDT_START_STOP_BIT;
	84	writel(val, SP5100_WDT_CONTROL(tcobase));
	85	spin_unlock_irqrestore(&tco_lock, flags);
	86	}
	87
	88	static void tco_timer_stop(void)
	89	{
	90	u32 val;
	91	unsigned long flags;
	92
	93	spin_lock_irqsave(&tco_lock, flags);
	94	val = readl(SP5100_WDT_CONTROL(tcobase));
	95	val &= ~SP5100_WDT_START_STOP_BIT;
	96	writel(val, SP5100_WDT_CONTROL(tcobase));
	97	spin_unlock_irqrestore(&tco_lock, flags);
	98	}
	99
	100	static void tco_timer_keepalive(void)
	101	{
	102	u32 val;
	103	unsigned long flags;
	104
	105	spin_lock_irqsave(&tco_lock, flags);
	106	val = readl(SP5100_WDT_CONTROL(tcobase));
	107	val \|= SP5100_WDT_TRIGGER_BIT;
	108	writel(val, SP5100_WDT_CONTROL(tcobase));
	109	spin_unlock_irqrestore(&tco_lock, flags);
	110	}
	111
	112	static int tco_timer_set_heartbeat(int t)
	113	{
	114	unsigned long flags;
	115
	116	if (t < 0 \|\| t > 0xffff)
	117	return -EINVAL;
	118
	119	/* Write new heartbeat to watchdog */
	120	spin_lock_irqsave(&tco_lock, flags);
	121	writel(t, SP5100_WDT_COUNT(tcobase));
	122	spin_unlock_irqrestore(&tco_lock, flags);
	123
	124	heartbeat = t;
	125	return 0;
	126	}
	127
740fbddf TT	128	static void tco_timer_enable(void)
	129	{
	130	int val;
	131
	132	if (sp5100_tco_pci->revision >= 0x40) {
	133	/* For SB800 or later */
	134	/* Set the Watchdog timer resolution to 1 sec */
	135	outb(SB800_PM_WATCHDOG_CONFIG, SB800_IO_PM_INDEX_REG);
	136	val = inb(SB800_IO_PM_DATA_REG);
	137	val \|= SB800_PM_WATCHDOG_SECOND_RES;
	138	outb(val, SB800_IO_PM_DATA_REG);
	139
	140	/* Enable watchdog decode bit and watchdog timer */
	141	outb(SB800_PM_WATCHDOG_CONTROL, SB800_IO_PM_INDEX_REG);
	142	val = inb(SB800_IO_PM_DATA_REG);
	143	val \|= SB800_PCI_WATCHDOG_DECODE_EN;
	144	val &= ~SB800_PM_WATCHDOG_DISABLE;
	145	outb(val, SB800_IO_PM_DATA_REG);
	146	} else {
	147	/* For SP5100 or SB7x0 */
	148	/* Enable watchdog decode bit */
	149	pci_read_config_dword(sp5100_tco_pci,
	150	SP5100_PCI_WATCHDOG_MISC_REG,
	151	&val);
	152
	153	val \|= SP5100_PCI_WATCHDOG_DECODE_EN;
	154
	155	pci_write_config_dword(sp5100_tco_pci,
	156	SP5100_PCI_WATCHDOG_MISC_REG,
	157	val);
	158
	159	/* Enable Watchdog timer and set the resolution to 1 sec */
	160	outb(SP5100_PM_WATCHDOG_CONTROL, SP5100_IO_PM_INDEX_REG);
	161	val = inb(SP5100_IO_PM_DATA_REG);
	162	val \|= SP5100_PM_WATCHDOG_SECOND_RES;
	163	val &= ~SP5100_PM_WATCHDOG_DISABLE;
	164	outb(val, SP5100_IO_PM_DATA_REG);
	165	}
	166	}
	167
15e28bf1 PG	168	/*
	169	* /dev/watchdog handling
	170	*/
	171
	172	static int sp5100_tco_open(struct inode inode, struct file file)
	173	{
	174	/* /dev/watchdog can only be opened once */
	175	if (test_and_set_bit(0, &timer_alive))
	176	return -EBUSY;
	177
	178	/* Reload and activate timer */
	179	tco_timer_start();
	180	tco_timer_keepalive();
	181	return nonseekable_open(inode, file);
	182	}
	183
	184	static int sp5100_tco_release(struct inode inode, struct file file)
	185	{
	186	/* Shut off the timer. */
	187	if (tco_expect_close == 42) {
	188	tco_timer_stop();
	189	} else {
27c766aa	190	pr_crit("Unexpected close, not stopping watchdog!\n");
15e28bf1 PG	191	tco_timer_keepalive();
	192	}
	193	clear_bit(0, &timer_alive);
	194	tco_expect_close = 0;
	195	return 0;
	196	}
	197
	198	static ssize_t sp5100_tco_write(struct file file, const char __user data,
	199	size_t len, loff_t *ppos)
	200	{
	201	/* See if we got the magic character 'V' and reload the timer */
	202	if (len) {
	203	if (!nowayout) {
	204	size_t i;
	205
	206	/* note: just in case someone wrote the magic character
	207	* five months ago... */
	208	tco_expect_close = 0;
	209
	210	/* scan to see whether or not we got the magic character
	211	*/
	212	for (i = 0; i != len; i++) {
	213	char c;
	214	if (get_user(c, data + i))
	215	return -EFAULT;
	216	if (c == 'V')
	217	tco_expect_close = 42;
	218	}
	219	}
	220
	221	/* someone wrote to us, we should reload the timer */
	222	tco_timer_keepalive();
	223	}
	224	return len;
	225	}
	226
	227	static long sp5100_tco_ioctl(struct file *file, unsigned int cmd,
	228	unsigned long arg)
	229	{
	230	int new_options, retval = -EINVAL;
	231	int new_heartbeat;
	232	void __user argp = (void __user )arg;
	233	int __user *p = argp;
	234	static const struct watchdog_info ident = {
	235	.options = WDIOF_SETTIMEOUT \|
	236	WDIOF_KEEPALIVEPING \|
	237	WDIOF_MAGICCLOSE,
	238	.firmware_version = 0,
	239	.identity = TCO_MODULE_NAME,
	240	};
	241
	242	switch (cmd) {
	243	case WDIOC_GETSUPPORT:
	244	return copy_to_user(argp, &ident,
	245	sizeof(ident)) ? -EFAULT : 0;
	246	case WDIOC_GETSTATUS:
	247	case WDIOC_GETBOOTSTATUS:
	248	return put_user(0, p);
	249	case WDIOC_SETOPTIONS:
	250	if (get_user(new_options, p))
	251	return -EFAULT;
	252	if (new_options & WDIOS_DISABLECARD) {
	253	tco_timer_stop();
	254	retval = 0;
255	}
256	if (new_options & WDIOS_ENABLECARD) {
257	tco_timer_start();
258	tco_timer_keepalive();
259	retval = 0;
260	}
261	return retval;
262	case WDIOC_KEEPALIVE:
263	tco_timer_keepalive();
264	return 0;
265	case WDIOC_SETTIMEOUT:
266	if (get_user(new_heartbeat, p))
267	return -EFAULT;
268	if (tco_timer_set_heartbeat(new_heartbeat))
269	return -EINVAL;
270	tco_timer_keepalive();
271	/* Fall through */
272	case WDIOC_GETTIMEOUT:
273	return put_user(heartbeat, p);
274	default:
275	return -ENOTTY;
276	}
277	}
278
279	/*
280	* Kernel Interfaces
281	*/
282
283	static const struct file_operations sp5100_tco_fops = {
284	.owner = THIS_MODULE,
285	.llseek = no_llseek,
286	.write = sp5100_tco_write,
287	.unlocked_ioctl = sp5100_tco_ioctl,
288	.open = sp5100_tco_open,
289	.release = sp5100_tco_release,
290	};
291
292	static struct miscdevice sp5100_tco_miscdev = {
293	.minor = WATCHDOG_MINOR,
294	.name = "watchdog",
295	.fops = &sp5100_tco_fops,
296	};
297
298	/*
299	* Data for PCI driver interface
300	*
301	* This data only exists for exporting the supported
302	* PCI ids via MODULE_DEVICE_TABLE. We do not actually
303	* register a pci_driver, because someone else might
304	* want to register another driver on the same PCI id.
305	*/
bc17f9dc	306	static const struct pci_device_id sp5100_tco_pci_tbl[] = {
15e28bf1 PG	307	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_ANY_ID,
15e28bf1 PG	308	PCI_ANY_ID, },
190aa430 DT	309	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, PCI_ANY_ID,
190aa430 DT	310	PCI_ANY_ID, },
cca118fa HR	311	{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
cca118fa HR	312	PCI_ANY_ID, },
15e28bf1 PG	313	{ 0, }, /* End of list */
	314	};
	315	MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl);
	316
	317	/*
	318	* Init & exit routines
	319	*/
2d991a16	320	static unsigned char sp5100_tco_setupdevice(void)
15e28bf1 PG	321	{
15e28bf1 PG	322	struct pci_dev *dev = NULL;
740fbddf	323	const char *dev_name = NULL;
18e43212	324	u32 val;
740fbddf	325	u32 index_reg, data_reg, base_addr;
15e28bf1 PG	326
	327	/* Match the PCI device */
	328	for_each_pci_dev(dev) {
	329	if (pci_match_id(sp5100_tco_pci_tbl, dev) != NULL) {
	330	sp5100_tco_pci = dev;
	331	break;
	332	}
	333	}
	334
	335	if (!sp5100_tco_pci)
	336	return 0;
	337
bdecfcdb HR	338	pr_info("PCI Vendor ID: 0x%x, Device ID: 0x%x, Revision ID: 0x%x\n",
	339	sp5100_tco_pci->vendor, sp5100_tco_pci->device,
	340	sp5100_tco_pci->revision);
740fbddf TT	341
	342	/*
	343	* Determine type of southbridge chipset.
	344	*/
bdecfcdb HR	345	if (sp5100_tco_pci->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
bdecfcdb HR	346	sp5100_tco_pci->revision < 0x40) {
740fbddf TT	347	dev_name = SP5100_DEVNAME;
	348	index_reg = SP5100_IO_PM_INDEX_REG;
	349	data_reg = SP5100_IO_PM_DATA_REG;
	350	base_addr = SP5100_PM_WATCHDOG_BASE;
bdecfcdb HR	351	} else {
	352	dev_name = SB800_DEVNAME;
	353	index_reg = SB800_IO_PM_INDEX_REG;
	354	data_reg = SB800_IO_PM_DATA_REG;
	355	base_addr = SB800_PM_WATCHDOG_BASE;
740fbddf TT	356	}
740fbddf TT	357
15e28bf1 PG	358	/* Request the IO ports used by this driver */
15e28bf1 PG	359	pm_iobase = SP5100_IO_PM_INDEX_REG;
740fbddf	360	if (!request_region(pm_iobase, SP5100_PM_IOPORTS_SIZE, dev_name)) {
27c766aa	361	pr_err("I/O address 0x%04x already in use\n", pm_iobase);
15e28bf1 PG	362	goto exit;
	363	}
	364
740fbddf TT	365	/*
	366	* First, Find the watchdog timer MMIO address from indirect I/O.
	367	*/
	368	outb(base_addr+3, index_reg);
	369	val = inb(data_reg);
	370	outb(base_addr+2, index_reg);
	371	val = val << 8 \| inb(data_reg);
	372	outb(base_addr+1, index_reg);
	373	val = val << 8 \| inb(data_reg);
	374	outb(base_addr+0, index_reg);
	375	/* Low three bits of BASE are reserved */
	376	val = val << 8 \| (inb(data_reg) & 0xf8);
	377
	378	pr_debug("Got 0x%04x from indirect I/O\n", val);
	379
	380	/* Check MMIO address conflict */
	381	if (request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE,
	382	dev_name))
	383	goto setup_wdt;
	384	else
	385	pr_debug("MMIO address 0x%04x already in use\n", val);
	386
	387	/*
	388	* Secondly, Find the watchdog timer MMIO address
	389	* from SBResource_MMIO register.
	390	*/
bdecfcdb HR	391	if (sp5100_tco_pci->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
	392	sp5100_tco_pci->revision < 0x40) {
	393	/* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
	394	pci_read_config_dword(sp5100_tco_pci,
	395	SP5100_SB_RESOURCE_MMIO_BASE, &val);
	396	} else {
740fbddf TT	397	/* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
	398	outb(SB800_PM_ACPI_MMIO_EN+3, SB800_IO_PM_INDEX_REG);
	399	val = inb(SB800_IO_PM_DATA_REG);
	400	outb(SB800_PM_ACPI_MMIO_EN+2, SB800_IO_PM_INDEX_REG);
	401	val = val << 8 \| inb(SB800_IO_PM_DATA_REG);
	402	outb(SB800_PM_ACPI_MMIO_EN+1, SB800_IO_PM_INDEX_REG);
	403	val = val << 8 \| inb(SB800_IO_PM_DATA_REG);
	404	outb(SB800_PM_ACPI_MMIO_EN+0, SB800_IO_PM_INDEX_REG);
	405	val = val << 8 \| inb(SB800_IO_PM_DATA_REG);
740fbddf TT	406	}
	407
	408	/* The SBResource_MMIO is enabled and mapped memory space? */
	409	if ((val & (SB800_ACPI_MMIO_DECODE_EN \| SB800_ACPI_MMIO_SEL)) ==
	410	SB800_ACPI_MMIO_DECODE_EN) {
	411	/* Clear unnecessary the low twelve bits */
	412	val &= ~0xFFF;
	413	/* Add the Watchdog Timer offset to base address. */
	414	val += SB800_PM_WDT_MMIO_OFFSET;
	415	/* Check MMIO address conflict */
	416	if (request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE,
	417	dev_name)) {
	418	pr_debug("Got 0x%04x from SBResource_MMIO register\n",
	419	val);
	420	goto setup_wdt;
	421	} else
	422	pr_debug("MMIO address 0x%04x already in use\n", val);
	423	} else
	424	pr_debug("SBResource_MMIO is disabled(0x%04x)\n", val);
	425
18e43212 TT	426	pr_notice("failed to find MMIO address, giving up.\n");
18e43212 TT	427	goto unreg_region;
740fbddf TT	428
740fbddf TT	429	setup_wdt:
90d241ed YL	430	tcobase_phys = val;
90d241ed YL	431
15e28bf1	432	tcobase = ioremap(val, SP5100_WDT_MEM_MAP_SIZE);
62a9aebc	433	if (!tcobase) {
27c766aa	434	pr_err("failed to get tcobase address\n");
90d241ed	435	goto unreg_mem_region;
15e28bf1 PG	436	}
15e28bf1 PG	437
740fbddf	438	pr_info("Using 0x%04x for watchdog MMIO address\n", val);
15e28bf1	439
740fbddf TT	440	/* Setup the watchdog timer */
740fbddf TT	441	tco_timer_enable();
15e28bf1	442
740fbddf	443	/* Check that the watchdog action is set to reset the system */
15e28bf1	444	val = readl(SP5100_WDT_CONTROL(tcobase));
740fbddf TT	445	/*
	446	* Save WatchDogFired status, because WatchDogFired flag is
	447	* cleared here.
	448	*/
	449	tco_wdt_fired = val & SP5100_PM_WATCHDOG_FIRED;
15e28bf1 PG	450	val &= ~SP5100_PM_WATCHDOG_ACTION_RESET;
	451	writel(val, SP5100_WDT_CONTROL(tcobase));
	452
	453	/* Set a reasonable heartbeat before we stop the timer */
	454	tco_timer_set_heartbeat(heartbeat);
	455
	456	/*
	457	* Stop the TCO before we change anything so we don't race with
	458	* a zeroed timer.
	459	*/
	460	tco_timer_stop();
	461
	462	/* Done */
	463	return 1;
	464
90d241ed YL	465	unreg_mem_region:
90d241ed YL	466	release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE);
15e28bf1 PG	467	unreg_region:
	468	release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE);
	469	exit:
	470	return 0;
	471	}
	472
2d991a16	473	static int sp5100_tco_init(struct platform_device *dev)
15e28bf1 PG	474	{
15e28bf1 PG	475	int ret;
15e28bf1	476
740fbddf TT	477	/*
740fbddf TT	478	* Check whether or not the hardware watchdog is there. If found, then
15e28bf1 PG	479	* set it up.
	480	*/
	481	if (!sp5100_tco_setupdevice())
	482	return -ENODEV;
	483
	484	/* Check to see if last reboot was due to watchdog timeout */
740fbddf TT	485	pr_info("Last reboot was %striggered by watchdog.\n",
740fbddf TT	486	tco_wdt_fired ? "" : "not ");
15e28bf1 PG	487
	488	/*
	489	* Check that the heartbeat value is within it's range.
	490	* If not, reset to the default.
	491	*/
	492	if (tco_timer_set_heartbeat(heartbeat)) {
	493	heartbeat = WATCHDOG_HEARTBEAT;
	494	tco_timer_set_heartbeat(heartbeat);
	495	}
	496
	497	ret = misc_register(&sp5100_tco_miscdev);
	498	if (ret != 0) {
27c766aa	499	pr_err("cannot register miscdev on minor=%d (err=%d)\n",
15e28bf1 PG	500	WATCHDOG_MINOR, ret);
	501	goto exit;
	502	}
	503
	504	clear_bit(0, &timer_alive);
	505
740fbddf	506	/* Show module parameters */
18e43212 TT	507	pr_info("initialized (0x%p). heartbeat=%d sec (nowayout=%d)\n",
18e43212 TT	508	tcobase, heartbeat, nowayout);
15e28bf1 PG	509
	510	return 0;
	511
	512	exit:
	513	iounmap(tcobase);
90d241ed	514	release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE);
15e28bf1 PG	515	release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE);
	516	return ret;
	517	}
	518
4b12b896	519	static void sp5100_tco_cleanup(void)
15e28bf1 PG	520	{
	521	/* Stop the timer before we leave */
	522	if (!nowayout)
	523	tco_timer_stop();
	524
	525	/* Deregister */
	526	misc_deregister(&sp5100_tco_miscdev);
	527	iounmap(tcobase);
90d241ed	528	release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE);
15e28bf1 PG	529	release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE);
	530	}
	531
4b12b896	532	static int sp5100_tco_remove(struct platform_device *dev)
15e28bf1 PG	533	{
	534	if (tcobase)
	535	sp5100_tco_cleanup();
	536	return 0;
	537	}
	538
	539	static void sp5100_tco_shutdown(struct platform_device *dev)
	540	{
	541	tco_timer_stop();
	542	}
	543
	544	static struct platform_driver sp5100_tco_driver = {
	545	.probe = sp5100_tco_init,
82268714	546	.remove = sp5100_tco_remove,
15e28bf1 PG	547	.shutdown = sp5100_tco_shutdown,
15e28bf1 PG	548	.driver = {
15e28bf1 PG	549	.name = TCO_MODULE_NAME,
	550	},
	551	};
	552
	553	static int __init sp5100_tco_init_module(void)
	554	{
	555	int err;
	556
740fbddf	557	pr_info("SP5100/SB800 TCO WatchDog Timer Driver v%s\n", TCO_VERSION);
15e28bf1 PG	558
	559	err = platform_driver_register(&sp5100_tco_driver);
	560	if (err)
	561	return err;
	562
	563	sp5100_tco_platform_device = platform_device_register_simple(
	564	TCO_MODULE_NAME, -1, NULL, 0);
	565	if (IS_ERR(sp5100_tco_platform_device)) {
	566	err = PTR_ERR(sp5100_tco_platform_device);
	567	goto unreg_platform_driver;
	568	}
	569
	570	return 0;
	571
	572	unreg_platform_driver:
	573	platform_driver_unregister(&sp5100_tco_driver);
	574	return err;
	575	}
	576
	577	static void __exit sp5100_tco_cleanup_module(void)
	578	{
	579	platform_device_unregister(sp5100_tco_platform_device);
	580	platform_driver_unregister(&sp5100_tco_driver);
740fbddf	581	pr_info("SP5100/SB800 TCO Watchdog Module Unloaded\n");
15e28bf1 PG	582	}
	583
	584	module_init(sp5100_tco_init_module);
	585	module_exit(sp5100_tco_cleanup_module);
	586
	587	MODULE_AUTHOR("Priyanka Gupta");
740fbddf	588	MODULE_DESCRIPTION("TCO timer driver for SP5100/SB800 chipset");
15e28bf1	589	MODULE_LICENSE("GPL");