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[deliverable/binutils-gdb.git] / gas / config / tc-arc.c
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252b5132 1/* tc-arc.c -- Assembler for the ARC
2571583a 2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19203624 19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
252b5132 23#include "as.h"
886a2506 24#include "subsegs.h"
a161fe53 25#include "struc-symbol.h"
886a2506 26#include "dwarf2dbg.h"
726c18e1 27#include "dw2gencfi.h"
3882b010 28#include "safe-ctype.h"
886a2506 29
252b5132 30#include "opcode/arc.h"
53a346d8 31#include "opcode/arc-attrs.h"
252b5132 32#include "elf/arc.h"
b99747ae 33#include "../opcodes/arc-ext.h"
252b5132 34
886a2506 35/* Defines section. */
0d2bcfaf 36
886a2506
NC		 37#define MAX_INSN_FIXUPS 2
38#define MAX_CONSTR_STR 20
4670103e 39#define FRAG_MAX_GROWTH 8
0d2bcfaf 40
886a2506
NC		 41#ifdef DEBUG
42# define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
43#else
44# define pr_debug(fmt, args...)
45#endif
46
47#define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
48#define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
db18dbab
GM		 49#define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
50 && (SUB_OPCODE (x) == 0x28))
886a2506
NC		 51
52/* Equal to MAX_PRECISION in atof-ieee.c. */
53#define MAX_LITTLENUMS 6
54
9004b6bd
AB		 55#ifndef TARGET_WITH_CPU
56#define TARGET_WITH_CPU "arc700"
57#endif /* TARGET_WITH_CPU */
58
53a346d8
CZ		 59#define ARC_GET_FLAG(s) (*symbol_get_tc (s))
60#define ARC_SET_FLAG(s,v) (*symbol_get_tc (s) |= (v))
61#define streq(a, b) (strcmp (a, b) == 0)
62
4670103e
CZ		 63/* Enum used to enumerate the relaxable ins operands. */
64enum rlx_operand_type
65{
66 EMPTY = 0,
67 REGISTER,
68 REGISTER_S, /* Register for short instruction(s). */
69 REGISTER_NO_GP, /* Is a register but not gp register specifically. */
70 REGISTER_DUP, /* Duplication of previous operand of type register. */
71 IMMEDIATE,
72 BRACKET
73};
74
75enum arc_rlx_types
76{
77 ARC_RLX_NONE = 0,
78 ARC_RLX_BL_S,
79 ARC_RLX_BL,
80 ARC_RLX_B_S,
81 ARC_RLX_B,
82 ARC_RLX_ADD_U3,
83 ARC_RLX_ADD_U6,
84 ARC_RLX_ADD_LIMM,
85 ARC_RLX_LD_U7,
86 ARC_RLX_LD_S9,
87 ARC_RLX_LD_LIMM,
88 ARC_RLX_MOV_U8,
89 ARC_RLX_MOV_S12,
90 ARC_RLX_MOV_LIMM,
91 ARC_RLX_SUB_U3,
92 ARC_RLX_SUB_U6,
93 ARC_RLX_SUB_LIMM,
94 ARC_RLX_MPY_U6,
95 ARC_RLX_MPY_LIMM,
96 ARC_RLX_MOV_RU6,
97 ARC_RLX_MOV_RLIMM,
98 ARC_RLX_ADD_RRU6,
99 ARC_RLX_ADD_RRLIMM,
100};
101
886a2506
NC		 102/* Macros section. */
103
104#define regno(x) ((x) & 0x3F)
105#define is_ir_num(x) (((x) & ~0x3F) == 0)
8ddf6b2a
CZ		 106#define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
107#define is_spfp_p(op) (((sc) == SPX))
108#define is_dpfp_p(op) (((sc) == DPX))
109#define is_fpuda_p(op) (((sc) == DPA))
db18dbab
GM		 110#define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
111 || (op)->insn_class == JUMP))
c810e0b8 112#define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
bdd582db 113#define is_nps400_p(op) (((sc) == NPS400))
0d2bcfaf 114
886a2506
NC		 115/* Generic assembler global variables which must be defined by all
116 targets. */
0d2bcfaf 117
886a2506 118/* Characters which always start a comment. */
252b5132
RH		 119const char comment_chars[] = "#;";
120
886a2506 121/* Characters which start a comment at the beginning of a line. */
252b5132
RH		 122const char line_comment_chars[] = "#";
123
886a2506
NC		 124/* Characters which may be used to separate multiple commands on a
125 single line. */
126const char line_separator_chars[] = "`";
252b5132 127
886a2506
NC		 128/* Characters which are used to indicate an exponent in a floating
129 point number. */
252b5132
RH		 130const char EXP_CHARS[] = "eE";
131
bcee8eb8
AM		 132/* Chars that mean this number is a floating point constant
133 As in 0f12.456 or 0d1.2345e12. */
252b5132
RH		 134const char FLT_CHARS[] = "rRsSfFdD";
135
136/* Byte order. */
137extern int target_big_endian;
138const char *arc_target_format = DEFAULT_TARGET_FORMAT;
139static int byte_order = DEFAULT_BYTE_ORDER;
140
b99747ae
CZ		 141/* Arc extension section. */
142static segT arcext_section;
143
4670103e
CZ		 144/* By default relaxation is disabled. */
145static int relaxation_state = 0;
146
886a2506 147extern int arc_get_mach (char *);
0d2bcfaf 148
4670103e 149/* Forward declarations. */
886a2506
NC		 150static void arc_lcomm (int);
151static void arc_option (int);
152static void arc_extra_reloc (int);
b99747ae 153static void arc_extinsn (int);
f36e33da 154static void arc_extcorereg (int);
53a346d8 155static void arc_attribute (int);
4670103e 156
886a2506 157const pseudo_typeS md_pseudo_table[] =
6f4b1afc
CM		 158{
159 /* Make sure that .word is 32 bits. */
160 { "word", cons, 4 },
886a2506 161
6f4b1afc
CM		 162 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
163 { "lcomm", arc_lcomm, 0 },
164 { "lcommon", arc_lcomm, 0 },
165 { "cpu", arc_option, 0 },
252b5132 166
53a346d8 167 { "arc_attribute", arc_attribute, 0 },
f36e33da
CZ		 168 { "extinstruction", arc_extinsn, 0 },
169 { "extcoreregister", arc_extcorereg, EXT_CORE_REGISTER },
170 { "extauxregister", arc_extcorereg, EXT_AUX_REGISTER },
171 { "extcondcode", arc_extcorereg, EXT_COND_CODE },
b99747ae 172
6f4b1afc
CM		 173 { "tls_gd_ld", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_LD },
174 { "tls_gd_call", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_CALL },
886a2506 175
6f4b1afc
CM		 176 { NULL, NULL, 0 }
177};
252b5132 178
252b5132 179const char *md_shortopts = "";
ea1562b3
NC		 180
181enum options
6f4b1afc
CM		 182{
183 OPTION_EB = OPTION_MD_BASE,
184 OPTION_EL,
185
186 OPTION_ARC600,
187 OPTION_ARC601,
188 OPTION_ARC700,
189 OPTION_ARCEM,
190 OPTION_ARCHS,
191
192 OPTION_MCPU,
193 OPTION_CD,
4670103e 194 OPTION_RELAX,
bdd582db 195 OPTION_NPS400,
6f4b1afc 196
ce440d63
GM		 197 OPTION_SPFP,
198 OPTION_DPFP,
199 OPTION_FPUDA,
200
6f4b1afc
CM		 201 /* The following options are deprecated and provided here only for
202 compatibility reasons. */
203 OPTION_USER_MODE,
204 OPTION_LD_EXT_MASK,
205 OPTION_SWAP,
206 OPTION_NORM,
207 OPTION_BARREL_SHIFT,
208 OPTION_MIN_MAX,
209 OPTION_NO_MPY,
210 OPTION_EA,
211 OPTION_MUL64,
212 OPTION_SIMD,
6f4b1afc
CM		 213 OPTION_XMAC_D16,
214 OPTION_XMAC_24,
215 OPTION_DSP_PACKA,
216 OPTION_CRC,
217 OPTION_DVBF,
218 OPTION_TELEPHONY,
219 OPTION_XYMEMORY,
220 OPTION_LOCK,
221 OPTION_SWAPE,
ce440d63 222 OPTION_RTSC
6f4b1afc 223};
ea1562b3
NC		 224
225struct option md_longopts[] =
6f4b1afc
CM		 226{
227 { "EB", no_argument, NULL, OPTION_EB },
228 { "EL", no_argument, NULL, OPTION_EL },
229 { "mcpu", required_argument, NULL, OPTION_MCPU },
230 { "mA6", no_argument, NULL, OPTION_ARC600 },
24b368f8
CZ		 231 { "mARC600", no_argument, NULL, OPTION_ARC600 },
232 { "mARC601", no_argument, NULL, OPTION_ARC601 },
233 { "mARC700", no_argument, NULL, OPTION_ARC700 },
6f4b1afc
CM		 234 { "mA7", no_argument, NULL, OPTION_ARC700 },
235 { "mEM", no_argument, NULL, OPTION_ARCEM },
236 { "mHS", no_argument, NULL, OPTION_ARCHS },
237 { "mcode-density", no_argument, NULL, OPTION_CD },
4670103e 238 { "mrelax", no_argument, NULL, OPTION_RELAX },
bdd582db 239 { "mnps400", no_argument, NULL, OPTION_NPS400 },
6f4b1afc 240
ce440d63
GM		 241 /* Floating point options */
242 { "mspfp", no_argument, NULL, OPTION_SPFP},
243 { "mspfp-compact", no_argument, NULL, OPTION_SPFP},
244 { "mspfp_compact", no_argument, NULL, OPTION_SPFP},
245 { "mspfp-fast", no_argument, NULL, OPTION_SPFP},
246 { "mspfp_fast", no_argument, NULL, OPTION_SPFP},
247 { "mdpfp", no_argument, NULL, OPTION_DPFP},
248 { "mdpfp-compact", no_argument, NULL, OPTION_DPFP},
249 { "mdpfp_compact", no_argument, NULL, OPTION_DPFP},
250 { "mdpfp-fast", no_argument, NULL, OPTION_DPFP},
251 { "mdpfp_fast", no_argument, NULL, OPTION_DPFP},
252 { "mfpuda", no_argument, NULL, OPTION_FPUDA},
253
6f4b1afc
CM		 254 /* The following options are deprecated and provided here only for
255 compatibility reasons. */
256 { "mav2em", no_argument, NULL, OPTION_ARCEM },
257 { "mav2hs", no_argument, NULL, OPTION_ARCHS },
258 { "muser-mode-only", no_argument, NULL, OPTION_USER_MODE },
259 { "mld-extension-reg-mask", required_argument, NULL, OPTION_LD_EXT_MASK },
260 { "mswap", no_argument, NULL, OPTION_SWAP },
261 { "mnorm", no_argument, NULL, OPTION_NORM },
262 { "mbarrel-shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
263 { "mbarrel_shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
264 { "mmin-max", no_argument, NULL, OPTION_MIN_MAX },
265 { "mmin_max", no_argument, NULL, OPTION_MIN_MAX },
266 { "mno-mpy", no_argument, NULL, OPTION_NO_MPY },
267 { "mea", no_argument, NULL, OPTION_EA },
268 { "mEA", no_argument, NULL, OPTION_EA },
269 { "mmul64", no_argument, NULL, OPTION_MUL64 },
270 { "msimd", no_argument, NULL, OPTION_SIMD},
6f4b1afc
CM		 271 { "mmac-d16", no_argument, NULL, OPTION_XMAC_D16},
272 { "mmac_d16", no_argument, NULL, OPTION_XMAC_D16},
273 { "mmac-24", no_argument, NULL, OPTION_XMAC_24},
274 { "mmac_24", no_argument, NULL, OPTION_XMAC_24},
275 { "mdsp-packa", no_argument, NULL, OPTION_DSP_PACKA},
276 { "mdsp_packa", no_argument, NULL, OPTION_DSP_PACKA},
277 { "mcrc", no_argument, NULL, OPTION_CRC},
278 { "mdvbf", no_argument, NULL, OPTION_DVBF},
279 { "mtelephony", no_argument, NULL, OPTION_TELEPHONY},
280 { "mxy", no_argument, NULL, OPTION_XYMEMORY},
281 { "mlock", no_argument, NULL, OPTION_LOCK},
282 { "mswape", no_argument, NULL, OPTION_SWAPE},
283 { "mrtsc", no_argument, NULL, OPTION_RTSC},
6f4b1afc
CM		 284
285 { NULL, no_argument, NULL, 0 }
286};
252b5132 287
886a2506 288size_t md_longopts_size = sizeof (md_longopts);
0d2bcfaf 289
886a2506 290/* Local data and data types. */
252b5132 291
886a2506
NC		 292/* Used since new relocation types are introduced in this
293 file (DUMMY_RELOC_LITUSE_*). */
294typedef int extended_bfd_reloc_code_real_type;
252b5132 295
886a2506 296struct arc_fixup
252b5132 297{
886a2506 298 expressionS exp;
252b5132 299
886a2506 300 extended_bfd_reloc_code_real_type reloc;
252b5132 301
886a2506
NC		 302 /* index into arc_operands. */
303 unsigned int opindex;
252b5132 304
886a2506
NC		 305 /* PC-relative, used by internals fixups. */
306 unsigned char pcrel;
252b5132 307
886a2506
NC		 308 /* TRUE if this fixup is for LIMM operand. */
309 bfd_boolean islong;
310};
252b5132 311
886a2506
NC		 312struct arc_insn
313{
bdfe53e3 314 unsigned long long int insn;
886a2506
NC		 315 int nfixups;
316 struct arc_fixup fixups[MAX_INSN_FIXUPS];
317 long limm;
91fdca6f 318 unsigned int len; /* Length of instruction in bytes. */
886a2506
NC		 319 bfd_boolean has_limm; /* Boolean value: TRUE if limm field is
320 valid. */
4670103e
CZ		 321 bfd_boolean relax; /* Boolean value: TRUE if needs
322 relaxation. */
886a2506 323};
ea1562b3 324
886a2506
NC		 325/* Structure to hold any last two instructions. */
326static struct arc_last_insn
252b5132 327{
886a2506
NC		 328 /* Saved instruction opcode. */
329 const struct arc_opcode *opcode;
252b5132 330
886a2506
NC		 331 /* Boolean value: TRUE if current insn is short. */
332 bfd_boolean has_limm;
252b5132 333
886a2506
NC		 334 /* Boolean value: TRUE if current insn has delay slot. */
335 bfd_boolean has_delay_slot;
336} arc_last_insns[2];
252b5132 337
b99747ae
CZ		 338/* Extension instruction suffix classes. */
339typedef struct
340{
341 const char *name;
342 int len;
c810e0b8 343 int attr_class;
b99747ae
CZ		 344} attributes_t;
345
346static const attributes_t suffixclass[] =
347{
348 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG },
349 { "SUFFIX_COND", 11, ARC_SUFFIX_COND },
350 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE }
351};
352
353/* Extension instruction syntax classes. */
354static const attributes_t syntaxclass[] =
355{
356 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP },
945e0f82
CZ		 357 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP },
358 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP },
359 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP }
b99747ae
CZ		 360};
361
362/* Extension instruction syntax classes modifiers. */
363static const attributes_t syntaxclassmod[] =
364{
365 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED },
366 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM }
367};
368
f36e33da
CZ		 369/* Extension register type. */
370typedef struct
371{
372 char *name;
373 int number;
374 int imode;
375} extRegister_t;
376
377/* A structure to hold the additional conditional codes. */
378static struct
379{
380 struct arc_flag_operand *arc_ext_condcode;
381 int size;
382} ext_condcode = { NULL, 0 };
383
da5be039
AB		 384/* Structure to hold an entry in ARC_OPCODE_HASH. */
385struct arc_opcode_hash_entry
386{
387 /* The number of pointers in the OPCODE list. */
388 size_t count;
389
390 /* Points to a list of opcode pointers. */
391 const struct arc_opcode **opcode;
392};
393
1328504b
AB		 394/* Structure used for iterating through an arc_opcode_hash_entry. */
395struct arc_opcode_hash_entry_iterator
396{
397 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
398 size_t index;
399
400 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
401 returned by this iterator. */
402 const struct arc_opcode *opcode;
403};
404
4670103e
CZ		 405/* Forward declaration. */
406static void assemble_insn
407 (const struct arc_opcode *, const expressionS *, int,
408 const struct arc_flags *, int, struct arc_insn *);
409
bb65a718
AB		 410/* The selection of the machine type can come from different sources. This
411 enum is used to track how the selection was made in order to perform
412 error checks. */
413enum mach_selection_type
414 {
415 MACH_SELECTION_NONE,
416 MACH_SELECTION_FROM_DEFAULT,
417 MACH_SELECTION_FROM_CPU_DIRECTIVE,
418 MACH_SELECTION_FROM_COMMAND_LINE
419 };
420
421/* How the current machine type was selected. */
422static enum mach_selection_type mach_selection_mode = MACH_SELECTION_NONE;
0d2bcfaf 423
886a2506
NC		 424/* The hash table of instruction opcodes. */
425static struct hash_control *arc_opcode_hash;
0d2bcfaf 426
886a2506
NC		 427/* The hash table of register symbols. */
428static struct hash_control *arc_reg_hash;
252b5132 429
f36e33da
CZ		 430/* The hash table of aux register symbols. */
431static struct hash_control *arc_aux_hash;
432
db18dbab
GM		 433/* The hash table of address types. */
434static struct hash_control *arc_addrtype_hash;
435
a9752fdf
CZ		 436#define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
437 { #NAME, ARC_OPCODE_ARC600, bfd_mach_arc_arc600, \
438 E_ARC_MACH_ARC600, EXTRA}
439#define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
440 { #NAME, ARC_OPCODE_ARC700, bfd_mach_arc_arc700, \
441 E_ARC_MACH_ARC700, EXTRA}
442#define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
443 { #NAME, ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, \
444 EF_ARC_CPU_ARCV2EM, EXTRA}
445#define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
446 { #NAME, ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \
447 EF_ARC_CPU_ARCV2HS, EXTRA}
940171d0
AK		 448#define ARC_CPU_TYPE_NONE \
449 { 0, 0, 0, 0, 0 }
a9752fdf 450
886a2506
NC		 451/* A table of CPU names and opcode sets. */
452static const struct cpu_type
453{
454 const char *name;
455 unsigned flags;
456 int mach;
457 unsigned eflags;
458 unsigned features;
252b5132 459}
886a2506 460 cpu_types[] =
252b5132 461{
940171d0 462 #include "elf/arc-cpu.def"
886a2506 463};
252b5132 464
bb65a718 465/* Information about the cpu/variant we're assembling for. */
53a346d8 466static struct cpu_type selected_cpu = { 0, 0, 0, E_ARC_OSABI_CURRENT, 0 };
bb050a69 467
53a346d8
CZ		 468/* MPY option. */
469static unsigned mpy_option = 0;
470
471/* Use PIC. */
472static unsigned pic_option = 0;
473
474/* Use small data. */
475static unsigned sda_option = 0;
476
477/* Use TLS. */
478static unsigned tls_option = 0;
bb65a718 479
a9752fdf
CZ		 480/* Command line given features. */
481static unsigned cl_features = 0;
482
886a2506
NC		 483/* Used by the arc_reloc_op table. Order is important. */
484#define O_gotoff O_md1 /* @gotoff relocation. */
485#define O_gotpc O_md2 /* @gotpc relocation. */
486#define O_plt O_md3 /* @plt relocation. */
487#define O_sda O_md4 /* @sda relocation. */
488#define O_pcl O_md5 /* @pcl relocation. */
489#define O_tlsgd O_md6 /* @tlsgd relocation. */
490#define O_tlsie O_md7 /* @tlsie relocation. */
491#define O_tpoff9 O_md8 /* @tpoff9 relocation. */
492#define O_tpoff O_md9 /* @tpoff relocation. */
493#define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
494#define O_dtpoff O_md11 /* @dtpoff relocation. */
495#define O_last O_dtpoff
496
497/* Used to define a bracket as operand in tokens. */
498#define O_bracket O_md32
499
db18dbab
GM		 500/* Used to define a colon as an operand in tokens. */
501#define O_colon O_md31
502
503/* Used to define address types in nps400. */
504#define O_addrtype O_md30
505
886a2506
NC		 506/* Dummy relocation, to be sorted out. */
507#define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
508
509#define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
510
511/* A table to map the spelling of a relocation operand into an appropriate
512 bfd_reloc_code_real_type type. The table is assumed to be ordered such
513 that op-O_literal indexes into it. */
514#define ARC_RELOC_TABLE(op) \
515 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
516 ? (abort (), 0) \
517 : (int) (op) - (int) O_gotoff) ])
518
519#define DEF(NAME, RELOC, REQ) \
520 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
521
522static const struct arc_reloc_op_tag
523{
524 /* String to lookup. */
525 const char *name;
526 /* Size of the string. */
527 size_t length;
528 /* Which operator to use. */
529 operatorT op;
530 extended_bfd_reloc_code_real_type reloc;
531 /* Allows complex relocation expression like identifier@reloc +
532 const. */
533 unsigned int complex_expr : 1;
534}
535 arc_reloc_op[] =
6f4b1afc
CM		 536{
537 DEF (gotoff, BFD_RELOC_ARC_GOTOFF, 1),
538 DEF (gotpc, BFD_RELOC_ARC_GOTPC32, 0),
539 DEF (plt, BFD_RELOC_ARC_PLT32, 0),
540 DEF (sda, DUMMY_RELOC_ARC_ENTRY, 1),
541 DEF (pcl, BFD_RELOC_ARC_PC32, 1),
542 DEF (tlsgd, BFD_RELOC_ARC_TLS_GD_GOT, 0),
543 DEF (tlsie, BFD_RELOC_ARC_TLS_IE_GOT, 0),
544 DEF (tpoff9, BFD_RELOC_ARC_TLS_LE_S9, 0),
b125bd17 545 DEF (tpoff, BFD_RELOC_ARC_TLS_LE_32, 1),
6f4b1afc 546 DEF (dtpoff9, BFD_RELOC_ARC_TLS_DTPOFF_S9, 0),
05bbf016 547 DEF (dtpoff, BFD_RELOC_ARC_TLS_DTPOFF, 1),
6f4b1afc 548};
252b5132 549
886a2506
NC		 550static const int arc_num_reloc_op
551= sizeof (arc_reloc_op) / sizeof (*arc_reloc_op);
552
4670103e
CZ		 553/* Structure for relaxable instruction that have to be swapped with a
554 smaller alternative instruction. */
555struct arc_relaxable_ins
556{
557 /* Mnemonic that should be checked. */
558 const char *mnemonic_r;
559
560 /* Operands that should be checked.
561 Indexes of operands from operand array. */
562 enum rlx_operand_type operands[6];
563
564 /* Flags that should be checked. */
565 unsigned flag_classes[5];
566
567 /* Mnemonic (smaller) alternative to be used later for relaxation. */
568 const char *mnemonic_alt;
569
570 /* Index of operand that generic relaxation has to check. */
571 unsigned opcheckidx;
572
573 /* Base subtype index used. */
574 enum arc_rlx_types subtype;
575};
576
577#define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
578 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
579 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
580 (SIZE), \
581 (NEXT) } \
582
583#define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
584 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
585 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
586 (SIZE), \
587 (NEXT) } \
588
589
590/* ARC relaxation table. */
591const relax_typeS md_relax_table[] =
592{
593 /* Fake entry. */
594 {0, 0, 0, 0},
595
596 /* BL_S s13 ->
597 BL s25. */
db18dbab
GM		 598 RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL),
599 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
4670103e
CZ		 600
601 /* B_S s10 ->
602 B s25. */
db18dbab
GM		 603 RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B),
604 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
4670103e
CZ		 605
606 /* ADD_S c,b, u3 ->
607 ADD<.f> a,b,u6 ->
608 ADD<.f> a,b,limm. */
db18dbab
GM		 609 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6),
610 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM),
611 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 612
613 /* LD_S a, [b, u7] ->
614 LD<zz><.x><.aa><.di> a, [b, s9] ->
615 LD<zz><.x><.aa><.di> a, [b, limm] */
db18dbab
GM		 616 RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9),
617 RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM),
618 RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE),
4670103e
CZ		 619
620 /* MOV_S b, u8 ->
621 MOV<.f> b, s12 ->
622 MOV<.f> b, limm. */
db18dbab
GM		 623 RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12),
624 RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM),
625 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 626
627 /* SUB_S c, b, u3 ->
628 SUB<.f> a, b, u6 ->
629 SUB<.f> a, b, limm. */
db18dbab
GM		 630 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6),
631 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM),
632 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 633
634 /* MPY<.f> a, b, u6 ->
635 MPY<.f> a, b, limm. */
db18dbab
GM		 636 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM),
637 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 638
639 /* MOV<.f><.cc> b, u6 ->
640 MOV<.f><.cc> b, limm. */
db18dbab
GM		 641 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM),
642 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 643
644 /* ADD<.f><.cc> b, b, u6 ->
645 ADD<.f><.cc> b, b, limm. */
db18dbab
GM		 646 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM),
647 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 648};
649
650/* Order of this table's entries matters! */
651const struct arc_relaxable_ins arc_relaxable_insns[] =
652{
653 { "bl", { IMMEDIATE }, { 0 }, "bl_s", 0, ARC_RLX_BL_S },
654 { "b", { IMMEDIATE }, { 0 }, "b_s", 0, ARC_RLX_B_S },
655 { "add", { REGISTER, REGISTER_DUP, IMMEDIATE }, { 5, 1, 0 }, "add",
656 2, ARC_RLX_ADD_RRU6},
657 { "add", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "add_s", 2,
658 ARC_RLX_ADD_U3 },
659 { "add", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "add", 2,
660 ARC_RLX_ADD_U6 },
661 { "ld", { REGISTER_S, BRACKET, REGISTER_S, IMMEDIATE, BRACKET },
662 { 0 }, "ld_s", 3, ARC_RLX_LD_U7 },
663 { "ld", { REGISTER, BRACKET, REGISTER_NO_GP, IMMEDIATE, BRACKET },
664 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9 },
665 { "mov", { REGISTER_S, IMMEDIATE }, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8 },
666 { "mov", { REGISTER, IMMEDIATE }, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12 },
667 { "mov", { REGISTER, IMMEDIATE }, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6 },
668 { "sub", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "sub_s", 2,
669 ARC_RLX_SUB_U3 },
670 { "sub", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "sub", 2,
671 ARC_RLX_SUB_U6 },
672 { "mpy", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "mpy", 2,
673 ARC_RLX_MPY_U6 },
674};
675
676const unsigned arc_num_relaxable_ins = ARRAY_SIZE (arc_relaxable_insns);
677
886a2506
NC		 678/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
679symbolS * GOT_symbol = 0;
680
681/* Set to TRUE when we assemble instructions. */
682static bfd_boolean assembling_insn = FALSE;
683
53a346d8
CZ		 684/* List with attributes set explicitly. */
685static bfd_boolean attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
686
886a2506
NC		 687/* Functions implementation. */
688
b9b47ab7
AB		 689/* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
690 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
691 are no matching entries in ARC_OPCODE_HASH. */
da5be039 692
b9b47ab7 693static const struct arc_opcode_hash_entry *
da5be039
AB		 694arc_find_opcode (const char *name)
695{
696 const struct arc_opcode_hash_entry *entry;
da5be039
AB		 697
698 entry = hash_find (arc_opcode_hash, name);
b9b47ab7 699 return entry;
da5be039
AB		 700}
701
1328504b
AB		 702/* Initialise the iterator ITER. */
703
704static void
705arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator *iter)
706{
707 iter->index = 0;
708 iter->opcode = NULL;
709}
710
711/* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
712 calls to this function. Return NULL when all ARC_OPCODE entries have
713 been returned. */
714
715static const struct arc_opcode *
716arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry *entry,
717 struct arc_opcode_hash_entry_iterator *iter)
718{
719 if (iter->opcode == NULL && iter->index == 0)
720 {
721 gas_assert (entry->count > 0);
722 iter->opcode = entry->opcode[iter->index];
723 }
724 else if (iter->opcode != NULL)
725 {
726 const char *old_name = iter->opcode->name;
727
728 iter->opcode++;
fe779266
AB		 729 if (iter->opcode->name == NULL
730 || strcmp (old_name, iter->opcode->name) != 0)
1328504b
AB		 731 {
732 iter->index++;
733 if (iter->index == entry->count)
734 iter->opcode = NULL;
735 else
736 iter->opcode = entry->opcode[iter->index];
737 }
738 }
739
740 return iter->opcode;
741}
742
b99747ae
CZ		 743/* Insert an opcode into opcode hash structure. */
744
745static void
746arc_insert_opcode (const struct arc_opcode *opcode)
747{
748 const char *name, *retval;
749 struct arc_opcode_hash_entry *entry;
750 name = opcode->name;
751
752 entry = hash_find (arc_opcode_hash, name);
753 if (entry == NULL)
754 {
add39d23 755 entry = XNEW (struct arc_opcode_hash_entry);
b99747ae
CZ		 756 entry->count = 0;
757 entry->opcode = NULL;
758
759 retval = hash_insert (arc_opcode_hash, name, (void *) entry);
760 if (retval)
761 as_fatal (_("internal error: can't hash opcode '%s': %s"),
762 name, retval);
763 }
764
add39d23
TS		 765 entry->opcode = XRESIZEVEC (const struct arc_opcode *, entry->opcode,
766 entry->count + 1);
b99747ae
CZ		 767
768 if (entry->opcode == NULL)
769 as_fatal (_("Virtual memory exhausted"));
770
771 entry->opcode[entry->count] = opcode;
772 entry->count++;
773}
774
775
bdfe53e3
AB		 776/* Like md_number_to_chars but for middle-endian values. The 4-byte limm
777 value, is encoded as 'middle-endian' for a little-endian target. This
778 function is used for regular 4, 6, and 8 byte instructions as well. */
886a2506
NC		 779
780static void
bdfe53e3 781md_number_to_chars_midend (char *buf, unsigned long long val, int n)
886a2506 782{
bdfe53e3 783 switch (n)
886a2506 784 {
bdfe53e3
AB		 785 case 2:
786 md_number_to_chars (buf, val, n);
787 break;
788 case 6:
789 md_number_to_chars (buf, (val & 0xffff00000000) >> 32, 2);
790 md_number_to_chars_midend (buf + 2, (val & 0xffffffff), 4);
791 break;
792 case 4:
886a2506
NC		 793 md_number_to_chars (buf, (val & 0xffff0000) >> 16, 2);
794 md_number_to_chars (buf + 2, (val & 0xffff), 2);
bdfe53e3
AB		 795 break;
796 case 8:
797 md_number_to_chars_midend (buf, (val & 0xffffffff00000000) >> 32, 4);
798 md_number_to_chars_midend (buf + 4, (val & 0xffffffff), 4);
799 break;
800 default:
801 abort ();
886a2506 802 }
252b5132
RH		 803}
804
bb050a69
CZ		 805/* Check if a feature is allowed for a specific CPU. */
806
807static void
808arc_check_feature (void)
809{
810 unsigned i;
811
812 if (!selected_cpu.features
813 || !selected_cpu.name)
814 return;
53a346d8
CZ		 815
816 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
817 if ((selected_cpu.features & feature_list[i].feature)
818 && !(selected_cpu.flags & feature_list[i].cpus))
819 as_bad (_("invalid %s option for %s cpu"), feature_list[i].name,
820 selected_cpu.name);
821
822 for (i = 0; i < ARRAY_SIZE (conflict_list); i++)
823 if ((selected_cpu.features & conflict_list[i]) == conflict_list[i])
824 as_bad(_("conflicting ISA extension attributes."));
bb050a69
CZ		 825}
826
24740d83 827/* Select an appropriate entry from CPU_TYPES based on ARG and initialise
bb65a718
AB		 828 the relevant static global variables. Parameter SEL describes where
829 this selection originated from. */
24740d83
AB		 830
831static void
bb65a718 832arc_select_cpu (const char *arg, enum mach_selection_type sel)
24740d83 833{
24740d83
AB		 834 int i;
835
bb65a718
AB		 836 /* We should only set a default if we've not made a selection from some
837 other source. */
838 gas_assert (sel != MACH_SELECTION_FROM_DEFAULT
839 || mach_selection_mode == MACH_SELECTION_NONE);
840
bb050a69
CZ		 841 if ((mach_selection_mode == MACH_SELECTION_FROM_CPU_DIRECTIVE)
842 && (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE))
843 as_bad (_("Multiple .cpu directives found"));
844
bb65a718 845 /* Look for a matching entry in CPU_TYPES array. */
24740d83
AB		 846 for (i = 0; cpu_types[i].name; ++i)
847 {
848 if (!strcasecmp (cpu_types[i].name, arg))
849 {
bb65a718
AB		 850 /* If a previous selection was made on the command line, then we
851 allow later selections on the command line to override earlier
852 ones. However, a selection from a '.cpu NAME' directive must
853 match the command line selection, or we give a warning. */
854 if (mach_selection_mode == MACH_SELECTION_FROM_COMMAND_LINE)
855 {
856 gas_assert (sel == MACH_SELECTION_FROM_COMMAND_LINE
857 || sel == MACH_SELECTION_FROM_CPU_DIRECTIVE);
858 if (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE
859 && selected_cpu.mach != cpu_types[i].mach)
860 {
861 as_warn (_("Command-line value overrides \".cpu\" directive"));
bb65a718 862 }
bb050a69 863 return;
bb65a718
AB		 864 }
865
bb050a69
CZ		 866 /* Initialise static global data about selected machine type. */
867 selected_cpu.flags = cpu_types[i].flags;
868 selected_cpu.name = cpu_types[i].name;
a9752fdf 869 selected_cpu.features = cpu_types[i].features | cl_features;
bb050a69 870 selected_cpu.mach = cpu_types[i].mach;
53a346d8
CZ		 871 selected_cpu.eflags = ((selected_cpu.eflags & ~EF_ARC_MACH_MSK)
872 | cpu_types[i].eflags);
24740d83
AB		 873 break;
874 }
875 }
876
877 if (!cpu_types[i].name)
878 as_fatal (_("unknown architecture: %s\n"), arg);
bb050a69
CZ		 879
880 /* Check if set features are compatible with the chosen CPU. */
881 arc_check_feature ();
53a346d8 882
bb65a718 883 mach_selection_mode = sel;
24740d83
AB		 884}
885
886a2506
NC		 886/* Here ends all the ARCompact extension instruction assembling
887 stuff. */
252b5132 888
886a2506
NC		 889static void
890arc_extra_reloc (int r_type)
ea1562b3 891{
886a2506
NC		 892 char *sym_name, c;
893 symbolS *sym, *lab = NULL;
894
895 if (*input_line_pointer == '@')
896 input_line_pointer++;
897 c = get_symbol_name (&sym_name);
898 sym = symbol_find_or_make (sym_name);
899 restore_line_pointer (c);
900 if (c == ',' && r_type == BFD_RELOC_ARC_TLS_GD_LD)
901 {
902 ++input_line_pointer;
903 char *lab_name;
904 c = get_symbol_name (&lab_name);
905 lab = symbol_find_or_make (lab_name);
906 restore_line_pointer (c);
907 }
841fdfcd
CZ		 908
909 /* These relocations exist as a mechanism for the compiler to tell the
910 linker how to patch the code if the tls model is optimised. However,
911 the relocation itself does not require any space within the assembler
912 fragment, and so we pass a size of 0.
913
914 The lines that generate these relocations look like this:
915
916 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
917
918 The '.tls_gd_ld @.tdata' is processed first and generates the
919 additional relocation, while the 'bl __tls_get_addr@plt' is processed
920 second and generates the additional branch.
921
922 It is possible that the additional relocation generated by the
923 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
924 while the 'bl __tls_get_addr@plt' will be generated as the first thing
925 in the next fragment. This will be fine; both relocations will still
926 appear to be at the same address in the generated object file.
927 However, this only works as the additional relocation is generated
928 with size of 0 bytes. */
886a2506
NC		 929 fixS *fixP
930 = fix_new (frag_now, /* Which frag? */
931 frag_now_fix (), /* Where in that frag? */
841fdfcd 932 0, /* size: 1, 2, or 4 usually. */
886a2506
NC		 933 sym, /* X_add_symbol. */
934 0, /* X_add_number. */
935 FALSE, /* TRUE if PC-relative relocation. */
936 r_type /* Relocation type. */);
937 fixP->fx_subsy = lab;
938}
252b5132 939
886a2506
NC		 940static symbolS *
941arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED,
942 symbolS *symbolP, addressT size)
943{
944 addressT align = 0;
945 SKIP_WHITESPACE ();
252b5132 946
886a2506
NC		 947 if (*input_line_pointer == ',')
948 {
949 align = parse_align (1);
252b5132 950
886a2506
NC		 951 if (align == (addressT) -1)
952 return NULL;
953 }
954 else
955 {
956 if (size >= 8)
957 align = 3;
958 else if (size >= 4)
959 align = 2;
960 else if (size >= 2)
961 align = 1;
962 else
963 align = 0;
964 }
252b5132 965
886a2506
NC		 966 bss_alloc (symbolP, size, align);
967 S_CLEAR_EXTERNAL (symbolP);
ea1562b3 968
886a2506
NC		 969 return symbolP;
970}
ea1562b3 971
886a2506
NC		 972static void
973arc_lcomm (int ignore)
974{
975 symbolS *symbolP = s_comm_internal (ignore, arc_lcomm_internal);
ea1562b3 976
886a2506
NC		 977 if (symbolP)
978 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
979}
ea1562b3 980
886a2506 981/* Select the cpu we're assembling for. */
ea1562b3 982
886a2506
NC		 983static void
984arc_option (int ignore ATTRIBUTE_UNUSED)
252b5132 985{
886a2506
NC		 986 char c;
987 char *cpu;
bb65a718 988 const char *cpu_name;
252b5132 989
886a2506 990 c = get_symbol_name (&cpu);
252b5132 991
a9752fdf 992 cpu_name = cpu;
bb65a718
AB		 993 if ((!strcmp ("ARC600", cpu))
994 || (!strcmp ("ARC601", cpu))
995 || (!strcmp ("A6", cpu)))
996 cpu_name = "arc600";
997 else if ((!strcmp ("ARC700", cpu))
998 || (!strcmp ("A7", cpu)))
999 cpu_name = "arc700";
1000 else if (!strcmp ("EM", cpu))
1001 cpu_name = "arcem";
1002 else if (!strcmp ("HS", cpu))
1003 cpu_name = "archs";
1004 else if (!strcmp ("NPS400", cpu))
1005 cpu_name = "nps400";
886a2506 1006
a9752fdf 1007 arc_select_cpu (cpu_name, MACH_SELECTION_FROM_CPU_DIRECTIVE);
24b368f8 1008
24b368f8 1009 restore_line_pointer (c);
886a2506 1010 demand_empty_rest_of_line ();
ea1562b3 1011}
252b5132 1012
886a2506
NC		 1013/* Smartly print an expression. */
1014
ea1562b3 1015static void
886a2506 1016debug_exp (expressionS *t)
ea1562b3 1017{
886a2506
NC		 1018 const char *name ATTRIBUTE_UNUSED;
1019 const char *namemd ATTRIBUTE_UNUSED;
252b5132 1020
886a2506 1021 pr_debug ("debug_exp: ");
252b5132 1022
886a2506 1023 switch (t->X_op)
252b5132 1024 {
886a2506
NC		 1025 default: name = "unknown"; break;
1026 case O_illegal: name = "O_illegal"; break;
1027 case O_absent: name = "O_absent"; break;
1028 case O_constant: name = "O_constant"; break;
1029 case O_symbol: name = "O_symbol"; break;
1030 case O_symbol_rva: name = "O_symbol_rva"; break;
1031 case O_register: name = "O_register"; break;
1032 case O_big: name = "O_big"; break;
1033 case O_uminus: name = "O_uminus"; break;
1034 case O_bit_not: name = "O_bit_not"; break;
1035 case O_logical_not: name = "O_logical_not"; break;
1036 case O_multiply: name = "O_multiply"; break;
1037 case O_divide: name = "O_divide"; break;
1038 case O_modulus: name = "O_modulus"; break;
1039 case O_left_shift: name = "O_left_shift"; break;
1040 case O_right_shift: name = "O_right_shift"; break;
1041 case O_bit_inclusive_or: name = "O_bit_inclusive_or"; break;
1042 case O_bit_or_not: name = "O_bit_or_not"; break;
1043 case O_bit_exclusive_or: name = "O_bit_exclusive_or"; break;
1044 case O_bit_and: name = "O_bit_and"; break;
1045 case O_add: name = "O_add"; break;
1046 case O_subtract: name = "O_subtract"; break;
1047 case O_eq: name = "O_eq"; break;
1048 case O_ne: name = "O_ne"; break;
1049 case O_lt: name = "O_lt"; break;
1050 case O_le: name = "O_le"; break;
1051 case O_ge: name = "O_ge"; break;
1052 case O_gt: name = "O_gt"; break;
1053 case O_logical_and: name = "O_logical_and"; break;
1054 case O_logical_or: name = "O_logical_or"; break;
1055 case O_index: name = "O_index"; break;
1056 case O_bracket: name = "O_bracket"; break;
db18dbab
GM		 1057 case O_colon: name = "O_colon"; break;
1058 case O_addrtype: name = "O_addrtype"; break;
ea1562b3 1059 }
252b5132 1060
886a2506 1061 switch (t->X_md)
ea1562b3 1062 {
886a2506
NC		 1063 default: namemd = "unknown"; break;
1064 case O_gotoff: namemd = "O_gotoff"; break;
1065 case O_gotpc: namemd = "O_gotpc"; break;
1066 case O_plt: namemd = "O_plt"; break;
1067 case O_sda: namemd = "O_sda"; break;
1068 case O_pcl: namemd = "O_pcl"; break;
1069 case O_tlsgd: namemd = "O_tlsgd"; break;
1070 case O_tlsie: namemd = "O_tlsie"; break;
1071 case O_tpoff9: namemd = "O_tpoff9"; break;
1072 case O_tpoff: namemd = "O_tpoff"; break;
1073 case O_dtpoff9: namemd = "O_dtpoff9"; break;
1074 case O_dtpoff: namemd = "O_dtpoff"; break;
ea1562b3 1075 }
252b5132 1076
886a2506
NC		 1077 pr_debug ("%s (%s, %s, %d, %s)", name,
1078 (t->X_add_symbol) ? S_GET_NAME (t->X_add_symbol) : "--",
1079 (t->X_op_symbol) ? S_GET_NAME (t->X_op_symbol) : "--",
1080 (int) t->X_add_number,
1081 (t->X_md) ? namemd : "--");
1082 pr_debug ("\n");
1083 fflush (stderr);
1084}
252b5132 1085
886a2506
NC		 1086/* Parse the arguments to an opcode. */
1087
1088static int
1089tokenize_arguments (char *str,
1090 expressionS *tok,
1091 int ntok)
1092{
1093 char *old_input_line_pointer;
1094 bfd_boolean saw_comma = FALSE;
1095 bfd_boolean saw_arg = FALSE;
1096 int brk_lvl = 0;
1097 int num_args = 0;
886a2506
NC		 1098 int i;
1099 size_t len;
1100 const struct arc_reloc_op_tag *r;
1101 expressionS tmpE;
6f4b1afc 1102 char *reloc_name, c;
886a2506
NC		 1103
1104 memset (tok, 0, sizeof (*tok) * ntok);
1105
1106 /* Save and restore input_line_pointer around this function. */
1107 old_input_line_pointer = input_line_pointer;
1108 input_line_pointer = str;
ea1562b3 1109
886a2506 1110 while (*input_line_pointer)
ea1562b3
NC		 1111 {
1112 SKIP_WHITESPACE ();
886a2506 1113 switch (*input_line_pointer)
252b5132 1114 {
886a2506
NC		 1115 case '\0':
1116 goto fini;
1117
1118 case ',':
1119 input_line_pointer++;
1120 if (saw_comma || !saw_arg)
1121 goto err;
1122 saw_comma = TRUE;
1123 break;
252b5132 1124
886a2506
NC		 1125 case '}':
1126 case ']':
1127 ++input_line_pointer;
1128 --brk_lvl;
3b889a78 1129 if (!saw_arg || num_args == ntok)
886a2506
NC		 1130 goto err;
1131 tok->X_op = O_bracket;
1132 ++tok;
1133 ++num_args;
1134 break;
ea1562b3 1135
886a2506
NC		 1136 case '{':
1137 case '[':
1138 input_line_pointer++;
3b889a78 1139 if (brk_lvl || num_args == ntok)
886a2506
NC		 1140 goto err;
1141 ++brk_lvl;
1142 tok->X_op = O_bracket;
1143 ++tok;
1144 ++num_args;
1145 break;
1146
db18dbab
GM		 1147 case ':':
1148 input_line_pointer++;
1149 if (!saw_arg || num_args == ntok)
1150 goto err;
1151 tok->X_op = O_colon;
1152 saw_arg = FALSE;
1153 ++tok;
1154 ++num_args;
1155 break;
1156
886a2506
NC		 1157 case '@':
1158 /* We have labels, function names and relocations, all
1159 starting with @ symbol. Sort them out. */
3b889a78 1160 if ((saw_arg && !saw_comma) || num_args == ntok)
886a2506
NC		 1161 goto err;
1162
1163 /* Parse @label. */
1164 tok->X_op = O_symbol;
1165 tok->X_md = O_absent;
1166 expression (tok);
1167 if (*input_line_pointer != '@')
1168 goto normalsymbol; /* This is not a relocation. */
1169
6f4b1afc
CM		 1170 relocationsym:
1171
33eaf5de 1172 /* A relocation operand has the following form
886a2506
NC		 1173 @identifier@relocation_type. The identifier is already
1174 in tok! */
1175 if (tok->X_op != O_symbol)
ea1562b3 1176 {
886a2506
NC		 1177 as_bad (_("No valid label relocation operand"));
1178 goto err;
252b5132 1179 }
886a2506
NC		 1180
1181 /* Parse @relocation_type. */
6f4b1afc
CM		 1182 input_line_pointer++;
1183 c = get_symbol_name (&reloc_name);
1184 len = input_line_pointer - reloc_name;
1185 if (len == 0)
252b5132 1186 {
886a2506
NC		 1187 as_bad (_("No relocation operand"));
1188 goto err;
252b5132 1189 }
252b5132 1190
886a2506
NC		 1191 /* Go through known relocation and try to find a match. */
1192 r = &arc_reloc_op[0];
1193 for (i = arc_num_reloc_op - 1; i >= 0; i--, r++)
6f4b1afc
CM		 1194 if (len == r->length
1195 && memcmp (reloc_name, r->name, len) == 0)
886a2506 1196 break;
886a2506 1197 if (i < 0)
252b5132 1198 {
6f4b1afc 1199 as_bad (_("Unknown relocation operand: @%s"), reloc_name);
886a2506
NC		 1200 goto err;
1201 }
1202
6f4b1afc
CM		 1203 *input_line_pointer = c;
1204 SKIP_WHITESPACE_AFTER_NAME ();
886a2506
NC		 1205 /* Extra check for TLS: base. */
1206 if (*input_line_pointer == '@')
1207 {
1208 symbolS *base;
1209 if (tok->X_op_symbol != NULL
1210 || tok->X_op != O_symbol)
252b5132 1211 {
6f4b1afc
CM		 1212 as_bad (_("Unable to parse TLS base: %s"),
1213 input_line_pointer);
886a2506 1214 goto err;
252b5132 1215 }
886a2506
NC		 1216 input_line_pointer++;
1217 char *sym_name;
6f4b1afc 1218 c = get_symbol_name (&sym_name);
886a2506
NC		 1219 base = symbol_find_or_make (sym_name);
1220 tok->X_op = O_subtract;
1221 tok->X_op_symbol = base;
1222 restore_line_pointer (c);
6f4b1afc
CM		 1223 tmpE.X_add_number = 0;
1224 }
32348c58 1225 if ((*input_line_pointer != '+')
6f4b1afc
CM		 1226 && (*input_line_pointer != '-'))
1227 {
1228 tmpE.X_add_number = 0;
ea1562b3 1229 }
6f4b1afc
CM		 1230 else
1231 {
1232 /* Parse the constant of a complex relocation expression
1233 like @identifier@reloc +/- const. */
1234 if (! r->complex_expr)
1235 {
1236 as_bad (_("@%s is not a complex relocation."), r->name);
1237 goto err;
1238 }
1239 expression (&tmpE);
1240 if (tmpE.X_op != O_constant)
1241 {
1242 as_bad (_("Bad expression: @%s + %s."),
1243 r->name, input_line_pointer);
1244 goto err;
1245 }
1246 }
1247
1248 tok->X_md = r->op;
1249 tok->X_add_number = tmpE.X_add_number;
1e07b820 1250
886a2506 1251 debug_exp (tok);
ea1562b3 1252
886a2506
NC		 1253 saw_comma = FALSE;
1254 saw_arg = TRUE;
1255 tok++;
1256 num_args++;
1257 break;
252b5132 1258
886a2506
NC		 1259 case '%':
1260 /* Can be a register. */
1261 ++input_line_pointer;
1262 /* Fall through. */
1263 default:
252b5132 1264
3b889a78 1265 if ((saw_arg && !saw_comma) || num_args == ntok)
886a2506 1266 goto err;
252b5132 1267
886a2506 1268 tok->X_op = O_absent;
6f4b1afc 1269 tok->X_md = O_absent;
886a2506 1270 expression (tok);
252b5132 1271
6f4b1afc
CM		 1272 /* Legacy: There are cases when we have
1273 identifier@relocation_type, if it is the case parse the
1274 relocation type as well. */
1275 if (*input_line_pointer == '@')
1276 goto relocationsym;
1277
886a2506
NC		 1278 normalsymbol:
1279 debug_exp (tok);
252b5132 1280
3b889a78
AB		 1281 if (tok->X_op == O_illegal
1282 || tok->X_op == O_absent
1283 || num_args == ntok)
886a2506 1284 goto err;
252b5132 1285
886a2506
NC		 1286 saw_comma = FALSE;
1287 saw_arg = TRUE;
1288 tok++;
1289 num_args++;
1290 break;
1291 }
ea1562b3 1292 }
252b5132 1293
886a2506
NC		 1294 fini:
1295 if (saw_comma || brk_lvl)
1296 goto err;
1297 input_line_pointer = old_input_line_pointer;
252b5132 1298
886a2506 1299 return num_args;
252b5132 1300
886a2506
NC		 1301 err:
1302 if (brk_lvl)
1303 as_bad (_("Brackets in operand field incorrect"));
1304 else if (saw_comma)
1305 as_bad (_("extra comma"));
1306 else if (!saw_arg)
1307 as_bad (_("missing argument"));
1308 else
1309 as_bad (_("missing comma or colon"));
1310 input_line_pointer = old_input_line_pointer;
1311 return -1;
252b5132 1312}
ea1562b3 1313
886a2506
NC		 1314/* Parse the flags to a structure. */
1315
1316static int
1317tokenize_flags (const char *str,
1318 struct arc_flags flags[],
1319 int nflg)
252b5132 1320{
886a2506
NC		 1321 char *old_input_line_pointer;
1322 bfd_boolean saw_flg = FALSE;
1323 bfd_boolean saw_dot = FALSE;
1324 int num_flags = 0;
1325 size_t flgnamelen;
252b5132 1326
886a2506 1327 memset (flags, 0, sizeof (*flags) * nflg);
0d2bcfaf 1328
886a2506
NC		 1329 /* Save and restore input_line_pointer around this function. */
1330 old_input_line_pointer = input_line_pointer;
1331 input_line_pointer = (char *) str;
0d2bcfaf 1332
886a2506
NC		 1333 while (*input_line_pointer)
1334 {
1335 switch (*input_line_pointer)
1336 {
1337 case ' ':
1338 case '\0':
1339 goto fini;
1340
1341 case '.':
1342 input_line_pointer++;
1343 if (saw_dot)
1344 goto err;
1345 saw_dot = TRUE;
1346 saw_flg = FALSE;
1347 break;
ea1562b3 1348
886a2506
NC		 1349 default:
1350 if (saw_flg && !saw_dot)
1351 goto err;
0d2bcfaf 1352
886a2506
NC		 1353 if (num_flags >= nflg)
1354 goto err;
0d2bcfaf 1355
692166c2
AB		 1356 flgnamelen = strspn (input_line_pointer,
1357 "abcdefghijklmnopqrstuvwxyz0123456789");
83cda17b 1358 if (flgnamelen > MAX_FLAG_NAME_LENGTH)
886a2506 1359 goto err;
0d2bcfaf 1360
886a2506 1361 memcpy (flags->name, input_line_pointer, flgnamelen);
0d2bcfaf 1362
886a2506
NC		 1363 input_line_pointer += flgnamelen;
1364 flags++;
1365 saw_dot = FALSE;
1366 saw_flg = TRUE;
1367 num_flags++;
1368 break;
1e07b820 1369 }
0d2bcfaf
NC		 1370 }
1371
886a2506
NC		 1372 fini:
1373 input_line_pointer = old_input_line_pointer;
1374 return num_flags;
0d2bcfaf 1375
886a2506
NC		 1376 err:
1377 if (saw_dot)
1378 as_bad (_("extra dot"));
1379 else if (!saw_flg)
1380 as_bad (_("unrecognized flag"));
1381 else
1382 as_bad (_("failed to parse flags"));
1383 input_line_pointer = old_input_line_pointer;
1384 return -1;
1385}
0d2bcfaf 1386
4670103e 1387/* Apply the fixups in order. */
0d2bcfaf 1388
4670103e
CZ		 1389static void
1390apply_fixups (struct arc_insn *insn, fragS *fragP, int fix)
886a2506 1391{
4670103e 1392 int i;
0d2bcfaf 1393
4670103e 1394 for (i = 0; i < insn->nfixups; i++)
252b5132 1395 {
4670103e
CZ		 1396 struct arc_fixup *fixup = &insn->fixups[i];
1397 int size, pcrel, offset = 0;
0d2bcfaf 1398
4670103e
CZ		 1399 /* FIXME! the reloc size is wrong in the BFD file.
1400 When it is fixed please delete me. */
91fdca6f 1401 size = ((insn->len == 2) && !fixup->islong) ? 2 : 4;
0d2bcfaf 1402
4670103e 1403 if (fixup->islong)
91fdca6f 1404 offset = insn->len;
252b5132 1405
4670103e
CZ		 1406 /* Some fixups are only used internally, thus no howto. */
1407 if ((int) fixup->reloc == 0)
1408 as_fatal (_("Unhandled reloc type"));
886a2506 1409
4670103e
CZ		 1410 if ((int) fixup->reloc < 0)
1411 {
1412 /* FIXME! the reloc size is wrong in the BFD file.
1413 When it is fixed please enable me.
91fdca6f 1414 size = ((insn->len == 2 && !fixup->islong) ? 2 : 4; */
4670103e
CZ		 1415 pcrel = fixup->pcrel;
1416 }
1417 else
1418 {
1419 reloc_howto_type *reloc_howto =
1420 bfd_reloc_type_lookup (stdoutput,
1421 (bfd_reloc_code_real_type) fixup->reloc);
1422 gas_assert (reloc_howto);
0d2bcfaf 1423
4670103e
CZ		 1424 /* FIXME! the reloc size is wrong in the BFD file.
1425 When it is fixed please enable me.
1426 size = bfd_get_reloc_size (reloc_howto); */
1427 pcrel = reloc_howto->pc_relative;
1428 }
0d2bcfaf 1429
4670103e
CZ		 1430 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1431offset %d + %d\n",
1432 fragP->fr_file, fragP->fr_line,
1433 (fixup->reloc < 0) ? "Internal" :
1434 bfd_get_reloc_code_name (fixup->reloc),
1435 pcrel ? "Y" : "N",
1436 size, fix, offset);
1437 fix_new_exp (fragP, fix + offset,
1438 size, &fixup->exp, pcrel, fixup->reloc);
0d2bcfaf 1439
4670103e
CZ		 1440 /* Check for ZOLs, and update symbol info if any. */
1441 if (LP_INSN (insn->insn))
886a2506 1442 {
4670103e
CZ		 1443 gas_assert (fixup->exp.X_add_symbol);
1444 ARC_SET_FLAG (fixup->exp.X_add_symbol, ARC_FLAG_ZOL);
886a2506
NC		 1445 }
1446 }
252b5132
RH		 1447}
1448
4670103e 1449/* Actually output an instruction with its fixup. */
886a2506 1450
4670103e
CZ		 1451static void
1452emit_insn0 (struct arc_insn *insn, char *where, bfd_boolean relax)
252b5132 1453{
4670103e 1454 char *f = where;
91fdca6f 1455 size_t total_len;
252b5132 1456
bdfe53e3
AB		 1457 pr_debug ("Emit insn : 0x%llx\n", insn->insn);
1458 pr_debug ("\tLength : 0x%d\n", insn->len);
4670103e 1459 pr_debug ("\tLong imm: 0x%lx\n", insn->limm);
0d2bcfaf 1460
4670103e 1461 /* Write out the instruction. */
91fdca6f
GM		 1462 total_len = insn->len + (insn->has_limm ? 4 : 0);
1463 if (!relax)
1464 f = frag_more (total_len);
1465
1466 md_number_to_chars_midend(f, insn->insn, insn->len);
1467
1468 if (insn->has_limm)
1469 md_number_to_chars_midend (f + insn->len, insn->limm, 4);
1470 dwarf2_emit_insn (total_len);
252b5132 1471
4670103e
CZ		 1472 if (!relax)
1473 apply_fixups (insn, frag_now, (f - frag_now->fr_literal));
1474}
252b5132 1475
4670103e
CZ		 1476static void
1477emit_insn1 (struct arc_insn *insn)
1478{
1479 /* How frag_var's args are currently configured:
1480 - rs_machine_dependent, to dictate it's a relaxation frag.
1481 - FRAG_MAX_GROWTH, maximum size of instruction
1482 - 0, variable size that might grow...unused by generic relaxation.
1483 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1484 - s, opand expression.
1485 - 0, offset but it's unused.
1486 - 0, opcode but it's unused. */
1487 symbolS *s = make_expr_symbol (&insn->fixups[0].exp);
1488 frag_now->tc_frag_data.pcrel = insn->fixups[0].pcrel;
1489
1490 if (frag_room () < FRAG_MAX_GROWTH)
1491 {
1492 /* Handle differently when frag literal memory is exhausted.
1493 This is used because when there's not enough memory left in
1494 the current frag, a new frag is created and the information
1495 we put into frag_now->tc_frag_data is disregarded. */
252b5132 1496
4670103e
CZ		 1497 struct arc_relax_type relax_info_copy;
1498 relax_substateT subtype = frag_now->fr_subtype;
252b5132 1499
4670103e
CZ		 1500 memcpy (&relax_info_copy, &frag_now->tc_frag_data,
1501 sizeof (struct arc_relax_type));
0d2bcfaf 1502
4670103e
CZ		 1503 frag_wane (frag_now);
1504 frag_grow (FRAG_MAX_GROWTH);
0d2bcfaf 1505
4670103e
CZ		 1506 memcpy (&frag_now->tc_frag_data, &relax_info_copy,
1507 sizeof (struct arc_relax_type));
252b5132 1508
4670103e
CZ		 1509 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1510 subtype, s, 0, 0);
1511 }
1512 else
1513 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1514 frag_now->fr_subtype, s, 0, 0);
1515}
252b5132 1516
4670103e
CZ		 1517static void
1518emit_insn (struct arc_insn *insn)
252b5132 1519{
4670103e
CZ		 1520 if (insn->relax)
1521 emit_insn1 (insn);
252b5132 1522 else
4670103e 1523 emit_insn0 (insn, NULL, FALSE);
252b5132
RH		 1524}
1525
4670103e 1526/* Check whether a symbol involves a register. */
252b5132 1527
4670103e
CZ		 1528static bfd_boolean
1529contains_register (symbolS *sym)
252b5132 1530{
4670103e
CZ		 1531 if (sym)
1532 {
1533 expressionS *ex = symbol_get_value_expression (sym);
252b5132 1534
4670103e
CZ		 1535 return ((O_register == ex->X_op)
1536 && !contains_register (ex->X_add_symbol)
1537 && !contains_register (ex->X_op_symbol));
1538 }
1539
1540 return FALSE;
252b5132
RH		 1541}
1542
4670103e 1543/* Returns the register number within a symbol. */
252b5132 1544
4670103e
CZ		 1545static int
1546get_register (symbolS *sym)
252b5132 1547{
4670103e
CZ		 1548 if (!contains_register (sym))
1549 return -1;
0d2bcfaf 1550
4670103e
CZ		 1551 expressionS *ex = symbol_get_value_expression (sym);
1552 return regno (ex->X_add_number);
1553}
252b5132 1554
4670103e
CZ		 1555/* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1556 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
f17c130b 1557
4670103e
CZ		 1558static bfd_boolean
1559generic_reloc_p (extended_bfd_reloc_code_real_type reloc)
1560{
1561 if (!reloc)
1562 return FALSE;
886a2506 1563
4670103e
CZ		 1564 switch (reloc)
1565 {
1566 case BFD_RELOC_ARC_SDA_LDST:
1567 case BFD_RELOC_ARC_SDA_LDST1:
1568 case BFD_RELOC_ARC_SDA_LDST2:
1569 case BFD_RELOC_ARC_SDA16_LD:
1570 case BFD_RELOC_ARC_SDA16_LD1:
1571 case BFD_RELOC_ARC_SDA16_LD2:
1572 case BFD_RELOC_ARC_SDA16_ST2:
1573 case BFD_RELOC_ARC_SDA32_ME:
1574 return FALSE;
1575 default:
1576 return TRUE;
f17c130b 1577 }
252b5132
RH		 1578}
1579
4670103e 1580/* Allocates a tok entry. */
252b5132 1581
4670103e
CZ		 1582static int
1583allocate_tok (expressionS *tok, int ntok, int cidx)
252b5132 1584{
4670103e
CZ		 1585 if (ntok > MAX_INSN_ARGS - 2)
1586 return 0; /* No space left. */
252b5132 1587
4670103e 1588 if (cidx > ntok)
33eaf5de 1589 return 0; /* Incorrect args. */
252b5132 1590
4670103e 1591 memcpy (&tok[ntok+1], &tok[ntok], sizeof (*tok));
252b5132 1592
4670103e
CZ		 1593 if (cidx == ntok)
1594 return 1; /* Success. */
1595 return allocate_tok (tok, ntok - 1, cidx);
1596}
886a2506 1597
8ddf6b2a
CZ		 1598/* Check if an particular ARC feature is enabled. */
1599
1600static bfd_boolean
1601check_cpu_feature (insn_subclass_t sc)
1602{
53a346d8 1603 if (is_code_density_p (sc) && !(selected_cpu.features & CD))
8ddf6b2a
CZ		 1604 return FALSE;
1605
53a346d8 1606 if (is_spfp_p (sc) && !(selected_cpu.features & SPX))
8ddf6b2a
CZ		 1607 return FALSE;
1608
53a346d8 1609 if (is_dpfp_p (sc) && !(selected_cpu.features & DPX))
8ddf6b2a
CZ		 1610 return FALSE;
1611
53a346d8 1612 if (is_fpuda_p (sc) && !(selected_cpu.features & DPA))
bdd582db
GM		 1613 return FALSE;
1614
53a346d8 1615 if (is_nps400_p (sc) && !(selected_cpu.features & NPS400))
8ddf6b2a
CZ		 1616 return FALSE;
1617
1618 return TRUE;
1619}
1620
4eb6f892
AB		 1621/* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1622 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1623 array and returns TRUE if the flag operands all match, otherwise,
1624 returns FALSE, in which case the FIRST_PFLAG array may have been
1625 modified. */
1626
1627static bfd_boolean
1628parse_opcode_flags (const struct arc_opcode *opcode,
1629 int nflgs,
1630 struct arc_flags *first_pflag)
1631{
1632 int lnflg, i;
1633 const unsigned char *flgidx;
1634
1635 lnflg = nflgs;
1636 for (i = 0; i < nflgs; i++)
1637 first_pflag[i].flgp = NULL;
1638
1639 /* Check the flags. Iterate over the valid flag classes. */
1640 for (flgidx = opcode->flags; *flgidx; ++flgidx)
1641 {
1642 /* Get a valid flag class. */
1643 const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
1644 const unsigned *flgopridx;
1645 int cl_matches = 0;
1646 struct arc_flags *pflag = NULL;
1647
6ec7c1ae
CZ		 1648 /* Check if opcode has implicit flag classes. */
1649 if (cl_flags->flag_class & F_CLASS_IMPLICIT)
1650 continue;
1651
4eb6f892
AB		 1652 /* Check for extension conditional codes. */
1653 if (ext_condcode.arc_ext_condcode
1654 && cl_flags->flag_class & F_CLASS_EXTEND)
1655 {
1656 struct arc_flag_operand *pf = ext_condcode.arc_ext_condcode;
1657 while (pf->name)
1658 {
1659 pflag = first_pflag;
1660 for (i = 0; i < nflgs; i++, pflag++)
1661 {
1662 if (!strcmp (pf->name, pflag->name))
1663 {
1664 if (pflag->flgp != NULL)
1665 return FALSE;
1666 /* Found it. */
1667 cl_matches++;
1668 pflag->flgp = pf;
1669 lnflg--;
1670 break;
1671 }
1672 }
1673 pf++;
1674 }
1675 }
1676
1677 for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
1678 {
1679 const struct arc_flag_operand *flg_operand;
1680
1681 pflag = first_pflag;
1682 flg_operand = &arc_flag_operands[*flgopridx];
1683 for (i = 0; i < nflgs; i++, pflag++)
1684 {
1685 /* Match against the parsed flags. */
1686 if (!strcmp (flg_operand->name, pflag->name))
1687 {
1688 if (pflag->flgp != NULL)
1689 return FALSE;
1690 cl_matches++;
1691 pflag->flgp = flg_operand;
1692 lnflg--;
1693 break; /* goto next flag class and parsed flag. */
1694 }
1695 }
1696 }
1697
1698 if ((cl_flags->flag_class & F_CLASS_REQUIRED) && cl_matches == 0)
1699 return FALSE;
1700 if ((cl_flags->flag_class & F_CLASS_OPTIONAL) && cl_matches > 1)
1701 return FALSE;
1702 }
1703
1704 /* Did I check all the parsed flags? */
1705 return lnflg ? FALSE : TRUE;
1706}
1707
1708
4670103e
CZ		 1709/* Search forward through all variants of an opcode looking for a
1710 syntax match. */
886a2506 1711
4670103e 1712static const struct arc_opcode *
b9b47ab7 1713find_opcode_match (const struct arc_opcode_hash_entry *entry,
4670103e
CZ		 1714 expressionS *tok,
1715 int *pntok,
1716 struct arc_flags *first_pflag,
1717 int nflgs,
abe7c33b
CZ		 1718 int *pcpumatch,
1719 const char **errmsg)
4670103e 1720{
1328504b
AB		 1721 const struct arc_opcode *opcode;
1722 struct arc_opcode_hash_entry_iterator iter;
4670103e
CZ		 1723 int ntok = *pntok;
1724 int got_cpu_match = 0;
1725 expressionS bktok[MAX_INSN_ARGS];
1726 int bkntok;
1727 expressionS emptyE;
886a2506 1728
1328504b 1729 arc_opcode_hash_entry_iterator_init (&iter);
4670103e
CZ		 1730 memset (&emptyE, 0, sizeof (emptyE));
1731 memcpy (bktok, tok, MAX_INSN_ARGS * sizeof (*tok));
1732 bkntok = ntok;
a161fe53 1733
1328504b
AB		 1734 for (opcode = arc_opcode_hash_entry_iterator_next (entry, &iter);
1735 opcode != NULL;
1736 opcode = arc_opcode_hash_entry_iterator_next (entry, &iter))
252b5132 1737 {
4670103e 1738 const unsigned char *opidx;
4eb6f892 1739 int tokidx = 0;
4670103e 1740 const expressionS *t = &emptyE;
252b5132 1741
bdfe53e3 1742 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08llX ",
4670103e 1743 frag_now->fr_file, frag_now->fr_line, opcode->opcode);
886a2506 1744
4670103e
CZ		 1745 /* Don't match opcodes that don't exist on this
1746 architecture. */
bb65a718 1747 if (!(opcode->cpu & selected_cpu.flags))
4670103e 1748 goto match_failed;
886a2506 1749
8ddf6b2a 1750 if (!check_cpu_feature (opcode->subclass))
4670103e 1751 goto match_failed;
886a2506 1752
4670103e
CZ		 1753 got_cpu_match = 1;
1754 pr_debug ("cpu ");
886a2506 1755
4670103e
CZ		 1756 /* Check the operands. */
1757 for (opidx = opcode->operands; *opidx; ++opidx)
252b5132 1758 {
4670103e 1759 const struct arc_operand *operand = &arc_operands[*opidx];
252b5132 1760
4670103e 1761 /* Only take input from real operands. */
db18dbab 1762 if (ARC_OPERAND_IS_FAKE (operand))
4670103e 1763 continue;
252b5132 1764
4670103e
CZ		 1765 /* When we expect input, make sure we have it. */
1766 if (tokidx >= ntok)
1767 goto match_failed;
6f4b1afc 1768
4670103e
CZ		 1769 /* Match operand type with expression type. */
1770 switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK)
1771 {
db18dbab 1772 case ARC_OPERAND_ADDRTYPE:
b437d035 1773 {
abe7c33b 1774 *errmsg = NULL;
b437d035
AB		 1775
1776 /* Check to be an address type. */
1777 if (tok[tokidx].X_op != O_addrtype)
1778 goto match_failed;
1779
1780 /* All address type operands need to have an insert
1781 method in order to check that we have the correct
1782 address type. */
1783 gas_assert (operand->insert != NULL);
1784 (*operand->insert) (0, tok[tokidx].X_add_number,
abe7c33b
CZ		 1785 errmsg);
1786 if (*errmsg != NULL)
b437d035
AB		 1787 goto match_failed;
1788 }
db18dbab
GM		 1789 break;
1790
4670103e
CZ		 1791 case ARC_OPERAND_IR:
1792 /* Check to be a register. */
1793 if ((tok[tokidx].X_op != O_register
1794 || !is_ir_num (tok[tokidx].X_add_number))
1795 && !(operand->flags & ARC_OPERAND_IGNORE))
1796 goto match_failed;
1797
1798 /* If expect duplicate, make sure it is duplicate. */
1799 if (operand->flags & ARC_OPERAND_DUPLICATE)
1800 {
1801 /* Check for duplicate. */
1802 if (t->X_op != O_register
1803 || !is_ir_num (t->X_add_number)
1804 || (regno (t->X_add_number) !=
1805 regno (tok[tokidx].X_add_number)))
1806 goto match_failed;
1807 }
1808
1809 /* Special handling? */
1810 if (operand->insert)
1811 {
abe7c33b 1812 *errmsg = NULL;
4670103e
CZ		 1813 (*operand->insert)(0,
1814 regno (tok[tokidx].X_add_number),
abe7c33b
CZ		 1815 errmsg);
1816 if (*errmsg)
4670103e
CZ		 1817 {
1818 if (operand->flags & ARC_OPERAND_IGNORE)
1819 {
1820 /* Missing argument, create one. */
1821 if (!allocate_tok (tok, ntok - 1, tokidx))
1822 goto match_failed;
1823
1824 tok[tokidx].X_op = O_absent;
1825 ++ntok;
1826 }
1827 else
1828 goto match_failed;
1829 }
1830 }
1831
1832 t = &tok[tokidx];
1833 break;
1834
1835 case ARC_OPERAND_BRAKET:
1836 /* Check if bracket is also in opcode table as
1837 operand. */
1838 if (tok[tokidx].X_op != O_bracket)
1839 goto match_failed;
1840 break;
1841
db18dbab
GM		 1842 case ARC_OPERAND_COLON:
1843 /* Check if colon is also in opcode table as operand. */
1844 if (tok[tokidx].X_op != O_colon)
1845 goto match_failed;
1846 break;
1847
4670103e
CZ		 1848 case ARC_OPERAND_LIMM:
1849 case ARC_OPERAND_SIGNED:
1850 case ARC_OPERAND_UNSIGNED:
1851 switch (tok[tokidx].X_op)
1852 {
1853 case O_illegal:
1854 case O_absent:
1855 case O_register:
1856 goto match_failed;
1857
1858 case O_bracket:
1859 /* Got an (too) early bracket, check if it is an
1860 ignored operand. N.B. This procedure works only
1861 when bracket is the last operand! */
1862 if (!(operand->flags & ARC_OPERAND_IGNORE))
1863 goto match_failed;
1864 /* Insert the missing operand. */
1865 if (!allocate_tok (tok, ntok - 1, tokidx))
1866 goto match_failed;
1867
1868 tok[tokidx].X_op = O_absent;
1869 ++ntok;
1870 break;
1871
22b92fc4
AB		 1872 case O_symbol:
1873 {
1874 const char *p;
22b92fc4 1875 const struct arc_aux_reg *auxr;
22b92fc4 1876
c810e0b8 1877 if (opcode->insn_class != AUXREG)
22b92fc4
AB		 1878 goto de_fault;
1879 p = S_GET_NAME (tok[tokidx].X_add_symbol);
f36e33da
CZ		 1880
1881 auxr = hash_find (arc_aux_hash, p);
1882 if (auxr)
1883 {
1884 /* We modify the token array here, safe in the
1885 knowledge, that if this was the wrong
1886 choice then the original contents will be
1887 restored from BKTOK. */
1888 tok[tokidx].X_op = O_constant;
1889 tok[tokidx].X_add_number = auxr->address;
1890 ARC_SET_FLAG (tok[tokidx].X_add_symbol, ARC_FLAG_AUX);
1891 }
22b92fc4
AB		 1892
1893 if (tok[tokidx].X_op != O_constant)
1894 goto de_fault;
1895 }
1a0670f3 1896 /* Fall through. */
4670103e
CZ		 1897 case O_constant:
1898 /* Check the range. */
1899 if (operand->bits != 32
1900 && !(operand->flags & ARC_OPERAND_NCHK))
1901 {
1902 offsetT min, max, val;
1903 val = tok[tokidx].X_add_number;
1904
1905 if (operand->flags & ARC_OPERAND_SIGNED)
1906 {
1907 max = (1 << (operand->bits - 1)) - 1;
1908 min = -(1 << (operand->bits - 1));
1909 }
1910 else
1911 {
1912 max = (1 << operand->bits) - 1;
1913 min = 0;
1914 }
1915
1916 if (val < min || val > max)
1917 goto match_failed;
1918
33eaf5de 1919 /* Check alignments. */
4670103e
CZ		 1920 if ((operand->flags & ARC_OPERAND_ALIGNED32)
1921 && (val & 0x03))
1922 goto match_failed;
1923
1924 if ((operand->flags & ARC_OPERAND_ALIGNED16)
1925 && (val & 0x01))
1926 goto match_failed;
1927 }
1928 else if (operand->flags & ARC_OPERAND_NCHK)
1929 {
1930 if (operand->insert)
1931 {
abe7c33b 1932 *errmsg = NULL;
4670103e
CZ		 1933 (*operand->insert)(0,
1934 tok[tokidx].X_add_number,
abe7c33b
CZ		 1935 errmsg);
1936 if (*errmsg)
4670103e
CZ		 1937 goto match_failed;
1938 }
4eb6f892 1939 else if (!(operand->flags & ARC_OPERAND_IGNORE))
4670103e
CZ		 1940 goto match_failed;
1941 }
1942 break;
1943
1944 case O_subtract:
1945 /* Check if it is register range. */
1946 if ((tok[tokidx].X_add_number == 0)
1947 && contains_register (tok[tokidx].X_add_symbol)
1948 && contains_register (tok[tokidx].X_op_symbol))
1949 {
1950 int regs;
1951
1952 regs = get_register (tok[tokidx].X_add_symbol);
1953 regs <<= 16;
1954 regs |= get_register (tok[tokidx].X_op_symbol);
1955 if (operand->insert)
1956 {
abe7c33b 1957 *errmsg = NULL;
4670103e
CZ		 1958 (*operand->insert)(0,
1959 regs,
abe7c33b
CZ		 1960 errmsg);
1961 if (*errmsg)
4670103e
CZ		 1962 goto match_failed;
1963 }
1964 else
1965 goto match_failed;
1966 break;
1967 }
1a0670f3 1968 /* Fall through. */
4670103e 1969 default:
22b92fc4 1970 de_fault:
4670103e
CZ		 1971 if (operand->default_reloc == 0)
1972 goto match_failed; /* The operand needs relocation. */
1973
1974 /* Relocs requiring long immediate. FIXME! make it
1975 generic and move it to a function. */
1976 switch (tok[tokidx].X_md)
1977 {
1978 case O_gotoff:
1979 case O_gotpc:
1980 case O_pcl:
1981 case O_tpoff:
1982 case O_dtpoff:
1983 case O_tlsgd:
1984 case O_tlsie:
1985 if (!(operand->flags & ARC_OPERAND_LIMM))
1986 goto match_failed;
1a0670f3 1987 /* Fall through. */
4670103e
CZ		 1988 case O_absent:
1989 if (!generic_reloc_p (operand->default_reloc))
1990 goto match_failed;
2b804145 1991 break;
4670103e
CZ		 1992 default:
1993 break;
1994 }
1995 break;
1996 }
1997 /* If expect duplicate, make sure it is duplicate. */
1998 if (operand->flags & ARC_OPERAND_DUPLICATE)
1999 {
2000 if (t->X_op == O_illegal
2001 || t->X_op == O_absent
2002 || t->X_op == O_register
2003 || (t->X_add_number != tok[tokidx].X_add_number))
2004 goto match_failed;
2005 }
2006 t = &tok[tokidx];
2007 break;
2008
2009 default:
2010 /* Everything else should have been fake. */
2011 abort ();
2012 }
2013
2014 ++tokidx;
2015 }
2016 pr_debug ("opr ");
2017
1ae8ab47 2018 /* Setup ready for flag parsing. */
4eb6f892 2019 if (!parse_opcode_flags (opcode, nflgs, first_pflag))
4670103e
CZ		 2020 goto match_failed;
2021
2022 pr_debug ("flg");
2023 /* Possible match -- did we use all of our input? */
2024 if (tokidx == ntok)
2025 {
2026 *pntok = ntok;
2027 pr_debug ("\n");
2028 return opcode;
2029 }
2030
2031 match_failed:;
2032 pr_debug ("\n");
2033 /* Restore the original parameters. */
2034 memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok));
2035 ntok = bkntok;
2036 }
4670103e
CZ		 2037
2038 if (*pcpumatch)
2039 *pcpumatch = got_cpu_match;
2040
2041 return NULL;
2042}
2043
2044/* Swap operand tokens. */
2045
2046static void
2047swap_operand (expressionS *operand_array,
2048 unsigned source,
2049 unsigned destination)
2050{
2051 expressionS cpy_operand;
2052 expressionS *src_operand;
2053 expressionS *dst_operand;
2054 size_t size;
2055
2056 if (source == destination)
2057 return;
2058
2059 src_operand = &operand_array[source];
2060 dst_operand = &operand_array[destination];
2061 size = sizeof (expressionS);
2062
2063 /* Make copy of operand to swap with and swap. */
2064 memcpy (&cpy_operand, dst_operand, size);
2065 memcpy (dst_operand, src_operand, size);
2066 memcpy (src_operand, &cpy_operand, size);
2067}
2068
2069/* Check if *op matches *tok type.
2070 Returns FALSE if they don't match, TRUE if they match. */
2071
2072static bfd_boolean
2073pseudo_operand_match (const expressionS *tok,
2074 const struct arc_operand_operation *op)
2075{
2076 offsetT min, max, val;
2077 bfd_boolean ret;
2078 const struct arc_operand *operand_real = &arc_operands[op->operand_idx];
2079
2080 ret = FALSE;
2081 switch (tok->X_op)
2082 {
2083 case O_constant:
2084 if (operand_real->bits == 32 && (operand_real->flags & ARC_OPERAND_LIMM))
2085 ret = 1;
2086 else if (!(operand_real->flags & ARC_OPERAND_IR))
2087 {
2088 val = tok->X_add_number + op->count;
2089 if (operand_real->flags & ARC_OPERAND_SIGNED)
2090 {
2091 max = (1 << (operand_real->bits - 1)) - 1;
2092 min = -(1 << (operand_real->bits - 1));
2093 }
2094 else
2095 {
2096 max = (1 << operand_real->bits) - 1;
2097 min = 0;
2098 }
2099 if (min <= val && val <= max)
2100 ret = TRUE;
2101 }
6f4b1afc
CM		 2102 break;
2103
4670103e
CZ		 2104 case O_symbol:
2105 /* Handle all symbols as long immediates or signed 9. */
db18dbab
GM		 2106 if (operand_real->flags & ARC_OPERAND_LIMM
2107 || ((operand_real->flags & ARC_OPERAND_SIGNED)
2108 && operand_real->bits == 9))
4670103e 2109 ret = TRUE;
6f4b1afc
CM		 2110 break;
2111
4670103e
CZ		 2112 case O_register:
2113 if (operand_real->flags & ARC_OPERAND_IR)
2114 ret = TRUE;
2115 break;
2116
2117 case O_bracket:
2118 if (operand_real->flags & ARC_OPERAND_BRAKET)
2119 ret = TRUE;
6f4b1afc
CM		 2120 break;
2121
2122 default:
4670103e 2123 /* Unknown. */
6f4b1afc
CM		 2124 break;
2125 }
4670103e
CZ		 2126 return ret;
2127}
6f4b1afc 2128
4670103e
CZ		 2129/* Find pseudo instruction in array. */
2130
2131static const struct arc_pseudo_insn *
2132find_pseudo_insn (const char *opname,
2133 int ntok,
2134 const expressionS *tok)
2135{
2136 const struct arc_pseudo_insn *pseudo_insn = NULL;
2137 const struct arc_operand_operation *op;
2138 unsigned int i;
2139 int j;
2140
2141 for (i = 0; i < arc_num_pseudo_insn; ++i)
6f4b1afc 2142 {
4670103e
CZ		 2143 pseudo_insn = &arc_pseudo_insns[i];
2144 if (strcmp (pseudo_insn->mnemonic_p, opname) == 0)
2145 {
2146 op = pseudo_insn->operand;
2147 for (j = 0; j < ntok; ++j)
2148 if (!pseudo_operand_match (&tok[j], &op[j]))
2149 break;
2150
2151 /* Found the right instruction. */
2152 if (j == ntok)
2153 return pseudo_insn;
2154 }
6f4b1afc 2155 }
4670103e
CZ		 2156 return NULL;
2157}
252b5132 2158
4670103e 2159/* Assumes the expressionS *tok is of sufficient size. */
252b5132 2160
b9b47ab7 2161static const struct arc_opcode_hash_entry *
4670103e
CZ		 2162find_special_case_pseudo (const char *opname,
2163 int *ntok,
2164 expressionS *tok,
2165 int *nflgs,
2166 struct arc_flags *pflags)
2167{
2168 const struct arc_pseudo_insn *pseudo_insn = NULL;
2169 const struct arc_operand_operation *operand_pseudo;
2170 const struct arc_operand *operand_real;
2171 unsigned i;
2172 char construct_operand[MAX_CONSTR_STR];
886a2506 2173
4670103e
CZ		 2174 /* Find whether opname is in pseudo instruction array. */
2175 pseudo_insn = find_pseudo_insn (opname, *ntok, tok);
2176
2177 if (pseudo_insn == NULL)
2178 return NULL;
2179
2180 /* Handle flag, Limited to one flag at the moment. */
2181 if (pseudo_insn->flag_r != NULL)
2182 *nflgs += tokenize_flags (pseudo_insn->flag_r, &pflags[*nflgs],
2183 MAX_INSN_FLGS - *nflgs);
2184
2185 /* Handle operand operations. */
2186 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
252b5132 2187 {
4670103e
CZ		 2188 operand_pseudo = &pseudo_insn->operand[i];
2189 operand_real = &arc_operands[operand_pseudo->operand_idx];
886a2506 2190
db18dbab
GM		 2191 if (operand_real->flags & ARC_OPERAND_BRAKET
2192 && !operand_pseudo->needs_insert)
4670103e 2193 continue;
b125bd17 2194
4670103e
CZ		 2195 /* Has to be inserted (i.e. this token does not exist yet). */
2196 if (operand_pseudo->needs_insert)
2197 {
2198 if (operand_real->flags & ARC_OPERAND_BRAKET)
2199 {
2200 tok[i].X_op = O_bracket;
2201 ++(*ntok);
2202 continue;
2203 }
b125bd17 2204
4670103e
CZ		 2205 /* Check if operand is a register or constant and handle it
2206 by type. */
2207 if (operand_real->flags & ARC_OPERAND_IR)
2208 snprintf (construct_operand, MAX_CONSTR_STR, "r%d",
2209 operand_pseudo->count);
2210 else
2211 snprintf (construct_operand, MAX_CONSTR_STR, "%d",
2212 operand_pseudo->count);
886a2506 2213
4670103e
CZ		 2214 tokenize_arguments (construct_operand, &tok[i], 1);
2215 ++(*ntok);
2216 }
2217
2218 else if (operand_pseudo->count)
2219 {
2220 /* Operand number has to be adjusted accordingly (by operand
2221 type). */
2222 switch (tok[i].X_op)
2223 {
2224 case O_constant:
2225 tok[i].X_add_number += operand_pseudo->count;
2226 break;
2227
2228 case O_symbol:
2229 break;
2230
2231 default:
2232 /* Ignored. */
2233 break;
2234 }
2235 }
2236 }
2237
2238 /* Swap operands if necessary. Only supports one swap at the
2239 moment. */
2240 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
2241 {
2242 operand_pseudo = &pseudo_insn->operand[i];
2243
2244 if (operand_pseudo->swap_operand_idx == i)
2245 continue;
2246
2247 swap_operand (tok, i, operand_pseudo->swap_operand_idx);
2248
2249 /* Prevent a swap back later by breaking out. */
2250 break;
2251 }
2252
da5be039 2253 return arc_find_opcode (pseudo_insn->mnemonic_r);
4670103e
CZ		 2254}
2255
b9b47ab7 2256static const struct arc_opcode_hash_entry *
4670103e
CZ		 2257find_special_case_flag (const char *opname,
2258 int *nflgs,
2259 struct arc_flags *pflags)
2260{
2261 unsigned int i;
2262 const char *flagnm;
2263 unsigned flag_idx, flag_arr_idx;
2264 size_t flaglen, oplen;
2265 const struct arc_flag_special *arc_flag_special_opcode;
b9b47ab7 2266 const struct arc_opcode_hash_entry *entry;
4670103e
CZ		 2267
2268 /* Search for special case instruction. */
2269 for (i = 0; i < arc_num_flag_special; i++)
2270 {
2271 arc_flag_special_opcode = &arc_flag_special_cases[i];
2272 oplen = strlen (arc_flag_special_opcode->name);
2273
2274 if (strncmp (opname, arc_flag_special_opcode->name, oplen) != 0)
2275 continue;
2276
2277 /* Found a potential special case instruction, now test for
2278 flags. */
2279 for (flag_arr_idx = 0;; ++flag_arr_idx)
2280 {
2281 flag_idx = arc_flag_special_opcode->flags[flag_arr_idx];
2282 if (flag_idx == 0)
2283 break; /* End of array, nothing found. */
886a2506 2284
4670103e
CZ		 2285 flagnm = arc_flag_operands[flag_idx].name;
2286 flaglen = strlen (flagnm);
2287 if (strcmp (opname + oplen, flagnm) == 0)
2288 {
b9b47ab7 2289 entry = arc_find_opcode (arc_flag_special_opcode->name);
886a2506 2290
4670103e
CZ		 2291 if (*nflgs + 1 > MAX_INSN_FLGS)
2292 break;
2293 memcpy (pflags[*nflgs].name, flagnm, flaglen);
2294 pflags[*nflgs].name[flaglen] = '\0';
2295 (*nflgs)++;
b9b47ab7 2296 return entry;
4670103e
CZ		 2297 }
2298 }
2299 }
2300 return NULL;
2301}
886a2506 2302
4670103e 2303/* Used to find special case opcode. */
886a2506 2304
b9b47ab7 2305static const struct arc_opcode_hash_entry *
4670103e
CZ		 2306find_special_case (const char *opname,
2307 int *nflgs,
2308 struct arc_flags *pflags,
2309 expressionS *tok,
2310 int *ntok)
2311{
b9b47ab7 2312 const struct arc_opcode_hash_entry *entry;
886a2506 2313
b9b47ab7 2314 entry = find_special_case_pseudo (opname, ntok, tok, nflgs, pflags);
886a2506 2315
b9b47ab7
AB		 2316 if (entry == NULL)
2317 entry = find_special_case_flag (opname, nflgs, pflags);
886a2506 2318
b9b47ab7 2319 return entry;
4670103e 2320}
886a2506 2321
53a346d8
CZ		 2322/* Autodetect cpu attribute list. */
2323
2324static void
2325autodetect_attributes (const struct arc_opcode *opcode,
2326 const expressionS *tok,
2327 int ntok)
2328{
2329 unsigned i;
2330 struct mpy_type
2331 {
2332 unsigned feature;
2333 unsigned encoding;
2334 } mpy_list[] = {{ MPY1E, 1 }, { MPY6E, 6 }, { MPY7E, 7 }, { MPY8E, 8 },
2335 { MPY9E, 9 }};
2336
2337 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
2338 if (opcode->subclass == feature_list[i].feature)
2339 selected_cpu.features |= feature_list[i].feature;
2340
2341 for (i = 0; i < ARRAY_SIZE (mpy_list); i++)
2342 if (opcode->subclass == mpy_list[i].feature)
2343 mpy_option = mpy_list[i].encoding;
2344
2345 for (i = 0; i < (unsigned) ntok; i++)
2346 {
2347 switch (tok[i].X_md)
2348 {
2349 case O_gotoff:
2350 case O_gotpc:
2351 case O_plt:
2352 pic_option = 2;
2353 break;
2354 case O_sda:
2355 sda_option = 2;
2356 break;
2357 case O_tlsgd:
2358 case O_tlsie:
2359 case O_tpoff9:
2360 case O_tpoff:
2361 case O_dtpoff9:
2362 case O_dtpoff:
2363 tls_option = 1;
2364 break;
2365 default:
2366 break;
2367 }
2368 }
2369}
2370
2371/* Given an opcode name, pre-tockenized set of argumenst and the
4670103e 2372 opcode flags, take it all the way through emission. */
886a2506 2373
4670103e
CZ		 2374static void
2375assemble_tokens (const char *opname,
2376 expressionS *tok,
2377 int ntok,
2378 struct arc_flags *pflags,
2379 int nflgs)
2380{
2381 bfd_boolean found_something = FALSE;
b9b47ab7 2382 const struct arc_opcode_hash_entry *entry;
4670103e 2383 int cpumatch = 1;
abe7c33b 2384 const char *errmsg = NULL;
886a2506 2385
4670103e 2386 /* Search opcodes. */
b9b47ab7 2387 entry = arc_find_opcode (opname);
886a2506 2388
4670103e 2389 /* Couldn't find opcode conventional way, try special cases. */
b9b47ab7
AB		 2390 if (entry == NULL)
2391 entry = find_special_case (opname, &nflgs, pflags, tok, &ntok);
886a2506 2392
b9b47ab7 2393 if (entry != NULL)
4670103e 2394 {
b9b47ab7
AB		 2395 const struct arc_opcode *opcode;
2396
1328504b
AB		 2397 pr_debug ("%s:%d: assemble_tokens: %s\n",
2398 frag_now->fr_file, frag_now->fr_line, opname);
4670103e 2399 found_something = TRUE;
b9b47ab7 2400 opcode = find_opcode_match (entry, tok, &ntok, pflags,
abe7c33b 2401 nflgs, &cpumatch, &errmsg);
b9b47ab7 2402 if (opcode != NULL)
4670103e
CZ		 2403 {
2404 struct arc_insn insn;
b9b47ab7 2405
53a346d8 2406 autodetect_attributes (opcode, tok, ntok);
4670103e
CZ		 2407 assemble_insn (opcode, tok, ntok, pflags, nflgs, &insn);
2408 emit_insn (&insn);
2409 return;
2410 }
2411 }
886a2506 2412
4670103e
CZ		 2413 if (found_something)
2414 {
2415 if (cpumatch)
abe7c33b
CZ		 2416 if (errmsg)
2417 as_bad (_("%s for instruction '%s'"), errmsg, opname);
2418 else
2419 as_bad (_("inappropriate arguments for opcode '%s'"), opname);
4670103e
CZ		 2420 else
2421 as_bad (_("opcode '%s' not supported for target %s"), opname,
bb65a718 2422 selected_cpu.name);
4670103e
CZ		 2423 }
2424 else
2425 as_bad (_("unknown opcode '%s'"), opname);
886a2506
NC		 2426}
2427
4670103e 2428/* The public interface to the instruction assembler. */
886a2506 2429
4670103e
CZ		 2430void
2431md_assemble (char *str)
886a2506 2432{
4670103e
CZ		 2433 char *opname;
2434 expressionS tok[MAX_INSN_ARGS];
2435 int ntok, nflg;
2436 size_t opnamelen;
2437 struct arc_flags flags[MAX_INSN_FLGS];
886a2506 2438
4670103e
CZ		 2439 /* Split off the opcode. */
2440 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_0123468");
29a2809e 2441 opname = xmemdup0 (str, opnamelen);
886a2506 2442
33eaf5de 2443 /* Signalize we are assembling the instructions. */
4670103e 2444 assembling_insn = TRUE;
886a2506 2445
4670103e
CZ		 2446 /* Tokenize the flags. */
2447 if ((nflg = tokenize_flags (str + opnamelen, flags, MAX_INSN_FLGS)) == -1)
2448 {
2449 as_bad (_("syntax error"));
2450 return;
2451 }
886a2506 2452
4670103e
CZ		 2453 /* Scan up to the end of the mnemonic which must end in space or end
2454 of string. */
2455 str += opnamelen;
2456 for (; *str != '\0'; str++)
2457 if (*str == ' ')
2458 break;
886a2506 2459
4670103e
CZ		 2460 /* Tokenize the rest of the line. */
2461 if ((ntok = tokenize_arguments (str, tok, MAX_INSN_ARGS)) < 0)
886a2506 2462 {
4670103e
CZ		 2463 as_bad (_("syntax error"));
2464 return;
252b5132
RH		 2465 }
2466
4670103e
CZ		 2467 /* Finish it off. */
2468 assemble_tokens (opname, tok, ntok, flags, nflg);
2469 assembling_insn = FALSE;
2470}
2471
2472/* Callback to insert a register into the hash table. */
2473
2474static void
f86f5863 2475declare_register (const char *name, int number)
4670103e
CZ		 2476{
2477 const char *err;
2478 symbolS *regS = symbol_create (name, reg_section,
2479 number, &zero_address_frag);
2480
2481 err = hash_insert (arc_reg_hash, S_GET_NAME (regS), (void *) regS);
2482 if (err)
e6ba1cba 2483 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
4670103e
CZ		 2484 name, err);
2485}
252b5132 2486
4670103e 2487/* Construct symbols for each of the general registers. */
252b5132 2488
4670103e
CZ		 2489static void
2490declare_register_set (void)
2491{
2492 int i;
2493 for (i = 0; i < 64; ++i)
886a2506 2494 {
4670103e
CZ		 2495 char name[7];
2496
2497 sprintf (name, "r%d", i);
2498 declare_register (name, i);
2499 if ((i & 0x01) == 0)
886a2506 2500 {
4670103e
CZ		 2501 sprintf (name, "r%dr%d", i, i+1);
2502 declare_register (name, i);
886a2506
NC		 2503 }
2504 }
252b5132 2505}
ea1562b3 2506
db18dbab
GM		 2507/* Construct a symbol for an address type. */
2508
2509static void
2510declare_addrtype (const char *name, int number)
2511{
2512 const char *err;
2513 symbolS *addrtypeS = symbol_create (name, undefined_section,
2514 number, &zero_address_frag);
2515
2516 err = hash_insert (arc_addrtype_hash, S_GET_NAME (addrtypeS),
2517 (void *) addrtypeS);
2518 if (err)
2519 as_fatal (_("Inserting \"%s\" into address type table failed: %s"),
2520 name, err);
2521}
2522
4670103e
CZ		 2523/* Port-specific assembler initialization. This function is called
2524 once, at assembler startup time. */
ea1562b3
NC		 2525
2526void
4670103e 2527md_begin (void)
ea1562b3 2528{
b99747ae 2529 const struct arc_opcode *opcode = arc_opcodes;
886a2506 2530
bb65a718
AB		 2531 if (mach_selection_mode == MACH_SELECTION_NONE)
2532 arc_select_cpu (TARGET_WITH_CPU, MACH_SELECTION_FROM_DEFAULT);
24740d83 2533
4670103e
CZ		 2534 /* The endianness can be chosen "at the factory". */
2535 target_big_endian = byte_order == BIG_ENDIAN;
886a2506 2536
bb65a718 2537 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
4670103e
CZ		 2538 as_warn (_("could not set architecture and machine"));
2539
2540 /* Set elf header flags. */
bb65a718 2541 bfd_set_private_flags (stdoutput, selected_cpu.eflags);
4670103e
CZ		 2542
2543 /* Set up a hash table for the instructions. */
2544 arc_opcode_hash = hash_new ();
2545 if (arc_opcode_hash == NULL)
2546 as_fatal (_("Virtual memory exhausted"));
2547
2548 /* Initialize the hash table with the insns. */
b99747ae 2549 do
ea1562b3 2550 {
b99747ae 2551 const char *name = opcode->name;
da5be039 2552
b99747ae 2553 arc_insert_opcode (opcode);
4670103e 2554
b99747ae
CZ		 2555 while (++opcode && opcode->name
2556 && (opcode->name == name
2557 || !strcmp (opcode->name, name)))
4670103e 2558 continue;
b99747ae 2559 }while (opcode->name);
4670103e
CZ		 2560
2561 /* Register declaration. */
2562 arc_reg_hash = hash_new ();
2563 if (arc_reg_hash == NULL)
2564 as_fatal (_("Virtual memory exhausted"));
2565
2566 declare_register_set ();
2567 declare_register ("gp", 26);
2568 declare_register ("fp", 27);
2569 declare_register ("sp", 28);
2570 declare_register ("ilink", 29);
2571 declare_register ("ilink1", 29);
2572 declare_register ("ilink2", 30);
2573 declare_register ("blink", 31);
2574
87789e08
CZ		 2575 /* XY memory registers. */
2576 declare_register ("x0_u0", 32);
2577 declare_register ("x0_u1", 33);
2578 declare_register ("x1_u0", 34);
2579 declare_register ("x1_u1", 35);
2580 declare_register ("x2_u0", 36);
2581 declare_register ("x2_u1", 37);
2582 declare_register ("x3_u0", 38);
2583 declare_register ("x3_u1", 39);
2584 declare_register ("y0_u0", 40);
2585 declare_register ("y0_u1", 41);
2586 declare_register ("y1_u0", 42);
2587 declare_register ("y1_u1", 43);
2588 declare_register ("y2_u0", 44);
2589 declare_register ("y2_u1", 45);
2590 declare_register ("y3_u0", 46);
2591 declare_register ("y3_u1", 47);
2592 declare_register ("x0_nu", 48);
2593 declare_register ("x1_nu", 49);
2594 declare_register ("x2_nu", 50);
2595 declare_register ("x3_nu", 51);
2596 declare_register ("y0_nu", 52);
2597 declare_register ("y1_nu", 53);
2598 declare_register ("y2_nu", 54);
2599 declare_register ("y3_nu", 55);
2600
4670103e
CZ		 2601 declare_register ("mlo", 57);
2602 declare_register ("mmid", 58);
2603 declare_register ("mhi", 59);
2604
2605 declare_register ("acc1", 56);
2606 declare_register ("acc2", 57);
2607
2608 declare_register ("lp_count", 60);
2609 declare_register ("pcl", 63);
2610
2611 /* Initialize the last instructions. */
2612 memset (&arc_last_insns[0], 0, sizeof (arc_last_insns));
f36e33da
CZ		 2613
2614 /* Aux register declaration. */
2615 arc_aux_hash = hash_new ();
2616 if (arc_aux_hash == NULL)
2617 as_fatal (_("Virtual memory exhausted"));
2618
2619 const struct arc_aux_reg *auxr = &arc_aux_regs[0];
2620 unsigned int i;
2621 for (i = 0; i < arc_num_aux_regs; i++, auxr++)
2622 {
2623 const char *retval;
2624
bb65a718 2625 if (!(auxr->cpu & selected_cpu.flags))
f36e33da
CZ		 2626 continue;
2627
2628 if ((auxr->subclass != NONE)
2629 && !check_cpu_feature (auxr->subclass))
2630 continue;
2631
2632 retval = hash_insert (arc_aux_hash, auxr->name, (void *) auxr);
2633 if (retval)
2634 as_fatal (_("internal error: can't hash aux register '%s': %s"),
2635 auxr->name, retval);
2636 }
db18dbab
GM		 2637
2638 /* Address type declaration. */
2639 arc_addrtype_hash = hash_new ();
2640 if (arc_addrtype_hash == NULL)
2641 as_fatal (_("Virtual memory exhausted"));
2642
2643 declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD);
2644 declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID);
2645 declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD);
2646 declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD);
2647 declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD);
2648 declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM);
2649 declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA);
2650 declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD);
2651 declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD);
2652 declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD);
2653 declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID);
2654 declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD);
2655 declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM);
2656 declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD);
2657 declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA);
2658 declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD);
886a2506 2659}
ea1562b3 2660
4670103e
CZ		 2661/* Write a value out to the object file, using the appropriate
2662 endianness. */
ea1562b3 2663
4670103e
CZ		 2664void
2665md_number_to_chars (char *buf,
2666 valueT val,
2667 int n)
886a2506 2668{
4670103e
CZ		 2669 if (target_big_endian)
2670 number_to_chars_bigendian (buf, val, n);
2671 else
2672 number_to_chars_littleendian (buf, val, n);
886a2506 2673}
ea1562b3 2674
4670103e 2675/* Round up a section size to the appropriate boundary. */
ea1562b3 2676
4670103e
CZ		 2677valueT
2678md_section_align (segT segment,
2679 valueT size)
886a2506 2680{
4670103e
CZ		 2681 int align = bfd_get_section_alignment (stdoutput, segment);
2682
2683 return ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
886a2506 2684}
ea1562b3 2685
4670103e
CZ		 2686/* The location from which a PC relative jump should be calculated,
2687 given a PC relative reloc. */
ea1562b3 2688
4670103e
CZ		 2689long
2690md_pcrel_from_section (fixS *fixP,
2691 segT sec)
886a2506 2692{
4670103e 2693 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
ea1562b3 2694
4670103e 2695 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP->fx_offset);
ea1562b3 2696
4670103e
CZ		 2697 if (fixP->fx_addsy != (symbolS *) NULL
2698 && (!S_IS_DEFINED (fixP->fx_addsy)
2699 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
2700 {
2701 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP->fx_addsy));
ea1562b3 2702
4670103e
CZ		 2703 /* The symbol is undefined (or is defined but not in this section).
2704 Let the linker figure it out. */
2705 return 0;
2706 }
2707
2708 if ((int) fixP->fx_r_type < 0)
886a2506 2709 {
4670103e
CZ		 2710 /* These are the "internal" relocations. Align them to
2711 32 bit boundary (PCL), for the moment. */
2712 base &= ~3;
886a2506 2713 }
4670103e
CZ		 2714 else
2715 {
2716 switch (fixP->fx_r_type)
2717 {
2718 case BFD_RELOC_ARC_PC32:
2719 /* The hardware calculates relative to the start of the
2720 insn, but this relocation is relative to location of the
2721 LIMM, compensate. The base always needs to be
2b0f3761 2722 subtracted by 4 as we do not support this type of PCrel
4670103e
CZ		 2723 relocation for short instructions. */
2724 base -= 4;
2725 /* Fall through. */
2726 case BFD_RELOC_ARC_PLT32:
2727 case BFD_RELOC_ARC_S25H_PCREL_PLT:
2728 case BFD_RELOC_ARC_S21H_PCREL_PLT:
2729 case BFD_RELOC_ARC_S25W_PCREL_PLT:
2730 case BFD_RELOC_ARC_S21W_PCREL_PLT:
2731
2732 case BFD_RELOC_ARC_S21H_PCREL:
2733 case BFD_RELOC_ARC_S25H_PCREL:
2734 case BFD_RELOC_ARC_S13_PCREL:
2735 case BFD_RELOC_ARC_S21W_PCREL:
2736 case BFD_RELOC_ARC_S25W_PCREL:
2737 base &= ~3;
2738 break;
2739 default:
2740 as_bad_where (fixP->fx_file, fixP->fx_line,
2741 _("unhandled reloc %s in md_pcrel_from_section"),
2742 bfd_get_reloc_code_name (fixP->fx_r_type));
2743 break;
2744 }
2745 }
2746
9e32d9ae
AB		 2747 pr_debug ("pcrel from %"BFD_VMA_FMT"x + %lx = %"BFD_VMA_FMT"x, "
2748 "symbol: %s (%"BFD_VMA_FMT"x)\n",
4670103e
CZ		 2749 fixP->fx_frag->fr_address, fixP->fx_where, base,
2750 fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "(null)",
2751 fixP->fx_addsy ? S_GET_VALUE (fixP->fx_addsy) : 0);
2752
2753 return base;
886a2506 2754}
ea1562b3 2755
33eaf5de 2756/* Given a BFD relocation find the corresponding operand. */
ea1562b3 2757
4670103e
CZ		 2758static const struct arc_operand *
2759find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc)
2760{
2761 unsigned i;
ea1562b3 2762
4670103e
CZ		 2763 for (i = 0; i < arc_num_operands; i++)
2764 if (arc_operands[i].default_reloc == reloc)
2765 return &arc_operands[i];
2766 return NULL;
2767}
ea1562b3 2768
4670103e 2769/* Insert an operand value into an instruction. */
ea1562b3 2770
bdfe53e3
AB		 2771static unsigned long long
2772insert_operand (unsigned long long insn,
4670103e 2773 const struct arc_operand *operand,
bdfe53e3 2774 long long val,
3b4dbbbf 2775 const char *file,
4670103e 2776 unsigned line)
886a2506 2777{
4670103e 2778 offsetT min = 0, max = 0;
ea1562b3 2779
4670103e
CZ		 2780 if (operand->bits != 32
2781 && !(operand->flags & ARC_OPERAND_NCHK)
2782 && !(operand->flags & ARC_OPERAND_FAKE))
886a2506 2783 {
4670103e
CZ		 2784 if (operand->flags & ARC_OPERAND_SIGNED)
2785 {
2786 max = (1 << (operand->bits - 1)) - 1;
2787 min = -(1 << (operand->bits - 1));
2788 }
2789 else
2790 {
2791 max = (1 << operand->bits) - 1;
2792 min = 0;
2793 }
886a2506 2794
4670103e
CZ		 2795 if (val < min || val > max)
2796 as_bad_value_out_of_range (_("operand"),
2797 val, min, max, file, line);
2798 }
ea1562b3 2799
cc07cda6 2800 pr_debug ("insert field: %ld <= %lld <= %ld in 0x%08llx\n",
4670103e 2801 min, val, max, insn);
ea1562b3 2802
4670103e
CZ		 2803 if ((operand->flags & ARC_OPERAND_ALIGNED32)
2804 && (val & 0x03))
2805 as_bad_where (file, line,
2806 _("Unaligned operand. Needs to be 32bit aligned"));
ea1562b3 2807
4670103e
CZ		 2808 if ((operand->flags & ARC_OPERAND_ALIGNED16)
2809 && (val & 0x01))
2810 as_bad_where (file, line,
2811 _("Unaligned operand. Needs to be 16bit aligned"));
ea1562b3 2812
4670103e
CZ		 2813 if (operand->insert)
2814 {
2815 const char *errmsg = NULL;
ea1562b3 2816
4670103e
CZ		 2817 insn = (*operand->insert) (insn, val, &errmsg);
2818 if (errmsg)
2819 as_warn_where (file, line, "%s", errmsg);
2820 }
2821 else
2822 {
2823 if (operand->flags & ARC_OPERAND_TRUNCATE)
2824 {
2825 if (operand->flags & ARC_OPERAND_ALIGNED32)
2826 val >>= 2;
2827 if (operand->flags & ARC_OPERAND_ALIGNED16)
2828 val >>= 1;
886a2506 2829 }
4670103e
CZ		 2830 insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift);
2831 }
2832 return insn;
2833}
ea1562b3 2834
4670103e
CZ		 2835/* Apply a fixup to the object code. At this point all symbol values
2836 should be fully resolved, and we attempt to completely resolve the
2837 reloc. If we can not do that, we determine the correct reloc code
2838 and put it back in the fixup. To indicate that a fixup has been
2839 eliminated, set fixP->fx_done. */
ea1562b3 2840
4670103e
CZ		 2841void
2842md_apply_fix (fixS *fixP,
2843 valueT *valP,
2844 segT seg)
2845{
2846 char * const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
2847 valueT value = *valP;
2848 unsigned insn = 0;
2849 symbolS *fx_addsy, *fx_subsy;
2850 offsetT fx_offset;
2851 segT add_symbol_segment = absolute_section;
2852 segT sub_symbol_segment = absolute_section;
2853 const struct arc_operand *operand = NULL;
2854 extended_bfd_reloc_code_real_type reloc;
886a2506 2855
4670103e
CZ		 2856 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2857 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2858 ((int) fixP->fx_r_type < 0) ? "Internal":
2859 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2860 fixP->fx_offset);
886a2506 2861
4670103e
CZ		 2862 fx_addsy = fixP->fx_addsy;
2863 fx_subsy = fixP->fx_subsy;
2864 fx_offset = 0;
886a2506 2865
4670103e
CZ		 2866 if (fx_addsy)
2867 {
2868 add_symbol_segment = S_GET_SEGMENT (fx_addsy);
886a2506
NC		 2869 }
2870
4670103e
CZ		 2871 if (fx_subsy
2872 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF
2873 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF_S9
2874 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_GD_LD)
2875 {
2876 resolve_symbol_value (fx_subsy);
2877 sub_symbol_segment = S_GET_SEGMENT (fx_subsy);
886a2506 2878
4670103e
CZ		 2879 if (sub_symbol_segment == absolute_section)
2880 {
2881 /* The symbol is really a constant. */
2882 fx_offset -= S_GET_VALUE (fx_subsy);
2883 fx_subsy = NULL;
2884 }
2885 else
2886 {
2887 as_bad_where (fixP->fx_file, fixP->fx_line,
2888 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2889 fx_addsy ? S_GET_NAME (fx_addsy) : "0",
2890 segment_name (add_symbol_segment),
2891 S_GET_NAME (fx_subsy),
2892 segment_name (sub_symbol_segment));
2893 return;
2894 }
2895 }
886a2506 2896
4670103e
CZ		 2897 if (fx_addsy
2898 && !S_IS_WEAK (fx_addsy))
2899 {
2900 if (add_symbol_segment == seg
2901 && fixP->fx_pcrel)
2902 {
2903 value += S_GET_VALUE (fx_addsy);
2904 value -= md_pcrel_from_section (fixP, seg);
2905 fx_addsy = NULL;
2906 fixP->fx_pcrel = FALSE;
2907 }
2908 else if (add_symbol_segment == absolute_section)
2909 {
2910 value = fixP->fx_offset;
2911 fx_offset += S_GET_VALUE (fixP->fx_addsy);
2912 fx_addsy = NULL;
2913 fixP->fx_pcrel = FALSE;
2914 }
2915 }
886a2506 2916
4670103e
CZ		 2917 if (!fx_addsy)
2918 fixP->fx_done = TRUE;
886a2506 2919
4670103e 2920 if (fixP->fx_pcrel)
886a2506 2921 {
4670103e
CZ		 2922 if (fx_addsy
2923 && ((S_IS_DEFINED (fx_addsy)
2924 && S_GET_SEGMENT (fx_addsy) != seg)
2925 || S_IS_WEAK (fx_addsy)))
2926 value += md_pcrel_from_section (fixP, seg);
886a2506 2927
4670103e
CZ		 2928 switch (fixP->fx_r_type)
2929 {
2930 case BFD_RELOC_ARC_32_ME:
2931 /* This is a pc-relative value in a LIMM. Adjust it to the
2932 address of the instruction not to the address of the
33eaf5de 2933 LIMM. Note: it is not any longer valid this affirmation as
4670103e
CZ		 2934 the linker consider ARC_PC32 a fixup to entire 64 bit
2935 insn. */
2936 fixP->fx_offset += fixP->fx_frag->fr_address;
2937 /* Fall through. */
2938 case BFD_RELOC_32:
2939 fixP->fx_r_type = BFD_RELOC_ARC_PC32;
2940 /* Fall through. */
2941 case BFD_RELOC_ARC_PC32:
2942 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
886a2506
NC		 2943 break;
2944 default:
4670103e 2945 if ((int) fixP->fx_r_type < 0)
6e3f3473 2946 as_bad_where (fixP->fx_file, fixP->fx_line,
2947 _("PC relative relocation not allowed for (internal)"
2948 " type %d"),
2949 fixP->fx_r_type);
886a2506 2950 break;
ea1562b3
NC		 2951 }
2952 }
2953
4670103e
CZ		 2954 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2955 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2956 ((int) fixP->fx_r_type < 0) ? "Internal":
2957 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2958 fixP->fx_offset);
886a2506 2959
886a2506 2960
4670103e
CZ		 2961 /* Now check for TLS relocations. */
2962 reloc = fixP->fx_r_type;
2963 switch (reloc)
886a2506 2964 {
4670103e
CZ		 2965 case BFD_RELOC_ARC_TLS_DTPOFF:
2966 case BFD_RELOC_ARC_TLS_LE_32:
2967 if (fixP->fx_done)
2968 break;
2969 /* Fall through. */
2970 case BFD_RELOC_ARC_TLS_GD_GOT:
2971 case BFD_RELOC_ARC_TLS_IE_GOT:
2972 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2973 break;
886a2506 2974
4670103e
CZ		 2975 case BFD_RELOC_ARC_TLS_GD_LD:
2976 gas_assert (!fixP->fx_offset);
2977 if (fixP->fx_subsy)
2978 fixP->fx_offset
2979 = (S_GET_VALUE (fixP->fx_subsy)
2980 - fixP->fx_frag->fr_address- fixP->fx_where);
2981 fixP->fx_subsy = NULL;
2982 /* Fall through. */
2983 case BFD_RELOC_ARC_TLS_GD_CALL:
2984 /* These two relocs are there just to allow ld to change the tls
2985 model for this symbol, by patching the code. The offset -
2986 and scale, if any - will be installed by the linker. */
2987 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2988 break;
886a2506 2989
4670103e
CZ		 2990 case BFD_RELOC_ARC_TLS_LE_S9:
2991 case BFD_RELOC_ARC_TLS_DTPOFF_S9:
2992 as_bad (_("TLS_*_S9 relocs are not supported yet"));
2993 break;
2994
2995 default:
2996 break;
886a2506
NC		 2997 }
2998
4670103e 2999 if (!fixP->fx_done)
886a2506 3000 {
4670103e 3001 return;
886a2506 3002 }
886a2506 3003
33eaf5de 3004 /* Adjust the value if we have a constant. */
4670103e 3005 value += fx_offset;
886a2506 3006
4670103e
CZ		 3007 /* For hosts with longs bigger than 32-bits make sure that the top
3008 bits of a 32-bit negative value read in by the parser are set,
3009 so that the correct comparisons are made. */
3010 if (value & 0x80000000)
69c9e028 3011 value |= (-1UL << 31);
886a2506 3012
4670103e
CZ		 3013 reloc = fixP->fx_r_type;
3014 switch (reloc)
3015 {
3016 case BFD_RELOC_8:
3017 case BFD_RELOC_16:
3018 case BFD_RELOC_24:
3019 case BFD_RELOC_32:
3020 case BFD_RELOC_64:
3021 case BFD_RELOC_ARC_32_PCREL:
3022 md_number_to_chars (fixpos, value, fixP->fx_size);
3023 return;
886a2506 3024
4670103e
CZ		 3025 case BFD_RELOC_ARC_GOTPC32:
3026 /* I cannot fix an GOTPC relocation because I need to relax it
3027 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
3028 as_bad (_("Unsupported operation on reloc"));
3029 return;
886a2506 3030
4670103e
CZ		 3031 case BFD_RELOC_ARC_TLS_DTPOFF:
3032 case BFD_RELOC_ARC_TLS_LE_32:
3033 gas_assert (!fixP->fx_addsy);
3034 gas_assert (!fixP->fx_subsy);
1a0670f3 3035 /* Fall through. */
886a2506 3036
4670103e
CZ		 3037 case BFD_RELOC_ARC_GOTOFF:
3038 case BFD_RELOC_ARC_32_ME:
3039 case BFD_RELOC_ARC_PC32:
3040 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
3041 return;
886a2506 3042
4670103e
CZ		 3043 case BFD_RELOC_ARC_PLT32:
3044 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
3045 return;
886a2506 3046
4670103e
CZ		 3047 case BFD_RELOC_ARC_S25H_PCREL_PLT:
3048 reloc = BFD_RELOC_ARC_S25W_PCREL;
3049 goto solve_plt;
886a2506 3050
4670103e
CZ		 3051 case BFD_RELOC_ARC_S21H_PCREL_PLT:
3052 reloc = BFD_RELOC_ARC_S21H_PCREL;
3053 goto solve_plt;
886a2506 3054
4670103e
CZ		 3055 case BFD_RELOC_ARC_S25W_PCREL_PLT:
3056 reloc = BFD_RELOC_ARC_S25W_PCREL;
3057 goto solve_plt;
886a2506 3058
4670103e
CZ		 3059 case BFD_RELOC_ARC_S21W_PCREL_PLT:
3060 reloc = BFD_RELOC_ARC_S21W_PCREL;
1a0670f3 3061 /* Fall through. */
886a2506 3062
4670103e
CZ		 3063 case BFD_RELOC_ARC_S25W_PCREL:
3064 case BFD_RELOC_ARC_S21W_PCREL:
3065 case BFD_RELOC_ARC_S21H_PCREL:
3066 case BFD_RELOC_ARC_S25H_PCREL:
3067 case BFD_RELOC_ARC_S13_PCREL:
3068 solve_plt:
3069 operand = find_operand_for_reloc (reloc);
3070 gas_assert (operand);
886a2506
NC		 3071 break;
3072
3073 default:
4670103e
CZ		 3074 {
3075 if ((int) fixP->fx_r_type >= 0)
3076 as_fatal (_("unhandled relocation type %s"),
3077 bfd_get_reloc_code_name (fixP->fx_r_type));
886a2506 3078
4670103e
CZ		 3079 /* The rest of these fixups needs to be completely resolved as
3080 constants. */
3081 if (fixP->fx_addsy != 0
3082 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section)
3083 as_bad_where (fixP->fx_file, fixP->fx_line,
3084 _("non-absolute expression in constant field"));
886a2506 3085
4670103e
CZ		 3086 gas_assert (-(int) fixP->fx_r_type < (int) arc_num_operands);
3087 operand = &arc_operands[-(int) fixP->fx_r_type];
3088 break;
3089 }
3090 }
886a2506 3091
4670103e 3092 if (target_big_endian)
886a2506 3093 {
4670103e 3094 switch (fixP->fx_size)
886a2506 3095 {
4670103e
CZ		 3096 case 4:
3097 insn = bfd_getb32 (fixpos);
3098 break;
3099 case 2:
3100 insn = bfd_getb16 (fixpos);
3101 break;
3102 default:
3103 as_bad_where (fixP->fx_file, fixP->fx_line,
3104 _("unknown fixup size"));
3105 }
3106 }
3107 else
3108 {
3109 insn = 0;
3110 switch (fixP->fx_size)
3111 {
3112 case 4:
3113 insn = bfd_getl16 (fixpos) << 16 | bfd_getl16 (fixpos + 2);
3114 break;
3115 case 2:
3116 insn = bfd_getl16 (fixpos);
3117 break;
3118 default:
3119 as_bad_where (fixP->fx_file, fixP->fx_line,
3120 _("unknown fixup size"));
886a2506
NC		 3121 }
3122 }
886a2506 3123
4670103e
CZ		 3124 insn = insert_operand (insn, operand, (offsetT) value,
3125 fixP->fx_file, fixP->fx_line);
886a2506 3126
4670103e
CZ		 3127 md_number_to_chars_midend (fixpos, insn, fixP->fx_size);
3128}
886a2506 3129
4670103e 3130/* Prepare machine-dependent frags for relaxation.
886a2506 3131
4670103e
CZ		 3132 Called just before relaxation starts. Any symbol that is now undefined
3133 will not become defined.
886a2506 3134
4670103e 3135 Return the correct fr_subtype in the frag.
886a2506 3136
4670103e
CZ		 3137 Return the initial "guess for fr_var" to caller. The guess for fr_var
3138 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3139 or fr_var contributes to our returned value.
886a2506 3140
4670103e
CZ		 3141 Although it may not be explicit in the frag, pretend
3142 fr_var starts with a value. */
886a2506 3143
4670103e
CZ		 3144int
3145md_estimate_size_before_relax (fragS *fragP,
3146 segT segment)
3147{
3148 int growth;
3149
3150 /* If the symbol is not located within the same section AND it's not
3151 an absolute section, use the maximum. OR if the symbol is a
3152 constant AND the insn is by nature not pc-rel, use the maximum.
3153 OR if the symbol is being equated against another symbol, use the
3154 maximum. OR if the symbol is weak use the maximum. */
3155 if ((S_GET_SEGMENT (fragP->fr_symbol) != segment
3156 && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section)
3157 || (symbol_constant_p (fragP->fr_symbol)
3158 && !fragP->tc_frag_data.pcrel)
3159 || symbol_equated_p (fragP->fr_symbol)
3160 || S_IS_WEAK (fragP->fr_symbol))
3161 {
3162 while (md_relax_table[fragP->fr_subtype].rlx_more != ARC_RLX_NONE)
3163 ++fragP->fr_subtype;
3164 }
886a2506 3165
4670103e
CZ		 3166 growth = md_relax_table[fragP->fr_subtype].rlx_length;
3167 fragP->fr_var = growth;
886a2506 3168
4670103e
CZ		 3169 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3170 fragP->fr_file, fragP->fr_line, growth);
886a2506 3171
4670103e
CZ		 3172 return growth;
3173}
886a2506 3174
4670103e
CZ		 3175/* Translate internal representation of relocation info to BFD target
3176 format. */
886a2506 3177
4670103e
CZ		 3178arelent *
3179tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
3180 fixS *fixP)
3181{
3182 arelent *reloc;
3183 bfd_reloc_code_real_type code;
886a2506 3184
add39d23
TS		 3185 reloc = XNEW (arelent);
3186 reloc->sym_ptr_ptr = XNEW (asymbol *);
4670103e
CZ		 3187 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
3188 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
886a2506 3189
4670103e
CZ		 3190 /* Make sure none of our internal relocations make it this far.
3191 They'd better have been fully resolved by this point. */
3192 gas_assert ((int) fixP->fx_r_type > 0);
886a2506 3193
4670103e 3194 code = fixP->fx_r_type;
886a2506 3195
4670103e
CZ		 3196 /* if we have something like add gp, pcl,
3197 _GLOBAL_OFFSET_TABLE_@gotpc. */
3198 if (code == BFD_RELOC_ARC_GOTPC32
3199 && GOT_symbol
3200 && fixP->fx_addsy == GOT_symbol)
3201 code = BFD_RELOC_ARC_GOTPC;
886a2506 3202
4670103e
CZ		 3203 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3204 if (reloc->howto == NULL)
886a2506 3205 {
4670103e
CZ		 3206 as_bad_where (fixP->fx_file, fixP->fx_line,
3207 _("cannot represent `%s' relocation in object file"),
3208 bfd_get_reloc_code_name (code));
3209 return NULL;
3210 }
886a2506 3211
4670103e
CZ		 3212 if (!fixP->fx_pcrel != !reloc->howto->pc_relative)
3213 as_fatal (_("internal error? cannot generate `%s' relocation"),
3214 bfd_get_reloc_code_name (code));
886a2506 3215
4670103e 3216 gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
886a2506 3217
05bbf016 3218 reloc->addend = fixP->fx_offset;
4670103e
CZ		 3219
3220 return reloc;
886a2506
NC		 3221}
3222
4670103e
CZ		 3223/* Perform post-processing of machine-dependent frags after relaxation.
3224 Called after relaxation is finished.
3225 In: Address of frag.
3226 fr_type == rs_machine_dependent.
3227 fr_subtype is what the address relaxed to.
886a2506 3228
4670103e
CZ		 3229 Out: Any fixS:s and constants are set up. */
3230
3231void
3232md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
3233 segT segment ATTRIBUTE_UNUSED,
3234 fragS *fragP)
886a2506 3235{
4670103e
CZ		 3236 const relax_typeS *table_entry;
3237 char *dest;
3238 const struct arc_opcode *opcode;
3239 struct arc_insn insn;
3240 int size, fix;
3241 struct arc_relax_type *relax_arg = &fragP->tc_frag_data;
886a2506 3242
4670103e
CZ		 3243 fix = (fragP->fr_fix < 0 ? 0 : fragP->fr_fix);
3244 dest = fragP->fr_literal + fix;
3245 table_entry = TC_GENERIC_RELAX_TABLE + fragP->fr_subtype;
886a2506 3246
9e32d9ae
AB		 3247 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
3248 "var: %"BFD_VMA_FMT"d\n",
4670103e
CZ		 3249 fragP->fr_file, fragP->fr_line,
3250 fragP->fr_subtype, fix, fragP->fr_var);
886a2506 3251
4670103e
CZ		 3252 if (fragP->fr_subtype <= 0
3253 && fragP->fr_subtype >= arc_num_relax_opcodes)
3254 as_fatal (_("no relaxation found for this instruction."));
886a2506 3255
4670103e 3256 opcode = &arc_relax_opcodes[fragP->fr_subtype];
886a2506 3257
4670103e
CZ		 3258 assemble_insn (opcode, relax_arg->tok, relax_arg->ntok, relax_arg->pflags,
3259 relax_arg->nflg, &insn);
886a2506 3260
4670103e 3261 apply_fixups (&insn, fragP, fix);
886a2506 3262
91fdca6f 3263 size = insn.len + (insn.has_limm ? 4 : 0);
4670103e
CZ		 3264 gas_assert (table_entry->rlx_length == size);
3265 emit_insn0 (&insn, dest, TRUE);
886a2506 3266
4670103e
CZ		 3267 fragP->fr_fix += table_entry->rlx_length;
3268 fragP->fr_var = 0;
886a2506
NC		 3269}
3270
4670103e
CZ		 3271/* We have no need to default values of symbols. We could catch
3272 register names here, but that is handled by inserting them all in
3273 the symbol table to begin with. */
886a2506 3274
4670103e
CZ		 3275symbolS *
3276md_undefined_symbol (char *name)
886a2506 3277{
4670103e
CZ		 3278 /* The arc abi demands that a GOT[0] should be referencible as
3279 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3280 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3281 if (((*name == '_')
3282 && (*(name+1) == 'G')
7ef0acc1 3283 && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)))
886a2506 3284 {
4670103e
CZ		 3285 if (!GOT_symbol)
3286 {
3287 if (symbol_find (name))
3288 as_bad ("GOT already in symbol table");
3289
3290 GOT_symbol = symbol_new (GLOBAL_OFFSET_TABLE_NAME, undefined_section,
3291 (valueT) 0, &zero_address_frag);
3292 };
3293 return GOT_symbol;
886a2506 3294 }
4670103e 3295 return NULL;
886a2506
NC		 3296}
3297
4670103e
CZ		 3298/* Turn a string in input_line_pointer into a floating point constant
3299 of type type, and store the appropriate bytes in *litP. The number
3300 of LITTLENUMS emitted is stored in *sizeP. An error message is
3301 returned, or NULL on OK. */
886a2506 3302
6d4af3c2 3303const char *
4670103e 3304md_atof (int type, char *litP, int *sizeP)
886a2506 3305{
4670103e
CZ		 3306 return ieee_md_atof (type, litP, sizeP, target_big_endian);
3307}
886a2506 3308
4670103e
CZ		 3309/* Called for any expression that can not be recognized. When the
3310 function is called, `input_line_pointer' will point to the start of
3311 the expression. */
886a2506 3312
4670103e
CZ		 3313void
3314md_operand (expressionS *expressionP ATTRIBUTE_UNUSED)
3315{
3316 char *p = input_line_pointer;
3317 if (*p == '@')
886a2506 3318 {
4670103e
CZ		 3319 input_line_pointer++;
3320 expressionP->X_op = O_symbol;
3321 expression (expressionP);
3322 }
3323}
886a2506 3324
4670103e
CZ		 3325/* This function is called from the function 'expression', it attempts
3326 to parse special names (in our case register names). It fills in
3327 the expression with the identified register. It returns TRUE if
3328 it is a register and FALSE otherwise. */
886a2506 3329
4670103e
CZ		 3330bfd_boolean
3331arc_parse_name (const char *name,
3332 struct expressionS *e)
3333{
3334 struct symbol *sym;
886a2506 3335
4670103e
CZ		 3336 if (!assembling_insn)
3337 return FALSE;
886a2506 3338
08ec958f 3339 if (e->X_op == O_symbol)
4670103e 3340 return FALSE;
886a2506 3341
4670103e
CZ		 3342 sym = hash_find (arc_reg_hash, name);
3343 if (sym)
3344 {
3345 e->X_op = O_register;
3346 e->X_add_number = S_GET_VALUE (sym);
3347 return TRUE;
3348 }
db18dbab
GM		 3349
3350 sym = hash_find (arc_addrtype_hash, name);
3351 if (sym)
3352 {
3353 e->X_op = O_addrtype;
3354 e->X_add_number = S_GET_VALUE (sym);
3355 return TRUE;
3356 }
3357
4670103e
CZ		 3358 return FALSE;
3359}
886a2506 3360
4670103e
CZ		 3361/* md_parse_option
3362 Invocation line includes a switch not recognized by the base assembler.
3363 See if it's a processor-specific option.
886a2506 3364
4670103e 3365 New options (supported) are:
886a2506 3366
4670103e
CZ		 3367 -mcpu=<cpu name> Assemble for selected processor
3368 -EB/-mbig-endian Big-endian
3369 -EL/-mlittle-endian Little-endian
3370 -mrelax Enable relaxation
886a2506 3371
4670103e 3372 The following CPU names are recognized:
ce440d63 3373 arc600, arc700, arcem, archs, nps400. */
886a2506 3374
4670103e 3375int
17b9d67d 3376md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
4670103e 3377{
4670103e
CZ		 3378 switch (c)
3379 {
3380 case OPTION_ARC600:
3381 case OPTION_ARC601:
3382 return md_parse_option (OPTION_MCPU, "arc600");
886a2506 3383
4670103e
CZ		 3384 case OPTION_ARC700:
3385 return md_parse_option (OPTION_MCPU, "arc700");
886a2506 3386
4670103e
CZ		 3387 case OPTION_ARCEM:
3388 return md_parse_option (OPTION_MCPU, "arcem");
886a2506 3389
4670103e
CZ		 3390 case OPTION_ARCHS:
3391 return md_parse_option (OPTION_MCPU, "archs");
886a2506 3392
4670103e
CZ		 3393 case OPTION_MCPU:
3394 {
bb65a718 3395 arc_select_cpu (arg, MACH_SELECTION_FROM_COMMAND_LINE);
4670103e
CZ		 3396 break;
3397 }
886a2506 3398
4670103e
CZ		 3399 case OPTION_EB:
3400 arc_target_format = "elf32-bigarc";
3401 byte_order = BIG_ENDIAN;
3402 break;
886a2506 3403
4670103e
CZ		 3404 case OPTION_EL:
3405 arc_target_format = "elf32-littlearc";
3406 byte_order = LITTLE_ENDIAN;
3407 break;
886a2506 3408
4670103e 3409 case OPTION_CD:
53a346d8
CZ		 3410 selected_cpu.features |= CD;
3411 cl_features |= CD;
bb050a69 3412 arc_check_feature ();
4670103e 3413 break;
886a2506 3414
4670103e
CZ		 3415 case OPTION_RELAX:
3416 relaxation_state = 1;
3417 break;
886a2506 3418
bdd582db 3419 case OPTION_NPS400:
53a346d8
CZ		 3420 selected_cpu.features |= NPS400;
3421 cl_features |= NPS400;
bb050a69 3422 arc_check_feature ();
ce440d63 3423 break;
bdd582db 3424
ce440d63 3425 case OPTION_SPFP:
53a346d8
CZ		 3426 selected_cpu.features |= SPX;
3427 cl_features |= SPX;
bb050a69 3428 arc_check_feature ();
ce440d63
GM		 3429 break;
3430
3431 case OPTION_DPFP:
53a346d8
CZ		 3432 selected_cpu.features |= DPX;
3433 cl_features |= DPX;
bb050a69 3434 arc_check_feature ();
ce440d63
GM		 3435 break;
3436
3437 case OPTION_FPUDA:
53a346d8
CZ		 3438 selected_cpu.features |= DPA;
3439 cl_features |= DPA;
bb050a69 3440 arc_check_feature ();
ce440d63
GM		 3441 break;
3442
3443 /* Dummy options are accepted but have no effect. */
4670103e
CZ		 3444 case OPTION_USER_MODE:
3445 case OPTION_LD_EXT_MASK:
3446 case OPTION_SWAP:
3447 case OPTION_NORM:
3448 case OPTION_BARREL_SHIFT:
3449 case OPTION_MIN_MAX:
3450 case OPTION_NO_MPY:
3451 case OPTION_EA:
3452 case OPTION_MUL64:
3453 case OPTION_SIMD:
4670103e
CZ		 3454 case OPTION_XMAC_D16:
3455 case OPTION_XMAC_24:
3456 case OPTION_DSP_PACKA:
3457 case OPTION_CRC:
3458 case OPTION_DVBF:
3459 case OPTION_TELEPHONY:
3460 case OPTION_XYMEMORY:
3461 case OPTION_LOCK:
3462 case OPTION_SWAPE:
3463 case OPTION_RTSC:
8ddf6b2a
CZ		 3464 break;
3465
4670103e
CZ		 3466 default:
3467 return 0;
3468 }
886a2506 3469
4670103e
CZ		 3470 return 1;
3471}
886a2506 3472
a9752fdf
CZ		 3473/* Display the list of cpu names for use in the help text. */
3474
3475static void
3476arc_show_cpu_list (FILE *stream)
3477{
3478 int i, offset;
731f7c4e 3479 static const char *space_buf = " ";
a9752fdf 3480
731f7c4e
MR		 3481 fprintf (stream, "%s", space_buf);
3482 offset = strlen (space_buf);
a9752fdf
CZ		 3483 for (i = 0; cpu_types[i].name != NULL; ++i)
3484 {
3485 bfd_boolean last = (cpu_types[i + 1].name == NULL);
3486
3487 /* If displaying the new cpu name string, and the ', ' (for all
3488 but the last one) will take us past a target width of 80
3489 characters, then it's time for a new line. */
3490 if (offset + strlen (cpu_types[i].name) + (last ? 0 : 2) > 80)
3491 {
731f7c4e
MR		 3492 fprintf (stream, "\n%s", space_buf);
3493 offset = strlen (space_buf);
a9752fdf
CZ		 3494 }
3495
3496 fprintf (stream, "%s%s", cpu_types[i].name, (last ? "\n" : ", "));
3497 offset += strlen (cpu_types [i].name) + (last ? 0 : 2);
3498 }
3499}
3500
4670103e
CZ		 3501void
3502md_show_usage (FILE *stream)
3503{
3504 fprintf (stream, _("ARC-specific assembler options:\n"));
886a2506 3505
a9752fdf
CZ		 3506 fprintf (stream, " -mcpu=<cpu name>\t (default: %s), assemble for"
3507 " CPU <cpu name>, one of:\n", TARGET_WITH_CPU);
3508 arc_show_cpu_list (stream);
3509 fprintf (stream, "\n");
bdd582db
GM		 3510 fprintf (stream, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
3511 fprintf (stream, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
3512 fprintf (stream, " -mEM\t\t\t same as -mcpu=arcem\n");
3513 fprintf (stream, " -mHS\t\t\t same as -mcpu=archs\n");
3514
3515 fprintf (stream, " -mnps400\t\t enable NPS-400 extended instructions\n");
a9752fdf
CZ		 3516 fprintf (stream, " -mspfp\t\t enable single-precision floating point"
3517 " instructions\n");
3518 fprintf (stream, " -mdpfp\t\t enable double-precision floating point"
3519 " instructions\n");
bdd582db
GM		 3520 fprintf (stream, " -mfpuda\t\t enable double-precision assist floating "
3521 "point\n\t\t\t instructions for ARC EM\n");
3522
4670103e
CZ		 3523 fprintf (stream,
3524 " -mcode-density\t enable code density option for ARC EM\n");
3525
3526 fprintf (stream, _("\
3527 -EB assemble code for a big-endian cpu\n"));
3528 fprintf (stream, _("\
3529 -EL assemble code for a little-endian cpu\n"));
3530 fprintf (stream, _("\
bdd582db
GM		 3531 -mrelax enable relaxation\n"));
3532
3533 fprintf (stream, _("The following ARC-specific assembler options are "
3534 "deprecated and are accepted\nfor compatibility only:\n"));
3535
3536 fprintf (stream, _(" -mEA\n"
3537 " -mbarrel-shifter\n"
3538 " -mbarrel_shifter\n"
3539 " -mcrc\n"
3540 " -mdsp-packa\n"
3541 " -mdsp_packa\n"
3542 " -mdvbf\n"
3543 " -mld-extension-reg-mask\n"
3544 " -mlock\n"
3545 " -mmac-24\n"
3546 " -mmac-d16\n"
3547 " -mmac_24\n"
3548 " -mmac_d16\n"
3549 " -mmin-max\n"
3550 " -mmin_max\n"
3551 " -mmul64\n"
3552 " -mno-mpy\n"
3553 " -mnorm\n"
3554 " -mrtsc\n"
3555 " -msimd\n"
3556 " -mswap\n"
3557 " -mswape\n"
3558 " -mtelephony\n"
3559 " -muser-mode-only\n"
3560 " -mxy\n"));
886a2506
NC		 3561}
3562
3563/* Find the proper relocation for the given opcode. */
3564
3565static extended_bfd_reloc_code_real_type
3566find_reloc (const char *name,
3567 const char *opcodename,
3568 const struct arc_flags *pflags,
3569 int nflg,
3570 extended_bfd_reloc_code_real_type reloc)
3571{
3572 unsigned int i;
3573 int j;
24b368f8 3574 bfd_boolean found_flag, tmp;
886a2506
NC		 3575 extended_bfd_reloc_code_real_type ret = BFD_RELOC_UNUSED;
3576
3577 for (i = 0; i < arc_num_equiv_tab; i++)
3578 {
3579 const struct arc_reloc_equiv_tab *r = &arc_reloc_equiv[i];
3580
3581 /* Find the entry. */
3582 if (strcmp (name, r->name))
3583 continue;
3584 if (r->mnemonic && (strcmp (r->mnemonic, opcodename)))
3585 continue;
24b368f8 3586 if (r->flags[0])
886a2506
NC		 3587 {
3588 if (!nflg)
3589 continue;
3590 found_flag = FALSE;
24b368f8
CZ		 3591 unsigned * psflg = (unsigned *)r->flags;
3592 do
3593 {
3594 tmp = FALSE;
3595 for (j = 0; j < nflg; j++)
3596 if (!strcmp (pflags[j].name,
3597 arc_flag_operands[*psflg].name))
3598 {
3599 tmp = TRUE;
3600 break;
3601 }
3602 if (!tmp)
3603 {
3604 found_flag = FALSE;
3605 break;
3606 }
3607 else
3608 {
3609 found_flag = TRUE;
3610 }
3611 ++ psflg;
3612 } while (*psflg);
3613
886a2506
NC		 3614 if (!found_flag)
3615 continue;
3616 }
3617
3618 if (reloc != r->oldreloc)
3619 continue;
3620 /* Found it. */
3621 ret = r->newreloc;
3622 break;
3623 }
3624
3625 if (ret == BFD_RELOC_UNUSED)
3626 as_bad (_("Unable to find %s relocation for instruction %s"),
3627 name, opcodename);
3628 return ret;
3629}
3630
4670103e
CZ		 3631/* All the symbol types that are allowed to be used for
3632 relaxation. */
3633
3634static bfd_boolean
3635may_relax_expr (expressionS tok)
3636{
3637 /* Check if we have unrelaxable relocs. */
3638 switch (tok.X_md)
3639 {
3640 default:
3641 break;
3642 case O_plt:
3643 return FALSE;
3644 }
3645
3646 switch (tok.X_op)
3647 {
3648 case O_symbol:
3649 case O_multiply:
3650 case O_divide:
3651 case O_modulus:
3652 case O_add:
3653 case O_subtract:
3654 break;
3655
3656 default:
3657 return FALSE;
3658 }
3659 return TRUE;
3660}
3661
3662/* Checks if flags are in line with relaxable insn. */
3663
3664static bfd_boolean
3665relaxable_flag (const struct arc_relaxable_ins *ins,
3666 const struct arc_flags *pflags,
3667 int nflgs)
3668{
3669 unsigned flag_class,
3670 flag,
3671 flag_class_idx = 0,
3672 flag_idx = 0;
3673
3674 const struct arc_flag_operand *flag_opand;
3675 int i, counttrue = 0;
3676
3677 /* Iterate through flags classes. */
3678 while ((flag_class = ins->flag_classes[flag_class_idx]) != 0)
3679 {
3680 /* Iterate through flags in flag class. */
3681 while ((flag = arc_flag_classes[flag_class].flags[flag_idx])
3682 != 0)
3683 {
3684 flag_opand = &arc_flag_operands[flag];
3685 /* Iterate through flags in ins to compare. */
3686 for (i = 0; i < nflgs; ++i)
3687 {
3688 if (strcmp (flag_opand->name, pflags[i].name) == 0)
3689 ++counttrue;
3690 }
3691
3692 ++flag_idx;
3693 }
3694
3695 ++flag_class_idx;
3696 flag_idx = 0;
3697 }
3698
3699 /* If counttrue == nflgs, then all flags have been found. */
3700 return (counttrue == nflgs ? TRUE : FALSE);
3701}
3702
3703/* Checks if operands are in line with relaxable insn. */
3704
3705static bfd_boolean
3706relaxable_operand (const struct arc_relaxable_ins *ins,
3707 const expressionS *tok,
3708 int ntok)
3709{
3710 const enum rlx_operand_type *operand = &ins->operands[0];
3711 int i = 0;
3712
3713 while (*operand != EMPTY)
3714 {
3715 const expressionS *epr = &tok[i];
3716
3717 if (i != 0 && i >= ntok)
3718 return FALSE;
3719
3720 switch (*operand)
3721 {
3722 case IMMEDIATE:
3723 if (!(epr->X_op == O_multiply
3724 || epr->X_op == O_divide
3725 || epr->X_op == O_modulus
3726 || epr->X_op == O_add
3727 || epr->X_op == O_subtract
3728 || epr->X_op == O_symbol))
3729 return FALSE;
3730 break;
3731
3732 case REGISTER_DUP:
3733 if ((i <= 0)
3734 || (epr->X_add_number != tok[i - 1].X_add_number))
3735 return FALSE;
3736 /* Fall through. */
3737 case REGISTER:
3738 if (epr->X_op != O_register)
3739 return FALSE;
3740 break;
3741
3742 case REGISTER_S:
3743 if (epr->X_op != O_register)
3744 return FALSE;
3745
3746 switch (epr->X_add_number)
3747 {
3748 case 0: case 1: case 2: case 3:
3749 case 12: case 13: case 14: case 15:
3750 break;
3751 default:
3752 return FALSE;
3753 }
3754 break;
3755
3756 case REGISTER_NO_GP:
3757 if ((epr->X_op != O_register)
3758 || (epr->X_add_number == 26)) /* 26 is the gp register. */
3759 return FALSE;
3760 break;
3761
3762 case BRACKET:
3763 if (epr->X_op != O_bracket)
3764 return FALSE;
3765 break;
3766
3767 default:
3768 /* Don't understand, bail out. */
3769 return FALSE;
3770 break;
3771 }
3772
3773 ++i;
3774 operand = &ins->operands[i];
3775 }
3776
3777 return (i == ntok ? TRUE : FALSE);
3778}
3779
3780/* Return TRUE if this OPDCODE is a candidate for relaxation. */
3781
3782static bfd_boolean
3783relax_insn_p (const struct arc_opcode *opcode,
3784 const expressionS *tok,
3785 int ntok,
3786 const struct arc_flags *pflags,
3787 int nflg)
3788{
3789 unsigned i;
3790 bfd_boolean rv = FALSE;
3791
3792 /* Check the relaxation table. */
3793 for (i = 0; i < arc_num_relaxable_ins && relaxation_state; ++i)
3794 {
3795 const struct arc_relaxable_ins *arc_rlx_ins = &arc_relaxable_insns[i];
3796
3797 if ((strcmp (opcode->name, arc_rlx_ins->mnemonic_r) == 0)
3798 && may_relax_expr (tok[arc_rlx_ins->opcheckidx])
3799 && relaxable_operand (arc_rlx_ins, tok, ntok)
3800 && relaxable_flag (arc_rlx_ins, pflags, nflg))
3801 {
3802 rv = TRUE;
3803 frag_now->fr_subtype = arc_relaxable_insns[i].subtype;
3804 memcpy (&frag_now->tc_frag_data.tok, tok,
3805 sizeof (expressionS) * ntok);
3806 memcpy (&frag_now->tc_frag_data.pflags, pflags,
3807 sizeof (struct arc_flags) * nflg);
3808 frag_now->tc_frag_data.nflg = nflg;
3809 frag_now->tc_frag_data.ntok = ntok;
3810 break;
3811 }
3812 }
3813
3814 return rv;
3815}
3816
886a2506
NC		 3817/* Turn an opcode description and a set of arguments into
3818 an instruction and a fixup. */
3819
3820static void
3821assemble_insn (const struct arc_opcode *opcode,
3822 const expressionS *tok,
3823 int ntok,
3824 const struct arc_flags *pflags,
3825 int nflg,
3826 struct arc_insn *insn)
3827{
3828 const expressionS *reloc_exp = NULL;
bdfe53e3 3829 unsigned long long image;
886a2506
NC		 3830 const unsigned char *argidx;
3831 int i;
3832 int tokidx = 0;
3833 unsigned char pcrel = 0;
3834 bfd_boolean needGOTSymbol;
3835 bfd_boolean has_delay_slot = FALSE;
3836 extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
3837
3838 memset (insn, 0, sizeof (*insn));
3839 image = opcode->opcode;
3840
bdfe53e3 3841 pr_debug ("%s:%d: assemble_insn: %s using opcode %llx\n",
886a2506
NC		 3842 frag_now->fr_file, frag_now->fr_line, opcode->name,
3843 opcode->opcode);
3844
3845 /* Handle operands. */
3846 for (argidx = opcode->operands; *argidx; ++argidx)
3847 {
3848 const struct arc_operand *operand = &arc_operands[*argidx];
3849 const expressionS *t = (const expressionS *) 0;
3850
db18dbab 3851 if (ARC_OPERAND_IS_FAKE (operand))
886a2506
NC		 3852 continue;
3853
3854 if (operand->flags & ARC_OPERAND_DUPLICATE)
3855 {
3856 /* Duplicate operand, already inserted. */
3857 tokidx ++;
3858 continue;
3859 }
3860
3861 if (tokidx >= ntok)
3862 {
3863 abort ();
3864 }
3865 else
3866 t = &tok[tokidx++];
3867
3868 /* Regardless if we have a reloc or not mark the instruction
3869 limm if it is the case. */
3870 if (operand->flags & ARC_OPERAND_LIMM)
3871 insn->has_limm = TRUE;
3872
3873 switch (t->X_op)
3874 {
3875 case O_register:
3876 image = insert_operand (image, operand, regno (t->X_add_number),
3877 NULL, 0);
3878 break;
3879
3880 case O_constant:
3881 image = insert_operand (image, operand, t->X_add_number, NULL, 0);
3882 reloc_exp = t;
3883 if (operand->flags & ARC_OPERAND_LIMM)
3884 insn->limm = t->X_add_number;
3885 break;
3886
3887 case O_bracket:
db18dbab
GM		 3888 case O_colon:
3889 case O_addrtype:
3890 /* Ignore brackets, colons, and address types. */
886a2506
NC		 3891 break;
3892
3893 case O_absent:
3894 gas_assert (operand->flags & ARC_OPERAND_IGNORE);
3895 break;
3896
3897 case O_subtract:
3898 /* Maybe register range. */
3899 if ((t->X_add_number == 0)
3900 && contains_register (t->X_add_symbol)
3901 && contains_register (t->X_op_symbol))
3902 {
3903 int regs;
3904
3905 regs = get_register (t->X_add_symbol);
3906 regs <<= 16;
3907 regs |= get_register (t->X_op_symbol);
3908 image = insert_operand (image, operand, regs, NULL, 0);
3909 break;
3910 }
1a0670f3 3911 /* Fall through. */
886a2506
NC		 3912
3913 default:
3914 /* This operand needs a relocation. */
3915 needGOTSymbol = FALSE;
3916
3917 switch (t->X_md)
3918 {
3919 case O_plt:
c810e0b8 3920 if (opcode->insn_class == JUMP)
6e3f3473 3921 as_bad (_("Unable to use @plt relocation for insn %s"),
3922 opcode->name);
886a2506
NC		 3923 needGOTSymbol = TRUE;
3924 reloc = find_reloc ("plt", opcode->name,
3925 pflags, nflg,
3926 operand->default_reloc);
3927 break;
3928
3929 case O_gotoff:
3930 case O_gotpc:
3931 needGOTSymbol = TRUE;
3932 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3933 break;
3934 case O_pcl:
cc07cda6
CZ		 3935 if (operand->flags & ARC_OPERAND_LIMM)
3936 {
3937 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3938 if (arc_opcode_len (opcode) == 2
3939 || opcode->insn_class == JUMP)
6e3f3473 3940 as_bad (_("Unable to use @pcl relocation for insn %s"),
3941 opcode->name);
cc07cda6
CZ		 3942 }
3943 else
3944 {
3945 /* This is a relaxed operand which initially was
3946 limm, choose whatever we have defined in the
3947 opcode as reloc. */
3948 reloc = operand->default_reloc;
3949 }
886a2506
NC		 3950 break;
3951 case O_sda:
3952 reloc = find_reloc ("sda", opcode->name,
3953 pflags, nflg,
3954 operand->default_reloc);
3955 break;
3956 case O_tlsgd:
3957 case O_tlsie:
3958 needGOTSymbol = TRUE;
3959 /* Fall-through. */
3960
3961 case O_tpoff:
3962 case O_dtpoff:
3963 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3964 break;
3965
3966 case O_tpoff9: /*FIXME! Check for the conditionality of
3967 the insn. */
3968 case O_dtpoff9: /*FIXME! Check for the conditionality of
3969 the insn. */
3970 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3971 break;
3972
3973 default:
3974 /* Just consider the default relocation. */
3975 reloc = operand->default_reloc;
3976 break;
3977 }
3978
3979 if (needGOTSymbol && (GOT_symbol == NULL))
3980 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3981
3982 reloc_exp = t;
3983
3984#if 0
3985 if (reloc > 0)
3986 {
3987 /* sanity checks. */
3988 reloc_howto_type *reloc_howto
3989 = bfd_reloc_type_lookup (stdoutput,
3990 (bfd_reloc_code_real_type) reloc);
3991 unsigned reloc_bitsize = reloc_howto->bitsize;
3992 if (reloc_howto->rightshift)
3993 reloc_bitsize -= reloc_howto->rightshift;
3994 if (reloc_bitsize != operand->bits)
3995 {
3996 as_bad (_("invalid relocation %s for field"),
3997 bfd_get_reloc_code_name (reloc));
3998 return;
3999 }
4000 }
4001#endif
4002 if (insn->nfixups >= MAX_INSN_FIXUPS)
4003 as_fatal (_("too many fixups"));
4004
4005 struct arc_fixup *fixup;
4006 fixup = &insn->fixups[insn->nfixups++];
4007 fixup->exp = *t;
4008 fixup->reloc = reloc;
cc07cda6
CZ		 4009 if ((int) reloc < 0)
4010 pcrel = (operand->flags & ARC_OPERAND_PCREL) ? 1 : 0;
4011 else
4012 {
4013 reloc_howto_type *reloc_howto =
4014 bfd_reloc_type_lookup (stdoutput,
4015 (bfd_reloc_code_real_type) fixup->reloc);
4016 pcrel = reloc_howto->pc_relative;
4017 }
886a2506
NC		 4018 fixup->pcrel = pcrel;
4019 fixup->islong = (operand->flags & ARC_OPERAND_LIMM) ?
4020 TRUE : FALSE;
4021 break;
4022 }
4023 }
4024
4025 /* Handle flags. */
4026 for (i = 0; i < nflg; i++)
4027 {
f36e33da 4028 const struct arc_flag_operand *flg_operand = pflags[i].flgp;
886a2506
NC		 4029
4030 /* Check if the instruction has a delay slot. */
4031 if (!strcmp (flg_operand->name, "d"))
4032 has_delay_slot = TRUE;
4033
2c52e2e8
RZ		 4034 /* There is an exceptional case when we cannot insert a flag just as
4035 it is. On ARCv2 the '.t' and '.nt' flags must be handled in
4036 relation with the relative address. Unfortunately, some of the
4037 ARC700 extensions (NPS400) also have a '.nt' flag that should be
4038 handled in the normal way.
4039
4040 Flag operands don't have an architecture field, so we can't
4041 directly validate that FLAG_OPERAND is valid for the current
4042 architecture, what we do instead is just validate that we're
4043 assembling for an ARCv2 architecture. */
4044 if ((selected_cpu.flags & ARC_OPCODE_ARCV2)
4045 && (!strcmp (flg_operand->name, "t")
4046 || !strcmp (flg_operand->name, "nt")))
886a2506
NC		 4047 {
4048 unsigned bitYoperand = 0;
4049 /* FIXME! move selection bbit/brcc in arc-opc.c. */
4050 if (!strcmp (flg_operand->name, "t"))
4051 if (!strcmp (opcode->name, "bbit0")
4052 || !strcmp (opcode->name, "bbit1"))
4053 bitYoperand = arc_NToperand;
4054 else
4055 bitYoperand = arc_Toperand;
4056 else
4057 if (!strcmp (opcode->name, "bbit0")
4058 || !strcmp (opcode->name, "bbit1"))
4059 bitYoperand = arc_Toperand;
4060 else
4061 bitYoperand = arc_NToperand;
4062
4063 gas_assert (reloc_exp != NULL);
4064 if (reloc_exp->X_op == O_constant)
4065 {
4066 /* Check if we have a constant and solved it
4067 immediately. */
4068 offsetT val = reloc_exp->X_add_number;
4069 image |= insert_operand (image, &arc_operands[bitYoperand],
4070 val, NULL, 0);
4071 }
4072 else
4073 {
4074 struct arc_fixup *fixup;
4075
4076 if (insn->nfixups >= MAX_INSN_FIXUPS)
4077 as_fatal (_("too many fixups"));
4078
4079 fixup = &insn->fixups[insn->nfixups++];
4080 fixup->exp = *reloc_exp;
4081 fixup->reloc = -bitYoperand;
4082 fixup->pcrel = pcrel;
4083 fixup->islong = FALSE;
4084 }
4085 }
4086 else
4087 image |= (flg_operand->code & ((1 << flg_operand->bits) - 1))
4088 << flg_operand->shift;
4089 }
4090
4670103e
CZ		 4091 insn->relax = relax_insn_p (opcode, tok, ntok, pflags, nflg);
4092
91fdca6f 4093 /* Instruction length. */
06fe285f 4094 insn->len = arc_opcode_len (opcode);
886a2506
NC		 4095
4096 insn->insn = image;
4097
4098 /* Update last insn status. */
4099 arc_last_insns[1] = arc_last_insns[0];
4100 arc_last_insns[0].opcode = opcode;
4101 arc_last_insns[0].has_limm = insn->has_limm;
4102 arc_last_insns[0].has_delay_slot = has_delay_slot;
4103
4104 /* Check if the current instruction is legally used. */
4105 if (arc_last_insns[1].has_delay_slot
4106 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
6e3f3473 4107 as_bad (_("Insn %s has a jump/branch instruction %s in its delay slot."),
4108 arc_last_insns[1].opcode->name,
4109 arc_last_insns[0].opcode->name);
886a2506
NC		 4110}
4111
886a2506
NC		 4112void
4113arc_handle_align (fragS* fragP)
4114{
4115 if ((fragP)->fr_type == rs_align_code)
4116 {
4117 char *dest = (fragP)->fr_literal + (fragP)->fr_fix;
4118 valueT count = ((fragP)->fr_next->fr_address
4119 - (fragP)->fr_address - (fragP)->fr_fix);
4120
4121 (fragP)->fr_var = 2;
4122
4123 if (count & 1)/* Padding in the gap till the next 2-byte
4124 boundary with 0s. */
4125 {
4126 (fragP)->fr_fix++;
4127 *dest++ = 0;
4128 }
4129 /* Writing nop_s. */
4130 md_number_to_chars (dest, NOP_OPCODE_S, 2);
4131 }
4132}
4133
4134/* Here we decide which fixups can be adjusted to make them relative
4135 to the beginning of the section instead of the symbol. Basically
4136 we need to make sure that the dynamic relocations are done
4137 correctly, so in some cases we force the original symbol to be
4138 used. */
4139
4140int
4141tc_arc_fix_adjustable (fixS *fixP)
4142{
4143
4144 /* Prevent all adjustments to global symbols. */
4145 if (S_IS_EXTERNAL (fixP->fx_addsy))
4146 return 0;
4147 if (S_IS_WEAK (fixP->fx_addsy))
4148 return 0;
4149
4150 /* Adjust_reloc_syms doesn't know about the GOT. */
4151 switch (fixP->fx_r_type)
4152 {
4153 case BFD_RELOC_ARC_GOTPC32:
4154 case BFD_RELOC_ARC_PLT32:
4155 case BFD_RELOC_ARC_S25H_PCREL_PLT:
4156 case BFD_RELOC_ARC_S21H_PCREL_PLT:
4157 case BFD_RELOC_ARC_S25W_PCREL_PLT:
4158 case BFD_RELOC_ARC_S21W_PCREL_PLT:
4159 return 0;
4160
4161 default:
4162 break;
4163 }
4164
841fdfcd 4165 return 1;
886a2506
NC		 4166}
4167
4168/* Compute the reloc type of an expression EXP. */
4169
4170static void
4171arc_check_reloc (expressionS *exp,
4172 bfd_reloc_code_real_type *r_type_p)
4173{
4174 if (*r_type_p == BFD_RELOC_32
4175 && exp->X_op == O_subtract
4176 && exp->X_op_symbol != NULL
4177 && exp->X_op_symbol->bsym->section == now_seg)
6f4b1afc 4178 *r_type_p = BFD_RELOC_ARC_32_PCREL;
886a2506
NC		 4179}
4180
4181
4182/* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4183
4184void
4185arc_cons_fix_new (fragS *frag,
4186 int off,
4187 int size,
4188 expressionS *exp,
4189 bfd_reloc_code_real_type r_type)
4190{
4191 r_type = BFD_RELOC_UNUSED;
4192
4193 switch (size)
4194 {
4195 case 1:
4196 r_type = BFD_RELOC_8;
4197 break;
4198
4199 case 2:
4200 r_type = BFD_RELOC_16;
4201 break;
4202
4203 case 3:
4204 r_type = BFD_RELOC_24;
4205 break;
4206
4207 case 4:
4208 r_type = BFD_RELOC_32;
4209 arc_check_reloc (exp, &r_type);
4210 break;
4211
4212 case 8:
4213 r_type = BFD_RELOC_64;
4214 break;
4215
4216 default:
4217 as_bad (_("unsupported BFD relocation size %u"), size);
4218 r_type = BFD_RELOC_UNUSED;
4219 }
4220
4221 fix_new_exp (frag, off, size, exp, 0, r_type);
4222}
4223
4224/* The actual routine that checks the ZOL conditions. */
4225
4226static void
4227check_zol (symbolS *s)
4228{
bb65a718 4229 switch (selected_cpu.mach)
886a2506
NC		 4230 {
4231 case bfd_mach_arc_arcv2:
bb65a718 4232 if (selected_cpu.flags & ARC_OPCODE_ARCv2EM)
886a2506
NC		 4233 return;
4234
4235 if (is_br_jmp_insn_p (arc_last_insns[0].opcode)
4236 || arc_last_insns[1].has_delay_slot)
4237 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4238 S_GET_NAME (s));
4239
4240 break;
4241 case bfd_mach_arc_arc600:
4242
4243 if (is_kernel_insn_p (arc_last_insns[0].opcode))
4244 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4245 S_GET_NAME (s));
4246
4247 if (arc_last_insns[0].has_limm
4248 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
4249 as_bad (_("A jump instruction with long immediate detected at the \
4250end of the ZOL label @%s"), S_GET_NAME (s));
4251
4252 /* Fall through. */
4253 case bfd_mach_arc_arc700:
4254 if (arc_last_insns[0].has_delay_slot)
4255 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4256 S_GET_NAME (s));
4257
4258 break;
4259 default:
4260 break;
4261 }
4262}
4263
4264/* If ZOL end check the last two instruction for illegals. */
4265void
4266arc_frob_label (symbolS * sym)
4267{
4268 if (ARC_GET_FLAG (sym) & ARC_FLAG_ZOL)
4269 check_zol (sym);
4270
4271 dwarf2_emit_label (sym);
ea1562b3 4272}
4670103e
CZ		 4273
4274/* Used because generic relaxation assumes a pc-rel value whilst we
4275 also relax instructions that use an absolute value resolved out of
4276 relative values (if that makes any sense). An example: 'add r1,
4277 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4278 but if they're in the same section we can subtract the section
4279 offset relocation which ends up in a resolved value. So if @.L2 is
4280 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4281 .text + 0x40 = 0x10. */
4282int
4283arc_pcrel_adjust (fragS *fragP)
4284{
cc07cda6
CZ		 4285 pr_debug ("arc_pcrel_adjust: address=%ld, fix=%ld, PCrel %s\n",
4286 fragP->fr_address, fragP->fr_fix,
4287 fragP->tc_frag_data.pcrel ? "Y" : "N");
4288
4670103e
CZ		 4289 if (!fragP->tc_frag_data.pcrel)
4290 return fragP->fr_address + fragP->fr_fix;
4291
cc07cda6
CZ		 4292 /* Take into account the PCL rounding. */
4293 return (fragP->fr_address + fragP->fr_fix) & 0x03;
4670103e 4294}
726c18e1
CZ		 4295
4296/* Initialize the DWARF-2 unwind information for this procedure. */
4297
4298void
4299tc_arc_frame_initial_instructions (void)
4300{
4301 /* Stack pointer is register 28. */
45a54ee5 4302 cfi_add_CFA_def_cfa (28, 0);
726c18e1
CZ		 4303}
4304
4305int
4306tc_arc_regname_to_dw2regnum (char *regname)
4307{
4308 struct symbol *sym;
4309
4310 sym = hash_find (arc_reg_hash, regname);
4311 if (sym)
4312 return S_GET_VALUE (sym);
4313
4314 return -1;
4315}
37ab9779
CZ		 4316
4317/* Adjust the symbol table. Delete found AUX register symbols. */
4318
4319void
4320arc_adjust_symtab (void)
4321{
4322 symbolS * sym;
4323
4324 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4325 {
4326 /* I've created a symbol during parsing process. Now, remove
4327 the symbol as it is found to be an AUX register. */
4328 if (ARC_GET_FLAG (sym) & ARC_FLAG_AUX)
4329 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
4330 }
4331
4332 /* Now do generic ELF adjustments. */
4333 elf_adjust_symtab ();
4334}
b99747ae
CZ		 4335
4336static void
4337tokenize_extinsn (extInstruction_t *einsn)
4338{
4339 char *p, c;
4340 char *insn_name;
4341 unsigned char major_opcode;
4342 unsigned char sub_opcode;
4343 unsigned char syntax_class = 0;
4344 unsigned char syntax_class_modifiers = 0;
4345 unsigned char suffix_class = 0;
4346 unsigned int i;
4347
4348 SKIP_WHITESPACE ();
4349
4350 /* 1st: get instruction name. */
4351 p = input_line_pointer;
4352 c = get_symbol_name (&p);
4353
4354 insn_name = xstrdup (p);
4355 restore_line_pointer (c);
4356
4357 /* 2nd: get major opcode. */
4358 if (*input_line_pointer != ',')
4359 {
4360 as_bad (_("expected comma after instruction name"));
4361 ignore_rest_of_line ();
4362 return;
4363 }
4364 input_line_pointer++;
4365 major_opcode = get_absolute_expression ();
4366
4367 /* 3rd: get sub-opcode. */
4368 SKIP_WHITESPACE ();
4369
4370 if (*input_line_pointer != ',')
4371 {
4372 as_bad (_("expected comma after major opcode"));
4373 ignore_rest_of_line ();
4374 return;
4375 }
4376 input_line_pointer++;
4377 sub_opcode = get_absolute_expression ();
4378
4379 /* 4th: get suffix class. */
4380 SKIP_WHITESPACE ();
4381
4382 if (*input_line_pointer != ',')
4383 {
4384 as_bad ("expected comma after sub opcode");
4385 ignore_rest_of_line ();
4386 return;
4387 }
4388 input_line_pointer++;
4389
4390 while (1)
4391 {
4392 SKIP_WHITESPACE ();
4393
4394 for (i = 0; i < ARRAY_SIZE (suffixclass); i++)
4395 {
4396 if (!strncmp (suffixclass[i].name, input_line_pointer,
4397 suffixclass[i].len))
4398 {
c810e0b8 4399 suffix_class |= suffixclass[i].attr_class;
b99747ae
CZ		 4400 input_line_pointer += suffixclass[i].len;
4401 break;
4402 }
4403 }
4404
4405 if (i == ARRAY_SIZE (suffixclass))
4406 {
4407 as_bad ("invalid suffix class");
4408 ignore_rest_of_line ();
4409 return;
4410 }
4411
4412 SKIP_WHITESPACE ();
4413
4414 if (*input_line_pointer == '|')
4415 input_line_pointer++;
4416 else
4417 break;
4418 }
4419
4420 /* 5th: get syntax class and syntax class modifiers. */
4421 if (*input_line_pointer != ',')
4422 {
4423 as_bad ("expected comma after suffix class");
4424 ignore_rest_of_line ();
4425 return;
4426 }
4427 input_line_pointer++;
4428
4429 while (1)
4430 {
4431 SKIP_WHITESPACE ();
4432
4433 for (i = 0; i < ARRAY_SIZE (syntaxclassmod); i++)
4434 {
4435 if (!strncmp (syntaxclassmod[i].name,
4436 input_line_pointer,
4437 syntaxclassmod[i].len))
4438 {
c810e0b8 4439 syntax_class_modifiers |= syntaxclassmod[i].attr_class;
b99747ae
CZ		 4440 input_line_pointer += syntaxclassmod[i].len;
4441 break;
4442 }
4443 }
4444
4445 if (i == ARRAY_SIZE (syntaxclassmod))
4446 {
4447 for (i = 0; i < ARRAY_SIZE (syntaxclass); i++)
4448 {
4449 if (!strncmp (syntaxclass[i].name,
4450 input_line_pointer,
4451 syntaxclass[i].len))
4452 {
c810e0b8 4453 syntax_class |= syntaxclass[i].attr_class;
b99747ae
CZ		 4454 input_line_pointer += syntaxclass[i].len;
4455 break;
4456 }
4457 }
4458
4459 if (i == ARRAY_SIZE (syntaxclass))
4460 {
4461 as_bad ("missing syntax class");
4462 ignore_rest_of_line ();
4463 return;
4464 }
4465 }
4466
4467 SKIP_WHITESPACE ();
4468
4469 if (*input_line_pointer == '|')
4470 input_line_pointer++;
4471 else
4472 break;
4473 }
4474
4475 demand_empty_rest_of_line ();
4476
4477 einsn->name = insn_name;
4478 einsn->major = major_opcode;
4479 einsn->minor = sub_opcode;
4480 einsn->syntax = syntax_class;
4481 einsn->modsyn = syntax_class_modifiers;
4482 einsn->suffix = suffix_class;
4483 einsn->flags = syntax_class
4484 | (syntax_class_modifiers & ARC_OP1_IMM_IMPLIED ? 0x10 : 0);
4485}
4486
4487/* Generate an extension section. */
4488
4489static int
4490arc_set_ext_seg (void)
4491{
4492 if (!arcext_section)
4493 {
4494 arcext_section = subseg_new (".arcextmap", 0);
4495 bfd_set_section_flags (stdoutput, arcext_section,
4496 SEC_READONLY | SEC_HAS_CONTENTS);
4497 }
4498 else
4499 subseg_set (arcext_section, 0);
4500 return 1;
4501}
4502
4503/* Create an extension instruction description in the arc extension
4504 section of the output file.
4505 The structure for an instruction is like this:
4506 [0]: Length of the record.
4507 [1]: Type of the record.
4508
4509 [2]: Major opcode.
4510 [3]: Sub-opcode.
4511 [4]: Syntax (flags).
4512 [5]+ Name instruction.
4513
4514 The sequence is terminated by an empty entry. */
4515
4516static void
4517create_extinst_section (extInstruction_t *einsn)
4518{
4519
4520 segT old_sec = now_seg;
4521 int old_subsec = now_subseg;
4522 char *p;
4523 int name_len = strlen (einsn->name);
4524
4525 arc_set_ext_seg ();
4526
4527 p = frag_more (1);
4528 *p = 5 + name_len + 1;
4529 p = frag_more (1);
4530 *p = EXT_INSTRUCTION;
4531 p = frag_more (1);
4532 *p = einsn->major;
4533 p = frag_more (1);
4534 *p = einsn->minor;
4535 p = frag_more (1);
4536 *p = einsn->flags;
4537 p = frag_more (name_len + 1);
4538 strcpy (p, einsn->name);
4539
4540 subseg_set (old_sec, old_subsec);
4541}
4542
4543/* Handler .extinstruction pseudo-op. */
4544
4545static void
4546arc_extinsn (int ignore ATTRIBUTE_UNUSED)
4547{
4548 extInstruction_t einsn;
4549 struct arc_opcode *arc_ext_opcodes;
4550 const char *errmsg = NULL;
4551 unsigned char moplow, mophigh;
4552
4553 memset (&einsn, 0, sizeof (einsn));
4554 tokenize_extinsn (&einsn);
4555
4556 /* Check if the name is already used. */
4557 if (arc_find_opcode (einsn.name))
4558 as_warn (_("Pseudocode already used %s"), einsn.name);
4559
4560 /* Check the opcode ranges. */
4561 moplow = 0x05;
bb65a718
AB		 4562 mophigh = (selected_cpu.flags & (ARC_OPCODE_ARCv2EM
4563 | ARC_OPCODE_ARCv2HS)) ? 0x07 : 0x0a;
b99747ae
CZ		 4564
4565 if ((einsn.major > mophigh) || (einsn.major < moplow))
4566 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow, mophigh);
4567
4568 if ((einsn.minor > 0x3f) && (einsn.major != 0x0a)
4569 && (einsn.major != 5) && (einsn.major != 9))
4570 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4571
945e0f82 4572 switch (einsn.syntax & ARC_SYNTAX_MASK)
b99747ae
CZ		 4573 {
4574 case ARC_SYNTAX_3OP:
4575 if (einsn.modsyn & ARC_OP1_IMM_IMPLIED)
4576 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4577 break;
4578 case ARC_SYNTAX_2OP:
945e0f82
CZ		 4579 case ARC_SYNTAX_1OP:
4580 case ARC_SYNTAX_NOP:
b99747ae
CZ		 4581 if (einsn.modsyn & ARC_OP1_MUST_BE_IMM)
4582 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4583 break;
4584 default:
4585 break;
4586 }
4587
bb65a718 4588 arc_ext_opcodes = arcExtMap_genOpcode (&einsn, selected_cpu.flags, &errmsg);
b99747ae
CZ		 4589 if (arc_ext_opcodes == NULL)
4590 {
4591 if (errmsg)
4592 as_fatal ("%s", errmsg);
4593 else
4594 as_fatal (_("Couldn't generate extension instruction opcodes"));
4595 }
4596 else if (errmsg)
4597 as_warn ("%s", errmsg);
4598
4599 /* Insert the extension instruction. */
4600 arc_insert_opcode ((const struct arc_opcode *) arc_ext_opcodes);
4601
4602 create_extinst_section (&einsn);
4603}
4604
06911889 4605static bfd_boolean
f36e33da
CZ		 4606tokenize_extregister (extRegister_t *ereg, int opertype)
4607{
4608 char *name;
4609 char *mode;
4610 char c;
4611 char *p;
4612 int number, imode = 0;
4613 bfd_boolean isCore_p = (opertype == EXT_CORE_REGISTER) ? TRUE : FALSE;
4614 bfd_boolean isReg_p = (opertype == EXT_CORE_REGISTER
4615 || opertype == EXT_AUX_REGISTER) ? TRUE : FALSE;
4616
4617 /* 1st: get register name. */
4618 SKIP_WHITESPACE ();
4619 p = input_line_pointer;
4620 c = get_symbol_name (&p);
4621
4622 name = xstrdup (p);
4623 restore_line_pointer (c);
4624
4625 /* 2nd: get register number. */
4626 SKIP_WHITESPACE ();
4627
4628 if (*input_line_pointer != ',')
4629 {
06911889 4630 as_bad (_("expected comma after name"));
f36e33da
CZ		 4631 ignore_rest_of_line ();
4632 free (name);
06911889 4633 return FALSE;
f36e33da
CZ		 4634 }
4635 input_line_pointer++;
4636 number = get_absolute_expression ();
4637
06911889
CZ		 4638 if ((number < 0)
4639 && (opertype != EXT_AUX_REGISTER))
f36e33da 4640 {
06911889
CZ		 4641 as_bad (_("%s second argument cannot be a negative number %d"),
4642 isCore_p ? "extCoreRegister's" : "extCondCode's",
4643 number);
f36e33da
CZ		 4644 ignore_rest_of_line ();
4645 free (name);
06911889 4646 return FALSE;
f36e33da
CZ		 4647 }
4648
4649 if (isReg_p)
4650 {
4651 /* 3rd: get register mode. */
4652 SKIP_WHITESPACE ();
4653
4654 if (*input_line_pointer != ',')
4655 {
4656 as_bad (_("expected comma after register number"));
4657 ignore_rest_of_line ();
4658 free (name);
06911889 4659 return FALSE;
f36e33da
CZ		 4660 }
4661
4662 input_line_pointer++;
4663 mode = input_line_pointer;
4664
4665 if (!strncmp (mode, "r|w", 3))
4666 {
4667 imode = 0;
4668 input_line_pointer += 3;
4669 }
4670 else if (!strncmp (mode, "r", 1))
4671 {
4672 imode = ARC_REGISTER_READONLY;
4673 input_line_pointer += 1;
4674 }
4675 else if (strncmp (mode, "w", 1))
4676 {
4677 as_bad (_("invalid mode"));
4678 ignore_rest_of_line ();
4679 free (name);
06911889 4680 return FALSE;
f36e33da
CZ		 4681 }
4682 else
4683 {
4684 imode = ARC_REGISTER_WRITEONLY;
4685 input_line_pointer += 1;
4686 }
4687 }
4688
4689 if (isCore_p)
4690 {
4691 /* 4th: get core register shortcut. */
4692 SKIP_WHITESPACE ();
4693 if (*input_line_pointer != ',')
4694 {
4695 as_bad (_("expected comma after register mode"));
4696 ignore_rest_of_line ();
4697 free (name);
06911889 4698 return FALSE;
f36e33da
CZ		 4699 }
4700
4701 input_line_pointer++;
4702
4703 if (!strncmp (input_line_pointer, "cannot_shortcut", 15))
4704 {
4705 imode |= ARC_REGISTER_NOSHORT_CUT;
4706 input_line_pointer += 15;
4707 }
4708 else if (strncmp (input_line_pointer, "can_shortcut", 12))
4709 {
4710 as_bad (_("shortcut designator invalid"));
4711 ignore_rest_of_line ();
4712 free (name);
06911889 4713 return FALSE;
f36e33da
CZ		 4714 }
4715 else
4716 {
4717 input_line_pointer += 12;
4718 }
4719 }
4720 demand_empty_rest_of_line ();
4721
4722 ereg->name = name;
4723 ereg->number = number;
4724 ereg->imode = imode;
06911889 4725 return TRUE;
f36e33da
CZ		 4726}
4727
4728/* Create an extension register/condition description in the arc
4729 extension section of the output file.
4730
4731 The structure for an instruction is like this:
4732 [0]: Length of the record.
4733 [1]: Type of the record.
4734
4735 For core regs and condition codes:
4736 [2]: Value.
4737 [3]+ Name.
4738
33eaf5de 4739 For auxiliary registers:
f36e33da
CZ		 4740 [2..5]: Value.
4741 [6]+ Name
4742
4743 The sequence is terminated by an empty entry. */
4744
4745static void
4746create_extcore_section (extRegister_t *ereg, int opertype)
4747{
4748 segT old_sec = now_seg;
4749 int old_subsec = now_subseg;
4750 char *p;
4751 int name_len = strlen (ereg->name);
4752
4753 arc_set_ext_seg ();
4754
4755 switch (opertype)
4756 {
4757 case EXT_COND_CODE:
4758 case EXT_CORE_REGISTER:
4759 p = frag_more (1);
4760 *p = 3 + name_len + 1;
4761 p = frag_more (1);
4762 *p = opertype;
4763 p = frag_more (1);
4764 *p = ereg->number;
4765 break;
4766 case EXT_AUX_REGISTER:
4767 p = frag_more (1);
4768 *p = 6 + name_len + 1;
4769 p = frag_more (1);
4770 *p = EXT_AUX_REGISTER;
4771 p = frag_more (1);
4772 *p = (ereg->number >> 24) & 0xff;
4773 p = frag_more (1);
4774 *p = (ereg->number >> 16) & 0xff;
4775 p = frag_more (1);
4776 *p = (ereg->number >> 8) & 0xff;
4777 p = frag_more (1);
4778 *p = (ereg->number) & 0xff;
4779 break;
4780 default:
4781 break;
4782 }
4783
4784 p = frag_more (name_len + 1);
4785 strcpy (p, ereg->name);
4786
4787 subseg_set (old_sec, old_subsec);
4788}
4789
4790/* Handler .extCoreRegister pseudo-op. */
4791
4792static void
4793arc_extcorereg (int opertype)
4794{
4795 extRegister_t ereg;
4796 struct arc_aux_reg *auxr;
4797 const char *retval;
4798 struct arc_flag_operand *ccode;
4799
4800 memset (&ereg, 0, sizeof (ereg));
06911889
CZ		 4801 if (!tokenize_extregister (&ereg, opertype))
4802 return;
f36e33da
CZ		 4803
4804 switch (opertype)
4805 {
4806 case EXT_CORE_REGISTER:
4807 /* Core register. */
4808 if (ereg.number > 60)
4809 as_bad (_("core register %s value (%d) too large"), ereg.name,
4810 ereg.number);
4811 declare_register (ereg.name, ereg.number);
4812 break;
4813 case EXT_AUX_REGISTER:
4814 /* Auxiliary register. */
add39d23 4815 auxr = XNEW (struct arc_aux_reg);
f36e33da 4816 auxr->name = ereg.name;
bb65a718 4817 auxr->cpu = selected_cpu.flags;
f36e33da
CZ		 4818 auxr->subclass = NONE;
4819 auxr->address = ereg.number;
4820 retval = hash_insert (arc_aux_hash, auxr->name, (void *) auxr);
4821 if (retval)
4822 as_fatal (_("internal error: can't hash aux register '%s': %s"),
4823 auxr->name, retval);
4824 break;
4825 case EXT_COND_CODE:
4826 /* Condition code. */
4827 if (ereg.number > 31)
4828 as_bad (_("condition code %s value (%d) too large"), ereg.name,
4829 ereg.number);
4830 ext_condcode.size ++;
4831 ext_condcode.arc_ext_condcode =
add39d23
TS		 4832 XRESIZEVEC (struct arc_flag_operand, ext_condcode.arc_ext_condcode,
4833 ext_condcode.size + 1);
f36e33da
CZ		 4834 if (ext_condcode.arc_ext_condcode == NULL)
4835 as_fatal (_("Virtual memory exhausted"));
4836
4837 ccode = ext_condcode.arc_ext_condcode + ext_condcode.size - 1;
4838 ccode->name = ereg.name;
4839 ccode->code = ereg.number;
4840 ccode->bits = 5;
4841 ccode->shift = 0;
4842 ccode->favail = 0; /* not used. */
4843 ccode++;
4844 memset (ccode, 0, sizeof (struct arc_flag_operand));
4845 break;
4846 default:
4847 as_bad (_("Unknown extension"));
4848 break;
4849 }
4850 create_extcore_section (&ereg, opertype);
4851}
4852
53a346d8
CZ		 4853/* Parse a .arc_attribute directive. */
4854
4855static void
4856arc_attribute (int ignored ATTRIBUTE_UNUSED)
4857{
4858 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
4859
4860 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4861 attributes_set_explicitly[tag] = TRUE;
4862}
4863
4864/* Set an attribute if it has not already been set by the user. */
4865
4866static void
4867arc_set_attribute_int (int tag, int value)
4868{
4869 if (tag < 1
4870 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
4871 || !attributes_set_explicitly[tag])
4872 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
4873}
4874
4875static void
4876arc_set_attribute_string (int tag, const char *value)
4877{
4878 if (tag < 1
4879 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
4880 || !attributes_set_explicitly[tag])
4881 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
4882}
4883
4884/* Allocate and concatenate two strings. s1 can be NULL but not
4885 s2. s1 pointer is freed at end of this procedure. */
4886
4887static char *
4888arc_stralloc (char * s1, const char * s2)
4889{
4890 char * p;
4891 int len = 0;
4892
4893 if (s1)
4894 len = strlen (s1) + 1;
4895
4896 /* Only s1 can be null. */
4897 gas_assert (s2);
4898 len += strlen (s2) + 1;
4899
4900 p = (char *) xmalloc (len);
4901 if (p == NULL)
4902 as_fatal (_("Virtual memory exhausted"));
4903
4904 if (s1)
4905 {
4906 strcpy (p, s1);
4907 strcat (p, ",");
4908 strcat (p, s2);
4909 free (s1);
4910 }
4911 else
4912 strcpy (p, s2);
4913
4914 return p;
4915}
4916
4917/* Set the public ARC object attributes. */
4918
4919static void
4920arc_set_public_attributes (void)
4921{
4922 int base = 0;
4923 char *s = NULL;
4924 unsigned int i;
4925
4926 /* Tag_ARC_CPU_name. */
4927 arc_set_attribute_string (Tag_ARC_CPU_name, selected_cpu.name);
4928
4929 /* Tag_ARC_CPU_base. */
4930 switch (selected_cpu.eflags & EF_ARC_MACH_MSK)
4931 {
4932 case E_ARC_MACH_ARC600:
4933 case E_ARC_MACH_ARC601:
4934 base = TAG_CPU_ARC6xx;
4935 break;
4936 case E_ARC_MACH_ARC700:
4937 base = TAG_CPU_ARC7xx;
4938 break;
4939 case EF_ARC_CPU_ARCV2EM:
4940 base = TAG_CPU_ARCEM;
4941 break;
4942 case EF_ARC_CPU_ARCV2HS:
4943 base = TAG_CPU_ARCHS;
4944 break;
4945 default:
4946 base = 0;
4947 break;
4948 }
4949 if (attributes_set_explicitly[Tag_ARC_CPU_base]
4950 && (base != bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
4951 Tag_ARC_CPU_base)))
4952 as_warn (_("Overwrite explicitly set Tag_ARC_CPU_base"));
4953 bfd_elf_add_proc_attr_int (stdoutput, Tag_ARC_CPU_base, base);
4954
4955 /* Tag_ARC_ABI_osver. */
4956 if (attributes_set_explicitly[Tag_ARC_ABI_osver])
4957 {
4958 int val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
4959 Tag_ARC_ABI_osver);
4960
4961 selected_cpu.eflags = ((selected_cpu.eflags & ~EF_ARC_OSABI_MSK)
4962 | (val & 0x0f << 8));
4963 }
4964 else
4965 {
4966 arc_set_attribute_int (Tag_ARC_ABI_osver, E_ARC_OSABI_CURRENT >> 8);
4967 }
4968
4969 /* Tag_ARC_ISA_config. */
4970 arc_check_feature();
4971
4972 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
4973 if (selected_cpu.features & feature_list[i].feature)
4974 s = arc_stralloc (s, feature_list[i].attr);
4975
4976 if (s)
4977 arc_set_attribute_string (Tag_ARC_ISA_config, s);
4978
4979 /* Tag_ARC_ISA_mpy_option. */
4980 arc_set_attribute_int (Tag_ARC_ISA_mpy_option, mpy_option);
4981
4982 /* Tag_ARC_ABI_pic. */
4983 arc_set_attribute_int (Tag_ARC_ABI_pic, pic_option);
4984
4985 /* Tag_ARC_ABI_sda. */
4986 arc_set_attribute_int (Tag_ARC_ABI_sda, sda_option);
4987
4988 /* Tag_ARC_ABI_tls. */
4989 arc_set_attribute_int (Tag_ARC_ABI_tls, tls_option);
4990}
4991
4992/* Add the default contents for the .ARC.attributes section. */
4993
4994void
4995arc_md_end (void)
4996{
4997 arc_set_public_attributes ();
4998
4999 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
5000 as_fatal (_("could not set architecture and machine"));
5001
5002 bfd_set_private_flags (stdoutput, selected_cpu.eflags);
5003}
5004
5005void arc_copy_symbol_attributes (symbolS *dest, symbolS *src)
5006{
5007 ARC_GET_FLAG (dest) = ARC_GET_FLAG (src);
5008}
5009
5010int arc_convert_symbolic_attribute (const char *name)
5011{
5012 static const struct
5013 {
5014 const char * name;
5015 const int tag;
5016 }
5017 attribute_table[] =
5018 {
5019#define T(tag) {#tag, tag}
5020 T (Tag_ARC_PCS_config),
5021 T (Tag_ARC_CPU_base),
5022 T (Tag_ARC_CPU_variation),
5023 T (Tag_ARC_CPU_name),
5024 T (Tag_ARC_ABI_rf16),
5025 T (Tag_ARC_ABI_osver),
5026 T (Tag_ARC_ABI_sda),
5027 T (Tag_ARC_ABI_pic),
5028 T (Tag_ARC_ABI_tls),
5029 T (Tag_ARC_ABI_enumsize),
5030 T (Tag_ARC_ABI_exceptions),
5031 T (Tag_ARC_ABI_double_size),
5032 T (Tag_ARC_ISA_config),
5033 T (Tag_ARC_ISA_apex),
5034 T (Tag_ARC_ISA_mpy_option)
5035#undef T
5036 };
5037 unsigned int i;
5038
5039 if (name == NULL)
5040 return -1;
5041
5042 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
5043 if (streq (name, attribute_table[i].name))
5044 return attribute_table[i].tag;
5045
5046 return -1;
5047}
5048
b99747ae
CZ		 5049/* Local variables:
5050 eval: (c-set-style "gnu")
5051 indent-tabs-mode: t
5052 End: */
GDB Binutils - Deliverables
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