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S/390: Suppress string diagnostics for pre-release GCC
[deliverable/binutils-gdb.git] / gas / config / tc-arc.c
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252b5132 1/* tc-arc.c -- Assembler for the ARC
219d1afa 2 Copyright (C) 1994-2018 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19203624 19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
252b5132 23#include "as.h"
886a2506 24#include "subsegs.h"
a161fe53 25#include "struc-symbol.h"
886a2506 26#include "dwarf2dbg.h"
726c18e1 27#include "dw2gencfi.h"
3882b010 28#include "safe-ctype.h"
886a2506 29
252b5132 30#include "opcode/arc.h"
53a346d8 31#include "opcode/arc-attrs.h"
252b5132 32#include "elf/arc.h"
b99747ae 33#include "../opcodes/arc-ext.h"
252b5132 34
886a2506 35/* Defines section. */
0d2bcfaf 36
886a2506
NC		 37#define MAX_INSN_FIXUPS 2
38#define MAX_CONSTR_STR 20
4670103e 39#define FRAG_MAX_GROWTH 8
0d2bcfaf 40
886a2506
NC		 41#ifdef DEBUG
42# define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
43#else
44# define pr_debug(fmt, args...)
45#endif
46
47#define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
48#define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
db18dbab
GM		 49#define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
50 && (SUB_OPCODE (x) == 0x28))
886a2506
NC		 51
52/* Equal to MAX_PRECISION in atof-ieee.c. */
53#define MAX_LITTLENUMS 6
54
9004b6bd
AB		 55#ifndef TARGET_WITH_CPU
56#define TARGET_WITH_CPU "arc700"
57#endif /* TARGET_WITH_CPU */
58
53a346d8
CZ		 59#define ARC_GET_FLAG(s) (*symbol_get_tc (s))
60#define ARC_SET_FLAG(s,v) (*symbol_get_tc (s) |= (v))
61#define streq(a, b) (strcmp (a, b) == 0)
62
4670103e
CZ		 63/* Enum used to enumerate the relaxable ins operands. */
64enum rlx_operand_type
65{
66 EMPTY = 0,
67 REGISTER,
68 REGISTER_S, /* Register for short instruction(s). */
69 REGISTER_NO_GP, /* Is a register but not gp register specifically. */
70 REGISTER_DUP, /* Duplication of previous operand of type register. */
71 IMMEDIATE,
72 BRACKET
73};
74
75enum arc_rlx_types
76{
77 ARC_RLX_NONE = 0,
78 ARC_RLX_BL_S,
79 ARC_RLX_BL,
80 ARC_RLX_B_S,
81 ARC_RLX_B,
82 ARC_RLX_ADD_U3,
83 ARC_RLX_ADD_U6,
84 ARC_RLX_ADD_LIMM,
85 ARC_RLX_LD_U7,
86 ARC_RLX_LD_S9,
87 ARC_RLX_LD_LIMM,
88 ARC_RLX_MOV_U8,
89 ARC_RLX_MOV_S12,
90 ARC_RLX_MOV_LIMM,
91 ARC_RLX_SUB_U3,
92 ARC_RLX_SUB_U6,
93 ARC_RLX_SUB_LIMM,
94 ARC_RLX_MPY_U6,
95 ARC_RLX_MPY_LIMM,
96 ARC_RLX_MOV_RU6,
97 ARC_RLX_MOV_RLIMM,
98 ARC_RLX_ADD_RRU6,
99 ARC_RLX_ADD_RRLIMM,
100};
101
886a2506
NC		 102/* Macros section. */
103
104#define regno(x) ((x) & 0x3F)
105#define is_ir_num(x) (((x) & ~0x3F) == 0)
8ddf6b2a
CZ		 106#define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
107#define is_spfp_p(op) (((sc) == SPX))
108#define is_dpfp_p(op) (((sc) == DPX))
109#define is_fpuda_p(op) (((sc) == DPA))
cf9bdae9 110#define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
111 || (op)->insn_class == JUMP \
112 || (op)->insn_class == BRCC \
113 || (op)->insn_class == BBIT0 \
114 || (op)->insn_class == BBIT1 \
115 || (op)->insn_class == BI \
116 || (op)->insn_class == EI \
117 || (op)->insn_class == ENTER \
118 || (op)->insn_class == JLI \
119 || (op)->insn_class == LOOP \
120 || (op)->insn_class == LEAVE \
121 ))
c810e0b8 122#define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
bdd582db 123#define is_nps400_p(op) (((sc) == NPS400))
0d2bcfaf 124
886a2506
NC		 125/* Generic assembler global variables which must be defined by all
126 targets. */
0d2bcfaf 127
886a2506 128/* Characters which always start a comment. */
252b5132
RH		 129const char comment_chars[] = "#;";
130
886a2506 131/* Characters which start a comment at the beginning of a line. */
252b5132
RH		 132const char line_comment_chars[] = "#";
133
886a2506
NC		 134/* Characters which may be used to separate multiple commands on a
135 single line. */
136const char line_separator_chars[] = "`";
252b5132 137
886a2506
NC		 138/* Characters which are used to indicate an exponent in a floating
139 point number. */
252b5132
RH		 140const char EXP_CHARS[] = "eE";
141
bcee8eb8
AM		 142/* Chars that mean this number is a floating point constant
143 As in 0f12.456 or 0d1.2345e12. */
252b5132
RH		 144const char FLT_CHARS[] = "rRsSfFdD";
145
146/* Byte order. */
147extern int target_big_endian;
148const char *arc_target_format = DEFAULT_TARGET_FORMAT;
149static int byte_order = DEFAULT_BYTE_ORDER;
150
b99747ae
CZ		 151/* Arc extension section. */
152static segT arcext_section;
153
4670103e
CZ		 154/* By default relaxation is disabled. */
155static int relaxation_state = 0;
156
886a2506 157extern int arc_get_mach (char *);
0d2bcfaf 158
4670103e 159/* Forward declarations. */
886a2506
NC		 160static void arc_lcomm (int);
161static void arc_option (int);
162static void arc_extra_reloc (int);
b99747ae 163static void arc_extinsn (int);
f36e33da 164static void arc_extcorereg (int);
53a346d8 165static void arc_attribute (int);
4670103e 166
886a2506 167const pseudo_typeS md_pseudo_table[] =
6f4b1afc
CM		 168{
169 /* Make sure that .word is 32 bits. */
170 { "word", cons, 4 },
886a2506 171
6f4b1afc
CM		 172 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
173 { "lcomm", arc_lcomm, 0 },
174 { "lcommon", arc_lcomm, 0 },
175 { "cpu", arc_option, 0 },
252b5132 176
53a346d8 177 { "arc_attribute", arc_attribute, 0 },
f36e33da
CZ		 178 { "extinstruction", arc_extinsn, 0 },
179 { "extcoreregister", arc_extcorereg, EXT_CORE_REGISTER },
180 { "extauxregister", arc_extcorereg, EXT_AUX_REGISTER },
181 { "extcondcode", arc_extcorereg, EXT_COND_CODE },
b99747ae 182
6f4b1afc
CM		 183 { "tls_gd_ld", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_LD },
184 { "tls_gd_call", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_CALL },
886a2506 185
6f4b1afc
CM		 186 { NULL, NULL, 0 }
187};
252b5132 188
252b5132 189const char *md_shortopts = "";
ea1562b3
NC		 190
191enum options
6f4b1afc
CM		 192{
193 OPTION_EB = OPTION_MD_BASE,
194 OPTION_EL,
195
196 OPTION_ARC600,
197 OPTION_ARC601,
198 OPTION_ARC700,
199 OPTION_ARCEM,
200 OPTION_ARCHS,
201
202 OPTION_MCPU,
203 OPTION_CD,
4670103e 204 OPTION_RELAX,
bdd582db 205 OPTION_NPS400,
6f4b1afc 206
ce440d63
GM		 207 OPTION_SPFP,
208 OPTION_DPFP,
209 OPTION_FPUDA,
210
6f4b1afc
CM		 211 /* The following options are deprecated and provided here only for
212 compatibility reasons. */
213 OPTION_USER_MODE,
214 OPTION_LD_EXT_MASK,
215 OPTION_SWAP,
216 OPTION_NORM,
217 OPTION_BARREL_SHIFT,
218 OPTION_MIN_MAX,
219 OPTION_NO_MPY,
220 OPTION_EA,
221 OPTION_MUL64,
222 OPTION_SIMD,
6f4b1afc
CM		 223 OPTION_XMAC_D16,
224 OPTION_XMAC_24,
225 OPTION_DSP_PACKA,
226 OPTION_CRC,
227 OPTION_DVBF,
228 OPTION_TELEPHONY,
229 OPTION_XYMEMORY,
230 OPTION_LOCK,
231 OPTION_SWAPE,
ce440d63 232 OPTION_RTSC
6f4b1afc 233};
ea1562b3
NC		 234
235struct option md_longopts[] =
6f4b1afc
CM		 236{
237 { "EB", no_argument, NULL, OPTION_EB },
238 { "EL", no_argument, NULL, OPTION_EL },
239 { "mcpu", required_argument, NULL, OPTION_MCPU },
240 { "mA6", no_argument, NULL, OPTION_ARC600 },
24b368f8
CZ		 241 { "mARC600", no_argument, NULL, OPTION_ARC600 },
242 { "mARC601", no_argument, NULL, OPTION_ARC601 },
243 { "mARC700", no_argument, NULL, OPTION_ARC700 },
6f4b1afc
CM		 244 { "mA7", no_argument, NULL, OPTION_ARC700 },
245 { "mEM", no_argument, NULL, OPTION_ARCEM },
246 { "mHS", no_argument, NULL, OPTION_ARCHS },
247 { "mcode-density", no_argument, NULL, OPTION_CD },
4670103e 248 { "mrelax", no_argument, NULL, OPTION_RELAX },
bdd582db 249 { "mnps400", no_argument, NULL, OPTION_NPS400 },
6f4b1afc 250
ce440d63
GM		 251 /* Floating point options */
252 { "mspfp", no_argument, NULL, OPTION_SPFP},
253 { "mspfp-compact", no_argument, NULL, OPTION_SPFP},
254 { "mspfp_compact", no_argument, NULL, OPTION_SPFP},
255 { "mspfp-fast", no_argument, NULL, OPTION_SPFP},
256 { "mspfp_fast", no_argument, NULL, OPTION_SPFP},
257 { "mdpfp", no_argument, NULL, OPTION_DPFP},
258 { "mdpfp-compact", no_argument, NULL, OPTION_DPFP},
259 { "mdpfp_compact", no_argument, NULL, OPTION_DPFP},
260 { "mdpfp-fast", no_argument, NULL, OPTION_DPFP},
261 { "mdpfp_fast", no_argument, NULL, OPTION_DPFP},
262 { "mfpuda", no_argument, NULL, OPTION_FPUDA},
263
6f4b1afc
CM		 264 /* The following options are deprecated and provided here only for
265 compatibility reasons. */
266 { "mav2em", no_argument, NULL, OPTION_ARCEM },
267 { "mav2hs", no_argument, NULL, OPTION_ARCHS },
268 { "muser-mode-only", no_argument, NULL, OPTION_USER_MODE },
269 { "mld-extension-reg-mask", required_argument, NULL, OPTION_LD_EXT_MASK },
270 { "mswap", no_argument, NULL, OPTION_SWAP },
271 { "mnorm", no_argument, NULL, OPTION_NORM },
272 { "mbarrel-shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
273 { "mbarrel_shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
274 { "mmin-max", no_argument, NULL, OPTION_MIN_MAX },
275 { "mmin_max", no_argument, NULL, OPTION_MIN_MAX },
276 { "mno-mpy", no_argument, NULL, OPTION_NO_MPY },
277 { "mea", no_argument, NULL, OPTION_EA },
278 { "mEA", no_argument, NULL, OPTION_EA },
279 { "mmul64", no_argument, NULL, OPTION_MUL64 },
280 { "msimd", no_argument, NULL, OPTION_SIMD},
6f4b1afc
CM		 281 { "mmac-d16", no_argument, NULL, OPTION_XMAC_D16},
282 { "mmac_d16", no_argument, NULL, OPTION_XMAC_D16},
283 { "mmac-24", no_argument, NULL, OPTION_XMAC_24},
284 { "mmac_24", no_argument, NULL, OPTION_XMAC_24},
285 { "mdsp-packa", no_argument, NULL, OPTION_DSP_PACKA},
286 { "mdsp_packa", no_argument, NULL, OPTION_DSP_PACKA},
287 { "mcrc", no_argument, NULL, OPTION_CRC},
288 { "mdvbf", no_argument, NULL, OPTION_DVBF},
289 { "mtelephony", no_argument, NULL, OPTION_TELEPHONY},
290 { "mxy", no_argument, NULL, OPTION_XYMEMORY},
291 { "mlock", no_argument, NULL, OPTION_LOCK},
292 { "mswape", no_argument, NULL, OPTION_SWAPE},
293 { "mrtsc", no_argument, NULL, OPTION_RTSC},
6f4b1afc
CM		 294
295 { NULL, no_argument, NULL, 0 }
296};
252b5132 297
886a2506 298size_t md_longopts_size = sizeof (md_longopts);
0d2bcfaf 299
886a2506 300/* Local data and data types. */
252b5132 301
886a2506
NC		 302/* Used since new relocation types are introduced in this
303 file (DUMMY_RELOC_LITUSE_*). */
304typedef int extended_bfd_reloc_code_real_type;
252b5132 305
886a2506 306struct arc_fixup
252b5132 307{
886a2506 308 expressionS exp;
252b5132 309
886a2506 310 extended_bfd_reloc_code_real_type reloc;
252b5132 311
886a2506
NC		 312 /* index into arc_operands. */
313 unsigned int opindex;
252b5132 314
886a2506
NC		 315 /* PC-relative, used by internals fixups. */
316 unsigned char pcrel;
252b5132 317
886a2506
NC		 318 /* TRUE if this fixup is for LIMM operand. */
319 bfd_boolean islong;
320};
252b5132 321
886a2506
NC		 322struct arc_insn
323{
bdfe53e3 324 unsigned long long int insn;
886a2506
NC		 325 int nfixups;
326 struct arc_fixup fixups[MAX_INSN_FIXUPS];
327 long limm;
91fdca6f 328 unsigned int len; /* Length of instruction in bytes. */
886a2506
NC		 329 bfd_boolean has_limm; /* Boolean value: TRUE if limm field is
330 valid. */
4670103e
CZ		 331 bfd_boolean relax; /* Boolean value: TRUE if needs
332 relaxation. */
886a2506 333};
ea1562b3 334
886a2506
NC		 335/* Structure to hold any last two instructions. */
336static struct arc_last_insn
252b5132 337{
886a2506
NC		 338 /* Saved instruction opcode. */
339 const struct arc_opcode *opcode;
252b5132 340
886a2506
NC		 341 /* Boolean value: TRUE if current insn is short. */
342 bfd_boolean has_limm;
252b5132 343
886a2506
NC		 344 /* Boolean value: TRUE if current insn has delay slot. */
345 bfd_boolean has_delay_slot;
346} arc_last_insns[2];
252b5132 347
b99747ae
CZ		 348/* Extension instruction suffix classes. */
349typedef struct
350{
351 const char *name;
352 int len;
c810e0b8 353 int attr_class;
b99747ae
CZ		 354} attributes_t;
355
356static const attributes_t suffixclass[] =
357{
358 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG },
359 { "SUFFIX_COND", 11, ARC_SUFFIX_COND },
360 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE }
361};
362
363/* Extension instruction syntax classes. */
364static const attributes_t syntaxclass[] =
365{
366 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP },
945e0f82
CZ		 367 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP },
368 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP },
369 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP }
b99747ae
CZ		 370};
371
372/* Extension instruction syntax classes modifiers. */
373static const attributes_t syntaxclassmod[] =
374{
375 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED },
376 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM }
377};
378
f36e33da
CZ		 379/* Extension register type. */
380typedef struct
381{
382 char *name;
383 int number;
384 int imode;
385} extRegister_t;
386
387/* A structure to hold the additional conditional codes. */
388static struct
389{
390 struct arc_flag_operand *arc_ext_condcode;
391 int size;
392} ext_condcode = { NULL, 0 };
393
da5be039
AB		 394/* Structure to hold an entry in ARC_OPCODE_HASH. */
395struct arc_opcode_hash_entry
396{
397 /* The number of pointers in the OPCODE list. */
398 size_t count;
399
400 /* Points to a list of opcode pointers. */
401 const struct arc_opcode **opcode;
402};
403
1328504b
AB		 404/* Structure used for iterating through an arc_opcode_hash_entry. */
405struct arc_opcode_hash_entry_iterator
406{
407 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
408 size_t index;
409
410 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
411 returned by this iterator. */
412 const struct arc_opcode *opcode;
413};
414
4670103e
CZ		 415/* Forward declaration. */
416static void assemble_insn
417 (const struct arc_opcode *, const expressionS *, int,
418 const struct arc_flags *, int, struct arc_insn *);
419
bb65a718
AB		 420/* The selection of the machine type can come from different sources. This
421 enum is used to track how the selection was made in order to perform
422 error checks. */
423enum mach_selection_type
424 {
425 MACH_SELECTION_NONE,
426 MACH_SELECTION_FROM_DEFAULT,
427 MACH_SELECTION_FROM_CPU_DIRECTIVE,
428 MACH_SELECTION_FROM_COMMAND_LINE
429 };
430
431/* How the current machine type was selected. */
432static enum mach_selection_type mach_selection_mode = MACH_SELECTION_NONE;
0d2bcfaf 433
886a2506
NC		 434/* The hash table of instruction opcodes. */
435static struct hash_control *arc_opcode_hash;
0d2bcfaf 436
886a2506
NC		 437/* The hash table of register symbols. */
438static struct hash_control *arc_reg_hash;
252b5132 439
f36e33da
CZ		 440/* The hash table of aux register symbols. */
441static struct hash_control *arc_aux_hash;
442
db18dbab
GM		 443/* The hash table of address types. */
444static struct hash_control *arc_addrtype_hash;
445
a9752fdf
CZ		 446#define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
447 { #NAME, ARC_OPCODE_ARC600, bfd_mach_arc_arc600, \
448 E_ARC_MACH_ARC600, EXTRA}
449#define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
450 { #NAME, ARC_OPCODE_ARC700, bfd_mach_arc_arc700, \
451 E_ARC_MACH_ARC700, EXTRA}
452#define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
453 { #NAME, ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, \
454 EF_ARC_CPU_ARCV2EM, EXTRA}
455#define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
456 { #NAME, ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \
457 EF_ARC_CPU_ARCV2HS, EXTRA}
940171d0
AK		 458#define ARC_CPU_TYPE_NONE \
459 { 0, 0, 0, 0, 0 }
a9752fdf 460
886a2506
NC		 461/* A table of CPU names and opcode sets. */
462static const struct cpu_type
463{
464 const char *name;
465 unsigned flags;
466 int mach;
467 unsigned eflags;
468 unsigned features;
252b5132 469}
886a2506 470 cpu_types[] =
252b5132 471{
940171d0 472 #include "elf/arc-cpu.def"
886a2506 473};
252b5132 474
bb65a718 475/* Information about the cpu/variant we're assembling for. */
53a346d8 476static struct cpu_type selected_cpu = { 0, 0, 0, E_ARC_OSABI_CURRENT, 0 };
bb050a69 477
53a346d8
CZ		 478/* MPY option. */
479static unsigned mpy_option = 0;
480
481/* Use PIC. */
482static unsigned pic_option = 0;
483
484/* Use small data. */
485static unsigned sda_option = 0;
486
487/* Use TLS. */
488static unsigned tls_option = 0;
bb65a718 489
a9752fdf
CZ		 490/* Command line given features. */
491static unsigned cl_features = 0;
492
886a2506
NC		 493/* Used by the arc_reloc_op table. Order is important. */
494#define O_gotoff O_md1 /* @gotoff relocation. */
495#define O_gotpc O_md2 /* @gotpc relocation. */
496#define O_plt O_md3 /* @plt relocation. */
497#define O_sda O_md4 /* @sda relocation. */
498#define O_pcl O_md5 /* @pcl relocation. */
499#define O_tlsgd O_md6 /* @tlsgd relocation. */
500#define O_tlsie O_md7 /* @tlsie relocation. */
501#define O_tpoff9 O_md8 /* @tpoff9 relocation. */
502#define O_tpoff O_md9 /* @tpoff relocation. */
503#define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
504#define O_dtpoff O_md11 /* @dtpoff relocation. */
505#define O_last O_dtpoff
506
507/* Used to define a bracket as operand in tokens. */
508#define O_bracket O_md32
509
db18dbab
GM		 510/* Used to define a colon as an operand in tokens. */
511#define O_colon O_md31
512
513/* Used to define address types in nps400. */
514#define O_addrtype O_md30
515
886a2506
NC		 516/* Dummy relocation, to be sorted out. */
517#define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
518
519#define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
520
521/* A table to map the spelling of a relocation operand into an appropriate
522 bfd_reloc_code_real_type type. The table is assumed to be ordered such
523 that op-O_literal indexes into it. */
524#define ARC_RELOC_TABLE(op) \
525 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
526 ? (abort (), 0) \
527 : (int) (op) - (int) O_gotoff) ])
528
529#define DEF(NAME, RELOC, REQ) \
530 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
531
532static const struct arc_reloc_op_tag
533{
534 /* String to lookup. */
535 const char *name;
536 /* Size of the string. */
537 size_t length;
538 /* Which operator to use. */
539 operatorT op;
540 extended_bfd_reloc_code_real_type reloc;
541 /* Allows complex relocation expression like identifier@reloc +
542 const. */
543 unsigned int complex_expr : 1;
544}
545 arc_reloc_op[] =
6f4b1afc
CM		 546{
547 DEF (gotoff, BFD_RELOC_ARC_GOTOFF, 1),
548 DEF (gotpc, BFD_RELOC_ARC_GOTPC32, 0),
549 DEF (plt, BFD_RELOC_ARC_PLT32, 0),
550 DEF (sda, DUMMY_RELOC_ARC_ENTRY, 1),
551 DEF (pcl, BFD_RELOC_ARC_PC32, 1),
552 DEF (tlsgd, BFD_RELOC_ARC_TLS_GD_GOT, 0),
553 DEF (tlsie, BFD_RELOC_ARC_TLS_IE_GOT, 0),
554 DEF (tpoff9, BFD_RELOC_ARC_TLS_LE_S9, 0),
b125bd17 555 DEF (tpoff, BFD_RELOC_ARC_TLS_LE_32, 1),
6f4b1afc 556 DEF (dtpoff9, BFD_RELOC_ARC_TLS_DTPOFF_S9, 0),
05bbf016 557 DEF (dtpoff, BFD_RELOC_ARC_TLS_DTPOFF, 1),
6f4b1afc 558};
252b5132 559
886a2506
NC		 560static const int arc_num_reloc_op
561= sizeof (arc_reloc_op) / sizeof (*arc_reloc_op);
562
4670103e
CZ		 563/* Structure for relaxable instruction that have to be swapped with a
564 smaller alternative instruction. */
565struct arc_relaxable_ins
566{
567 /* Mnemonic that should be checked. */
568 const char *mnemonic_r;
569
570 /* Operands that should be checked.
571 Indexes of operands from operand array. */
572 enum rlx_operand_type operands[6];
573
574 /* Flags that should be checked. */
575 unsigned flag_classes[5];
576
577 /* Mnemonic (smaller) alternative to be used later for relaxation. */
578 const char *mnemonic_alt;
579
580 /* Index of operand that generic relaxation has to check. */
581 unsigned opcheckidx;
582
583 /* Base subtype index used. */
584 enum arc_rlx_types subtype;
585};
586
587#define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
588 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
589 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
590 (SIZE), \
591 (NEXT) } \
592
593#define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
594 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
595 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
596 (SIZE), \
597 (NEXT) } \
598
599
600/* ARC relaxation table. */
601const relax_typeS md_relax_table[] =
602{
603 /* Fake entry. */
604 {0, 0, 0, 0},
605
606 /* BL_S s13 ->
607 BL s25. */
db18dbab
GM		 608 RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL),
609 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
4670103e
CZ		 610
611 /* B_S s10 ->
612 B s25. */
db18dbab
GM		 613 RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B),
614 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
4670103e
CZ		 615
616 /* ADD_S c,b, u3 ->
617 ADD<.f> a,b,u6 ->
618 ADD<.f> a,b,limm. */
db18dbab
GM		 619 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6),
620 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM),
621 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 622
623 /* LD_S a, [b, u7] ->
624 LD<zz><.x><.aa><.di> a, [b, s9] ->
625 LD<zz><.x><.aa><.di> a, [b, limm] */
db18dbab
GM		 626 RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9),
627 RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM),
628 RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE),
4670103e
CZ		 629
630 /* MOV_S b, u8 ->
631 MOV<.f> b, s12 ->
632 MOV<.f> b, limm. */
db18dbab
GM		 633 RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12),
634 RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM),
635 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 636
637 /* SUB_S c, b, u3 ->
638 SUB<.f> a, b, u6 ->
639 SUB<.f> a, b, limm. */
db18dbab
GM		 640 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6),
641 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM),
642 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 643
644 /* MPY<.f> a, b, u6 ->
645 MPY<.f> a, b, limm. */
db18dbab
GM		 646 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM),
647 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 648
649 /* MOV<.f><.cc> b, u6 ->
650 MOV<.f><.cc> b, limm. */
db18dbab
GM		 651 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM),
652 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 653
654 /* ADD<.f><.cc> b, b, u6 ->
655 ADD<.f><.cc> b, b, limm. */
db18dbab
GM		 656 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM),
657 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 658};
659
660/* Order of this table's entries matters! */
661const struct arc_relaxable_ins arc_relaxable_insns[] =
662{
663 { "bl", { IMMEDIATE }, { 0 }, "bl_s", 0, ARC_RLX_BL_S },
664 { "b", { IMMEDIATE }, { 0 }, "b_s", 0, ARC_RLX_B_S },
665 { "add", { REGISTER, REGISTER_DUP, IMMEDIATE }, { 5, 1, 0 }, "add",
666 2, ARC_RLX_ADD_RRU6},
667 { "add", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "add_s", 2,
668 ARC_RLX_ADD_U3 },
669 { "add", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "add", 2,
670 ARC_RLX_ADD_U6 },
671 { "ld", { REGISTER_S, BRACKET, REGISTER_S, IMMEDIATE, BRACKET },
672 { 0 }, "ld_s", 3, ARC_RLX_LD_U7 },
673 { "ld", { REGISTER, BRACKET, REGISTER_NO_GP, IMMEDIATE, BRACKET },
674 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9 },
675 { "mov", { REGISTER_S, IMMEDIATE }, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8 },
676 { "mov", { REGISTER, IMMEDIATE }, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12 },
677 { "mov", { REGISTER, IMMEDIATE }, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6 },
678 { "sub", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "sub_s", 2,
679 ARC_RLX_SUB_U3 },
680 { "sub", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "sub", 2,
681 ARC_RLX_SUB_U6 },
682 { "mpy", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "mpy", 2,
683 ARC_RLX_MPY_U6 },
684};
685
686const unsigned arc_num_relaxable_ins = ARRAY_SIZE (arc_relaxable_insns);
687
886a2506
NC		 688/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
689symbolS * GOT_symbol = 0;
690
691/* Set to TRUE when we assemble instructions. */
692static bfd_boolean assembling_insn = FALSE;
693
53a346d8
CZ		 694/* List with attributes set explicitly. */
695static bfd_boolean attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
696
886a2506
NC		 697/* Functions implementation. */
698
b9b47ab7
AB		 699/* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
700 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
701 are no matching entries in ARC_OPCODE_HASH. */
da5be039 702
b9b47ab7 703static const struct arc_opcode_hash_entry *
da5be039
AB		 704arc_find_opcode (const char *name)
705{
706 const struct arc_opcode_hash_entry *entry;
da5be039
AB		 707
708 entry = hash_find (arc_opcode_hash, name);
b9b47ab7 709 return entry;
da5be039
AB		 710}
711
1328504b
AB		 712/* Initialise the iterator ITER. */
713
714static void
715arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator *iter)
716{
717 iter->index = 0;
718 iter->opcode = NULL;
719}
720
721/* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
722 calls to this function. Return NULL when all ARC_OPCODE entries have
723 been returned. */
724
725static const struct arc_opcode *
726arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry *entry,
727 struct arc_opcode_hash_entry_iterator *iter)
728{
729 if (iter->opcode == NULL && iter->index == 0)
730 {
731 gas_assert (entry->count > 0);
732 iter->opcode = entry->opcode[iter->index];
733 }
734 else if (iter->opcode != NULL)
735 {
736 const char *old_name = iter->opcode->name;
737
738 iter->opcode++;
fe779266
AB		 739 if (iter->opcode->name == NULL
740 || strcmp (old_name, iter->opcode->name) != 0)
1328504b
AB		 741 {
742 iter->index++;
743 if (iter->index == entry->count)
744 iter->opcode = NULL;
745 else
746 iter->opcode = entry->opcode[iter->index];
747 }
748 }
749
750 return iter->opcode;
751}
752
b99747ae
CZ		 753/* Insert an opcode into opcode hash structure. */
754
755static void
756arc_insert_opcode (const struct arc_opcode *opcode)
757{
758 const char *name, *retval;
759 struct arc_opcode_hash_entry *entry;
760 name = opcode->name;
761
762 entry = hash_find (arc_opcode_hash, name);
763 if (entry == NULL)
764 {
add39d23 765 entry = XNEW (struct arc_opcode_hash_entry);
b99747ae
CZ		 766 entry->count = 0;
767 entry->opcode = NULL;
768
769 retval = hash_insert (arc_opcode_hash, name, (void *) entry);
770 if (retval)
771 as_fatal (_("internal error: can't hash opcode '%s': %s"),
772 name, retval);
773 }
774
add39d23
TS		 775 entry->opcode = XRESIZEVEC (const struct arc_opcode *, entry->opcode,
776 entry->count + 1);
b99747ae
CZ		 777
778 if (entry->opcode == NULL)
779 as_fatal (_("Virtual memory exhausted"));
780
781 entry->opcode[entry->count] = opcode;
782 entry->count++;
783}
784
785
bdfe53e3
AB		 786/* Like md_number_to_chars but for middle-endian values. The 4-byte limm
787 value, is encoded as 'middle-endian' for a little-endian target. This
788 function is used for regular 4, 6, and 8 byte instructions as well. */
886a2506
NC		 789
790static void
bdfe53e3 791md_number_to_chars_midend (char *buf, unsigned long long val, int n)
886a2506 792{
bdfe53e3 793 switch (n)
886a2506 794 {
bdfe53e3
AB		 795 case 2:
796 md_number_to_chars (buf, val, n);
797 break;
798 case 6:
799 md_number_to_chars (buf, (val & 0xffff00000000) >> 32, 2);
800 md_number_to_chars_midend (buf + 2, (val & 0xffffffff), 4);
801 break;
802 case 4:
886a2506
NC		 803 md_number_to_chars (buf, (val & 0xffff0000) >> 16, 2);
804 md_number_to_chars (buf + 2, (val & 0xffff), 2);
bdfe53e3
AB		 805 break;
806 case 8:
807 md_number_to_chars_midend (buf, (val & 0xffffffff00000000) >> 32, 4);
808 md_number_to_chars_midend (buf + 4, (val & 0xffffffff), 4);
809 break;
810 default:
811 abort ();
886a2506 812 }
252b5132
RH		 813}
814
bb050a69
CZ		 815/* Check if a feature is allowed for a specific CPU. */
816
817static void
818arc_check_feature (void)
819{
820 unsigned i;
821
822 if (!selected_cpu.features
823 || !selected_cpu.name)
824 return;
53a346d8
CZ		 825
826 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
827 if ((selected_cpu.features & feature_list[i].feature)
828 && !(selected_cpu.flags & feature_list[i].cpus))
829 as_bad (_("invalid %s option for %s cpu"), feature_list[i].name,
830 selected_cpu.name);
831
832 for (i = 0; i < ARRAY_SIZE (conflict_list); i++)
833 if ((selected_cpu.features & conflict_list[i]) == conflict_list[i])
834 as_bad(_("conflicting ISA extension attributes."));
bb050a69
CZ		 835}
836
24740d83 837/* Select an appropriate entry from CPU_TYPES based on ARG and initialise
bb65a718
AB		 838 the relevant static global variables. Parameter SEL describes where
839 this selection originated from. */
24740d83
AB		 840
841static void
bb65a718 842arc_select_cpu (const char *arg, enum mach_selection_type sel)
24740d83 843{
24740d83
AB		 844 int i;
845
bb65a718
AB		 846 /* We should only set a default if we've not made a selection from some
847 other source. */
848 gas_assert (sel != MACH_SELECTION_FROM_DEFAULT
849 || mach_selection_mode == MACH_SELECTION_NONE);
850
bb050a69
CZ		 851 if ((mach_selection_mode == MACH_SELECTION_FROM_CPU_DIRECTIVE)
852 && (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE))
853 as_bad (_("Multiple .cpu directives found"));
854
bb65a718 855 /* Look for a matching entry in CPU_TYPES array. */
24740d83
AB		 856 for (i = 0; cpu_types[i].name; ++i)
857 {
858 if (!strcasecmp (cpu_types[i].name, arg))
859 {
bb65a718
AB		 860 /* If a previous selection was made on the command line, then we
861 allow later selections on the command line to override earlier
862 ones. However, a selection from a '.cpu NAME' directive must
863 match the command line selection, or we give a warning. */
864 if (mach_selection_mode == MACH_SELECTION_FROM_COMMAND_LINE)
865 {
866 gas_assert (sel == MACH_SELECTION_FROM_COMMAND_LINE
867 || sel == MACH_SELECTION_FROM_CPU_DIRECTIVE);
868 if (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE
869 && selected_cpu.mach != cpu_types[i].mach)
870 {
871 as_warn (_("Command-line value overrides \".cpu\" directive"));
bb65a718 872 }
bb050a69 873 return;
bb65a718
AB		 874 }
875
bb050a69
CZ		 876 /* Initialise static global data about selected machine type. */
877 selected_cpu.flags = cpu_types[i].flags;
878 selected_cpu.name = cpu_types[i].name;
a9752fdf 879 selected_cpu.features = cpu_types[i].features | cl_features;
bb050a69 880 selected_cpu.mach = cpu_types[i].mach;
53a346d8
CZ		 881 selected_cpu.eflags = ((selected_cpu.eflags & ~EF_ARC_MACH_MSK)
882 | cpu_types[i].eflags);
24740d83
AB		 883 break;
884 }
885 }
886
887 if (!cpu_types[i].name)
888 as_fatal (_("unknown architecture: %s\n"), arg);
bb050a69
CZ		 889
890 /* Check if set features are compatible with the chosen CPU. */
891 arc_check_feature ();
53a346d8 892
bb65a718 893 mach_selection_mode = sel;
24740d83
AB		 894}
895
886a2506
NC		 896/* Here ends all the ARCompact extension instruction assembling
897 stuff. */
252b5132 898
886a2506
NC		 899static void
900arc_extra_reloc (int r_type)
ea1562b3 901{
886a2506
NC		 902 char *sym_name, c;
903 symbolS *sym, *lab = NULL;
904
905 if (*input_line_pointer == '@')
906 input_line_pointer++;
907 c = get_symbol_name (&sym_name);
908 sym = symbol_find_or_make (sym_name);
909 restore_line_pointer (c);
910 if (c == ',' && r_type == BFD_RELOC_ARC_TLS_GD_LD)
911 {
912 ++input_line_pointer;
913 char *lab_name;
914 c = get_symbol_name (&lab_name);
915 lab = symbol_find_or_make (lab_name);
916 restore_line_pointer (c);
917 }
841fdfcd
CZ		 918
919 /* These relocations exist as a mechanism for the compiler to tell the
920 linker how to patch the code if the tls model is optimised. However,
921 the relocation itself does not require any space within the assembler
922 fragment, and so we pass a size of 0.
923
924 The lines that generate these relocations look like this:
925
926 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
927
928 The '.tls_gd_ld @.tdata' is processed first and generates the
929 additional relocation, while the 'bl __tls_get_addr@plt' is processed
930 second and generates the additional branch.
931
932 It is possible that the additional relocation generated by the
933 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
934 while the 'bl __tls_get_addr@plt' will be generated as the first thing
935 in the next fragment. This will be fine; both relocations will still
936 appear to be at the same address in the generated object file.
937 However, this only works as the additional relocation is generated
938 with size of 0 bytes. */
886a2506
NC		 939 fixS *fixP
940 = fix_new (frag_now, /* Which frag? */
941 frag_now_fix (), /* Where in that frag? */
841fdfcd 942 0, /* size: 1, 2, or 4 usually. */
886a2506
NC		 943 sym, /* X_add_symbol. */
944 0, /* X_add_number. */
945 FALSE, /* TRUE if PC-relative relocation. */
946 r_type /* Relocation type. */);
947 fixP->fx_subsy = lab;
948}
252b5132 949
886a2506
NC		 950static symbolS *
951arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED,
952 symbolS *symbolP, addressT size)
953{
954 addressT align = 0;
955 SKIP_WHITESPACE ();
252b5132 956
886a2506
NC		 957 if (*input_line_pointer == ',')
958 {
959 align = parse_align (1);
252b5132 960
886a2506
NC		 961 if (align == (addressT) -1)
962 return NULL;
963 }
964 else
965 {
966 if (size >= 8)
967 align = 3;
968 else if (size >= 4)
969 align = 2;
970 else if (size >= 2)
971 align = 1;
972 else
973 align = 0;
974 }
252b5132 975
886a2506
NC		 976 bss_alloc (symbolP, size, align);
977 S_CLEAR_EXTERNAL (symbolP);
ea1562b3 978
886a2506
NC		 979 return symbolP;
980}
ea1562b3 981
886a2506
NC		 982static void
983arc_lcomm (int ignore)
984{
985 symbolS *symbolP = s_comm_internal (ignore, arc_lcomm_internal);
ea1562b3 986
886a2506
NC		 987 if (symbolP)
988 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
989}
ea1562b3 990
886a2506 991/* Select the cpu we're assembling for. */
ea1562b3 992
886a2506
NC		 993static void
994arc_option (int ignore ATTRIBUTE_UNUSED)
252b5132 995{
886a2506
NC		 996 char c;
997 char *cpu;
bb65a718 998 const char *cpu_name;
252b5132 999
886a2506 1000 c = get_symbol_name (&cpu);
252b5132 1001
a9752fdf 1002 cpu_name = cpu;
bb65a718
AB		 1003 if ((!strcmp ("ARC600", cpu))
1004 || (!strcmp ("ARC601", cpu))
1005 || (!strcmp ("A6", cpu)))
1006 cpu_name = "arc600";
1007 else if ((!strcmp ("ARC700", cpu))
1008 || (!strcmp ("A7", cpu)))
1009 cpu_name = "arc700";
1010 else if (!strcmp ("EM", cpu))
1011 cpu_name = "arcem";
1012 else if (!strcmp ("HS", cpu))
1013 cpu_name = "archs";
1014 else if (!strcmp ("NPS400", cpu))
1015 cpu_name = "nps400";
886a2506 1016
a9752fdf 1017 arc_select_cpu (cpu_name, MACH_SELECTION_FROM_CPU_DIRECTIVE);
24b368f8 1018
24b368f8 1019 restore_line_pointer (c);
886a2506 1020 demand_empty_rest_of_line ();
ea1562b3 1021}
252b5132 1022
886a2506
NC		 1023/* Smartly print an expression. */
1024
ea1562b3 1025static void
886a2506 1026debug_exp (expressionS *t)
ea1562b3 1027{
886a2506
NC		 1028 const char *name ATTRIBUTE_UNUSED;
1029 const char *namemd ATTRIBUTE_UNUSED;
252b5132 1030
886a2506 1031 pr_debug ("debug_exp: ");
252b5132 1032
886a2506 1033 switch (t->X_op)
252b5132 1034 {
886a2506
NC		 1035 default: name = "unknown"; break;
1036 case O_illegal: name = "O_illegal"; break;
1037 case O_absent: name = "O_absent"; break;
1038 case O_constant: name = "O_constant"; break;
1039 case O_symbol: name = "O_symbol"; break;
1040 case O_symbol_rva: name = "O_symbol_rva"; break;
1041 case O_register: name = "O_register"; break;
1042 case O_big: name = "O_big"; break;
1043 case O_uminus: name = "O_uminus"; break;
1044 case O_bit_not: name = "O_bit_not"; break;
1045 case O_logical_not: name = "O_logical_not"; break;
1046 case O_multiply: name = "O_multiply"; break;
1047 case O_divide: name = "O_divide"; break;
1048 case O_modulus: name = "O_modulus"; break;
1049 case O_left_shift: name = "O_left_shift"; break;
1050 case O_right_shift: name = "O_right_shift"; break;
1051 case O_bit_inclusive_or: name = "O_bit_inclusive_or"; break;
1052 case O_bit_or_not: name = "O_bit_or_not"; break;
1053 case O_bit_exclusive_or: name = "O_bit_exclusive_or"; break;
1054 case O_bit_and: name = "O_bit_and"; break;
1055 case O_add: name = "O_add"; break;
1056 case O_subtract: name = "O_subtract"; break;
1057 case O_eq: name = "O_eq"; break;
1058 case O_ne: name = "O_ne"; break;
1059 case O_lt: name = "O_lt"; break;
1060 case O_le: name = "O_le"; break;
1061 case O_ge: name = "O_ge"; break;
1062 case O_gt: name = "O_gt"; break;
1063 case O_logical_and: name = "O_logical_and"; break;
1064 case O_logical_or: name = "O_logical_or"; break;
1065 case O_index: name = "O_index"; break;
1066 case O_bracket: name = "O_bracket"; break;
db18dbab
GM		 1067 case O_colon: name = "O_colon"; break;
1068 case O_addrtype: name = "O_addrtype"; break;
ea1562b3 1069 }
252b5132 1070
886a2506 1071 switch (t->X_md)
ea1562b3 1072 {
886a2506
NC		 1073 default: namemd = "unknown"; break;
1074 case O_gotoff: namemd = "O_gotoff"; break;
1075 case O_gotpc: namemd = "O_gotpc"; break;
1076 case O_plt: namemd = "O_plt"; break;
1077 case O_sda: namemd = "O_sda"; break;
1078 case O_pcl: namemd = "O_pcl"; break;
1079 case O_tlsgd: namemd = "O_tlsgd"; break;
1080 case O_tlsie: namemd = "O_tlsie"; break;
1081 case O_tpoff9: namemd = "O_tpoff9"; break;
1082 case O_tpoff: namemd = "O_tpoff"; break;
1083 case O_dtpoff9: namemd = "O_dtpoff9"; break;
1084 case O_dtpoff: namemd = "O_dtpoff"; break;
ea1562b3 1085 }
252b5132 1086
886a2506
NC		 1087 pr_debug ("%s (%s, %s, %d, %s)", name,
1088 (t->X_add_symbol) ? S_GET_NAME (t->X_add_symbol) : "--",
1089 (t->X_op_symbol) ? S_GET_NAME (t->X_op_symbol) : "--",
1090 (int) t->X_add_number,
1091 (t->X_md) ? namemd : "--");
1092 pr_debug ("\n");
1093 fflush (stderr);
1094}
252b5132 1095
886a2506
NC		 1096/* Parse the arguments to an opcode. */
1097
1098static int
1099tokenize_arguments (char *str,
1100 expressionS *tok,
1101 int ntok)
1102{
1103 char *old_input_line_pointer;
1104 bfd_boolean saw_comma = FALSE;
1105 bfd_boolean saw_arg = FALSE;
1106 int brk_lvl = 0;
1107 int num_args = 0;
886a2506
NC		 1108 int i;
1109 size_t len;
1110 const struct arc_reloc_op_tag *r;
1111 expressionS tmpE;
6f4b1afc 1112 char *reloc_name, c;
886a2506
NC		 1113
1114 memset (tok, 0, sizeof (*tok) * ntok);
1115
1116 /* Save and restore input_line_pointer around this function. */
1117 old_input_line_pointer = input_line_pointer;
1118 input_line_pointer = str;
ea1562b3 1119
886a2506 1120 while (*input_line_pointer)
ea1562b3
NC		 1121 {
1122 SKIP_WHITESPACE ();
886a2506 1123 switch (*input_line_pointer)
252b5132 1124 {
886a2506
NC		 1125 case '\0':
1126 goto fini;
1127
1128 case ',':
1129 input_line_pointer++;
1130 if (saw_comma || !saw_arg)
1131 goto err;
1132 saw_comma = TRUE;
1133 break;
252b5132 1134
886a2506
NC		 1135 case '}':
1136 case ']':
1137 ++input_line_pointer;
1138 --brk_lvl;
3b889a78 1139 if (!saw_arg || num_args == ntok)
886a2506
NC		 1140 goto err;
1141 tok->X_op = O_bracket;
1142 ++tok;
1143 ++num_args;
1144 break;
ea1562b3 1145
886a2506
NC		 1146 case '{':
1147 case '[':
1148 input_line_pointer++;
3b889a78 1149 if (brk_lvl || num_args == ntok)
886a2506
NC		 1150 goto err;
1151 ++brk_lvl;
1152 tok->X_op = O_bracket;
1153 ++tok;
1154 ++num_args;
1155 break;
1156
db18dbab
GM		 1157 case ':':
1158 input_line_pointer++;
1159 if (!saw_arg || num_args == ntok)
1160 goto err;
1161 tok->X_op = O_colon;
1162 saw_arg = FALSE;
1163 ++tok;
1164 ++num_args;
1165 break;
1166
886a2506
NC		 1167 case '@':
1168 /* We have labels, function names and relocations, all
1169 starting with @ symbol. Sort them out. */
3b889a78 1170 if ((saw_arg && !saw_comma) || num_args == ntok)
886a2506
NC		 1171 goto err;
1172
1173 /* Parse @label. */
1174 tok->X_op = O_symbol;
1175 tok->X_md = O_absent;
1176 expression (tok);
1177 if (*input_line_pointer != '@')
1178 goto normalsymbol; /* This is not a relocation. */
1179
6f4b1afc
CM		 1180 relocationsym:
1181
33eaf5de 1182 /* A relocation operand has the following form
886a2506
NC		 1183 @identifier@relocation_type. The identifier is already
1184 in tok! */
1185 if (tok->X_op != O_symbol)
ea1562b3 1186 {
886a2506
NC		 1187 as_bad (_("No valid label relocation operand"));
1188 goto err;
252b5132 1189 }
886a2506
NC		 1190
1191 /* Parse @relocation_type. */
6f4b1afc
CM		 1192 input_line_pointer++;
1193 c = get_symbol_name (&reloc_name);
1194 len = input_line_pointer - reloc_name;
1195 if (len == 0)
252b5132 1196 {
886a2506
NC		 1197 as_bad (_("No relocation operand"));
1198 goto err;
252b5132 1199 }
252b5132 1200
886a2506
NC		 1201 /* Go through known relocation and try to find a match. */
1202 r = &arc_reloc_op[0];
1203 for (i = arc_num_reloc_op - 1; i >= 0; i--, r++)
6f4b1afc
CM		 1204 if (len == r->length
1205 && memcmp (reloc_name, r->name, len) == 0)
886a2506 1206 break;
886a2506 1207 if (i < 0)
252b5132 1208 {
6f4b1afc 1209 as_bad (_("Unknown relocation operand: @%s"), reloc_name);
886a2506
NC		 1210 goto err;
1211 }
1212
6f4b1afc
CM		 1213 *input_line_pointer = c;
1214 SKIP_WHITESPACE_AFTER_NAME ();
886a2506
NC		 1215 /* Extra check for TLS: base. */
1216 if (*input_line_pointer == '@')
1217 {
1218 symbolS *base;
1219 if (tok->X_op_symbol != NULL
1220 || tok->X_op != O_symbol)
252b5132 1221 {
6f4b1afc
CM		 1222 as_bad (_("Unable to parse TLS base: %s"),
1223 input_line_pointer);
886a2506 1224 goto err;
252b5132 1225 }
886a2506
NC		 1226 input_line_pointer++;
1227 char *sym_name;
6f4b1afc 1228 c = get_symbol_name (&sym_name);
886a2506
NC		 1229 base = symbol_find_or_make (sym_name);
1230 tok->X_op = O_subtract;
1231 tok->X_op_symbol = base;
1232 restore_line_pointer (c);
6f4b1afc
CM		 1233 tmpE.X_add_number = 0;
1234 }
32348c58 1235 if ((*input_line_pointer != '+')
6f4b1afc
CM		 1236 && (*input_line_pointer != '-'))
1237 {
1238 tmpE.X_add_number = 0;
ea1562b3 1239 }
6f4b1afc
CM		 1240 else
1241 {
1242 /* Parse the constant of a complex relocation expression
1243 like @identifier@reloc +/- const. */
1244 if (! r->complex_expr)
1245 {
1246 as_bad (_("@%s is not a complex relocation."), r->name);
1247 goto err;
1248 }
1249 expression (&tmpE);
1250 if (tmpE.X_op != O_constant)
1251 {
1252 as_bad (_("Bad expression: @%s + %s."),
1253 r->name, input_line_pointer);
1254 goto err;
1255 }
1256 }
1257
1258 tok->X_md = r->op;
1259 tok->X_add_number = tmpE.X_add_number;
1e07b820 1260
886a2506 1261 debug_exp (tok);
ea1562b3 1262
886a2506
NC		 1263 saw_comma = FALSE;
1264 saw_arg = TRUE;
1265 tok++;
1266 num_args++;
1267 break;
252b5132 1268
886a2506
NC		 1269 case '%':
1270 /* Can be a register. */
1271 ++input_line_pointer;
1272 /* Fall through. */
1273 default:
252b5132 1274
3b889a78 1275 if ((saw_arg && !saw_comma) || num_args == ntok)
886a2506 1276 goto err;
252b5132 1277
886a2506 1278 tok->X_op = O_absent;
6f4b1afc 1279 tok->X_md = O_absent;
886a2506 1280 expression (tok);
252b5132 1281
6f4b1afc
CM		 1282 /* Legacy: There are cases when we have
1283 identifier@relocation_type, if it is the case parse the
1284 relocation type as well. */
1285 if (*input_line_pointer == '@')
1286 goto relocationsym;
1287
886a2506
NC		 1288 normalsymbol:
1289 debug_exp (tok);
252b5132 1290
3b889a78
AB		 1291 if (tok->X_op == O_illegal
1292 || tok->X_op == O_absent
1293 || num_args == ntok)
886a2506 1294 goto err;
252b5132 1295
886a2506
NC		 1296 saw_comma = FALSE;
1297 saw_arg = TRUE;
1298 tok++;
1299 num_args++;
1300 break;
1301 }
ea1562b3 1302 }
252b5132 1303
886a2506
NC		 1304 fini:
1305 if (saw_comma || brk_lvl)
1306 goto err;
1307 input_line_pointer = old_input_line_pointer;
252b5132 1308
886a2506 1309 return num_args;
252b5132 1310
886a2506
NC		 1311 err:
1312 if (brk_lvl)
1313 as_bad (_("Brackets in operand field incorrect"));
1314 else if (saw_comma)
1315 as_bad (_("extra comma"));
1316 else if (!saw_arg)
1317 as_bad (_("missing argument"));
1318 else
1319 as_bad (_("missing comma or colon"));
1320 input_line_pointer = old_input_line_pointer;
1321 return -1;
252b5132 1322}
ea1562b3 1323
886a2506
NC		 1324/* Parse the flags to a structure. */
1325
1326static int
1327tokenize_flags (const char *str,
1328 struct arc_flags flags[],
1329 int nflg)
252b5132 1330{
886a2506
NC		 1331 char *old_input_line_pointer;
1332 bfd_boolean saw_flg = FALSE;
1333 bfd_boolean saw_dot = FALSE;
1334 int num_flags = 0;
1335 size_t flgnamelen;
252b5132 1336
886a2506 1337 memset (flags, 0, sizeof (*flags) * nflg);
0d2bcfaf 1338
886a2506
NC		 1339 /* Save and restore input_line_pointer around this function. */
1340 old_input_line_pointer = input_line_pointer;
1341 input_line_pointer = (char *) str;
0d2bcfaf 1342
886a2506
NC		 1343 while (*input_line_pointer)
1344 {
1345 switch (*input_line_pointer)
1346 {
1347 case ' ':
1348 case '\0':
1349 goto fini;
1350
1351 case '.':
1352 input_line_pointer++;
1353 if (saw_dot)
1354 goto err;
1355 saw_dot = TRUE;
1356 saw_flg = FALSE;
1357 break;
ea1562b3 1358
886a2506
NC		 1359 default:
1360 if (saw_flg && !saw_dot)
1361 goto err;
0d2bcfaf 1362
886a2506
NC		 1363 if (num_flags >= nflg)
1364 goto err;
0d2bcfaf 1365
692166c2
AB		 1366 flgnamelen = strspn (input_line_pointer,
1367 "abcdefghijklmnopqrstuvwxyz0123456789");
83cda17b 1368 if (flgnamelen > MAX_FLAG_NAME_LENGTH)
886a2506 1369 goto err;
0d2bcfaf 1370
886a2506 1371 memcpy (flags->name, input_line_pointer, flgnamelen);
0d2bcfaf 1372
886a2506
NC		 1373 input_line_pointer += flgnamelen;
1374 flags++;
1375 saw_dot = FALSE;
1376 saw_flg = TRUE;
1377 num_flags++;
1378 break;
1e07b820 1379 }
0d2bcfaf
NC		 1380 }
1381
886a2506
NC		 1382 fini:
1383 input_line_pointer = old_input_line_pointer;
1384 return num_flags;
0d2bcfaf 1385
886a2506
NC		 1386 err:
1387 if (saw_dot)
1388 as_bad (_("extra dot"));
1389 else if (!saw_flg)
1390 as_bad (_("unrecognized flag"));
1391 else
1392 as_bad (_("failed to parse flags"));
1393 input_line_pointer = old_input_line_pointer;
1394 return -1;
1395}
0d2bcfaf 1396
4670103e 1397/* Apply the fixups in order. */
0d2bcfaf 1398
4670103e
CZ		 1399static void
1400apply_fixups (struct arc_insn *insn, fragS *fragP, int fix)
886a2506 1401{
4670103e 1402 int i;
0d2bcfaf 1403
4670103e 1404 for (i = 0; i < insn->nfixups; i++)
252b5132 1405 {
4670103e
CZ		 1406 struct arc_fixup *fixup = &insn->fixups[i];
1407 int size, pcrel, offset = 0;
0d2bcfaf 1408
4670103e
CZ		 1409 /* FIXME! the reloc size is wrong in the BFD file.
1410 When it is fixed please delete me. */
91fdca6f 1411 size = ((insn->len == 2) && !fixup->islong) ? 2 : 4;
0d2bcfaf 1412
4670103e 1413 if (fixup->islong)
91fdca6f 1414 offset = insn->len;
252b5132 1415
4670103e
CZ		 1416 /* Some fixups are only used internally, thus no howto. */
1417 if ((int) fixup->reloc == 0)
1418 as_fatal (_("Unhandled reloc type"));
886a2506 1419
4670103e
CZ		 1420 if ((int) fixup->reloc < 0)
1421 {
1422 /* FIXME! the reloc size is wrong in the BFD file.
1423 When it is fixed please enable me.
91fdca6f 1424 size = ((insn->len == 2 && !fixup->islong) ? 2 : 4; */
4670103e
CZ		 1425 pcrel = fixup->pcrel;
1426 }
1427 else
1428 {
1429 reloc_howto_type *reloc_howto =
1430 bfd_reloc_type_lookup (stdoutput,
1431 (bfd_reloc_code_real_type) fixup->reloc);
1432 gas_assert (reloc_howto);
0d2bcfaf 1433
4670103e
CZ		 1434 /* FIXME! the reloc size is wrong in the BFD file.
1435 When it is fixed please enable me.
1436 size = bfd_get_reloc_size (reloc_howto); */
1437 pcrel = reloc_howto->pc_relative;
1438 }
0d2bcfaf 1439
4670103e
CZ		 1440 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1441offset %d + %d\n",
1442 fragP->fr_file, fragP->fr_line,
1443 (fixup->reloc < 0) ? "Internal" :
1444 bfd_get_reloc_code_name (fixup->reloc),
1445 pcrel ? "Y" : "N",
1446 size, fix, offset);
1447 fix_new_exp (fragP, fix + offset,
1448 size, &fixup->exp, pcrel, fixup->reloc);
0d2bcfaf 1449
4670103e
CZ		 1450 /* Check for ZOLs, and update symbol info if any. */
1451 if (LP_INSN (insn->insn))
886a2506 1452 {
4670103e
CZ		 1453 gas_assert (fixup->exp.X_add_symbol);
1454 ARC_SET_FLAG (fixup->exp.X_add_symbol, ARC_FLAG_ZOL);
886a2506
NC		 1455 }
1456 }
252b5132
RH		 1457}
1458
4670103e 1459/* Actually output an instruction with its fixup. */
886a2506 1460
4670103e
CZ		 1461static void
1462emit_insn0 (struct arc_insn *insn, char *where, bfd_boolean relax)
252b5132 1463{
4670103e 1464 char *f = where;
91fdca6f 1465 size_t total_len;
252b5132 1466
bdfe53e3
AB		 1467 pr_debug ("Emit insn : 0x%llx\n", insn->insn);
1468 pr_debug ("\tLength : 0x%d\n", insn->len);
4670103e 1469 pr_debug ("\tLong imm: 0x%lx\n", insn->limm);
0d2bcfaf 1470
4670103e 1471 /* Write out the instruction. */
91fdca6f
GM		 1472 total_len = insn->len + (insn->has_limm ? 4 : 0);
1473 if (!relax)
1474 f = frag_more (total_len);
1475
1476 md_number_to_chars_midend(f, insn->insn, insn->len);
1477
1478 if (insn->has_limm)
1479 md_number_to_chars_midend (f + insn->len, insn->limm, 4);
1480 dwarf2_emit_insn (total_len);
252b5132 1481
4670103e
CZ		 1482 if (!relax)
1483 apply_fixups (insn, frag_now, (f - frag_now->fr_literal));
1484}
252b5132 1485
4670103e
CZ		 1486static void
1487emit_insn1 (struct arc_insn *insn)
1488{
1489 /* How frag_var's args are currently configured:
1490 - rs_machine_dependent, to dictate it's a relaxation frag.
1491 - FRAG_MAX_GROWTH, maximum size of instruction
1492 - 0, variable size that might grow...unused by generic relaxation.
1493 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1494 - s, opand expression.
1495 - 0, offset but it's unused.
1496 - 0, opcode but it's unused. */
1497 symbolS *s = make_expr_symbol (&insn->fixups[0].exp);
1498 frag_now->tc_frag_data.pcrel = insn->fixups[0].pcrel;
1499
1500 if (frag_room () < FRAG_MAX_GROWTH)
1501 {
1502 /* Handle differently when frag literal memory is exhausted.
1503 This is used because when there's not enough memory left in
1504 the current frag, a new frag is created and the information
1505 we put into frag_now->tc_frag_data is disregarded. */
252b5132 1506
4670103e
CZ		 1507 struct arc_relax_type relax_info_copy;
1508 relax_substateT subtype = frag_now->fr_subtype;
252b5132 1509
4670103e
CZ		 1510 memcpy (&relax_info_copy, &frag_now->tc_frag_data,
1511 sizeof (struct arc_relax_type));
0d2bcfaf 1512
4670103e
CZ		 1513 frag_wane (frag_now);
1514 frag_grow (FRAG_MAX_GROWTH);
0d2bcfaf 1515
4670103e
CZ		 1516 memcpy (&frag_now->tc_frag_data, &relax_info_copy,
1517 sizeof (struct arc_relax_type));
252b5132 1518
4670103e
CZ		 1519 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1520 subtype, s, 0, 0);
1521 }
1522 else
1523 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1524 frag_now->fr_subtype, s, 0, 0);
1525}
252b5132 1526
4670103e
CZ		 1527static void
1528emit_insn (struct arc_insn *insn)
252b5132 1529{
4670103e
CZ		 1530 if (insn->relax)
1531 emit_insn1 (insn);
252b5132 1532 else
4670103e 1533 emit_insn0 (insn, NULL, FALSE);
252b5132
RH		 1534}
1535
4670103e 1536/* Check whether a symbol involves a register. */
252b5132 1537
4670103e
CZ		 1538static bfd_boolean
1539contains_register (symbolS *sym)
252b5132 1540{
4670103e
CZ		 1541 if (sym)
1542 {
1543 expressionS *ex = symbol_get_value_expression (sym);
252b5132 1544
4670103e
CZ		 1545 return ((O_register == ex->X_op)
1546 && !contains_register (ex->X_add_symbol)
1547 && !contains_register (ex->X_op_symbol));
1548 }
1549
1550 return FALSE;
252b5132
RH		 1551}
1552
4670103e 1553/* Returns the register number within a symbol. */
252b5132 1554
4670103e
CZ		 1555static int
1556get_register (symbolS *sym)
252b5132 1557{
4670103e
CZ		 1558 if (!contains_register (sym))
1559 return -1;
0d2bcfaf 1560
4670103e
CZ		 1561 expressionS *ex = symbol_get_value_expression (sym);
1562 return regno (ex->X_add_number);
1563}
252b5132 1564
4670103e
CZ		 1565/* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1566 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
f17c130b 1567
4670103e
CZ		 1568static bfd_boolean
1569generic_reloc_p (extended_bfd_reloc_code_real_type reloc)
1570{
1571 if (!reloc)
1572 return FALSE;
886a2506 1573
4670103e
CZ		 1574 switch (reloc)
1575 {
1576 case BFD_RELOC_ARC_SDA_LDST:
1577 case BFD_RELOC_ARC_SDA_LDST1:
1578 case BFD_RELOC_ARC_SDA_LDST2:
1579 case BFD_RELOC_ARC_SDA16_LD:
1580 case BFD_RELOC_ARC_SDA16_LD1:
1581 case BFD_RELOC_ARC_SDA16_LD2:
1582 case BFD_RELOC_ARC_SDA16_ST2:
1583 case BFD_RELOC_ARC_SDA32_ME:
1584 return FALSE;
1585 default:
1586 return TRUE;
f17c130b 1587 }
252b5132
RH		 1588}
1589
4670103e 1590/* Allocates a tok entry. */
252b5132 1591
4670103e
CZ		 1592static int
1593allocate_tok (expressionS *tok, int ntok, int cidx)
252b5132 1594{
4670103e
CZ		 1595 if (ntok > MAX_INSN_ARGS - 2)
1596 return 0; /* No space left. */
252b5132 1597
4670103e 1598 if (cidx > ntok)
33eaf5de 1599 return 0; /* Incorrect args. */
252b5132 1600
4670103e 1601 memcpy (&tok[ntok+1], &tok[ntok], sizeof (*tok));
252b5132 1602
4670103e
CZ		 1603 if (cidx == ntok)
1604 return 1; /* Success. */
1605 return allocate_tok (tok, ntok - 1, cidx);
1606}
886a2506 1607
8ddf6b2a
CZ		 1608/* Check if an particular ARC feature is enabled. */
1609
1610static bfd_boolean
1611check_cpu_feature (insn_subclass_t sc)
1612{
53a346d8 1613 if (is_code_density_p (sc) && !(selected_cpu.features & CD))
8ddf6b2a
CZ		 1614 return FALSE;
1615
53a346d8 1616 if (is_spfp_p (sc) && !(selected_cpu.features & SPX))
8ddf6b2a
CZ		 1617 return FALSE;
1618
53a346d8 1619 if (is_dpfp_p (sc) && !(selected_cpu.features & DPX))
8ddf6b2a
CZ		 1620 return FALSE;
1621
53a346d8 1622 if (is_fpuda_p (sc) && !(selected_cpu.features & DPA))
bdd582db
GM		 1623 return FALSE;
1624
53a346d8 1625 if (is_nps400_p (sc) && !(selected_cpu.features & NPS400))
8ddf6b2a
CZ		 1626 return FALSE;
1627
1628 return TRUE;
1629}
1630
4eb6f892
AB		 1631/* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1632 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1633 array and returns TRUE if the flag operands all match, otherwise,
1634 returns FALSE, in which case the FIRST_PFLAG array may have been
1635 modified. */
1636
1637static bfd_boolean
1638parse_opcode_flags (const struct arc_opcode *opcode,
1639 int nflgs,
1640 struct arc_flags *first_pflag)
1641{
1642 int lnflg, i;
1643 const unsigned char *flgidx;
1644
1645 lnflg = nflgs;
1646 for (i = 0; i < nflgs; i++)
1647 first_pflag[i].flgp = NULL;
1648
1649 /* Check the flags. Iterate over the valid flag classes. */
1650 for (flgidx = opcode->flags; *flgidx; ++flgidx)
1651 {
1652 /* Get a valid flag class. */
1653 const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
1654 const unsigned *flgopridx;
1655 int cl_matches = 0;
1656 struct arc_flags *pflag = NULL;
1657
6ec7c1ae
CZ		 1658 /* Check if opcode has implicit flag classes. */
1659 if (cl_flags->flag_class & F_CLASS_IMPLICIT)
1660 continue;
1661
4eb6f892
AB		 1662 /* Check for extension conditional codes. */
1663 if (ext_condcode.arc_ext_condcode
1664 && cl_flags->flag_class & F_CLASS_EXTEND)
1665 {
1666 struct arc_flag_operand *pf = ext_condcode.arc_ext_condcode;
1667 while (pf->name)
1668 {
1669 pflag = first_pflag;
1670 for (i = 0; i < nflgs; i++, pflag++)
1671 {
1672 if (!strcmp (pf->name, pflag->name))
1673 {
1674 if (pflag->flgp != NULL)
1675 return FALSE;
1676 /* Found it. */
1677 cl_matches++;
1678 pflag->flgp = pf;
1679 lnflg--;
1680 break;
1681 }
1682 }
1683 pf++;
1684 }
1685 }
1686
1687 for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
1688 {
1689 const struct arc_flag_operand *flg_operand;
1690
1691 pflag = first_pflag;
1692 flg_operand = &arc_flag_operands[*flgopridx];
1693 for (i = 0; i < nflgs; i++, pflag++)
1694 {
1695 /* Match against the parsed flags. */
1696 if (!strcmp (flg_operand->name, pflag->name))
1697 {
1698 if (pflag->flgp != NULL)
1699 return FALSE;
1700 cl_matches++;
1701 pflag->flgp = flg_operand;
1702 lnflg--;
1703 break; /* goto next flag class and parsed flag. */
1704 }
1705 }
1706 }
1707
1708 if ((cl_flags->flag_class & F_CLASS_REQUIRED) && cl_matches == 0)
1709 return FALSE;
1710 if ((cl_flags->flag_class & F_CLASS_OPTIONAL) && cl_matches > 1)
1711 return FALSE;
1712 }
1713
1714 /* Did I check all the parsed flags? */
1715 return lnflg ? FALSE : TRUE;
1716}
1717
1718
4670103e
CZ		 1719/* Search forward through all variants of an opcode looking for a
1720 syntax match. */
886a2506 1721
4670103e 1722static const struct arc_opcode *
b9b47ab7 1723find_opcode_match (const struct arc_opcode_hash_entry *entry,
4670103e
CZ		 1724 expressionS *tok,
1725 int *pntok,
1726 struct arc_flags *first_pflag,
1727 int nflgs,
abe7c33b
CZ		 1728 int *pcpumatch,
1729 const char **errmsg)
4670103e 1730{
1328504b
AB		 1731 const struct arc_opcode *opcode;
1732 struct arc_opcode_hash_entry_iterator iter;
4670103e
CZ		 1733 int ntok = *pntok;
1734 int got_cpu_match = 0;
1735 expressionS bktok[MAX_INSN_ARGS];
1736 int bkntok;
1737 expressionS emptyE;
886a2506 1738
1328504b 1739 arc_opcode_hash_entry_iterator_init (&iter);
4670103e
CZ		 1740 memset (&emptyE, 0, sizeof (emptyE));
1741 memcpy (bktok, tok, MAX_INSN_ARGS * sizeof (*tok));
1742 bkntok = ntok;
a161fe53 1743
1328504b
AB		 1744 for (opcode = arc_opcode_hash_entry_iterator_next (entry, &iter);
1745 opcode != NULL;
1746 opcode = arc_opcode_hash_entry_iterator_next (entry, &iter))
252b5132 1747 {
4670103e 1748 const unsigned char *opidx;
4eb6f892 1749 int tokidx = 0;
4670103e 1750 const expressionS *t = &emptyE;
252b5132 1751
bdfe53e3 1752 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08llX ",
4670103e 1753 frag_now->fr_file, frag_now->fr_line, opcode->opcode);
886a2506 1754
4670103e
CZ		 1755 /* Don't match opcodes that don't exist on this
1756 architecture. */
bb65a718 1757 if (!(opcode->cpu & selected_cpu.flags))
4670103e 1758 goto match_failed;
886a2506 1759
8ddf6b2a 1760 if (!check_cpu_feature (opcode->subclass))
4670103e 1761 goto match_failed;
886a2506 1762
4670103e
CZ		 1763 got_cpu_match = 1;
1764 pr_debug ("cpu ");
886a2506 1765
4670103e
CZ		 1766 /* Check the operands. */
1767 for (opidx = opcode->operands; *opidx; ++opidx)
252b5132 1768 {
4670103e 1769 const struct arc_operand *operand = &arc_operands[*opidx];
252b5132 1770
4670103e 1771 /* Only take input from real operands. */
db18dbab 1772 if (ARC_OPERAND_IS_FAKE (operand))
4670103e 1773 continue;
252b5132 1774
4670103e
CZ		 1775 /* When we expect input, make sure we have it. */
1776 if (tokidx >= ntok)
1777 goto match_failed;
6f4b1afc 1778
4670103e
CZ		 1779 /* Match operand type with expression type. */
1780 switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK)
1781 {
db18dbab 1782 case ARC_OPERAND_ADDRTYPE:
b437d035 1783 {
abe7c33b 1784 *errmsg = NULL;
b437d035
AB		 1785
1786 /* Check to be an address type. */
1787 if (tok[tokidx].X_op != O_addrtype)
1788 goto match_failed;
1789
1790 /* All address type operands need to have an insert
1791 method in order to check that we have the correct
1792 address type. */
1793 gas_assert (operand->insert != NULL);
1794 (*operand->insert) (0, tok[tokidx].X_add_number,
abe7c33b
CZ		 1795 errmsg);
1796 if (*errmsg != NULL)
b437d035
AB		 1797 goto match_failed;
1798 }
db18dbab
GM		 1799 break;
1800
4670103e
CZ		 1801 case ARC_OPERAND_IR:
1802 /* Check to be a register. */
1803 if ((tok[tokidx].X_op != O_register
1804 || !is_ir_num (tok[tokidx].X_add_number))
1805 && !(operand->flags & ARC_OPERAND_IGNORE))
1806 goto match_failed;
1807
1808 /* If expect duplicate, make sure it is duplicate. */
1809 if (operand->flags & ARC_OPERAND_DUPLICATE)
1810 {
1811 /* Check for duplicate. */
1812 if (t->X_op != O_register
1813 || !is_ir_num (t->X_add_number)
1814 || (regno (t->X_add_number) !=
1815 regno (tok[tokidx].X_add_number)))
1816 goto match_failed;
1817 }
1818
1819 /* Special handling? */
1820 if (operand->insert)
1821 {
abe7c33b 1822 *errmsg = NULL;
4670103e
CZ		 1823 (*operand->insert)(0,
1824 regno (tok[tokidx].X_add_number),
abe7c33b
CZ		 1825 errmsg);
1826 if (*errmsg)
4670103e
CZ		 1827 {
1828 if (operand->flags & ARC_OPERAND_IGNORE)
1829 {
1830 /* Missing argument, create one. */
1831 if (!allocate_tok (tok, ntok - 1, tokidx))
1832 goto match_failed;
1833
1834 tok[tokidx].X_op = O_absent;
1835 ++ntok;
1836 }
1837 else
1838 goto match_failed;
1839 }
1840 }
1841
1842 t = &tok[tokidx];
1843 break;
1844
1845 case ARC_OPERAND_BRAKET:
1846 /* Check if bracket is also in opcode table as
1847 operand. */
1848 if (tok[tokidx].X_op != O_bracket)
1849 goto match_failed;
1850 break;
1851
db18dbab
GM		 1852 case ARC_OPERAND_COLON:
1853 /* Check if colon is also in opcode table as operand. */
1854 if (tok[tokidx].X_op != O_colon)
1855 goto match_failed;
1856 break;
1857
4670103e
CZ		 1858 case ARC_OPERAND_LIMM:
1859 case ARC_OPERAND_SIGNED:
1860 case ARC_OPERAND_UNSIGNED:
1861 switch (tok[tokidx].X_op)
1862 {
1863 case O_illegal:
1864 case O_absent:
1865 case O_register:
1866 goto match_failed;
1867
1868 case O_bracket:
1869 /* Got an (too) early bracket, check if it is an
1870 ignored operand. N.B. This procedure works only
1871 when bracket is the last operand! */
1872 if (!(operand->flags & ARC_OPERAND_IGNORE))
1873 goto match_failed;
1874 /* Insert the missing operand. */
1875 if (!allocate_tok (tok, ntok - 1, tokidx))
1876 goto match_failed;
1877
1878 tok[tokidx].X_op = O_absent;
1879 ++ntok;
1880 break;
1881
22b92fc4
AB		 1882 case O_symbol:
1883 {
1884 const char *p;
22b92fc4 1885 const struct arc_aux_reg *auxr;
22b92fc4 1886
c810e0b8 1887 if (opcode->insn_class != AUXREG)
22b92fc4
AB		 1888 goto de_fault;
1889 p = S_GET_NAME (tok[tokidx].X_add_symbol);
f36e33da
CZ		 1890
1891 auxr = hash_find (arc_aux_hash, p);
1892 if (auxr)
1893 {
1894 /* We modify the token array here, safe in the
1895 knowledge, that if this was the wrong
1896 choice then the original contents will be
1897 restored from BKTOK. */
1898 tok[tokidx].X_op = O_constant;
1899 tok[tokidx].X_add_number = auxr->address;
1900 ARC_SET_FLAG (tok[tokidx].X_add_symbol, ARC_FLAG_AUX);
1901 }
22b92fc4
AB		 1902
1903 if (tok[tokidx].X_op != O_constant)
1904 goto de_fault;
1905 }
1a0670f3 1906 /* Fall through. */
4670103e
CZ		 1907 case O_constant:
1908 /* Check the range. */
1909 if (operand->bits != 32
1910 && !(operand->flags & ARC_OPERAND_NCHK))
1911 {
1912 offsetT min, max, val;
1913 val = tok[tokidx].X_add_number;
1914
1915 if (operand->flags & ARC_OPERAND_SIGNED)
1916 {
1917 max = (1 << (operand->bits - 1)) - 1;
1918 min = -(1 << (operand->bits - 1));
1919 }
1920 else
1921 {
1922 max = (1 << operand->bits) - 1;
1923 min = 0;
1924 }
1925
1926 if (val < min || val > max)
1927 goto match_failed;
1928
33eaf5de 1929 /* Check alignments. */
4670103e
CZ		 1930 if ((operand->flags & ARC_OPERAND_ALIGNED32)
1931 && (val & 0x03))
1932 goto match_failed;
1933
1934 if ((operand->flags & ARC_OPERAND_ALIGNED16)
1935 && (val & 0x01))
1936 goto match_failed;
1937 }
1938 else if (operand->flags & ARC_OPERAND_NCHK)
1939 {
1940 if (operand->insert)
1941 {
abe7c33b 1942 *errmsg = NULL;
4670103e
CZ		 1943 (*operand->insert)(0,
1944 tok[tokidx].X_add_number,
abe7c33b
CZ		 1945 errmsg);
1946 if (*errmsg)
4670103e
CZ		 1947 goto match_failed;
1948 }
4eb6f892 1949 else if (!(operand->flags & ARC_OPERAND_IGNORE))
4670103e
CZ		 1950 goto match_failed;
1951 }
1952 break;
1953
1954 case O_subtract:
1955 /* Check if it is register range. */
1956 if ((tok[tokidx].X_add_number == 0)
1957 && contains_register (tok[tokidx].X_add_symbol)
1958 && contains_register (tok[tokidx].X_op_symbol))
1959 {
1960 int regs;
1961
1962 regs = get_register (tok[tokidx].X_add_symbol);
1963 regs <<= 16;
1964 regs |= get_register (tok[tokidx].X_op_symbol);
1965 if (operand->insert)
1966 {
abe7c33b 1967 *errmsg = NULL;
4670103e
CZ		 1968 (*operand->insert)(0,
1969 regs,
abe7c33b
CZ		 1970 errmsg);
1971 if (*errmsg)
4670103e
CZ		 1972 goto match_failed;
1973 }
1974 else
1975 goto match_failed;
1976 break;
1977 }
1a0670f3 1978 /* Fall through. */
4670103e 1979 default:
22b92fc4 1980 de_fault:
4670103e
CZ		 1981 if (operand->default_reloc == 0)
1982 goto match_failed; /* The operand needs relocation. */
1983
1984 /* Relocs requiring long immediate. FIXME! make it
1985 generic and move it to a function. */
1986 switch (tok[tokidx].X_md)
1987 {
1988 case O_gotoff:
1989 case O_gotpc:
1990 case O_pcl:
1991 case O_tpoff:
1992 case O_dtpoff:
1993 case O_tlsgd:
1994 case O_tlsie:
1995 if (!(operand->flags & ARC_OPERAND_LIMM))
1996 goto match_failed;
1a0670f3 1997 /* Fall through. */
4670103e
CZ		 1998 case O_absent:
1999 if (!generic_reloc_p (operand->default_reloc))
2000 goto match_failed;
2b804145 2001 break;
4670103e
CZ		 2002 default:
2003 break;
2004 }
2005 break;
2006 }
2007 /* If expect duplicate, make sure it is duplicate. */
2008 if (operand->flags & ARC_OPERAND_DUPLICATE)
2009 {
2010 if (t->X_op == O_illegal
2011 || t->X_op == O_absent
2012 || t->X_op == O_register
2013 || (t->X_add_number != tok[tokidx].X_add_number))
2014 goto match_failed;
2015 }
2016 t = &tok[tokidx];
2017 break;
2018
2019 default:
2020 /* Everything else should have been fake. */
2021 abort ();
2022 }
2023
2024 ++tokidx;
2025 }
2026 pr_debug ("opr ");
2027
1ae8ab47 2028 /* Setup ready for flag parsing. */
4eb6f892 2029 if (!parse_opcode_flags (opcode, nflgs, first_pflag))
4670103e
CZ		 2030 goto match_failed;
2031
2032 pr_debug ("flg");
2033 /* Possible match -- did we use all of our input? */
2034 if (tokidx == ntok)
2035 {
2036 *pntok = ntok;
2037 pr_debug ("\n");
2038 return opcode;
2039 }
2040
2041 match_failed:;
2042 pr_debug ("\n");
2043 /* Restore the original parameters. */
2044 memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok));
2045 ntok = bkntok;
2046 }
4670103e
CZ		 2047
2048 if (*pcpumatch)
2049 *pcpumatch = got_cpu_match;
2050
2051 return NULL;
2052}
2053
2054/* Swap operand tokens. */
2055
2056static void
2057swap_operand (expressionS *operand_array,
2058 unsigned source,
2059 unsigned destination)
2060{
2061 expressionS cpy_operand;
2062 expressionS *src_operand;
2063 expressionS *dst_operand;
2064 size_t size;
2065
2066 if (source == destination)
2067 return;
2068
2069 src_operand = &operand_array[source];
2070 dst_operand = &operand_array[destination];
2071 size = sizeof (expressionS);
2072
2073 /* Make copy of operand to swap with and swap. */
2074 memcpy (&cpy_operand, dst_operand, size);
2075 memcpy (dst_operand, src_operand, size);
2076 memcpy (src_operand, &cpy_operand, size);
2077}
2078
2079/* Check if *op matches *tok type.
2080 Returns FALSE if they don't match, TRUE if they match. */
2081
2082static bfd_boolean
2083pseudo_operand_match (const expressionS *tok,
2084 const struct arc_operand_operation *op)
2085{
2086 offsetT min, max, val;
2087 bfd_boolean ret;
2088 const struct arc_operand *operand_real = &arc_operands[op->operand_idx];
2089
2090 ret = FALSE;
2091 switch (tok->X_op)
2092 {
2093 case O_constant:
2094 if (operand_real->bits == 32 && (operand_real->flags & ARC_OPERAND_LIMM))
2095 ret = 1;
2096 else if (!(operand_real->flags & ARC_OPERAND_IR))
2097 {
2098 val = tok->X_add_number + op->count;
2099 if (operand_real->flags & ARC_OPERAND_SIGNED)
2100 {
2101 max = (1 << (operand_real->bits - 1)) - 1;
2102 min = -(1 << (operand_real->bits - 1));
2103 }
2104 else
2105 {
2106 max = (1 << operand_real->bits) - 1;
2107 min = 0;
2108 }
2109 if (min <= val && val <= max)
2110 ret = TRUE;
2111 }
6f4b1afc
CM		 2112 break;
2113
4670103e
CZ		 2114 case O_symbol:
2115 /* Handle all symbols as long immediates or signed 9. */
db18dbab
GM		 2116 if (operand_real->flags & ARC_OPERAND_LIMM
2117 || ((operand_real->flags & ARC_OPERAND_SIGNED)
2118 && operand_real->bits == 9))
4670103e 2119 ret = TRUE;
6f4b1afc
CM		 2120 break;
2121
4670103e
CZ		 2122 case O_register:
2123 if (operand_real->flags & ARC_OPERAND_IR)
2124 ret = TRUE;
2125 break;
2126
2127 case O_bracket:
2128 if (operand_real->flags & ARC_OPERAND_BRAKET)
2129 ret = TRUE;
6f4b1afc
CM		 2130 break;
2131
2132 default:
4670103e 2133 /* Unknown. */
6f4b1afc
CM		 2134 break;
2135 }
4670103e
CZ		 2136 return ret;
2137}
6f4b1afc 2138
4670103e
CZ		 2139/* Find pseudo instruction in array. */
2140
2141static const struct arc_pseudo_insn *
2142find_pseudo_insn (const char *opname,
2143 int ntok,
2144 const expressionS *tok)
2145{
2146 const struct arc_pseudo_insn *pseudo_insn = NULL;
2147 const struct arc_operand_operation *op;
2148 unsigned int i;
2149 int j;
2150
2151 for (i = 0; i < arc_num_pseudo_insn; ++i)
6f4b1afc 2152 {
4670103e
CZ		 2153 pseudo_insn = &arc_pseudo_insns[i];
2154 if (strcmp (pseudo_insn->mnemonic_p, opname) == 0)
2155 {
2156 op = pseudo_insn->operand;
2157 for (j = 0; j < ntok; ++j)
2158 if (!pseudo_operand_match (&tok[j], &op[j]))
2159 break;
2160
2161 /* Found the right instruction. */
2162 if (j == ntok)
2163 return pseudo_insn;
2164 }
6f4b1afc 2165 }
4670103e
CZ		 2166 return NULL;
2167}
252b5132 2168
4670103e 2169/* Assumes the expressionS *tok is of sufficient size. */
252b5132 2170
b9b47ab7 2171static const struct arc_opcode_hash_entry *
4670103e
CZ		 2172find_special_case_pseudo (const char *opname,
2173 int *ntok,
2174 expressionS *tok,
2175 int *nflgs,
2176 struct arc_flags *pflags)
2177{
2178 const struct arc_pseudo_insn *pseudo_insn = NULL;
2179 const struct arc_operand_operation *operand_pseudo;
2180 const struct arc_operand *operand_real;
2181 unsigned i;
2182 char construct_operand[MAX_CONSTR_STR];
886a2506 2183
4670103e
CZ		 2184 /* Find whether opname is in pseudo instruction array. */
2185 pseudo_insn = find_pseudo_insn (opname, *ntok, tok);
2186
2187 if (pseudo_insn == NULL)
2188 return NULL;
2189
2190 /* Handle flag, Limited to one flag at the moment. */
2191 if (pseudo_insn->flag_r != NULL)
2192 *nflgs += tokenize_flags (pseudo_insn->flag_r, &pflags[*nflgs],
2193 MAX_INSN_FLGS - *nflgs);
2194
2195 /* Handle operand operations. */
2196 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
252b5132 2197 {
4670103e
CZ		 2198 operand_pseudo = &pseudo_insn->operand[i];
2199 operand_real = &arc_operands[operand_pseudo->operand_idx];
886a2506 2200
db18dbab
GM		 2201 if (operand_real->flags & ARC_OPERAND_BRAKET
2202 && !operand_pseudo->needs_insert)
4670103e 2203 continue;
b125bd17 2204
4670103e
CZ		 2205 /* Has to be inserted (i.e. this token does not exist yet). */
2206 if (operand_pseudo->needs_insert)
2207 {
2208 if (operand_real->flags & ARC_OPERAND_BRAKET)
2209 {
2210 tok[i].X_op = O_bracket;
2211 ++(*ntok);
2212 continue;
2213 }
b125bd17 2214
4670103e
CZ		 2215 /* Check if operand is a register or constant and handle it
2216 by type. */
2217 if (operand_real->flags & ARC_OPERAND_IR)
2218 snprintf (construct_operand, MAX_CONSTR_STR, "r%d",
2219 operand_pseudo->count);
2220 else
2221 snprintf (construct_operand, MAX_CONSTR_STR, "%d",
2222 operand_pseudo->count);
886a2506 2223
4670103e
CZ		 2224 tokenize_arguments (construct_operand, &tok[i], 1);
2225 ++(*ntok);
2226 }
2227
2228 else if (operand_pseudo->count)
2229 {
2230 /* Operand number has to be adjusted accordingly (by operand
2231 type). */
2232 switch (tok[i].X_op)
2233 {
2234 case O_constant:
2235 tok[i].X_add_number += operand_pseudo->count;
2236 break;
2237
2238 case O_symbol:
2239 break;
2240
2241 default:
2242 /* Ignored. */
2243 break;
2244 }
2245 }
2246 }
2247
2248 /* Swap operands if necessary. Only supports one swap at the
2249 moment. */
2250 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
2251 {
2252 operand_pseudo = &pseudo_insn->operand[i];
2253
2254 if (operand_pseudo->swap_operand_idx == i)
2255 continue;
2256
2257 swap_operand (tok, i, operand_pseudo->swap_operand_idx);
2258
2259 /* Prevent a swap back later by breaking out. */
2260 break;
2261 }
2262
da5be039 2263 return arc_find_opcode (pseudo_insn->mnemonic_r);
4670103e
CZ		 2264}
2265
b9b47ab7 2266static const struct arc_opcode_hash_entry *
4670103e
CZ		 2267find_special_case_flag (const char *opname,
2268 int *nflgs,
2269 struct arc_flags *pflags)
2270{
2271 unsigned int i;
2272 const char *flagnm;
2273 unsigned flag_idx, flag_arr_idx;
2274 size_t flaglen, oplen;
2275 const struct arc_flag_special *arc_flag_special_opcode;
b9b47ab7 2276 const struct arc_opcode_hash_entry *entry;
4670103e
CZ		 2277
2278 /* Search for special case instruction. */
2279 for (i = 0; i < arc_num_flag_special; i++)
2280 {
2281 arc_flag_special_opcode = &arc_flag_special_cases[i];
2282 oplen = strlen (arc_flag_special_opcode->name);
2283
2284 if (strncmp (opname, arc_flag_special_opcode->name, oplen) != 0)
2285 continue;
2286
2287 /* Found a potential special case instruction, now test for
2288 flags. */
2289 for (flag_arr_idx = 0;; ++flag_arr_idx)
2290 {
2291 flag_idx = arc_flag_special_opcode->flags[flag_arr_idx];
2292 if (flag_idx == 0)
2293 break; /* End of array, nothing found. */
886a2506 2294
4670103e
CZ		 2295 flagnm = arc_flag_operands[flag_idx].name;
2296 flaglen = strlen (flagnm);
2297 if (strcmp (opname + oplen, flagnm) == 0)
2298 {
b9b47ab7 2299 entry = arc_find_opcode (arc_flag_special_opcode->name);
886a2506 2300
4670103e
CZ		 2301 if (*nflgs + 1 > MAX_INSN_FLGS)
2302 break;
2303 memcpy (pflags[*nflgs].name, flagnm, flaglen);
2304 pflags[*nflgs].name[flaglen] = '\0';
2305 (*nflgs)++;
b9b47ab7 2306 return entry;
4670103e
CZ		 2307 }
2308 }
2309 }
2310 return NULL;
2311}
886a2506 2312
4670103e 2313/* Used to find special case opcode. */
886a2506 2314
b9b47ab7 2315static const struct arc_opcode_hash_entry *
4670103e
CZ		 2316find_special_case (const char *opname,
2317 int *nflgs,
2318 struct arc_flags *pflags,
2319 expressionS *tok,
2320 int *ntok)
2321{
b9b47ab7 2322 const struct arc_opcode_hash_entry *entry;
886a2506 2323
b9b47ab7 2324 entry = find_special_case_pseudo (opname, ntok, tok, nflgs, pflags);
886a2506 2325
b9b47ab7
AB		 2326 if (entry == NULL)
2327 entry = find_special_case_flag (opname, nflgs, pflags);
886a2506 2328
b9b47ab7 2329 return entry;
4670103e 2330}
886a2506 2331
53a346d8
CZ		 2332/* Autodetect cpu attribute list. */
2333
2334static void
2335autodetect_attributes (const struct arc_opcode *opcode,
2336 const expressionS *tok,
2337 int ntok)
2338{
2339 unsigned i;
2340 struct mpy_type
2341 {
2342 unsigned feature;
2343 unsigned encoding;
2344 } mpy_list[] = {{ MPY1E, 1 }, { MPY6E, 6 }, { MPY7E, 7 }, { MPY8E, 8 },
2345 { MPY9E, 9 }};
2346
2347 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
2348 if (opcode->subclass == feature_list[i].feature)
2349 selected_cpu.features |= feature_list[i].feature;
2350
2351 for (i = 0; i < ARRAY_SIZE (mpy_list); i++)
2352 if (opcode->subclass == mpy_list[i].feature)
2353 mpy_option = mpy_list[i].encoding;
2354
2355 for (i = 0; i < (unsigned) ntok; i++)
2356 {
2357 switch (tok[i].X_md)
2358 {
2359 case O_gotoff:
2360 case O_gotpc:
2361 case O_plt:
2362 pic_option = 2;
2363 break;
2364 case O_sda:
2365 sda_option = 2;
2366 break;
2367 case O_tlsgd:
2368 case O_tlsie:
2369 case O_tpoff9:
2370 case O_tpoff:
2371 case O_dtpoff9:
2372 case O_dtpoff:
2373 tls_option = 1;
2374 break;
2375 default:
2376 break;
2377 }
2378 }
2379}
2380
2381/* Given an opcode name, pre-tockenized set of argumenst and the
4670103e 2382 opcode flags, take it all the way through emission. */
886a2506 2383
4670103e
CZ		 2384static void
2385assemble_tokens (const char *opname,
2386 expressionS *tok,
2387 int ntok,
2388 struct arc_flags *pflags,
2389 int nflgs)
2390{
2391 bfd_boolean found_something = FALSE;
b9b47ab7 2392 const struct arc_opcode_hash_entry *entry;
4670103e 2393 int cpumatch = 1;
abe7c33b 2394 const char *errmsg = NULL;
886a2506 2395
4670103e 2396 /* Search opcodes. */
b9b47ab7 2397 entry = arc_find_opcode (opname);
886a2506 2398
4670103e 2399 /* Couldn't find opcode conventional way, try special cases. */
b9b47ab7
AB		 2400 if (entry == NULL)
2401 entry = find_special_case (opname, &nflgs, pflags, tok, &ntok);
886a2506 2402
b9b47ab7 2403 if (entry != NULL)
4670103e 2404 {
b9b47ab7
AB		 2405 const struct arc_opcode *opcode;
2406
1328504b
AB		 2407 pr_debug ("%s:%d: assemble_tokens: %s\n",
2408 frag_now->fr_file, frag_now->fr_line, opname);
4670103e 2409 found_something = TRUE;
b9b47ab7 2410 opcode = find_opcode_match (entry, tok, &ntok, pflags,
abe7c33b 2411 nflgs, &cpumatch, &errmsg);
b9b47ab7 2412 if (opcode != NULL)
4670103e
CZ		 2413 {
2414 struct arc_insn insn;
b9b47ab7 2415
53a346d8 2416 autodetect_attributes (opcode, tok, ntok);
4670103e
CZ		 2417 assemble_insn (opcode, tok, ntok, pflags, nflgs, &insn);
2418 emit_insn (&insn);
2419 return;
2420 }
2421 }
886a2506 2422
4670103e
CZ		 2423 if (found_something)
2424 {
2425 if (cpumatch)
abe7c33b
CZ		 2426 if (errmsg)
2427 as_bad (_("%s for instruction '%s'"), errmsg, opname);
2428 else
2429 as_bad (_("inappropriate arguments for opcode '%s'"), opname);
4670103e
CZ		 2430 else
2431 as_bad (_("opcode '%s' not supported for target %s"), opname,
bb65a718 2432 selected_cpu.name);
4670103e
CZ		 2433 }
2434 else
2435 as_bad (_("unknown opcode '%s'"), opname);
886a2506
NC		 2436}
2437
4670103e 2438/* The public interface to the instruction assembler. */
886a2506 2439
4670103e
CZ		 2440void
2441md_assemble (char *str)
886a2506 2442{
4670103e
CZ		 2443 char *opname;
2444 expressionS tok[MAX_INSN_ARGS];
2445 int ntok, nflg;
2446 size_t opnamelen;
2447 struct arc_flags flags[MAX_INSN_FLGS];
886a2506 2448
4670103e
CZ		 2449 /* Split off the opcode. */
2450 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_0123468");
29a2809e 2451 opname = xmemdup0 (str, opnamelen);
886a2506 2452
33eaf5de 2453 /* Signalize we are assembling the instructions. */
4670103e 2454 assembling_insn = TRUE;
886a2506 2455
4670103e
CZ		 2456 /* Tokenize the flags. */
2457 if ((nflg = tokenize_flags (str + opnamelen, flags, MAX_INSN_FLGS)) == -1)
2458 {
2459 as_bad (_("syntax error"));
2460 return;
2461 }
886a2506 2462
4670103e
CZ		 2463 /* Scan up to the end of the mnemonic which must end in space or end
2464 of string. */
2465 str += opnamelen;
2466 for (; *str != '\0'; str++)
2467 if (*str == ' ')
2468 break;
886a2506 2469
4670103e
CZ		 2470 /* Tokenize the rest of the line. */
2471 if ((ntok = tokenize_arguments (str, tok, MAX_INSN_ARGS)) < 0)
886a2506 2472 {
4670103e
CZ		 2473 as_bad (_("syntax error"));
2474 return;
252b5132
RH		 2475 }
2476
4670103e
CZ		 2477 /* Finish it off. */
2478 assemble_tokens (opname, tok, ntok, flags, nflg);
2479 assembling_insn = FALSE;
2480}
2481
2482/* Callback to insert a register into the hash table. */
2483
2484static void
f86f5863 2485declare_register (const char *name, int number)
4670103e
CZ		 2486{
2487 const char *err;
2488 symbolS *regS = symbol_create (name, reg_section,
2489 number, &zero_address_frag);
2490
2491 err = hash_insert (arc_reg_hash, S_GET_NAME (regS), (void *) regS);
2492 if (err)
e6ba1cba 2493 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
4670103e
CZ		 2494 name, err);
2495}
252b5132 2496
4670103e 2497/* Construct symbols for each of the general registers. */
252b5132 2498
4670103e
CZ		 2499static void
2500declare_register_set (void)
2501{
2502 int i;
2503 for (i = 0; i < 64; ++i)
886a2506 2504 {
4670103e
CZ		 2505 char name[7];
2506
2507 sprintf (name, "r%d", i);
2508 declare_register (name, i);
2509 if ((i & 0x01) == 0)
886a2506 2510 {
4670103e
CZ		 2511 sprintf (name, "r%dr%d", i, i+1);
2512 declare_register (name, i);
886a2506
NC		 2513 }
2514 }
252b5132 2515}
ea1562b3 2516
db18dbab
GM		 2517/* Construct a symbol for an address type. */
2518
2519static void
2520declare_addrtype (const char *name, int number)
2521{
2522 const char *err;
2523 symbolS *addrtypeS = symbol_create (name, undefined_section,
2524 number, &zero_address_frag);
2525
2526 err = hash_insert (arc_addrtype_hash, S_GET_NAME (addrtypeS),
2527 (void *) addrtypeS);
2528 if (err)
2529 as_fatal (_("Inserting \"%s\" into address type table failed: %s"),
2530 name, err);
2531}
2532
4670103e
CZ		 2533/* Port-specific assembler initialization. This function is called
2534 once, at assembler startup time. */
ea1562b3
NC		 2535
2536void
4670103e 2537md_begin (void)
ea1562b3 2538{
b99747ae 2539 const struct arc_opcode *opcode = arc_opcodes;
886a2506 2540
bb65a718
AB		 2541 if (mach_selection_mode == MACH_SELECTION_NONE)
2542 arc_select_cpu (TARGET_WITH_CPU, MACH_SELECTION_FROM_DEFAULT);
24740d83 2543
4670103e
CZ		 2544 /* The endianness can be chosen "at the factory". */
2545 target_big_endian = byte_order == BIG_ENDIAN;
886a2506 2546
bb65a718 2547 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
4670103e
CZ		 2548 as_warn (_("could not set architecture and machine"));
2549
2550 /* Set elf header flags. */
bb65a718 2551 bfd_set_private_flags (stdoutput, selected_cpu.eflags);
4670103e
CZ		 2552
2553 /* Set up a hash table for the instructions. */
2554 arc_opcode_hash = hash_new ();
2555 if (arc_opcode_hash == NULL)
2556 as_fatal (_("Virtual memory exhausted"));
2557
2558 /* Initialize the hash table with the insns. */
b99747ae 2559 do
ea1562b3 2560 {
b99747ae 2561 const char *name = opcode->name;
da5be039 2562
b99747ae 2563 arc_insert_opcode (opcode);
4670103e 2564
b99747ae
CZ		 2565 while (++opcode && opcode->name
2566 && (opcode->name == name
2567 || !strcmp (opcode->name, name)))
4670103e 2568 continue;
b99747ae 2569 }while (opcode->name);
4670103e
CZ		 2570
2571 /* Register declaration. */
2572 arc_reg_hash = hash_new ();
2573 if (arc_reg_hash == NULL)
2574 as_fatal (_("Virtual memory exhausted"));
2575
2576 declare_register_set ();
2577 declare_register ("gp", 26);
2578 declare_register ("fp", 27);
2579 declare_register ("sp", 28);
2580 declare_register ("ilink", 29);
2581 declare_register ("ilink1", 29);
2582 declare_register ("ilink2", 30);
2583 declare_register ("blink", 31);
2584
87789e08
CZ		 2585 /* XY memory registers. */
2586 declare_register ("x0_u0", 32);
2587 declare_register ("x0_u1", 33);
2588 declare_register ("x1_u0", 34);
2589 declare_register ("x1_u1", 35);
2590 declare_register ("x2_u0", 36);
2591 declare_register ("x2_u1", 37);
2592 declare_register ("x3_u0", 38);
2593 declare_register ("x3_u1", 39);
2594 declare_register ("y0_u0", 40);
2595 declare_register ("y0_u1", 41);
2596 declare_register ("y1_u0", 42);
2597 declare_register ("y1_u1", 43);
2598 declare_register ("y2_u0", 44);
2599 declare_register ("y2_u1", 45);
2600 declare_register ("y3_u0", 46);
2601 declare_register ("y3_u1", 47);
2602 declare_register ("x0_nu", 48);
2603 declare_register ("x1_nu", 49);
2604 declare_register ("x2_nu", 50);
2605 declare_register ("x3_nu", 51);
2606 declare_register ("y0_nu", 52);
2607 declare_register ("y1_nu", 53);
2608 declare_register ("y2_nu", 54);
2609 declare_register ("y3_nu", 55);
2610
4670103e
CZ		 2611 declare_register ("mlo", 57);
2612 declare_register ("mmid", 58);
2613 declare_register ("mhi", 59);
2614
2615 declare_register ("acc1", 56);
2616 declare_register ("acc2", 57);
2617
2618 declare_register ("lp_count", 60);
2619 declare_register ("pcl", 63);
2620
2621 /* Initialize the last instructions. */
2622 memset (&arc_last_insns[0], 0, sizeof (arc_last_insns));
f36e33da
CZ		 2623
2624 /* Aux register declaration. */
2625 arc_aux_hash = hash_new ();
2626 if (arc_aux_hash == NULL)
2627 as_fatal (_("Virtual memory exhausted"));
2628
2629 const struct arc_aux_reg *auxr = &arc_aux_regs[0];
2630 unsigned int i;
2631 for (i = 0; i < arc_num_aux_regs; i++, auxr++)
2632 {
2633 const char *retval;
2634
bb65a718 2635 if (!(auxr->cpu & selected_cpu.flags))
f36e33da
CZ		 2636 continue;
2637
2638 if ((auxr->subclass != NONE)
2639 && !check_cpu_feature (auxr->subclass))
2640 continue;
2641
2642 retval = hash_insert (arc_aux_hash, auxr->name, (void *) auxr);
2643 if (retval)
2644 as_fatal (_("internal error: can't hash aux register '%s': %s"),
2645 auxr->name, retval);
2646 }
db18dbab
GM		 2647
2648 /* Address type declaration. */
2649 arc_addrtype_hash = hash_new ();
2650 if (arc_addrtype_hash == NULL)
2651 as_fatal (_("Virtual memory exhausted"));
2652
2653 declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD);
2654 declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID);
2655 declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD);
2656 declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD);
2657 declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD);
2658 declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM);
2659 declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA);
2660 declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD);
2661 declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD);
2662 declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD);
2663 declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID);
2664 declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD);
2665 declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM);
2666 declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD);
2667 declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA);
2668 declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD);
886a2506 2669}
ea1562b3 2670
4670103e
CZ		 2671/* Write a value out to the object file, using the appropriate
2672 endianness. */
ea1562b3 2673
4670103e
CZ		 2674void
2675md_number_to_chars (char *buf,
2676 valueT val,
2677 int n)
886a2506 2678{
4670103e
CZ		 2679 if (target_big_endian)
2680 number_to_chars_bigendian (buf, val, n);
2681 else
2682 number_to_chars_littleendian (buf, val, n);
886a2506 2683}
ea1562b3 2684
4670103e 2685/* Round up a section size to the appropriate boundary. */
ea1562b3 2686
4670103e
CZ		 2687valueT
2688md_section_align (segT segment,
2689 valueT size)
886a2506 2690{
4670103e
CZ		 2691 int align = bfd_get_section_alignment (stdoutput, segment);
2692
2693 return ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
886a2506 2694}
ea1562b3 2695
4670103e
CZ		 2696/* The location from which a PC relative jump should be calculated,
2697 given a PC relative reloc. */
ea1562b3 2698
4670103e
CZ		 2699long
2700md_pcrel_from_section (fixS *fixP,
2701 segT sec)
886a2506 2702{
4670103e 2703 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
ea1562b3 2704
4670103e 2705 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP->fx_offset);
ea1562b3 2706
4670103e
CZ		 2707 if (fixP->fx_addsy != (symbolS *) NULL
2708 && (!S_IS_DEFINED (fixP->fx_addsy)
2709 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
2710 {
2711 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP->fx_addsy));
ea1562b3 2712
4670103e
CZ		 2713 /* The symbol is undefined (or is defined but not in this section).
2714 Let the linker figure it out. */
2715 return 0;
2716 }
2717
2718 if ((int) fixP->fx_r_type < 0)
886a2506 2719 {
4670103e
CZ		 2720 /* These are the "internal" relocations. Align them to
2721 32 bit boundary (PCL), for the moment. */
2722 base &= ~3;
886a2506 2723 }
4670103e
CZ		 2724 else
2725 {
2726 switch (fixP->fx_r_type)
2727 {
2728 case BFD_RELOC_ARC_PC32:
2729 /* The hardware calculates relative to the start of the
2730 insn, but this relocation is relative to location of the
2731 LIMM, compensate. The base always needs to be
2b0f3761 2732 subtracted by 4 as we do not support this type of PCrel
4670103e
CZ		 2733 relocation for short instructions. */
2734 base -= 4;
2735 /* Fall through. */
2736 case BFD_RELOC_ARC_PLT32:
2737 case BFD_RELOC_ARC_S25H_PCREL_PLT:
2738 case BFD_RELOC_ARC_S21H_PCREL_PLT:
2739 case BFD_RELOC_ARC_S25W_PCREL_PLT:
2740 case BFD_RELOC_ARC_S21W_PCREL_PLT:
2741
2742 case BFD_RELOC_ARC_S21H_PCREL:
2743 case BFD_RELOC_ARC_S25H_PCREL:
2744 case BFD_RELOC_ARC_S13_PCREL:
2745 case BFD_RELOC_ARC_S21W_PCREL:
2746 case BFD_RELOC_ARC_S25W_PCREL:
2747 base &= ~3;
2748 break;
2749 default:
2750 as_bad_where (fixP->fx_file, fixP->fx_line,
2751 _("unhandled reloc %s in md_pcrel_from_section"),
2752 bfd_get_reloc_code_name (fixP->fx_r_type));
2753 break;
2754 }
2755 }
2756
9e32d9ae
AB		 2757 pr_debug ("pcrel from %"BFD_VMA_FMT"x + %lx = %"BFD_VMA_FMT"x, "
2758 "symbol: %s (%"BFD_VMA_FMT"x)\n",
4670103e
CZ		 2759 fixP->fx_frag->fr_address, fixP->fx_where, base,
2760 fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "(null)",
2761 fixP->fx_addsy ? S_GET_VALUE (fixP->fx_addsy) : 0);
2762
2763 return base;
886a2506 2764}
ea1562b3 2765
33eaf5de 2766/* Given a BFD relocation find the corresponding operand. */
ea1562b3 2767
4670103e
CZ		 2768static const struct arc_operand *
2769find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc)
2770{
2771 unsigned i;
ea1562b3 2772
4670103e
CZ		 2773 for (i = 0; i < arc_num_operands; i++)
2774 if (arc_operands[i].default_reloc == reloc)
2775 return &arc_operands[i];
2776 return NULL;
2777}
ea1562b3 2778
4670103e 2779/* Insert an operand value into an instruction. */
ea1562b3 2780
bdfe53e3
AB		 2781static unsigned long long
2782insert_operand (unsigned long long insn,
4670103e 2783 const struct arc_operand *operand,
bdfe53e3 2784 long long val,
3b4dbbbf 2785 const char *file,
4670103e 2786 unsigned line)
886a2506 2787{
4670103e 2788 offsetT min = 0, max = 0;
ea1562b3 2789
4670103e
CZ		 2790 if (operand->bits != 32
2791 && !(operand->flags & ARC_OPERAND_NCHK)
2792 && !(operand->flags & ARC_OPERAND_FAKE))
886a2506 2793 {
4670103e
CZ		 2794 if (operand->flags & ARC_OPERAND_SIGNED)
2795 {
2796 max = (1 << (operand->bits - 1)) - 1;
2797 min = -(1 << (operand->bits - 1));
2798 }
2799 else
2800 {
2801 max = (1 << operand->bits) - 1;
2802 min = 0;
2803 }
886a2506 2804
4670103e
CZ		 2805 if (val < min || val > max)
2806 as_bad_value_out_of_range (_("operand"),
2807 val, min, max, file, line);
2808 }
ea1562b3 2809
cc07cda6 2810 pr_debug ("insert field: %ld <= %lld <= %ld in 0x%08llx\n",
4670103e 2811 min, val, max, insn);
ea1562b3 2812
4670103e
CZ		 2813 if ((operand->flags & ARC_OPERAND_ALIGNED32)
2814 && (val & 0x03))
2815 as_bad_where (file, line,
2816 _("Unaligned operand. Needs to be 32bit aligned"));
ea1562b3 2817
4670103e
CZ		 2818 if ((operand->flags & ARC_OPERAND_ALIGNED16)
2819 && (val & 0x01))
2820 as_bad_where (file, line,
2821 _("Unaligned operand. Needs to be 16bit aligned"));
ea1562b3 2822
4670103e
CZ		 2823 if (operand->insert)
2824 {
2825 const char *errmsg = NULL;
ea1562b3 2826
4670103e
CZ		 2827 insn = (*operand->insert) (insn, val, &errmsg);
2828 if (errmsg)
2829 as_warn_where (file, line, "%s", errmsg);
2830 }
2831 else
2832 {
2833 if (operand->flags & ARC_OPERAND_TRUNCATE)
2834 {
2835 if (operand->flags & ARC_OPERAND_ALIGNED32)
2836 val >>= 2;
2837 if (operand->flags & ARC_OPERAND_ALIGNED16)
2838 val >>= 1;
886a2506 2839 }
4670103e
CZ		 2840 insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift);
2841 }
2842 return insn;
2843}
ea1562b3 2844
4670103e
CZ		 2845/* Apply a fixup to the object code. At this point all symbol values
2846 should be fully resolved, and we attempt to completely resolve the
2847 reloc. If we can not do that, we determine the correct reloc code
2848 and put it back in the fixup. To indicate that a fixup has been
2849 eliminated, set fixP->fx_done. */
ea1562b3 2850
4670103e
CZ		 2851void
2852md_apply_fix (fixS *fixP,
2853 valueT *valP,
2854 segT seg)
2855{
2856 char * const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
2857 valueT value = *valP;
2858 unsigned insn = 0;
2859 symbolS *fx_addsy, *fx_subsy;
2860 offsetT fx_offset;
2861 segT add_symbol_segment = absolute_section;
2862 segT sub_symbol_segment = absolute_section;
2863 const struct arc_operand *operand = NULL;
2864 extended_bfd_reloc_code_real_type reloc;
886a2506 2865
4670103e
CZ		 2866 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2867 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2868 ((int) fixP->fx_r_type < 0) ? "Internal":
2869 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2870 fixP->fx_offset);
886a2506 2871
4670103e
CZ		 2872 fx_addsy = fixP->fx_addsy;
2873 fx_subsy = fixP->fx_subsy;
2874 fx_offset = 0;
886a2506 2875
4670103e
CZ		 2876 if (fx_addsy)
2877 {
2878 add_symbol_segment = S_GET_SEGMENT (fx_addsy);
886a2506
NC		 2879 }
2880
4670103e
CZ		 2881 if (fx_subsy
2882 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF
2883 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF_S9
2884 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_GD_LD)
2885 {
2886 resolve_symbol_value (fx_subsy);
2887 sub_symbol_segment = S_GET_SEGMENT (fx_subsy);
886a2506 2888
4670103e
CZ		 2889 if (sub_symbol_segment == absolute_section)
2890 {
2891 /* The symbol is really a constant. */
2892 fx_offset -= S_GET_VALUE (fx_subsy);
2893 fx_subsy = NULL;
2894 }
2895 else
2896 {
2897 as_bad_where (fixP->fx_file, fixP->fx_line,
2898 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2899 fx_addsy ? S_GET_NAME (fx_addsy) : "0",
2900 segment_name (add_symbol_segment),
2901 S_GET_NAME (fx_subsy),
2902 segment_name (sub_symbol_segment));
2903 return;
2904 }
2905 }
886a2506 2906
4670103e
CZ		 2907 if (fx_addsy
2908 && !S_IS_WEAK (fx_addsy))
2909 {
2910 if (add_symbol_segment == seg
2911 && fixP->fx_pcrel)
2912 {
2913 value += S_GET_VALUE (fx_addsy);
2914 value -= md_pcrel_from_section (fixP, seg);
2915 fx_addsy = NULL;
2916 fixP->fx_pcrel = FALSE;
2917 }
2918 else if (add_symbol_segment == absolute_section)
2919 {
2920 value = fixP->fx_offset;
2921 fx_offset += S_GET_VALUE (fixP->fx_addsy);
2922 fx_addsy = NULL;
2923 fixP->fx_pcrel = FALSE;
2924 }
2925 }
886a2506 2926
4670103e
CZ		 2927 if (!fx_addsy)
2928 fixP->fx_done = TRUE;
886a2506 2929
4670103e 2930 if (fixP->fx_pcrel)
886a2506 2931 {
4670103e
CZ		 2932 if (fx_addsy
2933 && ((S_IS_DEFINED (fx_addsy)
2934 && S_GET_SEGMENT (fx_addsy) != seg)
2935 || S_IS_WEAK (fx_addsy)))
2936 value += md_pcrel_from_section (fixP, seg);
886a2506 2937
4670103e
CZ		 2938 switch (fixP->fx_r_type)
2939 {
2940 case BFD_RELOC_ARC_32_ME:
2941 /* This is a pc-relative value in a LIMM. Adjust it to the
2942 address of the instruction not to the address of the
33eaf5de 2943 LIMM. Note: it is not any longer valid this affirmation as
4670103e
CZ		 2944 the linker consider ARC_PC32 a fixup to entire 64 bit
2945 insn. */
2946 fixP->fx_offset += fixP->fx_frag->fr_address;
2947 /* Fall through. */
2948 case BFD_RELOC_32:
2949 fixP->fx_r_type = BFD_RELOC_ARC_PC32;
2950 /* Fall through. */
2951 case BFD_RELOC_ARC_PC32:
2952 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
886a2506
NC		 2953 break;
2954 default:
4670103e 2955 if ((int) fixP->fx_r_type < 0)
6e3f3473 2956 as_bad_where (fixP->fx_file, fixP->fx_line,
2957 _("PC relative relocation not allowed for (internal)"
2958 " type %d"),
2959 fixP->fx_r_type);
886a2506 2960 break;
ea1562b3
NC		 2961 }
2962 }
2963
4670103e
CZ		 2964 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2965 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2966 ((int) fixP->fx_r_type < 0) ? "Internal":
2967 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2968 fixP->fx_offset);
886a2506 2969
886a2506 2970
4670103e
CZ		 2971 /* Now check for TLS relocations. */
2972 reloc = fixP->fx_r_type;
2973 switch (reloc)
886a2506 2974 {
4670103e
CZ		 2975 case BFD_RELOC_ARC_TLS_DTPOFF:
2976 case BFD_RELOC_ARC_TLS_LE_32:
2977 if (fixP->fx_done)
2978 break;
2979 /* Fall through. */
2980 case BFD_RELOC_ARC_TLS_GD_GOT:
2981 case BFD_RELOC_ARC_TLS_IE_GOT:
2982 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2983 break;
886a2506 2984
4670103e
CZ		 2985 case BFD_RELOC_ARC_TLS_GD_LD:
2986 gas_assert (!fixP->fx_offset);
2987 if (fixP->fx_subsy)
2988 fixP->fx_offset
2989 = (S_GET_VALUE (fixP->fx_subsy)
2990 - fixP->fx_frag->fr_address- fixP->fx_where);
2991 fixP->fx_subsy = NULL;
2992 /* Fall through. */
2993 case BFD_RELOC_ARC_TLS_GD_CALL:
2994 /* These two relocs are there just to allow ld to change the tls
2995 model for this symbol, by patching the code. The offset -
2996 and scale, if any - will be installed by the linker. */
2997 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2998 break;
886a2506 2999
4670103e
CZ		 3000 case BFD_RELOC_ARC_TLS_LE_S9:
3001 case BFD_RELOC_ARC_TLS_DTPOFF_S9:
3002 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3003 break;
3004
3005 default:
3006 break;
886a2506
NC		 3007 }
3008
4670103e 3009 if (!fixP->fx_done)
886a2506 3010 {
4670103e 3011 return;
886a2506 3012 }
886a2506 3013
33eaf5de 3014 /* Adjust the value if we have a constant. */
4670103e 3015 value += fx_offset;
886a2506 3016
4670103e
CZ		 3017 /* For hosts with longs bigger than 32-bits make sure that the top
3018 bits of a 32-bit negative value read in by the parser are set,
3019 so that the correct comparisons are made. */
3020 if (value & 0x80000000)
69c9e028 3021 value |= (-1UL << 31);
886a2506 3022
4670103e
CZ		 3023 reloc = fixP->fx_r_type;
3024 switch (reloc)
3025 {
3026 case BFD_RELOC_8:
3027 case BFD_RELOC_16:
3028 case BFD_RELOC_24:
3029 case BFD_RELOC_32:
3030 case BFD_RELOC_64:
3031 case BFD_RELOC_ARC_32_PCREL:
3032 md_number_to_chars (fixpos, value, fixP->fx_size);
3033 return;
886a2506 3034
4670103e
CZ		 3035 case BFD_RELOC_ARC_GOTPC32:
3036 /* I cannot fix an GOTPC relocation because I need to relax it
3037 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
3038 as_bad (_("Unsupported operation on reloc"));
3039 return;
886a2506 3040
4670103e
CZ		 3041 case BFD_RELOC_ARC_TLS_DTPOFF:
3042 case BFD_RELOC_ARC_TLS_LE_32:
3043 gas_assert (!fixP->fx_addsy);
3044 gas_assert (!fixP->fx_subsy);
1a0670f3 3045 /* Fall through. */
886a2506 3046
4670103e
CZ		 3047 case BFD_RELOC_ARC_GOTOFF:
3048 case BFD_RELOC_ARC_32_ME:
3049 case BFD_RELOC_ARC_PC32:
3050 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
3051 return;
886a2506 3052
4670103e
CZ		 3053 case BFD_RELOC_ARC_PLT32:
3054 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
3055 return;
886a2506 3056
4670103e
CZ		 3057 case BFD_RELOC_ARC_S25H_PCREL_PLT:
3058 reloc = BFD_RELOC_ARC_S25W_PCREL;
3059 goto solve_plt;
886a2506 3060
4670103e
CZ		 3061 case BFD_RELOC_ARC_S21H_PCREL_PLT:
3062 reloc = BFD_RELOC_ARC_S21H_PCREL;
3063 goto solve_plt;
886a2506 3064
4670103e
CZ		 3065 case BFD_RELOC_ARC_S25W_PCREL_PLT:
3066 reloc = BFD_RELOC_ARC_S25W_PCREL;
3067 goto solve_plt;
886a2506 3068
4670103e
CZ		 3069 case BFD_RELOC_ARC_S21W_PCREL_PLT:
3070 reloc = BFD_RELOC_ARC_S21W_PCREL;
1a0670f3 3071 /* Fall through. */
886a2506 3072
4670103e
CZ		 3073 case BFD_RELOC_ARC_S25W_PCREL:
3074 case BFD_RELOC_ARC_S21W_PCREL:
3075 case BFD_RELOC_ARC_S21H_PCREL:
3076 case BFD_RELOC_ARC_S25H_PCREL:
3077 case BFD_RELOC_ARC_S13_PCREL:
3078 solve_plt:
3079 operand = find_operand_for_reloc (reloc);
3080 gas_assert (operand);
886a2506
NC		 3081 break;
3082
3083 default:
4670103e
CZ		 3084 {
3085 if ((int) fixP->fx_r_type >= 0)
3086 as_fatal (_("unhandled relocation type %s"),
3087 bfd_get_reloc_code_name (fixP->fx_r_type));
886a2506 3088
4670103e
CZ		 3089 /* The rest of these fixups needs to be completely resolved as
3090 constants. */
3091 if (fixP->fx_addsy != 0
3092 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section)
3093 as_bad_where (fixP->fx_file, fixP->fx_line,
3094 _("non-absolute expression in constant field"));
886a2506 3095
4670103e
CZ		 3096 gas_assert (-(int) fixP->fx_r_type < (int) arc_num_operands);
3097 operand = &arc_operands[-(int) fixP->fx_r_type];
3098 break;
3099 }
3100 }
886a2506 3101
4670103e 3102 if (target_big_endian)
886a2506 3103 {
4670103e 3104 switch (fixP->fx_size)
886a2506 3105 {
4670103e
CZ		 3106 case 4:
3107 insn = bfd_getb32 (fixpos);
3108 break;
3109 case 2:
3110 insn = bfd_getb16 (fixpos);
3111 break;
3112 default:
3113 as_bad_where (fixP->fx_file, fixP->fx_line,
3114 _("unknown fixup size"));
3115 }
3116 }
3117 else
3118 {
3119 insn = 0;
3120 switch (fixP->fx_size)
3121 {
3122 case 4:
3123 insn = bfd_getl16 (fixpos) << 16 | bfd_getl16 (fixpos + 2);
3124 break;
3125 case 2:
3126 insn = bfd_getl16 (fixpos);
3127 break;
3128 default:
3129 as_bad_where (fixP->fx_file, fixP->fx_line,
3130 _("unknown fixup size"));
886a2506
NC		 3131 }
3132 }
886a2506 3133
4670103e
CZ		 3134 insn = insert_operand (insn, operand, (offsetT) value,
3135 fixP->fx_file, fixP->fx_line);
886a2506 3136
4670103e
CZ		 3137 md_number_to_chars_midend (fixpos, insn, fixP->fx_size);
3138}
886a2506 3139
4670103e 3140/* Prepare machine-dependent frags for relaxation.
886a2506 3141
4670103e
CZ		 3142 Called just before relaxation starts. Any symbol that is now undefined
3143 will not become defined.
886a2506 3144
4670103e 3145 Return the correct fr_subtype in the frag.
886a2506 3146
4670103e
CZ		 3147 Return the initial "guess for fr_var" to caller. The guess for fr_var
3148 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3149 or fr_var contributes to our returned value.
886a2506 3150
4670103e
CZ		 3151 Although it may not be explicit in the frag, pretend
3152 fr_var starts with a value. */
886a2506 3153
4670103e
CZ		 3154int
3155md_estimate_size_before_relax (fragS *fragP,
3156 segT segment)
3157{
3158 int growth;
3159
3160 /* If the symbol is not located within the same section AND it's not
3161 an absolute section, use the maximum. OR if the symbol is a
3162 constant AND the insn is by nature not pc-rel, use the maximum.
3163 OR if the symbol is being equated against another symbol, use the
3164 maximum. OR if the symbol is weak use the maximum. */
3165 if ((S_GET_SEGMENT (fragP->fr_symbol) != segment
3166 && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section)
3167 || (symbol_constant_p (fragP->fr_symbol)
3168 && !fragP->tc_frag_data.pcrel)
3169 || symbol_equated_p (fragP->fr_symbol)
3170 || S_IS_WEAK (fragP->fr_symbol))
3171 {
3172 while (md_relax_table[fragP->fr_subtype].rlx_more != ARC_RLX_NONE)
3173 ++fragP->fr_subtype;
3174 }
886a2506 3175
4670103e
CZ		 3176 growth = md_relax_table[fragP->fr_subtype].rlx_length;
3177 fragP->fr_var = growth;
886a2506 3178
4670103e
CZ		 3179 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3180 fragP->fr_file, fragP->fr_line, growth);
886a2506 3181
4670103e
CZ		 3182 return growth;
3183}
886a2506 3184
4670103e
CZ		 3185/* Translate internal representation of relocation info to BFD target
3186 format. */
886a2506 3187
4670103e
CZ		 3188arelent *
3189tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
3190 fixS *fixP)
3191{
3192 arelent *reloc;
3193 bfd_reloc_code_real_type code;
886a2506 3194
add39d23
TS		 3195 reloc = XNEW (arelent);
3196 reloc->sym_ptr_ptr = XNEW (asymbol *);
4670103e
CZ		 3197 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
3198 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
886a2506 3199
4670103e
CZ		 3200 /* Make sure none of our internal relocations make it this far.
3201 They'd better have been fully resolved by this point. */
3202 gas_assert ((int) fixP->fx_r_type > 0);
886a2506 3203
4670103e 3204 code = fixP->fx_r_type;
886a2506 3205
4670103e
CZ		 3206 /* if we have something like add gp, pcl,
3207 _GLOBAL_OFFSET_TABLE_@gotpc. */
3208 if (code == BFD_RELOC_ARC_GOTPC32
3209 && GOT_symbol
3210 && fixP->fx_addsy == GOT_symbol)
3211 code = BFD_RELOC_ARC_GOTPC;
886a2506 3212
4670103e
CZ		 3213 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3214 if (reloc->howto == NULL)
886a2506 3215 {
4670103e
CZ		 3216 as_bad_where (fixP->fx_file, fixP->fx_line,
3217 _("cannot represent `%s' relocation in object file"),
3218 bfd_get_reloc_code_name (code));
3219 return NULL;
3220 }
886a2506 3221
4670103e
CZ		 3222 if (!fixP->fx_pcrel != !reloc->howto->pc_relative)
3223 as_fatal (_("internal error? cannot generate `%s' relocation"),
3224 bfd_get_reloc_code_name (code));
886a2506 3225
4670103e 3226 gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
886a2506 3227
05bbf016 3228 reloc->addend = fixP->fx_offset;
4670103e
CZ		 3229
3230 return reloc;
886a2506
NC		 3231}
3232
4670103e
CZ		 3233/* Perform post-processing of machine-dependent frags after relaxation.
3234 Called after relaxation is finished.
3235 In: Address of frag.
3236 fr_type == rs_machine_dependent.
3237 fr_subtype is what the address relaxed to.
886a2506 3238
4670103e
CZ		 3239 Out: Any fixS:s and constants are set up. */
3240
3241void
3242md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
3243 segT segment ATTRIBUTE_UNUSED,
3244 fragS *fragP)
886a2506 3245{
4670103e
CZ		 3246 const relax_typeS *table_entry;
3247 char *dest;
3248 const struct arc_opcode *opcode;
3249 struct arc_insn insn;
3250 int size, fix;
3251 struct arc_relax_type *relax_arg = &fragP->tc_frag_data;
886a2506 3252
4670103e
CZ		 3253 fix = (fragP->fr_fix < 0 ? 0 : fragP->fr_fix);
3254 dest = fragP->fr_literal + fix;
3255 table_entry = TC_GENERIC_RELAX_TABLE + fragP->fr_subtype;
886a2506 3256
9e32d9ae
AB		 3257 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
3258 "var: %"BFD_VMA_FMT"d\n",
4670103e
CZ		 3259 fragP->fr_file, fragP->fr_line,
3260 fragP->fr_subtype, fix, fragP->fr_var);
886a2506 3261
4670103e
CZ		 3262 if (fragP->fr_subtype <= 0
3263 && fragP->fr_subtype >= arc_num_relax_opcodes)
3264 as_fatal (_("no relaxation found for this instruction."));
886a2506 3265
4670103e 3266 opcode = &arc_relax_opcodes[fragP->fr_subtype];
886a2506 3267
4670103e
CZ		 3268 assemble_insn (opcode, relax_arg->tok, relax_arg->ntok, relax_arg->pflags,
3269 relax_arg->nflg, &insn);
886a2506 3270
4670103e 3271 apply_fixups (&insn, fragP, fix);
886a2506 3272
91fdca6f 3273 size = insn.len + (insn.has_limm ? 4 : 0);
4670103e
CZ		 3274 gas_assert (table_entry->rlx_length == size);
3275 emit_insn0 (&insn, dest, TRUE);
886a2506 3276
4670103e
CZ		 3277 fragP->fr_fix += table_entry->rlx_length;
3278 fragP->fr_var = 0;
886a2506
NC		 3279}
3280
4670103e
CZ		 3281/* We have no need to default values of symbols. We could catch
3282 register names here, but that is handled by inserting them all in
3283 the symbol table to begin with. */
886a2506 3284
4670103e
CZ		 3285symbolS *
3286md_undefined_symbol (char *name)
886a2506 3287{
4670103e
CZ		 3288 /* The arc abi demands that a GOT[0] should be referencible as
3289 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3290 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3291 if (((*name == '_')
3292 && (*(name+1) == 'G')
7ef0acc1 3293 && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)))
886a2506 3294 {
4670103e
CZ		 3295 if (!GOT_symbol)
3296 {
3297 if (symbol_find (name))
3298 as_bad ("GOT already in symbol table");
3299
3300 GOT_symbol = symbol_new (GLOBAL_OFFSET_TABLE_NAME, undefined_section,
3301 (valueT) 0, &zero_address_frag);
3302 };
3303 return GOT_symbol;
886a2506 3304 }
4670103e 3305 return NULL;
886a2506
NC		 3306}
3307
4670103e
CZ		 3308/* Turn a string in input_line_pointer into a floating point constant
3309 of type type, and store the appropriate bytes in *litP. The number
3310 of LITTLENUMS emitted is stored in *sizeP. An error message is
3311 returned, or NULL on OK. */
886a2506 3312
6d4af3c2 3313const char *
4670103e 3314md_atof (int type, char *litP, int *sizeP)
886a2506 3315{
4670103e
CZ		 3316 return ieee_md_atof (type, litP, sizeP, target_big_endian);
3317}
886a2506 3318
4670103e
CZ		 3319/* Called for any expression that can not be recognized. When the
3320 function is called, `input_line_pointer' will point to the start of
3321 the expression. */
886a2506 3322
4670103e
CZ		 3323void
3324md_operand (expressionS *expressionP ATTRIBUTE_UNUSED)
3325{
3326 char *p = input_line_pointer;
3327 if (*p == '@')
886a2506 3328 {
4670103e
CZ		 3329 input_line_pointer++;
3330 expressionP->X_op = O_symbol;
3331 expression (expressionP);
3332 }
3333}
886a2506 3334
4670103e
CZ		 3335/* This function is called from the function 'expression', it attempts
3336 to parse special names (in our case register names). It fills in
3337 the expression with the identified register. It returns TRUE if
3338 it is a register and FALSE otherwise. */
886a2506 3339
4670103e
CZ		 3340bfd_boolean
3341arc_parse_name (const char *name,
3342 struct expressionS *e)
3343{
3344 struct symbol *sym;
886a2506 3345
4670103e
CZ		 3346 if (!assembling_insn)
3347 return FALSE;
886a2506 3348
08ec958f 3349 if (e->X_op == O_symbol)
4670103e 3350 return FALSE;
886a2506 3351
4670103e
CZ		 3352 sym = hash_find (arc_reg_hash, name);
3353 if (sym)
3354 {
3355 e->X_op = O_register;
3356 e->X_add_number = S_GET_VALUE (sym);
3357 return TRUE;
3358 }
db18dbab
GM		 3359
3360 sym = hash_find (arc_addrtype_hash, name);
3361 if (sym)
3362 {
3363 e->X_op = O_addrtype;
3364 e->X_add_number = S_GET_VALUE (sym);
3365 return TRUE;
3366 }
3367
4670103e
CZ		 3368 return FALSE;
3369}
886a2506 3370
4670103e
CZ		 3371/* md_parse_option
3372 Invocation line includes a switch not recognized by the base assembler.
3373 See if it's a processor-specific option.
886a2506 3374
4670103e 3375 New options (supported) are:
886a2506 3376
4670103e
CZ		 3377 -mcpu=<cpu name> Assemble for selected processor
3378 -EB/-mbig-endian Big-endian
3379 -EL/-mlittle-endian Little-endian
3380 -mrelax Enable relaxation
886a2506 3381
4670103e 3382 The following CPU names are recognized:
ce440d63 3383 arc600, arc700, arcem, archs, nps400. */
886a2506 3384
4670103e 3385int
17b9d67d 3386md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
4670103e 3387{
4670103e
CZ		 3388 switch (c)
3389 {
3390 case OPTION_ARC600:
3391 case OPTION_ARC601:
3392 return md_parse_option (OPTION_MCPU, "arc600");
886a2506 3393
4670103e
CZ		 3394 case OPTION_ARC700:
3395 return md_parse_option (OPTION_MCPU, "arc700");
886a2506 3396
4670103e
CZ		 3397 case OPTION_ARCEM:
3398 return md_parse_option (OPTION_MCPU, "arcem");
886a2506 3399
4670103e
CZ		 3400 case OPTION_ARCHS:
3401 return md_parse_option (OPTION_MCPU, "archs");
886a2506 3402
4670103e
CZ		 3403 case OPTION_MCPU:
3404 {
bb65a718 3405 arc_select_cpu (arg, MACH_SELECTION_FROM_COMMAND_LINE);
4670103e
CZ		 3406 break;
3407 }
886a2506 3408
4670103e
CZ		 3409 case OPTION_EB:
3410 arc_target_format = "elf32-bigarc";
3411 byte_order = BIG_ENDIAN;
3412 break;
886a2506 3413
4670103e
CZ		 3414 case OPTION_EL:
3415 arc_target_format = "elf32-littlearc";
3416 byte_order = LITTLE_ENDIAN;
3417 break;
886a2506 3418
4670103e 3419 case OPTION_CD:
53a346d8
CZ		 3420 selected_cpu.features |= CD;
3421 cl_features |= CD;
bb050a69 3422 arc_check_feature ();
4670103e 3423 break;
886a2506 3424
4670103e
CZ		 3425 case OPTION_RELAX:
3426 relaxation_state = 1;
3427 break;
886a2506 3428
bdd582db 3429 case OPTION_NPS400:
53a346d8
CZ		 3430 selected_cpu.features |= NPS400;
3431 cl_features |= NPS400;
bb050a69 3432 arc_check_feature ();
ce440d63 3433 break;
bdd582db 3434
ce440d63 3435 case OPTION_SPFP:
53a346d8
CZ		 3436 selected_cpu.features |= SPX;
3437 cl_features |= SPX;
bb050a69 3438 arc_check_feature ();
ce440d63
GM		 3439 break;
3440
3441 case OPTION_DPFP:
53a346d8
CZ		 3442 selected_cpu.features |= DPX;
3443 cl_features |= DPX;
bb050a69 3444 arc_check_feature ();
ce440d63
GM		 3445 break;
3446
3447 case OPTION_FPUDA:
53a346d8
CZ		 3448 selected_cpu.features |= DPA;
3449 cl_features |= DPA;
bb050a69 3450 arc_check_feature ();
ce440d63
GM		 3451 break;
3452
3453 /* Dummy options are accepted but have no effect. */
4670103e
CZ		 3454 case OPTION_USER_MODE:
3455 case OPTION_LD_EXT_MASK:
3456 case OPTION_SWAP:
3457 case OPTION_NORM:
3458 case OPTION_BARREL_SHIFT:
3459 case OPTION_MIN_MAX:
3460 case OPTION_NO_MPY:
3461 case OPTION_EA:
3462 case OPTION_MUL64:
3463 case OPTION_SIMD:
4670103e
CZ		 3464 case OPTION_XMAC_D16:
3465 case OPTION_XMAC_24:
3466 case OPTION_DSP_PACKA:
3467 case OPTION_CRC:
3468 case OPTION_DVBF:
3469 case OPTION_TELEPHONY:
3470 case OPTION_XYMEMORY:
3471 case OPTION_LOCK:
3472 case OPTION_SWAPE:
3473 case OPTION_RTSC:
8ddf6b2a
CZ		 3474 break;
3475
4670103e
CZ		 3476 default:
3477 return 0;
3478 }
886a2506 3479
4670103e
CZ		 3480 return 1;
3481}
886a2506 3482
a9752fdf
CZ		 3483/* Display the list of cpu names for use in the help text. */
3484
3485static void
3486arc_show_cpu_list (FILE *stream)
3487{
3488 int i, offset;
731f7c4e 3489 static const char *space_buf = " ";
a9752fdf 3490
731f7c4e
MR		 3491 fprintf (stream, "%s", space_buf);
3492 offset = strlen (space_buf);
a9752fdf
CZ		 3493 for (i = 0; cpu_types[i].name != NULL; ++i)
3494 {
3495 bfd_boolean last = (cpu_types[i + 1].name == NULL);
3496
3497 /* If displaying the new cpu name string, and the ', ' (for all
3498 but the last one) will take us past a target width of 80
3499 characters, then it's time for a new line. */
3500 if (offset + strlen (cpu_types[i].name) + (last ? 0 : 2) > 80)
3501 {
731f7c4e
MR		 3502 fprintf (stream, "\n%s", space_buf);
3503 offset = strlen (space_buf);
a9752fdf
CZ		 3504 }
3505
3506 fprintf (stream, "%s%s", cpu_types[i].name, (last ? "\n" : ", "));
3507 offset += strlen (cpu_types [i].name) + (last ? 0 : 2);
3508 }
3509}
3510
4670103e
CZ		 3511void
3512md_show_usage (FILE *stream)
3513{
3514 fprintf (stream, _("ARC-specific assembler options:\n"));
886a2506 3515
a9752fdf
CZ		 3516 fprintf (stream, " -mcpu=<cpu name>\t (default: %s), assemble for"
3517 " CPU <cpu name>, one of:\n", TARGET_WITH_CPU);
3518 arc_show_cpu_list (stream);
3519 fprintf (stream, "\n");
bdd582db
GM		 3520 fprintf (stream, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
3521 fprintf (stream, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
3522 fprintf (stream, " -mEM\t\t\t same as -mcpu=arcem\n");
3523 fprintf (stream, " -mHS\t\t\t same as -mcpu=archs\n");
3524
3525 fprintf (stream, " -mnps400\t\t enable NPS-400 extended instructions\n");
a9752fdf
CZ		 3526 fprintf (stream, " -mspfp\t\t enable single-precision floating point"
3527 " instructions\n");
3528 fprintf (stream, " -mdpfp\t\t enable double-precision floating point"
3529 " instructions\n");
bdd582db
GM		 3530 fprintf (stream, " -mfpuda\t\t enable double-precision assist floating "
3531 "point\n\t\t\t instructions for ARC EM\n");
3532
4670103e
CZ		 3533 fprintf (stream,
3534 " -mcode-density\t enable code density option for ARC EM\n");
3535
3536 fprintf (stream, _("\
3537 -EB assemble code for a big-endian cpu\n"));
3538 fprintf (stream, _("\
3539 -EL assemble code for a little-endian cpu\n"));
3540 fprintf (stream, _("\
bdd582db
GM		 3541 -mrelax enable relaxation\n"));
3542
3543 fprintf (stream, _("The following ARC-specific assembler options are "
3544 "deprecated and are accepted\nfor compatibility only:\n"));
3545
3546 fprintf (stream, _(" -mEA\n"
3547 " -mbarrel-shifter\n"
3548 " -mbarrel_shifter\n"
3549 " -mcrc\n"
3550 " -mdsp-packa\n"
3551 " -mdsp_packa\n"
3552 " -mdvbf\n"
3553 " -mld-extension-reg-mask\n"
3554 " -mlock\n"
3555 " -mmac-24\n"
3556 " -mmac-d16\n"
3557 " -mmac_24\n"
3558 " -mmac_d16\n"
3559 " -mmin-max\n"
3560 " -mmin_max\n"
3561 " -mmul64\n"
3562 " -mno-mpy\n"
3563 " -mnorm\n"
3564 " -mrtsc\n"
3565 " -msimd\n"
3566 " -mswap\n"
3567 " -mswape\n"
3568 " -mtelephony\n"
3569 " -muser-mode-only\n"
3570 " -mxy\n"));
886a2506
NC		 3571}
3572
3573/* Find the proper relocation for the given opcode. */
3574
3575static extended_bfd_reloc_code_real_type
3576find_reloc (const char *name,
3577 const char *opcodename,
3578 const struct arc_flags *pflags,
3579 int nflg,
3580 extended_bfd_reloc_code_real_type reloc)
3581{
3582 unsigned int i;
3583 int j;
24b368f8 3584 bfd_boolean found_flag, tmp;
886a2506
NC		 3585 extended_bfd_reloc_code_real_type ret = BFD_RELOC_UNUSED;
3586
3587 for (i = 0; i < arc_num_equiv_tab; i++)
3588 {
3589 const struct arc_reloc_equiv_tab *r = &arc_reloc_equiv[i];
3590
3591 /* Find the entry. */
3592 if (strcmp (name, r->name))
3593 continue;
3594 if (r->mnemonic && (strcmp (r->mnemonic, opcodename)))
3595 continue;
24b368f8 3596 if (r->flags[0])
886a2506
NC		 3597 {
3598 if (!nflg)
3599 continue;
3600 found_flag = FALSE;
24b368f8
CZ		 3601 unsigned * psflg = (unsigned *)r->flags;
3602 do
3603 {
3604 tmp = FALSE;
3605 for (j = 0; j < nflg; j++)
3606 if (!strcmp (pflags[j].name,
3607 arc_flag_operands[*psflg].name))
3608 {
3609 tmp = TRUE;
3610 break;
3611 }
3612 if (!tmp)
3613 {
3614 found_flag = FALSE;
3615 break;
3616 }
3617 else
3618 {
3619 found_flag = TRUE;
3620 }
3621 ++ psflg;
3622 } while (*psflg);
3623
886a2506
NC		 3624 if (!found_flag)
3625 continue;
3626 }
3627
3628 if (reloc != r->oldreloc)
3629 continue;
3630 /* Found it. */
3631 ret = r->newreloc;
3632 break;
3633 }
3634
3635 if (ret == BFD_RELOC_UNUSED)
3636 as_bad (_("Unable to find %s relocation for instruction %s"),
3637 name, opcodename);
3638 return ret;
3639}
3640
4670103e
CZ		 3641/* All the symbol types that are allowed to be used for
3642 relaxation. */
3643
3644static bfd_boolean
3645may_relax_expr (expressionS tok)
3646{
3647 /* Check if we have unrelaxable relocs. */
3648 switch (tok.X_md)
3649 {
3650 default:
3651 break;
3652 case O_plt:
3653 return FALSE;
3654 }
3655
3656 switch (tok.X_op)
3657 {
3658 case O_symbol:
3659 case O_multiply:
3660 case O_divide:
3661 case O_modulus:
3662 case O_add:
3663 case O_subtract:
3664 break;
3665
3666 default:
3667 return FALSE;
3668 }
3669 return TRUE;
3670}
3671
3672/* Checks if flags are in line with relaxable insn. */
3673
3674static bfd_boolean
3675relaxable_flag (const struct arc_relaxable_ins *ins,
3676 const struct arc_flags *pflags,
3677 int nflgs)
3678{
3679 unsigned flag_class,
3680 flag,
3681 flag_class_idx = 0,
3682 flag_idx = 0;
3683
3684 const struct arc_flag_operand *flag_opand;
3685 int i, counttrue = 0;
3686
3687 /* Iterate through flags classes. */
3688 while ((flag_class = ins->flag_classes[flag_class_idx]) != 0)
3689 {
3690 /* Iterate through flags in flag class. */
3691 while ((flag = arc_flag_classes[flag_class].flags[flag_idx])
3692 != 0)
3693 {
3694 flag_opand = &arc_flag_operands[flag];
3695 /* Iterate through flags in ins to compare. */
3696 for (i = 0; i < nflgs; ++i)
3697 {
3698 if (strcmp (flag_opand->name, pflags[i].name) == 0)
3699 ++counttrue;
3700 }
3701
3702 ++flag_idx;
3703 }
3704
3705 ++flag_class_idx;
3706 flag_idx = 0;
3707 }
3708
3709 /* If counttrue == nflgs, then all flags have been found. */
3710 return (counttrue == nflgs ? TRUE : FALSE);
3711}
3712
3713/* Checks if operands are in line with relaxable insn. */
3714
3715static bfd_boolean
3716relaxable_operand (const struct arc_relaxable_ins *ins,
3717 const expressionS *tok,
3718 int ntok)
3719{
3720 const enum rlx_operand_type *operand = &ins->operands[0];
3721 int i = 0;
3722
3723 while (*operand != EMPTY)
3724 {
3725 const expressionS *epr = &tok[i];
3726
3727 if (i != 0 && i >= ntok)
3728 return FALSE;
3729
3730 switch (*operand)
3731 {
3732 case IMMEDIATE:
3733 if (!(epr->X_op == O_multiply
3734 || epr->X_op == O_divide
3735 || epr->X_op == O_modulus
3736 || epr->X_op == O_add
3737 || epr->X_op == O_subtract
3738 || epr->X_op == O_symbol))
3739 return FALSE;
3740 break;
3741
3742 case REGISTER_DUP:
3743 if ((i <= 0)
3744 || (epr->X_add_number != tok[i - 1].X_add_number))
3745 return FALSE;
3746 /* Fall through. */
3747 case REGISTER:
3748 if (epr->X_op != O_register)
3749 return FALSE;
3750 break;
3751
3752 case REGISTER_S:
3753 if (epr->X_op != O_register)
3754 return FALSE;
3755
3756 switch (epr->X_add_number)
3757 {
3758 case 0: case 1: case 2: case 3:
3759 case 12: case 13: case 14: case 15:
3760 break;
3761 default:
3762 return FALSE;
3763 }
3764 break;
3765
3766 case REGISTER_NO_GP:
3767 if ((epr->X_op != O_register)
3768 || (epr->X_add_number == 26)) /* 26 is the gp register. */
3769 return FALSE;
3770 break;
3771
3772 case BRACKET:
3773 if (epr->X_op != O_bracket)
3774 return FALSE;
3775 break;
3776
3777 default:
3778 /* Don't understand, bail out. */
3779 return FALSE;
3780 break;
3781 }
3782
3783 ++i;
3784 operand = &ins->operands[i];
3785 }
3786
3787 return (i == ntok ? TRUE : FALSE);
3788}
3789
3790/* Return TRUE if this OPDCODE is a candidate for relaxation. */
3791
3792static bfd_boolean
3793relax_insn_p (const struct arc_opcode *opcode,
3794 const expressionS *tok,
3795 int ntok,
3796 const struct arc_flags *pflags,
3797 int nflg)
3798{
3799 unsigned i;
3800 bfd_boolean rv = FALSE;
3801
3802 /* Check the relaxation table. */
3803 for (i = 0; i < arc_num_relaxable_ins && relaxation_state; ++i)
3804 {
3805 const struct arc_relaxable_ins *arc_rlx_ins = &arc_relaxable_insns[i];
3806
3807 if ((strcmp (opcode->name, arc_rlx_ins->mnemonic_r) == 0)
3808 && may_relax_expr (tok[arc_rlx_ins->opcheckidx])
3809 && relaxable_operand (arc_rlx_ins, tok, ntok)
3810 && relaxable_flag (arc_rlx_ins, pflags, nflg))
3811 {
3812 rv = TRUE;
3813 frag_now->fr_subtype = arc_relaxable_insns[i].subtype;
3814 memcpy (&frag_now->tc_frag_data.tok, tok,
3815 sizeof (expressionS) * ntok);
3816 memcpy (&frag_now->tc_frag_data.pflags, pflags,
3817 sizeof (struct arc_flags) * nflg);
3818 frag_now->tc_frag_data.nflg = nflg;
3819 frag_now->tc_frag_data.ntok = ntok;
3820 break;
3821 }
3822 }
3823
3824 return rv;
3825}
3826
886a2506
NC		 3827/* Turn an opcode description and a set of arguments into
3828 an instruction and a fixup. */
3829
3830static void
3831assemble_insn (const struct arc_opcode *opcode,
3832 const expressionS *tok,
3833 int ntok,
3834 const struct arc_flags *pflags,
3835 int nflg,
3836 struct arc_insn *insn)
3837{
3838 const expressionS *reloc_exp = NULL;
bdfe53e3 3839 unsigned long long image;
886a2506
NC		 3840 const unsigned char *argidx;
3841 int i;
3842 int tokidx = 0;
3843 unsigned char pcrel = 0;
3844 bfd_boolean needGOTSymbol;
3845 bfd_boolean has_delay_slot = FALSE;
3846 extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
3847
3848 memset (insn, 0, sizeof (*insn));
3849 image = opcode->opcode;
3850
bdfe53e3 3851 pr_debug ("%s:%d: assemble_insn: %s using opcode %llx\n",
886a2506
NC		 3852 frag_now->fr_file, frag_now->fr_line, opcode->name,
3853 opcode->opcode);
3854
3855 /* Handle operands. */
3856 for (argidx = opcode->operands; *argidx; ++argidx)
3857 {
3858 const struct arc_operand *operand = &arc_operands[*argidx];
3859 const expressionS *t = (const expressionS *) 0;
3860
db18dbab 3861 if (ARC_OPERAND_IS_FAKE (operand))
886a2506
NC		 3862 continue;
3863
3864 if (operand->flags & ARC_OPERAND_DUPLICATE)
3865 {
3866 /* Duplicate operand, already inserted. */
3867 tokidx ++;
3868 continue;
3869 }
3870
3871 if (tokidx >= ntok)
3872 {
3873 abort ();
3874 }
3875 else
3876 t = &tok[tokidx++];
3877
3878 /* Regardless if we have a reloc or not mark the instruction
3879 limm if it is the case. */
3880 if (operand->flags & ARC_OPERAND_LIMM)
3881 insn->has_limm = TRUE;
3882
3883 switch (t->X_op)
3884 {
3885 case O_register:
3886 image = insert_operand (image, operand, regno (t->X_add_number),
3887 NULL, 0);
3888 break;
3889
3890 case O_constant:
3891 image = insert_operand (image, operand, t->X_add_number, NULL, 0);
3892 reloc_exp = t;
3893 if (operand->flags & ARC_OPERAND_LIMM)
3894 insn->limm = t->X_add_number;
3895 break;
3896
3897 case O_bracket:
db18dbab
GM		 3898 case O_colon:
3899 case O_addrtype:
3900 /* Ignore brackets, colons, and address types. */
886a2506
NC		 3901 break;
3902
3903 case O_absent:
3904 gas_assert (operand->flags & ARC_OPERAND_IGNORE);
3905 break;
3906
3907 case O_subtract:
3908 /* Maybe register range. */
3909 if ((t->X_add_number == 0)
3910 && contains_register (t->X_add_symbol)
3911 && contains_register (t->X_op_symbol))
3912 {
3913 int regs;
3914
3915 regs = get_register (t->X_add_symbol);
3916 regs <<= 16;
3917 regs |= get_register (t->X_op_symbol);
3918 image = insert_operand (image, operand, regs, NULL, 0);
3919 break;
3920 }
1a0670f3 3921 /* Fall through. */
886a2506
NC		 3922
3923 default:
3924 /* This operand needs a relocation. */
3925 needGOTSymbol = FALSE;
3926
3927 switch (t->X_md)
3928 {
3929 case O_plt:
c810e0b8 3930 if (opcode->insn_class == JUMP)
6e3f3473 3931 as_bad (_("Unable to use @plt relocation for insn %s"),
3932 opcode->name);
886a2506
NC		 3933 needGOTSymbol = TRUE;
3934 reloc = find_reloc ("plt", opcode->name,
3935 pflags, nflg,
3936 operand->default_reloc);
3937 break;
3938
3939 case O_gotoff:
3940 case O_gotpc:
3941 needGOTSymbol = TRUE;
3942 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3943 break;
3944 case O_pcl:
cc07cda6
CZ		 3945 if (operand->flags & ARC_OPERAND_LIMM)
3946 {
3947 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3948 if (arc_opcode_len (opcode) == 2
3949 || opcode->insn_class == JUMP)
6e3f3473 3950 as_bad (_("Unable to use @pcl relocation for insn %s"),
3951 opcode->name);
cc07cda6
CZ		 3952 }
3953 else
3954 {
3955 /* This is a relaxed operand which initially was
3956 limm, choose whatever we have defined in the
3957 opcode as reloc. */
3958 reloc = operand->default_reloc;
3959 }
886a2506
NC		 3960 break;
3961 case O_sda:
3962 reloc = find_reloc ("sda", opcode->name,
3963 pflags, nflg,
3964 operand->default_reloc);
3965 break;
3966 case O_tlsgd:
3967 case O_tlsie:
3968 needGOTSymbol = TRUE;
3969 /* Fall-through. */
3970
3971 case O_tpoff:
3972 case O_dtpoff:
3973 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3974 break;
3975
3976 case O_tpoff9: /*FIXME! Check for the conditionality of
3977 the insn. */
3978 case O_dtpoff9: /*FIXME! Check for the conditionality of
3979 the insn. */
3980 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3981 break;
3982
3983 default:
3984 /* Just consider the default relocation. */
3985 reloc = operand->default_reloc;
3986 break;
3987 }
3988
3989 if (needGOTSymbol && (GOT_symbol == NULL))
3990 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3991
3992 reloc_exp = t;
3993
3994#if 0
3995 if (reloc > 0)
3996 {
3997 /* sanity checks. */
3998 reloc_howto_type *reloc_howto
3999 = bfd_reloc_type_lookup (stdoutput,
4000 (bfd_reloc_code_real_type) reloc);
4001 unsigned reloc_bitsize = reloc_howto->bitsize;
4002 if (reloc_howto->rightshift)
4003 reloc_bitsize -= reloc_howto->rightshift;
4004 if (reloc_bitsize != operand->bits)
4005 {
4006 as_bad (_("invalid relocation %s for field"),
4007 bfd_get_reloc_code_name (reloc));
4008 return;
4009 }
4010 }
4011#endif
4012 if (insn->nfixups >= MAX_INSN_FIXUPS)
4013 as_fatal (_("too many fixups"));
4014
4015 struct arc_fixup *fixup;
4016 fixup = &insn->fixups[insn->nfixups++];
4017 fixup->exp = *t;
4018 fixup->reloc = reloc;
cc07cda6
CZ		 4019 if ((int) reloc < 0)
4020 pcrel = (operand->flags & ARC_OPERAND_PCREL) ? 1 : 0;
4021 else
4022 {
4023 reloc_howto_type *reloc_howto =
4024 bfd_reloc_type_lookup (stdoutput,
4025 (bfd_reloc_code_real_type) fixup->reloc);
4026 pcrel = reloc_howto->pc_relative;
4027 }
886a2506
NC		 4028 fixup->pcrel = pcrel;
4029 fixup->islong = (operand->flags & ARC_OPERAND_LIMM) ?
4030 TRUE : FALSE;
4031 break;
4032 }
4033 }
4034
4035 /* Handle flags. */
4036 for (i = 0; i < nflg; i++)
4037 {
f36e33da 4038 const struct arc_flag_operand *flg_operand = pflags[i].flgp;
886a2506
NC		 4039
4040 /* Check if the instruction has a delay slot. */
4041 if (!strcmp (flg_operand->name, "d"))
4042 has_delay_slot = TRUE;
4043
2c52e2e8
RZ		 4044 /* There is an exceptional case when we cannot insert a flag just as
4045 it is. On ARCv2 the '.t' and '.nt' flags must be handled in
4046 relation with the relative address. Unfortunately, some of the
4047 ARC700 extensions (NPS400) also have a '.nt' flag that should be
4048 handled in the normal way.
4049
4050 Flag operands don't have an architecture field, so we can't
4051 directly validate that FLAG_OPERAND is valid for the current
4052 architecture, what we do instead is just validate that we're
4053 assembling for an ARCv2 architecture. */
4054 if ((selected_cpu.flags & ARC_OPCODE_ARCV2)
4055 && (!strcmp (flg_operand->name, "t")
4056 || !strcmp (flg_operand->name, "nt")))
886a2506
NC		 4057 {
4058 unsigned bitYoperand = 0;
4059 /* FIXME! move selection bbit/brcc in arc-opc.c. */
4060 if (!strcmp (flg_operand->name, "t"))
4061 if (!strcmp (opcode->name, "bbit0")
4062 || !strcmp (opcode->name, "bbit1"))
4063 bitYoperand = arc_NToperand;
4064 else
4065 bitYoperand = arc_Toperand;
4066 else
4067 if (!strcmp (opcode->name, "bbit0")
4068 || !strcmp (opcode->name, "bbit1"))
4069 bitYoperand = arc_Toperand;
4070 else
4071 bitYoperand = arc_NToperand;
4072
4073 gas_assert (reloc_exp != NULL);
4074 if (reloc_exp->X_op == O_constant)
4075 {
4076 /* Check if we have a constant and solved it
4077 immediately. */
4078 offsetT val = reloc_exp->X_add_number;
4079 image |= insert_operand (image, &arc_operands[bitYoperand],
4080 val, NULL, 0);
4081 }
4082 else
4083 {
4084 struct arc_fixup *fixup;
4085
4086 if (insn->nfixups >= MAX_INSN_FIXUPS)
4087 as_fatal (_("too many fixups"));
4088
4089 fixup = &insn->fixups[insn->nfixups++];
4090 fixup->exp = *reloc_exp;
4091 fixup->reloc = -bitYoperand;
4092 fixup->pcrel = pcrel;
4093 fixup->islong = FALSE;
4094 }
4095 }
4096 else
4097 image |= (flg_operand->code & ((1 << flg_operand->bits) - 1))
4098 << flg_operand->shift;
4099 }
4100
4670103e
CZ		 4101 insn->relax = relax_insn_p (opcode, tok, ntok, pflags, nflg);
4102
91fdca6f 4103 /* Instruction length. */
06fe285f 4104 insn->len = arc_opcode_len (opcode);
886a2506
NC		 4105
4106 insn->insn = image;
4107
4108 /* Update last insn status. */
4109 arc_last_insns[1] = arc_last_insns[0];
4110 arc_last_insns[0].opcode = opcode;
4111 arc_last_insns[0].has_limm = insn->has_limm;
4112 arc_last_insns[0].has_delay_slot = has_delay_slot;
4113
4114 /* Check if the current instruction is legally used. */
4115 if (arc_last_insns[1].has_delay_slot
4116 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
6e3f3473 4117 as_bad (_("Insn %s has a jump/branch instruction %s in its delay slot."),
4118 arc_last_insns[1].opcode->name,
4119 arc_last_insns[0].opcode->name);
cf9bdae9 4120 if (arc_last_insns[1].has_delay_slot
4121 && arc_last_insns[0].has_limm)
4122 as_bad (_("Insn %s has an instruction %s with limm in its delay slot."),
4123 arc_last_insns[1].opcode->name,
4124 arc_last_insns[0].opcode->name);
886a2506
NC		 4125}
4126
886a2506
NC		 4127void
4128arc_handle_align (fragS* fragP)
4129{
4130 if ((fragP)->fr_type == rs_align_code)
4131 {
4132 char *dest = (fragP)->fr_literal + (fragP)->fr_fix;
4133 valueT count = ((fragP)->fr_next->fr_address
4134 - (fragP)->fr_address - (fragP)->fr_fix);
4135
4136 (fragP)->fr_var = 2;
4137
4138 if (count & 1)/* Padding in the gap till the next 2-byte
4139 boundary with 0s. */
4140 {
4141 (fragP)->fr_fix++;
4142 *dest++ = 0;
4143 }
4144 /* Writing nop_s. */
4145 md_number_to_chars (dest, NOP_OPCODE_S, 2);
4146 }
4147}
4148
4149/* Here we decide which fixups can be adjusted to make them relative
4150 to the beginning of the section instead of the symbol. Basically
4151 we need to make sure that the dynamic relocations are done
4152 correctly, so in some cases we force the original symbol to be
4153 used. */
4154
4155int
4156tc_arc_fix_adjustable (fixS *fixP)
4157{
4158
4159 /* Prevent all adjustments to global symbols. */
4160 if (S_IS_EXTERNAL (fixP->fx_addsy))
4161 return 0;
4162 if (S_IS_WEAK (fixP->fx_addsy))
4163 return 0;
4164
4165 /* Adjust_reloc_syms doesn't know about the GOT. */
4166 switch (fixP->fx_r_type)
4167 {
4168 case BFD_RELOC_ARC_GOTPC32:
4169 case BFD_RELOC_ARC_PLT32:
4170 case BFD_RELOC_ARC_S25H_PCREL_PLT:
4171 case BFD_RELOC_ARC_S21H_PCREL_PLT:
4172 case BFD_RELOC_ARC_S25W_PCREL_PLT:
4173 case BFD_RELOC_ARC_S21W_PCREL_PLT:
4174 return 0;
4175
4176 default:
4177 break;
4178 }
4179
841fdfcd 4180 return 1;
886a2506
NC		 4181}
4182
4183/* Compute the reloc type of an expression EXP. */
4184
4185static void
4186arc_check_reloc (expressionS *exp,
4187 bfd_reloc_code_real_type *r_type_p)
4188{
4189 if (*r_type_p == BFD_RELOC_32
4190 && exp->X_op == O_subtract
4191 && exp->X_op_symbol != NULL
4192 && exp->X_op_symbol->bsym->section == now_seg)
6f4b1afc 4193 *r_type_p = BFD_RELOC_ARC_32_PCREL;
886a2506
NC		 4194}
4195
4196
4197/* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4198
4199void
4200arc_cons_fix_new (fragS *frag,
4201 int off,
4202 int size,
4203 expressionS *exp,
4204 bfd_reloc_code_real_type r_type)
4205{
4206 r_type = BFD_RELOC_UNUSED;
4207
4208 switch (size)
4209 {
4210 case 1:
4211 r_type = BFD_RELOC_8;
4212 break;
4213
4214 case 2:
4215 r_type = BFD_RELOC_16;
4216 break;
4217
4218 case 3:
4219 r_type = BFD_RELOC_24;
4220 break;
4221
4222 case 4:
4223 r_type = BFD_RELOC_32;
4224 arc_check_reloc (exp, &r_type);
4225 break;
4226
4227 case 8:
4228 r_type = BFD_RELOC_64;
4229 break;
4230
4231 default:
4232 as_bad (_("unsupported BFD relocation size %u"), size);
4233 r_type = BFD_RELOC_UNUSED;
4234 }
4235
4236 fix_new_exp (frag, off, size, exp, 0, r_type);
4237}
4238
4239/* The actual routine that checks the ZOL conditions. */
4240
4241static void
4242check_zol (symbolS *s)
4243{
bb65a718 4244 switch (selected_cpu.mach)
886a2506
NC		 4245 {
4246 case bfd_mach_arc_arcv2:
bb65a718 4247 if (selected_cpu.flags & ARC_OPCODE_ARCv2EM)
886a2506
NC		 4248 return;
4249
4250 if (is_br_jmp_insn_p (arc_last_insns[0].opcode)
4251 || arc_last_insns[1].has_delay_slot)
4252 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4253 S_GET_NAME (s));
4254
4255 break;
4256 case bfd_mach_arc_arc600:
4257
4258 if (is_kernel_insn_p (arc_last_insns[0].opcode))
4259 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4260 S_GET_NAME (s));
4261
4262 if (arc_last_insns[0].has_limm
4263 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
4264 as_bad (_("A jump instruction with long immediate detected at the \
4265end of the ZOL label @%s"), S_GET_NAME (s));
4266
4267 /* Fall through. */
4268 case bfd_mach_arc_arc700:
4269 if (arc_last_insns[0].has_delay_slot)
4270 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4271 S_GET_NAME (s));
4272
4273 break;
4274 default:
4275 break;
4276 }
4277}
4278
4279/* If ZOL end check the last two instruction for illegals. */
4280void
4281arc_frob_label (symbolS * sym)
4282{
4283 if (ARC_GET_FLAG (sym) & ARC_FLAG_ZOL)
4284 check_zol (sym);
4285
4286 dwarf2_emit_label (sym);
ea1562b3 4287}
4670103e
CZ		 4288
4289/* Used because generic relaxation assumes a pc-rel value whilst we
4290 also relax instructions that use an absolute value resolved out of
4291 relative values (if that makes any sense). An example: 'add r1,
4292 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4293 but if they're in the same section we can subtract the section
4294 offset relocation which ends up in a resolved value. So if @.L2 is
4295 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4296 .text + 0x40 = 0x10. */
4297int
4298arc_pcrel_adjust (fragS *fragP)
4299{
cc07cda6
CZ		 4300 pr_debug ("arc_pcrel_adjust: address=%ld, fix=%ld, PCrel %s\n",
4301 fragP->fr_address, fragP->fr_fix,
4302 fragP->tc_frag_data.pcrel ? "Y" : "N");
4303
4670103e
CZ		 4304 if (!fragP->tc_frag_data.pcrel)
4305 return fragP->fr_address + fragP->fr_fix;
4306
cc07cda6
CZ		 4307 /* Take into account the PCL rounding. */
4308 return (fragP->fr_address + fragP->fr_fix) & 0x03;
4670103e 4309}
726c18e1
CZ		 4310
4311/* Initialize the DWARF-2 unwind information for this procedure. */
4312
4313void
4314tc_arc_frame_initial_instructions (void)
4315{
4316 /* Stack pointer is register 28. */
45a54ee5 4317 cfi_add_CFA_def_cfa (28, 0);
726c18e1
CZ		 4318}
4319
4320int
4321tc_arc_regname_to_dw2regnum (char *regname)
4322{
4323 struct symbol *sym;
4324
4325 sym = hash_find (arc_reg_hash, regname);
4326 if (sym)
4327 return S_GET_VALUE (sym);
4328
4329 return -1;
4330}
37ab9779
CZ		 4331
4332/* Adjust the symbol table. Delete found AUX register symbols. */
4333
4334void
4335arc_adjust_symtab (void)
4336{
4337 symbolS * sym;
4338
4339 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4340 {
4341 /* I've created a symbol during parsing process. Now, remove
4342 the symbol as it is found to be an AUX register. */
4343 if (ARC_GET_FLAG (sym) & ARC_FLAG_AUX)
4344 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
4345 }
4346
4347 /* Now do generic ELF adjustments. */
4348 elf_adjust_symtab ();
4349}
b99747ae
CZ		 4350
4351static void
4352tokenize_extinsn (extInstruction_t *einsn)
4353{
4354 char *p, c;
4355 char *insn_name;
4356 unsigned char major_opcode;
4357 unsigned char sub_opcode;
4358 unsigned char syntax_class = 0;
4359 unsigned char syntax_class_modifiers = 0;
4360 unsigned char suffix_class = 0;
4361 unsigned int i;
4362
4363 SKIP_WHITESPACE ();
4364
4365 /* 1st: get instruction name. */
4366 p = input_line_pointer;
4367 c = get_symbol_name (&p);
4368
4369 insn_name = xstrdup (p);
4370 restore_line_pointer (c);
4371
4372 /* 2nd: get major opcode. */
4373 if (*input_line_pointer != ',')
4374 {
4375 as_bad (_("expected comma after instruction name"));
4376 ignore_rest_of_line ();
4377 return;
4378 }
4379 input_line_pointer++;
4380 major_opcode = get_absolute_expression ();
4381
4382 /* 3rd: get sub-opcode. */
4383 SKIP_WHITESPACE ();
4384
4385 if (*input_line_pointer != ',')
4386 {
4387 as_bad (_("expected comma after major opcode"));
4388 ignore_rest_of_line ();
4389 return;
4390 }
4391 input_line_pointer++;
4392 sub_opcode = get_absolute_expression ();
4393
4394 /* 4th: get suffix class. */
4395 SKIP_WHITESPACE ();
4396
4397 if (*input_line_pointer != ',')
4398 {
4399 as_bad ("expected comma after sub opcode");
4400 ignore_rest_of_line ();
4401 return;
4402 }
4403 input_line_pointer++;
4404
4405 while (1)
4406 {
4407 SKIP_WHITESPACE ();
4408
4409 for (i = 0; i < ARRAY_SIZE (suffixclass); i++)
4410 {
4411 if (!strncmp (suffixclass[i].name, input_line_pointer,
4412 suffixclass[i].len))
4413 {
c810e0b8 4414 suffix_class |= suffixclass[i].attr_class;
b99747ae
CZ		 4415 input_line_pointer += suffixclass[i].len;
4416 break;
4417 }
4418 }
4419
4420 if (i == ARRAY_SIZE (suffixclass))
4421 {
4422 as_bad ("invalid suffix class");
4423 ignore_rest_of_line ();
4424 return;
4425 }
4426
4427 SKIP_WHITESPACE ();
4428
4429 if (*input_line_pointer == '|')
4430 input_line_pointer++;
4431 else
4432 break;
4433 }
4434
4435 /* 5th: get syntax class and syntax class modifiers. */
4436 if (*input_line_pointer != ',')
4437 {
4438 as_bad ("expected comma after suffix class");
4439 ignore_rest_of_line ();
4440 return;
4441 }
4442 input_line_pointer++;
4443
4444 while (1)
4445 {
4446 SKIP_WHITESPACE ();
4447
4448 for (i = 0; i < ARRAY_SIZE (syntaxclassmod); i++)
4449 {
4450 if (!strncmp (syntaxclassmod[i].name,
4451 input_line_pointer,
4452 syntaxclassmod[i].len))
4453 {
c810e0b8 4454 syntax_class_modifiers |= syntaxclassmod[i].attr_class;
b99747ae
CZ		 4455 input_line_pointer += syntaxclassmod[i].len;
4456 break;
4457 }
4458 }
4459
4460 if (i == ARRAY_SIZE (syntaxclassmod))
4461 {
4462 for (i = 0; i < ARRAY_SIZE (syntaxclass); i++)
4463 {
4464 if (!strncmp (syntaxclass[i].name,
4465 input_line_pointer,
4466 syntaxclass[i].len))
4467 {
c810e0b8 4468 syntax_class |= syntaxclass[i].attr_class;
b99747ae
CZ		 4469 input_line_pointer += syntaxclass[i].len;
4470 break;
4471 }
4472 }
4473
4474 if (i == ARRAY_SIZE (syntaxclass))
4475 {
4476 as_bad ("missing syntax class");
4477 ignore_rest_of_line ();
4478 return;
4479 }
4480 }
4481
4482 SKIP_WHITESPACE ();
4483
4484 if (*input_line_pointer == '|')
4485 input_line_pointer++;
4486 else
4487 break;
4488 }
4489
4490 demand_empty_rest_of_line ();
4491
4492 einsn->name = insn_name;
4493 einsn->major = major_opcode;
4494 einsn->minor = sub_opcode;
4495 einsn->syntax = syntax_class;
4496 einsn->modsyn = syntax_class_modifiers;
4497 einsn->suffix = suffix_class;
4498 einsn->flags = syntax_class
4499 | (syntax_class_modifiers & ARC_OP1_IMM_IMPLIED ? 0x10 : 0);
4500}
4501
4502/* Generate an extension section. */
4503
4504static int
4505arc_set_ext_seg (void)
4506{
4507 if (!arcext_section)
4508 {
4509 arcext_section = subseg_new (".arcextmap", 0);
4510 bfd_set_section_flags (stdoutput, arcext_section,
4511 SEC_READONLY | SEC_HAS_CONTENTS);
4512 }
4513 else
4514 subseg_set (arcext_section, 0);
4515 return 1;
4516}
4517
4518/* Create an extension instruction description in the arc extension
4519 section of the output file.
4520 The structure for an instruction is like this:
4521 [0]: Length of the record.
4522 [1]: Type of the record.
4523
4524 [2]: Major opcode.
4525 [3]: Sub-opcode.
4526 [4]: Syntax (flags).
4527 [5]+ Name instruction.
4528
4529 The sequence is terminated by an empty entry. */
4530
4531static void
4532create_extinst_section (extInstruction_t *einsn)
4533{
4534
4535 segT old_sec = now_seg;
4536 int old_subsec = now_subseg;
4537 char *p;
4538 int name_len = strlen (einsn->name);
4539
4540 arc_set_ext_seg ();
4541
4542 p = frag_more (1);
4543 *p = 5 + name_len + 1;
4544 p = frag_more (1);
4545 *p = EXT_INSTRUCTION;
4546 p = frag_more (1);
4547 *p = einsn->major;
4548 p = frag_more (1);
4549 *p = einsn->minor;
4550 p = frag_more (1);
4551 *p = einsn->flags;
4552 p = frag_more (name_len + 1);
4553 strcpy (p, einsn->name);
4554
4555 subseg_set (old_sec, old_subsec);
4556}
4557
4558/* Handler .extinstruction pseudo-op. */
4559
4560static void
4561arc_extinsn (int ignore ATTRIBUTE_UNUSED)
4562{
4563 extInstruction_t einsn;
4564 struct arc_opcode *arc_ext_opcodes;
4565 const char *errmsg = NULL;
4566 unsigned char moplow, mophigh;
4567
4568 memset (&einsn, 0, sizeof (einsn));
4569 tokenize_extinsn (&einsn);
4570
4571 /* Check if the name is already used. */
4572 if (arc_find_opcode (einsn.name))
4573 as_warn (_("Pseudocode already used %s"), einsn.name);
4574
4575 /* Check the opcode ranges. */
4576 moplow = 0x05;
bb65a718
AB		 4577 mophigh = (selected_cpu.flags & (ARC_OPCODE_ARCv2EM
4578 | ARC_OPCODE_ARCv2HS)) ? 0x07 : 0x0a;
b99747ae
CZ		 4579
4580 if ((einsn.major > mophigh) || (einsn.major < moplow))
4581 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow, mophigh);
4582
4583 if ((einsn.minor > 0x3f) && (einsn.major != 0x0a)
4584 && (einsn.major != 5) && (einsn.major != 9))
4585 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4586
945e0f82 4587 switch (einsn.syntax & ARC_SYNTAX_MASK)
b99747ae
CZ		 4588 {
4589 case ARC_SYNTAX_3OP:
4590 if (einsn.modsyn & ARC_OP1_IMM_IMPLIED)
4591 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4592 break;
4593 case ARC_SYNTAX_2OP:
945e0f82
CZ		 4594 case ARC_SYNTAX_1OP:
4595 case ARC_SYNTAX_NOP:
b99747ae
CZ		 4596 if (einsn.modsyn & ARC_OP1_MUST_BE_IMM)
4597 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4598 break;
4599 default:
4600 break;
4601 }
4602
bb65a718 4603 arc_ext_opcodes = arcExtMap_genOpcode (&einsn, selected_cpu.flags, &errmsg);
b99747ae
CZ		 4604 if (arc_ext_opcodes == NULL)
4605 {
4606 if (errmsg)
4607 as_fatal ("%s", errmsg);
4608 else
4609 as_fatal (_("Couldn't generate extension instruction opcodes"));
4610 }
4611 else if (errmsg)
4612 as_warn ("%s", errmsg);
4613
4614 /* Insert the extension instruction. */
4615 arc_insert_opcode ((const struct arc_opcode *) arc_ext_opcodes);
4616
4617 create_extinst_section (&einsn);
4618}
4619
06911889 4620static bfd_boolean
f36e33da
CZ		 4621tokenize_extregister (extRegister_t *ereg, int opertype)
4622{
4623 char *name;
4624 char *mode;
4625 char c;
4626 char *p;
4627 int number, imode = 0;
4628 bfd_boolean isCore_p = (opertype == EXT_CORE_REGISTER) ? TRUE : FALSE;
4629 bfd_boolean isReg_p = (opertype == EXT_CORE_REGISTER
4630 || opertype == EXT_AUX_REGISTER) ? TRUE : FALSE;
4631
4632 /* 1st: get register name. */
4633 SKIP_WHITESPACE ();
4634 p = input_line_pointer;
4635 c = get_symbol_name (&p);
4636
4637 name = xstrdup (p);
4638 restore_line_pointer (c);
4639
4640 /* 2nd: get register number. */
4641 SKIP_WHITESPACE ();
4642
4643 if (*input_line_pointer != ',')
4644 {
06911889 4645 as_bad (_("expected comma after name"));
f36e33da
CZ		 4646 ignore_rest_of_line ();
4647 free (name);
06911889 4648 return FALSE;
f36e33da
CZ		 4649 }
4650 input_line_pointer++;
4651 number = get_absolute_expression ();
4652
06911889
CZ		 4653 if ((number < 0)
4654 && (opertype != EXT_AUX_REGISTER))
f36e33da 4655 {
06911889
CZ		 4656 as_bad (_("%s second argument cannot be a negative number %d"),
4657 isCore_p ? "extCoreRegister's" : "extCondCode's",
4658 number);
f36e33da
CZ		 4659 ignore_rest_of_line ();
4660 free (name);
06911889 4661 return FALSE;
f36e33da
CZ		 4662 }
4663
4664 if (isReg_p)
4665 {
4666 /* 3rd: get register mode. */
4667 SKIP_WHITESPACE ();
4668
4669 if (*input_line_pointer != ',')
4670 {
4671 as_bad (_("expected comma after register number"));
4672 ignore_rest_of_line ();
4673 free (name);
06911889 4674 return FALSE;
f36e33da
CZ		 4675 }
4676
4677 input_line_pointer++;
4678 mode = input_line_pointer;
4679
4680 if (!strncmp (mode, "r|w", 3))
4681 {
4682 imode = 0;
4683 input_line_pointer += 3;
4684 }
4685 else if (!strncmp (mode, "r", 1))
4686 {
4687 imode = ARC_REGISTER_READONLY;
4688 input_line_pointer += 1;
4689 }
4690 else if (strncmp (mode, "w", 1))
4691 {
4692 as_bad (_("invalid mode"));
4693 ignore_rest_of_line ();
4694 free (name);
06911889 4695 return FALSE;
f36e33da
CZ		 4696 }
4697 else
4698 {
4699 imode = ARC_REGISTER_WRITEONLY;
4700 input_line_pointer += 1;
4701 }
4702 }
4703
4704 if (isCore_p)
4705 {
4706 /* 4th: get core register shortcut. */
4707 SKIP_WHITESPACE ();
4708 if (*input_line_pointer != ',')
4709 {
4710 as_bad (_("expected comma after register mode"));
4711 ignore_rest_of_line ();
4712 free (name);
06911889 4713 return FALSE;
f36e33da
CZ		 4714 }
4715
4716 input_line_pointer++;
4717
4718 if (!strncmp (input_line_pointer, "cannot_shortcut", 15))
4719 {
4720 imode |= ARC_REGISTER_NOSHORT_CUT;
4721 input_line_pointer += 15;
4722 }
4723 else if (strncmp (input_line_pointer, "can_shortcut", 12))
4724 {
4725 as_bad (_("shortcut designator invalid"));
4726 ignore_rest_of_line ();
4727 free (name);
06911889 4728 return FALSE;
f36e33da
CZ		 4729 }
4730 else
4731 {
4732 input_line_pointer += 12;
4733 }
4734 }
4735 demand_empty_rest_of_line ();
4736
4737 ereg->name = name;
4738 ereg->number = number;
4739 ereg->imode = imode;
06911889 4740 return TRUE;
f36e33da
CZ		 4741}
4742
4743/* Create an extension register/condition description in the arc
4744 extension section of the output file.
4745
4746 The structure for an instruction is like this:
4747 [0]: Length of the record.
4748 [1]: Type of the record.
4749
4750 For core regs and condition codes:
4751 [2]: Value.
4752 [3]+ Name.
4753
33eaf5de 4754 For auxiliary registers:
f36e33da
CZ		 4755 [2..5]: Value.
4756 [6]+ Name
4757
4758 The sequence is terminated by an empty entry. */
4759
4760static void
4761create_extcore_section (extRegister_t *ereg, int opertype)
4762{
4763 segT old_sec = now_seg;
4764 int old_subsec = now_subseg;
4765 char *p;
4766 int name_len = strlen (ereg->name);
4767
4768 arc_set_ext_seg ();
4769
4770 switch (opertype)
4771 {
4772 case EXT_COND_CODE:
4773 case EXT_CORE_REGISTER:
4774 p = frag_more (1);
4775 *p = 3 + name_len + 1;
4776 p = frag_more (1);
4777 *p = opertype;
4778 p = frag_more (1);
4779 *p = ereg->number;
4780 break;
4781 case EXT_AUX_REGISTER:
4782 p = frag_more (1);
4783 *p = 6 + name_len + 1;
4784 p = frag_more (1);
4785 *p = EXT_AUX_REGISTER;
4786 p = frag_more (1);
4787 *p = (ereg->number >> 24) & 0xff;
4788 p = frag_more (1);
4789 *p = (ereg->number >> 16) & 0xff;
4790 p = frag_more (1);
4791 *p = (ereg->number >> 8) & 0xff;
4792 p = frag_more (1);
4793 *p = (ereg->number) & 0xff;
4794 break;
4795 default:
4796 break;
4797 }
4798
4799 p = frag_more (name_len + 1);
4800 strcpy (p, ereg->name);
4801
4802 subseg_set (old_sec, old_subsec);
4803}
4804
4805/* Handler .extCoreRegister pseudo-op. */
4806
4807static void
4808arc_extcorereg (int opertype)
4809{
4810 extRegister_t ereg;
4811 struct arc_aux_reg *auxr;
4812 const char *retval;
4813 struct arc_flag_operand *ccode;
4814
4815 memset (&ereg, 0, sizeof (ereg));
06911889
CZ		 4816 if (!tokenize_extregister (&ereg, opertype))
4817 return;
f36e33da
CZ		 4818
4819 switch (opertype)
4820 {
4821 case EXT_CORE_REGISTER:
4822 /* Core register. */
4823 if (ereg.number > 60)
4824 as_bad (_("core register %s value (%d) too large"), ereg.name,
4825 ereg.number);
4826 declare_register (ereg.name, ereg.number);
4827 break;
4828 case EXT_AUX_REGISTER:
4829 /* Auxiliary register. */
add39d23 4830 auxr = XNEW (struct arc_aux_reg);
f36e33da 4831 auxr->name = ereg.name;
bb65a718 4832 auxr->cpu = selected_cpu.flags;
f36e33da
CZ		 4833 auxr->subclass = NONE;
4834 auxr->address = ereg.number;
4835 retval = hash_insert (arc_aux_hash, auxr->name, (void *) auxr);
4836 if (retval)
4837 as_fatal (_("internal error: can't hash aux register '%s': %s"),
4838 auxr->name, retval);
4839 break;
4840 case EXT_COND_CODE:
4841 /* Condition code. */
4842 if (ereg.number > 31)
4843 as_bad (_("condition code %s value (%d) too large"), ereg.name,
4844 ereg.number);
4845 ext_condcode.size ++;
4846 ext_condcode.arc_ext_condcode =
add39d23
TS		 4847 XRESIZEVEC (struct arc_flag_operand, ext_condcode.arc_ext_condcode,
4848 ext_condcode.size + 1);
f36e33da
CZ		 4849 if (ext_condcode.arc_ext_condcode == NULL)
4850 as_fatal (_("Virtual memory exhausted"));
4851
4852 ccode = ext_condcode.arc_ext_condcode + ext_condcode.size - 1;
4853 ccode->name = ereg.name;
4854 ccode->code = ereg.number;
4855 ccode->bits = 5;
4856 ccode->shift = 0;
4857 ccode->favail = 0; /* not used. */
4858 ccode++;
4859 memset (ccode, 0, sizeof (struct arc_flag_operand));
4860 break;
4861 default:
4862 as_bad (_("Unknown extension"));
4863 break;
4864 }
4865 create_extcore_section (&ereg, opertype);
4866}
4867
53a346d8
CZ		 4868/* Parse a .arc_attribute directive. */
4869
4870static void
4871arc_attribute (int ignored ATTRIBUTE_UNUSED)
4872{
4873 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
4874
4875 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4876 attributes_set_explicitly[tag] = TRUE;
4877}
4878
4879/* Set an attribute if it has not already been set by the user. */
4880
4881static void
4882arc_set_attribute_int (int tag, int value)
4883{
4884 if (tag < 1
4885 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
4886 || !attributes_set_explicitly[tag])
4887 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
4888}
4889
4890static void
4891arc_set_attribute_string (int tag, const char *value)
4892{
4893 if (tag < 1
4894 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
4895 || !attributes_set_explicitly[tag])
4896 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
4897}
4898
4899/* Allocate and concatenate two strings. s1 can be NULL but not
4900 s2. s1 pointer is freed at end of this procedure. */
4901
4902static char *
4903arc_stralloc (char * s1, const char * s2)
4904{
4905 char * p;
4906 int len = 0;
4907
4908 if (s1)
4909 len = strlen (s1) + 1;
4910
4911 /* Only s1 can be null. */
4912 gas_assert (s2);
4913 len += strlen (s2) + 1;
4914
4915 p = (char *) xmalloc (len);
4916 if (p == NULL)
4917 as_fatal (_("Virtual memory exhausted"));
4918
4919 if (s1)
4920 {
4921 strcpy (p, s1);
4922 strcat (p, ",");
4923 strcat (p, s2);
4924 free (s1);
4925 }
4926 else
4927 strcpy (p, s2);
4928
4929 return p;
4930}
4931
4932/* Set the public ARC object attributes. */
4933
4934static void
4935arc_set_public_attributes (void)
4936{
4937 int base = 0;
4938 char *s = NULL;
4939 unsigned int i;
4940
4941 /* Tag_ARC_CPU_name. */
4942 arc_set_attribute_string (Tag_ARC_CPU_name, selected_cpu.name);
4943
4944 /* Tag_ARC_CPU_base. */
4945 switch (selected_cpu.eflags & EF_ARC_MACH_MSK)
4946 {
4947 case E_ARC_MACH_ARC600:
4948 case E_ARC_MACH_ARC601:
4949 base = TAG_CPU_ARC6xx;
4950 break;
4951 case E_ARC_MACH_ARC700:
4952 base = TAG_CPU_ARC7xx;
4953 break;
4954 case EF_ARC_CPU_ARCV2EM:
4955 base = TAG_CPU_ARCEM;
4956 break;
4957 case EF_ARC_CPU_ARCV2HS:
4958 base = TAG_CPU_ARCHS;
4959 break;
4960 default:
4961 base = 0;
4962 break;
4963 }
4964 if (attributes_set_explicitly[Tag_ARC_CPU_base]
4965 && (base != bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
4966 Tag_ARC_CPU_base)))
4967 as_warn (_("Overwrite explicitly set Tag_ARC_CPU_base"));
4968 bfd_elf_add_proc_attr_int (stdoutput, Tag_ARC_CPU_base, base);
4969
4970 /* Tag_ARC_ABI_osver. */
4971 if (attributes_set_explicitly[Tag_ARC_ABI_osver])
4972 {
4973 int val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
4974 Tag_ARC_ABI_osver);
4975
4976 selected_cpu.eflags = ((selected_cpu.eflags & ~EF_ARC_OSABI_MSK)
4977 | (val & 0x0f << 8));
4978 }
4979 else
4980 {
4981 arc_set_attribute_int (Tag_ARC_ABI_osver, E_ARC_OSABI_CURRENT >> 8);
4982 }
4983
4984 /* Tag_ARC_ISA_config. */
4985 arc_check_feature();
4986
4987 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
4988 if (selected_cpu.features & feature_list[i].feature)
4989 s = arc_stralloc (s, feature_list[i].attr);
4990
4991 if (s)
4992 arc_set_attribute_string (Tag_ARC_ISA_config, s);
4993
4994 /* Tag_ARC_ISA_mpy_option. */
4995 arc_set_attribute_int (Tag_ARC_ISA_mpy_option, mpy_option);
4996
4997 /* Tag_ARC_ABI_pic. */
4998 arc_set_attribute_int (Tag_ARC_ABI_pic, pic_option);
4999
5000 /* Tag_ARC_ABI_sda. */
5001 arc_set_attribute_int (Tag_ARC_ABI_sda, sda_option);
5002
5003 /* Tag_ARC_ABI_tls. */
5004 arc_set_attribute_int (Tag_ARC_ABI_tls, tls_option);
5005}
5006
5007/* Add the default contents for the .ARC.attributes section. */
5008
5009void
5010arc_md_end (void)
5011{
5012 arc_set_public_attributes ();
5013
5014 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
5015 as_fatal (_("could not set architecture and machine"));
5016
5017 bfd_set_private_flags (stdoutput, selected_cpu.eflags);
5018}
5019
5020void arc_copy_symbol_attributes (symbolS *dest, symbolS *src)
5021{
5022 ARC_GET_FLAG (dest) = ARC_GET_FLAG (src);
5023}
5024
5025int arc_convert_symbolic_attribute (const char *name)
5026{
5027 static const struct
5028 {
5029 const char * name;
5030 const int tag;
5031 }
5032 attribute_table[] =
5033 {
5034#define T(tag) {#tag, tag}
5035 T (Tag_ARC_PCS_config),
5036 T (Tag_ARC_CPU_base),
5037 T (Tag_ARC_CPU_variation),
5038 T (Tag_ARC_CPU_name),
5039 T (Tag_ARC_ABI_rf16),
5040 T (Tag_ARC_ABI_osver),
5041 T (Tag_ARC_ABI_sda),
5042 T (Tag_ARC_ABI_pic),
5043 T (Tag_ARC_ABI_tls),
5044 T (Tag_ARC_ABI_enumsize),
5045 T (Tag_ARC_ABI_exceptions),
5046 T (Tag_ARC_ABI_double_size),
5047 T (Tag_ARC_ISA_config),
5048 T (Tag_ARC_ISA_apex),
5049 T (Tag_ARC_ISA_mpy_option)
5050#undef T
5051 };
5052 unsigned int i;
5053
5054 if (name == NULL)
5055 return -1;
5056
5057 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
5058 if (streq (name, attribute_table[i].name))
5059 return attribute_table[i].tag;
5060
5061 return -1;
5062}
5063
b99747ae
CZ		 5064/* Local variables:
5065 eval: (c-set-style "gnu")
5066 indent-tabs-mode: t
5067 End: */
GDB Binutils - Deliverables
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