projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ld -r script fixes
[deliverable/binutils-gdb.git] / gas / config / tc-arc.c
CommitLineData
252b5132 1/* tc-arc.c -- Assembler for the ARC
219d1afa 2 Copyright (C) 1994-2018 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19203624 19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
252b5132 23#include "as.h"
886a2506 24#include "subsegs.h"
a161fe53 25#include "struc-symbol.h"
886a2506 26#include "dwarf2dbg.h"
726c18e1 27#include "dw2gencfi.h"
3882b010 28#include "safe-ctype.h"
886a2506 29
252b5132 30#include "opcode/arc.h"
53a346d8 31#include "opcode/arc-attrs.h"
252b5132 32#include "elf/arc.h"
b99747ae 33#include "../opcodes/arc-ext.h"
252b5132 34
886a2506 35/* Defines section. */
0d2bcfaf 36
886a2506
NC		 37#define MAX_INSN_FIXUPS 2
38#define MAX_CONSTR_STR 20
4670103e 39#define FRAG_MAX_GROWTH 8
0d2bcfaf 40
886a2506
NC		 41#ifdef DEBUG
42# define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
43#else
44# define pr_debug(fmt, args...)
45#endif
46
47#define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
48#define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
db18dbab
GM		 49#define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) \
50 && (SUB_OPCODE (x) == 0x28))
886a2506
NC		 51
52/* Equal to MAX_PRECISION in atof-ieee.c. */
53#define MAX_LITTLENUMS 6
54
9004b6bd
AB		 55#ifndef TARGET_WITH_CPU
56#define TARGET_WITH_CPU "arc700"
57#endif /* TARGET_WITH_CPU */
58
53a346d8
CZ		 59#define ARC_GET_FLAG(s) (*symbol_get_tc (s))
60#define ARC_SET_FLAG(s,v) (*symbol_get_tc (s) |= (v))
61#define streq(a, b) (strcmp (a, b) == 0)
62
4670103e
CZ		 63/* Enum used to enumerate the relaxable ins operands. */
64enum rlx_operand_type
65{
66 EMPTY = 0,
67 REGISTER,
68 REGISTER_S, /* Register for short instruction(s). */
69 REGISTER_NO_GP, /* Is a register but not gp register specifically. */
70 REGISTER_DUP, /* Duplication of previous operand of type register. */
71 IMMEDIATE,
72 BRACKET
73};
74
75enum arc_rlx_types
76{
77 ARC_RLX_NONE = 0,
78 ARC_RLX_BL_S,
79 ARC_RLX_BL,
80 ARC_RLX_B_S,
81 ARC_RLX_B,
82 ARC_RLX_ADD_U3,
83 ARC_RLX_ADD_U6,
84 ARC_RLX_ADD_LIMM,
85 ARC_RLX_LD_U7,
86 ARC_RLX_LD_S9,
87 ARC_RLX_LD_LIMM,
88 ARC_RLX_MOV_U8,
89 ARC_RLX_MOV_S12,
90 ARC_RLX_MOV_LIMM,
91 ARC_RLX_SUB_U3,
92 ARC_RLX_SUB_U6,
93 ARC_RLX_SUB_LIMM,
94 ARC_RLX_MPY_U6,
95 ARC_RLX_MPY_LIMM,
96 ARC_RLX_MOV_RU6,
97 ARC_RLX_MOV_RLIMM,
98 ARC_RLX_ADD_RRU6,
99 ARC_RLX_ADD_RRLIMM,
100};
101
886a2506
NC		 102/* Macros section. */
103
104#define regno(x) ((x) & 0x3F)
105#define is_ir_num(x) (((x) & ~0x3F) == 0)
8ddf6b2a
CZ		 106#define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
107#define is_spfp_p(op) (((sc) == SPX))
108#define is_dpfp_p(op) (((sc) == DPX))
109#define is_fpuda_p(op) (((sc) == DPA))
cf9bdae9 110#define is_br_jmp_insn_p(op) (((op)->insn_class == BRANCH \
111 || (op)->insn_class == JUMP \
112 || (op)->insn_class == BRCC \
113 || (op)->insn_class == BBIT0 \
114 || (op)->insn_class == BBIT1 \
115 || (op)->insn_class == BI \
116 || (op)->insn_class == EI \
117 || (op)->insn_class == ENTER \
118 || (op)->insn_class == JLI \
119 || (op)->insn_class == LOOP \
120 || (op)->insn_class == LEAVE \
121 ))
c810e0b8 122#define is_kernel_insn_p(op) (((op)->insn_class == KERNEL))
bdd582db 123#define is_nps400_p(op) (((sc) == NPS400))
0d2bcfaf 124
886a2506
NC		 125/* Generic assembler global variables which must be defined by all
126 targets. */
0d2bcfaf 127
886a2506 128/* Characters which always start a comment. */
252b5132
RH		 129const char comment_chars[] = "#;";
130
886a2506 131/* Characters which start a comment at the beginning of a line. */
252b5132
RH		 132const char line_comment_chars[] = "#";
133
886a2506
NC		 134/* Characters which may be used to separate multiple commands on a
135 single line. */
136const char line_separator_chars[] = "`";
252b5132 137
886a2506
NC		 138/* Characters which are used to indicate an exponent in a floating
139 point number. */
252b5132
RH		 140const char EXP_CHARS[] = "eE";
141
bcee8eb8
AM		 142/* Chars that mean this number is a floating point constant
143 As in 0f12.456 or 0d1.2345e12. */
252b5132
RH		 144const char FLT_CHARS[] = "rRsSfFdD";
145
146/* Byte order. */
147extern int target_big_endian;
148const char *arc_target_format = DEFAULT_TARGET_FORMAT;
149static int byte_order = DEFAULT_BYTE_ORDER;
150
b99747ae
CZ		 151/* Arc extension section. */
152static segT arcext_section;
153
4670103e
CZ		 154/* By default relaxation is disabled. */
155static int relaxation_state = 0;
156
886a2506 157extern int arc_get_mach (char *);
0d2bcfaf 158
4670103e 159/* Forward declarations. */
886a2506
NC		 160static void arc_lcomm (int);
161static void arc_option (int);
162static void arc_extra_reloc (int);
b99747ae 163static void arc_extinsn (int);
f36e33da 164static void arc_extcorereg (int);
53a346d8 165static void arc_attribute (int);
4670103e 166
886a2506 167const pseudo_typeS md_pseudo_table[] =
6f4b1afc
CM		 168{
169 /* Make sure that .word is 32 bits. */
170 { "word", cons, 4 },
886a2506 171
6f4b1afc
CM		 172 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
173 { "lcomm", arc_lcomm, 0 },
174 { "lcommon", arc_lcomm, 0 },
175 { "cpu", arc_option, 0 },
252b5132 176
53a346d8 177 { "arc_attribute", arc_attribute, 0 },
f36e33da
CZ		 178 { "extinstruction", arc_extinsn, 0 },
179 { "extcoreregister", arc_extcorereg, EXT_CORE_REGISTER },
180 { "extauxregister", arc_extcorereg, EXT_AUX_REGISTER },
181 { "extcondcode", arc_extcorereg, EXT_COND_CODE },
b99747ae 182
6f4b1afc
CM		 183 { "tls_gd_ld", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_LD },
184 { "tls_gd_call", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_CALL },
886a2506 185
6f4b1afc
CM		 186 { NULL, NULL, 0 }
187};
252b5132 188
252b5132 189const char *md_shortopts = "";
ea1562b3
NC		 190
191enum options
6f4b1afc
CM		 192{
193 OPTION_EB = OPTION_MD_BASE,
194 OPTION_EL,
195
196 OPTION_ARC600,
197 OPTION_ARC601,
198 OPTION_ARC700,
199 OPTION_ARCEM,
200 OPTION_ARCHS,
201
202 OPTION_MCPU,
203 OPTION_CD,
4670103e 204 OPTION_RELAX,
bdd582db 205 OPTION_NPS400,
6f4b1afc 206
ce440d63
GM		 207 OPTION_SPFP,
208 OPTION_DPFP,
209 OPTION_FPUDA,
210
6f4b1afc
CM		 211 /* The following options are deprecated and provided here only for
212 compatibility reasons. */
213 OPTION_USER_MODE,
214 OPTION_LD_EXT_MASK,
215 OPTION_SWAP,
216 OPTION_NORM,
217 OPTION_BARREL_SHIFT,
218 OPTION_MIN_MAX,
219 OPTION_NO_MPY,
220 OPTION_EA,
221 OPTION_MUL64,
222 OPTION_SIMD,
6f4b1afc
CM		 223 OPTION_XMAC_D16,
224 OPTION_XMAC_24,
225 OPTION_DSP_PACKA,
226 OPTION_CRC,
227 OPTION_DVBF,
228 OPTION_TELEPHONY,
229 OPTION_XYMEMORY,
230 OPTION_LOCK,
231 OPTION_SWAPE,
ce440d63 232 OPTION_RTSC
6f4b1afc 233};
ea1562b3
NC		 234
235struct option md_longopts[] =
6f4b1afc
CM		 236{
237 { "EB", no_argument, NULL, OPTION_EB },
238 { "EL", no_argument, NULL, OPTION_EL },
239 { "mcpu", required_argument, NULL, OPTION_MCPU },
240 { "mA6", no_argument, NULL, OPTION_ARC600 },
24b368f8
CZ		 241 { "mARC600", no_argument, NULL, OPTION_ARC600 },
242 { "mARC601", no_argument, NULL, OPTION_ARC601 },
243 { "mARC700", no_argument, NULL, OPTION_ARC700 },
6f4b1afc
CM		 244 { "mA7", no_argument, NULL, OPTION_ARC700 },
245 { "mEM", no_argument, NULL, OPTION_ARCEM },
246 { "mHS", no_argument, NULL, OPTION_ARCHS },
247 { "mcode-density", no_argument, NULL, OPTION_CD },
4670103e 248 { "mrelax", no_argument, NULL, OPTION_RELAX },
bdd582db 249 { "mnps400", no_argument, NULL, OPTION_NPS400 },
6f4b1afc 250
ce440d63
GM		 251 /* Floating point options */
252 { "mspfp", no_argument, NULL, OPTION_SPFP},
253 { "mspfp-compact", no_argument, NULL, OPTION_SPFP},
254 { "mspfp_compact", no_argument, NULL, OPTION_SPFP},
255 { "mspfp-fast", no_argument, NULL, OPTION_SPFP},
256 { "mspfp_fast", no_argument, NULL, OPTION_SPFP},
257 { "mdpfp", no_argument, NULL, OPTION_DPFP},
258 { "mdpfp-compact", no_argument, NULL, OPTION_DPFP},
259 { "mdpfp_compact", no_argument, NULL, OPTION_DPFP},
260 { "mdpfp-fast", no_argument, NULL, OPTION_DPFP},
261 { "mdpfp_fast", no_argument, NULL, OPTION_DPFP},
262 { "mfpuda", no_argument, NULL, OPTION_FPUDA},
263
6f4b1afc
CM		 264 /* The following options are deprecated and provided here only for
265 compatibility reasons. */
266 { "mav2em", no_argument, NULL, OPTION_ARCEM },
267 { "mav2hs", no_argument, NULL, OPTION_ARCHS },
268 { "muser-mode-only", no_argument, NULL, OPTION_USER_MODE },
269 { "mld-extension-reg-mask", required_argument, NULL, OPTION_LD_EXT_MASK },
270 { "mswap", no_argument, NULL, OPTION_SWAP },
271 { "mnorm", no_argument, NULL, OPTION_NORM },
272 { "mbarrel-shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
273 { "mbarrel_shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
274 { "mmin-max", no_argument, NULL, OPTION_MIN_MAX },
275 { "mmin_max", no_argument, NULL, OPTION_MIN_MAX },
276 { "mno-mpy", no_argument, NULL, OPTION_NO_MPY },
277 { "mea", no_argument, NULL, OPTION_EA },
278 { "mEA", no_argument, NULL, OPTION_EA },
279 { "mmul64", no_argument, NULL, OPTION_MUL64 },
280 { "msimd", no_argument, NULL, OPTION_SIMD},
6f4b1afc
CM		 281 { "mmac-d16", no_argument, NULL, OPTION_XMAC_D16},
282 { "mmac_d16", no_argument, NULL, OPTION_XMAC_D16},
283 { "mmac-24", no_argument, NULL, OPTION_XMAC_24},
284 { "mmac_24", no_argument, NULL, OPTION_XMAC_24},
285 { "mdsp-packa", no_argument, NULL, OPTION_DSP_PACKA},
286 { "mdsp_packa", no_argument, NULL, OPTION_DSP_PACKA},
287 { "mcrc", no_argument, NULL, OPTION_CRC},
288 { "mdvbf", no_argument, NULL, OPTION_DVBF},
289 { "mtelephony", no_argument, NULL, OPTION_TELEPHONY},
290 { "mxy", no_argument, NULL, OPTION_XYMEMORY},
291 { "mlock", no_argument, NULL, OPTION_LOCK},
292 { "mswape", no_argument, NULL, OPTION_SWAPE},
293 { "mrtsc", no_argument, NULL, OPTION_RTSC},
6f4b1afc
CM		 294
295 { NULL, no_argument, NULL, 0 }
296};
252b5132 297
886a2506 298size_t md_longopts_size = sizeof (md_longopts);
0d2bcfaf 299
886a2506 300/* Local data and data types. */
252b5132 301
886a2506
NC		 302/* Used since new relocation types are introduced in this
303 file (DUMMY_RELOC_LITUSE_*). */
304typedef int extended_bfd_reloc_code_real_type;
252b5132 305
886a2506 306struct arc_fixup
252b5132 307{
886a2506 308 expressionS exp;
252b5132 309
886a2506 310 extended_bfd_reloc_code_real_type reloc;
252b5132 311
886a2506
NC		 312 /* index into arc_operands. */
313 unsigned int opindex;
252b5132 314
886a2506
NC		 315 /* PC-relative, used by internals fixups. */
316 unsigned char pcrel;
252b5132 317
886a2506
NC		 318 /* TRUE if this fixup is for LIMM operand. */
319 bfd_boolean islong;
320};
252b5132 321
886a2506
NC		 322struct arc_insn
323{
bdfe53e3 324 unsigned long long int insn;
886a2506
NC		 325 int nfixups;
326 struct arc_fixup fixups[MAX_INSN_FIXUPS];
327 long limm;
91fdca6f 328 unsigned int len; /* Length of instruction in bytes. */
886a2506
NC		 329 bfd_boolean has_limm; /* Boolean value: TRUE if limm field is
330 valid. */
4670103e
CZ		 331 bfd_boolean relax; /* Boolean value: TRUE if needs
332 relaxation. */
886a2506 333};
ea1562b3 334
886a2506
NC		 335/* Structure to hold any last two instructions. */
336static struct arc_last_insn
252b5132 337{
886a2506
NC		 338 /* Saved instruction opcode. */
339 const struct arc_opcode *opcode;
252b5132 340
886a2506
NC		 341 /* Boolean value: TRUE if current insn is short. */
342 bfd_boolean has_limm;
252b5132 343
886a2506
NC		 344 /* Boolean value: TRUE if current insn has delay slot. */
345 bfd_boolean has_delay_slot;
346} arc_last_insns[2];
252b5132 347
b99747ae
CZ		 348/* Extension instruction suffix classes. */
349typedef struct
350{
351 const char *name;
352 int len;
c810e0b8 353 int attr_class;
b99747ae
CZ		 354} attributes_t;
355
356static const attributes_t suffixclass[] =
357{
358 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG },
359 { "SUFFIX_COND", 11, ARC_SUFFIX_COND },
360 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE }
361};
362
363/* Extension instruction syntax classes. */
364static const attributes_t syntaxclass[] =
365{
366 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP },
945e0f82
CZ		 367 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP },
368 { "SYNTAX_1OP", 10, ARC_SYNTAX_1OP },
369 { "SYNTAX_NOP", 10, ARC_SYNTAX_NOP }
b99747ae
CZ		 370};
371
372/* Extension instruction syntax classes modifiers. */
373static const attributes_t syntaxclassmod[] =
374{
375 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED },
376 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM }
377};
378
f36e33da
CZ		 379/* Extension register type. */
380typedef struct
381{
382 char *name;
383 int number;
384 int imode;
385} extRegister_t;
386
387/* A structure to hold the additional conditional codes. */
388static struct
389{
390 struct arc_flag_operand *arc_ext_condcode;
391 int size;
392} ext_condcode = { NULL, 0 };
393
da5be039
AB		 394/* Structure to hold an entry in ARC_OPCODE_HASH. */
395struct arc_opcode_hash_entry
396{
397 /* The number of pointers in the OPCODE list. */
398 size_t count;
399
400 /* Points to a list of opcode pointers. */
401 const struct arc_opcode **opcode;
402};
403
1328504b
AB		 404/* Structure used for iterating through an arc_opcode_hash_entry. */
405struct arc_opcode_hash_entry_iterator
406{
407 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
408 size_t index;
409
410 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
411 returned by this iterator. */
412 const struct arc_opcode *opcode;
413};
414
4670103e
CZ		 415/* Forward declaration. */
416static void assemble_insn
417 (const struct arc_opcode *, const expressionS *, int,
418 const struct arc_flags *, int, struct arc_insn *);
419
bb65a718
AB		 420/* The selection of the machine type can come from different sources. This
421 enum is used to track how the selection was made in order to perform
422 error checks. */
423enum mach_selection_type
424 {
425 MACH_SELECTION_NONE,
426 MACH_SELECTION_FROM_DEFAULT,
427 MACH_SELECTION_FROM_CPU_DIRECTIVE,
428 MACH_SELECTION_FROM_COMMAND_LINE
429 };
430
431/* How the current machine type was selected. */
432static enum mach_selection_type mach_selection_mode = MACH_SELECTION_NONE;
0d2bcfaf 433
886a2506
NC		 434/* The hash table of instruction opcodes. */
435static struct hash_control *arc_opcode_hash;
0d2bcfaf 436
886a2506
NC		 437/* The hash table of register symbols. */
438static struct hash_control *arc_reg_hash;
252b5132 439
f36e33da
CZ		 440/* The hash table of aux register symbols. */
441static struct hash_control *arc_aux_hash;
442
db18dbab
GM		 443/* The hash table of address types. */
444static struct hash_control *arc_addrtype_hash;
445
a9752fdf
CZ		 446#define ARC_CPU_TYPE_A6xx(NAME,EXTRA) \
447 { #NAME, ARC_OPCODE_ARC600, bfd_mach_arc_arc600, \
448 E_ARC_MACH_ARC600, EXTRA}
449#define ARC_CPU_TYPE_A7xx(NAME,EXTRA) \
450 { #NAME, ARC_OPCODE_ARC700, bfd_mach_arc_arc700, \
451 E_ARC_MACH_ARC700, EXTRA}
452#define ARC_CPU_TYPE_AV2EM(NAME,EXTRA) \
453 { #NAME, ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2, \
454 EF_ARC_CPU_ARCV2EM, EXTRA}
455#define ARC_CPU_TYPE_AV2HS(NAME,EXTRA) \
456 { #NAME, ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2, \
457 EF_ARC_CPU_ARCV2HS, EXTRA}
940171d0
AK		 458#define ARC_CPU_TYPE_NONE \
459 { 0, 0, 0, 0, 0 }
a9752fdf 460
886a2506
NC		 461/* A table of CPU names and opcode sets. */
462static const struct cpu_type
463{
464 const char *name;
465 unsigned flags;
466 int mach;
467 unsigned eflags;
468 unsigned features;
252b5132 469}
886a2506 470 cpu_types[] =
252b5132 471{
940171d0 472 #include "elf/arc-cpu.def"
886a2506 473};
252b5132 474
bb65a718 475/* Information about the cpu/variant we're assembling for. */
53a346d8 476static struct cpu_type selected_cpu = { 0, 0, 0, E_ARC_OSABI_CURRENT, 0 };
bb050a69 477
63741043 478/* TRUE if current assembly code uses RF16 only registers. */
479static bfd_boolean rf16_only = TRUE;
480
53a346d8
CZ		 481/* MPY option. */
482static unsigned mpy_option = 0;
483
484/* Use PIC. */
485static unsigned pic_option = 0;
486
487/* Use small data. */
488static unsigned sda_option = 0;
489
490/* Use TLS. */
491static unsigned tls_option = 0;
bb65a718 492
a9752fdf
CZ		 493/* Command line given features. */
494static unsigned cl_features = 0;
495
886a2506
NC		 496/* Used by the arc_reloc_op table. Order is important. */
497#define O_gotoff O_md1 /* @gotoff relocation. */
498#define O_gotpc O_md2 /* @gotpc relocation. */
499#define O_plt O_md3 /* @plt relocation. */
500#define O_sda O_md4 /* @sda relocation. */
501#define O_pcl O_md5 /* @pcl relocation. */
502#define O_tlsgd O_md6 /* @tlsgd relocation. */
503#define O_tlsie O_md7 /* @tlsie relocation. */
504#define O_tpoff9 O_md8 /* @tpoff9 relocation. */
505#define O_tpoff O_md9 /* @tpoff relocation. */
506#define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
507#define O_dtpoff O_md11 /* @dtpoff relocation. */
508#define O_last O_dtpoff
509
510/* Used to define a bracket as operand in tokens. */
511#define O_bracket O_md32
512
db18dbab
GM		 513/* Used to define a colon as an operand in tokens. */
514#define O_colon O_md31
515
516/* Used to define address types in nps400. */
517#define O_addrtype O_md30
518
886a2506
NC		 519/* Dummy relocation, to be sorted out. */
520#define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
521
522#define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
523
524/* A table to map the spelling of a relocation operand into an appropriate
525 bfd_reloc_code_real_type type. The table is assumed to be ordered such
526 that op-O_literal indexes into it. */
527#define ARC_RELOC_TABLE(op) \
528 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
529 ? (abort (), 0) \
530 : (int) (op) - (int) O_gotoff) ])
531
532#define DEF(NAME, RELOC, REQ) \
533 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
534
535static const struct arc_reloc_op_tag
536{
537 /* String to lookup. */
538 const char *name;
539 /* Size of the string. */
540 size_t length;
541 /* Which operator to use. */
542 operatorT op;
543 extended_bfd_reloc_code_real_type reloc;
544 /* Allows complex relocation expression like identifier@reloc +
545 const. */
546 unsigned int complex_expr : 1;
547}
548 arc_reloc_op[] =
6f4b1afc
CM		 549{
550 DEF (gotoff, BFD_RELOC_ARC_GOTOFF, 1),
551 DEF (gotpc, BFD_RELOC_ARC_GOTPC32, 0),
552 DEF (plt, BFD_RELOC_ARC_PLT32, 0),
553 DEF (sda, DUMMY_RELOC_ARC_ENTRY, 1),
554 DEF (pcl, BFD_RELOC_ARC_PC32, 1),
555 DEF (tlsgd, BFD_RELOC_ARC_TLS_GD_GOT, 0),
556 DEF (tlsie, BFD_RELOC_ARC_TLS_IE_GOT, 0),
557 DEF (tpoff9, BFD_RELOC_ARC_TLS_LE_S9, 0),
b125bd17 558 DEF (tpoff, BFD_RELOC_ARC_TLS_LE_32, 1),
6f4b1afc 559 DEF (dtpoff9, BFD_RELOC_ARC_TLS_DTPOFF_S9, 0),
05bbf016 560 DEF (dtpoff, BFD_RELOC_ARC_TLS_DTPOFF, 1),
6f4b1afc 561};
252b5132 562
886a2506
NC		 563static const int arc_num_reloc_op
564= sizeof (arc_reloc_op) / sizeof (*arc_reloc_op);
565
4670103e
CZ		 566/* Structure for relaxable instruction that have to be swapped with a
567 smaller alternative instruction. */
568struct arc_relaxable_ins
569{
570 /* Mnemonic that should be checked. */
571 const char *mnemonic_r;
572
573 /* Operands that should be checked.
574 Indexes of operands from operand array. */
575 enum rlx_operand_type operands[6];
576
577 /* Flags that should be checked. */
578 unsigned flag_classes[5];
579
580 /* Mnemonic (smaller) alternative to be used later for relaxation. */
581 const char *mnemonic_alt;
582
583 /* Index of operand that generic relaxation has to check. */
584 unsigned opcheckidx;
585
586 /* Base subtype index used. */
587 enum arc_rlx_types subtype;
588};
589
590#define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
591 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
592 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
593 (SIZE), \
594 (NEXT) } \
595
596#define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
597 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
598 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
599 (SIZE), \
600 (NEXT) } \
601
602
603/* ARC relaxation table. */
604const relax_typeS md_relax_table[] =
605{
606 /* Fake entry. */
607 {0, 0, 0, 0},
608
609 /* BL_S s13 ->
610 BL s25. */
db18dbab
GM		 611 RELAX_TABLE_ENTRY (13, 1, 2, ARC_RLX_BL),
612 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
4670103e
CZ		 613
614 /* B_S s10 ->
615 B s25. */
db18dbab
GM		 616 RELAX_TABLE_ENTRY (10, 1, 2, ARC_RLX_B),
617 RELAX_TABLE_ENTRY (25, 1, 4, ARC_RLX_NONE),
4670103e
CZ		 618
619 /* ADD_S c,b, u3 ->
620 ADD<.f> a,b,u6 ->
621 ADD<.f> a,b,limm. */
db18dbab
GM		 622 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_ADD_U6),
623 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_LIMM),
624 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 625
626 /* LD_S a, [b, u7] ->
627 LD<zz><.x><.aa><.di> a, [b, s9] ->
628 LD<zz><.x><.aa><.di> a, [b, limm] */
db18dbab
GM		 629 RELAX_TABLE_ENTRY (7, 0, 2, ARC_RLX_LD_S9),
630 RELAX_TABLE_ENTRY (9, 1, 4, ARC_RLX_LD_LIMM),
631 RELAX_TABLE_ENTRY_MAX (1, 8, ARC_RLX_NONE),
4670103e
CZ		 632
633 /* MOV_S b, u8 ->
634 MOV<.f> b, s12 ->
635 MOV<.f> b, limm. */
db18dbab
GM		 636 RELAX_TABLE_ENTRY (8, 0, 2, ARC_RLX_MOV_S12),
637 RELAX_TABLE_ENTRY (8, 0, 4, ARC_RLX_MOV_LIMM),
638 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 639
640 /* SUB_S c, b, u3 ->
641 SUB<.f> a, b, u6 ->
642 SUB<.f> a, b, limm. */
db18dbab
GM		 643 RELAX_TABLE_ENTRY (3, 0, 2, ARC_RLX_SUB_U6),
644 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_SUB_LIMM),
645 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 646
647 /* MPY<.f> a, b, u6 ->
648 MPY<.f> a, b, limm. */
db18dbab
GM		 649 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MPY_LIMM),
650 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 651
652 /* MOV<.f><.cc> b, u6 ->
653 MOV<.f><.cc> b, limm. */
db18dbab
GM		 654 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_MOV_RLIMM),
655 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 656
657 /* ADD<.f><.cc> b, b, u6 ->
658 ADD<.f><.cc> b, b, limm. */
db18dbab
GM		 659 RELAX_TABLE_ENTRY (6, 0, 4, ARC_RLX_ADD_RRLIMM),
660 RELAX_TABLE_ENTRY_MAX (0, 8, ARC_RLX_NONE),
4670103e
CZ		 661};
662
663/* Order of this table's entries matters! */
664const struct arc_relaxable_ins arc_relaxable_insns[] =
665{
666 { "bl", { IMMEDIATE }, { 0 }, "bl_s", 0, ARC_RLX_BL_S },
667 { "b", { IMMEDIATE }, { 0 }, "b_s", 0, ARC_RLX_B_S },
668 { "add", { REGISTER, REGISTER_DUP, IMMEDIATE }, { 5, 1, 0 }, "add",
669 2, ARC_RLX_ADD_RRU6},
670 { "add", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "add_s", 2,
671 ARC_RLX_ADD_U3 },
672 { "add", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "add", 2,
673 ARC_RLX_ADD_U6 },
674 { "ld", { REGISTER_S, BRACKET, REGISTER_S, IMMEDIATE, BRACKET },
675 { 0 }, "ld_s", 3, ARC_RLX_LD_U7 },
676 { "ld", { REGISTER, BRACKET, REGISTER_NO_GP, IMMEDIATE, BRACKET },
677 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9 },
678 { "mov", { REGISTER_S, IMMEDIATE }, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8 },
679 { "mov", { REGISTER, IMMEDIATE }, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12 },
680 { "mov", { REGISTER, IMMEDIATE }, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6 },
681 { "sub", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "sub_s", 2,
682 ARC_RLX_SUB_U3 },
683 { "sub", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "sub", 2,
684 ARC_RLX_SUB_U6 },
685 { "mpy", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "mpy", 2,
686 ARC_RLX_MPY_U6 },
687};
688
689const unsigned arc_num_relaxable_ins = ARRAY_SIZE (arc_relaxable_insns);
690
886a2506
NC		 691/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
692symbolS * GOT_symbol = 0;
693
694/* Set to TRUE when we assemble instructions. */
695static bfd_boolean assembling_insn = FALSE;
696
53a346d8
CZ		 697/* List with attributes set explicitly. */
698static bfd_boolean attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
699
886a2506
NC		 700/* Functions implementation. */
701
b9b47ab7
AB		 702/* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
703 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
704 are no matching entries in ARC_OPCODE_HASH. */
da5be039 705
b9b47ab7 706static const struct arc_opcode_hash_entry *
da5be039
AB		 707arc_find_opcode (const char *name)
708{
709 const struct arc_opcode_hash_entry *entry;
da5be039
AB		 710
711 entry = hash_find (arc_opcode_hash, name);
b9b47ab7 712 return entry;
da5be039
AB		 713}
714
1328504b
AB		 715/* Initialise the iterator ITER. */
716
717static void
718arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator *iter)
719{
720 iter->index = 0;
721 iter->opcode = NULL;
722}
723
724/* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
725 calls to this function. Return NULL when all ARC_OPCODE entries have
726 been returned. */
727
728static const struct arc_opcode *
729arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry *entry,
730 struct arc_opcode_hash_entry_iterator *iter)
731{
732 if (iter->opcode == NULL && iter->index == 0)
733 {
734 gas_assert (entry->count > 0);
735 iter->opcode = entry->opcode[iter->index];
736 }
737 else if (iter->opcode != NULL)
738 {
739 const char *old_name = iter->opcode->name;
740
741 iter->opcode++;
fe779266
AB		 742 if (iter->opcode->name == NULL
743 || strcmp (old_name, iter->opcode->name) != 0)
1328504b
AB		 744 {
745 iter->index++;
746 if (iter->index == entry->count)
747 iter->opcode = NULL;
748 else
749 iter->opcode = entry->opcode[iter->index];
750 }
751 }
752
753 return iter->opcode;
754}
755
b99747ae
CZ		 756/* Insert an opcode into opcode hash structure. */
757
758static void
759arc_insert_opcode (const struct arc_opcode *opcode)
760{
761 const char *name, *retval;
762 struct arc_opcode_hash_entry *entry;
763 name = opcode->name;
764
765 entry = hash_find (arc_opcode_hash, name);
766 if (entry == NULL)
767 {
add39d23 768 entry = XNEW (struct arc_opcode_hash_entry);
b99747ae
CZ		 769 entry->count = 0;
770 entry->opcode = NULL;
771
772 retval = hash_insert (arc_opcode_hash, name, (void *) entry);
773 if (retval)
774 as_fatal (_("internal error: can't hash opcode '%s': %s"),
775 name, retval);
776 }
777
add39d23
TS		 778 entry->opcode = XRESIZEVEC (const struct arc_opcode *, entry->opcode,
779 entry->count + 1);
b99747ae
CZ		 780
781 if (entry->opcode == NULL)
782 as_fatal (_("Virtual memory exhausted"));
783
784 entry->opcode[entry->count] = opcode;
785 entry->count++;
786}
787
788
bdfe53e3
AB		 789/* Like md_number_to_chars but for middle-endian values. The 4-byte limm
790 value, is encoded as 'middle-endian' for a little-endian target. This
791 function is used for regular 4, 6, and 8 byte instructions as well. */
886a2506
NC		 792
793static void
bdfe53e3 794md_number_to_chars_midend (char *buf, unsigned long long val, int n)
886a2506 795{
bdfe53e3 796 switch (n)
886a2506 797 {
bdfe53e3
AB		 798 case 2:
799 md_number_to_chars (buf, val, n);
800 break;
801 case 6:
53b6d6f5 802 md_number_to_chars (buf, (val & 0xffff00000000ull) >> 32, 2);
bdfe53e3
AB		 803 md_number_to_chars_midend (buf + 2, (val & 0xffffffff), 4);
804 break;
805 case 4:
886a2506
NC		 806 md_number_to_chars (buf, (val & 0xffff0000) >> 16, 2);
807 md_number_to_chars (buf + 2, (val & 0xffff), 2);
bdfe53e3
AB		 808 break;
809 case 8:
53b6d6f5 810 md_number_to_chars_midend (buf, (val & 0xffffffff00000000ull) >> 32, 4);
bdfe53e3
AB		 811 md_number_to_chars_midend (buf + 4, (val & 0xffffffff), 4);
812 break;
813 default:
814 abort ();
886a2506 815 }
252b5132
RH		 816}
817
bb050a69
CZ		 818/* Check if a feature is allowed for a specific CPU. */
819
820static void
821arc_check_feature (void)
822{
823 unsigned i;
824
825 if (!selected_cpu.features
826 || !selected_cpu.name)
827 return;
53a346d8
CZ		 828
829 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
830 if ((selected_cpu.features & feature_list[i].feature)
831 && !(selected_cpu.flags & feature_list[i].cpus))
832 as_bad (_("invalid %s option for %s cpu"), feature_list[i].name,
833 selected_cpu.name);
834
835 for (i = 0; i < ARRAY_SIZE (conflict_list); i++)
836 if ((selected_cpu.features & conflict_list[i]) == conflict_list[i])
837 as_bad(_("conflicting ISA extension attributes."));
bb050a69
CZ		 838}
839
24740d83 840/* Select an appropriate entry from CPU_TYPES based on ARG and initialise
bb65a718
AB		 841 the relevant static global variables. Parameter SEL describes where
842 this selection originated from. */
24740d83
AB		 843
844static void
bb65a718 845arc_select_cpu (const char *arg, enum mach_selection_type sel)
24740d83 846{
24740d83
AB		 847 int i;
848
bb65a718
AB		 849 /* We should only set a default if we've not made a selection from some
850 other source. */
851 gas_assert (sel != MACH_SELECTION_FROM_DEFAULT
852 || mach_selection_mode == MACH_SELECTION_NONE);
853
bb050a69
CZ		 854 if ((mach_selection_mode == MACH_SELECTION_FROM_CPU_DIRECTIVE)
855 && (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE))
856 as_bad (_("Multiple .cpu directives found"));
857
bb65a718 858 /* Look for a matching entry in CPU_TYPES array. */
24740d83
AB		 859 for (i = 0; cpu_types[i].name; ++i)
860 {
861 if (!strcasecmp (cpu_types[i].name, arg))
862 {
bb65a718
AB		 863 /* If a previous selection was made on the command line, then we
864 allow later selections on the command line to override earlier
865 ones. However, a selection from a '.cpu NAME' directive must
866 match the command line selection, or we give a warning. */
867 if (mach_selection_mode == MACH_SELECTION_FROM_COMMAND_LINE)
868 {
869 gas_assert (sel == MACH_SELECTION_FROM_COMMAND_LINE
870 || sel == MACH_SELECTION_FROM_CPU_DIRECTIVE);
871 if (sel == MACH_SELECTION_FROM_CPU_DIRECTIVE
872 && selected_cpu.mach != cpu_types[i].mach)
873 {
874 as_warn (_("Command-line value overrides \".cpu\" directive"));
bb65a718 875 }
bb050a69 876 return;
bb65a718
AB		 877 }
878
bb050a69
CZ		 879 /* Initialise static global data about selected machine type. */
880 selected_cpu.flags = cpu_types[i].flags;
881 selected_cpu.name = cpu_types[i].name;
a9752fdf 882 selected_cpu.features = cpu_types[i].features | cl_features;
bb050a69 883 selected_cpu.mach = cpu_types[i].mach;
53a346d8
CZ		 884 selected_cpu.eflags = ((selected_cpu.eflags & ~EF_ARC_MACH_MSK)
885 | cpu_types[i].eflags);
24740d83
AB		 886 break;
887 }
888 }
889
890 if (!cpu_types[i].name)
891 as_fatal (_("unknown architecture: %s\n"), arg);
bb050a69
CZ		 892
893 /* Check if set features are compatible with the chosen CPU. */
894 arc_check_feature ();
53a346d8 895
bb65a718 896 mach_selection_mode = sel;
24740d83
AB		 897}
898
886a2506
NC		 899/* Here ends all the ARCompact extension instruction assembling
900 stuff. */
252b5132 901
886a2506
NC		 902static void
903arc_extra_reloc (int r_type)
ea1562b3 904{
886a2506
NC		 905 char *sym_name, c;
906 symbolS *sym, *lab = NULL;
907
908 if (*input_line_pointer == '@')
909 input_line_pointer++;
910 c = get_symbol_name (&sym_name);
911 sym = symbol_find_or_make (sym_name);
912 restore_line_pointer (c);
913 if (c == ',' && r_type == BFD_RELOC_ARC_TLS_GD_LD)
914 {
915 ++input_line_pointer;
916 char *lab_name;
917 c = get_symbol_name (&lab_name);
918 lab = symbol_find_or_make (lab_name);
919 restore_line_pointer (c);
920 }
841fdfcd
CZ		 921
922 /* These relocations exist as a mechanism for the compiler to tell the
923 linker how to patch the code if the tls model is optimised. However,
924 the relocation itself does not require any space within the assembler
925 fragment, and so we pass a size of 0.
926
927 The lines that generate these relocations look like this:
928
929 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
930
931 The '.tls_gd_ld @.tdata' is processed first and generates the
932 additional relocation, while the 'bl __tls_get_addr@plt' is processed
933 second and generates the additional branch.
934
935 It is possible that the additional relocation generated by the
936 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
937 while the 'bl __tls_get_addr@plt' will be generated as the first thing
938 in the next fragment. This will be fine; both relocations will still
939 appear to be at the same address in the generated object file.
940 However, this only works as the additional relocation is generated
941 with size of 0 bytes. */
886a2506
NC		 942 fixS *fixP
943 = fix_new (frag_now, /* Which frag? */
944 frag_now_fix (), /* Where in that frag? */
841fdfcd 945 0, /* size: 1, 2, or 4 usually. */
886a2506
NC		 946 sym, /* X_add_symbol. */
947 0, /* X_add_number. */
948 FALSE, /* TRUE if PC-relative relocation. */
949 r_type /* Relocation type. */);
950 fixP->fx_subsy = lab;
951}
252b5132 952
886a2506
NC		 953static symbolS *
954arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED,
955 symbolS *symbolP, addressT size)
956{
957 addressT align = 0;
958 SKIP_WHITESPACE ();
252b5132 959
886a2506
NC		 960 if (*input_line_pointer == ',')
961 {
962 align = parse_align (1);
252b5132 963
886a2506
NC		 964 if (align == (addressT) -1)
965 return NULL;
966 }
967 else
968 {
969 if (size >= 8)
970 align = 3;
971 else if (size >= 4)
972 align = 2;
973 else if (size >= 2)
974 align = 1;
975 else
976 align = 0;
977 }
252b5132 978
886a2506
NC		 979 bss_alloc (symbolP, size, align);
980 S_CLEAR_EXTERNAL (symbolP);
ea1562b3 981
886a2506
NC		 982 return symbolP;
983}
ea1562b3 984
886a2506
NC		 985static void
986arc_lcomm (int ignore)
987{
988 symbolS *symbolP = s_comm_internal (ignore, arc_lcomm_internal);
ea1562b3 989
886a2506
NC		 990 if (symbolP)
991 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
992}
ea1562b3 993
886a2506 994/* Select the cpu we're assembling for. */
ea1562b3 995
886a2506
NC		 996static void
997arc_option (int ignore ATTRIBUTE_UNUSED)
252b5132 998{
886a2506
NC		 999 char c;
1000 char *cpu;
bb65a718 1001 const char *cpu_name;
252b5132 1002
886a2506 1003 c = get_symbol_name (&cpu);
252b5132 1004
a9752fdf 1005 cpu_name = cpu;
bb65a718
AB		 1006 if ((!strcmp ("ARC600", cpu))
1007 || (!strcmp ("ARC601", cpu))
1008 || (!strcmp ("A6", cpu)))
1009 cpu_name = "arc600";
1010 else if ((!strcmp ("ARC700", cpu))
1011 || (!strcmp ("A7", cpu)))
1012 cpu_name = "arc700";
1013 else if (!strcmp ("EM", cpu))
1014 cpu_name = "arcem";
1015 else if (!strcmp ("HS", cpu))
1016 cpu_name = "archs";
1017 else if (!strcmp ("NPS400", cpu))
1018 cpu_name = "nps400";
886a2506 1019
a9752fdf 1020 arc_select_cpu (cpu_name, MACH_SELECTION_FROM_CPU_DIRECTIVE);
24b368f8 1021
24b368f8 1022 restore_line_pointer (c);
886a2506 1023 demand_empty_rest_of_line ();
ea1562b3 1024}
252b5132 1025
886a2506
NC		 1026/* Smartly print an expression. */
1027
ea1562b3 1028static void
886a2506 1029debug_exp (expressionS *t)
ea1562b3 1030{
886a2506
NC		 1031 const char *name ATTRIBUTE_UNUSED;
1032 const char *namemd ATTRIBUTE_UNUSED;
252b5132 1033
886a2506 1034 pr_debug ("debug_exp: ");
252b5132 1035
886a2506 1036 switch (t->X_op)
252b5132 1037 {
886a2506
NC		 1038 default: name = "unknown"; break;
1039 case O_illegal: name = "O_illegal"; break;
1040 case O_absent: name = "O_absent"; break;
1041 case O_constant: name = "O_constant"; break;
1042 case O_symbol: name = "O_symbol"; break;
1043 case O_symbol_rva: name = "O_symbol_rva"; break;
1044 case O_register: name = "O_register"; break;
1045 case O_big: name = "O_big"; break;
1046 case O_uminus: name = "O_uminus"; break;
1047 case O_bit_not: name = "O_bit_not"; break;
1048 case O_logical_not: name = "O_logical_not"; break;
1049 case O_multiply: name = "O_multiply"; break;
1050 case O_divide: name = "O_divide"; break;
1051 case O_modulus: name = "O_modulus"; break;
1052 case O_left_shift: name = "O_left_shift"; break;
1053 case O_right_shift: name = "O_right_shift"; break;
1054 case O_bit_inclusive_or: name = "O_bit_inclusive_or"; break;
1055 case O_bit_or_not: name = "O_bit_or_not"; break;
1056 case O_bit_exclusive_or: name = "O_bit_exclusive_or"; break;
1057 case O_bit_and: name = "O_bit_and"; break;
1058 case O_add: name = "O_add"; break;
1059 case O_subtract: name = "O_subtract"; break;
1060 case O_eq: name = "O_eq"; break;
1061 case O_ne: name = "O_ne"; break;
1062 case O_lt: name = "O_lt"; break;
1063 case O_le: name = "O_le"; break;
1064 case O_ge: name = "O_ge"; break;
1065 case O_gt: name = "O_gt"; break;
1066 case O_logical_and: name = "O_logical_and"; break;
1067 case O_logical_or: name = "O_logical_or"; break;
1068 case O_index: name = "O_index"; break;
1069 case O_bracket: name = "O_bracket"; break;
db18dbab
GM		 1070 case O_colon: name = "O_colon"; break;
1071 case O_addrtype: name = "O_addrtype"; break;
ea1562b3 1072 }
252b5132 1073
886a2506 1074 switch (t->X_md)
ea1562b3 1075 {
886a2506
NC		 1076 default: namemd = "unknown"; break;
1077 case O_gotoff: namemd = "O_gotoff"; break;
1078 case O_gotpc: namemd = "O_gotpc"; break;
1079 case O_plt: namemd = "O_plt"; break;
1080 case O_sda: namemd = "O_sda"; break;
1081 case O_pcl: namemd = "O_pcl"; break;
1082 case O_tlsgd: namemd = "O_tlsgd"; break;
1083 case O_tlsie: namemd = "O_tlsie"; break;
1084 case O_tpoff9: namemd = "O_tpoff9"; break;
1085 case O_tpoff: namemd = "O_tpoff"; break;
1086 case O_dtpoff9: namemd = "O_dtpoff9"; break;
1087 case O_dtpoff: namemd = "O_dtpoff"; break;
ea1562b3 1088 }
252b5132 1089
886a2506
NC		 1090 pr_debug ("%s (%s, %s, %d, %s)", name,
1091 (t->X_add_symbol) ? S_GET_NAME (t->X_add_symbol) : "--",
1092 (t->X_op_symbol) ? S_GET_NAME (t->X_op_symbol) : "--",
1093 (int) t->X_add_number,
1094 (t->X_md) ? namemd : "--");
1095 pr_debug ("\n");
1096 fflush (stderr);
1097}
252b5132 1098
886a2506
NC		 1099/* Parse the arguments to an opcode. */
1100
1101static int
1102tokenize_arguments (char *str,
1103 expressionS *tok,
1104 int ntok)
1105{
1106 char *old_input_line_pointer;
1107 bfd_boolean saw_comma = FALSE;
1108 bfd_boolean saw_arg = FALSE;
1109 int brk_lvl = 0;
1110 int num_args = 0;
886a2506
NC		 1111 int i;
1112 size_t len;
1113 const struct arc_reloc_op_tag *r;
1114 expressionS tmpE;
6f4b1afc 1115 char *reloc_name, c;
886a2506
NC		 1116
1117 memset (tok, 0, sizeof (*tok) * ntok);
1118
1119 /* Save and restore input_line_pointer around this function. */
1120 old_input_line_pointer = input_line_pointer;
1121 input_line_pointer = str;
ea1562b3 1122
886a2506 1123 while (*input_line_pointer)
ea1562b3
NC		 1124 {
1125 SKIP_WHITESPACE ();
886a2506 1126 switch (*input_line_pointer)
252b5132 1127 {
886a2506
NC		 1128 case '\0':
1129 goto fini;
1130
1131 case ',':
1132 input_line_pointer++;
1133 if (saw_comma || !saw_arg)
1134 goto err;
1135 saw_comma = TRUE;
1136 break;
252b5132 1137
886a2506
NC		 1138 case '}':
1139 case ']':
1140 ++input_line_pointer;
1141 --brk_lvl;
3b889a78 1142 if (!saw_arg || num_args == ntok)
886a2506
NC		 1143 goto err;
1144 tok->X_op = O_bracket;
1145 ++tok;
1146 ++num_args;
1147 break;
ea1562b3 1148
886a2506
NC		 1149 case '{':
1150 case '[':
1151 input_line_pointer++;
3b889a78 1152 if (brk_lvl || num_args == ntok)
886a2506
NC		 1153 goto err;
1154 ++brk_lvl;
1155 tok->X_op = O_bracket;
1156 ++tok;
1157 ++num_args;
1158 break;
1159
db18dbab
GM		 1160 case ':':
1161 input_line_pointer++;
1162 if (!saw_arg || num_args == ntok)
1163 goto err;
1164 tok->X_op = O_colon;
1165 saw_arg = FALSE;
1166 ++tok;
1167 ++num_args;
1168 break;
1169
886a2506
NC		 1170 case '@':
1171 /* We have labels, function names and relocations, all
1172 starting with @ symbol. Sort them out. */
3b889a78 1173 if ((saw_arg && !saw_comma) || num_args == ntok)
886a2506
NC		 1174 goto err;
1175
1176 /* Parse @label. */
1177 tok->X_op = O_symbol;
1178 tok->X_md = O_absent;
1179 expression (tok);
1180 if (*input_line_pointer != '@')
1181 goto normalsymbol; /* This is not a relocation. */
1182
6f4b1afc
CM		 1183 relocationsym:
1184
33eaf5de 1185 /* A relocation operand has the following form
886a2506
NC		 1186 @identifier@relocation_type. The identifier is already
1187 in tok! */
1188 if (tok->X_op != O_symbol)
ea1562b3 1189 {
886a2506
NC		 1190 as_bad (_("No valid label relocation operand"));
1191 goto err;
252b5132 1192 }
886a2506
NC		 1193
1194 /* Parse @relocation_type. */
6f4b1afc
CM		 1195 input_line_pointer++;
1196 c = get_symbol_name (&reloc_name);
1197 len = input_line_pointer - reloc_name;
1198 if (len == 0)
252b5132 1199 {
886a2506
NC		 1200 as_bad (_("No relocation operand"));
1201 goto err;
252b5132 1202 }
252b5132 1203
886a2506
NC		 1204 /* Go through known relocation and try to find a match. */
1205 r = &arc_reloc_op[0];
1206 for (i = arc_num_reloc_op - 1; i >= 0; i--, r++)
6f4b1afc
CM		 1207 if (len == r->length
1208 && memcmp (reloc_name, r->name, len) == 0)
886a2506 1209 break;
886a2506 1210 if (i < 0)
252b5132 1211 {
6f4b1afc 1212 as_bad (_("Unknown relocation operand: @%s"), reloc_name);
886a2506
NC		 1213 goto err;
1214 }
1215
6f4b1afc
CM		 1216 *input_line_pointer = c;
1217 SKIP_WHITESPACE_AFTER_NAME ();
886a2506
NC		 1218 /* Extra check for TLS: base. */
1219 if (*input_line_pointer == '@')
1220 {
1221 symbolS *base;
1222 if (tok->X_op_symbol != NULL
1223 || tok->X_op != O_symbol)
252b5132 1224 {
6f4b1afc
CM		 1225 as_bad (_("Unable to parse TLS base: %s"),
1226 input_line_pointer);
886a2506 1227 goto err;
252b5132 1228 }
886a2506
NC		 1229 input_line_pointer++;
1230 char *sym_name;
6f4b1afc 1231 c = get_symbol_name (&sym_name);
886a2506
NC		 1232 base = symbol_find_or_make (sym_name);
1233 tok->X_op = O_subtract;
1234 tok->X_op_symbol = base;
1235 restore_line_pointer (c);
6f4b1afc
CM		 1236 tmpE.X_add_number = 0;
1237 }
32348c58 1238 if ((*input_line_pointer != '+')
6f4b1afc
CM		 1239 && (*input_line_pointer != '-'))
1240 {
1241 tmpE.X_add_number = 0;
ea1562b3 1242 }
6f4b1afc
CM		 1243 else
1244 {
1245 /* Parse the constant of a complex relocation expression
1246 like @identifier@reloc +/- const. */
1247 if (! r->complex_expr)
1248 {
1249 as_bad (_("@%s is not a complex relocation."), r->name);
1250 goto err;
1251 }
1252 expression (&tmpE);
1253 if (tmpE.X_op != O_constant)
1254 {
1255 as_bad (_("Bad expression: @%s + %s."),
1256 r->name, input_line_pointer);
1257 goto err;
1258 }
1259 }
1260
1261 tok->X_md = r->op;
1262 tok->X_add_number = tmpE.X_add_number;
1e07b820 1263
886a2506 1264 debug_exp (tok);
ea1562b3 1265
886a2506
NC		 1266 saw_comma = FALSE;
1267 saw_arg = TRUE;
1268 tok++;
1269 num_args++;
1270 break;
252b5132 1271
886a2506
NC		 1272 case '%':
1273 /* Can be a register. */
1274 ++input_line_pointer;
1275 /* Fall through. */
1276 default:
252b5132 1277
3b889a78 1278 if ((saw_arg && !saw_comma) || num_args == ntok)
886a2506 1279 goto err;
252b5132 1280
886a2506 1281 tok->X_op = O_absent;
6f4b1afc 1282 tok->X_md = O_absent;
886a2506 1283 expression (tok);
252b5132 1284
6f4b1afc
CM		 1285 /* Legacy: There are cases when we have
1286 identifier@relocation_type, if it is the case parse the
1287 relocation type as well. */
1288 if (*input_line_pointer == '@')
1289 goto relocationsym;
1290
886a2506
NC		 1291 normalsymbol:
1292 debug_exp (tok);
252b5132 1293
3b889a78
AB		 1294 if (tok->X_op == O_illegal
1295 || tok->X_op == O_absent
1296 || num_args == ntok)
886a2506 1297 goto err;
252b5132 1298
886a2506
NC		 1299 saw_comma = FALSE;
1300 saw_arg = TRUE;
1301 tok++;
1302 num_args++;
1303 break;
1304 }
ea1562b3 1305 }
252b5132 1306
886a2506
NC		 1307 fini:
1308 if (saw_comma || brk_lvl)
1309 goto err;
1310 input_line_pointer = old_input_line_pointer;
252b5132 1311
886a2506 1312 return num_args;
252b5132 1313
886a2506
NC		 1314 err:
1315 if (brk_lvl)
1316 as_bad (_("Brackets in operand field incorrect"));
1317 else if (saw_comma)
1318 as_bad (_("extra comma"));
1319 else if (!saw_arg)
1320 as_bad (_("missing argument"));
1321 else
1322 as_bad (_("missing comma or colon"));
1323 input_line_pointer = old_input_line_pointer;
1324 return -1;
252b5132 1325}
ea1562b3 1326
886a2506
NC		 1327/* Parse the flags to a structure. */
1328
1329static int
1330tokenize_flags (const char *str,
1331 struct arc_flags flags[],
1332 int nflg)
252b5132 1333{
886a2506
NC		 1334 char *old_input_line_pointer;
1335 bfd_boolean saw_flg = FALSE;
1336 bfd_boolean saw_dot = FALSE;
1337 int num_flags = 0;
1338 size_t flgnamelen;
252b5132 1339
886a2506 1340 memset (flags, 0, sizeof (*flags) * nflg);
0d2bcfaf 1341
886a2506
NC		 1342 /* Save and restore input_line_pointer around this function. */
1343 old_input_line_pointer = input_line_pointer;
1344 input_line_pointer = (char *) str;
0d2bcfaf 1345
886a2506
NC		 1346 while (*input_line_pointer)
1347 {
1348 switch (*input_line_pointer)
1349 {
1350 case ' ':
1351 case '\0':
1352 goto fini;
1353
1354 case '.':
1355 input_line_pointer++;
1356 if (saw_dot)
1357 goto err;
1358 saw_dot = TRUE;
1359 saw_flg = FALSE;
1360 break;
ea1562b3 1361
886a2506
NC		 1362 default:
1363 if (saw_flg && !saw_dot)
1364 goto err;
0d2bcfaf 1365
886a2506
NC		 1366 if (num_flags >= nflg)
1367 goto err;
0d2bcfaf 1368
692166c2
AB		 1369 flgnamelen = strspn (input_line_pointer,
1370 "abcdefghijklmnopqrstuvwxyz0123456789");
83cda17b 1371 if (flgnamelen > MAX_FLAG_NAME_LENGTH)
886a2506 1372 goto err;
0d2bcfaf 1373
886a2506 1374 memcpy (flags->name, input_line_pointer, flgnamelen);
0d2bcfaf 1375
886a2506
NC		 1376 input_line_pointer += flgnamelen;
1377 flags++;
1378 saw_dot = FALSE;
1379 saw_flg = TRUE;
1380 num_flags++;
1381 break;
1e07b820 1382 }
0d2bcfaf
NC		 1383 }
1384
886a2506
NC		 1385 fini:
1386 input_line_pointer = old_input_line_pointer;
1387 return num_flags;
0d2bcfaf 1388
886a2506
NC		 1389 err:
1390 if (saw_dot)
1391 as_bad (_("extra dot"));
1392 else if (!saw_flg)
1393 as_bad (_("unrecognized flag"));
1394 else
1395 as_bad (_("failed to parse flags"));
1396 input_line_pointer = old_input_line_pointer;
1397 return -1;
1398}
0d2bcfaf 1399
4670103e 1400/* Apply the fixups in order. */
0d2bcfaf 1401
4670103e
CZ		 1402static void
1403apply_fixups (struct arc_insn *insn, fragS *fragP, int fix)
886a2506 1404{
4670103e 1405 int i;
0d2bcfaf 1406
4670103e 1407 for (i = 0; i < insn->nfixups; i++)
252b5132 1408 {
4670103e
CZ		 1409 struct arc_fixup *fixup = &insn->fixups[i];
1410 int size, pcrel, offset = 0;
0d2bcfaf 1411
4670103e
CZ		 1412 /* FIXME! the reloc size is wrong in the BFD file.
1413 When it is fixed please delete me. */
91fdca6f 1414 size = ((insn->len == 2) && !fixup->islong) ? 2 : 4;
0d2bcfaf 1415
4670103e 1416 if (fixup->islong)
91fdca6f 1417 offset = insn->len;
252b5132 1418
4670103e
CZ		 1419 /* Some fixups are only used internally, thus no howto. */
1420 if ((int) fixup->reloc == 0)
1421 as_fatal (_("Unhandled reloc type"));
886a2506 1422
4670103e
CZ		 1423 if ((int) fixup->reloc < 0)
1424 {
1425 /* FIXME! the reloc size is wrong in the BFD file.
1426 When it is fixed please enable me.
91fdca6f 1427 size = ((insn->len == 2 && !fixup->islong) ? 2 : 4; */
4670103e
CZ		 1428 pcrel = fixup->pcrel;
1429 }
1430 else
1431 {
1432 reloc_howto_type *reloc_howto =
1433 bfd_reloc_type_lookup (stdoutput,
1434 (bfd_reloc_code_real_type) fixup->reloc);
1435 gas_assert (reloc_howto);
0d2bcfaf 1436
4670103e
CZ		 1437 /* FIXME! the reloc size is wrong in the BFD file.
1438 When it is fixed please enable me.
1439 size = bfd_get_reloc_size (reloc_howto); */
1440 pcrel = reloc_howto->pc_relative;
1441 }
0d2bcfaf 1442
4670103e
CZ		 1443 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1444offset %d + %d\n",
1445 fragP->fr_file, fragP->fr_line,
1446 (fixup->reloc < 0) ? "Internal" :
1447 bfd_get_reloc_code_name (fixup->reloc),
1448 pcrel ? "Y" : "N",
1449 size, fix, offset);
1450 fix_new_exp (fragP, fix + offset,
1451 size, &fixup->exp, pcrel, fixup->reloc);
0d2bcfaf 1452
4670103e
CZ		 1453 /* Check for ZOLs, and update symbol info if any. */
1454 if (LP_INSN (insn->insn))
886a2506 1455 {
4670103e
CZ		 1456 gas_assert (fixup->exp.X_add_symbol);
1457 ARC_SET_FLAG (fixup->exp.X_add_symbol, ARC_FLAG_ZOL);
886a2506
NC		 1458 }
1459 }
252b5132
RH		 1460}
1461
4670103e 1462/* Actually output an instruction with its fixup. */
886a2506 1463
4670103e
CZ		 1464static void
1465emit_insn0 (struct arc_insn *insn, char *where, bfd_boolean relax)
252b5132 1466{
4670103e 1467 char *f = where;
91fdca6f 1468 size_t total_len;
252b5132 1469
bdfe53e3
AB		 1470 pr_debug ("Emit insn : 0x%llx\n", insn->insn);
1471 pr_debug ("\tLength : 0x%d\n", insn->len);
4670103e 1472 pr_debug ("\tLong imm: 0x%lx\n", insn->limm);
0d2bcfaf 1473
4670103e 1474 /* Write out the instruction. */
91fdca6f
GM		 1475 total_len = insn->len + (insn->has_limm ? 4 : 0);
1476 if (!relax)
1477 f = frag_more (total_len);
1478
1479 md_number_to_chars_midend(f, insn->insn, insn->len);
1480
1481 if (insn->has_limm)
1482 md_number_to_chars_midend (f + insn->len, insn->limm, 4);
1483 dwarf2_emit_insn (total_len);
252b5132 1484
4670103e
CZ		 1485 if (!relax)
1486 apply_fixups (insn, frag_now, (f - frag_now->fr_literal));
1487}
252b5132 1488
4670103e
CZ		 1489static void
1490emit_insn1 (struct arc_insn *insn)
1491{
1492 /* How frag_var's args are currently configured:
1493 - rs_machine_dependent, to dictate it's a relaxation frag.
1494 - FRAG_MAX_GROWTH, maximum size of instruction
1495 - 0, variable size that might grow...unused by generic relaxation.
1496 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1497 - s, opand expression.
1498 - 0, offset but it's unused.
1499 - 0, opcode but it's unused. */
1500 symbolS *s = make_expr_symbol (&insn->fixups[0].exp);
1501 frag_now->tc_frag_data.pcrel = insn->fixups[0].pcrel;
1502
1503 if (frag_room () < FRAG_MAX_GROWTH)
1504 {
1505 /* Handle differently when frag literal memory is exhausted.
1506 This is used because when there's not enough memory left in
1507 the current frag, a new frag is created and the information
1508 we put into frag_now->tc_frag_data is disregarded. */
252b5132 1509
4670103e
CZ		 1510 struct arc_relax_type relax_info_copy;
1511 relax_substateT subtype = frag_now->fr_subtype;
252b5132 1512
4670103e
CZ		 1513 memcpy (&relax_info_copy, &frag_now->tc_frag_data,
1514 sizeof (struct arc_relax_type));
0d2bcfaf 1515
4670103e
CZ		 1516 frag_wane (frag_now);
1517 frag_grow (FRAG_MAX_GROWTH);
0d2bcfaf 1518
4670103e
CZ		 1519 memcpy (&frag_now->tc_frag_data, &relax_info_copy,
1520 sizeof (struct arc_relax_type));
252b5132 1521
4670103e
CZ		 1522 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1523 subtype, s, 0, 0);
1524 }
1525 else
1526 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1527 frag_now->fr_subtype, s, 0, 0);
1528}
252b5132 1529
4670103e
CZ		 1530static void
1531emit_insn (struct arc_insn *insn)
252b5132 1532{
4670103e
CZ		 1533 if (insn->relax)
1534 emit_insn1 (insn);
252b5132 1535 else
4670103e 1536 emit_insn0 (insn, NULL, FALSE);
252b5132
RH		 1537}
1538
4670103e 1539/* Check whether a symbol involves a register. */
252b5132 1540
4670103e
CZ		 1541static bfd_boolean
1542contains_register (symbolS *sym)
252b5132 1543{
4670103e
CZ		 1544 if (sym)
1545 {
1546 expressionS *ex = symbol_get_value_expression (sym);
252b5132 1547
4670103e
CZ		 1548 return ((O_register == ex->X_op)
1549 && !contains_register (ex->X_add_symbol)
1550 && !contains_register (ex->X_op_symbol));
1551 }
1552
1553 return FALSE;
252b5132
RH		 1554}
1555
4670103e 1556/* Returns the register number within a symbol. */
252b5132 1557
4670103e
CZ		 1558static int
1559get_register (symbolS *sym)
252b5132 1560{
4670103e
CZ		 1561 if (!contains_register (sym))
1562 return -1;
0d2bcfaf 1563
4670103e
CZ		 1564 expressionS *ex = symbol_get_value_expression (sym);
1565 return regno (ex->X_add_number);
1566}
252b5132 1567
4670103e
CZ		 1568/* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1569 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
f17c130b 1570
4670103e
CZ		 1571static bfd_boolean
1572generic_reloc_p (extended_bfd_reloc_code_real_type reloc)
1573{
1574 if (!reloc)
1575 return FALSE;
886a2506 1576
4670103e
CZ		 1577 switch (reloc)
1578 {
1579 case BFD_RELOC_ARC_SDA_LDST:
1580 case BFD_RELOC_ARC_SDA_LDST1:
1581 case BFD_RELOC_ARC_SDA_LDST2:
1582 case BFD_RELOC_ARC_SDA16_LD:
1583 case BFD_RELOC_ARC_SDA16_LD1:
1584 case BFD_RELOC_ARC_SDA16_LD2:
1585 case BFD_RELOC_ARC_SDA16_ST2:
1586 case BFD_RELOC_ARC_SDA32_ME:
1587 return FALSE;
1588 default:
1589 return TRUE;
f17c130b 1590 }
252b5132
RH		 1591}
1592
4670103e 1593/* Allocates a tok entry. */
252b5132 1594
4670103e
CZ		 1595static int
1596allocate_tok (expressionS *tok, int ntok, int cidx)
252b5132 1597{
4670103e
CZ		 1598 if (ntok > MAX_INSN_ARGS - 2)
1599 return 0; /* No space left. */
252b5132 1600
4670103e 1601 if (cidx > ntok)
33eaf5de 1602 return 0; /* Incorrect args. */
252b5132 1603
4670103e 1604 memcpy (&tok[ntok+1], &tok[ntok], sizeof (*tok));
252b5132 1605
4670103e
CZ		 1606 if (cidx == ntok)
1607 return 1; /* Success. */
1608 return allocate_tok (tok, ntok - 1, cidx);
1609}
886a2506 1610
8ddf6b2a
CZ		 1611/* Check if an particular ARC feature is enabled. */
1612
1613static bfd_boolean
1614check_cpu_feature (insn_subclass_t sc)
1615{
53a346d8 1616 if (is_code_density_p (sc) && !(selected_cpu.features & CD))
8ddf6b2a
CZ		 1617 return FALSE;
1618
53a346d8 1619 if (is_spfp_p (sc) && !(selected_cpu.features & SPX))
8ddf6b2a
CZ		 1620 return FALSE;
1621
53a346d8 1622 if (is_dpfp_p (sc) && !(selected_cpu.features & DPX))
8ddf6b2a
CZ		 1623 return FALSE;
1624
53a346d8 1625 if (is_fpuda_p (sc) && !(selected_cpu.features & DPA))
bdd582db
GM		 1626 return FALSE;
1627
53a346d8 1628 if (is_nps400_p (sc) && !(selected_cpu.features & NPS400))
8ddf6b2a
CZ		 1629 return FALSE;
1630
1631 return TRUE;
1632}
1633
4eb6f892
AB		 1634/* Parse the flags described by FIRST_PFLAG and NFLGS against the flag
1635 operands in OPCODE. Stores the matching OPCODES into the FIRST_PFLAG
1636 array and returns TRUE if the flag operands all match, otherwise,
1637 returns FALSE, in which case the FIRST_PFLAG array may have been
1638 modified. */
1639
1640static bfd_boolean
1641parse_opcode_flags (const struct arc_opcode *opcode,
1642 int nflgs,
1643 struct arc_flags *first_pflag)
1644{
1645 int lnflg, i;
1646 const unsigned char *flgidx;
1647
1648 lnflg = nflgs;
1649 for (i = 0; i < nflgs; i++)
1650 first_pflag[i].flgp = NULL;
1651
1652 /* Check the flags. Iterate over the valid flag classes. */
1653 for (flgidx = opcode->flags; *flgidx; ++flgidx)
1654 {
1655 /* Get a valid flag class. */
1656 const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
1657 const unsigned *flgopridx;
1658 int cl_matches = 0;
1659 struct arc_flags *pflag = NULL;
1660
6ec7c1ae
CZ		 1661 /* Check if opcode has implicit flag classes. */
1662 if (cl_flags->flag_class & F_CLASS_IMPLICIT)
1663 continue;
1664
4eb6f892
AB		 1665 /* Check for extension conditional codes. */
1666 if (ext_condcode.arc_ext_condcode
1667 && cl_flags->flag_class & F_CLASS_EXTEND)
1668 {
1669 struct arc_flag_operand *pf = ext_condcode.arc_ext_condcode;
1670 while (pf->name)
1671 {
1672 pflag = first_pflag;
1673 for (i = 0; i < nflgs; i++, pflag++)
1674 {
1675 if (!strcmp (pf->name, pflag->name))
1676 {
1677 if (pflag->flgp != NULL)
1678 return FALSE;
1679 /* Found it. */
1680 cl_matches++;
1681 pflag->flgp = pf;
1682 lnflg--;
1683 break;
1684 }
1685 }
1686 pf++;
1687 }
1688 }
1689
1690 for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
1691 {
1692 const struct arc_flag_operand *flg_operand;
1693
1694 pflag = first_pflag;
1695 flg_operand = &arc_flag_operands[*flgopridx];
1696 for (i = 0; i < nflgs; i++, pflag++)
1697 {
1698 /* Match against the parsed flags. */
1699 if (!strcmp (flg_operand->name, pflag->name))
1700 {
1701 if (pflag->flgp != NULL)
1702 return FALSE;
1703 cl_matches++;
1704 pflag->flgp = flg_operand;
1705 lnflg--;
1706 break; /* goto next flag class and parsed flag. */
1707 }
1708 }
1709 }
1710
1711 if ((cl_flags->flag_class & F_CLASS_REQUIRED) && cl_matches == 0)
1712 return FALSE;
1713 if ((cl_flags->flag_class & F_CLASS_OPTIONAL) && cl_matches > 1)
1714 return FALSE;
1715 }
1716
1717 /* Did I check all the parsed flags? */
1718 return lnflg ? FALSE : TRUE;
1719}
1720
1721
4670103e
CZ		 1722/* Search forward through all variants of an opcode looking for a
1723 syntax match. */
886a2506 1724
4670103e 1725static const struct arc_opcode *
b9b47ab7 1726find_opcode_match (const struct arc_opcode_hash_entry *entry,
4670103e
CZ		 1727 expressionS *tok,
1728 int *pntok,
1729 struct arc_flags *first_pflag,
1730 int nflgs,
abe7c33b
CZ		 1731 int *pcpumatch,
1732 const char **errmsg)
4670103e 1733{
1328504b
AB		 1734 const struct arc_opcode *opcode;
1735 struct arc_opcode_hash_entry_iterator iter;
4670103e
CZ		 1736 int ntok = *pntok;
1737 int got_cpu_match = 0;
1738 expressionS bktok[MAX_INSN_ARGS];
1739 int bkntok;
1740 expressionS emptyE;
886a2506 1741
1328504b 1742 arc_opcode_hash_entry_iterator_init (&iter);
4670103e
CZ		 1743 memset (&emptyE, 0, sizeof (emptyE));
1744 memcpy (bktok, tok, MAX_INSN_ARGS * sizeof (*tok));
1745 bkntok = ntok;
a161fe53 1746
1328504b
AB		 1747 for (opcode = arc_opcode_hash_entry_iterator_next (entry, &iter);
1748 opcode != NULL;
1749 opcode = arc_opcode_hash_entry_iterator_next (entry, &iter))
252b5132 1750 {
4670103e 1751 const unsigned char *opidx;
4eb6f892 1752 int tokidx = 0;
4670103e 1753 const expressionS *t = &emptyE;
252b5132 1754
bdfe53e3 1755 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08llX ",
4670103e 1756 frag_now->fr_file, frag_now->fr_line, opcode->opcode);
886a2506 1757
4670103e
CZ		 1758 /* Don't match opcodes that don't exist on this
1759 architecture. */
bb65a718 1760 if (!(opcode->cpu & selected_cpu.flags))
4670103e 1761 goto match_failed;
886a2506 1762
8ddf6b2a 1763 if (!check_cpu_feature (opcode->subclass))
4670103e 1764 goto match_failed;
886a2506 1765
4670103e
CZ		 1766 got_cpu_match = 1;
1767 pr_debug ("cpu ");
886a2506 1768
4670103e
CZ		 1769 /* Check the operands. */
1770 for (opidx = opcode->operands; *opidx; ++opidx)
252b5132 1771 {
4670103e 1772 const struct arc_operand *operand = &arc_operands[*opidx];
252b5132 1773
4670103e 1774 /* Only take input from real operands. */
db18dbab 1775 if (ARC_OPERAND_IS_FAKE (operand))
4670103e 1776 continue;
252b5132 1777
4670103e
CZ		 1778 /* When we expect input, make sure we have it. */
1779 if (tokidx >= ntok)
1780 goto match_failed;
6f4b1afc 1781
4670103e
CZ		 1782 /* Match operand type with expression type. */
1783 switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK)
1784 {
db18dbab 1785 case ARC_OPERAND_ADDRTYPE:
b437d035 1786 {
abe7c33b 1787 *errmsg = NULL;
b437d035
AB		 1788
1789 /* Check to be an address type. */
1790 if (tok[tokidx].X_op != O_addrtype)
1791 goto match_failed;
1792
1793 /* All address type operands need to have an insert
1794 method in order to check that we have the correct
1795 address type. */
1796 gas_assert (operand->insert != NULL);
1797 (*operand->insert) (0, tok[tokidx].X_add_number,
abe7c33b
CZ		 1798 errmsg);
1799 if (*errmsg != NULL)
b437d035
AB		 1800 goto match_failed;
1801 }
db18dbab
GM		 1802 break;
1803
4670103e
CZ		 1804 case ARC_OPERAND_IR:
1805 /* Check to be a register. */
1806 if ((tok[tokidx].X_op != O_register
1807 || !is_ir_num (tok[tokidx].X_add_number))
1808 && !(operand->flags & ARC_OPERAND_IGNORE))
1809 goto match_failed;
1810
1811 /* If expect duplicate, make sure it is duplicate. */
1812 if (operand->flags & ARC_OPERAND_DUPLICATE)
1813 {
1814 /* Check for duplicate. */
1815 if (t->X_op != O_register
1816 || !is_ir_num (t->X_add_number)
1817 || (regno (t->X_add_number) !=
1818 regno (tok[tokidx].X_add_number)))
1819 goto match_failed;
1820 }
1821
1822 /* Special handling? */
1823 if (operand->insert)
1824 {
abe7c33b 1825 *errmsg = NULL;
4670103e
CZ		 1826 (*operand->insert)(0,
1827 regno (tok[tokidx].X_add_number),
abe7c33b
CZ		 1828 errmsg);
1829 if (*errmsg)
4670103e
CZ		 1830 {
1831 if (operand->flags & ARC_OPERAND_IGNORE)
1832 {
1833 /* Missing argument, create one. */
1834 if (!allocate_tok (tok, ntok - 1, tokidx))
1835 goto match_failed;
1836
1837 tok[tokidx].X_op = O_absent;
1838 ++ntok;
1839 }
1840 else
1841 goto match_failed;
1842 }
1843 }
1844
1845 t = &tok[tokidx];
1846 break;
1847
1848 case ARC_OPERAND_BRAKET:
1849 /* Check if bracket is also in opcode table as
1850 operand. */
1851 if (tok[tokidx].X_op != O_bracket)
1852 goto match_failed;
1853 break;
1854
db18dbab
GM		 1855 case ARC_OPERAND_COLON:
1856 /* Check if colon is also in opcode table as operand. */
1857 if (tok[tokidx].X_op != O_colon)
1858 goto match_failed;
1859 break;
1860
4670103e
CZ		 1861 case ARC_OPERAND_LIMM:
1862 case ARC_OPERAND_SIGNED:
1863 case ARC_OPERAND_UNSIGNED:
1864 switch (tok[tokidx].X_op)
1865 {
1866 case O_illegal:
1867 case O_absent:
1868 case O_register:
1869 goto match_failed;
1870
1871 case O_bracket:
1872 /* Got an (too) early bracket, check if it is an
1873 ignored operand. N.B. This procedure works only
1874 when bracket is the last operand! */
1875 if (!(operand->flags & ARC_OPERAND_IGNORE))
1876 goto match_failed;
1877 /* Insert the missing operand. */
1878 if (!allocate_tok (tok, ntok - 1, tokidx))
1879 goto match_failed;
1880
1881 tok[tokidx].X_op = O_absent;
1882 ++ntok;
1883 break;
1884
22b92fc4
AB		 1885 case O_symbol:
1886 {
1887 const char *p;
b6523c37 1888 char *tmpp, *pp;
22b92fc4 1889 const struct arc_aux_reg *auxr;
22b92fc4 1890
c810e0b8 1891 if (opcode->insn_class != AUXREG)
22b92fc4
AB		 1892 goto de_fault;
1893 p = S_GET_NAME (tok[tokidx].X_add_symbol);
f36e33da 1894
b6523c37 1895 /* For compatibility reasons, an aux register can
1896 be spelled with upper or lower case
1897 letters. */
1898 tmpp = strdup (p);
1899 for (pp = tmpp; *pp; ++pp) *pp = TOLOWER (*pp);
1900
1901 auxr = hash_find (arc_aux_hash, tmpp);
f36e33da
CZ		 1902 if (auxr)
1903 {
1904 /* We modify the token array here, safe in the
1905 knowledge, that if this was the wrong
1906 choice then the original contents will be
1907 restored from BKTOK. */
1908 tok[tokidx].X_op = O_constant;
1909 tok[tokidx].X_add_number = auxr->address;
1910 ARC_SET_FLAG (tok[tokidx].X_add_symbol, ARC_FLAG_AUX);
1911 }
b6523c37 1912 free (tmpp);
22b92fc4
AB		 1913
1914 if (tok[tokidx].X_op != O_constant)
1915 goto de_fault;
1916 }
1a0670f3 1917 /* Fall through. */
4670103e
CZ		 1918 case O_constant:
1919 /* Check the range. */
1920 if (operand->bits != 32
1921 && !(operand->flags & ARC_OPERAND_NCHK))
1922 {
1923 offsetT min, max, val;
1924 val = tok[tokidx].X_add_number;
1925
1926 if (operand->flags & ARC_OPERAND_SIGNED)
1927 {
1928 max = (1 << (operand->bits - 1)) - 1;
1929 min = -(1 << (operand->bits - 1));
1930 }
1931 else
1932 {
1933 max = (1 << operand->bits) - 1;
1934 min = 0;
1935 }
1936
1937 if (val < min || val > max)
1938 goto match_failed;
1939
33eaf5de 1940 /* Check alignments. */
4670103e
CZ		 1941 if ((operand->flags & ARC_OPERAND_ALIGNED32)
1942 && (val & 0x03))
1943 goto match_failed;
1944
1945 if ((operand->flags & ARC_OPERAND_ALIGNED16)
1946 && (val & 0x01))
1947 goto match_failed;
1948 }
1949 else if (operand->flags & ARC_OPERAND_NCHK)
1950 {
1951 if (operand->insert)
1952 {
abe7c33b 1953 *errmsg = NULL;
4670103e
CZ		 1954 (*operand->insert)(0,
1955 tok[tokidx].X_add_number,
abe7c33b
CZ		 1956 errmsg);
1957 if (*errmsg)
4670103e
CZ		 1958 goto match_failed;
1959 }
4eb6f892 1960 else if (!(operand->flags & ARC_OPERAND_IGNORE))
4670103e
CZ		 1961 goto match_failed;
1962 }
1963 break;
1964
1965 case O_subtract:
1966 /* Check if it is register range. */
1967 if ((tok[tokidx].X_add_number == 0)
1968 && contains_register (tok[tokidx].X_add_symbol)
1969 && contains_register (tok[tokidx].X_op_symbol))
1970 {
1971 int regs;
1972
1973 regs = get_register (tok[tokidx].X_add_symbol);
1974 regs <<= 16;
1975 regs |= get_register (tok[tokidx].X_op_symbol);
1976 if (operand->insert)
1977 {
abe7c33b 1978 *errmsg = NULL;
4670103e
CZ		 1979 (*operand->insert)(0,
1980 regs,
abe7c33b
CZ		 1981 errmsg);
1982 if (*errmsg)
4670103e
CZ		 1983 goto match_failed;
1984 }
1985 else
1986 goto match_failed;
1987 break;
1988 }
1a0670f3 1989 /* Fall through. */
4670103e 1990 default:
22b92fc4 1991 de_fault:
4670103e
CZ		 1992 if (operand->default_reloc == 0)
1993 goto match_failed; /* The operand needs relocation. */
1994
1995 /* Relocs requiring long immediate. FIXME! make it
1996 generic and move it to a function. */
1997 switch (tok[tokidx].X_md)
1998 {
1999 case O_gotoff:
2000 case O_gotpc:
2001 case O_pcl:
2002 case O_tpoff:
2003 case O_dtpoff:
2004 case O_tlsgd:
2005 case O_tlsie:
2006 if (!(operand->flags & ARC_OPERAND_LIMM))
2007 goto match_failed;
1a0670f3 2008 /* Fall through. */
4670103e
CZ		 2009 case O_absent:
2010 if (!generic_reloc_p (operand->default_reloc))
2011 goto match_failed;
2b804145 2012 break;
4670103e
CZ		 2013 default:
2014 break;
2015 }
2016 break;
2017 }
2018 /* If expect duplicate, make sure it is duplicate. */
2019 if (operand->flags & ARC_OPERAND_DUPLICATE)
2020 {
2021 if (t->X_op == O_illegal
2022 || t->X_op == O_absent
2023 || t->X_op == O_register
2024 || (t->X_add_number != tok[tokidx].X_add_number))
2025 goto match_failed;
2026 }
2027 t = &tok[tokidx];
2028 break;
2029
2030 default:
2031 /* Everything else should have been fake. */
2032 abort ();
2033 }
2034
2035 ++tokidx;
2036 }
2037 pr_debug ("opr ");
2038
1ae8ab47 2039 /* Setup ready for flag parsing. */
4eb6f892 2040 if (!parse_opcode_flags (opcode, nflgs, first_pflag))
4670103e
CZ		 2041 goto match_failed;
2042
2043 pr_debug ("flg");
2044 /* Possible match -- did we use all of our input? */
2045 if (tokidx == ntok)
2046 {
2047 *pntok = ntok;
2048 pr_debug ("\n");
2049 return opcode;
2050 }
2051
2052 match_failed:;
2053 pr_debug ("\n");
2054 /* Restore the original parameters. */
2055 memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok));
2056 ntok = bkntok;
2057 }
4670103e
CZ		 2058
2059 if (*pcpumatch)
2060 *pcpumatch = got_cpu_match;
2061
2062 return NULL;
2063}
2064
2065/* Swap operand tokens. */
2066
2067static void
2068swap_operand (expressionS *operand_array,
2069 unsigned source,
2070 unsigned destination)
2071{
2072 expressionS cpy_operand;
2073 expressionS *src_operand;
2074 expressionS *dst_operand;
2075 size_t size;
2076
2077 if (source == destination)
2078 return;
2079
2080 src_operand = &operand_array[source];
2081 dst_operand = &operand_array[destination];
2082 size = sizeof (expressionS);
2083
2084 /* Make copy of operand to swap with and swap. */
2085 memcpy (&cpy_operand, dst_operand, size);
2086 memcpy (dst_operand, src_operand, size);
2087 memcpy (src_operand, &cpy_operand, size);
2088}
2089
2090/* Check if *op matches *tok type.
2091 Returns FALSE if they don't match, TRUE if they match. */
2092
2093static bfd_boolean
2094pseudo_operand_match (const expressionS *tok,
2095 const struct arc_operand_operation *op)
2096{
2097 offsetT min, max, val;
2098 bfd_boolean ret;
2099 const struct arc_operand *operand_real = &arc_operands[op->operand_idx];
2100
2101 ret = FALSE;
2102 switch (tok->X_op)
2103 {
2104 case O_constant:
2105 if (operand_real->bits == 32 && (operand_real->flags & ARC_OPERAND_LIMM))
2106 ret = 1;
2107 else if (!(operand_real->flags & ARC_OPERAND_IR))
2108 {
2109 val = tok->X_add_number + op->count;
2110 if (operand_real->flags & ARC_OPERAND_SIGNED)
2111 {
2112 max = (1 << (operand_real->bits - 1)) - 1;
2113 min = -(1 << (operand_real->bits - 1));
2114 }
2115 else
2116 {
2117 max = (1 << operand_real->bits) - 1;
2118 min = 0;
2119 }
2120 if (min <= val && val <= max)
2121 ret = TRUE;
2122 }
6f4b1afc
CM		 2123 break;
2124
4670103e
CZ		 2125 case O_symbol:
2126 /* Handle all symbols as long immediates or signed 9. */
db18dbab
GM		 2127 if (operand_real->flags & ARC_OPERAND_LIMM
2128 || ((operand_real->flags & ARC_OPERAND_SIGNED)
2129 && operand_real->bits == 9))
4670103e 2130 ret = TRUE;
6f4b1afc
CM		 2131 break;
2132
4670103e
CZ		 2133 case O_register:
2134 if (operand_real->flags & ARC_OPERAND_IR)
2135 ret = TRUE;
2136 break;
2137
2138 case O_bracket:
2139 if (operand_real->flags & ARC_OPERAND_BRAKET)
2140 ret = TRUE;
6f4b1afc
CM		 2141 break;
2142
2143 default:
4670103e 2144 /* Unknown. */
6f4b1afc
CM		 2145 break;
2146 }
4670103e
CZ		 2147 return ret;
2148}
6f4b1afc 2149
4670103e
CZ		 2150/* Find pseudo instruction in array. */
2151
2152static const struct arc_pseudo_insn *
2153find_pseudo_insn (const char *opname,
2154 int ntok,
2155 const expressionS *tok)
2156{
2157 const struct arc_pseudo_insn *pseudo_insn = NULL;
2158 const struct arc_operand_operation *op;
2159 unsigned int i;
2160 int j;
2161
2162 for (i = 0; i < arc_num_pseudo_insn; ++i)
6f4b1afc 2163 {
4670103e
CZ		 2164 pseudo_insn = &arc_pseudo_insns[i];
2165 if (strcmp (pseudo_insn->mnemonic_p, opname) == 0)
2166 {
2167 op = pseudo_insn->operand;
2168 for (j = 0; j < ntok; ++j)
2169 if (!pseudo_operand_match (&tok[j], &op[j]))
2170 break;
2171
2172 /* Found the right instruction. */
2173 if (j == ntok)
2174 return pseudo_insn;
2175 }
6f4b1afc 2176 }
4670103e
CZ		 2177 return NULL;
2178}
252b5132 2179
4670103e 2180/* Assumes the expressionS *tok is of sufficient size. */
252b5132 2181
b9b47ab7 2182static const struct arc_opcode_hash_entry *
4670103e
CZ		 2183find_special_case_pseudo (const char *opname,
2184 int *ntok,
2185 expressionS *tok,
2186 int *nflgs,
2187 struct arc_flags *pflags)
2188{
2189 const struct arc_pseudo_insn *pseudo_insn = NULL;
2190 const struct arc_operand_operation *operand_pseudo;
2191 const struct arc_operand *operand_real;
2192 unsigned i;
2193 char construct_operand[MAX_CONSTR_STR];
886a2506 2194
4670103e
CZ		 2195 /* Find whether opname is in pseudo instruction array. */
2196 pseudo_insn = find_pseudo_insn (opname, *ntok, tok);
2197
2198 if (pseudo_insn == NULL)
2199 return NULL;
2200
2201 /* Handle flag, Limited to one flag at the moment. */
2202 if (pseudo_insn->flag_r != NULL)
2203 *nflgs += tokenize_flags (pseudo_insn->flag_r, &pflags[*nflgs],
2204 MAX_INSN_FLGS - *nflgs);
2205
2206 /* Handle operand operations. */
2207 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
252b5132 2208 {
4670103e
CZ		 2209 operand_pseudo = &pseudo_insn->operand[i];
2210 operand_real = &arc_operands[operand_pseudo->operand_idx];
886a2506 2211
db18dbab
GM		 2212 if (operand_real->flags & ARC_OPERAND_BRAKET
2213 && !operand_pseudo->needs_insert)
4670103e 2214 continue;
b125bd17 2215
4670103e
CZ		 2216 /* Has to be inserted (i.e. this token does not exist yet). */
2217 if (operand_pseudo->needs_insert)
2218 {
2219 if (operand_real->flags & ARC_OPERAND_BRAKET)
2220 {
2221 tok[i].X_op = O_bracket;
2222 ++(*ntok);
2223 continue;
2224 }
b125bd17 2225
4670103e
CZ		 2226 /* Check if operand is a register or constant and handle it
2227 by type. */
2228 if (operand_real->flags & ARC_OPERAND_IR)
2229 snprintf (construct_operand, MAX_CONSTR_STR, "r%d",
2230 operand_pseudo->count);
2231 else
2232 snprintf (construct_operand, MAX_CONSTR_STR, "%d",
2233 operand_pseudo->count);
886a2506 2234
4670103e
CZ		 2235 tokenize_arguments (construct_operand, &tok[i], 1);
2236 ++(*ntok);
2237 }
2238
2239 else if (operand_pseudo->count)
2240 {
2241 /* Operand number has to be adjusted accordingly (by operand
2242 type). */
2243 switch (tok[i].X_op)
2244 {
2245 case O_constant:
2246 tok[i].X_add_number += operand_pseudo->count;
2247 break;
2248
2249 case O_symbol:
2250 break;
2251
2252 default:
2253 /* Ignored. */
2254 break;
2255 }
2256 }
2257 }
2258
2259 /* Swap operands if necessary. Only supports one swap at the
2260 moment. */
2261 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
2262 {
2263 operand_pseudo = &pseudo_insn->operand[i];
2264
2265 if (operand_pseudo->swap_operand_idx == i)
2266 continue;
2267
2268 swap_operand (tok, i, operand_pseudo->swap_operand_idx);
2269
2270 /* Prevent a swap back later by breaking out. */
2271 break;
2272 }
2273
da5be039 2274 return arc_find_opcode (pseudo_insn->mnemonic_r);
4670103e
CZ		 2275}
2276
b9b47ab7 2277static const struct arc_opcode_hash_entry *
4670103e
CZ		 2278find_special_case_flag (const char *opname,
2279 int *nflgs,
2280 struct arc_flags *pflags)
2281{
2282 unsigned int i;
2283 const char *flagnm;
2284 unsigned flag_idx, flag_arr_idx;
2285 size_t flaglen, oplen;
2286 const struct arc_flag_special *arc_flag_special_opcode;
b9b47ab7 2287 const struct arc_opcode_hash_entry *entry;
4670103e
CZ		 2288
2289 /* Search for special case instruction. */
2290 for (i = 0; i < arc_num_flag_special; i++)
2291 {
2292 arc_flag_special_opcode = &arc_flag_special_cases[i];
2293 oplen = strlen (arc_flag_special_opcode->name);
2294
2295 if (strncmp (opname, arc_flag_special_opcode->name, oplen) != 0)
2296 continue;
2297
2298 /* Found a potential special case instruction, now test for
2299 flags. */
2300 for (flag_arr_idx = 0;; ++flag_arr_idx)
2301 {
2302 flag_idx = arc_flag_special_opcode->flags[flag_arr_idx];
2303 if (flag_idx == 0)
2304 break; /* End of array, nothing found. */
886a2506 2305
4670103e
CZ		 2306 flagnm = arc_flag_operands[flag_idx].name;
2307 flaglen = strlen (flagnm);
2308 if (strcmp (opname + oplen, flagnm) == 0)
2309 {
b9b47ab7 2310 entry = arc_find_opcode (arc_flag_special_opcode->name);
886a2506 2311
4670103e
CZ		 2312 if (*nflgs + 1 > MAX_INSN_FLGS)
2313 break;
2314 memcpy (pflags[*nflgs].name, flagnm, flaglen);
2315 pflags[*nflgs].name[flaglen] = '\0';
2316 (*nflgs)++;
b9b47ab7 2317 return entry;
4670103e
CZ		 2318 }
2319 }
2320 }
2321 return NULL;
2322}
886a2506 2323
4670103e 2324/* Used to find special case opcode. */
886a2506 2325
b9b47ab7 2326static const struct arc_opcode_hash_entry *
4670103e
CZ		 2327find_special_case (const char *opname,
2328 int *nflgs,
2329 struct arc_flags *pflags,
2330 expressionS *tok,
2331 int *ntok)
2332{
b9b47ab7 2333 const struct arc_opcode_hash_entry *entry;
886a2506 2334
b9b47ab7 2335 entry = find_special_case_pseudo (opname, ntok, tok, nflgs, pflags);
886a2506 2336
b9b47ab7
AB		 2337 if (entry == NULL)
2338 entry = find_special_case_flag (opname, nflgs, pflags);
886a2506 2339
b9b47ab7 2340 return entry;
4670103e 2341}
886a2506 2342
53a346d8
CZ		 2343/* Autodetect cpu attribute list. */
2344
2345static void
2346autodetect_attributes (const struct arc_opcode *opcode,
2347 const expressionS *tok,
2348 int ntok)
2349{
2350 unsigned i;
2351 struct mpy_type
2352 {
2353 unsigned feature;
2354 unsigned encoding;
2355 } mpy_list[] = {{ MPY1E, 1 }, { MPY6E, 6 }, { MPY7E, 7 }, { MPY8E, 8 },
2356 { MPY9E, 9 }};
2357
2358 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
2359 if (opcode->subclass == feature_list[i].feature)
2360 selected_cpu.features |= feature_list[i].feature;
2361
2362 for (i = 0; i < ARRAY_SIZE (mpy_list); i++)
2363 if (opcode->subclass == mpy_list[i].feature)
2364 mpy_option = mpy_list[i].encoding;
2365
2366 for (i = 0; i < (unsigned) ntok; i++)
2367 {
2368 switch (tok[i].X_md)
2369 {
2370 case O_gotoff:
2371 case O_gotpc:
2372 case O_plt:
2373 pic_option = 2;
2374 break;
2375 case O_sda:
2376 sda_option = 2;
2377 break;
2378 case O_tlsgd:
2379 case O_tlsie:
2380 case O_tpoff9:
2381 case O_tpoff:
2382 case O_dtpoff9:
2383 case O_dtpoff:
2384 tls_option = 1;
2385 break;
2386 default:
2387 break;
2388 }
63741043 2389
2390 switch (tok[i].X_op)
2391 {
2392 case O_register:
2393 if ((tok[i].X_add_number >= 4 && tok[i].X_add_number <= 9)
2394 || (tok[i].X_add_number >= 16 && tok[i].X_add_number <= 25))
2395 rf16_only = FALSE;
2396 break;
2397 default:
2398 break;
2399 }
53a346d8
CZ		 2400 }
2401}
2402
2403/* Given an opcode name, pre-tockenized set of argumenst and the
4670103e 2404 opcode flags, take it all the way through emission. */
886a2506 2405
4670103e
CZ		 2406static void
2407assemble_tokens (const char *opname,
2408 expressionS *tok,
2409 int ntok,
2410 struct arc_flags *pflags,
2411 int nflgs)
2412{
2413 bfd_boolean found_something = FALSE;
b9b47ab7 2414 const struct arc_opcode_hash_entry *entry;
4670103e 2415 int cpumatch = 1;
abe7c33b 2416 const char *errmsg = NULL;
886a2506 2417
4670103e 2418 /* Search opcodes. */
b9b47ab7 2419 entry = arc_find_opcode (opname);
886a2506 2420
4670103e 2421 /* Couldn't find opcode conventional way, try special cases. */
b9b47ab7
AB		 2422 if (entry == NULL)
2423 entry = find_special_case (opname, &nflgs, pflags, tok, &ntok);
886a2506 2424
b9b47ab7 2425 if (entry != NULL)
4670103e 2426 {
b9b47ab7
AB		 2427 const struct arc_opcode *opcode;
2428
1328504b
AB		 2429 pr_debug ("%s:%d: assemble_tokens: %s\n",
2430 frag_now->fr_file, frag_now->fr_line, opname);
4670103e 2431 found_something = TRUE;
b9b47ab7 2432 opcode = find_opcode_match (entry, tok, &ntok, pflags,
abe7c33b 2433 nflgs, &cpumatch, &errmsg);
b9b47ab7 2434 if (opcode != NULL)
4670103e
CZ		 2435 {
2436 struct arc_insn insn;
b9b47ab7 2437
53a346d8 2438 autodetect_attributes (opcode, tok, ntok);
4670103e
CZ		 2439 assemble_insn (opcode, tok, ntok, pflags, nflgs, &insn);
2440 emit_insn (&insn);
2441 return;
2442 }
2443 }
886a2506 2444
4670103e
CZ		 2445 if (found_something)
2446 {
2447 if (cpumatch)
abe7c33b
CZ		 2448 if (errmsg)
2449 as_bad (_("%s for instruction '%s'"), errmsg, opname);
2450 else
2451 as_bad (_("inappropriate arguments for opcode '%s'"), opname);
4670103e
CZ		 2452 else
2453 as_bad (_("opcode '%s' not supported for target %s"), opname,
bb65a718 2454 selected_cpu.name);
4670103e
CZ		 2455 }
2456 else
2457 as_bad (_("unknown opcode '%s'"), opname);
886a2506
NC		 2458}
2459
4670103e 2460/* The public interface to the instruction assembler. */
886a2506 2461
4670103e
CZ		 2462void
2463md_assemble (char *str)
886a2506 2464{
4670103e
CZ		 2465 char *opname;
2466 expressionS tok[MAX_INSN_ARGS];
2467 int ntok, nflg;
2468 size_t opnamelen;
2469 struct arc_flags flags[MAX_INSN_FLGS];
886a2506 2470
4670103e
CZ		 2471 /* Split off the opcode. */
2472 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_0123468");
29a2809e 2473 opname = xmemdup0 (str, opnamelen);
886a2506 2474
33eaf5de 2475 /* Signalize we are assembling the instructions. */
4670103e 2476 assembling_insn = TRUE;
886a2506 2477
4670103e
CZ		 2478 /* Tokenize the flags. */
2479 if ((nflg = tokenize_flags (str + opnamelen, flags, MAX_INSN_FLGS)) == -1)
2480 {
2481 as_bad (_("syntax error"));
2482 return;
2483 }
886a2506 2484
4670103e
CZ		 2485 /* Scan up to the end of the mnemonic which must end in space or end
2486 of string. */
2487 str += opnamelen;
2488 for (; *str != '\0'; str++)
2489 if (*str == ' ')
2490 break;
886a2506 2491
4670103e
CZ		 2492 /* Tokenize the rest of the line. */
2493 if ((ntok = tokenize_arguments (str, tok, MAX_INSN_ARGS)) < 0)
886a2506 2494 {
4670103e
CZ		 2495 as_bad (_("syntax error"));
2496 return;
252b5132
RH		 2497 }
2498
4670103e
CZ		 2499 /* Finish it off. */
2500 assemble_tokens (opname, tok, ntok, flags, nflg);
2501 assembling_insn = FALSE;
2502}
2503
2504/* Callback to insert a register into the hash table. */
2505
2506static void
f86f5863 2507declare_register (const char *name, int number)
4670103e
CZ		 2508{
2509 const char *err;
2510 symbolS *regS = symbol_create (name, reg_section,
2511 number, &zero_address_frag);
2512
2513 err = hash_insert (arc_reg_hash, S_GET_NAME (regS), (void *) regS);
2514 if (err)
e6ba1cba 2515 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
4670103e
CZ		 2516 name, err);
2517}
252b5132 2518
4670103e 2519/* Construct symbols for each of the general registers. */
252b5132 2520
4670103e
CZ		 2521static void
2522declare_register_set (void)
2523{
2524 int i;
2525 for (i = 0; i < 64; ++i)
886a2506 2526 {
4670103e
CZ		 2527 char name[7];
2528
2529 sprintf (name, "r%d", i);
2530 declare_register (name, i);
2531 if ((i & 0x01) == 0)
886a2506 2532 {
4670103e
CZ		 2533 sprintf (name, "r%dr%d", i, i+1);
2534 declare_register (name, i);
886a2506
NC		 2535 }
2536 }
252b5132 2537}
ea1562b3 2538
db18dbab
GM		 2539/* Construct a symbol for an address type. */
2540
2541static void
2542declare_addrtype (const char *name, int number)
2543{
2544 const char *err;
2545 symbolS *addrtypeS = symbol_create (name, undefined_section,
2546 number, &zero_address_frag);
2547
2548 err = hash_insert (arc_addrtype_hash, S_GET_NAME (addrtypeS),
2549 (void *) addrtypeS);
2550 if (err)
2551 as_fatal (_("Inserting \"%s\" into address type table failed: %s"),
2552 name, err);
2553}
2554
4670103e
CZ		 2555/* Port-specific assembler initialization. This function is called
2556 once, at assembler startup time. */
ea1562b3
NC		 2557
2558void
4670103e 2559md_begin (void)
ea1562b3 2560{
b99747ae 2561 const struct arc_opcode *opcode = arc_opcodes;
886a2506 2562
bb65a718
AB		 2563 if (mach_selection_mode == MACH_SELECTION_NONE)
2564 arc_select_cpu (TARGET_WITH_CPU, MACH_SELECTION_FROM_DEFAULT);
24740d83 2565
4670103e
CZ		 2566 /* The endianness can be chosen "at the factory". */
2567 target_big_endian = byte_order == BIG_ENDIAN;
886a2506 2568
bb65a718 2569 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
4670103e
CZ		 2570 as_warn (_("could not set architecture and machine"));
2571
2572 /* Set elf header flags. */
bb65a718 2573 bfd_set_private_flags (stdoutput, selected_cpu.eflags);
4670103e
CZ		 2574
2575 /* Set up a hash table for the instructions. */
2576 arc_opcode_hash = hash_new ();
2577 if (arc_opcode_hash == NULL)
2578 as_fatal (_("Virtual memory exhausted"));
2579
2580 /* Initialize the hash table with the insns. */
b99747ae 2581 do
ea1562b3 2582 {
b99747ae 2583 const char *name = opcode->name;
da5be039 2584
b99747ae 2585 arc_insert_opcode (opcode);
4670103e 2586
b99747ae
CZ		 2587 while (++opcode && opcode->name
2588 && (opcode->name == name
2589 || !strcmp (opcode->name, name)))
4670103e 2590 continue;
b99747ae 2591 }while (opcode->name);
4670103e
CZ		 2592
2593 /* Register declaration. */
2594 arc_reg_hash = hash_new ();
2595 if (arc_reg_hash == NULL)
2596 as_fatal (_("Virtual memory exhausted"));
2597
2598 declare_register_set ();
2599 declare_register ("gp", 26);
2600 declare_register ("fp", 27);
2601 declare_register ("sp", 28);
2602 declare_register ("ilink", 29);
2603 declare_register ("ilink1", 29);
2604 declare_register ("ilink2", 30);
2605 declare_register ("blink", 31);
2606
87789e08
CZ		 2607 /* XY memory registers. */
2608 declare_register ("x0_u0", 32);
2609 declare_register ("x0_u1", 33);
2610 declare_register ("x1_u0", 34);
2611 declare_register ("x1_u1", 35);
2612 declare_register ("x2_u0", 36);
2613 declare_register ("x2_u1", 37);
2614 declare_register ("x3_u0", 38);
2615 declare_register ("x3_u1", 39);
2616 declare_register ("y0_u0", 40);
2617 declare_register ("y0_u1", 41);
2618 declare_register ("y1_u0", 42);
2619 declare_register ("y1_u1", 43);
2620 declare_register ("y2_u0", 44);
2621 declare_register ("y2_u1", 45);
2622 declare_register ("y3_u0", 46);
2623 declare_register ("y3_u1", 47);
2624 declare_register ("x0_nu", 48);
2625 declare_register ("x1_nu", 49);
2626 declare_register ("x2_nu", 50);
2627 declare_register ("x3_nu", 51);
2628 declare_register ("y0_nu", 52);
2629 declare_register ("y1_nu", 53);
2630 declare_register ("y2_nu", 54);
2631 declare_register ("y3_nu", 55);
2632
4670103e
CZ		 2633 declare_register ("mlo", 57);
2634 declare_register ("mmid", 58);
2635 declare_register ("mhi", 59);
2636
2637 declare_register ("acc1", 56);
2638 declare_register ("acc2", 57);
2639
2640 declare_register ("lp_count", 60);
2641 declare_register ("pcl", 63);
2642
2643 /* Initialize the last instructions. */
2644 memset (&arc_last_insns[0], 0, sizeof (arc_last_insns));
f36e33da
CZ		 2645
2646 /* Aux register declaration. */
2647 arc_aux_hash = hash_new ();
2648 if (arc_aux_hash == NULL)
2649 as_fatal (_("Virtual memory exhausted"));
2650
2651 const struct arc_aux_reg *auxr = &arc_aux_regs[0];
2652 unsigned int i;
2653 for (i = 0; i < arc_num_aux_regs; i++, auxr++)
2654 {
2655 const char *retval;
2656
bb65a718 2657 if (!(auxr->cpu & selected_cpu.flags))
f36e33da
CZ		 2658 continue;
2659
2660 if ((auxr->subclass != NONE)
2661 && !check_cpu_feature (auxr->subclass))
2662 continue;
2663
2664 retval = hash_insert (arc_aux_hash, auxr->name, (void *) auxr);
2665 if (retval)
2666 as_fatal (_("internal error: can't hash aux register '%s': %s"),
2667 auxr->name, retval);
2668 }
db18dbab
GM		 2669
2670 /* Address type declaration. */
2671 arc_addrtype_hash = hash_new ();
2672 if (arc_addrtype_hash == NULL)
2673 as_fatal (_("Virtual memory exhausted"));
2674
2675 declare_addrtype ("bd", ARC_NPS400_ADDRTYPE_BD);
2676 declare_addrtype ("jid", ARC_NPS400_ADDRTYPE_JID);
2677 declare_addrtype ("lbd", ARC_NPS400_ADDRTYPE_LBD);
2678 declare_addrtype ("mbd", ARC_NPS400_ADDRTYPE_MBD);
2679 declare_addrtype ("sd", ARC_NPS400_ADDRTYPE_SD);
2680 declare_addrtype ("sm", ARC_NPS400_ADDRTYPE_SM);
2681 declare_addrtype ("xa", ARC_NPS400_ADDRTYPE_XA);
2682 declare_addrtype ("xd", ARC_NPS400_ADDRTYPE_XD);
2683 declare_addrtype ("cd", ARC_NPS400_ADDRTYPE_CD);
2684 declare_addrtype ("cbd", ARC_NPS400_ADDRTYPE_CBD);
2685 declare_addrtype ("cjid", ARC_NPS400_ADDRTYPE_CJID);
2686 declare_addrtype ("clbd", ARC_NPS400_ADDRTYPE_CLBD);
2687 declare_addrtype ("cm", ARC_NPS400_ADDRTYPE_CM);
2688 declare_addrtype ("csd", ARC_NPS400_ADDRTYPE_CSD);
2689 declare_addrtype ("cxa", ARC_NPS400_ADDRTYPE_CXA);
2690 declare_addrtype ("cxd", ARC_NPS400_ADDRTYPE_CXD);
886a2506 2691}
ea1562b3 2692
4670103e
CZ		 2693/* Write a value out to the object file, using the appropriate
2694 endianness. */
ea1562b3 2695
4670103e
CZ		 2696void
2697md_number_to_chars (char *buf,
2698 valueT val,
2699 int n)
886a2506 2700{
4670103e
CZ		 2701 if (target_big_endian)
2702 number_to_chars_bigendian (buf, val, n);
2703 else
2704 number_to_chars_littleendian (buf, val, n);
886a2506 2705}
ea1562b3 2706
4670103e 2707/* Round up a section size to the appropriate boundary. */
ea1562b3 2708
4670103e
CZ		 2709valueT
2710md_section_align (segT segment,
2711 valueT size)
886a2506 2712{
4670103e
CZ		 2713 int align = bfd_get_section_alignment (stdoutput, segment);
2714
2715 return ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
886a2506 2716}
ea1562b3 2717
4670103e
CZ		 2718/* The location from which a PC relative jump should be calculated,
2719 given a PC relative reloc. */
ea1562b3 2720
4670103e
CZ		 2721long
2722md_pcrel_from_section (fixS *fixP,
2723 segT sec)
886a2506 2724{
4670103e 2725 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
ea1562b3 2726
4670103e 2727 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP->fx_offset);
ea1562b3 2728
4670103e
CZ		 2729 if (fixP->fx_addsy != (symbolS *) NULL
2730 && (!S_IS_DEFINED (fixP->fx_addsy)
2731 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
2732 {
2733 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP->fx_addsy));
ea1562b3 2734
4670103e
CZ		 2735 /* The symbol is undefined (or is defined but not in this section).
2736 Let the linker figure it out. */
2737 return 0;
2738 }
2739
2740 if ((int) fixP->fx_r_type < 0)
886a2506 2741 {
4670103e
CZ		 2742 /* These are the "internal" relocations. Align them to
2743 32 bit boundary (PCL), for the moment. */
2744 base &= ~3;
886a2506 2745 }
4670103e
CZ		 2746 else
2747 {
2748 switch (fixP->fx_r_type)
2749 {
2750 case BFD_RELOC_ARC_PC32:
2751 /* The hardware calculates relative to the start of the
2752 insn, but this relocation is relative to location of the
2753 LIMM, compensate. The base always needs to be
2b0f3761 2754 subtracted by 4 as we do not support this type of PCrel
4670103e
CZ		 2755 relocation for short instructions. */
2756 base -= 4;
2757 /* Fall through. */
2758 case BFD_RELOC_ARC_PLT32:
2759 case BFD_RELOC_ARC_S25H_PCREL_PLT:
2760 case BFD_RELOC_ARC_S21H_PCREL_PLT:
2761 case BFD_RELOC_ARC_S25W_PCREL_PLT:
2762 case BFD_RELOC_ARC_S21W_PCREL_PLT:
2763
2764 case BFD_RELOC_ARC_S21H_PCREL:
2765 case BFD_RELOC_ARC_S25H_PCREL:
2766 case BFD_RELOC_ARC_S13_PCREL:
2767 case BFD_RELOC_ARC_S21W_PCREL:
2768 case BFD_RELOC_ARC_S25W_PCREL:
2769 base &= ~3;
2770 break;
2771 default:
2772 as_bad_where (fixP->fx_file, fixP->fx_line,
2773 _("unhandled reloc %s in md_pcrel_from_section"),
2774 bfd_get_reloc_code_name (fixP->fx_r_type));
2775 break;
2776 }
2777 }
2778
9e32d9ae
AB		 2779 pr_debug ("pcrel from %"BFD_VMA_FMT"x + %lx = %"BFD_VMA_FMT"x, "
2780 "symbol: %s (%"BFD_VMA_FMT"x)\n",
4670103e
CZ		 2781 fixP->fx_frag->fr_address, fixP->fx_where, base,
2782 fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "(null)",
2783 fixP->fx_addsy ? S_GET_VALUE (fixP->fx_addsy) : 0);
2784
2785 return base;
886a2506 2786}
ea1562b3 2787
33eaf5de 2788/* Given a BFD relocation find the corresponding operand. */
ea1562b3 2789
4670103e
CZ		 2790static const struct arc_operand *
2791find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc)
2792{
2793 unsigned i;
ea1562b3 2794
4670103e
CZ		 2795 for (i = 0; i < arc_num_operands; i++)
2796 if (arc_operands[i].default_reloc == reloc)
2797 return &arc_operands[i];
2798 return NULL;
2799}
ea1562b3 2800
4670103e 2801/* Insert an operand value into an instruction. */
ea1562b3 2802
bdfe53e3
AB		 2803static unsigned long long
2804insert_operand (unsigned long long insn,
4670103e 2805 const struct arc_operand *operand,
bdfe53e3 2806 long long val,
3b4dbbbf 2807 const char *file,
4670103e 2808 unsigned line)
886a2506 2809{
4670103e 2810 offsetT min = 0, max = 0;
ea1562b3 2811
4670103e
CZ		 2812 if (operand->bits != 32
2813 && !(operand->flags & ARC_OPERAND_NCHK)
2814 && !(operand->flags & ARC_OPERAND_FAKE))
886a2506 2815 {
4670103e
CZ		 2816 if (operand->flags & ARC_OPERAND_SIGNED)
2817 {
2818 max = (1 << (operand->bits - 1)) - 1;
2819 min = -(1 << (operand->bits - 1));
2820 }
2821 else
2822 {
2823 max = (1 << operand->bits) - 1;
2824 min = 0;
2825 }
886a2506 2826
4670103e
CZ		 2827 if (val < min || val > max)
2828 as_bad_value_out_of_range (_("operand"),
2829 val, min, max, file, line);
2830 }
ea1562b3 2831
cc07cda6 2832 pr_debug ("insert field: %ld <= %lld <= %ld in 0x%08llx\n",
4670103e 2833 min, val, max, insn);
ea1562b3 2834
4670103e
CZ		 2835 if ((operand->flags & ARC_OPERAND_ALIGNED32)
2836 && (val & 0x03))
2837 as_bad_where (file, line,
2838 _("Unaligned operand. Needs to be 32bit aligned"));
ea1562b3 2839
4670103e
CZ		 2840 if ((operand->flags & ARC_OPERAND_ALIGNED16)
2841 && (val & 0x01))
2842 as_bad_where (file, line,
2843 _("Unaligned operand. Needs to be 16bit aligned"));
ea1562b3 2844
4670103e
CZ		 2845 if (operand->insert)
2846 {
2847 const char *errmsg = NULL;
ea1562b3 2848
4670103e
CZ		 2849 insn = (*operand->insert) (insn, val, &errmsg);
2850 if (errmsg)
2851 as_warn_where (file, line, "%s", errmsg);
2852 }
2853 else
2854 {
2855 if (operand->flags & ARC_OPERAND_TRUNCATE)
2856 {
2857 if (operand->flags & ARC_OPERAND_ALIGNED32)
2858 val >>= 2;
2859 if (operand->flags & ARC_OPERAND_ALIGNED16)
2860 val >>= 1;
886a2506 2861 }
4670103e
CZ		 2862 insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift);
2863 }
2864 return insn;
2865}
ea1562b3 2866
4670103e
CZ		 2867/* Apply a fixup to the object code. At this point all symbol values
2868 should be fully resolved, and we attempt to completely resolve the
2869 reloc. If we can not do that, we determine the correct reloc code
2870 and put it back in the fixup. To indicate that a fixup has been
2871 eliminated, set fixP->fx_done. */
ea1562b3 2872
4670103e
CZ		 2873void
2874md_apply_fix (fixS *fixP,
2875 valueT *valP,
2876 segT seg)
2877{
2878 char * const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
2879 valueT value = *valP;
2880 unsigned insn = 0;
2881 symbolS *fx_addsy, *fx_subsy;
2882 offsetT fx_offset;
2883 segT add_symbol_segment = absolute_section;
2884 segT sub_symbol_segment = absolute_section;
2885 const struct arc_operand *operand = NULL;
2886 extended_bfd_reloc_code_real_type reloc;
886a2506 2887
4670103e
CZ		 2888 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2889 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2890 ((int) fixP->fx_r_type < 0) ? "Internal":
2891 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2892 fixP->fx_offset);
886a2506 2893
4670103e
CZ		 2894 fx_addsy = fixP->fx_addsy;
2895 fx_subsy = fixP->fx_subsy;
2896 fx_offset = 0;
886a2506 2897
4670103e
CZ		 2898 if (fx_addsy)
2899 {
2900 add_symbol_segment = S_GET_SEGMENT (fx_addsy);
886a2506
NC		 2901 }
2902
4670103e
CZ		 2903 if (fx_subsy
2904 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF
2905 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF_S9
2906 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_GD_LD)
2907 {
2908 resolve_symbol_value (fx_subsy);
2909 sub_symbol_segment = S_GET_SEGMENT (fx_subsy);
886a2506 2910
4670103e
CZ		 2911 if (sub_symbol_segment == absolute_section)
2912 {
2913 /* The symbol is really a constant. */
2914 fx_offset -= S_GET_VALUE (fx_subsy);
2915 fx_subsy = NULL;
2916 }
2917 else
2918 {
2919 as_bad_where (fixP->fx_file, fixP->fx_line,
2920 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2921 fx_addsy ? S_GET_NAME (fx_addsy) : "0",
2922 segment_name (add_symbol_segment),
2923 S_GET_NAME (fx_subsy),
2924 segment_name (sub_symbol_segment));
2925 return;
2926 }
2927 }
886a2506 2928
4670103e
CZ		 2929 if (fx_addsy
2930 && !S_IS_WEAK (fx_addsy))
2931 {
2932 if (add_symbol_segment == seg
2933 && fixP->fx_pcrel)
2934 {
2935 value += S_GET_VALUE (fx_addsy);
2936 value -= md_pcrel_from_section (fixP, seg);
2937 fx_addsy = NULL;
2938 fixP->fx_pcrel = FALSE;
2939 }
2940 else if (add_symbol_segment == absolute_section)
2941 {
2942 value = fixP->fx_offset;
2943 fx_offset += S_GET_VALUE (fixP->fx_addsy);
2944 fx_addsy = NULL;
2945 fixP->fx_pcrel = FALSE;
2946 }
2947 }
886a2506 2948
4670103e
CZ		 2949 if (!fx_addsy)
2950 fixP->fx_done = TRUE;
886a2506 2951
4670103e 2952 if (fixP->fx_pcrel)
886a2506 2953 {
4670103e
CZ		 2954 if (fx_addsy
2955 && ((S_IS_DEFINED (fx_addsy)
2956 && S_GET_SEGMENT (fx_addsy) != seg)
2957 || S_IS_WEAK (fx_addsy)))
2958 value += md_pcrel_from_section (fixP, seg);
886a2506 2959
4670103e
CZ		 2960 switch (fixP->fx_r_type)
2961 {
2962 case BFD_RELOC_ARC_32_ME:
2963 /* This is a pc-relative value in a LIMM. Adjust it to the
2964 address of the instruction not to the address of the
33eaf5de 2965 LIMM. Note: it is not any longer valid this affirmation as
4670103e
CZ		 2966 the linker consider ARC_PC32 a fixup to entire 64 bit
2967 insn. */
2968 fixP->fx_offset += fixP->fx_frag->fr_address;
2969 /* Fall through. */
2970 case BFD_RELOC_32:
2971 fixP->fx_r_type = BFD_RELOC_ARC_PC32;
2972 /* Fall through. */
2973 case BFD_RELOC_ARC_PC32:
2974 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
886a2506
NC		 2975 break;
2976 default:
4670103e 2977 if ((int) fixP->fx_r_type < 0)
6e3f3473 2978 as_bad_where (fixP->fx_file, fixP->fx_line,
2979 _("PC relative relocation not allowed for (internal)"
2980 " type %d"),
2981 fixP->fx_r_type);
886a2506 2982 break;
ea1562b3
NC		 2983 }
2984 }
2985
4670103e
CZ		 2986 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2987 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2988 ((int) fixP->fx_r_type < 0) ? "Internal":
2989 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2990 fixP->fx_offset);
886a2506 2991
886a2506 2992
4670103e
CZ		 2993 /* Now check for TLS relocations. */
2994 reloc = fixP->fx_r_type;
2995 switch (reloc)
886a2506 2996 {
4670103e
CZ		 2997 case BFD_RELOC_ARC_TLS_DTPOFF:
2998 case BFD_RELOC_ARC_TLS_LE_32:
2999 if (fixP->fx_done)
3000 break;
3001 /* Fall through. */
3002 case BFD_RELOC_ARC_TLS_GD_GOT:
3003 case BFD_RELOC_ARC_TLS_IE_GOT:
3004 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3005 break;
886a2506 3006
4670103e
CZ		 3007 case BFD_RELOC_ARC_TLS_GD_LD:
3008 gas_assert (!fixP->fx_offset);
3009 if (fixP->fx_subsy)
3010 fixP->fx_offset
3011 = (S_GET_VALUE (fixP->fx_subsy)
3012 - fixP->fx_frag->fr_address- fixP->fx_where);
3013 fixP->fx_subsy = NULL;
3014 /* Fall through. */
3015 case BFD_RELOC_ARC_TLS_GD_CALL:
3016 /* These two relocs are there just to allow ld to change the tls
3017 model for this symbol, by patching the code. The offset -
3018 and scale, if any - will be installed by the linker. */
3019 S_SET_THREAD_LOCAL (fixP->fx_addsy);
3020 break;
886a2506 3021
4670103e
CZ		 3022 case BFD_RELOC_ARC_TLS_LE_S9:
3023 case BFD_RELOC_ARC_TLS_DTPOFF_S9:
3024 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3025 break;
3026
3027 default:
3028 break;
886a2506
NC		 3029 }
3030
4670103e 3031 if (!fixP->fx_done)
886a2506 3032 {
4670103e 3033 return;
886a2506 3034 }
886a2506 3035
33eaf5de 3036 /* Adjust the value if we have a constant. */
4670103e 3037 value += fx_offset;
886a2506 3038
4670103e
CZ		 3039 /* For hosts with longs bigger than 32-bits make sure that the top
3040 bits of a 32-bit negative value read in by the parser are set,
3041 so that the correct comparisons are made. */
3042 if (value & 0x80000000)
69c9e028 3043 value |= (-1UL << 31);
886a2506 3044
4670103e
CZ		 3045 reloc = fixP->fx_r_type;
3046 switch (reloc)
3047 {
3048 case BFD_RELOC_8:
3049 case BFD_RELOC_16:
3050 case BFD_RELOC_24:
3051 case BFD_RELOC_32:
3052 case BFD_RELOC_64:
3053 case BFD_RELOC_ARC_32_PCREL:
3054 md_number_to_chars (fixpos, value, fixP->fx_size);
3055 return;
886a2506 3056
4670103e
CZ		 3057 case BFD_RELOC_ARC_GOTPC32:
3058 /* I cannot fix an GOTPC relocation because I need to relax it
3059 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
3060 as_bad (_("Unsupported operation on reloc"));
3061 return;
886a2506 3062
4670103e
CZ		 3063 case BFD_RELOC_ARC_TLS_DTPOFF:
3064 case BFD_RELOC_ARC_TLS_LE_32:
3065 gas_assert (!fixP->fx_addsy);
3066 gas_assert (!fixP->fx_subsy);
1a0670f3 3067 /* Fall through. */
886a2506 3068
4670103e
CZ		 3069 case BFD_RELOC_ARC_GOTOFF:
3070 case BFD_RELOC_ARC_32_ME:
3071 case BFD_RELOC_ARC_PC32:
3072 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
3073 return;
886a2506 3074
4670103e
CZ		 3075 case BFD_RELOC_ARC_PLT32:
3076 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
3077 return;
886a2506 3078
4670103e
CZ		 3079 case BFD_RELOC_ARC_S25H_PCREL_PLT:
3080 reloc = BFD_RELOC_ARC_S25W_PCREL;
3081 goto solve_plt;
886a2506 3082
4670103e
CZ		 3083 case BFD_RELOC_ARC_S21H_PCREL_PLT:
3084 reloc = BFD_RELOC_ARC_S21H_PCREL;
3085 goto solve_plt;
886a2506 3086
4670103e
CZ		 3087 case BFD_RELOC_ARC_S25W_PCREL_PLT:
3088 reloc = BFD_RELOC_ARC_S25W_PCREL;
3089 goto solve_plt;
886a2506 3090
4670103e
CZ		 3091 case BFD_RELOC_ARC_S21W_PCREL_PLT:
3092 reloc = BFD_RELOC_ARC_S21W_PCREL;
1a0670f3 3093 /* Fall through. */
886a2506 3094
4670103e
CZ		 3095 case BFD_RELOC_ARC_S25W_PCREL:
3096 case BFD_RELOC_ARC_S21W_PCREL:
3097 case BFD_RELOC_ARC_S21H_PCREL:
3098 case BFD_RELOC_ARC_S25H_PCREL:
3099 case BFD_RELOC_ARC_S13_PCREL:
3100 solve_plt:
3101 operand = find_operand_for_reloc (reloc);
3102 gas_assert (operand);
886a2506
NC		 3103 break;
3104
3105 default:
4670103e
CZ		 3106 {
3107 if ((int) fixP->fx_r_type >= 0)
3108 as_fatal (_("unhandled relocation type %s"),
3109 bfd_get_reloc_code_name (fixP->fx_r_type));
886a2506 3110
4670103e
CZ		 3111 /* The rest of these fixups needs to be completely resolved as
3112 constants. */
3113 if (fixP->fx_addsy != 0
3114 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section)
3115 as_bad_where (fixP->fx_file, fixP->fx_line,
3116 _("non-absolute expression in constant field"));
886a2506 3117
4670103e
CZ		 3118 gas_assert (-(int) fixP->fx_r_type < (int) arc_num_operands);
3119 operand = &arc_operands[-(int) fixP->fx_r_type];
3120 break;
3121 }
3122 }
886a2506 3123
4670103e 3124 if (target_big_endian)
886a2506 3125 {
4670103e 3126 switch (fixP->fx_size)
886a2506 3127 {
4670103e
CZ		 3128 case 4:
3129 insn = bfd_getb32 (fixpos);
3130 break;
3131 case 2:
3132 insn = bfd_getb16 (fixpos);
3133 break;
3134 default:
3135 as_bad_where (fixP->fx_file, fixP->fx_line,
3136 _("unknown fixup size"));
3137 }
3138 }
3139 else
3140 {
3141 insn = 0;
3142 switch (fixP->fx_size)
3143 {
3144 case 4:
3145 insn = bfd_getl16 (fixpos) << 16 | bfd_getl16 (fixpos + 2);
3146 break;
3147 case 2:
3148 insn = bfd_getl16 (fixpos);
3149 break;
3150 default:
3151 as_bad_where (fixP->fx_file, fixP->fx_line,
3152 _("unknown fixup size"));
886a2506
NC		 3153 }
3154 }
886a2506 3155
4670103e
CZ		 3156 insn = insert_operand (insn, operand, (offsetT) value,
3157 fixP->fx_file, fixP->fx_line);
886a2506 3158
4670103e
CZ		 3159 md_number_to_chars_midend (fixpos, insn, fixP->fx_size);
3160}
886a2506 3161
4670103e 3162/* Prepare machine-dependent frags for relaxation.
886a2506 3163
4670103e
CZ		 3164 Called just before relaxation starts. Any symbol that is now undefined
3165 will not become defined.
886a2506 3166
4670103e 3167 Return the correct fr_subtype in the frag.
886a2506 3168
4670103e
CZ		 3169 Return the initial "guess for fr_var" to caller. The guess for fr_var
3170 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
3171 or fr_var contributes to our returned value.
886a2506 3172
4670103e
CZ		 3173 Although it may not be explicit in the frag, pretend
3174 fr_var starts with a value. */
886a2506 3175
4670103e
CZ		 3176int
3177md_estimate_size_before_relax (fragS *fragP,
3178 segT segment)
3179{
3180 int growth;
3181
3182 /* If the symbol is not located within the same section AND it's not
3183 an absolute section, use the maximum. OR if the symbol is a
3184 constant AND the insn is by nature not pc-rel, use the maximum.
3185 OR if the symbol is being equated against another symbol, use the
3186 maximum. OR if the symbol is weak use the maximum. */
3187 if ((S_GET_SEGMENT (fragP->fr_symbol) != segment
3188 && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section)
3189 || (symbol_constant_p (fragP->fr_symbol)
3190 && !fragP->tc_frag_data.pcrel)
3191 || symbol_equated_p (fragP->fr_symbol)
3192 || S_IS_WEAK (fragP->fr_symbol))
3193 {
3194 while (md_relax_table[fragP->fr_subtype].rlx_more != ARC_RLX_NONE)
3195 ++fragP->fr_subtype;
3196 }
886a2506 3197
4670103e
CZ		 3198 growth = md_relax_table[fragP->fr_subtype].rlx_length;
3199 fragP->fr_var = growth;
886a2506 3200
4670103e
CZ		 3201 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
3202 fragP->fr_file, fragP->fr_line, growth);
886a2506 3203
4670103e
CZ		 3204 return growth;
3205}
886a2506 3206
4670103e
CZ		 3207/* Translate internal representation of relocation info to BFD target
3208 format. */
886a2506 3209
4670103e
CZ		 3210arelent *
3211tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
3212 fixS *fixP)
3213{
3214 arelent *reloc;
3215 bfd_reloc_code_real_type code;
886a2506 3216
add39d23
TS		 3217 reloc = XNEW (arelent);
3218 reloc->sym_ptr_ptr = XNEW (asymbol *);
4670103e
CZ		 3219 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
3220 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
886a2506 3221
4670103e
CZ		 3222 /* Make sure none of our internal relocations make it this far.
3223 They'd better have been fully resolved by this point. */
3224 gas_assert ((int) fixP->fx_r_type > 0);
886a2506 3225
4670103e 3226 code = fixP->fx_r_type;
886a2506 3227
4670103e
CZ		 3228 /* if we have something like add gp, pcl,
3229 _GLOBAL_OFFSET_TABLE_@gotpc. */
3230 if (code == BFD_RELOC_ARC_GOTPC32
3231 && GOT_symbol
3232 && fixP->fx_addsy == GOT_symbol)
3233 code = BFD_RELOC_ARC_GOTPC;
886a2506 3234
4670103e
CZ		 3235 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
3236 if (reloc->howto == NULL)
886a2506 3237 {
4670103e
CZ		 3238 as_bad_where (fixP->fx_file, fixP->fx_line,
3239 _("cannot represent `%s' relocation in object file"),
3240 bfd_get_reloc_code_name (code));
3241 return NULL;
3242 }
886a2506 3243
4670103e
CZ		 3244 if (!fixP->fx_pcrel != !reloc->howto->pc_relative)
3245 as_fatal (_("internal error? cannot generate `%s' relocation"),
3246 bfd_get_reloc_code_name (code));
886a2506 3247
4670103e 3248 gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
886a2506 3249
05bbf016 3250 reloc->addend = fixP->fx_offset;
4670103e
CZ		 3251
3252 return reloc;
886a2506
NC		 3253}
3254
4670103e
CZ		 3255/* Perform post-processing of machine-dependent frags after relaxation.
3256 Called after relaxation is finished.
3257 In: Address of frag.
3258 fr_type == rs_machine_dependent.
3259 fr_subtype is what the address relaxed to.
886a2506 3260
4670103e
CZ		 3261 Out: Any fixS:s and constants are set up. */
3262
3263void
3264md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
3265 segT segment ATTRIBUTE_UNUSED,
3266 fragS *fragP)
886a2506 3267{
4670103e
CZ		 3268 const relax_typeS *table_entry;
3269 char *dest;
3270 const struct arc_opcode *opcode;
3271 struct arc_insn insn;
3272 int size, fix;
3273 struct arc_relax_type *relax_arg = &fragP->tc_frag_data;
886a2506 3274
4670103e
CZ		 3275 fix = (fragP->fr_fix < 0 ? 0 : fragP->fr_fix);
3276 dest = fragP->fr_literal + fix;
3277 table_entry = TC_GENERIC_RELAX_TABLE + fragP->fr_subtype;
886a2506 3278
9e32d9ae
AB		 3279 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, "
3280 "var: %"BFD_VMA_FMT"d\n",
4670103e
CZ		 3281 fragP->fr_file, fragP->fr_line,
3282 fragP->fr_subtype, fix, fragP->fr_var);
886a2506 3283
4670103e
CZ		 3284 if (fragP->fr_subtype <= 0
3285 && fragP->fr_subtype >= arc_num_relax_opcodes)
3286 as_fatal (_("no relaxation found for this instruction."));
886a2506 3287
4670103e 3288 opcode = &arc_relax_opcodes[fragP->fr_subtype];
886a2506 3289
4670103e
CZ		 3290 assemble_insn (opcode, relax_arg->tok, relax_arg->ntok, relax_arg->pflags,
3291 relax_arg->nflg, &insn);
886a2506 3292
4670103e 3293 apply_fixups (&insn, fragP, fix);
886a2506 3294
91fdca6f 3295 size = insn.len + (insn.has_limm ? 4 : 0);
4670103e
CZ		 3296 gas_assert (table_entry->rlx_length == size);
3297 emit_insn0 (&insn, dest, TRUE);
886a2506 3298
4670103e
CZ		 3299 fragP->fr_fix += table_entry->rlx_length;
3300 fragP->fr_var = 0;
886a2506
NC		 3301}
3302
4670103e
CZ		 3303/* We have no need to default values of symbols. We could catch
3304 register names here, but that is handled by inserting them all in
3305 the symbol table to begin with. */
886a2506 3306
4670103e
CZ		 3307symbolS *
3308md_undefined_symbol (char *name)
886a2506 3309{
4670103e
CZ		 3310 /* The arc abi demands that a GOT[0] should be referencible as
3311 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3312 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3313 if (((*name == '_')
3314 && (*(name+1) == 'G')
7ef0acc1 3315 && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)))
886a2506 3316 {
4670103e
CZ		 3317 if (!GOT_symbol)
3318 {
3319 if (symbol_find (name))
3320 as_bad ("GOT already in symbol table");
3321
3322 GOT_symbol = symbol_new (GLOBAL_OFFSET_TABLE_NAME, undefined_section,
3323 (valueT) 0, &zero_address_frag);
3324 };
3325 return GOT_symbol;
886a2506 3326 }
4670103e 3327 return NULL;
886a2506
NC		 3328}
3329
4670103e
CZ		 3330/* Turn a string in input_line_pointer into a floating point constant
3331 of type type, and store the appropriate bytes in *litP. The number
3332 of LITTLENUMS emitted is stored in *sizeP. An error message is
3333 returned, or NULL on OK. */
886a2506 3334
6d4af3c2 3335const char *
4670103e 3336md_atof (int type, char *litP, int *sizeP)
886a2506 3337{
4670103e
CZ		 3338 return ieee_md_atof (type, litP, sizeP, target_big_endian);
3339}
886a2506 3340
4670103e
CZ		 3341/* Called for any expression that can not be recognized. When the
3342 function is called, `input_line_pointer' will point to the start of
3343 the expression. */
886a2506 3344
4670103e
CZ		 3345void
3346md_operand (expressionS *expressionP ATTRIBUTE_UNUSED)
3347{
3348 char *p = input_line_pointer;
3349 if (*p == '@')
886a2506 3350 {
4670103e
CZ		 3351 input_line_pointer++;
3352 expressionP->X_op = O_symbol;
3353 expression (expressionP);
3354 }
3355}
886a2506 3356
4670103e
CZ		 3357/* This function is called from the function 'expression', it attempts
3358 to parse special names (in our case register names). It fills in
3359 the expression with the identified register. It returns TRUE if
3360 it is a register and FALSE otherwise. */
886a2506 3361
4670103e
CZ		 3362bfd_boolean
3363arc_parse_name (const char *name,
3364 struct expressionS *e)
3365{
3366 struct symbol *sym;
886a2506 3367
4670103e
CZ		 3368 if (!assembling_insn)
3369 return FALSE;
886a2506 3370
08ec958f 3371 if (e->X_op == O_symbol)
4670103e 3372 return FALSE;
886a2506 3373
4670103e
CZ		 3374 sym = hash_find (arc_reg_hash, name);
3375 if (sym)
3376 {
3377 e->X_op = O_register;
3378 e->X_add_number = S_GET_VALUE (sym);
3379 return TRUE;
3380 }
db18dbab
GM		 3381
3382 sym = hash_find (arc_addrtype_hash, name);
3383 if (sym)
3384 {
3385 e->X_op = O_addrtype;
3386 e->X_add_number = S_GET_VALUE (sym);
3387 return TRUE;
3388 }
3389
4670103e
CZ		 3390 return FALSE;
3391}
886a2506 3392
4670103e
CZ		 3393/* md_parse_option
3394 Invocation line includes a switch not recognized by the base assembler.
3395 See if it's a processor-specific option.
886a2506 3396
4670103e 3397 New options (supported) are:
886a2506 3398
4670103e
CZ		 3399 -mcpu=<cpu name> Assemble for selected processor
3400 -EB/-mbig-endian Big-endian
3401 -EL/-mlittle-endian Little-endian
3402 -mrelax Enable relaxation
886a2506 3403
4670103e 3404 The following CPU names are recognized:
ce440d63 3405 arc600, arc700, arcem, archs, nps400. */
886a2506 3406
4670103e 3407int
17b9d67d 3408md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
4670103e 3409{
4670103e
CZ		 3410 switch (c)
3411 {
3412 case OPTION_ARC600:
3413 case OPTION_ARC601:
3414 return md_parse_option (OPTION_MCPU, "arc600");
886a2506 3415
4670103e
CZ		 3416 case OPTION_ARC700:
3417 return md_parse_option (OPTION_MCPU, "arc700");
886a2506 3418
4670103e
CZ		 3419 case OPTION_ARCEM:
3420 return md_parse_option (OPTION_MCPU, "arcem");
886a2506 3421
4670103e
CZ		 3422 case OPTION_ARCHS:
3423 return md_parse_option (OPTION_MCPU, "archs");
886a2506 3424
4670103e
CZ		 3425 case OPTION_MCPU:
3426 {
bb65a718 3427 arc_select_cpu (arg, MACH_SELECTION_FROM_COMMAND_LINE);
4670103e
CZ		 3428 break;
3429 }
886a2506 3430
4670103e
CZ		 3431 case OPTION_EB:
3432 arc_target_format = "elf32-bigarc";
3433 byte_order = BIG_ENDIAN;
3434 break;
886a2506 3435
4670103e
CZ		 3436 case OPTION_EL:
3437 arc_target_format = "elf32-littlearc";
3438 byte_order = LITTLE_ENDIAN;
3439 break;
886a2506 3440
4670103e 3441 case OPTION_CD:
53a346d8
CZ		 3442 selected_cpu.features |= CD;
3443 cl_features |= CD;
bb050a69 3444 arc_check_feature ();
4670103e 3445 break;
886a2506 3446
4670103e
CZ		 3447 case OPTION_RELAX:
3448 relaxation_state = 1;
3449 break;
886a2506 3450
bdd582db 3451 case OPTION_NPS400:
53a346d8
CZ		 3452 selected_cpu.features |= NPS400;
3453 cl_features |= NPS400;
bb050a69 3454 arc_check_feature ();
ce440d63 3455 break;
bdd582db 3456
ce440d63 3457 case OPTION_SPFP:
53a346d8
CZ		 3458 selected_cpu.features |= SPX;
3459 cl_features |= SPX;
bb050a69 3460 arc_check_feature ();
ce440d63
GM		 3461 break;
3462
3463 case OPTION_DPFP:
53a346d8
CZ		 3464 selected_cpu.features |= DPX;
3465 cl_features |= DPX;
bb050a69 3466 arc_check_feature ();
ce440d63
GM		 3467 break;
3468
3469 case OPTION_FPUDA:
53a346d8
CZ		 3470 selected_cpu.features |= DPA;
3471 cl_features |= DPA;
bb050a69 3472 arc_check_feature ();
ce440d63
GM		 3473 break;
3474
3475 /* Dummy options are accepted but have no effect. */
4670103e
CZ		 3476 case OPTION_USER_MODE:
3477 case OPTION_LD_EXT_MASK:
3478 case OPTION_SWAP:
3479 case OPTION_NORM:
3480 case OPTION_BARREL_SHIFT:
3481 case OPTION_MIN_MAX:
3482 case OPTION_NO_MPY:
3483 case OPTION_EA:
3484 case OPTION_MUL64:
3485 case OPTION_SIMD:
4670103e
CZ		 3486 case OPTION_XMAC_D16:
3487 case OPTION_XMAC_24:
3488 case OPTION_DSP_PACKA:
3489 case OPTION_CRC:
3490 case OPTION_DVBF:
3491 case OPTION_TELEPHONY:
3492 case OPTION_XYMEMORY:
3493 case OPTION_LOCK:
3494 case OPTION_SWAPE:
3495 case OPTION_RTSC:
8ddf6b2a
CZ		 3496 break;
3497
4670103e
CZ		 3498 default:
3499 return 0;
3500 }
886a2506 3501
4670103e
CZ		 3502 return 1;
3503}
886a2506 3504
a9752fdf
CZ		 3505/* Display the list of cpu names for use in the help text. */
3506
3507static void
3508arc_show_cpu_list (FILE *stream)
3509{
3510 int i, offset;
731f7c4e 3511 static const char *space_buf = " ";
a9752fdf 3512
731f7c4e
MR		 3513 fprintf (stream, "%s", space_buf);
3514 offset = strlen (space_buf);
a9752fdf
CZ		 3515 for (i = 0; cpu_types[i].name != NULL; ++i)
3516 {
3517 bfd_boolean last = (cpu_types[i + 1].name == NULL);
3518
3519 /* If displaying the new cpu name string, and the ', ' (for all
3520 but the last one) will take us past a target width of 80
3521 characters, then it's time for a new line. */
3522 if (offset + strlen (cpu_types[i].name) + (last ? 0 : 2) > 80)
3523 {
731f7c4e
MR		 3524 fprintf (stream, "\n%s", space_buf);
3525 offset = strlen (space_buf);
a9752fdf
CZ		 3526 }
3527
3528 fprintf (stream, "%s%s", cpu_types[i].name, (last ? "\n" : ", "));
3529 offset += strlen (cpu_types [i].name) + (last ? 0 : 2);
3530 }
3531}
3532
4670103e
CZ		 3533void
3534md_show_usage (FILE *stream)
3535{
3536 fprintf (stream, _("ARC-specific assembler options:\n"));
886a2506 3537
a9752fdf
CZ		 3538 fprintf (stream, " -mcpu=<cpu name>\t (default: %s), assemble for"
3539 " CPU <cpu name>, one of:\n", TARGET_WITH_CPU);
3540 arc_show_cpu_list (stream);
3541 fprintf (stream, "\n");
bdd582db
GM		 3542 fprintf (stream, " -mA6/-mARC600/-mARC601 same as -mcpu=arc600\n");
3543 fprintf (stream, " -mA7/-mARC700\t\t same as -mcpu=arc700\n");
3544 fprintf (stream, " -mEM\t\t\t same as -mcpu=arcem\n");
3545 fprintf (stream, " -mHS\t\t\t same as -mcpu=archs\n");
3546
3547 fprintf (stream, " -mnps400\t\t enable NPS-400 extended instructions\n");
a9752fdf
CZ		 3548 fprintf (stream, " -mspfp\t\t enable single-precision floating point"
3549 " instructions\n");
3550 fprintf (stream, " -mdpfp\t\t enable double-precision floating point"
3551 " instructions\n");
bdd582db
GM		 3552 fprintf (stream, " -mfpuda\t\t enable double-precision assist floating "
3553 "point\n\t\t\t instructions for ARC EM\n");
3554
4670103e
CZ		 3555 fprintf (stream,
3556 " -mcode-density\t enable code density option for ARC EM\n");
3557
3558 fprintf (stream, _("\
3559 -EB assemble code for a big-endian cpu\n"));
3560 fprintf (stream, _("\
3561 -EL assemble code for a little-endian cpu\n"));
3562 fprintf (stream, _("\
bdd582db
GM		 3563 -mrelax enable relaxation\n"));
3564
3565 fprintf (stream, _("The following ARC-specific assembler options are "
3566 "deprecated and are accepted\nfor compatibility only:\n"));
3567
3568 fprintf (stream, _(" -mEA\n"
3569 " -mbarrel-shifter\n"
3570 " -mbarrel_shifter\n"
3571 " -mcrc\n"
3572 " -mdsp-packa\n"
3573 " -mdsp_packa\n"
3574 " -mdvbf\n"
3575 " -mld-extension-reg-mask\n"
3576 " -mlock\n"
3577 " -mmac-24\n"
3578 " -mmac-d16\n"
3579 " -mmac_24\n"
3580 " -mmac_d16\n"
3581 " -mmin-max\n"
3582 " -mmin_max\n"
3583 " -mmul64\n"
3584 " -mno-mpy\n"
3585 " -mnorm\n"
3586 " -mrtsc\n"
3587 " -msimd\n"
3588 " -mswap\n"
3589 " -mswape\n"
3590 " -mtelephony\n"
3591 " -muser-mode-only\n"
3592 " -mxy\n"));
886a2506
NC		 3593}
3594
3595/* Find the proper relocation for the given opcode. */
3596
3597static extended_bfd_reloc_code_real_type
3598find_reloc (const char *name,
3599 const char *opcodename,
3600 const struct arc_flags *pflags,
3601 int nflg,
3602 extended_bfd_reloc_code_real_type reloc)
3603{
3604 unsigned int i;
3605 int j;
24b368f8 3606 bfd_boolean found_flag, tmp;
886a2506
NC		 3607 extended_bfd_reloc_code_real_type ret = BFD_RELOC_UNUSED;
3608
3609 for (i = 0; i < arc_num_equiv_tab; i++)
3610 {
3611 const struct arc_reloc_equiv_tab *r = &arc_reloc_equiv[i];
3612
3613 /* Find the entry. */
3614 if (strcmp (name, r->name))
3615 continue;
3616 if (r->mnemonic && (strcmp (r->mnemonic, opcodename)))
3617 continue;
24b368f8 3618 if (r->flags[0])
886a2506
NC		 3619 {
3620 if (!nflg)
3621 continue;
3622 found_flag = FALSE;
24b368f8
CZ		 3623 unsigned * psflg = (unsigned *)r->flags;
3624 do
3625 {
3626 tmp = FALSE;
3627 for (j = 0; j < nflg; j++)
3628 if (!strcmp (pflags[j].name,
3629 arc_flag_operands[*psflg].name))
3630 {
3631 tmp = TRUE;
3632 break;
3633 }
3634 if (!tmp)
3635 {
3636 found_flag = FALSE;
3637 break;
3638 }
3639 else
3640 {
3641 found_flag = TRUE;
3642 }
3643 ++ psflg;
3644 } while (*psflg);
3645
886a2506
NC		 3646 if (!found_flag)
3647 continue;
3648 }
3649
3650 if (reloc != r->oldreloc)
3651 continue;
3652 /* Found it. */
3653 ret = r->newreloc;
3654 break;
3655 }
3656
3657 if (ret == BFD_RELOC_UNUSED)
3658 as_bad (_("Unable to find %s relocation for instruction %s"),
3659 name, opcodename);
3660 return ret;
3661}
3662
4670103e
CZ		 3663/* All the symbol types that are allowed to be used for
3664 relaxation. */
3665
3666static bfd_boolean
3667may_relax_expr (expressionS tok)
3668{
3669 /* Check if we have unrelaxable relocs. */
3670 switch (tok.X_md)
3671 {
3672 default:
3673 break;
3674 case O_plt:
3675 return FALSE;
3676 }
3677
3678 switch (tok.X_op)
3679 {
3680 case O_symbol:
3681 case O_multiply:
3682 case O_divide:
3683 case O_modulus:
3684 case O_add:
3685 case O_subtract:
3686 break;
3687
3688 default:
3689 return FALSE;
3690 }
3691 return TRUE;
3692}
3693
3694/* Checks if flags are in line with relaxable insn. */
3695
3696static bfd_boolean
3697relaxable_flag (const struct arc_relaxable_ins *ins,
3698 const struct arc_flags *pflags,
3699 int nflgs)
3700{
3701 unsigned flag_class,
3702 flag,
3703 flag_class_idx = 0,
3704 flag_idx = 0;
3705
3706 const struct arc_flag_operand *flag_opand;
3707 int i, counttrue = 0;
3708
3709 /* Iterate through flags classes. */
3710 while ((flag_class = ins->flag_classes[flag_class_idx]) != 0)
3711 {
3712 /* Iterate through flags in flag class. */
3713 while ((flag = arc_flag_classes[flag_class].flags[flag_idx])
3714 != 0)
3715 {
3716 flag_opand = &arc_flag_operands[flag];
3717 /* Iterate through flags in ins to compare. */
3718 for (i = 0; i < nflgs; ++i)
3719 {
3720 if (strcmp (flag_opand->name, pflags[i].name) == 0)
3721 ++counttrue;
3722 }
3723
3724 ++flag_idx;
3725 }
3726
3727 ++flag_class_idx;
3728 flag_idx = 0;
3729 }
3730
3731 /* If counttrue == nflgs, then all flags have been found. */
3732 return (counttrue == nflgs ? TRUE : FALSE);
3733}
3734
3735/* Checks if operands are in line with relaxable insn. */
3736
3737static bfd_boolean
3738relaxable_operand (const struct arc_relaxable_ins *ins,
3739 const expressionS *tok,
3740 int ntok)
3741{
3742 const enum rlx_operand_type *operand = &ins->operands[0];
3743 int i = 0;
3744
3745 while (*operand != EMPTY)
3746 {
3747 const expressionS *epr = &tok[i];
3748
3749 if (i != 0 && i >= ntok)
3750 return FALSE;
3751
3752 switch (*operand)
3753 {
3754 case IMMEDIATE:
3755 if (!(epr->X_op == O_multiply
3756 || epr->X_op == O_divide
3757 || epr->X_op == O_modulus
3758 || epr->X_op == O_add
3759 || epr->X_op == O_subtract
3760 || epr->X_op == O_symbol))
3761 return FALSE;
3762 break;
3763
3764 case REGISTER_DUP:
3765 if ((i <= 0)
3766 || (epr->X_add_number != tok[i - 1].X_add_number))
3767 return FALSE;
3768 /* Fall through. */
3769 case REGISTER:
3770 if (epr->X_op != O_register)
3771 return FALSE;
3772 break;
3773
3774 case REGISTER_S:
3775 if (epr->X_op != O_register)
3776 return FALSE;
3777
3778 switch (epr->X_add_number)
3779 {
3780 case 0: case 1: case 2: case 3:
3781 case 12: case 13: case 14: case 15:
3782 break;
3783 default:
3784 return FALSE;
3785 }
3786 break;
3787
3788 case REGISTER_NO_GP:
3789 if ((epr->X_op != O_register)
3790 || (epr->X_add_number == 26)) /* 26 is the gp register. */
3791 return FALSE;
3792 break;
3793
3794 case BRACKET:
3795 if (epr->X_op != O_bracket)
3796 return FALSE;
3797 break;
3798
3799 default:
3800 /* Don't understand, bail out. */
3801 return FALSE;
3802 break;
3803 }
3804
3805 ++i;
3806 operand = &ins->operands[i];
3807 }
3808
3809 return (i == ntok ? TRUE : FALSE);
3810}
3811
3812/* Return TRUE if this OPDCODE is a candidate for relaxation. */
3813
3814static bfd_boolean
3815relax_insn_p (const struct arc_opcode *opcode,
3816 const expressionS *tok,
3817 int ntok,
3818 const struct arc_flags *pflags,
3819 int nflg)
3820{
3821 unsigned i;
3822 bfd_boolean rv = FALSE;
3823
3824 /* Check the relaxation table. */
3825 for (i = 0; i < arc_num_relaxable_ins && relaxation_state; ++i)
3826 {
3827 const struct arc_relaxable_ins *arc_rlx_ins = &arc_relaxable_insns[i];
3828
3829 if ((strcmp (opcode->name, arc_rlx_ins->mnemonic_r) == 0)
3830 && may_relax_expr (tok[arc_rlx_ins->opcheckidx])
3831 && relaxable_operand (arc_rlx_ins, tok, ntok)
3832 && relaxable_flag (arc_rlx_ins, pflags, nflg))
3833 {
3834 rv = TRUE;
3835 frag_now->fr_subtype = arc_relaxable_insns[i].subtype;
3836 memcpy (&frag_now->tc_frag_data.tok, tok,
3837 sizeof (expressionS) * ntok);
3838 memcpy (&frag_now->tc_frag_data.pflags, pflags,
3839 sizeof (struct arc_flags) * nflg);
3840 frag_now->tc_frag_data.nflg = nflg;
3841 frag_now->tc_frag_data.ntok = ntok;
3842 break;
3843 }
3844 }
3845
3846 return rv;
3847}
3848
886a2506
NC		 3849/* Turn an opcode description and a set of arguments into
3850 an instruction and a fixup. */
3851
3852static void
3853assemble_insn (const struct arc_opcode *opcode,
3854 const expressionS *tok,
3855 int ntok,
3856 const struct arc_flags *pflags,
3857 int nflg,
3858 struct arc_insn *insn)
3859{
3860 const expressionS *reloc_exp = NULL;
bdfe53e3 3861 unsigned long long image;
886a2506
NC		 3862 const unsigned char *argidx;
3863 int i;
3864 int tokidx = 0;
3865 unsigned char pcrel = 0;
3866 bfd_boolean needGOTSymbol;
3867 bfd_boolean has_delay_slot = FALSE;
3868 extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
3869
3870 memset (insn, 0, sizeof (*insn));
3871 image = opcode->opcode;
3872
bdfe53e3 3873 pr_debug ("%s:%d: assemble_insn: %s using opcode %llx\n",
886a2506
NC		 3874 frag_now->fr_file, frag_now->fr_line, opcode->name,
3875 opcode->opcode);
3876
3877 /* Handle operands. */
3878 for (argidx = opcode->operands; *argidx; ++argidx)
3879 {
3880 const struct arc_operand *operand = &arc_operands[*argidx];
3881 const expressionS *t = (const expressionS *) 0;
3882
db18dbab 3883 if (ARC_OPERAND_IS_FAKE (operand))
886a2506
NC		 3884 continue;
3885
3886 if (operand->flags & ARC_OPERAND_DUPLICATE)
3887 {
3888 /* Duplicate operand, already inserted. */
3889 tokidx ++;
3890 continue;
3891 }
3892
3893 if (tokidx >= ntok)
3894 {
3895 abort ();
3896 }
3897 else
3898 t = &tok[tokidx++];
3899
3900 /* Regardless if we have a reloc or not mark the instruction
3901 limm if it is the case. */
3902 if (operand->flags & ARC_OPERAND_LIMM)
3903 insn->has_limm = TRUE;
3904
3905 switch (t->X_op)
3906 {
3907 case O_register:
3908 image = insert_operand (image, operand, regno (t->X_add_number),
3909 NULL, 0);
3910 break;
3911
3912 case O_constant:
3913 image = insert_operand (image, operand, t->X_add_number, NULL, 0);
3914 reloc_exp = t;
3915 if (operand->flags & ARC_OPERAND_LIMM)
3916 insn->limm = t->X_add_number;
3917 break;
3918
3919 case O_bracket:
db18dbab
GM		 3920 case O_colon:
3921 case O_addrtype:
3922 /* Ignore brackets, colons, and address types. */
886a2506
NC		 3923 break;
3924
3925 case O_absent:
3926 gas_assert (operand->flags & ARC_OPERAND_IGNORE);
3927 break;
3928
3929 case O_subtract:
3930 /* Maybe register range. */
3931 if ((t->X_add_number == 0)
3932 && contains_register (t->X_add_symbol)
3933 && contains_register (t->X_op_symbol))
3934 {
3935 int regs;
3936
3937 regs = get_register (t->X_add_symbol);
3938 regs <<= 16;
3939 regs |= get_register (t->X_op_symbol);
3940 image = insert_operand (image, operand, regs, NULL, 0);
3941 break;
3942 }
1a0670f3 3943 /* Fall through. */
886a2506
NC		 3944
3945 default:
3946 /* This operand needs a relocation. */
3947 needGOTSymbol = FALSE;
3948
3949 switch (t->X_md)
3950 {
3951 case O_plt:
c810e0b8 3952 if (opcode->insn_class == JUMP)
6e3f3473 3953 as_bad (_("Unable to use @plt relocation for insn %s"),
3954 opcode->name);
886a2506
NC		 3955 needGOTSymbol = TRUE;
3956 reloc = find_reloc ("plt", opcode->name,
3957 pflags, nflg,
3958 operand->default_reloc);
3959 break;
3960
3961 case O_gotoff:
3962 case O_gotpc:
3963 needGOTSymbol = TRUE;
3964 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3965 break;
3966 case O_pcl:
cc07cda6
CZ		 3967 if (operand->flags & ARC_OPERAND_LIMM)
3968 {
3969 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3970 if (arc_opcode_len (opcode) == 2
3971 || opcode->insn_class == JUMP)
6e3f3473 3972 as_bad (_("Unable to use @pcl relocation for insn %s"),
3973 opcode->name);
cc07cda6
CZ		 3974 }
3975 else
3976 {
3977 /* This is a relaxed operand which initially was
3978 limm, choose whatever we have defined in the
3979 opcode as reloc. */
3980 reloc = operand->default_reloc;
3981 }
886a2506
NC		 3982 break;
3983 case O_sda:
3984 reloc = find_reloc ("sda", opcode->name,
3985 pflags, nflg,
3986 operand->default_reloc);
3987 break;
3988 case O_tlsgd:
3989 case O_tlsie:
3990 needGOTSymbol = TRUE;
3991 /* Fall-through. */
3992
3993 case O_tpoff:
3994 case O_dtpoff:
3995 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3996 break;
3997
3998 case O_tpoff9: /*FIXME! Check for the conditionality of
3999 the insn. */
4000 case O_dtpoff9: /*FIXME! Check for the conditionality of
4001 the insn. */
4002 as_bad (_("TLS_*_S9 relocs are not supported yet"));
4003 break;
4004
4005 default:
4006 /* Just consider the default relocation. */
4007 reloc = operand->default_reloc;
4008 break;
4009 }
4010
4011 if (needGOTSymbol && (GOT_symbol == NULL))
4012 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4013
4014 reloc_exp = t;
4015
4016#if 0
4017 if (reloc > 0)
4018 {
4019 /* sanity checks. */
4020 reloc_howto_type *reloc_howto
4021 = bfd_reloc_type_lookup (stdoutput,
4022 (bfd_reloc_code_real_type) reloc);
4023 unsigned reloc_bitsize = reloc_howto->bitsize;
4024 if (reloc_howto->rightshift)
4025 reloc_bitsize -= reloc_howto->rightshift;
4026 if (reloc_bitsize != operand->bits)
4027 {
4028 as_bad (_("invalid relocation %s for field"),
4029 bfd_get_reloc_code_name (reloc));
4030 return;
4031 }
4032 }
4033#endif
4034 if (insn->nfixups >= MAX_INSN_FIXUPS)
4035 as_fatal (_("too many fixups"));
4036
4037 struct arc_fixup *fixup;
4038 fixup = &insn->fixups[insn->nfixups++];
4039 fixup->exp = *t;
4040 fixup->reloc = reloc;
cc07cda6
CZ		 4041 if ((int) reloc < 0)
4042 pcrel = (operand->flags & ARC_OPERAND_PCREL) ? 1 : 0;
4043 else
4044 {
4045 reloc_howto_type *reloc_howto =
4046 bfd_reloc_type_lookup (stdoutput,
4047 (bfd_reloc_code_real_type) fixup->reloc);
4048 pcrel = reloc_howto->pc_relative;
4049 }
886a2506
NC		 4050 fixup->pcrel = pcrel;
4051 fixup->islong = (operand->flags & ARC_OPERAND_LIMM) ?
4052 TRUE : FALSE;
4053 break;
4054 }
4055 }
4056
4057 /* Handle flags. */
4058 for (i = 0; i < nflg; i++)
4059 {
f36e33da 4060 const struct arc_flag_operand *flg_operand = pflags[i].flgp;
886a2506
NC		 4061
4062 /* Check if the instruction has a delay slot. */
4063 if (!strcmp (flg_operand->name, "d"))
4064 has_delay_slot = TRUE;
4065
2c52e2e8
RZ		 4066 /* There is an exceptional case when we cannot insert a flag just as
4067 it is. On ARCv2 the '.t' and '.nt' flags must be handled in
4068 relation with the relative address. Unfortunately, some of the
4069 ARC700 extensions (NPS400) also have a '.nt' flag that should be
4070 handled in the normal way.
4071
4072 Flag operands don't have an architecture field, so we can't
4073 directly validate that FLAG_OPERAND is valid for the current
4074 architecture, what we do instead is just validate that we're
4075 assembling for an ARCv2 architecture. */
4076 if ((selected_cpu.flags & ARC_OPCODE_ARCV2)
4077 && (!strcmp (flg_operand->name, "t")
4078 || !strcmp (flg_operand->name, "nt")))
886a2506
NC		 4079 {
4080 unsigned bitYoperand = 0;
4081 /* FIXME! move selection bbit/brcc in arc-opc.c. */
4082 if (!strcmp (flg_operand->name, "t"))
4083 if (!strcmp (opcode->name, "bbit0")
4084 || !strcmp (opcode->name, "bbit1"))
4085 bitYoperand = arc_NToperand;
4086 else
4087 bitYoperand = arc_Toperand;
4088 else
4089 if (!strcmp (opcode->name, "bbit0")
4090 || !strcmp (opcode->name, "bbit1"))
4091 bitYoperand = arc_Toperand;
4092 else
4093 bitYoperand = arc_NToperand;
4094
4095 gas_assert (reloc_exp != NULL);
4096 if (reloc_exp->X_op == O_constant)
4097 {
4098 /* Check if we have a constant and solved it
4099 immediately. */
4100 offsetT val = reloc_exp->X_add_number;
4101 image |= insert_operand (image, &arc_operands[bitYoperand],
4102 val, NULL, 0);
4103 }
4104 else
4105 {
4106 struct arc_fixup *fixup;
4107
4108 if (insn->nfixups >= MAX_INSN_FIXUPS)
4109 as_fatal (_("too many fixups"));
4110
4111 fixup = &insn->fixups[insn->nfixups++];
4112 fixup->exp = *reloc_exp;
4113 fixup->reloc = -bitYoperand;
4114 fixup->pcrel = pcrel;
4115 fixup->islong = FALSE;
4116 }
4117 }
4118 else
4119 image |= (flg_operand->code & ((1 << flg_operand->bits) - 1))
4120 << flg_operand->shift;
4121 }
4122
4670103e
CZ		 4123 insn->relax = relax_insn_p (opcode, tok, ntok, pflags, nflg);
4124
91fdca6f 4125 /* Instruction length. */
06fe285f 4126 insn->len = arc_opcode_len (opcode);
886a2506
NC		 4127
4128 insn->insn = image;
4129
4130 /* Update last insn status. */
4131 arc_last_insns[1] = arc_last_insns[0];
4132 arc_last_insns[0].opcode = opcode;
4133 arc_last_insns[0].has_limm = insn->has_limm;
4134 arc_last_insns[0].has_delay_slot = has_delay_slot;
4135
4136 /* Check if the current instruction is legally used. */
4137 if (arc_last_insns[1].has_delay_slot
4138 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
6e3f3473 4139 as_bad (_("Insn %s has a jump/branch instruction %s in its delay slot."),
4140 arc_last_insns[1].opcode->name,
4141 arc_last_insns[0].opcode->name);
cf9bdae9 4142 if (arc_last_insns[1].has_delay_slot
4143 && arc_last_insns[0].has_limm)
4144 as_bad (_("Insn %s has an instruction %s with limm in its delay slot."),
4145 arc_last_insns[1].opcode->name,
4146 arc_last_insns[0].opcode->name);
886a2506
NC		 4147}
4148
886a2506
NC		 4149void
4150arc_handle_align (fragS* fragP)
4151{
4152 if ((fragP)->fr_type == rs_align_code)
4153 {
4154 char *dest = (fragP)->fr_literal + (fragP)->fr_fix;
4155 valueT count = ((fragP)->fr_next->fr_address
4156 - (fragP)->fr_address - (fragP)->fr_fix);
4157
4158 (fragP)->fr_var = 2;
4159
4160 if (count & 1)/* Padding in the gap till the next 2-byte
4161 boundary with 0s. */
4162 {
4163 (fragP)->fr_fix++;
4164 *dest++ = 0;
4165 }
4166 /* Writing nop_s. */
4167 md_number_to_chars (dest, NOP_OPCODE_S, 2);
4168 }
4169}
4170
4171/* Here we decide which fixups can be adjusted to make them relative
4172 to the beginning of the section instead of the symbol. Basically
4173 we need to make sure that the dynamic relocations are done
4174 correctly, so in some cases we force the original symbol to be
4175 used. */
4176
4177int
4178tc_arc_fix_adjustable (fixS *fixP)
4179{
4180
4181 /* Prevent all adjustments to global symbols. */
4182 if (S_IS_EXTERNAL (fixP->fx_addsy))
4183 return 0;
4184 if (S_IS_WEAK (fixP->fx_addsy))
4185 return 0;
4186
4187 /* Adjust_reloc_syms doesn't know about the GOT. */
4188 switch (fixP->fx_r_type)
4189 {
4190 case BFD_RELOC_ARC_GOTPC32:
4191 case BFD_RELOC_ARC_PLT32:
4192 case BFD_RELOC_ARC_S25H_PCREL_PLT:
4193 case BFD_RELOC_ARC_S21H_PCREL_PLT:
4194 case BFD_RELOC_ARC_S25W_PCREL_PLT:
4195 case BFD_RELOC_ARC_S21W_PCREL_PLT:
4196 return 0;
4197
4198 default:
4199 break;
4200 }
4201
841fdfcd 4202 return 1;
886a2506
NC		 4203}
4204
4205/* Compute the reloc type of an expression EXP. */
4206
4207static void
4208arc_check_reloc (expressionS *exp,
4209 bfd_reloc_code_real_type *r_type_p)
4210{
4211 if (*r_type_p == BFD_RELOC_32
4212 && exp->X_op == O_subtract
4213 && exp->X_op_symbol != NULL
4214 && exp->X_op_symbol->bsym->section == now_seg)
6f4b1afc 4215 *r_type_p = BFD_RELOC_ARC_32_PCREL;
886a2506
NC		 4216}
4217
4218
4219/* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
4220
4221void
4222arc_cons_fix_new (fragS *frag,
4223 int off,
4224 int size,
4225 expressionS *exp,
4226 bfd_reloc_code_real_type r_type)
4227{
4228 r_type = BFD_RELOC_UNUSED;
4229
4230 switch (size)
4231 {
4232 case 1:
4233 r_type = BFD_RELOC_8;
4234 break;
4235
4236 case 2:
4237 r_type = BFD_RELOC_16;
4238 break;
4239
4240 case 3:
4241 r_type = BFD_RELOC_24;
4242 break;
4243
4244 case 4:
4245 r_type = BFD_RELOC_32;
4246 arc_check_reloc (exp, &r_type);
4247 break;
4248
4249 case 8:
4250 r_type = BFD_RELOC_64;
4251 break;
4252
4253 default:
4254 as_bad (_("unsupported BFD relocation size %u"), size);
4255 r_type = BFD_RELOC_UNUSED;
4256 }
4257
4258 fix_new_exp (frag, off, size, exp, 0, r_type);
4259}
4260
4261/* The actual routine that checks the ZOL conditions. */
4262
4263static void
4264check_zol (symbolS *s)
4265{
bb65a718 4266 switch (selected_cpu.mach)
886a2506
NC		 4267 {
4268 case bfd_mach_arc_arcv2:
bb65a718 4269 if (selected_cpu.flags & ARC_OPCODE_ARCv2EM)
886a2506
NC		 4270 return;
4271
4272 if (is_br_jmp_insn_p (arc_last_insns[0].opcode)
4273 || arc_last_insns[1].has_delay_slot)
4274 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
4275 S_GET_NAME (s));
4276
4277 break;
4278 case bfd_mach_arc_arc600:
4279
4280 if (is_kernel_insn_p (arc_last_insns[0].opcode))
4281 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
4282 S_GET_NAME (s));
4283
4284 if (arc_last_insns[0].has_limm
4285 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
4286 as_bad (_("A jump instruction with long immediate detected at the \
4287end of the ZOL label @%s"), S_GET_NAME (s));
4288
4289 /* Fall through. */
4290 case bfd_mach_arc_arc700:
4291 if (arc_last_insns[0].has_delay_slot)
4292 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
4293 S_GET_NAME (s));
4294
4295 break;
4296 default:
4297 break;
4298 }
4299}
4300
4301/* If ZOL end check the last two instruction for illegals. */
4302void
4303arc_frob_label (symbolS * sym)
4304{
4305 if (ARC_GET_FLAG (sym) & ARC_FLAG_ZOL)
4306 check_zol (sym);
4307
4308 dwarf2_emit_label (sym);
ea1562b3 4309}
4670103e
CZ		 4310
4311/* Used because generic relaxation assumes a pc-rel value whilst we
4312 also relax instructions that use an absolute value resolved out of
4313 relative values (if that makes any sense). An example: 'add r1,
4314 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
4315 but if they're in the same section we can subtract the section
4316 offset relocation which ends up in a resolved value. So if @.L2 is
4317 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
4318 .text + 0x40 = 0x10. */
4319int
4320arc_pcrel_adjust (fragS *fragP)
4321{
cc07cda6
CZ		 4322 pr_debug ("arc_pcrel_adjust: address=%ld, fix=%ld, PCrel %s\n",
4323 fragP->fr_address, fragP->fr_fix,
4324 fragP->tc_frag_data.pcrel ? "Y" : "N");
4325
4670103e
CZ		 4326 if (!fragP->tc_frag_data.pcrel)
4327 return fragP->fr_address + fragP->fr_fix;
4328
cc07cda6
CZ		 4329 /* Take into account the PCL rounding. */
4330 return (fragP->fr_address + fragP->fr_fix) & 0x03;
4670103e 4331}
726c18e1
CZ		 4332
4333/* Initialize the DWARF-2 unwind information for this procedure. */
4334
4335void
4336tc_arc_frame_initial_instructions (void)
4337{
4338 /* Stack pointer is register 28. */
45a54ee5 4339 cfi_add_CFA_def_cfa (28, 0);
726c18e1
CZ		 4340}
4341
4342int
4343tc_arc_regname_to_dw2regnum (char *regname)
4344{
4345 struct symbol *sym;
4346
4347 sym = hash_find (arc_reg_hash, regname);
4348 if (sym)
4349 return S_GET_VALUE (sym);
4350
4351 return -1;
4352}
37ab9779
CZ		 4353
4354/* Adjust the symbol table. Delete found AUX register symbols. */
4355
4356void
4357arc_adjust_symtab (void)
4358{
4359 symbolS * sym;
4360
4361 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
4362 {
4363 /* I've created a symbol during parsing process. Now, remove
4364 the symbol as it is found to be an AUX register. */
4365 if (ARC_GET_FLAG (sym) & ARC_FLAG_AUX)
4366 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
4367 }
4368
4369 /* Now do generic ELF adjustments. */
4370 elf_adjust_symtab ();
4371}
b99747ae
CZ		 4372
4373static void
4374tokenize_extinsn (extInstruction_t *einsn)
4375{
4376 char *p, c;
4377 char *insn_name;
4378 unsigned char major_opcode;
4379 unsigned char sub_opcode;
4380 unsigned char syntax_class = 0;
4381 unsigned char syntax_class_modifiers = 0;
4382 unsigned char suffix_class = 0;
4383 unsigned int i;
4384
4385 SKIP_WHITESPACE ();
4386
4387 /* 1st: get instruction name. */
4388 p = input_line_pointer;
4389 c = get_symbol_name (&p);
4390
4391 insn_name = xstrdup (p);
4392 restore_line_pointer (c);
4393
f02806be 4394 /* Convert to lower case. */
4395 for (p = insn_name; *p; ++p)
4396 *p = TOLOWER (*p);
4397
b99747ae
CZ		 4398 /* 2nd: get major opcode. */
4399 if (*input_line_pointer != ',')
4400 {
4401 as_bad (_("expected comma after instruction name"));
4402 ignore_rest_of_line ();
4403 return;
4404 }
4405 input_line_pointer++;
4406 major_opcode = get_absolute_expression ();
4407
4408 /* 3rd: get sub-opcode. */
4409 SKIP_WHITESPACE ();
4410
4411 if (*input_line_pointer != ',')
4412 {
4413 as_bad (_("expected comma after major opcode"));
4414 ignore_rest_of_line ();
4415 return;
4416 }
4417 input_line_pointer++;
4418 sub_opcode = get_absolute_expression ();
4419
4420 /* 4th: get suffix class. */
4421 SKIP_WHITESPACE ();
4422
4423 if (*input_line_pointer != ',')
4424 {
4425 as_bad ("expected comma after sub opcode");
4426 ignore_rest_of_line ();
4427 return;
4428 }
4429 input_line_pointer++;
4430
4431 while (1)
4432 {
4433 SKIP_WHITESPACE ();
4434
4435 for (i = 0; i < ARRAY_SIZE (suffixclass); i++)
4436 {
4437 if (!strncmp (suffixclass[i].name, input_line_pointer,
4438 suffixclass[i].len))
4439 {
c810e0b8 4440 suffix_class |= suffixclass[i].attr_class;
b99747ae
CZ		 4441 input_line_pointer += suffixclass[i].len;
4442 break;
4443 }
4444 }
4445
4446 if (i == ARRAY_SIZE (suffixclass))
4447 {
4448 as_bad ("invalid suffix class");
4449 ignore_rest_of_line ();
4450 return;
4451 }
4452
4453 SKIP_WHITESPACE ();
4454
4455 if (*input_line_pointer == '|')
4456 input_line_pointer++;
4457 else
4458 break;
4459 }
4460
4461 /* 5th: get syntax class and syntax class modifiers. */
4462 if (*input_line_pointer != ',')
4463 {
4464 as_bad ("expected comma after suffix class");
4465 ignore_rest_of_line ();
4466 return;
4467 }
4468 input_line_pointer++;
4469
4470 while (1)
4471 {
4472 SKIP_WHITESPACE ();
4473
4474 for (i = 0; i < ARRAY_SIZE (syntaxclassmod); i++)
4475 {
4476 if (!strncmp (syntaxclassmod[i].name,
4477 input_line_pointer,
4478 syntaxclassmod[i].len))
4479 {
c810e0b8 4480 syntax_class_modifiers |= syntaxclassmod[i].attr_class;
b99747ae
CZ		 4481 input_line_pointer += syntaxclassmod[i].len;
4482 break;
4483 }
4484 }
4485
4486 if (i == ARRAY_SIZE (syntaxclassmod))
4487 {
4488 for (i = 0; i < ARRAY_SIZE (syntaxclass); i++)
4489 {
4490 if (!strncmp (syntaxclass[i].name,
4491 input_line_pointer,
4492 syntaxclass[i].len))
4493 {
c810e0b8 4494 syntax_class |= syntaxclass[i].attr_class;
b99747ae
CZ		 4495 input_line_pointer += syntaxclass[i].len;
4496 break;
4497 }
4498 }
4499
4500 if (i == ARRAY_SIZE (syntaxclass))
4501 {
4502 as_bad ("missing syntax class");
4503 ignore_rest_of_line ();
4504 return;
4505 }
4506 }
4507
4508 SKIP_WHITESPACE ();
4509
4510 if (*input_line_pointer == '|')
4511 input_line_pointer++;
4512 else
4513 break;
4514 }
4515
4516 demand_empty_rest_of_line ();
4517
4518 einsn->name = insn_name;
4519 einsn->major = major_opcode;
4520 einsn->minor = sub_opcode;
4521 einsn->syntax = syntax_class;
4522 einsn->modsyn = syntax_class_modifiers;
4523 einsn->suffix = suffix_class;
4524 einsn->flags = syntax_class
4525 | (syntax_class_modifiers & ARC_OP1_IMM_IMPLIED ? 0x10 : 0);
4526}
4527
4528/* Generate an extension section. */
4529
4530static int
4531arc_set_ext_seg (void)
4532{
4533 if (!arcext_section)
4534 {
4535 arcext_section = subseg_new (".arcextmap", 0);
4536 bfd_set_section_flags (stdoutput, arcext_section,
4537 SEC_READONLY | SEC_HAS_CONTENTS);
4538 }
4539 else
4540 subseg_set (arcext_section, 0);
4541 return 1;
4542}
4543
4544/* Create an extension instruction description in the arc extension
4545 section of the output file.
4546 The structure for an instruction is like this:
4547 [0]: Length of the record.
4548 [1]: Type of the record.
4549
4550 [2]: Major opcode.
4551 [3]: Sub-opcode.
4552 [4]: Syntax (flags).
4553 [5]+ Name instruction.
4554
4555 The sequence is terminated by an empty entry. */
4556
4557static void
4558create_extinst_section (extInstruction_t *einsn)
4559{
4560
4561 segT old_sec = now_seg;
4562 int old_subsec = now_subseg;
4563 char *p;
4564 int name_len = strlen (einsn->name);
4565
4566 arc_set_ext_seg ();
4567
4568 p = frag_more (1);
4569 *p = 5 + name_len + 1;
4570 p = frag_more (1);
4571 *p = EXT_INSTRUCTION;
4572 p = frag_more (1);
4573 *p = einsn->major;
4574 p = frag_more (1);
4575 *p = einsn->minor;
4576 p = frag_more (1);
4577 *p = einsn->flags;
4578 p = frag_more (name_len + 1);
4579 strcpy (p, einsn->name);
4580
4581 subseg_set (old_sec, old_subsec);
4582}
4583
4584/* Handler .extinstruction pseudo-op. */
4585
4586static void
4587arc_extinsn (int ignore ATTRIBUTE_UNUSED)
4588{
4589 extInstruction_t einsn;
4590 struct arc_opcode *arc_ext_opcodes;
4591 const char *errmsg = NULL;
4592 unsigned char moplow, mophigh;
4593
4594 memset (&einsn, 0, sizeof (einsn));
4595 tokenize_extinsn (&einsn);
4596
4597 /* Check if the name is already used. */
4598 if (arc_find_opcode (einsn.name))
4599 as_warn (_("Pseudocode already used %s"), einsn.name);
4600
4601 /* Check the opcode ranges. */
4602 moplow = 0x05;
bb65a718
AB		 4603 mophigh = (selected_cpu.flags & (ARC_OPCODE_ARCv2EM
4604 | ARC_OPCODE_ARCv2HS)) ? 0x07 : 0x0a;
b99747ae
CZ		 4605
4606 if ((einsn.major > mophigh) || (einsn.major < moplow))
4607 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow, mophigh);
4608
4609 if ((einsn.minor > 0x3f) && (einsn.major != 0x0a)
4610 && (einsn.major != 5) && (einsn.major != 9))
4611 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4612
945e0f82 4613 switch (einsn.syntax & ARC_SYNTAX_MASK)
b99747ae
CZ		 4614 {
4615 case ARC_SYNTAX_3OP:
4616 if (einsn.modsyn & ARC_OP1_IMM_IMPLIED)
4617 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4618 break;
4619 case ARC_SYNTAX_2OP:
945e0f82
CZ		 4620 case ARC_SYNTAX_1OP:
4621 case ARC_SYNTAX_NOP:
b99747ae
CZ		 4622 if (einsn.modsyn & ARC_OP1_MUST_BE_IMM)
4623 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4624 break;
4625 default:
4626 break;
4627 }
4628
bb65a718 4629 arc_ext_opcodes = arcExtMap_genOpcode (&einsn, selected_cpu.flags, &errmsg);
b99747ae
CZ		 4630 if (arc_ext_opcodes == NULL)
4631 {
4632 if (errmsg)
4633 as_fatal ("%s", errmsg);
4634 else
4635 as_fatal (_("Couldn't generate extension instruction opcodes"));
4636 }
4637 else if (errmsg)
4638 as_warn ("%s", errmsg);
4639
4640 /* Insert the extension instruction. */
4641 arc_insert_opcode ((const struct arc_opcode *) arc_ext_opcodes);
4642
4643 create_extinst_section (&einsn);
4644}
4645
06911889 4646static bfd_boolean
f36e33da
CZ		 4647tokenize_extregister (extRegister_t *ereg, int opertype)
4648{
4649 char *name;
4650 char *mode;
4651 char c;
4652 char *p;
4653 int number, imode = 0;
4654 bfd_boolean isCore_p = (opertype == EXT_CORE_REGISTER) ? TRUE : FALSE;
4655 bfd_boolean isReg_p = (opertype == EXT_CORE_REGISTER
4656 || opertype == EXT_AUX_REGISTER) ? TRUE : FALSE;
4657
4658 /* 1st: get register name. */
4659 SKIP_WHITESPACE ();
4660 p = input_line_pointer;
4661 c = get_symbol_name (&p);
4662
4663 name = xstrdup (p);
4664 restore_line_pointer (c);
4665
4666 /* 2nd: get register number. */
4667 SKIP_WHITESPACE ();
4668
4669 if (*input_line_pointer != ',')
4670 {
06911889 4671 as_bad (_("expected comma after name"));
f36e33da
CZ		 4672 ignore_rest_of_line ();
4673 free (name);
06911889 4674 return FALSE;
f36e33da
CZ		 4675 }
4676 input_line_pointer++;
4677 number = get_absolute_expression ();
4678
06911889
CZ		 4679 if ((number < 0)
4680 && (opertype != EXT_AUX_REGISTER))
f36e33da 4681 {
06911889
CZ		 4682 as_bad (_("%s second argument cannot be a negative number %d"),
4683 isCore_p ? "extCoreRegister's" : "extCondCode's",
4684 number);
f36e33da
CZ		 4685 ignore_rest_of_line ();
4686 free (name);
06911889 4687 return FALSE;
f36e33da
CZ		 4688 }
4689
4690 if (isReg_p)
4691 {
4692 /* 3rd: get register mode. */
4693 SKIP_WHITESPACE ();
4694
4695 if (*input_line_pointer != ',')
4696 {
4697 as_bad (_("expected comma after register number"));
4698 ignore_rest_of_line ();
4699 free (name);
06911889 4700 return FALSE;
f36e33da
CZ		 4701 }
4702
4703 input_line_pointer++;
4704 mode = input_line_pointer;
4705
4706 if (!strncmp (mode, "r|w", 3))
4707 {
4708 imode = 0;
4709 input_line_pointer += 3;
4710 }
4711 else if (!strncmp (mode, "r", 1))
4712 {
4713 imode = ARC_REGISTER_READONLY;
4714 input_line_pointer += 1;
4715 }
4716 else if (strncmp (mode, "w", 1))
4717 {
4718 as_bad (_("invalid mode"));
4719 ignore_rest_of_line ();
4720 free (name);
06911889 4721 return FALSE;
f36e33da
CZ		 4722 }
4723 else
4724 {
4725 imode = ARC_REGISTER_WRITEONLY;
4726 input_line_pointer += 1;
4727 }
4728 }
4729
4730 if (isCore_p)
4731 {
4732 /* 4th: get core register shortcut. */
4733 SKIP_WHITESPACE ();
4734 if (*input_line_pointer != ',')
4735 {
4736 as_bad (_("expected comma after register mode"));
4737 ignore_rest_of_line ();
4738 free (name);
06911889 4739 return FALSE;
f36e33da
CZ		 4740 }
4741
4742 input_line_pointer++;
4743
4744 if (!strncmp (input_line_pointer, "cannot_shortcut", 15))
4745 {
4746 imode |= ARC_REGISTER_NOSHORT_CUT;
4747 input_line_pointer += 15;
4748 }
4749 else if (strncmp (input_line_pointer, "can_shortcut", 12))
4750 {
4751 as_bad (_("shortcut designator invalid"));
4752 ignore_rest_of_line ();
4753 free (name);
06911889 4754 return FALSE;
f36e33da
CZ		 4755 }
4756 else
4757 {
4758 input_line_pointer += 12;
4759 }
4760 }
4761 demand_empty_rest_of_line ();
4762
4763 ereg->name = name;
4764 ereg->number = number;
4765 ereg->imode = imode;
06911889 4766 return TRUE;
f36e33da
CZ		 4767}
4768
4769/* Create an extension register/condition description in the arc
4770 extension section of the output file.
4771
4772 The structure for an instruction is like this:
4773 [0]: Length of the record.
4774 [1]: Type of the record.
4775
4776 For core regs and condition codes:
4777 [2]: Value.
4778 [3]+ Name.
4779
33eaf5de 4780 For auxiliary registers:
f36e33da
CZ		 4781 [2..5]: Value.
4782 [6]+ Name
4783
4784 The sequence is terminated by an empty entry. */
4785
4786static void
4787create_extcore_section (extRegister_t *ereg, int opertype)
4788{
4789 segT old_sec = now_seg;
4790 int old_subsec = now_subseg;
4791 char *p;
4792 int name_len = strlen (ereg->name);
4793
4794 arc_set_ext_seg ();
4795
4796 switch (opertype)
4797 {
4798 case EXT_COND_CODE:
4799 case EXT_CORE_REGISTER:
4800 p = frag_more (1);
4801 *p = 3 + name_len + 1;
4802 p = frag_more (1);
4803 *p = opertype;
4804 p = frag_more (1);
4805 *p = ereg->number;
4806 break;
4807 case EXT_AUX_REGISTER:
4808 p = frag_more (1);
4809 *p = 6 + name_len + 1;
4810 p = frag_more (1);
4811 *p = EXT_AUX_REGISTER;
4812 p = frag_more (1);
4813 *p = (ereg->number >> 24) & 0xff;
4814 p = frag_more (1);
4815 *p = (ereg->number >> 16) & 0xff;
4816 p = frag_more (1);
4817 *p = (ereg->number >> 8) & 0xff;
4818 p = frag_more (1);
4819 *p = (ereg->number) & 0xff;
4820 break;
4821 default:
4822 break;
4823 }
4824
4825 p = frag_more (name_len + 1);
4826 strcpy (p, ereg->name);
4827
4828 subseg_set (old_sec, old_subsec);
4829}
4830
4831/* Handler .extCoreRegister pseudo-op. */
4832
4833static void
4834arc_extcorereg (int opertype)
4835{
4836 extRegister_t ereg;
4837 struct arc_aux_reg *auxr;
4838 const char *retval;
4839 struct arc_flag_operand *ccode;
4840
4841 memset (&ereg, 0, sizeof (ereg));
06911889
CZ		 4842 if (!tokenize_extregister (&ereg, opertype))
4843 return;
f36e33da
CZ		 4844
4845 switch (opertype)
4846 {
4847 case EXT_CORE_REGISTER:
4848 /* Core register. */
4849 if (ereg.number > 60)
4850 as_bad (_("core register %s value (%d) too large"), ereg.name,
4851 ereg.number);
4852 declare_register (ereg.name, ereg.number);
4853 break;
4854 case EXT_AUX_REGISTER:
4855 /* Auxiliary register. */
add39d23 4856 auxr = XNEW (struct arc_aux_reg);
f36e33da 4857 auxr->name = ereg.name;
bb65a718 4858 auxr->cpu = selected_cpu.flags;
f36e33da
CZ		 4859 auxr->subclass = NONE;
4860 auxr->address = ereg.number;
4861 retval = hash_insert (arc_aux_hash, auxr->name, (void *) auxr);
4862 if (retval)
4863 as_fatal (_("internal error: can't hash aux register '%s': %s"),
4864 auxr->name, retval);
4865 break;
4866 case EXT_COND_CODE:
4867 /* Condition code. */
4868 if (ereg.number > 31)
4869 as_bad (_("condition code %s value (%d) too large"), ereg.name,
4870 ereg.number);
4871 ext_condcode.size ++;
4872 ext_condcode.arc_ext_condcode =
add39d23
TS		 4873 XRESIZEVEC (struct arc_flag_operand, ext_condcode.arc_ext_condcode,
4874 ext_condcode.size + 1);
f36e33da
CZ		 4875 if (ext_condcode.arc_ext_condcode == NULL)
4876 as_fatal (_("Virtual memory exhausted"));
4877
4878 ccode = ext_condcode.arc_ext_condcode + ext_condcode.size - 1;
4879 ccode->name = ereg.name;
4880 ccode->code = ereg.number;
4881 ccode->bits = 5;
4882 ccode->shift = 0;
4883 ccode->favail = 0; /* not used. */
4884 ccode++;
4885 memset (ccode, 0, sizeof (struct arc_flag_operand));
4886 break;
4887 default:
4888 as_bad (_("Unknown extension"));
4889 break;
4890 }
4891 create_extcore_section (&ereg, opertype);
4892}
4893
53a346d8
CZ		 4894/* Parse a .arc_attribute directive. */
4895
4896static void
4897arc_attribute (int ignored ATTRIBUTE_UNUSED)
4898{
4899 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
4900
4901 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4902 attributes_set_explicitly[tag] = TRUE;
4903}
4904
4905/* Set an attribute if it has not already been set by the user. */
4906
4907static void
4908arc_set_attribute_int (int tag, int value)
4909{
4910 if (tag < 1
4911 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
4912 || !attributes_set_explicitly[tag])
4913 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
4914}
4915
4916static void
4917arc_set_attribute_string (int tag, const char *value)
4918{
4919 if (tag < 1
4920 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
4921 || !attributes_set_explicitly[tag])
4922 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
4923}
4924
4925/* Allocate and concatenate two strings. s1 can be NULL but not
4926 s2. s1 pointer is freed at end of this procedure. */
4927
4928static char *
4929arc_stralloc (char * s1, const char * s2)
4930{
4931 char * p;
4932 int len = 0;
4933
4934 if (s1)
4935 len = strlen (s1) + 1;
4936
4937 /* Only s1 can be null. */
4938 gas_assert (s2);
4939 len += strlen (s2) + 1;
4940
4941 p = (char *) xmalloc (len);
4942 if (p == NULL)
4943 as_fatal (_("Virtual memory exhausted"));
4944
4945 if (s1)
4946 {
4947 strcpy (p, s1);
4948 strcat (p, ",");
4949 strcat (p, s2);
4950 free (s1);
4951 }
4952 else
4953 strcpy (p, s2);
4954
4955 return p;
4956}
4957
4958/* Set the public ARC object attributes. */
4959
4960static void
4961arc_set_public_attributes (void)
4962{
4963 int base = 0;
4964 char *s = NULL;
4965 unsigned int i;
4966
4967 /* Tag_ARC_CPU_name. */
4968 arc_set_attribute_string (Tag_ARC_CPU_name, selected_cpu.name);
4969
4970 /* Tag_ARC_CPU_base. */
4971 switch (selected_cpu.eflags & EF_ARC_MACH_MSK)
4972 {
4973 case E_ARC_MACH_ARC600:
4974 case E_ARC_MACH_ARC601:
4975 base = TAG_CPU_ARC6xx;
4976 break;
4977 case E_ARC_MACH_ARC700:
4978 base = TAG_CPU_ARC7xx;
4979 break;
4980 case EF_ARC_CPU_ARCV2EM:
4981 base = TAG_CPU_ARCEM;
4982 break;
4983 case EF_ARC_CPU_ARCV2HS:
4984 base = TAG_CPU_ARCHS;
4985 break;
4986 default:
4987 base = 0;
4988 break;
4989 }
4990 if (attributes_set_explicitly[Tag_ARC_CPU_base]
4991 && (base != bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
4992 Tag_ARC_CPU_base)))
4993 as_warn (_("Overwrite explicitly set Tag_ARC_CPU_base"));
4994 bfd_elf_add_proc_attr_int (stdoutput, Tag_ARC_CPU_base, base);
4995
4996 /* Tag_ARC_ABI_osver. */
4997 if (attributes_set_explicitly[Tag_ARC_ABI_osver])
4998 {
4999 int val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
5000 Tag_ARC_ABI_osver);
5001
5002 selected_cpu.eflags = ((selected_cpu.eflags & ~EF_ARC_OSABI_MSK)
5003 | (val & 0x0f << 8));
5004 }
5005 else
5006 {
5007 arc_set_attribute_int (Tag_ARC_ABI_osver, E_ARC_OSABI_CURRENT >> 8);
5008 }
5009
5010 /* Tag_ARC_ISA_config. */
5011 arc_check_feature();
5012
5013 for (i = 0; i < ARRAY_SIZE (feature_list); i++)
5014 if (selected_cpu.features & feature_list[i].feature)
5015 s = arc_stralloc (s, feature_list[i].attr);
5016
5017 if (s)
5018 arc_set_attribute_string (Tag_ARC_ISA_config, s);
5019
5020 /* Tag_ARC_ISA_mpy_option. */
5021 arc_set_attribute_int (Tag_ARC_ISA_mpy_option, mpy_option);
5022
5023 /* Tag_ARC_ABI_pic. */
5024 arc_set_attribute_int (Tag_ARC_ABI_pic, pic_option);
5025
5026 /* Tag_ARC_ABI_sda. */
5027 arc_set_attribute_int (Tag_ARC_ABI_sda, sda_option);
5028
5029 /* Tag_ARC_ABI_tls. */
5030 arc_set_attribute_int (Tag_ARC_ABI_tls, tls_option);
db1e1b45 5031
5032 /* Tag_ARC_ATR_version. */
5033 arc_set_attribute_int (Tag_ARC_ATR_version, 1);
63741043 5034
5035 /* Tag_ARC_ABI_rf16. */
5036 if (attributes_set_explicitly[Tag_ARC_ABI_rf16]
5037 && bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_PROC,
5038 Tag_ARC_ABI_rf16)
5039 && !rf16_only)
5040 {
5041 as_warn (_("Overwrite explicitly set Tag_ARC_ABI_rf16 to full "
5042 "register file"));
5043 bfd_elf_add_proc_attr_int (stdoutput, Tag_ARC_ABI_rf16, 0);
5044 }
53a346d8
CZ		 5045}
5046
5047/* Add the default contents for the .ARC.attributes section. */
5048
5049void
5050arc_md_end (void)
5051{
5052 arc_set_public_attributes ();
5053
5054 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, selected_cpu.mach))
5055 as_fatal (_("could not set architecture and machine"));
5056
5057 bfd_set_private_flags (stdoutput, selected_cpu.eflags);
5058}
5059
5060void arc_copy_symbol_attributes (symbolS *dest, symbolS *src)
5061{
5062 ARC_GET_FLAG (dest) = ARC_GET_FLAG (src);
5063}
5064
5065int arc_convert_symbolic_attribute (const char *name)
5066{
5067 static const struct
5068 {
5069 const char * name;
5070 const int tag;
5071 }
5072 attribute_table[] =
5073 {
5074#define T(tag) {#tag, tag}
5075 T (Tag_ARC_PCS_config),
5076 T (Tag_ARC_CPU_base),
5077 T (Tag_ARC_CPU_variation),
5078 T (Tag_ARC_CPU_name),
5079 T (Tag_ARC_ABI_rf16),
5080 T (Tag_ARC_ABI_osver),
5081 T (Tag_ARC_ABI_sda),
5082 T (Tag_ARC_ABI_pic),
5083 T (Tag_ARC_ABI_tls),
5084 T (Tag_ARC_ABI_enumsize),
5085 T (Tag_ARC_ABI_exceptions),
5086 T (Tag_ARC_ABI_double_size),
5087 T (Tag_ARC_ISA_config),
5088 T (Tag_ARC_ISA_apex),
db1e1b45 5089 T (Tag_ARC_ISA_mpy_option),
5090 T (Tag_ARC_ATR_version)
53a346d8
CZ		 5091#undef T
5092 };
5093 unsigned int i;
5094
5095 if (name == NULL)
5096 return -1;
5097
5098 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
5099 if (streq (name, attribute_table[i].name))
5100 return attribute_table[i].tag;
5101
5102 return -1;
5103}
5104
b99747ae
CZ		 5105/* Local variables:
5106 eval: (c-set-style "gnu")
5107 indent-tabs-mode: t
5108 End: */
GDB Binutils - Deliverables
This page took 1.094793 seconds and 4 git commands to generate.