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Add support for .extCondCode, .extCoreRegister and .extAuxRegister.
[deliverable/binutils-gdb.git] / gas / config / tc-arc.c
CommitLineData
252b5132 1/* tc-arc.c -- Assembler for the ARC
6f2750fe 2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributor: Claudiu Zissulescu <claziss@synopsys.com>
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19203624 19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
252b5132 23#include "as.h"
886a2506 24#include "subsegs.h"
a161fe53 25#include "struc-symbol.h"
886a2506 26#include "dwarf2dbg.h"
726c18e1 27#include "dw2gencfi.h"
3882b010 28#include "safe-ctype.h"
886a2506 29
252b5132
RH		 30#include "opcode/arc.h"
31#include "elf/arc.h"
b99747ae 32#include "../opcodes/arc-ext.h"
252b5132 33
886a2506 34/* Defines section. */
0d2bcfaf 35
886a2506
NC		 36#define MAX_INSN_FIXUPS 2
37#define MAX_CONSTR_STR 20
4670103e 38#define FRAG_MAX_GROWTH 8
0d2bcfaf 39
886a2506
NC		 40#ifdef DEBUG
41# define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
42#else
43# define pr_debug(fmt, args...)
44#endif
45
46#define MAJOR_OPCODE(x) (((x) & 0xF8000000) >> 27)
47#define SUB_OPCODE(x) (((x) & 0x003F0000) >> 16)
4670103e 48#define LP_INSN(x) ((MAJOR_OPCODE (x) == 0x4) && \
886a2506
NC		 49 (SUB_OPCODE (x) == 0x28))
50
51/* Equal to MAX_PRECISION in atof-ieee.c. */
52#define MAX_LITTLENUMS 6
53
4670103e
CZ		 54/* Enum used to enumerate the relaxable ins operands. */
55enum rlx_operand_type
56{
57 EMPTY = 0,
58 REGISTER,
59 REGISTER_S, /* Register for short instruction(s). */
60 REGISTER_NO_GP, /* Is a register but not gp register specifically. */
61 REGISTER_DUP, /* Duplication of previous operand of type register. */
62 IMMEDIATE,
63 BRACKET
64};
65
66enum arc_rlx_types
67{
68 ARC_RLX_NONE = 0,
69 ARC_RLX_BL_S,
70 ARC_RLX_BL,
71 ARC_RLX_B_S,
72 ARC_RLX_B,
73 ARC_RLX_ADD_U3,
74 ARC_RLX_ADD_U6,
75 ARC_RLX_ADD_LIMM,
76 ARC_RLX_LD_U7,
77 ARC_RLX_LD_S9,
78 ARC_RLX_LD_LIMM,
79 ARC_RLX_MOV_U8,
80 ARC_RLX_MOV_S12,
81 ARC_RLX_MOV_LIMM,
82 ARC_RLX_SUB_U3,
83 ARC_RLX_SUB_U6,
84 ARC_RLX_SUB_LIMM,
85 ARC_RLX_MPY_U6,
86 ARC_RLX_MPY_LIMM,
87 ARC_RLX_MOV_RU6,
88 ARC_RLX_MOV_RLIMM,
89 ARC_RLX_ADD_RRU6,
90 ARC_RLX_ADD_RRLIMM,
91};
92
886a2506
NC		 93/* Macros section. */
94
95#define regno(x) ((x) & 0x3F)
96#define is_ir_num(x) (((x) & ~0x3F) == 0)
8ddf6b2a
CZ		 97#define is_code_density_p(sc) (((sc) == CD1 || (sc) == CD2))
98#define is_spfp_p(op) (((sc) == SPX))
99#define is_dpfp_p(op) (((sc) == DPX))
100#define is_fpuda_p(op) (((sc) == DPA))
886a2506
NC		 101#define is_br_jmp_insn_p(op) (((op)->class == BRANCH || (op)->class == JUMP))
102#define is_kernel_insn_p(op) (((op)->class == KERNEL))
0d2bcfaf 103
886a2506
NC		 104/* Generic assembler global variables which must be defined by all
105 targets. */
0d2bcfaf 106
886a2506 107/* Characters which always start a comment. */
252b5132
RH		 108const char comment_chars[] = "#;";
109
886a2506 110/* Characters which start a comment at the beginning of a line. */
252b5132
RH		 111const char line_comment_chars[] = "#";
112
886a2506
NC		 113/* Characters which may be used to separate multiple commands on a
114 single line. */
115const char line_separator_chars[] = "`";
252b5132 116
886a2506
NC		 117/* Characters which are used to indicate an exponent in a floating
118 point number. */
252b5132
RH		 119const char EXP_CHARS[] = "eE";
120
bcee8eb8
AM		 121/* Chars that mean this number is a floating point constant
122 As in 0f12.456 or 0d1.2345e12. */
252b5132
RH		 123const char FLT_CHARS[] = "rRsSfFdD";
124
125/* Byte order. */
126extern int target_big_endian;
127const char *arc_target_format = DEFAULT_TARGET_FORMAT;
128static int byte_order = DEFAULT_BYTE_ORDER;
129
b99747ae
CZ		 130/* Arc extension section. */
131static segT arcext_section;
132
4670103e
CZ		 133/* By default relaxation is disabled. */
134static int relaxation_state = 0;
135
886a2506 136extern int arc_get_mach (char *);
0d2bcfaf 137
4670103e 138/* Forward declarations. */
886a2506
NC		 139static void arc_lcomm (int);
140static void arc_option (int);
141static void arc_extra_reloc (int);
b99747ae 142static void arc_extinsn (int);
f36e33da 143static void arc_extcorereg (int);
4670103e 144
886a2506 145const pseudo_typeS md_pseudo_table[] =
6f4b1afc
CM		 146{
147 /* Make sure that .word is 32 bits. */
148 { "word", cons, 4 },
886a2506 149
6f4b1afc
CM		 150 { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */
151 { "lcomm", arc_lcomm, 0 },
152 { "lcommon", arc_lcomm, 0 },
153 { "cpu", arc_option, 0 },
252b5132 154
f36e33da
CZ		 155 { "extinstruction", arc_extinsn, 0 },
156 { "extcoreregister", arc_extcorereg, EXT_CORE_REGISTER },
157 { "extauxregister", arc_extcorereg, EXT_AUX_REGISTER },
158 { "extcondcode", arc_extcorereg, EXT_COND_CODE },
b99747ae 159
6f4b1afc
CM		 160 { "tls_gd_ld", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_LD },
161 { "tls_gd_call", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_CALL },
886a2506 162
6f4b1afc
CM		 163 { NULL, NULL, 0 }
164};
252b5132 165
252b5132 166const char *md_shortopts = "";
ea1562b3
NC		 167
168enum options
6f4b1afc
CM		 169{
170 OPTION_EB = OPTION_MD_BASE,
171 OPTION_EL,
172
173 OPTION_ARC600,
174 OPTION_ARC601,
175 OPTION_ARC700,
176 OPTION_ARCEM,
177 OPTION_ARCHS,
178
179 OPTION_MCPU,
180 OPTION_CD,
4670103e 181 OPTION_RELAX,
6f4b1afc
CM		 182
183 /* The following options are deprecated and provided here only for
184 compatibility reasons. */
185 OPTION_USER_MODE,
186 OPTION_LD_EXT_MASK,
187 OPTION_SWAP,
188 OPTION_NORM,
189 OPTION_BARREL_SHIFT,
190 OPTION_MIN_MAX,
191 OPTION_NO_MPY,
192 OPTION_EA,
193 OPTION_MUL64,
194 OPTION_SIMD,
195 OPTION_SPFP,
196 OPTION_DPFP,
197 OPTION_XMAC_D16,
198 OPTION_XMAC_24,
199 OPTION_DSP_PACKA,
200 OPTION_CRC,
201 OPTION_DVBF,
202 OPTION_TELEPHONY,
203 OPTION_XYMEMORY,
204 OPTION_LOCK,
205 OPTION_SWAPE,
206 OPTION_RTSC,
207 OPTION_FPUDA
208};
ea1562b3
NC		 209
210struct option md_longopts[] =
6f4b1afc
CM		 211{
212 { "EB", no_argument, NULL, OPTION_EB },
213 { "EL", no_argument, NULL, OPTION_EL },
214 { "mcpu", required_argument, NULL, OPTION_MCPU },
215 { "mA6", no_argument, NULL, OPTION_ARC600 },
24b368f8
CZ		 216 { "mARC600", no_argument, NULL, OPTION_ARC600 },
217 { "mARC601", no_argument, NULL, OPTION_ARC601 },
218 { "mARC700", no_argument, NULL, OPTION_ARC700 },
6f4b1afc
CM		 219 { "mA7", no_argument, NULL, OPTION_ARC700 },
220 { "mEM", no_argument, NULL, OPTION_ARCEM },
221 { "mHS", no_argument, NULL, OPTION_ARCHS },
222 { "mcode-density", no_argument, NULL, OPTION_CD },
4670103e 223 { "mrelax", no_argument, NULL, OPTION_RELAX },
6f4b1afc
CM		 224
225 /* The following options are deprecated and provided here only for
226 compatibility reasons. */
227 { "mav2em", no_argument, NULL, OPTION_ARCEM },
228 { "mav2hs", no_argument, NULL, OPTION_ARCHS },
229 { "muser-mode-only", no_argument, NULL, OPTION_USER_MODE },
230 { "mld-extension-reg-mask", required_argument, NULL, OPTION_LD_EXT_MASK },
231 { "mswap", no_argument, NULL, OPTION_SWAP },
232 { "mnorm", no_argument, NULL, OPTION_NORM },
233 { "mbarrel-shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
234 { "mbarrel_shifter", no_argument, NULL, OPTION_BARREL_SHIFT },
235 { "mmin-max", no_argument, NULL, OPTION_MIN_MAX },
236 { "mmin_max", no_argument, NULL, OPTION_MIN_MAX },
237 { "mno-mpy", no_argument, NULL, OPTION_NO_MPY },
238 { "mea", no_argument, NULL, OPTION_EA },
239 { "mEA", no_argument, NULL, OPTION_EA },
240 { "mmul64", no_argument, NULL, OPTION_MUL64 },
241 { "msimd", no_argument, NULL, OPTION_SIMD},
242 { "mspfp", no_argument, NULL, OPTION_SPFP},
243 { "mspfp-compact", no_argument, NULL, OPTION_SPFP},
244 { "mspfp_compact", no_argument, NULL, OPTION_SPFP},
245 { "mspfp-fast", no_argument, NULL, OPTION_SPFP},
246 { "mspfp_fast", no_argument, NULL, OPTION_SPFP},
247 { "mdpfp", no_argument, NULL, OPTION_DPFP},
248 { "mdpfp-compact", no_argument, NULL, OPTION_DPFP},
249 { "mdpfp_compact", no_argument, NULL, OPTION_DPFP},
250 { "mdpfp-fast", no_argument, NULL, OPTION_DPFP},
251 { "mdpfp_fast", no_argument, NULL, OPTION_DPFP},
252 { "mmac-d16", no_argument, NULL, OPTION_XMAC_D16},
253 { "mmac_d16", no_argument, NULL, OPTION_XMAC_D16},
254 { "mmac-24", no_argument, NULL, OPTION_XMAC_24},
255 { "mmac_24", no_argument, NULL, OPTION_XMAC_24},
256 { "mdsp-packa", no_argument, NULL, OPTION_DSP_PACKA},
257 { "mdsp_packa", no_argument, NULL, OPTION_DSP_PACKA},
258 { "mcrc", no_argument, NULL, OPTION_CRC},
259 { "mdvbf", no_argument, NULL, OPTION_DVBF},
260 { "mtelephony", no_argument, NULL, OPTION_TELEPHONY},
261 { "mxy", no_argument, NULL, OPTION_XYMEMORY},
262 { "mlock", no_argument, NULL, OPTION_LOCK},
263 { "mswape", no_argument, NULL, OPTION_SWAPE},
264 { "mrtsc", no_argument, NULL, OPTION_RTSC},
265 { "mfpuda", no_argument, NULL, OPTION_FPUDA},
266
267 { NULL, no_argument, NULL, 0 }
268};
252b5132 269
886a2506 270size_t md_longopts_size = sizeof (md_longopts);
0d2bcfaf 271
886a2506 272/* Local data and data types. */
252b5132 273
886a2506
NC		 274/* Used since new relocation types are introduced in this
275 file (DUMMY_RELOC_LITUSE_*). */
276typedef int extended_bfd_reloc_code_real_type;
252b5132 277
886a2506 278struct arc_fixup
252b5132 279{
886a2506 280 expressionS exp;
252b5132 281
886a2506 282 extended_bfd_reloc_code_real_type reloc;
252b5132 283
886a2506
NC		 284 /* index into arc_operands. */
285 unsigned int opindex;
252b5132 286
886a2506
NC		 287 /* PC-relative, used by internals fixups. */
288 unsigned char pcrel;
252b5132 289
886a2506
NC		 290 /* TRUE if this fixup is for LIMM operand. */
291 bfd_boolean islong;
292};
252b5132 293
886a2506
NC		 294struct arc_insn
295{
296 unsigned int insn;
297 int nfixups;
298 struct arc_fixup fixups[MAX_INSN_FIXUPS];
299 long limm;
300 bfd_boolean short_insn; /* Boolean value: TRUE if current insn is
301 short. */
302 bfd_boolean has_limm; /* Boolean value: TRUE if limm field is
303 valid. */
4670103e
CZ		 304 bfd_boolean relax; /* Boolean value: TRUE if needs
305 relaxation. */
886a2506 306};
ea1562b3 307
886a2506
NC		 308/* Structure to hold any last two instructions. */
309static struct arc_last_insn
252b5132 310{
886a2506
NC		 311 /* Saved instruction opcode. */
312 const struct arc_opcode *opcode;
252b5132 313
886a2506
NC		 314 /* Boolean value: TRUE if current insn is short. */
315 bfd_boolean has_limm;
252b5132 316
886a2506
NC		 317 /* Boolean value: TRUE if current insn has delay slot. */
318 bfd_boolean has_delay_slot;
319} arc_last_insns[2];
252b5132 320
b99747ae
CZ		 321/* Extension instruction suffix classes. */
322typedef struct
323{
324 const char *name;
325 int len;
326 int class;
327} attributes_t;
328
329static const attributes_t suffixclass[] =
330{
331 { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG },
332 { "SUFFIX_COND", 11, ARC_SUFFIX_COND },
333 { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE }
334};
335
336/* Extension instruction syntax classes. */
337static const attributes_t syntaxclass[] =
338{
339 { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP },
340 { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP }
341};
342
343/* Extension instruction syntax classes modifiers. */
344static const attributes_t syntaxclassmod[] =
345{
346 { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED },
347 { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM }
348};
349
f36e33da
CZ		 350/* Extension register type. */
351typedef struct
352{
353 char *name;
354 int number;
355 int imode;
356} extRegister_t;
357
358/* A structure to hold the additional conditional codes. */
359static struct
360{
361 struct arc_flag_operand *arc_ext_condcode;
362 int size;
363} ext_condcode = { NULL, 0 };
364
da5be039
AB		 365/* Structure to hold an entry in ARC_OPCODE_HASH. */
366struct arc_opcode_hash_entry
367{
368 /* The number of pointers in the OPCODE list. */
369 size_t count;
370
371 /* Points to a list of opcode pointers. */
372 const struct arc_opcode **opcode;
373};
374
1328504b
AB		 375/* Structure used for iterating through an arc_opcode_hash_entry. */
376struct arc_opcode_hash_entry_iterator
377{
378 /* Index into the OPCODE element of the arc_opcode_hash_entry. */
379 size_t index;
380
381 /* The specific ARC_OPCODE from the ARC_OPCODES table that was last
382 returned by this iterator. */
383 const struct arc_opcode *opcode;
384};
385
4670103e
CZ		 386/* Forward declaration. */
387static void assemble_insn
388 (const struct arc_opcode *, const expressionS *, int,
389 const struct arc_flags *, int, struct arc_insn *);
390
886a2506 391/* The cpu for which we are generating code. */
24740d83
AB		 392static unsigned arc_target;
393static const char *arc_target_name;
394static unsigned arc_features;
252b5132 395
886a2506 396/* The default architecture. */
24740d83 397static int arc_mach_type;
252b5132 398
886a2506
NC		 399/* Non-zero if the cpu type has been explicitly specified. */
400static int mach_type_specified_p = 0;
0d2bcfaf 401
886a2506
NC		 402/* The hash table of instruction opcodes. */
403static struct hash_control *arc_opcode_hash;
0d2bcfaf 404
886a2506
NC		 405/* The hash table of register symbols. */
406static struct hash_control *arc_reg_hash;
252b5132 407
f36e33da
CZ		 408/* The hash table of aux register symbols. */
409static struct hash_control *arc_aux_hash;
410
886a2506
NC		 411/* A table of CPU names and opcode sets. */
412static const struct cpu_type
413{
414 const char *name;
415 unsigned flags;
416 int mach;
417 unsigned eflags;
418 unsigned features;
252b5132 419}
886a2506 420 cpu_types[] =
252b5132 421{
886a2506
NC		 422 { "arc600", ARC_OPCODE_ARC600, bfd_mach_arc_arc600,
423 E_ARC_MACH_ARC600, 0x00},
424 { "arc700", ARC_OPCODE_ARC700, bfd_mach_arc_arc700,
425 E_ARC_MACH_ARC700, 0x00},
8699fc3e
AB		 426 { "nps400", ARC_OPCODE_ARC700 | ARC_OPCODE_NPS400, bfd_mach_arc_nps400,
427 E_ARC_MACH_NPS400, 0x00},
886a2506 428 { "arcem", ARC_OPCODE_ARCv2EM, bfd_mach_arc_arcv2,
7e458899 429 EF_ARC_CPU_ARCV2EM, ARC_CD},
886a2506
NC		 430 { "archs", ARC_OPCODE_ARCv2HS, bfd_mach_arc_arcv2,
431 EF_ARC_CPU_ARCV2HS, ARC_CD},
886a2506
NC		 432 { 0, 0, 0, 0, 0 }
433};
252b5132 434
886a2506
NC		 435/* Used by the arc_reloc_op table. Order is important. */
436#define O_gotoff O_md1 /* @gotoff relocation. */
437#define O_gotpc O_md2 /* @gotpc relocation. */
438#define O_plt O_md3 /* @plt relocation. */
439#define O_sda O_md4 /* @sda relocation. */
440#define O_pcl O_md5 /* @pcl relocation. */
441#define O_tlsgd O_md6 /* @tlsgd relocation. */
442#define O_tlsie O_md7 /* @tlsie relocation. */
443#define O_tpoff9 O_md8 /* @tpoff9 relocation. */
444#define O_tpoff O_md9 /* @tpoff relocation. */
445#define O_dtpoff9 O_md10 /* @dtpoff9 relocation. */
446#define O_dtpoff O_md11 /* @dtpoff relocation. */
447#define O_last O_dtpoff
448
449/* Used to define a bracket as operand in tokens. */
450#define O_bracket O_md32
451
452/* Dummy relocation, to be sorted out. */
453#define DUMMY_RELOC_ARC_ENTRY (BFD_RELOC_UNUSED + 1)
454
455#define USER_RELOC_P(R) ((R) >= O_gotoff && (R) <= O_last)
456
457/* A table to map the spelling of a relocation operand into an appropriate
458 bfd_reloc_code_real_type type. The table is assumed to be ordered such
459 that op-O_literal indexes into it. */
460#define ARC_RELOC_TABLE(op) \
461 (&arc_reloc_op[ ((!USER_RELOC_P (op)) \
462 ? (abort (), 0) \
463 : (int) (op) - (int) O_gotoff) ])
464
465#define DEF(NAME, RELOC, REQ) \
466 { #NAME, sizeof (#NAME)-1, O_##NAME, RELOC, REQ}
467
468static const struct arc_reloc_op_tag
469{
470 /* String to lookup. */
471 const char *name;
472 /* Size of the string. */
473 size_t length;
474 /* Which operator to use. */
475 operatorT op;
476 extended_bfd_reloc_code_real_type reloc;
477 /* Allows complex relocation expression like identifier@reloc +
478 const. */
479 unsigned int complex_expr : 1;
480}
481 arc_reloc_op[] =
6f4b1afc
CM		 482{
483 DEF (gotoff, BFD_RELOC_ARC_GOTOFF, 1),
484 DEF (gotpc, BFD_RELOC_ARC_GOTPC32, 0),
485 DEF (plt, BFD_RELOC_ARC_PLT32, 0),
486 DEF (sda, DUMMY_RELOC_ARC_ENTRY, 1),
487 DEF (pcl, BFD_RELOC_ARC_PC32, 1),
488 DEF (tlsgd, BFD_RELOC_ARC_TLS_GD_GOT, 0),
489 DEF (tlsie, BFD_RELOC_ARC_TLS_IE_GOT, 0),
490 DEF (tpoff9, BFD_RELOC_ARC_TLS_LE_S9, 0),
b125bd17 491 DEF (tpoff, BFD_RELOC_ARC_TLS_LE_32, 1),
6f4b1afc
CM		 492 DEF (dtpoff9, BFD_RELOC_ARC_TLS_DTPOFF_S9, 0),
493 DEF (dtpoff, BFD_RELOC_ARC_TLS_DTPOFF, 0),
494};
252b5132 495
886a2506
NC		 496static const int arc_num_reloc_op
497= sizeof (arc_reloc_op) / sizeof (*arc_reloc_op);
498
4670103e
CZ		 499/* Structure for relaxable instruction that have to be swapped with a
500 smaller alternative instruction. */
501struct arc_relaxable_ins
502{
503 /* Mnemonic that should be checked. */
504 const char *mnemonic_r;
505
506 /* Operands that should be checked.
507 Indexes of operands from operand array. */
508 enum rlx_operand_type operands[6];
509
510 /* Flags that should be checked. */
511 unsigned flag_classes[5];
512
513 /* Mnemonic (smaller) alternative to be used later for relaxation. */
514 const char *mnemonic_alt;
515
516 /* Index of operand that generic relaxation has to check. */
517 unsigned opcheckidx;
518
519 /* Base subtype index used. */
520 enum arc_rlx_types subtype;
521};
522
523#define RELAX_TABLE_ENTRY(BITS, ISSIGNED, SIZE, NEXT) \
524 { (ISSIGNED) ? ((1 << ((BITS) - 1)) - 1) : ((1 << (BITS)) - 1), \
525 (ISSIGNED) ? -(1 << ((BITS) - 1)) : 0, \
526 (SIZE), \
527 (NEXT) } \
528
529#define RELAX_TABLE_ENTRY_MAX(ISSIGNED, SIZE, NEXT) \
530 { (ISSIGNED) ? 0x7FFFFFFF : 0xFFFFFFFF, \
531 (ISSIGNED) ? -(0x7FFFFFFF) : 0, \
532 (SIZE), \
533 (NEXT) } \
534
535
536/* ARC relaxation table. */
537const relax_typeS md_relax_table[] =
538{
539 /* Fake entry. */
540 {0, 0, 0, 0},
541
542 /* BL_S s13 ->
543 BL s25. */
544 RELAX_TABLE_ENTRY(13, 1, 2, ARC_RLX_BL),
545 RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE),
546
547 /* B_S s10 ->
548 B s25. */
549 RELAX_TABLE_ENTRY(10, 1, 2, ARC_RLX_B),
550 RELAX_TABLE_ENTRY(25, 1, 4, ARC_RLX_NONE),
551
552 /* ADD_S c,b, u3 ->
553 ADD<.f> a,b,u6 ->
554 ADD<.f> a,b,limm. */
555 RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_ADD_U6),
556 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_LIMM),
557 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
558
559 /* LD_S a, [b, u7] ->
560 LD<zz><.x><.aa><.di> a, [b, s9] ->
561 LD<zz><.x><.aa><.di> a, [b, limm] */
562 RELAX_TABLE_ENTRY(7, 0, 2, ARC_RLX_LD_S9),
563 RELAX_TABLE_ENTRY(9, 1, 4, ARC_RLX_LD_LIMM),
564 RELAX_TABLE_ENTRY_MAX(1, 8, ARC_RLX_NONE),
565
566 /* MOV_S b, u8 ->
567 MOV<.f> b, s12 ->
568 MOV<.f> b, limm. */
569 RELAX_TABLE_ENTRY(8, 0, 2, ARC_RLX_MOV_S12),
570 RELAX_TABLE_ENTRY(8, 0, 4, ARC_RLX_MOV_LIMM),
571 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
572
573 /* SUB_S c, b, u3 ->
574 SUB<.f> a, b, u6 ->
575 SUB<.f> a, b, limm. */
576 RELAX_TABLE_ENTRY(3, 0, 2, ARC_RLX_SUB_U6),
577 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_SUB_LIMM),
578 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
579
580 /* MPY<.f> a, b, u6 ->
581 MPY<.f> a, b, limm. */
582 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MPY_LIMM),
583 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
584
585 /* MOV<.f><.cc> b, u6 ->
586 MOV<.f><.cc> b, limm. */
587 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_MOV_RLIMM),
588 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
589
590 /* ADD<.f><.cc> b, b, u6 ->
591 ADD<.f><.cc> b, b, limm. */
592 RELAX_TABLE_ENTRY(6, 0, 4, ARC_RLX_ADD_RRLIMM),
593 RELAX_TABLE_ENTRY_MAX(0, 8, ARC_RLX_NONE),
594};
595
596/* Order of this table's entries matters! */
597const struct arc_relaxable_ins arc_relaxable_insns[] =
598{
599 { "bl", { IMMEDIATE }, { 0 }, "bl_s", 0, ARC_RLX_BL_S },
600 { "b", { IMMEDIATE }, { 0 }, "b_s", 0, ARC_RLX_B_S },
601 { "add", { REGISTER, REGISTER_DUP, IMMEDIATE }, { 5, 1, 0 }, "add",
602 2, ARC_RLX_ADD_RRU6},
603 { "add", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "add_s", 2,
604 ARC_RLX_ADD_U3 },
605 { "add", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "add", 2,
606 ARC_RLX_ADD_U6 },
607 { "ld", { REGISTER_S, BRACKET, REGISTER_S, IMMEDIATE, BRACKET },
608 { 0 }, "ld_s", 3, ARC_RLX_LD_U7 },
609 { "ld", { REGISTER, BRACKET, REGISTER_NO_GP, IMMEDIATE, BRACKET },
610 { 11, 4, 14, 17, 0 }, "ld", 3, ARC_RLX_LD_S9 },
611 { "mov", { REGISTER_S, IMMEDIATE }, { 0 }, "mov_s", 1, ARC_RLX_MOV_U8 },
612 { "mov", { REGISTER, IMMEDIATE }, { 5, 0 }, "mov", 1, ARC_RLX_MOV_S12 },
613 { "mov", { REGISTER, IMMEDIATE }, { 5, 1, 0 },"mov", 1, ARC_RLX_MOV_RU6 },
614 { "sub", { REGISTER_S, REGISTER_S, IMMEDIATE }, { 0 }, "sub_s", 2,
615 ARC_RLX_SUB_U3 },
616 { "sub", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "sub", 2,
617 ARC_RLX_SUB_U6 },
618 { "mpy", { REGISTER, REGISTER, IMMEDIATE }, { 5, 0 }, "mpy", 2,
619 ARC_RLX_MPY_U6 },
620};
621
622const unsigned arc_num_relaxable_ins = ARRAY_SIZE (arc_relaxable_insns);
623
886a2506
NC		 624/* Flags to set in the elf header. */
625static flagword arc_eflag = 0x00;
626
627/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
628symbolS * GOT_symbol = 0;
629
630/* Set to TRUE when we assemble instructions. */
631static bfd_boolean assembling_insn = FALSE;
632
886a2506
NC		 633/* Functions implementation. */
634
b9b47ab7
AB		 635/* Return a pointer to ARC_OPCODE_HASH_ENTRY that identifies all
636 ARC_OPCODE entries in ARC_OPCODE_HASH that match NAME, or NULL if there
637 are no matching entries in ARC_OPCODE_HASH. */
da5be039 638
b9b47ab7 639static const struct arc_opcode_hash_entry *
da5be039
AB		 640arc_find_opcode (const char *name)
641{
642 const struct arc_opcode_hash_entry *entry;
da5be039
AB		 643
644 entry = hash_find (arc_opcode_hash, name);
b9b47ab7 645 return entry;
da5be039
AB		 646}
647
1328504b
AB		 648/* Initialise the iterator ITER. */
649
650static void
651arc_opcode_hash_entry_iterator_init (struct arc_opcode_hash_entry_iterator *iter)
652{
653 iter->index = 0;
654 iter->opcode = NULL;
655}
656
657/* Return the next ARC_OPCODE from ENTRY, using ITER to hold state between
658 calls to this function. Return NULL when all ARC_OPCODE entries have
659 been returned. */
660
661static const struct arc_opcode *
662arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry *entry,
663 struct arc_opcode_hash_entry_iterator *iter)
664{
665 if (iter->opcode == NULL && iter->index == 0)
666 {
667 gas_assert (entry->count > 0);
668 iter->opcode = entry->opcode[iter->index];
669 }
670 else if (iter->opcode != NULL)
671 {
672 const char *old_name = iter->opcode->name;
673
674 iter->opcode++;
b99747ae
CZ		 675 if (iter->opcode->name
676 && (strcmp (old_name, iter->opcode->name) != 0))
1328504b
AB		 677 {
678 iter->index++;
679 if (iter->index == entry->count)
680 iter->opcode = NULL;
681 else
682 iter->opcode = entry->opcode[iter->index];
683 }
684 }
685
686 return iter->opcode;
687}
688
b99747ae
CZ		 689/* Insert an opcode into opcode hash structure. */
690
691static void
692arc_insert_opcode (const struct arc_opcode *opcode)
693{
694 const char *name, *retval;
695 struct arc_opcode_hash_entry *entry;
696 name = opcode->name;
697
698 entry = hash_find (arc_opcode_hash, name);
699 if (entry == NULL)
700 {
701 entry = xmalloc (sizeof (*entry));
702 entry->count = 0;
703 entry->opcode = NULL;
704
705 retval = hash_insert (arc_opcode_hash, name, (void *) entry);
706 if (retval)
707 as_fatal (_("internal error: can't hash opcode '%s': %s"),
708 name, retval);
709 }
710
711 entry->opcode = xrealloc (entry->opcode,
712 sizeof (const struct arc_opcode *)
713 * (entry->count + 1));
714
715 if (entry->opcode == NULL)
716 as_fatal (_("Virtual memory exhausted"));
717
718 entry->opcode[entry->count] = opcode;
719 entry->count++;
720}
721
722
886a2506
NC		 723/* Like md_number_to_chars but used for limms. The 4-byte limm value,
724 is encoded as 'middle-endian' for a little-endian target. FIXME!
725 this function is used for regular 4 byte instructions as well. */
726
727static void
6f4b1afc 728md_number_to_chars_midend (char *buf, valueT val, int n)
886a2506
NC		 729{
730 if (n == 4)
731 {
732 md_number_to_chars (buf, (val & 0xffff0000) >> 16, 2);
733 md_number_to_chars (buf + 2, (val & 0xffff), 2);
252b5132
RH		 734 }
735 else
886a2506
NC		 736 {
737 md_number_to_chars (buf, val, n);
738 }
252b5132
RH		 739}
740
24740d83
AB		 741/* Select an appropriate entry from CPU_TYPES based on ARG and initialise
742 the relevant static global variables. */
743
744static void
745arc_select_cpu (const char *arg)
746{
a9522a21 747 int cpu_flags = 0;
24740d83
AB		 748 int i;
749
750 for (i = 0; cpu_types[i].name; ++i)
751 {
752 if (!strcasecmp (cpu_types[i].name, arg))
753 {
754 arc_target = cpu_types[i].flags;
755 arc_target_name = cpu_types[i].name;
756 arc_features = cpu_types[i].features;
757 arc_mach_type = cpu_types[i].mach;
758 cpu_flags = cpu_types[i].eflags;
759 break;
760 }
761 }
762
763 if (!cpu_types[i].name)
764 as_fatal (_("unknown architecture: %s\n"), arg);
a9522a21
AB		 765 gas_assert (cpu_flags != 0);
766 arc_eflag = (arc_eflag & ~EF_ARC_MACH_MSK) | cpu_flags;
24740d83
AB		 767}
768
886a2506
NC		 769/* Here ends all the ARCompact extension instruction assembling
770 stuff. */
252b5132 771
886a2506
NC		 772static void
773arc_extra_reloc (int r_type)
ea1562b3 774{
886a2506
NC		 775 char *sym_name, c;
776 symbolS *sym, *lab = NULL;
777
778 if (*input_line_pointer == '@')
779 input_line_pointer++;
780 c = get_symbol_name (&sym_name);
781 sym = symbol_find_or_make (sym_name);
782 restore_line_pointer (c);
783 if (c == ',' && r_type == BFD_RELOC_ARC_TLS_GD_LD)
784 {
785 ++input_line_pointer;
786 char *lab_name;
787 c = get_symbol_name (&lab_name);
788 lab = symbol_find_or_make (lab_name);
789 restore_line_pointer (c);
790 }
841fdfcd
CZ		 791
792 /* These relocations exist as a mechanism for the compiler to tell the
793 linker how to patch the code if the tls model is optimised. However,
794 the relocation itself does not require any space within the assembler
795 fragment, and so we pass a size of 0.
796
797 The lines that generate these relocations look like this:
798
799 .tls_gd_ld @.tdata`bl __tls_get_addr@plt
800
801 The '.tls_gd_ld @.tdata' is processed first and generates the
802 additional relocation, while the 'bl __tls_get_addr@plt' is processed
803 second and generates the additional branch.
804
805 It is possible that the additional relocation generated by the
806 '.tls_gd_ld @.tdata' will be attached at the very end of one fragment,
807 while the 'bl __tls_get_addr@plt' will be generated as the first thing
808 in the next fragment. This will be fine; both relocations will still
809 appear to be at the same address in the generated object file.
810 However, this only works as the additional relocation is generated
811 with size of 0 bytes. */
886a2506
NC		 812 fixS *fixP
813 = fix_new (frag_now, /* Which frag? */
814 frag_now_fix (), /* Where in that frag? */
841fdfcd 815 0, /* size: 1, 2, or 4 usually. */
886a2506
NC		 816 sym, /* X_add_symbol. */
817 0, /* X_add_number. */
818 FALSE, /* TRUE if PC-relative relocation. */
819 r_type /* Relocation type. */);
820 fixP->fx_subsy = lab;
821}
252b5132 822
886a2506
NC		 823static symbolS *
824arc_lcomm_internal (int ignore ATTRIBUTE_UNUSED,
825 symbolS *symbolP, addressT size)
826{
827 addressT align = 0;
828 SKIP_WHITESPACE ();
252b5132 829
886a2506
NC		 830 if (*input_line_pointer == ',')
831 {
832 align = parse_align (1);
252b5132 833
886a2506
NC		 834 if (align == (addressT) -1)
835 return NULL;
836 }
837 else
838 {
839 if (size >= 8)
840 align = 3;
841 else if (size >= 4)
842 align = 2;
843 else if (size >= 2)
844 align = 1;
845 else
846 align = 0;
847 }
252b5132 848
886a2506
NC		 849 bss_alloc (symbolP, size, align);
850 S_CLEAR_EXTERNAL (symbolP);
ea1562b3 851
886a2506
NC		 852 return symbolP;
853}
ea1562b3 854
886a2506
NC		 855static void
856arc_lcomm (int ignore)
857{
858 symbolS *symbolP = s_comm_internal (ignore, arc_lcomm_internal);
ea1562b3 859
886a2506
NC		 860 if (symbolP)
861 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT;
862}
ea1562b3 863
886a2506 864/* Select the cpu we're assembling for. */
ea1562b3 865
886a2506
NC		 866static void
867arc_option (int ignore ATTRIBUTE_UNUSED)
252b5132 868{
886a2506
NC		 869 int mach = -1;
870 char c;
871 char *cpu;
252b5132 872
886a2506
NC		 873 c = get_symbol_name (&cpu);
874 mach = arc_get_mach (cpu);
252b5132 875
886a2506
NC		 876 if (mach == -1)
877 goto bad_cpu;
878
879 if (!mach_type_specified_p)
ea1562b3 880 {
24b368f8
CZ		 881 if ((!strcmp ("ARC600", cpu))
882 || (!strcmp ("ARC601", cpu))
883 || (!strcmp ("A6", cpu)))
884 {
885 md_parse_option (OPTION_MCPU, "arc600");
886 }
887 else if ((!strcmp ("ARC700", cpu))
888 || (!strcmp ("A7", cpu)))
889 {
890 md_parse_option (OPTION_MCPU, "arc700");
891 }
892 else if (!strcmp ("EM", cpu))
893 {
894 md_parse_option (OPTION_MCPU, "arcem");
895 }
896 else if (!strcmp ("HS", cpu))
897 {
898 md_parse_option (OPTION_MCPU, "archs");
899 }
900 else
e6ba1cba 901 as_fatal (_("could not find the architecture"));
24b368f8 902
886a2506 903 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, mach))
e6ba1cba 904 as_fatal (_("could not set architecture and machine"));
ea1562b3
NC		 905 }
906 else
886a2506 907 if (arc_mach_type != mach)
e6ba1cba 908 as_warn (_("Command-line value overrides \".cpu\" directive"));
886a2506 909
24b368f8 910 restore_line_pointer (c);
886a2506 911 demand_empty_rest_of_line ();
886a2506
NC		 912 return;
913
914 bad_cpu:
24b368f8 915 restore_line_pointer (c);
e6ba1cba 916 as_bad (_("invalid identifier for \".cpu\""));
886a2506 917 ignore_rest_of_line ();
ea1562b3 918}
252b5132 919
886a2506
NC		 920/* Smartly print an expression. */
921
ea1562b3 922static void
886a2506 923debug_exp (expressionS *t)
ea1562b3 924{
886a2506
NC		 925 const char *name ATTRIBUTE_UNUSED;
926 const char *namemd ATTRIBUTE_UNUSED;
252b5132 927
886a2506 928 pr_debug ("debug_exp: ");
252b5132 929
886a2506 930 switch (t->X_op)
252b5132 931 {
886a2506
NC		 932 default: name = "unknown"; break;
933 case O_illegal: name = "O_illegal"; break;
934 case O_absent: name = "O_absent"; break;
935 case O_constant: name = "O_constant"; break;
936 case O_symbol: name = "O_symbol"; break;
937 case O_symbol_rva: name = "O_symbol_rva"; break;
938 case O_register: name = "O_register"; break;
939 case O_big: name = "O_big"; break;
940 case O_uminus: name = "O_uminus"; break;
941 case O_bit_not: name = "O_bit_not"; break;
942 case O_logical_not: name = "O_logical_not"; break;
943 case O_multiply: name = "O_multiply"; break;
944 case O_divide: name = "O_divide"; break;
945 case O_modulus: name = "O_modulus"; break;
946 case O_left_shift: name = "O_left_shift"; break;
947 case O_right_shift: name = "O_right_shift"; break;
948 case O_bit_inclusive_or: name = "O_bit_inclusive_or"; break;
949 case O_bit_or_not: name = "O_bit_or_not"; break;
950 case O_bit_exclusive_or: name = "O_bit_exclusive_or"; break;
951 case O_bit_and: name = "O_bit_and"; break;
952 case O_add: name = "O_add"; break;
953 case O_subtract: name = "O_subtract"; break;
954 case O_eq: name = "O_eq"; break;
955 case O_ne: name = "O_ne"; break;
956 case O_lt: name = "O_lt"; break;
957 case O_le: name = "O_le"; break;
958 case O_ge: name = "O_ge"; break;
959 case O_gt: name = "O_gt"; break;
960 case O_logical_and: name = "O_logical_and"; break;
961 case O_logical_or: name = "O_logical_or"; break;
962 case O_index: name = "O_index"; break;
963 case O_bracket: name = "O_bracket"; break;
ea1562b3 964 }
252b5132 965
886a2506 966 switch (t->X_md)
ea1562b3 967 {
886a2506
NC		 968 default: namemd = "unknown"; break;
969 case O_gotoff: namemd = "O_gotoff"; break;
970 case O_gotpc: namemd = "O_gotpc"; break;
971 case O_plt: namemd = "O_plt"; break;
972 case O_sda: namemd = "O_sda"; break;
973 case O_pcl: namemd = "O_pcl"; break;
974 case O_tlsgd: namemd = "O_tlsgd"; break;
975 case O_tlsie: namemd = "O_tlsie"; break;
976 case O_tpoff9: namemd = "O_tpoff9"; break;
977 case O_tpoff: namemd = "O_tpoff"; break;
978 case O_dtpoff9: namemd = "O_dtpoff9"; break;
979 case O_dtpoff: namemd = "O_dtpoff"; break;
ea1562b3 980 }
252b5132 981
886a2506
NC		 982 pr_debug ("%s (%s, %s, %d, %s)", name,
983 (t->X_add_symbol) ? S_GET_NAME (t->X_add_symbol) : "--",
984 (t->X_op_symbol) ? S_GET_NAME (t->X_op_symbol) : "--",
985 (int) t->X_add_number,
986 (t->X_md) ? namemd : "--");
987 pr_debug ("\n");
988 fflush (stderr);
989}
252b5132 990
886a2506
NC		 991/* Parse the arguments to an opcode. */
992
993static int
994tokenize_arguments (char *str,
995 expressionS *tok,
996 int ntok)
997{
998 char *old_input_line_pointer;
999 bfd_boolean saw_comma = FALSE;
1000 bfd_boolean saw_arg = FALSE;
1001 int brk_lvl = 0;
1002 int num_args = 0;
886a2506
NC		 1003 int i;
1004 size_t len;
1005 const struct arc_reloc_op_tag *r;
1006 expressionS tmpE;
6f4b1afc 1007 char *reloc_name, c;
886a2506
NC		 1008
1009 memset (tok, 0, sizeof (*tok) * ntok);
1010
1011 /* Save and restore input_line_pointer around this function. */
1012 old_input_line_pointer = input_line_pointer;
1013 input_line_pointer = str;
ea1562b3 1014
886a2506 1015 while (*input_line_pointer)
ea1562b3
NC		 1016 {
1017 SKIP_WHITESPACE ();
886a2506 1018 switch (*input_line_pointer)
252b5132 1019 {
886a2506
NC		 1020 case '\0':
1021 goto fini;
1022
1023 case ',':
1024 input_line_pointer++;
1025 if (saw_comma || !saw_arg)
1026 goto err;
1027 saw_comma = TRUE;
1028 break;
252b5132 1029
886a2506
NC		 1030 case '}':
1031 case ']':
1032 ++input_line_pointer;
1033 --brk_lvl;
1034 if (!saw_arg)
1035 goto err;
1036 tok->X_op = O_bracket;
1037 ++tok;
1038 ++num_args;
1039 break;
ea1562b3 1040
886a2506
NC		 1041 case '{':
1042 case '[':
1043 input_line_pointer++;
1044 if (brk_lvl)
1045 goto err;
1046 ++brk_lvl;
1047 tok->X_op = O_bracket;
1048 ++tok;
1049 ++num_args;
1050 break;
1051
1052 case '@':
1053 /* We have labels, function names and relocations, all
1054 starting with @ symbol. Sort them out. */
1055 if (saw_arg && !saw_comma)
1056 goto err;
1057
1058 /* Parse @label. */
1059 tok->X_op = O_symbol;
1060 tok->X_md = O_absent;
1061 expression (tok);
1062 if (*input_line_pointer != '@')
1063 goto normalsymbol; /* This is not a relocation. */
1064
6f4b1afc
CM		 1065 relocationsym:
1066
886a2506
NC		 1067 /* A relocation opernad has the following form
1068 @identifier@relocation_type. The identifier is already
1069 in tok! */
1070 if (tok->X_op != O_symbol)
ea1562b3 1071 {
886a2506
NC		 1072 as_bad (_("No valid label relocation operand"));
1073 goto err;
252b5132 1074 }
886a2506
NC		 1075
1076 /* Parse @relocation_type. */
6f4b1afc
CM		 1077 input_line_pointer++;
1078 c = get_symbol_name (&reloc_name);
1079 len = input_line_pointer - reloc_name;
1080 if (len == 0)
252b5132 1081 {
886a2506
NC		 1082 as_bad (_("No relocation operand"));
1083 goto err;
252b5132 1084 }
252b5132 1085
886a2506
NC		 1086 /* Go through known relocation and try to find a match. */
1087 r = &arc_reloc_op[0];
1088 for (i = arc_num_reloc_op - 1; i >= 0; i--, r++)
6f4b1afc
CM		 1089 if (len == r->length
1090 && memcmp (reloc_name, r->name, len) == 0)
886a2506 1091 break;
886a2506 1092 if (i < 0)
252b5132 1093 {
6f4b1afc 1094 as_bad (_("Unknown relocation operand: @%s"), reloc_name);
886a2506
NC		 1095 goto err;
1096 }
1097
6f4b1afc
CM		 1098 *input_line_pointer = c;
1099 SKIP_WHITESPACE_AFTER_NAME ();
886a2506
NC		 1100 /* Extra check for TLS: base. */
1101 if (*input_line_pointer == '@')
1102 {
1103 symbolS *base;
1104 if (tok->X_op_symbol != NULL
1105 || tok->X_op != O_symbol)
252b5132 1106 {
6f4b1afc
CM		 1107 as_bad (_("Unable to parse TLS base: %s"),
1108 input_line_pointer);
886a2506 1109 goto err;
252b5132 1110 }
886a2506
NC		 1111 input_line_pointer++;
1112 char *sym_name;
6f4b1afc 1113 c = get_symbol_name (&sym_name);
886a2506
NC		 1114 base = symbol_find_or_make (sym_name);
1115 tok->X_op = O_subtract;
1116 tok->X_op_symbol = base;
1117 restore_line_pointer (c);
6f4b1afc
CM		 1118 tmpE.X_add_number = 0;
1119 }
1120 else if ((*input_line_pointer != '+')
1121 && (*input_line_pointer != '-'))
1122 {
1123 tmpE.X_add_number = 0;
ea1562b3 1124 }
6f4b1afc
CM		 1125 else
1126 {
1127 /* Parse the constant of a complex relocation expression
1128 like @identifier@reloc +/- const. */
1129 if (! r->complex_expr)
1130 {
1131 as_bad (_("@%s is not a complex relocation."), r->name);
1132 goto err;
1133 }
1134 expression (&tmpE);
1135 if (tmpE.X_op != O_constant)
1136 {
1137 as_bad (_("Bad expression: @%s + %s."),
1138 r->name, input_line_pointer);
1139 goto err;
1140 }
1141 }
1142
1143 tok->X_md = r->op;
1144 tok->X_add_number = tmpE.X_add_number;
1e07b820 1145
886a2506 1146 debug_exp (tok);
ea1562b3 1147
886a2506
NC		 1148 saw_comma = FALSE;
1149 saw_arg = TRUE;
1150 tok++;
1151 num_args++;
1152 break;
252b5132 1153
886a2506
NC		 1154 case '%':
1155 /* Can be a register. */
1156 ++input_line_pointer;
1157 /* Fall through. */
1158 default:
252b5132 1159
886a2506
NC		 1160 if (saw_arg && !saw_comma)
1161 goto err;
252b5132 1162
886a2506 1163 tok->X_op = O_absent;
6f4b1afc 1164 tok->X_md = O_absent;
886a2506 1165 expression (tok);
252b5132 1166
6f4b1afc
CM		 1167 /* Legacy: There are cases when we have
1168 identifier@relocation_type, if it is the case parse the
1169 relocation type as well. */
1170 if (*input_line_pointer == '@')
1171 goto relocationsym;
1172
886a2506
NC		 1173 normalsymbol:
1174 debug_exp (tok);
252b5132 1175
886a2506
NC		 1176 if (tok->X_op == O_illegal || tok->X_op == O_absent)
1177 goto err;
252b5132 1178
886a2506
NC		 1179 saw_comma = FALSE;
1180 saw_arg = TRUE;
1181 tok++;
1182 num_args++;
1183 break;
1184 }
ea1562b3 1185 }
252b5132 1186
886a2506
NC		 1187 fini:
1188 if (saw_comma || brk_lvl)
1189 goto err;
1190 input_line_pointer = old_input_line_pointer;
252b5132 1191
886a2506 1192 return num_args;
252b5132 1193
886a2506
NC		 1194 err:
1195 if (brk_lvl)
1196 as_bad (_("Brackets in operand field incorrect"));
1197 else if (saw_comma)
1198 as_bad (_("extra comma"));
1199 else if (!saw_arg)
1200 as_bad (_("missing argument"));
1201 else
1202 as_bad (_("missing comma or colon"));
1203 input_line_pointer = old_input_line_pointer;
1204 return -1;
252b5132 1205}
ea1562b3 1206
886a2506
NC		 1207/* Parse the flags to a structure. */
1208
1209static int
1210tokenize_flags (const char *str,
1211 struct arc_flags flags[],
1212 int nflg)
252b5132 1213{
886a2506
NC		 1214 char *old_input_line_pointer;
1215 bfd_boolean saw_flg = FALSE;
1216 bfd_boolean saw_dot = FALSE;
1217 int num_flags = 0;
1218 size_t flgnamelen;
252b5132 1219
886a2506 1220 memset (flags, 0, sizeof (*flags) * nflg);
0d2bcfaf 1221
886a2506
NC		 1222 /* Save and restore input_line_pointer around this function. */
1223 old_input_line_pointer = input_line_pointer;
1224 input_line_pointer = (char *) str;
0d2bcfaf 1225
886a2506
NC		 1226 while (*input_line_pointer)
1227 {
1228 switch (*input_line_pointer)
1229 {
1230 case ' ':
1231 case '\0':
1232 goto fini;
1233
1234 case '.':
1235 input_line_pointer++;
1236 if (saw_dot)
1237 goto err;
1238 saw_dot = TRUE;
1239 saw_flg = FALSE;
1240 break;
ea1562b3 1241
886a2506
NC		 1242 default:
1243 if (saw_flg && !saw_dot)
1244 goto err;
0d2bcfaf 1245
886a2506
NC		 1246 if (num_flags >= nflg)
1247 goto err;
0d2bcfaf 1248
692166c2
AB		 1249 flgnamelen = strspn (input_line_pointer,
1250 "abcdefghijklmnopqrstuvwxyz0123456789");
83cda17b 1251 if (flgnamelen > MAX_FLAG_NAME_LENGTH)
886a2506 1252 goto err;
0d2bcfaf 1253
886a2506 1254 memcpy (flags->name, input_line_pointer, flgnamelen);
0d2bcfaf 1255
886a2506
NC		 1256 input_line_pointer += flgnamelen;
1257 flags++;
1258 saw_dot = FALSE;
1259 saw_flg = TRUE;
1260 num_flags++;
1261 break;
1e07b820 1262 }
0d2bcfaf
NC		 1263 }
1264
886a2506
NC		 1265 fini:
1266 input_line_pointer = old_input_line_pointer;
1267 return num_flags;
0d2bcfaf 1268
886a2506
NC		 1269 err:
1270 if (saw_dot)
1271 as_bad (_("extra dot"));
1272 else if (!saw_flg)
1273 as_bad (_("unrecognized flag"));
1274 else
1275 as_bad (_("failed to parse flags"));
1276 input_line_pointer = old_input_line_pointer;
1277 return -1;
1278}
0d2bcfaf 1279
4670103e 1280/* Apply the fixups in order. */
0d2bcfaf 1281
4670103e
CZ		 1282static void
1283apply_fixups (struct arc_insn *insn, fragS *fragP, int fix)
886a2506 1284{
4670103e 1285 int i;
0d2bcfaf 1286
4670103e 1287 for (i = 0; i < insn->nfixups; i++)
252b5132 1288 {
4670103e
CZ		 1289 struct arc_fixup *fixup = &insn->fixups[i];
1290 int size, pcrel, offset = 0;
0d2bcfaf 1291
4670103e
CZ		 1292 /* FIXME! the reloc size is wrong in the BFD file.
1293 When it is fixed please delete me. */
1294 size = (insn->short_insn && !fixup->islong) ? 2 : 4;
0d2bcfaf 1295
4670103e
CZ		 1296 if (fixup->islong)
1297 offset = (insn->short_insn) ? 2 : 4;
252b5132 1298
4670103e
CZ		 1299 /* Some fixups are only used internally, thus no howto. */
1300 if ((int) fixup->reloc == 0)
1301 as_fatal (_("Unhandled reloc type"));
886a2506 1302
4670103e
CZ		 1303 if ((int) fixup->reloc < 0)
1304 {
1305 /* FIXME! the reloc size is wrong in the BFD file.
1306 When it is fixed please enable me.
1307 size = (insn->short_insn && !fixup->islong) ? 2 : 4; */
1308 pcrel = fixup->pcrel;
1309 }
1310 else
1311 {
1312 reloc_howto_type *reloc_howto =
1313 bfd_reloc_type_lookup (stdoutput,
1314 (bfd_reloc_code_real_type) fixup->reloc);
1315 gas_assert (reloc_howto);
0d2bcfaf 1316
4670103e
CZ		 1317 /* FIXME! the reloc size is wrong in the BFD file.
1318 When it is fixed please enable me.
1319 size = bfd_get_reloc_size (reloc_howto); */
1320 pcrel = reloc_howto->pc_relative;
1321 }
0d2bcfaf 1322
4670103e
CZ		 1323 pr_debug ("%s:%d: apply_fixups: new %s fixup (PCrel:%s) of size %d @ \
1324offset %d + %d\n",
1325 fragP->fr_file, fragP->fr_line,
1326 (fixup->reloc < 0) ? "Internal" :
1327 bfd_get_reloc_code_name (fixup->reloc),
1328 pcrel ? "Y" : "N",
1329 size, fix, offset);
1330 fix_new_exp (fragP, fix + offset,
1331 size, &fixup->exp, pcrel, fixup->reloc);
0d2bcfaf 1332
4670103e
CZ		 1333 /* Check for ZOLs, and update symbol info if any. */
1334 if (LP_INSN (insn->insn))
886a2506 1335 {
4670103e
CZ		 1336 gas_assert (fixup->exp.X_add_symbol);
1337 ARC_SET_FLAG (fixup->exp.X_add_symbol, ARC_FLAG_ZOL);
886a2506
NC		 1338 }
1339 }
252b5132
RH		 1340}
1341
4670103e 1342/* Actually output an instruction with its fixup. */
886a2506 1343
4670103e
CZ		 1344static void
1345emit_insn0 (struct arc_insn *insn, char *where, bfd_boolean relax)
252b5132 1346{
4670103e 1347 char *f = where;
252b5132 1348
4670103e
CZ		 1349 pr_debug ("Emit insn : 0x%x\n", insn->insn);
1350 pr_debug ("\tShort : 0x%d\n", insn->short_insn);
1351 pr_debug ("\tLong imm: 0x%lx\n", insn->limm);
0d2bcfaf 1352
4670103e
CZ		 1353 /* Write out the instruction. */
1354 if (insn->short_insn)
0d2bcfaf 1355 {
4670103e
CZ		 1356 if (insn->has_limm)
1357 {
1358 if (!relax)
1359 f = frag_more (6);
1360 md_number_to_chars (f, insn->insn, 2);
1361 md_number_to_chars_midend (f + 2, insn->limm, 4);
1362 dwarf2_emit_insn (6);
1363 }
1364 else
1365 {
1366 if (!relax)
1367 f = frag_more (2);
1368 md_number_to_chars (f, insn->insn, 2);
1369 dwarf2_emit_insn (2);
1370 }
1371 }
1372 else
1373 {
1374 if (insn->has_limm)
1375 {
1376 if (!relax)
1377 f = frag_more (8);
1378 md_number_to_chars_midend (f, insn->insn, 4);
1379 md_number_to_chars_midend (f + 4, insn->limm, 4);
1380 dwarf2_emit_insn (8);
1381 }
1382 else
1383 {
1384 if (!relax)
1385 f = frag_more (4);
1386 md_number_to_chars_midend (f, insn->insn, 4);
1387 dwarf2_emit_insn (4);
1388 }
252b5132 1389 }
252b5132 1390
4670103e
CZ		 1391 if (!relax)
1392 apply_fixups (insn, frag_now, (f - frag_now->fr_literal));
1393}
252b5132 1394
4670103e
CZ		 1395static void
1396emit_insn1 (struct arc_insn *insn)
1397{
1398 /* How frag_var's args are currently configured:
1399 - rs_machine_dependent, to dictate it's a relaxation frag.
1400 - FRAG_MAX_GROWTH, maximum size of instruction
1401 - 0, variable size that might grow...unused by generic relaxation.
1402 - frag_now->fr_subtype, fr_subtype starting value, set previously.
1403 - s, opand expression.
1404 - 0, offset but it's unused.
1405 - 0, opcode but it's unused. */
1406 symbolS *s = make_expr_symbol (&insn->fixups[0].exp);
1407 frag_now->tc_frag_data.pcrel = insn->fixups[0].pcrel;
1408
1409 if (frag_room () < FRAG_MAX_GROWTH)
1410 {
1411 /* Handle differently when frag literal memory is exhausted.
1412 This is used because when there's not enough memory left in
1413 the current frag, a new frag is created and the information
1414 we put into frag_now->tc_frag_data is disregarded. */
252b5132 1415
4670103e
CZ		 1416 struct arc_relax_type relax_info_copy;
1417 relax_substateT subtype = frag_now->fr_subtype;
252b5132 1418
4670103e
CZ		 1419 memcpy (&relax_info_copy, &frag_now->tc_frag_data,
1420 sizeof (struct arc_relax_type));
0d2bcfaf 1421
4670103e
CZ		 1422 frag_wane (frag_now);
1423 frag_grow (FRAG_MAX_GROWTH);
0d2bcfaf 1424
4670103e
CZ		 1425 memcpy (&frag_now->tc_frag_data, &relax_info_copy,
1426 sizeof (struct arc_relax_type));
252b5132 1427
4670103e
CZ		 1428 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1429 subtype, s, 0, 0);
1430 }
1431 else
1432 frag_var (rs_machine_dependent, FRAG_MAX_GROWTH, 0,
1433 frag_now->fr_subtype, s, 0, 0);
1434}
252b5132 1435
4670103e
CZ		 1436static void
1437emit_insn (struct arc_insn *insn)
252b5132 1438{
4670103e
CZ		 1439 if (insn->relax)
1440 emit_insn1 (insn);
252b5132 1441 else
4670103e 1442 emit_insn0 (insn, NULL, FALSE);
252b5132
RH		 1443}
1444
4670103e 1445/* Check whether a symbol involves a register. */
252b5132 1446
4670103e
CZ		 1447static bfd_boolean
1448contains_register (symbolS *sym)
252b5132 1449{
4670103e
CZ		 1450 if (sym)
1451 {
1452 expressionS *ex = symbol_get_value_expression (sym);
252b5132 1453
4670103e
CZ		 1454 return ((O_register == ex->X_op)
1455 && !contains_register (ex->X_add_symbol)
1456 && !contains_register (ex->X_op_symbol));
1457 }
1458
1459 return FALSE;
252b5132
RH		 1460}
1461
4670103e 1462/* Returns the register number within a symbol. */
252b5132 1463
4670103e
CZ		 1464static int
1465get_register (symbolS *sym)
252b5132 1466{
4670103e
CZ		 1467 if (!contains_register (sym))
1468 return -1;
0d2bcfaf 1469
4670103e
CZ		 1470 expressionS *ex = symbol_get_value_expression (sym);
1471 return regno (ex->X_add_number);
1472}
252b5132 1473
4670103e
CZ		 1474/* Return true if a RELOC is generic. A generic reloc is PC-rel of a
1475 simple ME relocation (e.g. RELOC_ARC_32_ME, BFD_RELOC_ARC_PC32. */
f17c130b 1476
4670103e
CZ		 1477static bfd_boolean
1478generic_reloc_p (extended_bfd_reloc_code_real_type reloc)
1479{
1480 if (!reloc)
1481 return FALSE;
886a2506 1482
4670103e
CZ		 1483 switch (reloc)
1484 {
1485 case BFD_RELOC_ARC_SDA_LDST:
1486 case BFD_RELOC_ARC_SDA_LDST1:
1487 case BFD_RELOC_ARC_SDA_LDST2:
1488 case BFD_RELOC_ARC_SDA16_LD:
1489 case BFD_RELOC_ARC_SDA16_LD1:
1490 case BFD_RELOC_ARC_SDA16_LD2:
1491 case BFD_RELOC_ARC_SDA16_ST2:
1492 case BFD_RELOC_ARC_SDA32_ME:
1493 return FALSE;
1494 default:
1495 return TRUE;
f17c130b 1496 }
252b5132
RH		 1497}
1498
4670103e 1499/* Allocates a tok entry. */
252b5132 1500
4670103e
CZ		 1501static int
1502allocate_tok (expressionS *tok, int ntok, int cidx)
252b5132 1503{
4670103e
CZ		 1504 if (ntok > MAX_INSN_ARGS - 2)
1505 return 0; /* No space left. */
252b5132 1506
4670103e
CZ		 1507 if (cidx > ntok)
1508 return 0; /* Incorect args. */
252b5132 1509
4670103e 1510 memcpy (&tok[ntok+1], &tok[ntok], sizeof (*tok));
252b5132 1511
4670103e
CZ		 1512 if (cidx == ntok)
1513 return 1; /* Success. */
1514 return allocate_tok (tok, ntok - 1, cidx);
1515}
886a2506 1516
8ddf6b2a
CZ		 1517/* Check if an particular ARC feature is enabled. */
1518
1519static bfd_boolean
1520check_cpu_feature (insn_subclass_t sc)
1521{
1522 if (!(arc_features & ARC_CD)
1523 && is_code_density_p (sc))
1524 return FALSE;
1525
1526 if (!(arc_features & ARC_SPFP)
1527 && is_spfp_p (sc))
1528 return FALSE;
1529
1530 if (!(arc_features & ARC_DPFP)
1531 && is_dpfp_p (sc))
1532 return FALSE;
1533
1534 if (!(arc_features & ARC_FPUDA)
1535 && is_fpuda_p (sc))
1536 return FALSE;
1537
1538 return TRUE;
1539}
1540
4670103e
CZ		 1541/* Search forward through all variants of an opcode looking for a
1542 syntax match. */
886a2506 1543
4670103e 1544static const struct arc_opcode *
b9b47ab7 1545find_opcode_match (const struct arc_opcode_hash_entry *entry,
4670103e
CZ		 1546 expressionS *tok,
1547 int *pntok,
1548 struct arc_flags *first_pflag,
1549 int nflgs,
1550 int *pcpumatch)
1551{
1328504b
AB		 1552 const struct arc_opcode *opcode;
1553 struct arc_opcode_hash_entry_iterator iter;
4670103e
CZ		 1554 int ntok = *pntok;
1555 int got_cpu_match = 0;
1556 expressionS bktok[MAX_INSN_ARGS];
1557 int bkntok;
1558 expressionS emptyE;
886a2506 1559
1328504b 1560 arc_opcode_hash_entry_iterator_init (&iter);
4670103e
CZ		 1561 memset (&emptyE, 0, sizeof (emptyE));
1562 memcpy (bktok, tok, MAX_INSN_ARGS * sizeof (*tok));
1563 bkntok = ntok;
a161fe53 1564
1328504b
AB		 1565 for (opcode = arc_opcode_hash_entry_iterator_next (entry, &iter);
1566 opcode != NULL;
1567 opcode = arc_opcode_hash_entry_iterator_next (entry, &iter))
252b5132 1568 {
4670103e
CZ		 1569 const unsigned char *opidx;
1570 const unsigned char *flgidx;
1ae8ab47 1571 int tokidx = 0, lnflg, i;
4670103e 1572 const expressionS *t = &emptyE;
252b5132 1573
4670103e
CZ		 1574 pr_debug ("%s:%d: find_opcode_match: trying opcode 0x%08X ",
1575 frag_now->fr_file, frag_now->fr_line, opcode->opcode);
886a2506 1576
4670103e
CZ		 1577 /* Don't match opcodes that don't exist on this
1578 architecture. */
1579 if (!(opcode->cpu & arc_target))
1580 goto match_failed;
886a2506 1581
8ddf6b2a 1582 if (!check_cpu_feature (opcode->subclass))
4670103e 1583 goto match_failed;
886a2506 1584
4670103e
CZ		 1585 got_cpu_match = 1;
1586 pr_debug ("cpu ");
886a2506 1587
4670103e
CZ		 1588 /* Check the operands. */
1589 for (opidx = opcode->operands; *opidx; ++opidx)
252b5132 1590 {
4670103e 1591 const struct arc_operand *operand = &arc_operands[*opidx];
252b5132 1592
4670103e
CZ		 1593 /* Only take input from real operands. */
1594 if ((operand->flags & ARC_OPERAND_FAKE)
1595 && !(operand->flags & ARC_OPERAND_BRAKET))
1596 continue;
252b5132 1597
4670103e
CZ		 1598 /* When we expect input, make sure we have it. */
1599 if (tokidx >= ntok)
1600 goto match_failed;
6f4b1afc 1601
4670103e
CZ		 1602 /* Match operand type with expression type. */
1603 switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK)
1604 {
1605 case ARC_OPERAND_IR:
1606 /* Check to be a register. */
1607 if ((tok[tokidx].X_op != O_register
1608 || !is_ir_num (tok[tokidx].X_add_number))
1609 && !(operand->flags & ARC_OPERAND_IGNORE))
1610 goto match_failed;
1611
1612 /* If expect duplicate, make sure it is duplicate. */
1613 if (operand->flags & ARC_OPERAND_DUPLICATE)
1614 {
1615 /* Check for duplicate. */
1616 if (t->X_op != O_register
1617 || !is_ir_num (t->X_add_number)
1618 || (regno (t->X_add_number) !=
1619 regno (tok[tokidx].X_add_number)))
1620 goto match_failed;
1621 }
1622
1623 /* Special handling? */
1624 if (operand->insert)
1625 {
1626 const char *errmsg = NULL;
1627 (*operand->insert)(0,
1628 regno (tok[tokidx].X_add_number),
1629 &errmsg);
1630 if (errmsg)
1631 {
1632 if (operand->flags & ARC_OPERAND_IGNORE)
1633 {
1634 /* Missing argument, create one. */
1635 if (!allocate_tok (tok, ntok - 1, tokidx))
1636 goto match_failed;
1637
1638 tok[tokidx].X_op = O_absent;
1639 ++ntok;
1640 }
1641 else
1642 goto match_failed;
1643 }
1644 }
1645
1646 t = &tok[tokidx];
1647 break;
1648
1649 case ARC_OPERAND_BRAKET:
1650 /* Check if bracket is also in opcode table as
1651 operand. */
1652 if (tok[tokidx].X_op != O_bracket)
1653 goto match_failed;
1654 break;
1655
1656 case ARC_OPERAND_LIMM:
1657 case ARC_OPERAND_SIGNED:
1658 case ARC_OPERAND_UNSIGNED:
1659 switch (tok[tokidx].X_op)
1660 {
1661 case O_illegal:
1662 case O_absent:
1663 case O_register:
1664 goto match_failed;
1665
1666 case O_bracket:
1667 /* Got an (too) early bracket, check if it is an
1668 ignored operand. N.B. This procedure works only
1669 when bracket is the last operand! */
1670 if (!(operand->flags & ARC_OPERAND_IGNORE))
1671 goto match_failed;
1672 /* Insert the missing operand. */
1673 if (!allocate_tok (tok, ntok - 1, tokidx))
1674 goto match_failed;
1675
1676 tok[tokidx].X_op = O_absent;
1677 ++ntok;
1678 break;
1679
22b92fc4
AB		 1680 case O_symbol:
1681 {
1682 const char *p;
22b92fc4 1683 const struct arc_aux_reg *auxr;
22b92fc4
AB		 1684
1685 if (opcode->class != AUXREG)
1686 goto de_fault;
1687 p = S_GET_NAME (tok[tokidx].X_add_symbol);
f36e33da
CZ		 1688
1689 auxr = hash_find (arc_aux_hash, p);
1690 if (auxr)
1691 {
1692 /* We modify the token array here, safe in the
1693 knowledge, that if this was the wrong
1694 choice then the original contents will be
1695 restored from BKTOK. */
1696 tok[tokidx].X_op = O_constant;
1697 tok[tokidx].X_add_number = auxr->address;
1698 ARC_SET_FLAG (tok[tokidx].X_add_symbol, ARC_FLAG_AUX);
1699 }
22b92fc4
AB		 1700
1701 if (tok[tokidx].X_op != O_constant)
1702 goto de_fault;
1703 }
1704 /* Fall-through */
4670103e
CZ		 1705 case O_constant:
1706 /* Check the range. */
1707 if (operand->bits != 32
1708 && !(operand->flags & ARC_OPERAND_NCHK))
1709 {
1710 offsetT min, max, val;
1711 val = tok[tokidx].X_add_number;
1712
1713 if (operand->flags & ARC_OPERAND_SIGNED)
1714 {
1715 max = (1 << (operand->bits - 1)) - 1;
1716 min = -(1 << (operand->bits - 1));
1717 }
1718 else
1719 {
1720 max = (1 << operand->bits) - 1;
1721 min = 0;
1722 }
1723
1724 if (val < min || val > max)
1725 goto match_failed;
1726
1727 /* Check alignmets. */
1728 if ((operand->flags & ARC_OPERAND_ALIGNED32)
1729 && (val & 0x03))
1730 goto match_failed;
1731
1732 if ((operand->flags & ARC_OPERAND_ALIGNED16)
1733 && (val & 0x01))
1734 goto match_failed;
1735 }
1736 else if (operand->flags & ARC_OPERAND_NCHK)
1737 {
1738 if (operand->insert)
1739 {
1740 const char *errmsg = NULL;
1741 (*operand->insert)(0,
1742 tok[tokidx].X_add_number,
1743 &errmsg);
1744 if (errmsg)
1745 goto match_failed;
1746 }
1747 else
1748 goto match_failed;
1749 }
1750 break;
1751
1752 case O_subtract:
1753 /* Check if it is register range. */
1754 if ((tok[tokidx].X_add_number == 0)
1755 && contains_register (tok[tokidx].X_add_symbol)
1756 && contains_register (tok[tokidx].X_op_symbol))
1757 {
1758 int regs;
1759
1760 regs = get_register (tok[tokidx].X_add_symbol);
1761 regs <<= 16;
1762 regs |= get_register (tok[tokidx].X_op_symbol);
1763 if (operand->insert)
1764 {
1765 const char *errmsg = NULL;
1766 (*operand->insert)(0,
1767 regs,
1768 &errmsg);
1769 if (errmsg)
1770 goto match_failed;
1771 }
1772 else
1773 goto match_failed;
1774 break;
1775 }
1776 default:
22b92fc4 1777 de_fault:
4670103e
CZ		 1778 if (operand->default_reloc == 0)
1779 goto match_failed; /* The operand needs relocation. */
1780
1781 /* Relocs requiring long immediate. FIXME! make it
1782 generic and move it to a function. */
1783 switch (tok[tokidx].X_md)
1784 {
1785 case O_gotoff:
1786 case O_gotpc:
1787 case O_pcl:
1788 case O_tpoff:
1789 case O_dtpoff:
1790 case O_tlsgd:
1791 case O_tlsie:
1792 if (!(operand->flags & ARC_OPERAND_LIMM))
1793 goto match_failed;
1794 case O_absent:
1795 if (!generic_reloc_p (operand->default_reloc))
1796 goto match_failed;
1797 default:
1798 break;
1799 }
1800 break;
1801 }
1802 /* If expect duplicate, make sure it is duplicate. */
1803 if (operand->flags & ARC_OPERAND_DUPLICATE)
1804 {
1805 if (t->X_op == O_illegal
1806 || t->X_op == O_absent
1807 || t->X_op == O_register
1808 || (t->X_add_number != tok[tokidx].X_add_number))
1809 goto match_failed;
1810 }
1811 t = &tok[tokidx];
1812 break;
1813
1814 default:
1815 /* Everything else should have been fake. */
1816 abort ();
1817 }
1818
1819 ++tokidx;
1820 }
1821 pr_debug ("opr ");
1822
1ae8ab47
AB		 1823 /* Setup ready for flag parsing. */
1824 lnflg = nflgs;
1825 for (i = 0; i < nflgs; i++)
f36e33da 1826 first_pflag[i].flgp = NULL;
4670103e 1827
1ae8ab47
AB		 1828 /* Check the flags. Iterate over the valid flag classes. */
1829 for (flgidx = opcode->flags; *flgidx; ++flgidx)
4670103e
CZ		 1830 {
1831 /* Get a valid flag class. */
1832 const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
1833 const unsigned *flgopridx;
1ae8ab47 1834 int cl_matches = 0;
f36e33da
CZ		 1835 struct arc_flags *pflag = NULL;
1836
1837 /* Check for extension conditional codes. */
1838 if (ext_condcode.arc_ext_condcode
1839 && cl_flags->class & F_CLASS_EXTEND)
1840 {
1841 struct arc_flag_operand *pf = ext_condcode.arc_ext_condcode;
1842 while (pf->name)
1843 {
1844 pflag = first_pflag;
1845 for (i = 0; i < nflgs; i++, pflag++)
1846 {
1847 if (!strcmp (pf->name, pflag->name))
1848 {
1849 if (pflag->flgp != NULL)
1850 goto match_failed;
1851 /* Found it. */
1852 cl_matches++;
1853 pflag->flgp = pf;
1854 lnflg--;
1855 break;
1856 }
1857 }
1858 pf++;
1859 }
1860 }
4670103e
CZ		 1861
1862 for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
1863 {
1864 const struct arc_flag_operand *flg_operand;
4670103e 1865
f36e33da 1866 pflag = first_pflag;
4670103e
CZ		 1867 flg_operand = &arc_flag_operands[*flgopridx];
1868 for (i = 0; i < nflgs; i++, pflag++)
1869 {
1870 /* Match against the parsed flags. */
1871 if (!strcmp (flg_operand->name, pflag->name))
1872 {
f36e33da 1873 if (pflag->flgp != NULL)
1ae8ab47
AB		 1874 goto match_failed;
1875 cl_matches++;
f36e33da 1876 pflag->flgp = (struct arc_flag_operand *) flg_operand;
4670103e
CZ		 1877 lnflg--;
1878 break; /* goto next flag class and parsed flag. */
1879 }
1880 }
1881 }
1ae8ab47 1882
f36e33da 1883 if ((cl_flags->class & F_CLASS_REQUIRED) && cl_matches == 0)
1ae8ab47 1884 goto match_failed;
f36e33da 1885 if ((cl_flags->class & F_CLASS_OPTIONAL) && cl_matches > 1)
1ae8ab47 1886 goto match_failed;
4670103e
CZ		 1887 }
1888 /* Did I check all the parsed flags? */
1889 if (lnflg)
1890 goto match_failed;
1891
1892 pr_debug ("flg");
1893 /* Possible match -- did we use all of our input? */
1894 if (tokidx == ntok)
1895 {
1896 *pntok = ntok;
1897 pr_debug ("\n");
1898 return opcode;
1899 }
1900
1901 match_failed:;
1902 pr_debug ("\n");
1903 /* Restore the original parameters. */
1904 memcpy (tok, bktok, MAX_INSN_ARGS * sizeof (*tok));
1905 ntok = bkntok;
1906 }
4670103e
CZ		 1907
1908 if (*pcpumatch)
1909 *pcpumatch = got_cpu_match;
1910
1911 return NULL;
1912}
1913
1914/* Swap operand tokens. */
1915
1916static void
1917swap_operand (expressionS *operand_array,
1918 unsigned source,
1919 unsigned destination)
1920{
1921 expressionS cpy_operand;
1922 expressionS *src_operand;
1923 expressionS *dst_operand;
1924 size_t size;
1925
1926 if (source == destination)
1927 return;
1928
1929 src_operand = &operand_array[source];
1930 dst_operand = &operand_array[destination];
1931 size = sizeof (expressionS);
1932
1933 /* Make copy of operand to swap with and swap. */
1934 memcpy (&cpy_operand, dst_operand, size);
1935 memcpy (dst_operand, src_operand, size);
1936 memcpy (src_operand, &cpy_operand, size);
1937}
1938
1939/* Check if *op matches *tok type.
1940 Returns FALSE if they don't match, TRUE if they match. */
1941
1942static bfd_boolean
1943pseudo_operand_match (const expressionS *tok,
1944 const struct arc_operand_operation *op)
1945{
1946 offsetT min, max, val;
1947 bfd_boolean ret;
1948 const struct arc_operand *operand_real = &arc_operands[op->operand_idx];
1949
1950 ret = FALSE;
1951 switch (tok->X_op)
1952 {
1953 case O_constant:
1954 if (operand_real->bits == 32 && (operand_real->flags & ARC_OPERAND_LIMM))
1955 ret = 1;
1956 else if (!(operand_real->flags & ARC_OPERAND_IR))
1957 {
1958 val = tok->X_add_number + op->count;
1959 if (operand_real->flags & ARC_OPERAND_SIGNED)
1960 {
1961 max = (1 << (operand_real->bits - 1)) - 1;
1962 min = -(1 << (operand_real->bits - 1));
1963 }
1964 else
1965 {
1966 max = (1 << operand_real->bits) - 1;
1967 min = 0;
1968 }
1969 if (min <= val && val <= max)
1970 ret = TRUE;
1971 }
6f4b1afc
CM		 1972 break;
1973
4670103e
CZ		 1974 case O_symbol:
1975 /* Handle all symbols as long immediates or signed 9. */
1976 if (operand_real->flags & ARC_OPERAND_LIMM ||
1977 ((operand_real->flags & ARC_OPERAND_SIGNED) && operand_real->bits == 9))
1978 ret = TRUE;
6f4b1afc
CM		 1979 break;
1980
4670103e
CZ		 1981 case O_register:
1982 if (operand_real->flags & ARC_OPERAND_IR)
1983 ret = TRUE;
1984 break;
1985
1986 case O_bracket:
1987 if (operand_real->flags & ARC_OPERAND_BRAKET)
1988 ret = TRUE;
6f4b1afc
CM		 1989 break;
1990
1991 default:
4670103e 1992 /* Unknown. */
6f4b1afc
CM		 1993 break;
1994 }
4670103e
CZ		 1995 return ret;
1996}
6f4b1afc 1997
4670103e
CZ		 1998/* Find pseudo instruction in array. */
1999
2000static const struct arc_pseudo_insn *
2001find_pseudo_insn (const char *opname,
2002 int ntok,
2003 const expressionS *tok)
2004{
2005 const struct arc_pseudo_insn *pseudo_insn = NULL;
2006 const struct arc_operand_operation *op;
2007 unsigned int i;
2008 int j;
2009
2010 for (i = 0; i < arc_num_pseudo_insn; ++i)
6f4b1afc 2011 {
4670103e
CZ		 2012 pseudo_insn = &arc_pseudo_insns[i];
2013 if (strcmp (pseudo_insn->mnemonic_p, opname) == 0)
2014 {
2015 op = pseudo_insn->operand;
2016 for (j = 0; j < ntok; ++j)
2017 if (!pseudo_operand_match (&tok[j], &op[j]))
2018 break;
2019
2020 /* Found the right instruction. */
2021 if (j == ntok)
2022 return pseudo_insn;
2023 }
6f4b1afc 2024 }
4670103e
CZ		 2025 return NULL;
2026}
252b5132 2027
4670103e 2028/* Assumes the expressionS *tok is of sufficient size. */
252b5132 2029
b9b47ab7 2030static const struct arc_opcode_hash_entry *
4670103e
CZ		 2031find_special_case_pseudo (const char *opname,
2032 int *ntok,
2033 expressionS *tok,
2034 int *nflgs,
2035 struct arc_flags *pflags)
2036{
2037 const struct arc_pseudo_insn *pseudo_insn = NULL;
2038 const struct arc_operand_operation *operand_pseudo;
2039 const struct arc_operand *operand_real;
2040 unsigned i;
2041 char construct_operand[MAX_CONSTR_STR];
886a2506 2042
4670103e
CZ		 2043 /* Find whether opname is in pseudo instruction array. */
2044 pseudo_insn = find_pseudo_insn (opname, *ntok, tok);
2045
2046 if (pseudo_insn == NULL)
2047 return NULL;
2048
2049 /* Handle flag, Limited to one flag at the moment. */
2050 if (pseudo_insn->flag_r != NULL)
2051 *nflgs += tokenize_flags (pseudo_insn->flag_r, &pflags[*nflgs],
2052 MAX_INSN_FLGS - *nflgs);
2053
2054 /* Handle operand operations. */
2055 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
252b5132 2056 {
4670103e
CZ		 2057 operand_pseudo = &pseudo_insn->operand[i];
2058 operand_real = &arc_operands[operand_pseudo->operand_idx];
886a2506 2059
4670103e
CZ		 2060 if (operand_real->flags & ARC_OPERAND_BRAKET &&
2061 !operand_pseudo->needs_insert)
2062 continue;
b125bd17 2063
4670103e
CZ		 2064 /* Has to be inserted (i.e. this token does not exist yet). */
2065 if (operand_pseudo->needs_insert)
2066 {
2067 if (operand_real->flags & ARC_OPERAND_BRAKET)
2068 {
2069 tok[i].X_op = O_bracket;
2070 ++(*ntok);
2071 continue;
2072 }
b125bd17 2073
4670103e
CZ		 2074 /* Check if operand is a register or constant and handle it
2075 by type. */
2076 if (operand_real->flags & ARC_OPERAND_IR)
2077 snprintf (construct_operand, MAX_CONSTR_STR, "r%d",
2078 operand_pseudo->count);
2079 else
2080 snprintf (construct_operand, MAX_CONSTR_STR, "%d",
2081 operand_pseudo->count);
886a2506 2082
4670103e
CZ		 2083 tokenize_arguments (construct_operand, &tok[i], 1);
2084 ++(*ntok);
2085 }
2086
2087 else if (operand_pseudo->count)
2088 {
2089 /* Operand number has to be adjusted accordingly (by operand
2090 type). */
2091 switch (tok[i].X_op)
2092 {
2093 case O_constant:
2094 tok[i].X_add_number += operand_pseudo->count;
2095 break;
2096
2097 case O_symbol:
2098 break;
2099
2100 default:
2101 /* Ignored. */
2102 break;
2103 }
2104 }
2105 }
2106
2107 /* Swap operands if necessary. Only supports one swap at the
2108 moment. */
2109 for (i = 0; i < pseudo_insn->operand_cnt; ++i)
2110 {
2111 operand_pseudo = &pseudo_insn->operand[i];
2112
2113 if (operand_pseudo->swap_operand_idx == i)
2114 continue;
2115
2116 swap_operand (tok, i, operand_pseudo->swap_operand_idx);
2117
2118 /* Prevent a swap back later by breaking out. */
2119 break;
2120 }
2121
da5be039 2122 return arc_find_opcode (pseudo_insn->mnemonic_r);
4670103e
CZ		 2123}
2124
b9b47ab7 2125static const struct arc_opcode_hash_entry *
4670103e
CZ		 2126find_special_case_flag (const char *opname,
2127 int *nflgs,
2128 struct arc_flags *pflags)
2129{
2130 unsigned int i;
2131 const char *flagnm;
2132 unsigned flag_idx, flag_arr_idx;
2133 size_t flaglen, oplen;
2134 const struct arc_flag_special *arc_flag_special_opcode;
b9b47ab7 2135 const struct arc_opcode_hash_entry *entry;
4670103e
CZ		 2136
2137 /* Search for special case instruction. */
2138 for (i = 0; i < arc_num_flag_special; i++)
2139 {
2140 arc_flag_special_opcode = &arc_flag_special_cases[i];
2141 oplen = strlen (arc_flag_special_opcode->name);
2142
2143 if (strncmp (opname, arc_flag_special_opcode->name, oplen) != 0)
2144 continue;
2145
2146 /* Found a potential special case instruction, now test for
2147 flags. */
2148 for (flag_arr_idx = 0;; ++flag_arr_idx)
2149 {
2150 flag_idx = arc_flag_special_opcode->flags[flag_arr_idx];
2151 if (flag_idx == 0)
2152 break; /* End of array, nothing found. */
886a2506 2153
4670103e
CZ		 2154 flagnm = arc_flag_operands[flag_idx].name;
2155 flaglen = strlen (flagnm);
2156 if (strcmp (opname + oplen, flagnm) == 0)
2157 {
b9b47ab7 2158 entry = arc_find_opcode (arc_flag_special_opcode->name);
886a2506 2159
4670103e
CZ		 2160 if (*nflgs + 1 > MAX_INSN_FLGS)
2161 break;
2162 memcpy (pflags[*nflgs].name, flagnm, flaglen);
2163 pflags[*nflgs].name[flaglen] = '\0';
2164 (*nflgs)++;
b9b47ab7 2165 return entry;
4670103e
CZ		 2166 }
2167 }
2168 }
2169 return NULL;
2170}
886a2506 2171
4670103e 2172/* Used to find special case opcode. */
886a2506 2173
b9b47ab7 2174static const struct arc_opcode_hash_entry *
4670103e
CZ		 2175find_special_case (const char *opname,
2176 int *nflgs,
2177 struct arc_flags *pflags,
2178 expressionS *tok,
2179 int *ntok)
2180{
b9b47ab7 2181 const struct arc_opcode_hash_entry *entry;
886a2506 2182
b9b47ab7 2183 entry = find_special_case_pseudo (opname, ntok, tok, nflgs, pflags);
886a2506 2184
b9b47ab7
AB		 2185 if (entry == NULL)
2186 entry = find_special_case_flag (opname, nflgs, pflags);
886a2506 2187
b9b47ab7 2188 return entry;
4670103e 2189}
886a2506 2190
4670103e
CZ		 2191/* Given an opcode name, pre-tockenized set of argumenst and the
2192 opcode flags, take it all the way through emission. */
886a2506 2193
4670103e
CZ		 2194static void
2195assemble_tokens (const char *opname,
2196 expressionS *tok,
2197 int ntok,
2198 struct arc_flags *pflags,
2199 int nflgs)
2200{
2201 bfd_boolean found_something = FALSE;
b9b47ab7 2202 const struct arc_opcode_hash_entry *entry;
4670103e 2203 int cpumatch = 1;
886a2506 2204
4670103e 2205 /* Search opcodes. */
b9b47ab7 2206 entry = arc_find_opcode (opname);
886a2506 2207
4670103e 2208 /* Couldn't find opcode conventional way, try special cases. */
b9b47ab7
AB		 2209 if (entry == NULL)
2210 entry = find_special_case (opname, &nflgs, pflags, tok, &ntok);
886a2506 2211
b9b47ab7 2212 if (entry != NULL)
4670103e 2213 {
b9b47ab7
AB		 2214 const struct arc_opcode *opcode;
2215
1328504b
AB		 2216 pr_debug ("%s:%d: assemble_tokens: %s\n",
2217 frag_now->fr_file, frag_now->fr_line, opname);
4670103e 2218 found_something = TRUE;
b9b47ab7
AB		 2219 opcode = find_opcode_match (entry, tok, &ntok, pflags,
2220 nflgs, &cpumatch);
2221 if (opcode != NULL)
4670103e
CZ		 2222 {
2223 struct arc_insn insn;
b9b47ab7 2224
4670103e
CZ		 2225 assemble_insn (opcode, tok, ntok, pflags, nflgs, &insn);
2226 emit_insn (&insn);
2227 return;
2228 }
2229 }
886a2506 2230
4670103e
CZ		 2231 if (found_something)
2232 {
2233 if (cpumatch)
2234 as_bad (_("inappropriate arguments for opcode '%s'"), opname);
2235 else
2236 as_bad (_("opcode '%s' not supported for target %s"), opname,
2237 arc_target_name);
2238 }
2239 else
2240 as_bad (_("unknown opcode '%s'"), opname);
886a2506
NC		 2241}
2242
4670103e 2243/* The public interface to the instruction assembler. */
886a2506 2244
4670103e
CZ		 2245void
2246md_assemble (char *str)
886a2506 2247{
4670103e
CZ		 2248 char *opname;
2249 expressionS tok[MAX_INSN_ARGS];
2250 int ntok, nflg;
2251 size_t opnamelen;
2252 struct arc_flags flags[MAX_INSN_FLGS];
886a2506 2253
4670103e
CZ		 2254 /* Split off the opcode. */
2255 opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_0123468");
2256 opname = xmalloc (opnamelen + 1);
2257 memcpy (opname, str, opnamelen);
2258 opname[opnamelen] = '\0';
886a2506 2259
4670103e
CZ		 2260 /* Signalize we are assmbling the instructions. */
2261 assembling_insn = TRUE;
886a2506 2262
4670103e
CZ		 2263 /* Tokenize the flags. */
2264 if ((nflg = tokenize_flags (str + opnamelen, flags, MAX_INSN_FLGS)) == -1)
2265 {
2266 as_bad (_("syntax error"));
2267 return;
2268 }
886a2506 2269
4670103e
CZ		 2270 /* Scan up to the end of the mnemonic which must end in space or end
2271 of string. */
2272 str += opnamelen;
2273 for (; *str != '\0'; str++)
2274 if (*str == ' ')
2275 break;
886a2506 2276
4670103e
CZ		 2277 /* Tokenize the rest of the line. */
2278 if ((ntok = tokenize_arguments (str, tok, MAX_INSN_ARGS)) < 0)
886a2506 2279 {
4670103e
CZ		 2280 as_bad (_("syntax error"));
2281 return;
252b5132
RH		 2282 }
2283
4670103e
CZ		 2284 /* Finish it off. */
2285 assemble_tokens (opname, tok, ntok, flags, nflg);
2286 assembling_insn = FALSE;
2287}
2288
2289/* Callback to insert a register into the hash table. */
2290
2291static void
f86f5863 2292declare_register (const char *name, int number)
4670103e
CZ		 2293{
2294 const char *err;
2295 symbolS *regS = symbol_create (name, reg_section,
2296 number, &zero_address_frag);
2297
2298 err = hash_insert (arc_reg_hash, S_GET_NAME (regS), (void *) regS);
2299 if (err)
e6ba1cba 2300 as_fatal (_("Inserting \"%s\" into register table failed: %s"),
4670103e
CZ		 2301 name, err);
2302}
252b5132 2303
4670103e 2304/* Construct symbols for each of the general registers. */
252b5132 2305
4670103e
CZ		 2306static void
2307declare_register_set (void)
2308{
2309 int i;
2310 for (i = 0; i < 64; ++i)
886a2506 2311 {
4670103e
CZ		 2312 char name[7];
2313
2314 sprintf (name, "r%d", i);
2315 declare_register (name, i);
2316 if ((i & 0x01) == 0)
886a2506 2317 {
4670103e
CZ		 2318 sprintf (name, "r%dr%d", i, i+1);
2319 declare_register (name, i);
886a2506
NC		 2320 }
2321 }
252b5132 2322}
ea1562b3 2323
4670103e
CZ		 2324/* Port-specific assembler initialization. This function is called
2325 once, at assembler startup time. */
ea1562b3
NC		 2326
2327void
4670103e 2328md_begin (void)
ea1562b3 2329{
b99747ae 2330 const struct arc_opcode *opcode = arc_opcodes;
886a2506 2331
24740d83
AB		 2332 if (!mach_type_specified_p)
2333 arc_select_cpu ("arc700");
2334
4670103e
CZ		 2335 /* The endianness can be chosen "at the factory". */
2336 target_big_endian = byte_order == BIG_ENDIAN;
886a2506 2337
4670103e
CZ		 2338 if (!bfd_set_arch_mach (stdoutput, bfd_arch_arc, arc_mach_type))
2339 as_warn (_("could not set architecture and machine"));
2340
2341 /* Set elf header flags. */
2342 bfd_set_private_flags (stdoutput, arc_eflag);
2343
2344 /* Set up a hash table for the instructions. */
2345 arc_opcode_hash = hash_new ();
2346 if (arc_opcode_hash == NULL)
2347 as_fatal (_("Virtual memory exhausted"));
2348
2349 /* Initialize the hash table with the insns. */
b99747ae 2350 do
ea1562b3 2351 {
b99747ae 2352 const char *name = opcode->name;
da5be039 2353
b99747ae 2354 arc_insert_opcode (opcode);
4670103e 2355
b99747ae
CZ		 2356 while (++opcode && opcode->name
2357 && (opcode->name == name
2358 || !strcmp (opcode->name, name)))
4670103e 2359 continue;
b99747ae 2360 }while (opcode->name);
4670103e
CZ		 2361
2362 /* Register declaration. */
2363 arc_reg_hash = hash_new ();
2364 if (arc_reg_hash == NULL)
2365 as_fatal (_("Virtual memory exhausted"));
2366
2367 declare_register_set ();
2368 declare_register ("gp", 26);
2369 declare_register ("fp", 27);
2370 declare_register ("sp", 28);
2371 declare_register ("ilink", 29);
2372 declare_register ("ilink1", 29);
2373 declare_register ("ilink2", 30);
2374 declare_register ("blink", 31);
2375
2376 declare_register ("mlo", 57);
2377 declare_register ("mmid", 58);
2378 declare_register ("mhi", 59);
2379
2380 declare_register ("acc1", 56);
2381 declare_register ("acc2", 57);
2382
2383 declare_register ("lp_count", 60);
2384 declare_register ("pcl", 63);
2385
2386 /* Initialize the last instructions. */
2387 memset (&arc_last_insns[0], 0, sizeof (arc_last_insns));
f36e33da
CZ		 2388
2389 /* Aux register declaration. */
2390 arc_aux_hash = hash_new ();
2391 if (arc_aux_hash == NULL)
2392 as_fatal (_("Virtual memory exhausted"));
2393
2394 const struct arc_aux_reg *auxr = &arc_aux_regs[0];
2395 unsigned int i;
2396 for (i = 0; i < arc_num_aux_regs; i++, auxr++)
2397 {
2398 const char *retval;
2399
2400 if (!(auxr->cpu & arc_target))
2401 continue;
2402
2403 if ((auxr->subclass != NONE)
2404 && !check_cpu_feature (auxr->subclass))
2405 continue;
2406
2407 retval = hash_insert (arc_aux_hash, auxr->name, (void *) auxr);
2408 if (retval)
2409 as_fatal (_("internal error: can't hash aux register '%s': %s"),
2410 auxr->name, retval);
2411 }
886a2506 2412}
ea1562b3 2413
4670103e
CZ		 2414/* Write a value out to the object file, using the appropriate
2415 endianness. */
ea1562b3 2416
4670103e
CZ		 2417void
2418md_number_to_chars (char *buf,
2419 valueT val,
2420 int n)
886a2506 2421{
4670103e
CZ		 2422 if (target_big_endian)
2423 number_to_chars_bigendian (buf, val, n);
2424 else
2425 number_to_chars_littleendian (buf, val, n);
886a2506 2426}
ea1562b3 2427
4670103e 2428/* Round up a section size to the appropriate boundary. */
ea1562b3 2429
4670103e
CZ		 2430valueT
2431md_section_align (segT segment,
2432 valueT size)
886a2506 2433{
4670103e
CZ		 2434 int align = bfd_get_section_alignment (stdoutput, segment);
2435
2436 return ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
886a2506 2437}
ea1562b3 2438
4670103e
CZ		 2439/* The location from which a PC relative jump should be calculated,
2440 given a PC relative reloc. */
ea1562b3 2441
4670103e
CZ		 2442long
2443md_pcrel_from_section (fixS *fixP,
2444 segT sec)
886a2506 2445{
4670103e 2446 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
ea1562b3 2447
4670103e 2448 pr_debug ("pcrel_from_section, fx_offset = %d\n", (int) fixP->fx_offset);
ea1562b3 2449
4670103e
CZ		 2450 if (fixP->fx_addsy != (symbolS *) NULL
2451 && (!S_IS_DEFINED (fixP->fx_addsy)
2452 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
2453 {
2454 pr_debug ("Unknown pcrel symbol: %s\n", S_GET_NAME (fixP->fx_addsy));
ea1562b3 2455
4670103e
CZ		 2456 /* The symbol is undefined (or is defined but not in this section).
2457 Let the linker figure it out. */
2458 return 0;
2459 }
2460
2461 if ((int) fixP->fx_r_type < 0)
886a2506 2462 {
4670103e
CZ		 2463 /* These are the "internal" relocations. Align them to
2464 32 bit boundary (PCL), for the moment. */
2465 base &= ~3;
886a2506 2466 }
4670103e
CZ		 2467 else
2468 {
2469 switch (fixP->fx_r_type)
2470 {
2471 case BFD_RELOC_ARC_PC32:
2472 /* The hardware calculates relative to the start of the
2473 insn, but this relocation is relative to location of the
2474 LIMM, compensate. The base always needs to be
2475 substracted by 4 as we do not support this type of PCrel
2476 relocation for short instructions. */
2477 base -= 4;
2478 /* Fall through. */
2479 case BFD_RELOC_ARC_PLT32:
2480 case BFD_RELOC_ARC_S25H_PCREL_PLT:
2481 case BFD_RELOC_ARC_S21H_PCREL_PLT:
2482 case BFD_RELOC_ARC_S25W_PCREL_PLT:
2483 case BFD_RELOC_ARC_S21W_PCREL_PLT:
2484
2485 case BFD_RELOC_ARC_S21H_PCREL:
2486 case BFD_RELOC_ARC_S25H_PCREL:
2487 case BFD_RELOC_ARC_S13_PCREL:
2488 case BFD_RELOC_ARC_S21W_PCREL:
2489 case BFD_RELOC_ARC_S25W_PCREL:
2490 base &= ~3;
2491 break;
2492 default:
2493 as_bad_where (fixP->fx_file, fixP->fx_line,
2494 _("unhandled reloc %s in md_pcrel_from_section"),
2495 bfd_get_reloc_code_name (fixP->fx_r_type));
2496 break;
2497 }
2498 }
2499
2500 pr_debug ("pcrel from %x + %lx = %x, symbol: %s (%x)\n",
2501 fixP->fx_frag->fr_address, fixP->fx_where, base,
2502 fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "(null)",
2503 fixP->fx_addsy ? S_GET_VALUE (fixP->fx_addsy) : 0);
2504
2505 return base;
886a2506 2506}
ea1562b3 2507
4670103e 2508/* Given a BFD relocation find the coresponding operand. */
ea1562b3 2509
4670103e
CZ		 2510static const struct arc_operand *
2511find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc)
2512{
2513 unsigned i;
ea1562b3 2514
4670103e
CZ		 2515 for (i = 0; i < arc_num_operands; i++)
2516 if (arc_operands[i].default_reloc == reloc)
2517 return &arc_operands[i];
2518 return NULL;
2519}
ea1562b3 2520
4670103e 2521/* Insert an operand value into an instruction. */
ea1562b3 2522
4670103e
CZ		 2523static unsigned
2524insert_operand (unsigned insn,
2525 const struct arc_operand *operand,
2526 offsetT val,
3b4dbbbf 2527 const char *file,
4670103e 2528 unsigned line)
886a2506 2529{
4670103e 2530 offsetT min = 0, max = 0;
ea1562b3 2531
4670103e
CZ		 2532 if (operand->bits != 32
2533 && !(operand->flags & ARC_OPERAND_NCHK)
2534 && !(operand->flags & ARC_OPERAND_FAKE))
886a2506 2535 {
4670103e
CZ		 2536 if (operand->flags & ARC_OPERAND_SIGNED)
2537 {
2538 max = (1 << (operand->bits - 1)) - 1;
2539 min = -(1 << (operand->bits - 1));
2540 }
2541 else
2542 {
2543 max = (1 << operand->bits) - 1;
2544 min = 0;
2545 }
886a2506 2546
4670103e
CZ		 2547 if (val < min || val > max)
2548 as_bad_value_out_of_range (_("operand"),
2549 val, min, max, file, line);
2550 }
ea1562b3 2551
4670103e
CZ		 2552 pr_debug ("insert field: %ld <= %ld <= %ld in 0x%08x\n",
2553 min, val, max, insn);
ea1562b3 2554
4670103e
CZ		 2555 if ((operand->flags & ARC_OPERAND_ALIGNED32)
2556 && (val & 0x03))
2557 as_bad_where (file, line,
2558 _("Unaligned operand. Needs to be 32bit aligned"));
ea1562b3 2559
4670103e
CZ		 2560 if ((operand->flags & ARC_OPERAND_ALIGNED16)
2561 && (val & 0x01))
2562 as_bad_where (file, line,
2563 _("Unaligned operand. Needs to be 16bit aligned"));
ea1562b3 2564
4670103e
CZ		 2565 if (operand->insert)
2566 {
2567 const char *errmsg = NULL;
ea1562b3 2568
4670103e
CZ		 2569 insn = (*operand->insert) (insn, val, &errmsg);
2570 if (errmsg)
2571 as_warn_where (file, line, "%s", errmsg);
2572 }
2573 else
2574 {
2575 if (operand->flags & ARC_OPERAND_TRUNCATE)
2576 {
2577 if (operand->flags & ARC_OPERAND_ALIGNED32)
2578 val >>= 2;
2579 if (operand->flags & ARC_OPERAND_ALIGNED16)
2580 val >>= 1;
886a2506 2581 }
4670103e
CZ		 2582 insn |= ((val & ((1 << operand->bits) - 1)) << operand->shift);
2583 }
2584 return insn;
2585}
ea1562b3 2586
4670103e
CZ		 2587/* Apply a fixup to the object code. At this point all symbol values
2588 should be fully resolved, and we attempt to completely resolve the
2589 reloc. If we can not do that, we determine the correct reloc code
2590 and put it back in the fixup. To indicate that a fixup has been
2591 eliminated, set fixP->fx_done. */
ea1562b3 2592
4670103e
CZ		 2593void
2594md_apply_fix (fixS *fixP,
2595 valueT *valP,
2596 segT seg)
2597{
2598 char * const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where;
2599 valueT value = *valP;
2600 unsigned insn = 0;
2601 symbolS *fx_addsy, *fx_subsy;
2602 offsetT fx_offset;
2603 segT add_symbol_segment = absolute_section;
2604 segT sub_symbol_segment = absolute_section;
2605 const struct arc_operand *operand = NULL;
2606 extended_bfd_reloc_code_real_type reloc;
886a2506 2607
4670103e
CZ		 2608 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2609 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2610 ((int) fixP->fx_r_type < 0) ? "Internal":
2611 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2612 fixP->fx_offset);
886a2506 2613
4670103e
CZ		 2614 fx_addsy = fixP->fx_addsy;
2615 fx_subsy = fixP->fx_subsy;
2616 fx_offset = 0;
886a2506 2617
4670103e
CZ		 2618 if (fx_addsy)
2619 {
2620 add_symbol_segment = S_GET_SEGMENT (fx_addsy);
886a2506
NC		 2621 }
2622
4670103e
CZ		 2623 if (fx_subsy
2624 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF
2625 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_DTPOFF_S9
2626 && fixP->fx_r_type != BFD_RELOC_ARC_TLS_GD_LD)
2627 {
2628 resolve_symbol_value (fx_subsy);
2629 sub_symbol_segment = S_GET_SEGMENT (fx_subsy);
886a2506 2630
4670103e
CZ		 2631 if (sub_symbol_segment == absolute_section)
2632 {
2633 /* The symbol is really a constant. */
2634 fx_offset -= S_GET_VALUE (fx_subsy);
2635 fx_subsy = NULL;
2636 }
2637 else
2638 {
2639 as_bad_where (fixP->fx_file, fixP->fx_line,
2640 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
2641 fx_addsy ? S_GET_NAME (fx_addsy) : "0",
2642 segment_name (add_symbol_segment),
2643 S_GET_NAME (fx_subsy),
2644 segment_name (sub_symbol_segment));
2645 return;
2646 }
2647 }
886a2506 2648
4670103e
CZ		 2649 if (fx_addsy
2650 && !S_IS_WEAK (fx_addsy))
2651 {
2652 if (add_symbol_segment == seg
2653 && fixP->fx_pcrel)
2654 {
2655 value += S_GET_VALUE (fx_addsy);
2656 value -= md_pcrel_from_section (fixP, seg);
2657 fx_addsy = NULL;
2658 fixP->fx_pcrel = FALSE;
2659 }
2660 else if (add_symbol_segment == absolute_section)
2661 {
2662 value = fixP->fx_offset;
2663 fx_offset += S_GET_VALUE (fixP->fx_addsy);
2664 fx_addsy = NULL;
2665 fixP->fx_pcrel = FALSE;
2666 }
2667 }
886a2506 2668
4670103e
CZ		 2669 if (!fx_addsy)
2670 fixP->fx_done = TRUE;
886a2506 2671
4670103e 2672 if (fixP->fx_pcrel)
886a2506 2673 {
4670103e
CZ		 2674 if (fx_addsy
2675 && ((S_IS_DEFINED (fx_addsy)
2676 && S_GET_SEGMENT (fx_addsy) != seg)
2677 || S_IS_WEAK (fx_addsy)))
2678 value += md_pcrel_from_section (fixP, seg);
886a2506 2679
4670103e
CZ		 2680 switch (fixP->fx_r_type)
2681 {
2682 case BFD_RELOC_ARC_32_ME:
2683 /* This is a pc-relative value in a LIMM. Adjust it to the
2684 address of the instruction not to the address of the
2685 LIMM. Note: it is not anylonger valid this afirmation as
2686 the linker consider ARC_PC32 a fixup to entire 64 bit
2687 insn. */
2688 fixP->fx_offset += fixP->fx_frag->fr_address;
2689 /* Fall through. */
2690 case BFD_RELOC_32:
2691 fixP->fx_r_type = BFD_RELOC_ARC_PC32;
2692 /* Fall through. */
2693 case BFD_RELOC_ARC_PC32:
2694 /* fixP->fx_offset += fixP->fx_where - fixP->fx_dot_value; */
886a2506
NC		 2695 break;
2696 default:
4670103e
CZ		 2697 if ((int) fixP->fx_r_type < 0)
2698 as_fatal (_("PC relative relocation not allowed for (internal) type %d"),
2699 fixP->fx_r_type);
886a2506 2700 break;
ea1562b3
NC		 2701 }
2702 }
2703
4670103e
CZ		 2704 pr_debug ("%s:%u: apply_fix: r_type=%d (%s) value=0x%lX offset=0x%lX\n",
2705 fixP->fx_file, fixP->fx_line, fixP->fx_r_type,
2706 ((int) fixP->fx_r_type < 0) ? "Internal":
2707 bfd_get_reloc_code_name (fixP->fx_r_type), value,
2708 fixP->fx_offset);
886a2506 2709
886a2506 2710
4670103e
CZ		 2711 /* Now check for TLS relocations. */
2712 reloc = fixP->fx_r_type;
2713 switch (reloc)
886a2506 2714 {
4670103e
CZ		 2715 case BFD_RELOC_ARC_TLS_DTPOFF:
2716 case BFD_RELOC_ARC_TLS_LE_32:
2717 if (fixP->fx_done)
2718 break;
2719 /* Fall through. */
2720 case BFD_RELOC_ARC_TLS_GD_GOT:
2721 case BFD_RELOC_ARC_TLS_IE_GOT:
2722 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2723 break;
886a2506 2724
4670103e
CZ		 2725 case BFD_RELOC_ARC_TLS_GD_LD:
2726 gas_assert (!fixP->fx_offset);
2727 if (fixP->fx_subsy)
2728 fixP->fx_offset
2729 = (S_GET_VALUE (fixP->fx_subsy)
2730 - fixP->fx_frag->fr_address- fixP->fx_where);
2731 fixP->fx_subsy = NULL;
2732 /* Fall through. */
2733 case BFD_RELOC_ARC_TLS_GD_CALL:
2734 /* These two relocs are there just to allow ld to change the tls
2735 model for this symbol, by patching the code. The offset -
2736 and scale, if any - will be installed by the linker. */
2737 S_SET_THREAD_LOCAL (fixP->fx_addsy);
2738 break;
886a2506 2739
4670103e
CZ		 2740 case BFD_RELOC_ARC_TLS_LE_S9:
2741 case BFD_RELOC_ARC_TLS_DTPOFF_S9:
2742 as_bad (_("TLS_*_S9 relocs are not supported yet"));
2743 break;
2744
2745 default:
2746 break;
886a2506
NC		 2747 }
2748
4670103e 2749 if (!fixP->fx_done)
886a2506 2750 {
4670103e 2751 return;
886a2506 2752 }
886a2506 2753
4670103e
CZ		 2754 /* Addjust the value if we have a constant. */
2755 value += fx_offset;
886a2506 2756
4670103e
CZ		 2757 /* For hosts with longs bigger than 32-bits make sure that the top
2758 bits of a 32-bit negative value read in by the parser are set,
2759 so that the correct comparisons are made. */
2760 if (value & 0x80000000)
2761 value |= (-1L << 31);
886a2506 2762
4670103e
CZ		 2763 reloc = fixP->fx_r_type;
2764 switch (reloc)
2765 {
2766 case BFD_RELOC_8:
2767 case BFD_RELOC_16:
2768 case BFD_RELOC_24:
2769 case BFD_RELOC_32:
2770 case BFD_RELOC_64:
2771 case BFD_RELOC_ARC_32_PCREL:
2772 md_number_to_chars (fixpos, value, fixP->fx_size);
2773 return;
886a2506 2774
4670103e
CZ		 2775 case BFD_RELOC_ARC_GOTPC32:
2776 /* I cannot fix an GOTPC relocation because I need to relax it
2777 from ld rx,[pcl,@sym@gotpc] to add rx,pcl,@sym@gotpc. */
2778 as_bad (_("Unsupported operation on reloc"));
2779 return;
886a2506 2780
4670103e
CZ		 2781 case BFD_RELOC_ARC_TLS_DTPOFF:
2782 case BFD_RELOC_ARC_TLS_LE_32:
2783 gas_assert (!fixP->fx_addsy);
2784 gas_assert (!fixP->fx_subsy);
886a2506 2785
4670103e
CZ		 2786 case BFD_RELOC_ARC_GOTOFF:
2787 case BFD_RELOC_ARC_32_ME:
2788 case BFD_RELOC_ARC_PC32:
2789 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
2790 return;
886a2506 2791
4670103e
CZ		 2792 case BFD_RELOC_ARC_PLT32:
2793 md_number_to_chars_midend (fixpos, value, fixP->fx_size);
2794 return;
886a2506 2795
4670103e
CZ		 2796 case BFD_RELOC_ARC_S25H_PCREL_PLT:
2797 reloc = BFD_RELOC_ARC_S25W_PCREL;
2798 goto solve_plt;
886a2506 2799
4670103e
CZ		 2800 case BFD_RELOC_ARC_S21H_PCREL_PLT:
2801 reloc = BFD_RELOC_ARC_S21H_PCREL;
2802 goto solve_plt;
886a2506 2803
4670103e
CZ		 2804 case BFD_RELOC_ARC_S25W_PCREL_PLT:
2805 reloc = BFD_RELOC_ARC_S25W_PCREL;
2806 goto solve_plt;
886a2506 2807
4670103e
CZ		 2808 case BFD_RELOC_ARC_S21W_PCREL_PLT:
2809 reloc = BFD_RELOC_ARC_S21W_PCREL;
886a2506 2810
4670103e
CZ		 2811 case BFD_RELOC_ARC_S25W_PCREL:
2812 case BFD_RELOC_ARC_S21W_PCREL:
2813 case BFD_RELOC_ARC_S21H_PCREL:
2814 case BFD_RELOC_ARC_S25H_PCREL:
2815 case BFD_RELOC_ARC_S13_PCREL:
2816 solve_plt:
2817 operand = find_operand_for_reloc (reloc);
2818 gas_assert (operand);
886a2506
NC		 2819 break;
2820
2821 default:
4670103e
CZ		 2822 {
2823 if ((int) fixP->fx_r_type >= 0)
2824 as_fatal (_("unhandled relocation type %s"),
2825 bfd_get_reloc_code_name (fixP->fx_r_type));
886a2506 2826
4670103e
CZ		 2827 /* The rest of these fixups needs to be completely resolved as
2828 constants. */
2829 if (fixP->fx_addsy != 0
2830 && S_GET_SEGMENT (fixP->fx_addsy) != absolute_section)
2831 as_bad_where (fixP->fx_file, fixP->fx_line,
2832 _("non-absolute expression in constant field"));
886a2506 2833
4670103e
CZ		 2834 gas_assert (-(int) fixP->fx_r_type < (int) arc_num_operands);
2835 operand = &arc_operands[-(int) fixP->fx_r_type];
2836 break;
2837 }
2838 }
886a2506 2839
4670103e 2840 if (target_big_endian)
886a2506 2841 {
4670103e 2842 switch (fixP->fx_size)
886a2506 2843 {
4670103e
CZ		 2844 case 4:
2845 insn = bfd_getb32 (fixpos);
2846 break;
2847 case 2:
2848 insn = bfd_getb16 (fixpos);
2849 break;
2850 default:
2851 as_bad_where (fixP->fx_file, fixP->fx_line,
2852 _("unknown fixup size"));
2853 }
2854 }
2855 else
2856 {
2857 insn = 0;
2858 switch (fixP->fx_size)
2859 {
2860 case 4:
2861 insn = bfd_getl16 (fixpos) << 16 | bfd_getl16 (fixpos + 2);
2862 break;
2863 case 2:
2864 insn = bfd_getl16 (fixpos);
2865 break;
2866 default:
2867 as_bad_where (fixP->fx_file, fixP->fx_line,
2868 _("unknown fixup size"));
886a2506
NC		 2869 }
2870 }
886a2506 2871
4670103e
CZ		 2872 insn = insert_operand (insn, operand, (offsetT) value,
2873 fixP->fx_file, fixP->fx_line);
886a2506 2874
4670103e
CZ		 2875 md_number_to_chars_midend (fixpos, insn, fixP->fx_size);
2876}
886a2506 2877
4670103e 2878/* Prepare machine-dependent frags for relaxation.
886a2506 2879
4670103e
CZ		 2880 Called just before relaxation starts. Any symbol that is now undefined
2881 will not become defined.
886a2506 2882
4670103e 2883 Return the correct fr_subtype in the frag.
886a2506 2884
4670103e
CZ		 2885 Return the initial "guess for fr_var" to caller. The guess for fr_var
2886 is *actually* the growth beyond fr_fix. Whatever we do to grow fr_fix
2887 or fr_var contributes to our returned value.
886a2506 2888
4670103e
CZ		 2889 Although it may not be explicit in the frag, pretend
2890 fr_var starts with a value. */
886a2506 2891
4670103e
CZ		 2892int
2893md_estimate_size_before_relax (fragS *fragP,
2894 segT segment)
2895{
2896 int growth;
2897
2898 /* If the symbol is not located within the same section AND it's not
2899 an absolute section, use the maximum. OR if the symbol is a
2900 constant AND the insn is by nature not pc-rel, use the maximum.
2901 OR if the symbol is being equated against another symbol, use the
2902 maximum. OR if the symbol is weak use the maximum. */
2903 if ((S_GET_SEGMENT (fragP->fr_symbol) != segment
2904 && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section)
2905 || (symbol_constant_p (fragP->fr_symbol)
2906 && !fragP->tc_frag_data.pcrel)
2907 || symbol_equated_p (fragP->fr_symbol)
2908 || S_IS_WEAK (fragP->fr_symbol))
2909 {
2910 while (md_relax_table[fragP->fr_subtype].rlx_more != ARC_RLX_NONE)
2911 ++fragP->fr_subtype;
2912 }
886a2506 2913
4670103e
CZ		 2914 growth = md_relax_table[fragP->fr_subtype].rlx_length;
2915 fragP->fr_var = growth;
886a2506 2916
4670103e
CZ		 2917 pr_debug ("%s:%d: md_estimate_size_before_relax: %d\n",
2918 fragP->fr_file, fragP->fr_line, growth);
886a2506 2919
4670103e
CZ		 2920 return growth;
2921}
886a2506 2922
4670103e
CZ		 2923/* Translate internal representation of relocation info to BFD target
2924 format. */
886a2506 2925
4670103e
CZ		 2926arelent *
2927tc_gen_reloc (asection *section ATTRIBUTE_UNUSED,
2928 fixS *fixP)
2929{
2930 arelent *reloc;
2931 bfd_reloc_code_real_type code;
886a2506 2932
4670103e
CZ		 2933 reloc = (arelent *) xmalloc (sizeof (* reloc));
2934 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
2935 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
2936 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
886a2506 2937
4670103e
CZ		 2938 /* Make sure none of our internal relocations make it this far.
2939 They'd better have been fully resolved by this point. */
2940 gas_assert ((int) fixP->fx_r_type > 0);
886a2506 2941
4670103e 2942 code = fixP->fx_r_type;
886a2506 2943
4670103e
CZ		 2944 /* if we have something like add gp, pcl,
2945 _GLOBAL_OFFSET_TABLE_@gotpc. */
2946 if (code == BFD_RELOC_ARC_GOTPC32
2947 && GOT_symbol
2948 && fixP->fx_addsy == GOT_symbol)
2949 code = BFD_RELOC_ARC_GOTPC;
886a2506 2950
4670103e
CZ		 2951 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
2952 if (reloc->howto == NULL)
886a2506 2953 {
4670103e
CZ		 2954 as_bad_where (fixP->fx_file, fixP->fx_line,
2955 _("cannot represent `%s' relocation in object file"),
2956 bfd_get_reloc_code_name (code));
2957 return NULL;
2958 }
886a2506 2959
4670103e
CZ		 2960 if (!fixP->fx_pcrel != !reloc->howto->pc_relative)
2961 as_fatal (_("internal error? cannot generate `%s' relocation"),
2962 bfd_get_reloc_code_name (code));
886a2506 2963
4670103e 2964 gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
886a2506 2965
4670103e
CZ		 2966 if (code == BFD_RELOC_ARC_TLS_DTPOFF
2967 || code == BFD_RELOC_ARC_TLS_DTPOFF_S9)
2968 {
2969 asymbol *sym
2970 = fixP->fx_subsy ? symbol_get_bfdsym (fixP->fx_subsy) : NULL;
2971 /* We just want to store a 24 bit index, but we have to wait
2972 till after write_contents has been called via
2973 bfd_map_over_sections before we can get the index from
2974 _bfd_elf_symbol_from_bfd_symbol. Thus, the write_relocs
2975 function is elf32-arc.c has to pick up the slack.
2976 Unfortunately, this leads to problems with hosts that have
2977 pointers wider than long (bfd_vma). There would be various
2978 ways to handle this, all error-prone :-( */
2979 reloc->addend = (bfd_vma) sym;
2980 if ((asymbol *) reloc->addend != sym)
2981 {
2982 as_bad ("Can't store pointer\n");
2983 return NULL;
886a2506
NC		 2984 }
2985 }
4670103e
CZ		 2986 else
2987 reloc->addend = fixP->fx_offset;
2988
2989 return reloc;
886a2506
NC		 2990}
2991
4670103e
CZ		 2992/* Perform post-processing of machine-dependent frags after relaxation.
2993 Called after relaxation is finished.
2994 In: Address of frag.
2995 fr_type == rs_machine_dependent.
2996 fr_subtype is what the address relaxed to.
886a2506 2997
4670103e
CZ		 2998 Out: Any fixS:s and constants are set up. */
2999
3000void
3001md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
3002 segT segment ATTRIBUTE_UNUSED,
3003 fragS *fragP)
886a2506 3004{
4670103e
CZ		 3005 const relax_typeS *table_entry;
3006 char *dest;
3007 const struct arc_opcode *opcode;
3008 struct arc_insn insn;
3009 int size, fix;
3010 struct arc_relax_type *relax_arg = &fragP->tc_frag_data;
886a2506 3011
4670103e
CZ		 3012 fix = (fragP->fr_fix < 0 ? 0 : fragP->fr_fix);
3013 dest = fragP->fr_literal + fix;
3014 table_entry = TC_GENERIC_RELAX_TABLE + fragP->fr_subtype;
886a2506 3015
4670103e
CZ		 3016 pr_debug ("%s:%d: md_convert_frag, subtype: %d, fix: %d, var: %d\n",
3017 fragP->fr_file, fragP->fr_line,
3018 fragP->fr_subtype, fix, fragP->fr_var);
886a2506 3019
4670103e
CZ		 3020 if (fragP->fr_subtype <= 0
3021 && fragP->fr_subtype >= arc_num_relax_opcodes)
3022 as_fatal (_("no relaxation found for this instruction."));
886a2506 3023
4670103e 3024 opcode = &arc_relax_opcodes[fragP->fr_subtype];
886a2506 3025
4670103e
CZ		 3026 assemble_insn (opcode, relax_arg->tok, relax_arg->ntok, relax_arg->pflags,
3027 relax_arg->nflg, &insn);
886a2506 3028
4670103e 3029 apply_fixups (&insn, fragP, fix);
886a2506 3030
4670103e
CZ		 3031 size = insn.short_insn ? (insn.has_limm ? 6 : 2) : (insn.has_limm ? 8 : 4);
3032 gas_assert (table_entry->rlx_length == size);
3033 emit_insn0 (&insn, dest, TRUE);
886a2506 3034
4670103e
CZ		 3035 fragP->fr_fix += table_entry->rlx_length;
3036 fragP->fr_var = 0;
886a2506
NC		 3037}
3038
4670103e
CZ		 3039/* We have no need to default values of symbols. We could catch
3040 register names here, but that is handled by inserting them all in
3041 the symbol table to begin with. */
886a2506 3042
4670103e
CZ		 3043symbolS *
3044md_undefined_symbol (char *name)
886a2506 3045{
4670103e
CZ		 3046 /* The arc abi demands that a GOT[0] should be referencible as
3047 [pc+_DYNAMIC@gotpc]. Hence we convert a _DYNAMIC@gotpc to a
3048 GOTPC reference to _GLOBAL_OFFSET_TABLE_. */
3049 if (((*name == '_')
3050 && (*(name+1) == 'G')
3051 && (strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0))
3052 || ((*name == '_')
3053 && (*(name+1) == 'D')
3054 && (strcmp (name, DYNAMIC_STRUCT_NAME) == 0)))
886a2506 3055 {
4670103e
CZ		 3056 if (!GOT_symbol)
3057 {
3058 if (symbol_find (name))
3059 as_bad ("GOT already in symbol table");
3060
3061 GOT_symbol = symbol_new (GLOBAL_OFFSET_TABLE_NAME, undefined_section,
3062 (valueT) 0, &zero_address_frag);
3063 };
3064 return GOT_symbol;
886a2506 3065 }
4670103e 3066 return NULL;
886a2506
NC		 3067}
3068
4670103e
CZ		 3069/* Turn a string in input_line_pointer into a floating point constant
3070 of type type, and store the appropriate bytes in *litP. The number
3071 of LITTLENUMS emitted is stored in *sizeP. An error message is
3072 returned, or NULL on OK. */
886a2506 3073
6d4af3c2 3074const char *
4670103e 3075md_atof (int type, char *litP, int *sizeP)
886a2506 3076{
4670103e
CZ		 3077 return ieee_md_atof (type, litP, sizeP, target_big_endian);
3078}
886a2506 3079
4670103e
CZ		 3080/* Called for any expression that can not be recognized. When the
3081 function is called, `input_line_pointer' will point to the start of
3082 the expression. */
886a2506 3083
4670103e
CZ		 3084void
3085md_operand (expressionS *expressionP ATTRIBUTE_UNUSED)
3086{
3087 char *p = input_line_pointer;
3088 if (*p == '@')
886a2506 3089 {
4670103e
CZ		 3090 input_line_pointer++;
3091 expressionP->X_op = O_symbol;
3092 expression (expressionP);
3093 }
3094}
886a2506 3095
4670103e
CZ		 3096/* This function is called from the function 'expression', it attempts
3097 to parse special names (in our case register names). It fills in
3098 the expression with the identified register. It returns TRUE if
3099 it is a register and FALSE otherwise. */
886a2506 3100
4670103e
CZ		 3101bfd_boolean
3102arc_parse_name (const char *name,
3103 struct expressionS *e)
3104{
3105 struct symbol *sym;
886a2506 3106
4670103e
CZ		 3107 if (!assembling_insn)
3108 return FALSE;
886a2506 3109
4670103e
CZ		 3110 /* Handle only registers. */
3111 if (e->X_op != O_absent)
3112 return FALSE;
886a2506 3113
4670103e
CZ		 3114 sym = hash_find (arc_reg_hash, name);
3115 if (sym)
3116 {
3117 e->X_op = O_register;
3118 e->X_add_number = S_GET_VALUE (sym);
3119 return TRUE;
3120 }
3121 return FALSE;
3122}
886a2506 3123
4670103e
CZ		 3124/* md_parse_option
3125 Invocation line includes a switch not recognized by the base assembler.
3126 See if it's a processor-specific option.
886a2506 3127
4670103e 3128 New options (supported) are:
886a2506 3129
4670103e
CZ		 3130 -mcpu=<cpu name> Assemble for selected processor
3131 -EB/-mbig-endian Big-endian
3132 -EL/-mlittle-endian Little-endian
3133 -mrelax Enable relaxation
886a2506 3134
4670103e
CZ		 3135 The following CPU names are recognized:
3136 arc700, av2em, av2hs. */
886a2506 3137
4670103e 3138int
17b9d67d 3139md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
4670103e 3140{
4670103e
CZ		 3141 switch (c)
3142 {
3143 case OPTION_ARC600:
3144 case OPTION_ARC601:
3145 return md_parse_option (OPTION_MCPU, "arc600");
886a2506 3146
4670103e
CZ		 3147 case OPTION_ARC700:
3148 return md_parse_option (OPTION_MCPU, "arc700");
886a2506 3149
4670103e
CZ		 3150 case OPTION_ARCEM:
3151 return md_parse_option (OPTION_MCPU, "arcem");
886a2506 3152
4670103e
CZ		 3153 case OPTION_ARCHS:
3154 return md_parse_option (OPTION_MCPU, "archs");
886a2506 3155
4670103e
CZ		 3156 case OPTION_MCPU:
3157 {
24740d83
AB		 3158 arc_select_cpu (arg);
3159 mach_type_specified_p = 1;
4670103e
CZ		 3160 break;
3161 }
886a2506 3162
4670103e
CZ		 3163 case OPTION_EB:
3164 arc_target_format = "elf32-bigarc";
3165 byte_order = BIG_ENDIAN;
3166 break;
886a2506 3167
4670103e
CZ		 3168 case OPTION_EL:
3169 arc_target_format = "elf32-littlearc";
3170 byte_order = LITTLE_ENDIAN;
3171 break;
886a2506 3172
4670103e
CZ		 3173 case OPTION_CD:
3174 /* This option has an effect only on ARC EM. */
3175 if (arc_target & ARC_OPCODE_ARCv2EM)
3176 arc_features |= ARC_CD;
8ddf6b2a
CZ		 3177 else
3178 as_warn (_("Code density option invalid for selected CPU"));
4670103e 3179 break;
886a2506 3180
4670103e
CZ		 3181 case OPTION_RELAX:
3182 relaxation_state = 1;
3183 break;
886a2506 3184
4670103e
CZ		 3185 case OPTION_USER_MODE:
3186 case OPTION_LD_EXT_MASK:
3187 case OPTION_SWAP:
3188 case OPTION_NORM:
3189 case OPTION_BARREL_SHIFT:
3190 case OPTION_MIN_MAX:
3191 case OPTION_NO_MPY:
3192 case OPTION_EA:
3193 case OPTION_MUL64:
3194 case OPTION_SIMD:
8ddf6b2a
CZ		 3195 /* Dummy options are accepted but have no effect. */
3196 break;
3197
4670103e 3198 case OPTION_SPFP:
8ddf6b2a
CZ		 3199 arc_features |= ARC_SPFP;
3200 break;
3201
4670103e 3202 case OPTION_DPFP:
8ddf6b2a
CZ		 3203 arc_features |= ARC_DPFP;
3204 break;
3205
4670103e
CZ		 3206 case OPTION_XMAC_D16:
3207 case OPTION_XMAC_24:
3208 case OPTION_DSP_PACKA:
3209 case OPTION_CRC:
3210 case OPTION_DVBF:
3211 case OPTION_TELEPHONY:
3212 case OPTION_XYMEMORY:
3213 case OPTION_LOCK:
3214 case OPTION_SWAPE:
3215 case OPTION_RTSC:
4670103e
CZ		 3216 /* Dummy options are accepted but have no effect. */
3217 break;
886a2506 3218
8ddf6b2a
CZ		 3219 case OPTION_FPUDA:
3220 /* This option has an effect only on ARC EM. */
3221 if (arc_target & ARC_OPCODE_ARCv2EM)
3222 arc_features |= ARC_FPUDA;
3223 else
3224 as_warn (_("FPUDA invalid for selected CPU"));
3225 break;
3226
4670103e
CZ		 3227 default:
3228 return 0;
3229 }
886a2506 3230
4670103e
CZ		 3231 return 1;
3232}
886a2506 3233
4670103e
CZ		 3234void
3235md_show_usage (FILE *stream)
3236{
3237 fprintf (stream, _("ARC-specific assembler options:\n"));
886a2506 3238
4670103e
CZ		 3239 fprintf (stream, " -mcpu=<cpu name>\t assemble for CPU <cpu name>\n");
3240 fprintf (stream,
3241 " -mcode-density\t enable code density option for ARC EM\n");
3242
3243 fprintf (stream, _("\
3244 -EB assemble code for a big-endian cpu\n"));
3245 fprintf (stream, _("\
3246 -EL assemble code for a little-endian cpu\n"));
3247 fprintf (stream, _("\
3248 -mrelax Enable relaxation\n"));
886a2506 3249
886a2506
NC		 3250}
3251
3252/* Find the proper relocation for the given opcode. */
3253
3254static extended_bfd_reloc_code_real_type
3255find_reloc (const char *name,
3256 const char *opcodename,
3257 const struct arc_flags *pflags,
3258 int nflg,
3259 extended_bfd_reloc_code_real_type reloc)
3260{
3261 unsigned int i;
3262 int j;
24b368f8 3263 bfd_boolean found_flag, tmp;
886a2506
NC		 3264 extended_bfd_reloc_code_real_type ret = BFD_RELOC_UNUSED;
3265
3266 for (i = 0; i < arc_num_equiv_tab; i++)
3267 {
3268 const struct arc_reloc_equiv_tab *r = &arc_reloc_equiv[i];
3269
3270 /* Find the entry. */
3271 if (strcmp (name, r->name))
3272 continue;
3273 if (r->mnemonic && (strcmp (r->mnemonic, opcodename)))
3274 continue;
24b368f8 3275 if (r->flags[0])
886a2506
NC		 3276 {
3277 if (!nflg)
3278 continue;
3279 found_flag = FALSE;
24b368f8
CZ		 3280 unsigned * psflg = (unsigned *)r->flags;
3281 do
3282 {
3283 tmp = FALSE;
3284 for (j = 0; j < nflg; j++)
3285 if (!strcmp (pflags[j].name,
3286 arc_flag_operands[*psflg].name))
3287 {
3288 tmp = TRUE;
3289 break;
3290 }
3291 if (!tmp)
3292 {
3293 found_flag = FALSE;
3294 break;
3295 }
3296 else
3297 {
3298 found_flag = TRUE;
3299 }
3300 ++ psflg;
3301 } while (*psflg);
3302
886a2506
NC		 3303 if (!found_flag)
3304 continue;
3305 }
3306
3307 if (reloc != r->oldreloc)
3308 continue;
3309 /* Found it. */
3310 ret = r->newreloc;
3311 break;
3312 }
3313
3314 if (ret == BFD_RELOC_UNUSED)
3315 as_bad (_("Unable to find %s relocation for instruction %s"),
3316 name, opcodename);
3317 return ret;
3318}
3319
4670103e
CZ		 3320/* All the symbol types that are allowed to be used for
3321 relaxation. */
3322
3323static bfd_boolean
3324may_relax_expr (expressionS tok)
3325{
3326 /* Check if we have unrelaxable relocs. */
3327 switch (tok.X_md)
3328 {
3329 default:
3330 break;
3331 case O_plt:
3332 return FALSE;
3333 }
3334
3335 switch (tok.X_op)
3336 {
3337 case O_symbol:
3338 case O_multiply:
3339 case O_divide:
3340 case O_modulus:
3341 case O_add:
3342 case O_subtract:
3343 break;
3344
3345 default:
3346 return FALSE;
3347 }
3348 return TRUE;
3349}
3350
3351/* Checks if flags are in line with relaxable insn. */
3352
3353static bfd_boolean
3354relaxable_flag (const struct arc_relaxable_ins *ins,
3355 const struct arc_flags *pflags,
3356 int nflgs)
3357{
3358 unsigned flag_class,
3359 flag,
3360 flag_class_idx = 0,
3361 flag_idx = 0;
3362
3363 const struct arc_flag_operand *flag_opand;
3364 int i, counttrue = 0;
3365
3366 /* Iterate through flags classes. */
3367 while ((flag_class = ins->flag_classes[flag_class_idx]) != 0)
3368 {
3369 /* Iterate through flags in flag class. */
3370 while ((flag = arc_flag_classes[flag_class].flags[flag_idx])
3371 != 0)
3372 {
3373 flag_opand = &arc_flag_operands[flag];
3374 /* Iterate through flags in ins to compare. */
3375 for (i = 0; i < nflgs; ++i)
3376 {
3377 if (strcmp (flag_opand->name, pflags[i].name) == 0)
3378 ++counttrue;
3379 }
3380
3381 ++flag_idx;
3382 }
3383
3384 ++flag_class_idx;
3385 flag_idx = 0;
3386 }
3387
3388 /* If counttrue == nflgs, then all flags have been found. */
3389 return (counttrue == nflgs ? TRUE : FALSE);
3390}
3391
3392/* Checks if operands are in line with relaxable insn. */
3393
3394static bfd_boolean
3395relaxable_operand (const struct arc_relaxable_ins *ins,
3396 const expressionS *tok,
3397 int ntok)
3398{
3399 const enum rlx_operand_type *operand = &ins->operands[0];
3400 int i = 0;
3401
3402 while (*operand != EMPTY)
3403 {
3404 const expressionS *epr = &tok[i];
3405
3406 if (i != 0 && i >= ntok)
3407 return FALSE;
3408
3409 switch (*operand)
3410 {
3411 case IMMEDIATE:
3412 if (!(epr->X_op == O_multiply
3413 || epr->X_op == O_divide
3414 || epr->X_op == O_modulus
3415 || epr->X_op == O_add
3416 || epr->X_op == O_subtract
3417 || epr->X_op == O_symbol))
3418 return FALSE;
3419 break;
3420
3421 case REGISTER_DUP:
3422 if ((i <= 0)
3423 || (epr->X_add_number != tok[i - 1].X_add_number))
3424 return FALSE;
3425 /* Fall through. */
3426 case REGISTER:
3427 if (epr->X_op != O_register)
3428 return FALSE;
3429 break;
3430
3431 case REGISTER_S:
3432 if (epr->X_op != O_register)
3433 return FALSE;
3434
3435 switch (epr->X_add_number)
3436 {
3437 case 0: case 1: case 2: case 3:
3438 case 12: case 13: case 14: case 15:
3439 break;
3440 default:
3441 return FALSE;
3442 }
3443 break;
3444
3445 case REGISTER_NO_GP:
3446 if ((epr->X_op != O_register)
3447 || (epr->X_add_number == 26)) /* 26 is the gp register. */
3448 return FALSE;
3449 break;
3450
3451 case BRACKET:
3452 if (epr->X_op != O_bracket)
3453 return FALSE;
3454 break;
3455
3456 default:
3457 /* Don't understand, bail out. */
3458 return FALSE;
3459 break;
3460 }
3461
3462 ++i;
3463 operand = &ins->operands[i];
3464 }
3465
3466 return (i == ntok ? TRUE : FALSE);
3467}
3468
3469/* Return TRUE if this OPDCODE is a candidate for relaxation. */
3470
3471static bfd_boolean
3472relax_insn_p (const struct arc_opcode *opcode,
3473 const expressionS *tok,
3474 int ntok,
3475 const struct arc_flags *pflags,
3476 int nflg)
3477{
3478 unsigned i;
3479 bfd_boolean rv = FALSE;
3480
3481 /* Check the relaxation table. */
3482 for (i = 0; i < arc_num_relaxable_ins && relaxation_state; ++i)
3483 {
3484 const struct arc_relaxable_ins *arc_rlx_ins = &arc_relaxable_insns[i];
3485
3486 if ((strcmp (opcode->name, arc_rlx_ins->mnemonic_r) == 0)
3487 && may_relax_expr (tok[arc_rlx_ins->opcheckidx])
3488 && relaxable_operand (arc_rlx_ins, tok, ntok)
3489 && relaxable_flag (arc_rlx_ins, pflags, nflg))
3490 {
3491 rv = TRUE;
3492 frag_now->fr_subtype = arc_relaxable_insns[i].subtype;
3493 memcpy (&frag_now->tc_frag_data.tok, tok,
3494 sizeof (expressionS) * ntok);
3495 memcpy (&frag_now->tc_frag_data.pflags, pflags,
3496 sizeof (struct arc_flags) * nflg);
3497 frag_now->tc_frag_data.nflg = nflg;
3498 frag_now->tc_frag_data.ntok = ntok;
3499 break;
3500 }
3501 }
3502
3503 return rv;
3504}
3505
886a2506
NC		 3506/* Turn an opcode description and a set of arguments into
3507 an instruction and a fixup. */
3508
3509static void
3510assemble_insn (const struct arc_opcode *opcode,
3511 const expressionS *tok,
3512 int ntok,
3513 const struct arc_flags *pflags,
3514 int nflg,
3515 struct arc_insn *insn)
3516{
3517 const expressionS *reloc_exp = NULL;
3518 unsigned image;
3519 const unsigned char *argidx;
3520 int i;
3521 int tokidx = 0;
3522 unsigned char pcrel = 0;
3523 bfd_boolean needGOTSymbol;
3524 bfd_boolean has_delay_slot = FALSE;
3525 extended_bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED;
3526
3527 memset (insn, 0, sizeof (*insn));
3528 image = opcode->opcode;
3529
3530 pr_debug ("%s:%d: assemble_insn: %s using opcode %x\n",
3531 frag_now->fr_file, frag_now->fr_line, opcode->name,
3532 opcode->opcode);
3533
3534 /* Handle operands. */
3535 for (argidx = opcode->operands; *argidx; ++argidx)
3536 {
3537 const struct arc_operand *operand = &arc_operands[*argidx];
3538 const expressionS *t = (const expressionS *) 0;
3539
3540 if ((operand->flags & ARC_OPERAND_FAKE)
3541 && !(operand->flags & ARC_OPERAND_BRAKET))
3542 continue;
3543
3544 if (operand->flags & ARC_OPERAND_DUPLICATE)
3545 {
3546 /* Duplicate operand, already inserted. */
3547 tokidx ++;
3548 continue;
3549 }
3550
3551 if (tokidx >= ntok)
3552 {
3553 abort ();
3554 }
3555 else
3556 t = &tok[tokidx++];
3557
3558 /* Regardless if we have a reloc or not mark the instruction
3559 limm if it is the case. */
3560 if (operand->flags & ARC_OPERAND_LIMM)
3561 insn->has_limm = TRUE;
3562
3563 switch (t->X_op)
3564 {
3565 case O_register:
3566 image = insert_operand (image, operand, regno (t->X_add_number),
3567 NULL, 0);
3568 break;
3569
3570 case O_constant:
3571 image = insert_operand (image, operand, t->X_add_number, NULL, 0);
3572 reloc_exp = t;
3573 if (operand->flags & ARC_OPERAND_LIMM)
3574 insn->limm = t->X_add_number;
3575 break;
3576
3577 case O_bracket:
3578 /* Ignore brackets. */
3579 break;
3580
3581 case O_absent:
3582 gas_assert (operand->flags & ARC_OPERAND_IGNORE);
3583 break;
3584
3585 case O_subtract:
3586 /* Maybe register range. */
3587 if ((t->X_add_number == 0)
3588 && contains_register (t->X_add_symbol)
3589 && contains_register (t->X_op_symbol))
3590 {
3591 int regs;
3592
3593 regs = get_register (t->X_add_symbol);
3594 regs <<= 16;
3595 regs |= get_register (t->X_op_symbol);
3596 image = insert_operand (image, operand, regs, NULL, 0);
3597 break;
3598 }
3599
3600 default:
3601 /* This operand needs a relocation. */
3602 needGOTSymbol = FALSE;
3603
3604 switch (t->X_md)
3605 {
3606 case O_plt:
6ec1f282
CZ		 3607 if (opcode->class == JUMP)
3608 as_bad_where (frag_now->fr_file, frag_now->fr_line,
3609 _("Unable to use @plt relocatio for insn %s"),
3610 opcode->name);
886a2506
NC		 3611 needGOTSymbol = TRUE;
3612 reloc = find_reloc ("plt", opcode->name,
3613 pflags, nflg,
3614 operand->default_reloc);
3615 break;
3616
3617 case O_gotoff:
3618 case O_gotpc:
3619 needGOTSymbol = TRUE;
3620 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3621 break;
3622 case O_pcl:
3623 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
6ec1f282 3624 if (ARC_SHORT (opcode->mask) || opcode->class == JUMP)
886a2506
NC		 3625 as_bad_where (frag_now->fr_file, frag_now->fr_line,
3626 _("Unable to use @pcl relocation for insn %s"),
3627 opcode->name);
3628 break;
3629 case O_sda:
3630 reloc = find_reloc ("sda", opcode->name,
3631 pflags, nflg,
3632 operand->default_reloc);
3633 break;
3634 case O_tlsgd:
3635 case O_tlsie:
3636 needGOTSymbol = TRUE;
3637 /* Fall-through. */
3638
3639 case O_tpoff:
3640 case O_dtpoff:
3641 reloc = ARC_RELOC_TABLE (t->X_md)->reloc;
3642 break;
3643
3644 case O_tpoff9: /*FIXME! Check for the conditionality of
3645 the insn. */
3646 case O_dtpoff9: /*FIXME! Check for the conditionality of
3647 the insn. */
3648 as_bad (_("TLS_*_S9 relocs are not supported yet"));
3649 break;
3650
3651 default:
3652 /* Just consider the default relocation. */
3653 reloc = operand->default_reloc;
3654 break;
3655 }
3656
3657 if (needGOTSymbol && (GOT_symbol == NULL))
3658 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3659
3660 reloc_exp = t;
3661
3662#if 0
3663 if (reloc > 0)
3664 {
3665 /* sanity checks. */
3666 reloc_howto_type *reloc_howto
3667 = bfd_reloc_type_lookup (stdoutput,
3668 (bfd_reloc_code_real_type) reloc);
3669 unsigned reloc_bitsize = reloc_howto->bitsize;
3670 if (reloc_howto->rightshift)
3671 reloc_bitsize -= reloc_howto->rightshift;
3672 if (reloc_bitsize != operand->bits)
3673 {
3674 as_bad (_("invalid relocation %s for field"),
3675 bfd_get_reloc_code_name (reloc));
3676 return;
3677 }
3678 }
3679#endif
3680 if (insn->nfixups >= MAX_INSN_FIXUPS)
3681 as_fatal (_("too many fixups"));
3682
3683 struct arc_fixup *fixup;
3684 fixup = &insn->fixups[insn->nfixups++];
3685 fixup->exp = *t;
3686 fixup->reloc = reloc;
3687 pcrel = (operand->flags & ARC_OPERAND_PCREL) ? 1 : 0;
3688 fixup->pcrel = pcrel;
3689 fixup->islong = (operand->flags & ARC_OPERAND_LIMM) ?
3690 TRUE : FALSE;
3691 break;
3692 }
3693 }
3694
3695 /* Handle flags. */
3696 for (i = 0; i < nflg; i++)
3697 {
f36e33da 3698 const struct arc_flag_operand *flg_operand = pflags[i].flgp;
886a2506
NC		 3699
3700 /* Check if the instruction has a delay slot. */
3701 if (!strcmp (flg_operand->name, "d"))
3702 has_delay_slot = TRUE;
3703
3704 /* There is an exceptional case when we cannot insert a flag
3705 just as it is. The .T flag must be handled in relation with
3706 the relative address. */
3707 if (!strcmp (flg_operand->name, "t")
3708 || !strcmp (flg_operand->name, "nt"))
3709 {
3710 unsigned bitYoperand = 0;
3711 /* FIXME! move selection bbit/brcc in arc-opc.c. */
3712 if (!strcmp (flg_operand->name, "t"))
3713 if (!strcmp (opcode->name, "bbit0")
3714 || !strcmp (opcode->name, "bbit1"))
3715 bitYoperand = arc_NToperand;
3716 else
3717 bitYoperand = arc_Toperand;
3718 else
3719 if (!strcmp (opcode->name, "bbit0")
3720 || !strcmp (opcode->name, "bbit1"))
3721 bitYoperand = arc_Toperand;
3722 else
3723 bitYoperand = arc_NToperand;
3724
3725 gas_assert (reloc_exp != NULL);
3726 if (reloc_exp->X_op == O_constant)
3727 {
3728 /* Check if we have a constant and solved it
3729 immediately. */
3730 offsetT val = reloc_exp->X_add_number;
3731 image |= insert_operand (image, &arc_operands[bitYoperand],
3732 val, NULL, 0);
3733 }
3734 else
3735 {
3736 struct arc_fixup *fixup;
3737
3738 if (insn->nfixups >= MAX_INSN_FIXUPS)
3739 as_fatal (_("too many fixups"));
3740
3741 fixup = &insn->fixups[insn->nfixups++];
3742 fixup->exp = *reloc_exp;
3743 fixup->reloc = -bitYoperand;
3744 fixup->pcrel = pcrel;
3745 fixup->islong = FALSE;
3746 }
3747 }
3748 else
3749 image |= (flg_operand->code & ((1 << flg_operand->bits) - 1))
3750 << flg_operand->shift;
3751 }
3752
4670103e
CZ		 3753 insn->relax = relax_insn_p (opcode, tok, ntok, pflags, nflg);
3754
886a2506
NC		 3755 /* Short instruction? */
3756 insn->short_insn = ARC_SHORT (opcode->mask) ? TRUE : FALSE;
3757
3758 insn->insn = image;
3759
3760 /* Update last insn status. */
3761 arc_last_insns[1] = arc_last_insns[0];
3762 arc_last_insns[0].opcode = opcode;
3763 arc_last_insns[0].has_limm = insn->has_limm;
3764 arc_last_insns[0].has_delay_slot = has_delay_slot;
3765
3766 /* Check if the current instruction is legally used. */
3767 if (arc_last_insns[1].has_delay_slot
3768 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
3769 as_bad_where (frag_now->fr_file, frag_now->fr_line,
3770 _("A jump/branch instruction in delay slot."));
3771}
3772
886a2506
NC		 3773void
3774arc_handle_align (fragS* fragP)
3775{
3776 if ((fragP)->fr_type == rs_align_code)
3777 {
3778 char *dest = (fragP)->fr_literal + (fragP)->fr_fix;
3779 valueT count = ((fragP)->fr_next->fr_address
3780 - (fragP)->fr_address - (fragP)->fr_fix);
3781
3782 (fragP)->fr_var = 2;
3783
3784 if (count & 1)/* Padding in the gap till the next 2-byte
3785 boundary with 0s. */
3786 {
3787 (fragP)->fr_fix++;
3788 *dest++ = 0;
3789 }
3790 /* Writing nop_s. */
3791 md_number_to_chars (dest, NOP_OPCODE_S, 2);
3792 }
3793}
3794
3795/* Here we decide which fixups can be adjusted to make them relative
3796 to the beginning of the section instead of the symbol. Basically
3797 we need to make sure that the dynamic relocations are done
3798 correctly, so in some cases we force the original symbol to be
3799 used. */
3800
3801int
3802tc_arc_fix_adjustable (fixS *fixP)
3803{
3804
3805 /* Prevent all adjustments to global symbols. */
3806 if (S_IS_EXTERNAL (fixP->fx_addsy))
3807 return 0;
3808 if (S_IS_WEAK (fixP->fx_addsy))
3809 return 0;
3810
3811 /* Adjust_reloc_syms doesn't know about the GOT. */
3812 switch (fixP->fx_r_type)
3813 {
3814 case BFD_RELOC_ARC_GOTPC32:
3815 case BFD_RELOC_ARC_PLT32:
3816 case BFD_RELOC_ARC_S25H_PCREL_PLT:
3817 case BFD_RELOC_ARC_S21H_PCREL_PLT:
3818 case BFD_RELOC_ARC_S25W_PCREL_PLT:
3819 case BFD_RELOC_ARC_S21W_PCREL_PLT:
3820 return 0;
3821
3822 default:
3823 break;
3824 }
3825
841fdfcd 3826 return 1;
886a2506
NC		 3827}
3828
3829/* Compute the reloc type of an expression EXP. */
3830
3831static void
3832arc_check_reloc (expressionS *exp,
3833 bfd_reloc_code_real_type *r_type_p)
3834{
3835 if (*r_type_p == BFD_RELOC_32
3836 && exp->X_op == O_subtract
3837 && exp->X_op_symbol != NULL
3838 && exp->X_op_symbol->bsym->section == now_seg)
6f4b1afc 3839 *r_type_p = BFD_RELOC_ARC_32_PCREL;
886a2506
NC		 3840}
3841
3842
3843/* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */
3844
3845void
3846arc_cons_fix_new (fragS *frag,
3847 int off,
3848 int size,
3849 expressionS *exp,
3850 bfd_reloc_code_real_type r_type)
3851{
3852 r_type = BFD_RELOC_UNUSED;
3853
3854 switch (size)
3855 {
3856 case 1:
3857 r_type = BFD_RELOC_8;
3858 break;
3859
3860 case 2:
3861 r_type = BFD_RELOC_16;
3862 break;
3863
3864 case 3:
3865 r_type = BFD_RELOC_24;
3866 break;
3867
3868 case 4:
3869 r_type = BFD_RELOC_32;
3870 arc_check_reloc (exp, &r_type);
3871 break;
3872
3873 case 8:
3874 r_type = BFD_RELOC_64;
3875 break;
3876
3877 default:
3878 as_bad (_("unsupported BFD relocation size %u"), size);
3879 r_type = BFD_RELOC_UNUSED;
3880 }
3881
3882 fix_new_exp (frag, off, size, exp, 0, r_type);
3883}
3884
3885/* The actual routine that checks the ZOL conditions. */
3886
3887static void
3888check_zol (symbolS *s)
3889{
3890 switch (arc_mach_type)
3891 {
3892 case bfd_mach_arc_arcv2:
3893 if (arc_target & ARC_OPCODE_ARCv2EM)
3894 return;
3895
3896 if (is_br_jmp_insn_p (arc_last_insns[0].opcode)
3897 || arc_last_insns[1].has_delay_slot)
3898 as_bad (_("Jump/Branch instruction detected at the end of the ZOL label @%s"),
3899 S_GET_NAME (s));
3900
3901 break;
3902 case bfd_mach_arc_arc600:
3903
3904 if (is_kernel_insn_p (arc_last_insns[0].opcode))
3905 as_bad (_("Kernel instruction detected at the end of the ZOL label @%s"),
3906 S_GET_NAME (s));
3907
3908 if (arc_last_insns[0].has_limm
3909 && is_br_jmp_insn_p (arc_last_insns[0].opcode))
3910 as_bad (_("A jump instruction with long immediate detected at the \
3911end of the ZOL label @%s"), S_GET_NAME (s));
3912
3913 /* Fall through. */
8699fc3e 3914 case bfd_mach_arc_nps400:
886a2506
NC		 3915 case bfd_mach_arc_arc700:
3916 if (arc_last_insns[0].has_delay_slot)
3917 as_bad (_("An illegal use of delay slot detected at the end of the ZOL label @%s"),
3918 S_GET_NAME (s));
3919
3920 break;
3921 default:
3922 break;
3923 }
3924}
3925
3926/* If ZOL end check the last two instruction for illegals. */
3927void
3928arc_frob_label (symbolS * sym)
3929{
3930 if (ARC_GET_FLAG (sym) & ARC_FLAG_ZOL)
3931 check_zol (sym);
3932
3933 dwarf2_emit_label (sym);
ea1562b3 3934}
4670103e
CZ		 3935
3936/* Used because generic relaxation assumes a pc-rel value whilst we
3937 also relax instructions that use an absolute value resolved out of
3938 relative values (if that makes any sense). An example: 'add r1,
3939 r2, @.L2 - .' The symbols . and @.L2 are relative to the section
3940 but if they're in the same section we can subtract the section
3941 offset relocation which ends up in a resolved value. So if @.L2 is
3942 .text + 0x50 and . is .text + 0x10, we can say that .text + 0x50 -
3943 .text + 0x40 = 0x10. */
3944int
3945arc_pcrel_adjust (fragS *fragP)
3946{
3947 if (!fragP->tc_frag_data.pcrel)
3948 return fragP->fr_address + fragP->fr_fix;
3949
3950 return 0;
3951}
726c18e1
CZ		 3952
3953/* Initialize the DWARF-2 unwind information for this procedure. */
3954
3955void
3956tc_arc_frame_initial_instructions (void)
3957{
3958 /* Stack pointer is register 28. */
3959 cfi_add_CFA_def_cfa_register (28);
3960}
3961
3962int
3963tc_arc_regname_to_dw2regnum (char *regname)
3964{
3965 struct symbol *sym;
3966
3967 sym = hash_find (arc_reg_hash, regname);
3968 if (sym)
3969 return S_GET_VALUE (sym);
3970
3971 return -1;
3972}
37ab9779
CZ		 3973
3974/* Adjust the symbol table. Delete found AUX register symbols. */
3975
3976void
3977arc_adjust_symtab (void)
3978{
3979 symbolS * sym;
3980
3981 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
3982 {
3983 /* I've created a symbol during parsing process. Now, remove
3984 the symbol as it is found to be an AUX register. */
3985 if (ARC_GET_FLAG (sym) & ARC_FLAG_AUX)
3986 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
3987 }
3988
3989 /* Now do generic ELF adjustments. */
3990 elf_adjust_symtab ();
3991}
b99747ae
CZ		 3992
3993static void
3994tokenize_extinsn (extInstruction_t *einsn)
3995{
3996 char *p, c;
3997 char *insn_name;
3998 unsigned char major_opcode;
3999 unsigned char sub_opcode;
4000 unsigned char syntax_class = 0;
4001 unsigned char syntax_class_modifiers = 0;
4002 unsigned char suffix_class = 0;
4003 unsigned int i;
4004
4005 SKIP_WHITESPACE ();
4006
4007 /* 1st: get instruction name. */
4008 p = input_line_pointer;
4009 c = get_symbol_name (&p);
4010
4011 insn_name = xstrdup (p);
4012 restore_line_pointer (c);
4013
4014 /* 2nd: get major opcode. */
4015 if (*input_line_pointer != ',')
4016 {
4017 as_bad (_("expected comma after instruction name"));
4018 ignore_rest_of_line ();
4019 return;
4020 }
4021 input_line_pointer++;
4022 major_opcode = get_absolute_expression ();
4023
4024 /* 3rd: get sub-opcode. */
4025 SKIP_WHITESPACE ();
4026
4027 if (*input_line_pointer != ',')
4028 {
4029 as_bad (_("expected comma after major opcode"));
4030 ignore_rest_of_line ();
4031 return;
4032 }
4033 input_line_pointer++;
4034 sub_opcode = get_absolute_expression ();
4035
4036 /* 4th: get suffix class. */
4037 SKIP_WHITESPACE ();
4038
4039 if (*input_line_pointer != ',')
4040 {
4041 as_bad ("expected comma after sub opcode");
4042 ignore_rest_of_line ();
4043 return;
4044 }
4045 input_line_pointer++;
4046
4047 while (1)
4048 {
4049 SKIP_WHITESPACE ();
4050
4051 for (i = 0; i < ARRAY_SIZE (suffixclass); i++)
4052 {
4053 if (!strncmp (suffixclass[i].name, input_line_pointer,
4054 suffixclass[i].len))
4055 {
4056 suffix_class |= suffixclass[i].class;
4057 input_line_pointer += suffixclass[i].len;
4058 break;
4059 }
4060 }
4061
4062 if (i == ARRAY_SIZE (suffixclass))
4063 {
4064 as_bad ("invalid suffix class");
4065 ignore_rest_of_line ();
4066 return;
4067 }
4068
4069 SKIP_WHITESPACE ();
4070
4071 if (*input_line_pointer == '|')
4072 input_line_pointer++;
4073 else
4074 break;
4075 }
4076
4077 /* 5th: get syntax class and syntax class modifiers. */
4078 if (*input_line_pointer != ',')
4079 {
4080 as_bad ("expected comma after suffix class");
4081 ignore_rest_of_line ();
4082 return;
4083 }
4084 input_line_pointer++;
4085
4086 while (1)
4087 {
4088 SKIP_WHITESPACE ();
4089
4090 for (i = 0; i < ARRAY_SIZE (syntaxclassmod); i++)
4091 {
4092 if (!strncmp (syntaxclassmod[i].name,
4093 input_line_pointer,
4094 syntaxclassmod[i].len))
4095 {
4096 syntax_class_modifiers |= syntaxclassmod[i].class;
4097 input_line_pointer += syntaxclassmod[i].len;
4098 break;
4099 }
4100 }
4101
4102 if (i == ARRAY_SIZE (syntaxclassmod))
4103 {
4104 for (i = 0; i < ARRAY_SIZE (syntaxclass); i++)
4105 {
4106 if (!strncmp (syntaxclass[i].name,
4107 input_line_pointer,
4108 syntaxclass[i].len))
4109 {
4110 syntax_class |= syntaxclass[i].class;
4111 input_line_pointer += syntaxclass[i].len;
4112 break;
4113 }
4114 }
4115
4116 if (i == ARRAY_SIZE (syntaxclass))
4117 {
4118 as_bad ("missing syntax class");
4119 ignore_rest_of_line ();
4120 return;
4121 }
4122 }
4123
4124 SKIP_WHITESPACE ();
4125
4126 if (*input_line_pointer == '|')
4127 input_line_pointer++;
4128 else
4129 break;
4130 }
4131
4132 demand_empty_rest_of_line ();
4133
4134 einsn->name = insn_name;
4135 einsn->major = major_opcode;
4136 einsn->minor = sub_opcode;
4137 einsn->syntax = syntax_class;
4138 einsn->modsyn = syntax_class_modifiers;
4139 einsn->suffix = suffix_class;
4140 einsn->flags = syntax_class
4141 | (syntax_class_modifiers & ARC_OP1_IMM_IMPLIED ? 0x10 : 0);
4142}
4143
4144/* Generate an extension section. */
4145
4146static int
4147arc_set_ext_seg (void)
4148{
4149 if (!arcext_section)
4150 {
4151 arcext_section = subseg_new (".arcextmap", 0);
4152 bfd_set_section_flags (stdoutput, arcext_section,
4153 SEC_READONLY | SEC_HAS_CONTENTS);
4154 }
4155 else
4156 subseg_set (arcext_section, 0);
4157 return 1;
4158}
4159
4160/* Create an extension instruction description in the arc extension
4161 section of the output file.
4162 The structure for an instruction is like this:
4163 [0]: Length of the record.
4164 [1]: Type of the record.
4165
4166 [2]: Major opcode.
4167 [3]: Sub-opcode.
4168 [4]: Syntax (flags).
4169 [5]+ Name instruction.
4170
4171 The sequence is terminated by an empty entry. */
4172
4173static void
4174create_extinst_section (extInstruction_t *einsn)
4175{
4176
4177 segT old_sec = now_seg;
4178 int old_subsec = now_subseg;
4179 char *p;
4180 int name_len = strlen (einsn->name);
4181
4182 arc_set_ext_seg ();
4183
4184 p = frag_more (1);
4185 *p = 5 + name_len + 1;
4186 p = frag_more (1);
4187 *p = EXT_INSTRUCTION;
4188 p = frag_more (1);
4189 *p = einsn->major;
4190 p = frag_more (1);
4191 *p = einsn->minor;
4192 p = frag_more (1);
4193 *p = einsn->flags;
4194 p = frag_more (name_len + 1);
4195 strcpy (p, einsn->name);
4196
4197 subseg_set (old_sec, old_subsec);
4198}
4199
4200/* Handler .extinstruction pseudo-op. */
4201
4202static void
4203arc_extinsn (int ignore ATTRIBUTE_UNUSED)
4204{
4205 extInstruction_t einsn;
4206 struct arc_opcode *arc_ext_opcodes;
4207 const char *errmsg = NULL;
4208 unsigned char moplow, mophigh;
4209
4210 memset (&einsn, 0, sizeof (einsn));
4211 tokenize_extinsn (&einsn);
4212
4213 /* Check if the name is already used. */
4214 if (arc_find_opcode (einsn.name))
4215 as_warn (_("Pseudocode already used %s"), einsn.name);
4216
4217 /* Check the opcode ranges. */
4218 moplow = 0x05;
4219 mophigh = (arc_target & (ARC_OPCODE_ARCv2EM
4220 | ARC_OPCODE_ARCv2HS)) ? 0x07 : 0x0a;
4221
4222 if ((einsn.major > mophigh) || (einsn.major < moplow))
4223 as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow, mophigh);
4224
4225 if ((einsn.minor > 0x3f) && (einsn.major != 0x0a)
4226 && (einsn.major != 5) && (einsn.major != 9))
4227 as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
4228
4229 switch (einsn.syntax & (ARC_SYNTAX_3OP | ARC_SYNTAX_2OP))
4230 {
4231 case ARC_SYNTAX_3OP:
4232 if (einsn.modsyn & ARC_OP1_IMM_IMPLIED)
4233 as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
4234 break;
4235 case ARC_SYNTAX_2OP:
4236 if (einsn.modsyn & ARC_OP1_MUST_BE_IMM)
4237 as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
4238 break;
4239 default:
4240 break;
4241 }
4242
4243 arc_ext_opcodes = arcExtMap_genOpcode (&einsn, arc_target, &errmsg);
4244 if (arc_ext_opcodes == NULL)
4245 {
4246 if (errmsg)
4247 as_fatal ("%s", errmsg);
4248 else
4249 as_fatal (_("Couldn't generate extension instruction opcodes"));
4250 }
4251 else if (errmsg)
4252 as_warn ("%s", errmsg);
4253
4254 /* Insert the extension instruction. */
4255 arc_insert_opcode ((const struct arc_opcode *) arc_ext_opcodes);
4256
4257 create_extinst_section (&einsn);
4258}
4259
f36e33da
CZ		 4260static void
4261tokenize_extregister (extRegister_t *ereg, int opertype)
4262{
4263 char *name;
4264 char *mode;
4265 char c;
4266 char *p;
4267 int number, imode = 0;
4268 bfd_boolean isCore_p = (opertype == EXT_CORE_REGISTER) ? TRUE : FALSE;
4269 bfd_boolean isReg_p = (opertype == EXT_CORE_REGISTER
4270 || opertype == EXT_AUX_REGISTER) ? TRUE : FALSE;
4271
4272 /* 1st: get register name. */
4273 SKIP_WHITESPACE ();
4274 p = input_line_pointer;
4275 c = get_symbol_name (&p);
4276
4277 name = xstrdup (p);
4278 restore_line_pointer (c);
4279
4280 /* 2nd: get register number. */
4281 SKIP_WHITESPACE ();
4282
4283 if (*input_line_pointer != ',')
4284 {
4285 as_bad (_("expected comma after register name"));
4286 ignore_rest_of_line ();
4287 free (name);
4288 return;
4289 }
4290 input_line_pointer++;
4291 number = get_absolute_expression ();
4292
4293 if (number < 0)
4294 {
4295 as_bad (_("negative operand number %d"), number);
4296 ignore_rest_of_line ();
4297 free (name);
4298 return;
4299 }
4300
4301 if (isReg_p)
4302 {
4303 /* 3rd: get register mode. */
4304 SKIP_WHITESPACE ();
4305
4306 if (*input_line_pointer != ',')
4307 {
4308 as_bad (_("expected comma after register number"));
4309 ignore_rest_of_line ();
4310 free (name);
4311 return;
4312 }
4313
4314 input_line_pointer++;
4315 mode = input_line_pointer;
4316
4317 if (!strncmp (mode, "r|w", 3))
4318 {
4319 imode = 0;
4320 input_line_pointer += 3;
4321 }
4322 else if (!strncmp (mode, "r", 1))
4323 {
4324 imode = ARC_REGISTER_READONLY;
4325 input_line_pointer += 1;
4326 }
4327 else if (strncmp (mode, "w", 1))
4328 {
4329 as_bad (_("invalid mode"));
4330 ignore_rest_of_line ();
4331 free (name);
4332 return;
4333 }
4334 else
4335 {
4336 imode = ARC_REGISTER_WRITEONLY;
4337 input_line_pointer += 1;
4338 }
4339 }
4340
4341 if (isCore_p)
4342 {
4343 /* 4th: get core register shortcut. */
4344 SKIP_WHITESPACE ();
4345 if (*input_line_pointer != ',')
4346 {
4347 as_bad (_("expected comma after register mode"));
4348 ignore_rest_of_line ();
4349 free (name);
4350 return;
4351 }
4352
4353 input_line_pointer++;
4354
4355 if (!strncmp (input_line_pointer, "cannot_shortcut", 15))
4356 {
4357 imode |= ARC_REGISTER_NOSHORT_CUT;
4358 input_line_pointer += 15;
4359 }
4360 else if (strncmp (input_line_pointer, "can_shortcut", 12))
4361 {
4362 as_bad (_("shortcut designator invalid"));
4363 ignore_rest_of_line ();
4364 free (name);
4365 return;
4366 }
4367 else
4368 {
4369 input_line_pointer += 12;
4370 }
4371 }
4372 demand_empty_rest_of_line ();
4373
4374 ereg->name = name;
4375 ereg->number = number;
4376 ereg->imode = imode;
4377}
4378
4379/* Create an extension register/condition description in the arc
4380 extension section of the output file.
4381
4382 The structure for an instruction is like this:
4383 [0]: Length of the record.
4384 [1]: Type of the record.
4385
4386 For core regs and condition codes:
4387 [2]: Value.
4388 [3]+ Name.
4389
4390 For auxilirary registers:
4391 [2..5]: Value.
4392 [6]+ Name
4393
4394 The sequence is terminated by an empty entry. */
4395
4396static void
4397create_extcore_section (extRegister_t *ereg, int opertype)
4398{
4399 segT old_sec = now_seg;
4400 int old_subsec = now_subseg;
4401 char *p;
4402 int name_len = strlen (ereg->name);
4403
4404 arc_set_ext_seg ();
4405
4406 switch (opertype)
4407 {
4408 case EXT_COND_CODE:
4409 case EXT_CORE_REGISTER:
4410 p = frag_more (1);
4411 *p = 3 + name_len + 1;
4412 p = frag_more (1);
4413 *p = opertype;
4414 p = frag_more (1);
4415 *p = ereg->number;
4416 break;
4417 case EXT_AUX_REGISTER:
4418 p = frag_more (1);
4419 *p = 6 + name_len + 1;
4420 p = frag_more (1);
4421 *p = EXT_AUX_REGISTER;
4422 p = frag_more (1);
4423 *p = (ereg->number >> 24) & 0xff;
4424 p = frag_more (1);
4425 *p = (ereg->number >> 16) & 0xff;
4426 p = frag_more (1);
4427 *p = (ereg->number >> 8) & 0xff;
4428 p = frag_more (1);
4429 *p = (ereg->number) & 0xff;
4430 break;
4431 default:
4432 break;
4433 }
4434
4435 p = frag_more (name_len + 1);
4436 strcpy (p, ereg->name);
4437
4438 subseg_set (old_sec, old_subsec);
4439}
4440
4441/* Handler .extCoreRegister pseudo-op. */
4442
4443static void
4444arc_extcorereg (int opertype)
4445{
4446 extRegister_t ereg;
4447 struct arc_aux_reg *auxr;
4448 const char *retval;
4449 struct arc_flag_operand *ccode;
4450
4451 memset (&ereg, 0, sizeof (ereg));
4452 tokenize_extregister (&ereg, opertype);
4453
4454 switch (opertype)
4455 {
4456 case EXT_CORE_REGISTER:
4457 /* Core register. */
4458 if (ereg.number > 60)
4459 as_bad (_("core register %s value (%d) too large"), ereg.name,
4460 ereg.number);
4461 declare_register (ereg.name, ereg.number);
4462 break;
4463 case EXT_AUX_REGISTER:
4464 /* Auxiliary register. */
4465 auxr = xmalloc (sizeof (struct arc_aux_reg));
4466 auxr->name = ereg.name;
4467 auxr->cpu = arc_target;
4468 auxr->subclass = NONE;
4469 auxr->address = ereg.number;
4470 retval = hash_insert (arc_aux_hash, auxr->name, (void *) auxr);
4471 if (retval)
4472 as_fatal (_("internal error: can't hash aux register '%s': %s"),
4473 auxr->name, retval);
4474 break;
4475 case EXT_COND_CODE:
4476 /* Condition code. */
4477 if (ereg.number > 31)
4478 as_bad (_("condition code %s value (%d) too large"), ereg.name,
4479 ereg.number);
4480 ext_condcode.size ++;
4481 ext_condcode.arc_ext_condcode =
4482 xrealloc (ext_condcode.arc_ext_condcode,
4483 (ext_condcode.size + 1) * sizeof (struct arc_flag_operand));
4484 if (ext_condcode.arc_ext_condcode == NULL)
4485 as_fatal (_("Virtual memory exhausted"));
4486
4487 ccode = ext_condcode.arc_ext_condcode + ext_condcode.size - 1;
4488 ccode->name = ereg.name;
4489 ccode->code = ereg.number;
4490 ccode->bits = 5;
4491 ccode->shift = 0;
4492 ccode->favail = 0; /* not used. */
4493 ccode++;
4494 memset (ccode, 0, sizeof (struct arc_flag_operand));
4495 break;
4496 default:
4497 as_bad (_("Unknown extension"));
4498 break;
4499 }
4500 create_extcore_section (&ereg, opertype);
4501}
4502
b99747ae
CZ		 4503/* Local variables:
4504 eval: (c-set-style "gnu")
4505 indent-tabs-mode: t
4506 End: */
GDB Binutils - Deliverables
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