projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Replace "if (x) free (x)" with "free (x)", gas
[deliverable/binutils-gdb.git] / gas / config / tc-arm.c
CommitLineData
b99bd4ef 1/* tc-arm.c -- Assemble for the ARM
b3adc24a 2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
b99bd4ef
NC		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
22d9c8c5 5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
34920d91
NC		 6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
b99bd4ef
NC		 8
9 This file is part of GAS, the GNU Assembler.
10
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
ec2655a6 13 the Free Software Foundation; either version 3, or (at your option)
b99bd4ef
NC		 14 any later version.
15
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
c19d1205 18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
b99bd4ef
NC		 19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
699d2810
NC		 23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 02110-1301, USA. */
b99bd4ef 25
42a68e18 26#include "as.h"
5287ad62 27#include <limits.h>
037e8744 28#include <stdarg.h>
c19d1205 29#define NO_RELOC 0
3882b010 30#include "safe-ctype.h"
b99bd4ef
NC		 31#include "subsegs.h"
32#include "obstack.h"
3da1d841 33#include "libiberty.h"
f263249b 34#include "opcode/arm.h"
f37164d7 35#include "cpu-arm.h"
f263249b 36
b99bd4ef
NC		 37#ifdef OBJ_ELF
38#include "elf/arm.h"
a394c00f 39#include "dw2gencfi.h"
b99bd4ef
NC		 40#endif
41
f0927246
NC		 42#include "dwarf2dbg.h"
43
7ed4c4c5
NC		 44#ifdef OBJ_ELF
45/* Must be at least the size of the largest unwind opcode (currently two). */
46#define ARM_OPCODE_CHUNK_SIZE 8
47
48/* This structure holds the unwinding state. */
49
50static struct
51{
c19d1205
ZW		 52 symbolS * proc_start;
53 symbolS * table_entry;
54 symbolS * personality_routine;
55 int personality_index;
7ed4c4c5 56 /* The segment containing the function. */
c19d1205
ZW		 57 segT saved_seg;
58 subsegT saved_subseg;
7ed4c4c5
NC		 59 /* Opcodes generated from this function. */
60 unsigned char * opcodes;
c19d1205
ZW		 61 int opcode_count;
62 int opcode_alloc;
7ed4c4c5 63 /* The number of bytes pushed to the stack. */
c19d1205 64 offsetT frame_size;
7ed4c4c5
NC		 65 /* We don't add stack adjustment opcodes immediately so that we can merge
66 multiple adjustments. We can also omit the final adjustment
67 when using a frame pointer. */
c19d1205 68 offsetT pending_offset;
7ed4c4c5 69 /* These two fields are set by both unwind_movsp and unwind_setfp. They
c19d1205
ZW		 70 hold the reg+offset to use when restoring sp from a frame pointer. */
71 offsetT fp_offset;
72 int fp_reg;
7ed4c4c5 73 /* Nonzero if an unwind_setfp directive has been seen. */
c19d1205 74 unsigned fp_used:1;
7ed4c4c5 75 /* Nonzero if the last opcode restores sp from fp_reg. */
c19d1205 76 unsigned sp_restored:1;
7ed4c4c5
NC		 77} unwind;
78
18a20338
CL		 79/* Whether --fdpic was given. */
80static int arm_fdpic;
81
8b1ad454
NC		 82#endif /* OBJ_ELF */
83
4962c51a
MS		 84/* Results from operand parsing worker functions. */
85
86typedef enum
87{
88 PARSE_OPERAND_SUCCESS,
89 PARSE_OPERAND_FAIL,
90 PARSE_OPERAND_FAIL_NO_BACKTRACK
91} parse_operand_result;
92
33a392fb
PB		 93enum arm_float_abi
94{
95 ARM_FLOAT_ABI_HARD,
96 ARM_FLOAT_ABI_SOFTFP,
97 ARM_FLOAT_ABI_SOFT
98};
99
c19d1205 100/* Types of processor to assemble for. */
b99bd4ef 101#ifndef CPU_DEFAULT
8a59fff3 102/* The code that was here used to select a default CPU depending on compiler
fa94de6b 103 pre-defines which were only present when doing native builds, thus
8a59fff3
MGD		 104 changing gas' default behaviour depending upon the build host.
105
106 If you have a target that requires a default CPU option then the you
107 should define CPU_DEFAULT here. */
b99bd4ef
NC		 108#endif
109
e8f8842d
TC		 110/* Perform range checks on positive and negative overflows by checking if the
111 VALUE given fits within the range of an BITS sized immediate. */
112static bfd_boolean out_of_range_p (offsetT value, offsetT bits)
113 {
114 gas_assert (bits < (offsetT)(sizeof (value) * 8));
115 return (value & ~((1 << bits)-1))
116 && ((value & ~((1 << bits)-1)) != ~((1 << bits)-1));
117}
118
b99bd4ef 119#ifndef FPU_DEFAULT
c820d418
MM		 120# ifdef TE_LINUX
121# define FPU_DEFAULT FPU_ARCH_FPA
122# elif defined (TE_NetBSD)
123# ifdef OBJ_ELF
124# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
125# else
126 /* Legacy a.out format. */
127# define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
128# endif
4e7fd91e
PB		 129# elif defined (TE_VXWORKS)
130# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
c820d418
MM		 131# else
132 /* For backwards compatibility, default to FPA. */
133# define FPU_DEFAULT FPU_ARCH_FPA
134# endif
135#endif /* ifndef FPU_DEFAULT */
b99bd4ef 136
c19d1205 137#define streq(a, b) (strcmp (a, b) == 0)
b99bd4ef 138
4d354d8b
TP		 139/* Current set of feature bits available (CPU+FPU). Different from
140 selected_cpu + selected_fpu in case of autodetection since the CPU
141 feature bits are then all set. */
e74cfd16 142static arm_feature_set cpu_variant;
4d354d8b
TP		 143/* Feature bits used in each execution state. Used to set build attribute
144 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
e74cfd16
PB		 145static arm_feature_set arm_arch_used;
146static arm_feature_set thumb_arch_used;
b99bd4ef 147
b99bd4ef 148/* Flags stored in private area of BFD structure. */
c19d1205
ZW		 149static int uses_apcs_26 = FALSE;
150static int atpcs = FALSE;
b34976b6
AM		 151static int support_interwork = FALSE;
152static int uses_apcs_float = FALSE;
c19d1205 153static int pic_code = FALSE;
845b51d6 154static int fix_v4bx = FALSE;
278df34e
NS		 155/* Warn on using deprecated features. */
156static int warn_on_deprecated = TRUE;
24f19ccb 157static int warn_on_restrict_it = FALSE;
278df34e 158
2e6976a8
DG		 159/* Understand CodeComposer Studio assembly syntax. */
160bfd_boolean codecomposer_syntax = FALSE;
03b1477f
RE		 161
162/* Variables that we set while parsing command-line options. Once all
163 options have been read we re-process these values to set the real
164 assembly flags. */
4d354d8b
TP		 165
166/* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
167 instead of -mcpu=arm1). */
168static const arm_feature_set *legacy_cpu = NULL;
169static const arm_feature_set *legacy_fpu = NULL;
170
171/* CPU, extension and FPU feature bits selected by -mcpu. */
172static const arm_feature_set *mcpu_cpu_opt = NULL;
173static arm_feature_set *mcpu_ext_opt = NULL;
174static const arm_feature_set *mcpu_fpu_opt = NULL;
175
176/* CPU, extension and FPU feature bits selected by -march. */
177static const arm_feature_set *march_cpu_opt = NULL;
178static arm_feature_set *march_ext_opt = NULL;
179static const arm_feature_set *march_fpu_opt = NULL;
180
181/* Feature bits selected by -mfpu. */
182static const arm_feature_set *mfpu_opt = NULL;
e74cfd16
PB		 183
184/* Constants for known architecture features. */
185static const arm_feature_set fpu_default = FPU_DEFAULT;
f85d59c3 186static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V1;
e74cfd16 187static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
f85d59c3
KT		 188static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V3;
189static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED = FPU_ARCH_NEON_V1;
e74cfd16
PB		 190static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
191static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
69c9e028 192#ifdef OBJ_ELF
e74cfd16 193static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
69c9e028 194#endif
e74cfd16
PB		 195static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
196
197#ifdef CPU_DEFAULT
198static const arm_feature_set cpu_default = CPU_DEFAULT;
199#endif
200
823d2571 201static const arm_feature_set arm_ext_v1 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1);
4070243b 202static const arm_feature_set arm_ext_v2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V2);
823d2571
TG		 203static const arm_feature_set arm_ext_v2s = ARM_FEATURE_CORE_LOW (ARM_EXT_V2S);
204static const arm_feature_set arm_ext_v3 = ARM_FEATURE_CORE_LOW (ARM_EXT_V3);
205static const arm_feature_set arm_ext_v3m = ARM_FEATURE_CORE_LOW (ARM_EXT_V3M);
206static const arm_feature_set arm_ext_v4 = ARM_FEATURE_CORE_LOW (ARM_EXT_V4);
207static const arm_feature_set arm_ext_v4t = ARM_FEATURE_CORE_LOW (ARM_EXT_V4T);
208static const arm_feature_set arm_ext_v5 = ARM_FEATURE_CORE_LOW (ARM_EXT_V5);
e74cfd16 209static const arm_feature_set arm_ext_v4t_5 =
823d2571
TG		 210 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5);
211static const arm_feature_set arm_ext_v5t = ARM_FEATURE_CORE_LOW (ARM_EXT_V5T);
212static const arm_feature_set arm_ext_v5e = ARM_FEATURE_CORE_LOW (ARM_EXT_V5E);
213static const arm_feature_set arm_ext_v5exp = ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP);
214static const arm_feature_set arm_ext_v5j = ARM_FEATURE_CORE_LOW (ARM_EXT_V5J);
215static const arm_feature_set arm_ext_v6 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
216static const arm_feature_set arm_ext_v6k = ARM_FEATURE_CORE_LOW (ARM_EXT_V6K);
217static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2);
55e8aae7
SP		 218/* Only for compatability of hint instructions. */
219static const arm_feature_set arm_ext_v6k_v6t2 =
220 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K | ARM_EXT_V6T2);
823d2571
TG		 221static const arm_feature_set arm_ext_v6_notm =
222 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM);
223static const arm_feature_set arm_ext_v6_dsp =
224 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP);
225static const arm_feature_set arm_ext_barrier =
226 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER);
227static const arm_feature_set arm_ext_msr =
228 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR);
229static const arm_feature_set arm_ext_div = ARM_FEATURE_CORE_LOW (ARM_EXT_DIV);
230static const arm_feature_set arm_ext_v7 = ARM_FEATURE_CORE_LOW (ARM_EXT_V7);
231static const arm_feature_set arm_ext_v7a = ARM_FEATURE_CORE_LOW (ARM_EXT_V7A);
232static const arm_feature_set arm_ext_v7r = ARM_FEATURE_CORE_LOW (ARM_EXT_V7R);
164446e0 233static const arm_feature_set arm_ext_v8r = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R);
69c9e028 234#ifdef OBJ_ELF
e7d39ed3 235static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M);
69c9e028 236#endif
823d2571 237static const arm_feature_set arm_ext_v8 = ARM_FEATURE_CORE_LOW (ARM_EXT_V8);
7e806470 238static const arm_feature_set arm_ext_m =
173205ca 239 ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_V7M,
16a1fa25 240 ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
823d2571
TG		 241static const arm_feature_set arm_ext_mp = ARM_FEATURE_CORE_LOW (ARM_EXT_MP);
242static const arm_feature_set arm_ext_sec = ARM_FEATURE_CORE_LOW (ARM_EXT_SEC);
243static const arm_feature_set arm_ext_os = ARM_FEATURE_CORE_LOW (ARM_EXT_OS);
244static const arm_feature_set arm_ext_adiv = ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV);
245static const arm_feature_set arm_ext_virt = ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT);
ddfded2f 246static const arm_feature_set arm_ext_pan = ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN);
4ed7ed8d 247static const arm_feature_set arm_ext_v8m = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M);
16a1fa25
TP		 248static const arm_feature_set arm_ext_v8m_main =
249 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN);
e12437dc
AV		 250static const arm_feature_set arm_ext_v8_1m_main =
251ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
16a1fa25
TP		 252/* Instructions in ARMv8-M only found in M profile architectures. */
253static const arm_feature_set arm_ext_v8m_m_only =
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
ff8646ee
TP		 255static const arm_feature_set arm_ext_v6t2_v8m =
256 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M);
4ed7ed8d
TP		 257/* Instructions shared between ARMv8-A and ARMv8-M. */
258static const arm_feature_set arm_ext_atomics =
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS);
69c9e028 260#ifdef OBJ_ELF
15afaa63
TP		 261/* DSP instructions Tag_DSP_extension refers to. */
262static const arm_feature_set arm_ext_dsp =
263 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E | ARM_EXT_V5ExP | ARM_EXT_V6_DSP);
69c9e028 264#endif
4d1464f2
MW		 265static const arm_feature_set arm_ext_ras =
266 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS);
b8ec4e87
JW		 267/* FP16 instructions. */
268static const arm_feature_set arm_ext_fp16 =
269 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
01f48020
TC		 270static const arm_feature_set arm_ext_fp16_fml =
271 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML);
dec41383
JW		 272static const arm_feature_set arm_ext_v8_2 =
273 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A);
49e8a725
SN		 274static const arm_feature_set arm_ext_v8_3 =
275 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A);
7fadb25d
SD		 276static const arm_feature_set arm_ext_sb =
277 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB);
dad0c3bf
SD		 278static const arm_feature_set arm_ext_predres =
279 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES);
aab2c27d
MM		 280static const arm_feature_set arm_ext_bf16 =
281 ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16);
616ce08e
MM		 282static const arm_feature_set arm_ext_i8mm =
283 ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM);
8b301fbb
MI		 284static const arm_feature_set arm_ext_crc =
285 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC);
4934a27c
MM		 286static const arm_feature_set arm_ext_cde =
287 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE);
288static const arm_feature_set arm_ext_cde0 =
289 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE0);
290static const arm_feature_set arm_ext_cde1 =
291 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE1);
292static const arm_feature_set arm_ext_cde2 =
293 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE2);
294static const arm_feature_set arm_ext_cde3 =
295 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE3);
296static const arm_feature_set arm_ext_cde4 =
297 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE4);
298static const arm_feature_set arm_ext_cde5 =
299 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE5);
300static const arm_feature_set arm_ext_cde6 =
301 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE6);
302static const arm_feature_set arm_ext_cde7 =
303 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE7);
e74cfd16
PB		 304
305static const arm_feature_set arm_arch_any = ARM_ANY;
2c6b98ea 306static const arm_feature_set fpu_any = FPU_ANY;
f85d59c3 307static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED = ARM_FEATURE (-1, -1, -1);
e74cfd16
PB		 308static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
309static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
310
2d447fca 311static const arm_feature_set arm_cext_iwmmxt2 =
823d2571 312 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2);
e74cfd16 313static const arm_feature_set arm_cext_iwmmxt =
823d2571 314 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT);
e74cfd16 315static const arm_feature_set arm_cext_xscale =
823d2571 316 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE);
e74cfd16 317static const arm_feature_set arm_cext_maverick =
823d2571
TG		 318 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK);
319static const arm_feature_set fpu_fpa_ext_v1 =
320 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1);
321static const arm_feature_set fpu_fpa_ext_v2 =
322 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2);
e74cfd16 323static const arm_feature_set fpu_vfp_ext_v1xd =
823d2571
TG		 324 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD);
325static const arm_feature_set fpu_vfp_ext_v1 =
326 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1);
327static const arm_feature_set fpu_vfp_ext_v2 =
328 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2);
329static const arm_feature_set fpu_vfp_ext_v3xd =
330 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD);
331static const arm_feature_set fpu_vfp_ext_v3 =
332 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3);
b1cc4aeb 333static const arm_feature_set fpu_vfp_ext_d32 =
823d2571
TG		 334 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32);
335static const arm_feature_set fpu_neon_ext_v1 =
336 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1);
5287ad62 337static const arm_feature_set fpu_vfp_v3_or_neon_ext =
823d2571 338 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
a7ad558c 339static const arm_feature_set mve_ext =
2da2eaf4 340 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE);
a7ad558c 341static const arm_feature_set mve_fp_ext =
2da2eaf4 342 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP);
5aae9ae9
MM		 343/* Note: This has more than one bit set, which means using it with
344 mark_feature_used (which returns if *any* of the bits are set in the current
345 cpu variant) can give surprising results. */
346static const arm_feature_set armv8m_fp =
347 ARM_FEATURE_COPROC (FPU_VFP_V5_SP_D16);
69c9e028 348#ifdef OBJ_ELF
823d2571
TG		 349static const arm_feature_set fpu_vfp_fp16 =
350 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16);
351static const arm_feature_set fpu_neon_ext_fma =
352 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA);
69c9e028 353#endif
823d2571
TG		 354static const arm_feature_set fpu_vfp_ext_fma =
355 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA);
bca38921 356static const arm_feature_set fpu_vfp_ext_armv8 =
823d2571 357 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8);
a715796b 358static const arm_feature_set fpu_vfp_ext_armv8xd =
823d2571 359 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD);
bca38921 360static const arm_feature_set fpu_neon_ext_armv8 =
823d2571 361 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8);
bca38921 362static const arm_feature_set fpu_crypto_ext_armv8 =
823d2571 363 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8);
d6b4b13e 364static const arm_feature_set fpu_neon_ext_v8_1 =
643afb90 365 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA);
c604a79a
JW		 366static const arm_feature_set fpu_neon_ext_dotprod =
367 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD);
e74cfd16 368
33a392fb 369static int mfloat_abi_opt = -1;
4d354d8b
TP		 370/* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
371 directive. */
372static arm_feature_set selected_arch = ARM_ARCH_NONE;
373/* Extension feature bits selected by the last -mcpu/-march or .arch_extension
374 directive. */
375static arm_feature_set selected_ext = ARM_ARCH_NONE;
376/* Feature bits selected by the last -mcpu/-march or by the combination of the
377 last .cpu/.arch directive .arch_extension directives since that
378 directive. */
e74cfd16 379static arm_feature_set selected_cpu = ARM_ARCH_NONE;
4d354d8b
TP		 380/* FPU feature bits selected by the last -mfpu or .fpu directive. */
381static arm_feature_set selected_fpu = FPU_NONE;
382/* Feature bits selected by the last .object_arch directive. */
383static arm_feature_set selected_object_arch = ARM_ARCH_NONE;
ee065d83 384/* Must be long enough to hold any of the names in arm_cpus. */
e20f9590 385static const struct arm_ext_table * selected_ctx_ext_table = NULL;
ef8e6722 386static char selected_cpu_name[20];
8d67f500 387
aacf0b33
KT		 388extern FLONUM_TYPE generic_floating_point_number;
389
8d67f500
NC		 390/* Return if no cpu was selected on command-line. */
391static bfd_boolean
392no_cpu_selected (void)
393{
823d2571 394 return ARM_FEATURE_EQUAL (selected_cpu, arm_arch_none);
8d67f500
NC		 395}
396
7cc69913 397#ifdef OBJ_ELF
deeaaff8
DJ		 398# ifdef EABI_DEFAULT
399static int meabi_flags = EABI_DEFAULT;
400# else
d507cf36 401static int meabi_flags = EF_ARM_EABI_UNKNOWN;
deeaaff8 402# endif
e1da3f5b 403
ee3c0378
AS		 404static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
405
e1da3f5b 406bfd_boolean
5f4273c7 407arm_is_eabi (void)
e1da3f5b
PB		 408{
409 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
410}
7cc69913 411#endif
b99bd4ef 412
b99bd4ef 413#ifdef OBJ_ELF
c19d1205 414/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
b99bd4ef
NC		 415symbolS * GOT_symbol;
416#endif
417
b99bd4ef
NC		 418/* 0: assemble for ARM,
419 1: assemble for Thumb,
420 2: assemble for Thumb even though target CPU does not support thumb
421 instructions. */
422static int thumb_mode = 0;
8dc2430f
NC		 423/* A value distinct from the possible values for thumb_mode that we
424 can use to record whether thumb_mode has been copied into the
425 tc_frag_data field of a frag. */
426#define MODE_RECORDED (1 << 4)
b99bd4ef 427
e07e6e58
NC		 428/* Specifies the intrinsic IT insn behavior mode. */
429enum implicit_it_mode
430{
431 IMPLICIT_IT_MODE_NEVER = 0x00,
432 IMPLICIT_IT_MODE_ARM = 0x01,
433 IMPLICIT_IT_MODE_THUMB = 0x02,
434 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
435};
436static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
437
c19d1205
ZW		 438/* If unified_syntax is true, we are processing the new unified
439 ARM/Thumb syntax. Important differences from the old ARM mode:
440
441 - Immediate operands do not require a # prefix.
442 - Conditional affixes always appear at the end of the
443 instruction. (For backward compatibility, those instructions
444 that formerly had them in the middle, continue to accept them
445 there.)
446 - The IT instruction may appear, and if it does is validated
447 against subsequent conditional affixes. It does not generate
448 machine code.
449
450 Important differences from the old Thumb mode:
451
452 - Immediate operands do not require a # prefix.
453 - Most of the V6T2 instructions are only available in unified mode.
454 - The .N and .W suffixes are recognized and honored (it is an error
455 if they cannot be honored).
456 - All instructions set the flags if and only if they have an 's' affix.
457 - Conditional affixes may be used. They are validated against
458 preceding IT instructions. Unlike ARM mode, you cannot use a
459 conditional affix except in the scope of an IT instruction. */
460
461static bfd_boolean unified_syntax = FALSE;
b99bd4ef 462
bacebabc
RM		 463/* An immediate operand can start with #, and ld*, st*, pld operands
464 can contain [ and ]. We need to tell APP not to elide whitespace
477330fc
RM		 465 before a [, which can appear as the first operand for pld.
466 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
467const char arm_symbol_chars[] = "#[]{}";
bacebabc 468
5287ad62
JB		 469enum neon_el_type
470{
dcbf9037 471 NT_invtype,
5287ad62
JB		 472 NT_untyped,
473 NT_integer,
474 NT_float,
475 NT_poly,
476 NT_signed,
aab2c27d 477 NT_bfloat,
dcbf9037 478 NT_unsigned
5287ad62
JB		 479};
480
481struct neon_type_el
482{
483 enum neon_el_type type;
484 unsigned size;
485};
486
5aae9ae9 487#define NEON_MAX_TYPE_ELS 5
5287ad62
JB		 488
489struct neon_type
490{
491 struct neon_type_el el[NEON_MAX_TYPE_ELS];
492 unsigned elems;
493};
494
5ee91343 495enum pred_instruction_type
e07e6e58 496{
5ee91343
AV		 497 OUTSIDE_PRED_INSN,
498 INSIDE_VPT_INSN,
e07e6e58
NC		 499 INSIDE_IT_INSN,
500 INSIDE_IT_LAST_INSN,
501 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
477330fc 502 if inside, should be the last one. */
e07e6e58 503 NEUTRAL_IT_INSN, /* This could be either inside or outside,
477330fc 504 i.e. BKPT and NOP. */
5ee91343
AV		 505 IT_INSN, /* The IT insn has been parsed. */
506 VPT_INSN, /* The VPT/VPST insn has been parsed. */
35c228db 507 MVE_OUTSIDE_PRED_INSN , /* Instruction to indicate a MVE instruction without
5ee91343 508 a predication code. */
4934a27c 509 MVE_UNPREDICABLE_INSN, /* MVE instruction that is non-predicable. */
e07e6e58
NC		 510};
511
ad6cec43
MGD		 512/* The maximum number of operands we need. */
513#define ARM_IT_MAX_OPERANDS 6
e2b0ab59 514#define ARM_IT_MAX_RELOCS 3
ad6cec43 515
b99bd4ef
NC		 516struct arm_it
517{
c19d1205 518 const char * error;
b99bd4ef 519 unsigned long instruction;
c19d1205
ZW		 520 int size;
521 int size_req;
522 int cond;
037e8744
JB		 523 /* "uncond_value" is set to the value in place of the conditional field in
524 unconditional versions of the instruction, or -1 if nothing is
525 appropriate. */
526 int uncond_value;
5287ad62 527 struct neon_type vectype;
88714cb8
DG		 528 /* This does not indicate an actual NEON instruction, only that
529 the mnemonic accepts neon-style type suffixes. */
530 int is_neon;
0110f2b8
PB		 531 /* Set to the opcode if the instruction needs relaxation.
532 Zero if the instruction is not relaxed. */
533 unsigned long relax;
b99bd4ef
NC		 534 struct
535 {
536 bfd_reloc_code_real_type type;
c19d1205
ZW		 537 expressionS exp;
538 int pc_rel;
e2b0ab59 539 } relocs[ARM_IT_MAX_RELOCS];
b99bd4ef 540
5ee91343 541 enum pred_instruction_type pred_insn_type;
e07e6e58 542
c19d1205
ZW		 543 struct
544 {
545 unsigned reg;
ca3f61f7 546 signed int imm;
dcbf9037 547 struct neon_type_el vectype;
ca3f61f7
NC		 548 unsigned present : 1; /* Operand present. */
549 unsigned isreg : 1; /* Operand was a register. */
f5f10c66
AV		 550 unsigned immisreg : 2; /* .imm field is a second register.
551 0: imm, 1: gpr, 2: MVE Q-register. */
57785aa2
AV		 552 unsigned isscalar : 2; /* Operand is a (SIMD) scalar:
553 0) not scalar,
554 1) Neon scalar,
555 2) MVE scalar. */
5287ad62 556 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
c96612cc 557 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
5287ad62
JB		 558 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
559 instructions. This allows us to disambiguate ARM <-> vector insns. */
560 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
037e8744 561 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
5ee91343 562 unsigned isquad : 1; /* Operand is SIMD quad register. */
037e8744 563 unsigned issingle : 1; /* Operand is VFP single-precision register. */
1b883319 564 unsigned iszr : 1; /* Operand is ZR register. */
ca3f61f7
NC		 565 unsigned hasreloc : 1; /* Operand has relocation suffix. */
566 unsigned writeback : 1; /* Operand has trailing ! */
567 unsigned preind : 1; /* Preindexed address. */
568 unsigned postind : 1; /* Postindexed address. */
569 unsigned negative : 1; /* Index register was negated. */
570 unsigned shifted : 1; /* Shift applied to operation. */
571 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
ad6cec43 572 } operands[ARM_IT_MAX_OPERANDS];
b99bd4ef
NC		 573};
574
c19d1205 575static struct arm_it inst;
b99bd4ef
NC		 576
577#define NUM_FLOAT_VALS 8
578
05d2d07e 579const char * fp_const[] =
b99bd4ef
NC		 580{
581 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
582};
583
b99bd4ef
NC		 584LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
585
586#define FAIL (-1)
587#define SUCCESS (0)
588
589#define SUFF_S 1
590#define SUFF_D 2
591#define SUFF_E 3
592#define SUFF_P 4
593
c19d1205
ZW		 594#define CP_T_X 0x00008000
595#define CP_T_Y 0x00400000
b99bd4ef 596
c19d1205
ZW		 597#define CONDS_BIT 0x00100000
598#define LOAD_BIT 0x00100000
b99bd4ef
NC		 599
600#define DOUBLE_LOAD_FLAG 0x00000001
601
602struct asm_cond
603{
d3ce72d0 604 const char * template_name;
c921be7d 605 unsigned long value;
b99bd4ef
NC		 606};
607
c19d1205 608#define COND_ALWAYS 0xE
b99bd4ef 609
b99bd4ef
NC		 610struct asm_psr
611{
d3ce72d0 612 const char * template_name;
c921be7d 613 unsigned long field;
b99bd4ef
NC		 614};
615
62b3e311
PB		 616struct asm_barrier_opt
617{
e797f7e0
MGD		 618 const char * template_name;
619 unsigned long value;
620 const arm_feature_set arch;
62b3e311
PB		 621};
622
2d2255b5 623/* The bit that distinguishes CPSR and SPSR. */
b99bd4ef
NC		 624#define SPSR_BIT (1 << 22)
625
c19d1205
ZW		 626/* The individual PSR flag bits. */
627#define PSR_c (1 << 16)
628#define PSR_x (1 << 17)
629#define PSR_s (1 << 18)
630#define PSR_f (1 << 19)
b99bd4ef 631
c19d1205 632struct reloc_entry
bfae80f2 633{
0198d5e6 634 const char * name;
c921be7d 635 bfd_reloc_code_real_type reloc;
bfae80f2
RE		 636};
637
5287ad62 638enum vfp_reg_pos
bfae80f2 639{
5287ad62
JB		 640 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
641 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
bfae80f2
RE		 642};
643
644enum vfp_ldstm_type
645{
646 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
647};
648
dcbf9037
JB		 649/* Bits for DEFINED field in neon_typed_alias. */
650#define NTA_HASTYPE 1
651#define NTA_HASINDEX 2
652
653struct neon_typed_alias
654{
c921be7d
NC		 655 unsigned char defined;
656 unsigned char index;
657 struct neon_type_el eltype;
dcbf9037
JB		 658};
659
c19d1205 660/* ARM register categories. This includes coprocessor numbers and various
5aa75429
TP		 661 architecture extensions' registers. Each entry should have an error message
662 in reg_expected_msgs below. */
c19d1205 663enum arm_reg_type
bfae80f2 664{
c19d1205
ZW		 665 REG_TYPE_RN,
666 REG_TYPE_CP,
667 REG_TYPE_CN,
668 REG_TYPE_FN,
669 REG_TYPE_VFS,
670 REG_TYPE_VFD,
5287ad62 671 REG_TYPE_NQ,
037e8744 672 REG_TYPE_VFSD,
5287ad62 673 REG_TYPE_NDQ,
dec41383 674 REG_TYPE_NSD,
037e8744 675 REG_TYPE_NSDQ,
c19d1205
ZW		 676 REG_TYPE_VFC,
677 REG_TYPE_MVF,
678 REG_TYPE_MVD,
679 REG_TYPE_MVFX,
680 REG_TYPE_MVDX,
681 REG_TYPE_MVAX,
5ee91343 682 REG_TYPE_MQ,
c19d1205
ZW		 683 REG_TYPE_DSPSC,
684 REG_TYPE_MMXWR,
685 REG_TYPE_MMXWC,
686 REG_TYPE_MMXWCG,
687 REG_TYPE_XSCALE,
5ee91343 688 REG_TYPE_RNB,
1b883319 689 REG_TYPE_ZR
bfae80f2
RE		 690};
691
dcbf9037
JB		 692/* Structure for a hash table entry for a register.
693 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
694 information which states whether a vector type or index is specified (for a
695 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
6c43fab6
RE		 696struct reg_entry
697{
c921be7d 698 const char * name;
90ec0d68 699 unsigned int number;
c921be7d
NC		 700 unsigned char type;
701 unsigned char builtin;
702 struct neon_typed_alias * neon;
6c43fab6
RE		 703};
704
c19d1205 705/* Diagnostics used when we don't get a register of the expected type. */
c921be7d 706const char * const reg_expected_msgs[] =
c19d1205 707{
5aa75429
TP		 708 [REG_TYPE_RN] = N_("ARM register expected"),
709 [REG_TYPE_CP] = N_("bad or missing co-processor number"),
710 [REG_TYPE_CN] = N_("co-processor register expected"),
711 [REG_TYPE_FN] = N_("FPA register expected"),
712 [REG_TYPE_VFS] = N_("VFP single precision register expected"),
713 [REG_TYPE_VFD] = N_("VFP/Neon double precision register expected"),
714 [REG_TYPE_NQ] = N_("Neon quad precision register expected"),
715 [REG_TYPE_VFSD] = N_("VFP single or double precision register expected"),
716 [REG_TYPE_NDQ] = N_("Neon double or quad precision register expected"),
717 [REG_TYPE_NSD] = N_("Neon single or double precision register expected"),
718 [REG_TYPE_NSDQ] = N_("VFP single, double or Neon quad precision register"
719 " expected"),
720 [REG_TYPE_VFC] = N_("VFP system register expected"),
721 [REG_TYPE_MVF] = N_("Maverick MVF register expected"),
722 [REG_TYPE_MVD] = N_("Maverick MVD register expected"),
723 [REG_TYPE_MVFX] = N_("Maverick MVFX register expected"),
724 [REG_TYPE_MVDX] = N_("Maverick MVDX register expected"),
725 [REG_TYPE_MVAX] = N_("Maverick MVAX register expected"),
726 [REG_TYPE_DSPSC] = N_("Maverick DSPSC register expected"),
727 [REG_TYPE_MMXWR] = N_("iWMMXt data register expected"),
728 [REG_TYPE_MMXWC] = N_("iWMMXt control register expected"),
729 [REG_TYPE_MMXWCG] = N_("iWMMXt scalar register expected"),
730 [REG_TYPE_XSCALE] = N_("XScale accumulator register expected"),
5ee91343 731 [REG_TYPE_MQ] = N_("MVE vector register expected"),
da3ec71f 732 [REG_TYPE_RNB] = ""
6c43fab6
RE		 733};
734
c19d1205 735/* Some well known registers that we refer to directly elsewhere. */
bd340a04 736#define REG_R12 12
c19d1205
ZW		 737#define REG_SP 13
738#define REG_LR 14
739#define REG_PC 15
404ff6b5 740
b99bd4ef
NC		 741/* ARM instructions take 4bytes in the object file, Thumb instructions
742 take 2: */
c19d1205 743#define INSN_SIZE 4
b99bd4ef
NC		 744
745struct asm_opcode
746{
747 /* Basic string to match. */
d3ce72d0 748 const char * template_name;
c19d1205
ZW		 749
750 /* Parameters to instruction. */
5be8be5d 751 unsigned int operands[8];
c19d1205
ZW		 752
753 /* Conditional tag - see opcode_lookup. */
754 unsigned int tag : 4;
b99bd4ef
NC		 755
756 /* Basic instruction code. */
a302e574 757 unsigned int avalue;
b99bd4ef 758
c19d1205
ZW		 759 /* Thumb-format instruction code. */
760 unsigned int tvalue;
b99bd4ef 761
90e4755a 762 /* Which architecture variant provides this instruction. */
c921be7d
NC		 763 const arm_feature_set * avariant;
764 const arm_feature_set * tvariant;
c19d1205
ZW		 765
766 /* Function to call to encode instruction in ARM format. */
767 void (* aencode) (void);
b99bd4ef 768
c19d1205
ZW		 769 /* Function to call to encode instruction in Thumb format. */
770 void (* tencode) (void);
5ee91343
AV		 771
772 /* Indicates whether this instruction may be vector predicated. */
773 unsigned int mayBeVecPred : 1;
b99bd4ef
NC		 774};
775
a737bd4d
NC		 776/* Defines for various bits that we will want to toggle. */
777#define INST_IMMEDIATE 0x02000000
778#define OFFSET_REG 0x02000000
c19d1205 779#define HWOFFSET_IMM 0x00400000
a737bd4d
NC		 780#define SHIFT_BY_REG 0x00000010
781#define PRE_INDEX 0x01000000
782#define INDEX_UP 0x00800000
783#define WRITE_BACK 0x00200000
784#define LDM_TYPE_2_OR_3 0x00400000
a028a6f5 785#define CPSI_MMOD 0x00020000
90e4755a 786
a737bd4d
NC		 787#define LITERAL_MASK 0xf000f000
788#define OPCODE_MASK 0xfe1fffff
789#define V4_STR_BIT 0x00000020
8335d6aa 790#define VLDR_VMOV_SAME 0x0040f000
90e4755a 791
efd81785
PB		 792#define T2_SUBS_PC_LR 0xf3de8f00
793
a737bd4d 794#define DATA_OP_SHIFT 21
bada4342 795#define SBIT_SHIFT 20
90e4755a 796
ef8d22e6
PB		 797#define T2_OPCODE_MASK 0xfe1fffff
798#define T2_DATA_OP_SHIFT 21
bada4342 799#define T2_SBIT_SHIFT 20
ef8d22e6 800
6530b175
NC		 801#define A_COND_MASK 0xf0000000
802#define A_PUSH_POP_OP_MASK 0x0fff0000
803
804/* Opcodes for pushing/poping registers to/from the stack. */
805#define A1_OPCODE_PUSH 0x092d0000
806#define A2_OPCODE_PUSH 0x052d0004
807#define A2_OPCODE_POP 0x049d0004
808
a737bd4d
NC		 809/* Codes to distinguish the arithmetic instructions. */
810#define OPCODE_AND 0
811#define OPCODE_EOR 1
812#define OPCODE_SUB 2
813#define OPCODE_RSB 3
814#define OPCODE_ADD 4
815#define OPCODE_ADC 5
816#define OPCODE_SBC 6
817#define OPCODE_RSC 7
818#define OPCODE_TST 8
819#define OPCODE_TEQ 9
820#define OPCODE_CMP 10
821#define OPCODE_CMN 11
822#define OPCODE_ORR 12
823#define OPCODE_MOV 13
824#define OPCODE_BIC 14
825#define OPCODE_MVN 15
90e4755a 826
ef8d22e6
PB		 827#define T2_OPCODE_AND 0
828#define T2_OPCODE_BIC 1
829#define T2_OPCODE_ORR 2
830#define T2_OPCODE_ORN 3
831#define T2_OPCODE_EOR 4
832#define T2_OPCODE_ADD 8
833#define T2_OPCODE_ADC 10
834#define T2_OPCODE_SBC 11
835#define T2_OPCODE_SUB 13
836#define T2_OPCODE_RSB 14
837
a737bd4d
NC		 838#define T_OPCODE_MUL 0x4340
839#define T_OPCODE_TST 0x4200
840#define T_OPCODE_CMN 0x42c0
841#define T_OPCODE_NEG 0x4240
842#define T_OPCODE_MVN 0x43c0
90e4755a 843
a737bd4d
NC		 844#define T_OPCODE_ADD_R3 0x1800
845#define T_OPCODE_SUB_R3 0x1a00
846#define T_OPCODE_ADD_HI 0x4400
847#define T_OPCODE_ADD_ST 0xb000
848#define T_OPCODE_SUB_ST 0xb080
849#define T_OPCODE_ADD_SP 0xa800
850#define T_OPCODE_ADD_PC 0xa000
851#define T_OPCODE_ADD_I8 0x3000
852#define T_OPCODE_SUB_I8 0x3800
853#define T_OPCODE_ADD_I3 0x1c00
854#define T_OPCODE_SUB_I3 0x1e00
b99bd4ef 855
a737bd4d
NC		 856#define T_OPCODE_ASR_R 0x4100
857#define T_OPCODE_LSL_R 0x4080
c19d1205
ZW		 858#define T_OPCODE_LSR_R 0x40c0
859#define T_OPCODE_ROR_R 0x41c0
a737bd4d
NC		 860#define T_OPCODE_ASR_I 0x1000
861#define T_OPCODE_LSL_I 0x0000
862#define T_OPCODE_LSR_I 0x0800
b99bd4ef 863
a737bd4d
NC		 864#define T_OPCODE_MOV_I8 0x2000
865#define T_OPCODE_CMP_I8 0x2800
866#define T_OPCODE_CMP_LR 0x4280
867#define T_OPCODE_MOV_HR 0x4600
868#define T_OPCODE_CMP_HR 0x4500
b99bd4ef 869
a737bd4d
NC		 870#define T_OPCODE_LDR_PC 0x4800
871#define T_OPCODE_LDR_SP 0x9800
872#define T_OPCODE_STR_SP 0x9000
873#define T_OPCODE_LDR_IW 0x6800
874#define T_OPCODE_STR_IW 0x6000
875#define T_OPCODE_LDR_IH 0x8800
876#define T_OPCODE_STR_IH 0x8000
877#define T_OPCODE_LDR_IB 0x7800
878#define T_OPCODE_STR_IB 0x7000
879#define T_OPCODE_LDR_RW 0x5800
880#define T_OPCODE_STR_RW 0x5000
881#define T_OPCODE_LDR_RH 0x5a00
882#define T_OPCODE_STR_RH 0x5200
883#define T_OPCODE_LDR_RB 0x5c00
884#define T_OPCODE_STR_RB 0x5400
c9b604bd 885
a737bd4d
NC		 886#define T_OPCODE_PUSH 0xb400
887#define T_OPCODE_POP 0xbc00
b99bd4ef 888
2fc8bdac 889#define T_OPCODE_BRANCH 0xe000
b99bd4ef 890
a737bd4d 891#define THUMB_SIZE 2 /* Size of thumb instruction. */
a737bd4d 892#define THUMB_PP_PC_LR 0x0100
c19d1205 893#define THUMB_LOAD_BIT 0x0800
53365c0d 894#define THUMB2_LOAD_BIT 0x00100000
c19d1205 895
5ee91343 896#define BAD_SYNTAX _("syntax error")
c19d1205 897#define BAD_ARGS _("bad arguments to instruction")
fdfde340 898#define BAD_SP _("r13 not allowed here")
c19d1205 899#define BAD_PC _("r15 not allowed here")
a302e574
AV		 900#define BAD_ODD _("Odd register not allowed here")
901#define BAD_EVEN _("Even register not allowed here")
c19d1205
ZW		 902#define BAD_COND _("instruction cannot be conditional")
903#define BAD_OVERLAP _("registers may not be the same")
904#define BAD_HIREG _("lo register required")
905#define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
35c228db 906#define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
dfa9f0d5 907#define BAD_BRANCH _("branch must be last instruction in IT block")
e12437dc 908#define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
4934a27c 909#define BAD_NO_VPT _("instruction not allowed in VPT block")
dfa9f0d5 910#define BAD_NOT_IT _("instruction not allowed in IT block")
5ee91343 911#define BAD_NOT_VPT _("instruction missing MVE vector predication code")
037e8744 912#define BAD_FPU _("selected FPU does not support instruction")
e07e6e58 913#define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
5ee91343
AV		 914#define BAD_OUT_VPT \
915 _("vector predicated instruction should be in VPT/VPST block")
e07e6e58 916#define BAD_IT_COND _("incorrect condition in IT block")
5ee91343 917#define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
e07e6e58 918#define BAD_IT_IT _("IT falling in the range of a previous IT block")
921e5f0a 919#define MISSING_FNSTART _("missing .fnstart before unwinding directive")
5be8be5d
DG		 920#define BAD_PC_ADDRESSING \
921 _("cannot use register index with PC-relative addressing")
922#define BAD_PC_WRITEBACK \
923 _("cannot use writeback with PC-relative addressing")
9db2f6b4
RL		 924#define BAD_RANGE _("branch out of range")
925#define BAD_FP16 _("selected processor does not support fp16 instruction")
aab2c27d 926#define BAD_BF16 _("selected processor does not support bf16 instruction")
4934a27c
MM		 927#define BAD_CDE _("selected processor does not support cde instruction")
928#define BAD_CDE_COPROC _("coprocessor for insn is not enabled for cde")
dd5181d5 929#define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
a9f02af8 930#define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
5ee91343
AV		 931#define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
932 "block")
933#define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
934 "block")
935#define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
936 " operand")
937#define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
938 " operand")
a302e574 939#define BAD_SIMD_TYPE _("bad type in SIMD instruction")
886e1c73
AV		 940#define BAD_MVE_AUTO \
941 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
942 " use a valid -march or -mcpu option.")
943#define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
944 "and source operands makes instruction UNPREDICTABLE")
35c228db 945#define BAD_EL_TYPE _("bad element type for instruction")
1b883319 946#define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
c19d1205 947
c921be7d
NC		 948static struct hash_control * arm_ops_hsh;
949static struct hash_control * arm_cond_hsh;
5ee91343 950static struct hash_control * arm_vcond_hsh;
c921be7d
NC		 951static struct hash_control * arm_shift_hsh;
952static struct hash_control * arm_psr_hsh;
953static struct hash_control * arm_v7m_psr_hsh;
954static struct hash_control * arm_reg_hsh;
955static struct hash_control * arm_reloc_hsh;
956static struct hash_control * arm_barrier_opt_hsh;
b99bd4ef 957
b99bd4ef
NC		 958/* Stuff needed to resolve the label ambiguity
959 As:
960 ...
961 label: <insn>
962 may differ from:
963 ...
964 label:
5f4273c7 965 <insn> */
b99bd4ef
NC		 966
967symbolS * last_label_seen;
b34976b6 968static int label_is_thumb_function_name = FALSE;
e07e6e58 969
3d0c9500
NC		 970/* Literal pool structure. Held on a per-section
971 and per-sub-section basis. */
a737bd4d 972
c19d1205 973#define MAX_LITERAL_POOL_SIZE 1024
3d0c9500 974typedef struct literal_pool
b99bd4ef 975{
c921be7d
NC		 976 expressionS literals [MAX_LITERAL_POOL_SIZE];
977 unsigned int next_free_entry;
978 unsigned int id;
979 symbolS * symbol;
980 segT section;
981 subsegT sub_section;
a8040cf2
NC		 982#ifdef OBJ_ELF
983 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
984#endif
c921be7d 985 struct literal_pool * next;
8335d6aa 986 unsigned int alignment;
3d0c9500 987} literal_pool;
b99bd4ef 988
3d0c9500
NC		 989/* Pointer to a linked list of literal pools. */
990literal_pool * list_of_pools = NULL;
e27ec89e 991
2e6976a8
DG		 992typedef enum asmfunc_states
993{
994 OUTSIDE_ASMFUNC,
995 WAITING_ASMFUNC_NAME,
996 WAITING_ENDASMFUNC
997} asmfunc_states;
998
999static asmfunc_states asmfunc_state = OUTSIDE_ASMFUNC;
1000
e07e6e58 1001#ifdef OBJ_ELF
5ee91343 1002# define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
e07e6e58 1003#else
5ee91343 1004static struct current_pred now_pred;
e07e6e58
NC		 1005#endif
1006
1007static inline int
5ee91343 1008now_pred_compatible (int cond)
e07e6e58 1009{
5ee91343 1010 return (cond & ~1) == (now_pred.cc & ~1);
e07e6e58
NC		 1011}
1012
1013static inline int
1014conditional_insn (void)
1015{
1016 return inst.cond != COND_ALWAYS;
1017}
1018
5ee91343 1019static int in_pred_block (void);
e07e6e58 1020
5ee91343 1021static int handle_pred_state (void);
e07e6e58
NC		 1022
1023static void force_automatic_it_block_close (void);
1024
c921be7d
NC		 1025static void it_fsm_post_encode (void);
1026
5ee91343 1027#define set_pred_insn_type(type) \
e07e6e58
NC		 1028 do \
1029 { \
5ee91343
AV		 1030 inst.pred_insn_type = type; \
1031 if (handle_pred_state () == FAIL) \
477330fc 1032 return; \
e07e6e58
NC		 1033 } \
1034 while (0)
1035
5ee91343 1036#define set_pred_insn_type_nonvoid(type, failret) \
c921be7d
NC		 1037 do \
1038 { \
5ee91343
AV		 1039 inst.pred_insn_type = type; \
1040 if (handle_pred_state () == FAIL) \
477330fc 1041 return failret; \
c921be7d
NC		 1042 } \
1043 while(0)
1044
5ee91343 1045#define set_pred_insn_type_last() \
e07e6e58
NC		 1046 do \
1047 { \
1048 if (inst.cond == COND_ALWAYS) \
5ee91343 1049 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
e07e6e58 1050 else \
5ee91343 1051 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
e07e6e58
NC		 1052 } \
1053 while (0)
1054
e39c1607
SD		 1055/* Toggle value[pos]. */
1056#define TOGGLE_BIT(value, pos) (value ^ (1 << pos))
1057
c19d1205 1058/* Pure syntax. */
b99bd4ef 1059
c19d1205
ZW		 1060/* This array holds the chars that always start a comment. If the
1061 pre-processor is disabled, these aren't very useful. */
2e6976a8 1062char arm_comment_chars[] = "@";
3d0c9500 1063
c19d1205
ZW		 1064/* This array holds the chars that only start a comment at the beginning of
1065 a line. If the line seems to have the form '# 123 filename'
1066 .line and .file directives will appear in the pre-processed output. */
1067/* Note that input_file.c hand checks for '#' at the beginning of the
1068 first line of the input file. This is because the compiler outputs
1069 #NO_APP at the beginning of its output. */
1070/* Also note that comments like this one will always work. */
1071const char line_comment_chars[] = "#";
3d0c9500 1072
2e6976a8 1073char arm_line_separator_chars[] = ";";
b99bd4ef 1074
c19d1205
ZW		 1075/* Chars that can be used to separate mant
1076 from exp in floating point numbers. */
1077const char EXP_CHARS[] = "eE";
3d0c9500 1078
c19d1205
ZW		 1079/* Chars that mean this number is a floating point constant. */
1080/* As in 0f12.456 */
1081/* or 0d1.2345e12 */
b99bd4ef 1082
5312fe52 1083const char FLT_CHARS[] = "rRsSfFdDxXeEpPHh";
3d0c9500 1084
c19d1205
ZW		 1085/* Prefix characters that indicate the start of an immediate
1086 value. */
1087#define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
3d0c9500 1088
c19d1205
ZW		 1089/* Separator character handling. */
1090
1091#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1092
5312fe52
BW		 1093enum fp_16bit_format
1094{
1095 ARM_FP16_FORMAT_IEEE = 0x1,
1096 ARM_FP16_FORMAT_ALTERNATIVE = 0x2,
1097 ARM_FP16_FORMAT_DEFAULT = 0x3
1098};
1099
1100static enum fp_16bit_format fp16_format = ARM_FP16_FORMAT_DEFAULT;
1101
1102
c19d1205
ZW		 1103static inline int
1104skip_past_char (char ** str, char c)
1105{
8ab8155f
NC		 1106 /* PR gas/14987: Allow for whitespace before the expected character. */
1107 skip_whitespace (*str);
427d0db6 1108
c19d1205
ZW		 1109 if (**str == c)
1110 {
1111 (*str)++;
1112 return SUCCESS;
3d0c9500 1113 }
c19d1205
ZW		 1114 else
1115 return FAIL;
1116}
c921be7d 1117
c19d1205 1118#define skip_past_comma(str) skip_past_char (str, ',')
3d0c9500 1119
c19d1205
ZW		 1120/* Arithmetic expressions (possibly involving symbols). */
1121
1122/* Return TRUE if anything in the expression is a bignum. */
1123
0198d5e6 1124static bfd_boolean
c19d1205
ZW		 1125walk_no_bignums (symbolS * sp)
1126{
1127 if (symbol_get_value_expression (sp)->X_op == O_big)
0198d5e6 1128 return TRUE;
c19d1205
ZW		 1129
1130 if (symbol_get_value_expression (sp)->X_add_symbol)
3d0c9500 1131 {
c19d1205
ZW		 1132 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
1133 || (symbol_get_value_expression (sp)->X_op_symbol
1134 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
3d0c9500
NC		 1135 }
1136
0198d5e6 1137 return FALSE;
3d0c9500
NC		 1138}
1139
0198d5e6 1140static bfd_boolean in_my_get_expression = FALSE;
c19d1205
ZW		 1141
1142/* Third argument to my_get_expression. */
1143#define GE_NO_PREFIX 0
1144#define GE_IMM_PREFIX 1
1145#define GE_OPT_PREFIX 2
5287ad62
JB		 1146/* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1147 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1148#define GE_OPT_PREFIX_BIG 3
a737bd4d 1149
b99bd4ef 1150static int
c19d1205 1151my_get_expression (expressionS * ep, char ** str, int prefix_mode)
b99bd4ef 1152{
c19d1205 1153 char * save_in;
b99bd4ef 1154
c19d1205
ZW		 1155 /* In unified syntax, all prefixes are optional. */
1156 if (unified_syntax)
5287ad62 1157 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
477330fc 1158 : GE_OPT_PREFIX;
b99bd4ef 1159
c19d1205 1160 switch (prefix_mode)
b99bd4ef 1161 {
c19d1205
ZW		 1162 case GE_NO_PREFIX: break;
1163 case GE_IMM_PREFIX:
1164 if (!is_immediate_prefix (**str))
1165 {
1166 inst.error = _("immediate expression requires a # prefix");
1167 return FAIL;
1168 }
1169 (*str)++;
1170 break;
1171 case GE_OPT_PREFIX:
5287ad62 1172 case GE_OPT_PREFIX_BIG:
c19d1205
ZW		 1173 if (is_immediate_prefix (**str))
1174 (*str)++;
1175 break;
0198d5e6
TC		 1176 default:
1177 abort ();
c19d1205 1178 }
b99bd4ef 1179
c19d1205 1180 memset (ep, 0, sizeof (expressionS));
b99bd4ef 1181
c19d1205
ZW		 1182 save_in = input_line_pointer;
1183 input_line_pointer = *str;
0198d5e6 1184 in_my_get_expression = TRUE;
2ac93be7 1185 expression (ep);
0198d5e6 1186 in_my_get_expression = FALSE;
c19d1205 1187
f86adc07 1188 if (ep->X_op == O_illegal || ep->X_op == O_absent)
b99bd4ef 1189 {
f86adc07 1190 /* We found a bad or missing expression in md_operand(). */
c19d1205
ZW		 1191 *str = input_line_pointer;
1192 input_line_pointer = save_in;
1193 if (inst.error == NULL)
f86adc07
NS		 1194 inst.error = (ep->X_op == O_absent
1195 ? _("missing expression") :_("bad expression"));
c19d1205
ZW		 1196 return 1;
1197 }
b99bd4ef 1198
c19d1205
ZW		 1199 /* Get rid of any bignums now, so that we don't generate an error for which
1200 we can't establish a line number later on. Big numbers are never valid
1201 in instructions, which is where this routine is always called. */
5287ad62
JB		 1202 if (prefix_mode != GE_OPT_PREFIX_BIG
1203 && (ep->X_op == O_big
477330fc 1204 || (ep->X_add_symbol
5287ad62 1205 && (walk_no_bignums (ep->X_add_symbol)
477330fc 1206 || (ep->X_op_symbol
5287ad62 1207 && walk_no_bignums (ep->X_op_symbol))))))
c19d1205
ZW		 1208 {
1209 inst.error = _("invalid constant");
1210 *str = input_line_pointer;
1211 input_line_pointer = save_in;
1212 return 1;
1213 }
b99bd4ef 1214
c19d1205
ZW		 1215 *str = input_line_pointer;
1216 input_line_pointer = save_in;
0198d5e6 1217 return SUCCESS;
b99bd4ef
NC		 1218}
1219
c19d1205
ZW		 1220/* Turn a string in input_line_pointer into a floating point constant
1221 of type TYPE, and store the appropriate bytes in *LITP. The number
1222 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1223 returned, or NULL on OK.
b99bd4ef 1224
c19d1205
ZW		 1225 Note that fp constants aren't represent in the normal way on the ARM.
1226 In big endian mode, things are as expected. However, in little endian
1227 mode fp constants are big-endian word-wise, and little-endian byte-wise
1228 within the words. For example, (double) 1.1 in big endian mode is
1229 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1230 the byte sequence 99 99 f1 3f 9a 99 99 99.
b99bd4ef 1231
c19d1205 1232 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
b99bd4ef 1233
6d4af3c2 1234const char *
c19d1205
ZW		 1235md_atof (int type, char * litP, int * sizeP)
1236{
1237 int prec;
1238 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1239 char *t;
1240 int i;
b99bd4ef 1241
c19d1205
ZW		 1242 switch (type)
1243 {
5312fe52
BW		 1244 case 'H':
1245 case 'h':
1246 prec = 1;
1247 break;
1248
27cce866
MM		 1249 /* If this is a bfloat16, then parse it slightly differently, as it
1250 does not follow the IEEE specification for floating point numbers
1251 exactly. */
1252 case 'b':
1253 {
1254 FLONUM_TYPE generic_float;
1255
1256 t = atof_ieee_detail (input_line_pointer, 1, 8, words, &generic_float);
1257
1258 if (t)
1259 input_line_pointer = t;
1260 else
1261 return _("invalid floating point number");
1262
1263 switch (generic_float.sign)
1264 {
1265 /* Is +Inf. */
1266 case 'P':
1267 words[0] = 0x7f80;
1268 break;
1269
1270 /* Is -Inf. */
1271 case 'N':
1272 words[0] = 0xff80;
1273 break;
1274
1275 /* Is NaN. */
1276 /* bfloat16 has two types of NaN - quiet and signalling.
1277 Quiet NaN has bit[6] == 1 && faction != 0, whereas
1278 signalling NaN's have bit[0] == 0 && fraction != 0.
1279 Chosen this specific encoding as it is the same form
1280 as used by other IEEE 754 encodings in GAS. */
1281 case 0:
1282 words[0] = 0x7fff;
1283 break;
1284
1285 default:
1286 break;
1287 }
1288
1289 *sizeP = 2;
1290
1291 md_number_to_chars (litP, (valueT) words[0], sizeof (LITTLENUM_TYPE));
1292
1293 return NULL;
1294 }
c19d1205
ZW		 1295 case 'f':
1296 case 'F':
1297 case 's':
1298 case 'S':
1299 prec = 2;
1300 break;
b99bd4ef 1301
c19d1205
ZW		 1302 case 'd':
1303 case 'D':
1304 case 'r':
1305 case 'R':
1306 prec = 4;
1307 break;
b99bd4ef 1308
c19d1205
ZW		 1309 case 'x':
1310 case 'X':
499ac353 1311 prec = 5;
c19d1205 1312 break;
b99bd4ef 1313
c19d1205
ZW		 1314 case 'p':
1315 case 'P':
499ac353 1316 prec = 5;
c19d1205 1317 break;
a737bd4d 1318
c19d1205
ZW		 1319 default:
1320 *sizeP = 0;
499ac353 1321 return _("Unrecognized or unsupported floating point constant");
c19d1205 1322 }
b99bd4ef 1323
c19d1205
ZW		 1324 t = atof_ieee (input_line_pointer, type, words);
1325 if (t)
1326 input_line_pointer = t;
499ac353 1327 *sizeP = prec * sizeof (LITTLENUM_TYPE);
b99bd4ef 1328
72c03e30
BW		 1329 if (target_big_endian || prec == 1)
1330 for (i = 0; i < prec; i++)
1331 {
1332 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1333 litP += sizeof (LITTLENUM_TYPE);
1334 }
1335 else if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1336 for (i = prec - 1; i >= 0; i--)
1337 {
1338 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1339 litP += sizeof (LITTLENUM_TYPE);
1340 }
c19d1205 1341 else
72c03e30
BW		 1342 /* For a 4 byte float the order of elements in `words' is 1 0.
1343 For an 8 byte float the order is 1 0 3 2. */
1344 for (i = 0; i < prec; i += 2)
1345 {
1346 md_number_to_chars (litP, (valueT) words[i + 1],
1347 sizeof (LITTLENUM_TYPE));
1348 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1349 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1350 litP += 2 * sizeof (LITTLENUM_TYPE);
1351 }
b99bd4ef 1352
499ac353 1353 return NULL;
c19d1205 1354}
b99bd4ef 1355
c19d1205
ZW		 1356/* We handle all bad expressions here, so that we can report the faulty
1357 instruction in the error message. */
0198d5e6 1358
c19d1205 1359void
91d6fa6a 1360md_operand (expressionS * exp)
c19d1205
ZW		 1361{
1362 if (in_my_get_expression)
91d6fa6a 1363 exp->X_op = O_illegal;
b99bd4ef
NC		 1364}
1365
c19d1205 1366/* Immediate values. */
b99bd4ef 1367
0198d5e6 1368#ifdef OBJ_ELF
c19d1205
ZW		 1369/* Generic immediate-value read function for use in directives.
1370 Accepts anything that 'expression' can fold to a constant.
1371 *val receives the number. */
0198d5e6 1372
c19d1205
ZW		 1373static int
1374immediate_for_directive (int *val)
b99bd4ef 1375{
c19d1205
ZW		 1376 expressionS exp;
1377 exp.X_op = O_illegal;
b99bd4ef 1378
c19d1205
ZW		 1379 if (is_immediate_prefix (*input_line_pointer))
1380 {
1381 input_line_pointer++;
1382 expression (&exp);
1383 }
b99bd4ef 1384
c19d1205
ZW		 1385 if (exp.X_op != O_constant)
1386 {
1387 as_bad (_("expected #constant"));
1388 ignore_rest_of_line ();
1389 return FAIL;
1390 }
1391 *val = exp.X_add_number;
1392 return SUCCESS;
b99bd4ef 1393}
c19d1205 1394#endif
b99bd4ef 1395
c19d1205 1396/* Register parsing. */
b99bd4ef 1397
c19d1205
ZW		 1398/* Generic register parser. CCP points to what should be the
1399 beginning of a register name. If it is indeed a valid register
1400 name, advance CCP over it and return the reg_entry structure;
1401 otherwise return NULL. Does not issue diagnostics. */
1402
1403static struct reg_entry *
1404arm_reg_parse_multi (char **ccp)
b99bd4ef 1405{
c19d1205
ZW		 1406 char *start = *ccp;
1407 char *p;
1408 struct reg_entry *reg;
b99bd4ef 1409
477330fc
RM		 1410 skip_whitespace (start);
1411
c19d1205
ZW		 1412#ifdef REGISTER_PREFIX
1413 if (*start != REGISTER_PREFIX)
01cfc07f 1414 return NULL;
c19d1205
ZW		 1415 start++;
1416#endif
1417#ifdef OPTIONAL_REGISTER_PREFIX
1418 if (*start == OPTIONAL_REGISTER_PREFIX)
1419 start++;
1420#endif
b99bd4ef 1421
c19d1205
ZW		 1422 p = start;
1423 if (!ISALPHA (*p) || !is_name_beginner (*p))
1424 return NULL;
b99bd4ef 1425
c19d1205
ZW		 1426 do
1427 p++;
1428 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1429
1430 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1431
1432 if (!reg)
1433 return NULL;
1434
1435 *ccp = p;
1436 return reg;
b99bd4ef
NC		 1437}
1438
1439static int
dcbf9037 1440arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
477330fc 1441 enum arm_reg_type type)
b99bd4ef 1442{
c19d1205
ZW		 1443 /* Alternative syntaxes are accepted for a few register classes. */
1444 switch (type)
1445 {
1446 case REG_TYPE_MVF:
1447 case REG_TYPE_MVD:
1448 case REG_TYPE_MVFX:
1449 case REG_TYPE_MVDX:
1450 /* Generic coprocessor register names are allowed for these. */
79134647 1451 if (reg && reg->type == REG_TYPE_CN)
c19d1205
ZW		 1452 return reg->number;
1453 break;
69b97547 1454
c19d1205
ZW		 1455 case REG_TYPE_CP:
1456 /* For backward compatibility, a bare number is valid here. */
1457 {
1458 unsigned long processor = strtoul (start, ccp, 10);
1459 if (*ccp != start && processor <= 15)
1460 return processor;
1461 }
1a0670f3 1462 /* Fall through. */
6057a28f 1463
c19d1205
ZW		 1464 case REG_TYPE_MMXWC:
1465 /* WC includes WCG. ??? I'm not sure this is true for all
1466 instructions that take WC registers. */
79134647 1467 if (reg && reg->type == REG_TYPE_MMXWCG)
c19d1205 1468 return reg->number;
6057a28f 1469 break;
c19d1205 1470
6057a28f 1471 default:
c19d1205 1472 break;
6057a28f
NC		 1473 }
1474
dcbf9037
JB		 1475 return FAIL;
1476}
1477
1478/* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1479 return value is the register number or FAIL. */
1480
1481static int
1482arm_reg_parse (char **ccp, enum arm_reg_type type)
1483{
1484 char *start = *ccp;
1485 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1486 int ret;
1487
1488 /* Do not allow a scalar (reg+index) to parse as a register. */
1489 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1490 return FAIL;
1491
1492 if (reg && reg->type == type)
1493 return reg->number;
1494
1495 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1496 return ret;
1497
c19d1205
ZW		 1498 *ccp = start;
1499 return FAIL;
1500}
69b97547 1501
dcbf9037
JB		 1502/* Parse a Neon type specifier. *STR should point at the leading '.'
1503 character. Does no verification at this stage that the type fits the opcode
1504 properly. E.g.,
1505
1506 .i32.i32.s16
1507 .s32.f32
1508 .u16
1509
1510 Can all be legally parsed by this function.
1511
1512 Fills in neon_type struct pointer with parsed information, and updates STR
1513 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1514 type, FAIL if not. */
1515
1516static int
1517parse_neon_type (struct neon_type *type, char **str)
1518{
1519 char *ptr = *str;
1520
1521 if (type)
1522 type->elems = 0;
1523
1524 while (type->elems < NEON_MAX_TYPE_ELS)
1525 {
1526 enum neon_el_type thistype = NT_untyped;
1527 unsigned thissize = -1u;
1528
1529 if (*ptr != '.')
1530 break;
1531
1532 ptr++;
1533
1534 /* Just a size without an explicit type. */
1535 if (ISDIGIT (*ptr))
1536 goto parsesize;
1537
1538 switch (TOLOWER (*ptr))
1539 {
1540 case 'i': thistype = NT_integer; break;
1541 case 'f': thistype = NT_float; break;
1542 case 'p': thistype = NT_poly; break;
1543 case 's': thistype = NT_signed; break;
1544 case 'u': thistype = NT_unsigned; break;
477330fc
RM		 1545 case 'd':
1546 thistype = NT_float;
1547 thissize = 64;
1548 ptr++;
1549 goto done;
aab2c27d
MM		 1550 case 'b':
1551 thistype = NT_bfloat;
1552 switch (TOLOWER (*(++ptr)))
1553 {
1554 case 'f':
1555 ptr += 1;
1556 thissize = strtoul (ptr, &ptr, 10);
1557 if (thissize != 16)
1558 {
1559 as_bad (_("bad size %d in type specifier"), thissize);
1560 return FAIL;
1561 }
1562 goto done;
1563 case '0': case '1': case '2': case '3': case '4':
1564 case '5': case '6': case '7': case '8': case '9':
1565 case ' ': case '.':
1566 as_bad (_("unexpected type character `b' -- did you mean `bf'?"));
1567 return FAIL;
1568 default:
1569 break;
1570 }
1571 break;
dcbf9037
JB		 1572 default:
1573 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1574 return FAIL;
1575 }
1576
1577 ptr++;
1578
1579 /* .f is an abbreviation for .f32. */
1580 if (thistype == NT_float && !ISDIGIT (*ptr))
1581 thissize = 32;
1582 else
1583 {
1584 parsesize:
1585 thissize = strtoul (ptr, &ptr, 10);
1586
1587 if (thissize != 8 && thissize != 16 && thissize != 32
477330fc
RM		 1588 && thissize != 64)
1589 {
1590 as_bad (_("bad size %d in type specifier"), thissize);
dcbf9037
JB		 1591 return FAIL;
1592 }
1593 }
1594
037e8744 1595 done:
dcbf9037 1596 if (type)
477330fc
RM		 1597 {
1598 type->el[type->elems].type = thistype;
dcbf9037
JB		 1599 type->el[type->elems].size = thissize;
1600 type->elems++;
1601 }
1602 }
1603
1604 /* Empty/missing type is not a successful parse. */
1605 if (type->elems == 0)
1606 return FAIL;
1607
1608 *str = ptr;
1609
1610 return SUCCESS;
1611}
1612
1613/* Errors may be set multiple times during parsing or bit encoding
1614 (particularly in the Neon bits), but usually the earliest error which is set
1615 will be the most meaningful. Avoid overwriting it with later (cascading)
1616 errors by calling this function. */
1617
1618static void
1619first_error (const char *err)
1620{
1621 if (!inst.error)
1622 inst.error = err;
1623}
1624
1625/* Parse a single type, e.g. ".s32", leading period included. */
1626static int
1627parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1628{
1629 char *str = *ccp;
1630 struct neon_type optype;
1631
1632 if (*str == '.')
1633 {
1634 if (parse_neon_type (&optype, &str) == SUCCESS)
477330fc
RM		 1635 {
1636 if (optype.elems == 1)
1637 *vectype = optype.el[0];
1638 else
1639 {
1640 first_error (_("only one type should be specified for operand"));
1641 return FAIL;
1642 }
1643 }
dcbf9037 1644 else
477330fc
RM		 1645 {
1646 first_error (_("vector type expected"));
1647 return FAIL;
1648 }
dcbf9037
JB		 1649 }
1650 else
1651 return FAIL;
5f4273c7 1652
dcbf9037 1653 *ccp = str;
5f4273c7 1654
dcbf9037
JB		 1655 return SUCCESS;
1656}
1657
1658/* Special meanings for indices (which have a range of 0-7), which will fit into
1659 a 4-bit integer. */
1660
1661#define NEON_ALL_LANES 15
1662#define NEON_INTERLEAVE_LANES 14
1663
5ee91343
AV		 1664/* Record a use of the given feature. */
1665static void
1666record_feature_use (const arm_feature_set *feature)
1667{
1668 if (thumb_mode)
1669 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
1670 else
1671 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
1672}
1673
1674/* If the given feature available in the selected CPU, mark it as used.
1675 Returns TRUE iff feature is available. */
1676static bfd_boolean
1677mark_feature_used (const arm_feature_set *feature)
1678{
886e1c73
AV		 1679
1680 /* Do not support the use of MVE only instructions when in auto-detection or
1681 -march=all. */
1682 if (((feature == &mve_ext) || (feature == &mve_fp_ext))
1683 && ARM_CPU_IS_ANY (cpu_variant))
1684 {
1685 first_error (BAD_MVE_AUTO);
1686 return FALSE;
1687 }
5ee91343
AV		 1688 /* Ensure the option is valid on the current architecture. */
1689 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
1690 return FALSE;
1691
1692 /* Add the appropriate architecture feature for the barrier option used.
1693 */
1694 record_feature_use (feature);
1695
1696 return TRUE;
1697}
1698
dcbf9037
JB		 1699/* Parse either a register or a scalar, with an optional type. Return the
1700 register number, and optionally fill in the actual type of the register
1701 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1702 type/index information in *TYPEINFO. */
1703
1704static int
1705parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
477330fc
RM		 1706 enum arm_reg_type *rtype,
1707 struct neon_typed_alias *typeinfo)
dcbf9037
JB		 1708{
1709 char *str = *ccp;
1710 struct reg_entry *reg = arm_reg_parse_multi (&str);
1711 struct neon_typed_alias atype;
1712 struct neon_type_el parsetype;
1713
1714 atype.defined = 0;
1715 atype.index = -1;
1716 atype.eltype.type = NT_invtype;
1717 atype.eltype.size = -1;
1718
1719 /* Try alternate syntax for some types of register. Note these are mutually
1720 exclusive with the Neon syntax extensions. */
1721 if (reg == NULL)
1722 {
1723 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1724 if (altreg != FAIL)
477330fc 1725 *ccp = str;
dcbf9037 1726 if (typeinfo)
477330fc 1727 *typeinfo = atype;
dcbf9037
JB		 1728 return altreg;
1729 }
1730
037e8744
JB		 1731 /* Undo polymorphism when a set of register types may be accepted. */
1732 if ((type == REG_TYPE_NDQ
1733 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1734 || (type == REG_TYPE_VFSD
477330fc 1735 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
037e8744 1736 || (type == REG_TYPE_NSDQ
477330fc
RM		 1737 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1738 || reg->type == REG_TYPE_NQ))
dec41383
JW		 1739 || (type == REG_TYPE_NSD
1740 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
f512f76f
NC		 1741 || (type == REG_TYPE_MMXWC
1742 && (reg->type == REG_TYPE_MMXWCG)))
21d799b5 1743 type = (enum arm_reg_type) reg->type;
dcbf9037 1744
5ee91343
AV		 1745 if (type == REG_TYPE_MQ)
1746 {
1747 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
1748 return FAIL;
1749
1750 if (!reg || reg->type != REG_TYPE_NQ)
1751 return FAIL;
1752
1753 if (reg->number > 14 && !mark_feature_used (&fpu_vfp_ext_d32))
1754 {
1755 first_error (_("expected MVE register [q0..q7]"));
1756 return FAIL;
1757 }
1758 type = REG_TYPE_NQ;
1759 }
1760 else if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
1761 && (type == REG_TYPE_NQ))
1762 return FAIL;
1763
1764
dcbf9037
JB		 1765 if (type != reg->type)
1766 return FAIL;
1767
1768 if (reg->neon)
1769 atype = *reg->neon;
5f4273c7 1770
dcbf9037
JB		 1771 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1772 {
1773 if ((atype.defined & NTA_HASTYPE) != 0)
477330fc
RM		 1774 {
1775 first_error (_("can't redefine type for operand"));
1776 return FAIL;
1777 }
dcbf9037
JB		 1778 atype.defined |= NTA_HASTYPE;
1779 atype.eltype = parsetype;
1780 }
5f4273c7 1781
dcbf9037
JB		 1782 if (skip_past_char (&str, '[') == SUCCESS)
1783 {
dec41383
JW		 1784 if (type != REG_TYPE_VFD
1785 && !(type == REG_TYPE_VFS
57785aa2
AV		 1786 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_2))
1787 && !(type == REG_TYPE_NQ
1788 && ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)))
477330fc 1789 {
57785aa2
AV		 1790 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
1791 first_error (_("only D and Q registers may be indexed"));
1792 else
1793 first_error (_("only D registers may be indexed"));
477330fc
RM		 1794 return FAIL;
1795 }
5f4273c7 1796
dcbf9037 1797 if ((atype.defined & NTA_HASINDEX) != 0)
477330fc
RM		 1798 {
1799 first_error (_("can't change index for operand"));
1800 return FAIL;
1801 }
dcbf9037
JB		 1802
1803 atype.defined |= NTA_HASINDEX;
1804
1805 if (skip_past_char (&str, ']') == SUCCESS)
477330fc 1806 atype.index = NEON_ALL_LANES;
dcbf9037 1807 else
477330fc
RM		 1808 {
1809 expressionS exp;
dcbf9037 1810
477330fc 1811 my_get_expression (&exp, &str, GE_NO_PREFIX);
dcbf9037 1812
477330fc
RM		 1813 if (exp.X_op != O_constant)
1814 {
1815 first_error (_("constant expression required"));
1816 return FAIL;
1817 }
dcbf9037 1818
477330fc
RM		 1819 if (skip_past_char (&str, ']') == FAIL)
1820 return FAIL;
dcbf9037 1821
477330fc
RM		 1822 atype.index = exp.X_add_number;
1823 }
dcbf9037 1824 }
5f4273c7 1825
dcbf9037
JB		 1826 if (typeinfo)
1827 *typeinfo = atype;
5f4273c7 1828
dcbf9037
JB		 1829 if (rtype)
1830 *rtype = type;
5f4273c7 1831
dcbf9037 1832 *ccp = str;
5f4273c7 1833
dcbf9037
JB		 1834 return reg->number;
1835}
1836
efd6b359 1837/* Like arm_reg_parse, but also allow the following extra features:
dcbf9037
JB		 1838 - If RTYPE is non-zero, return the (possibly restricted) type of the
1839 register (e.g. Neon double or quad reg when either has been requested).
1840 - If this is a Neon vector type with additional type information, fill
1841 in the struct pointed to by VECTYPE (if non-NULL).
5f4273c7 1842 This function will fault on encountering a scalar. */
dcbf9037
JB		 1843
1844static int
1845arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
477330fc 1846 enum arm_reg_type *rtype, struct neon_type_el *vectype)
dcbf9037
JB		 1847{
1848 struct neon_typed_alias atype;
1849 char *str = *ccp;
1850 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1851
1852 if (reg == FAIL)
1853 return FAIL;
1854
0855e32b
NS		 1855 /* Do not allow regname(... to parse as a register. */
1856 if (*str == '(')
1857 return FAIL;
1858
dcbf9037
JB		 1859 /* Do not allow a scalar (reg+index) to parse as a register. */
1860 if ((atype.defined & NTA_HASINDEX) != 0)
1861 {
1862 first_error (_("register operand expected, but got scalar"));
1863 return FAIL;
1864 }
1865
1866 if (vectype)
1867 *vectype = atype.eltype;
1868
1869 *ccp = str;
1870
1871 return reg;
1872}
1873
1874#define NEON_SCALAR_REG(X) ((X) >> 4)
1875#define NEON_SCALAR_INDEX(X) ((X) & 15)
1876
5287ad62
JB		 1877/* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1878 have enough information to be able to do a good job bounds-checking. So, we
1879 just do easy checks here, and do further checks later. */
1880
1881static int
57785aa2
AV		 1882parse_scalar (char **ccp, int elsize, struct neon_type_el *type, enum
1883 arm_reg_type reg_type)
5287ad62 1884{
dcbf9037 1885 int reg;
5287ad62 1886 char *str = *ccp;
dcbf9037 1887 struct neon_typed_alias atype;
57785aa2 1888 unsigned reg_size;
5f4273c7 1889
dec41383 1890 reg = parse_typed_reg_or_scalar (&str, reg_type, NULL, &atype);
5f4273c7 1891
57785aa2
AV		 1892 switch (reg_type)
1893 {
1894 case REG_TYPE_VFS:
1895 reg_size = 32;
1896 break;
1897 case REG_TYPE_VFD:
1898 reg_size = 64;
1899 break;
1900 case REG_TYPE_MQ:
1901 reg_size = 128;
1902 break;
1903 default:
1904 gas_assert (0);
1905 return FAIL;
1906 }
1907
dcbf9037 1908 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
5287ad62 1909 return FAIL;
5f4273c7 1910
57785aa2 1911 if (reg_type != REG_TYPE_MQ && atype.index == NEON_ALL_LANES)
5287ad62 1912 {
dcbf9037 1913 first_error (_("scalar must have an index"));
5287ad62
JB		 1914 return FAIL;
1915 }
57785aa2 1916 else if (atype.index >= reg_size / elsize)
5287ad62 1917 {
dcbf9037 1918 first_error (_("scalar index out of range"));
5287ad62
JB		 1919 return FAIL;
1920 }
5f4273c7 1921
dcbf9037
JB		 1922 if (type)
1923 *type = atype.eltype;
5f4273c7 1924
5287ad62 1925 *ccp = str;
5f4273c7 1926
dcbf9037 1927 return reg * 16 + atype.index;
5287ad62
JB		 1928}
1929
4b5a202f
AV		 1930/* Types of registers in a list. */
1931
1932enum reg_list_els
1933{
1934 REGLIST_RN,
1935 REGLIST_CLRM,
1936 REGLIST_VFP_S,
efd6b359 1937 REGLIST_VFP_S_VPR,
4b5a202f 1938 REGLIST_VFP_D,
efd6b359 1939 REGLIST_VFP_D_VPR,
4b5a202f
AV		 1940 REGLIST_NEON_D
1941};
1942
c19d1205 1943/* Parse an ARM register list. Returns the bitmask, or FAIL. */
e07e6e58 1944
c19d1205 1945static long
4b5a202f 1946parse_reg_list (char ** strp, enum reg_list_els etype)
c19d1205 1947{
4b5a202f
AV		 1948 char *str = *strp;
1949 long range = 0;
1950 int another_range;
1951
1952 gas_assert (etype == REGLIST_RN || etype == REGLIST_CLRM);
a737bd4d 1953
c19d1205
ZW		 1954 /* We come back here if we get ranges concatenated by '+' or '|'. */
1955 do
6057a28f 1956 {
477330fc
RM		 1957 skip_whitespace (str);
1958
c19d1205 1959 another_range = 0;
a737bd4d 1960
c19d1205
ZW		 1961 if (*str == '{')
1962 {
1963 int in_range = 0;
1964 int cur_reg = -1;
a737bd4d 1965
c19d1205
ZW		 1966 str++;
1967 do
1968 {
1969 int reg;
4b5a202f
AV		 1970 const char apsr_str[] = "apsr";
1971 int apsr_str_len = strlen (apsr_str);
6057a28f 1972
a65b5de6 1973 reg = arm_reg_parse (&str, REG_TYPE_RN);
4b5a202f 1974 if (etype == REGLIST_CLRM)
c19d1205 1975 {
4b5a202f
AV		 1976 if (reg == REG_SP || reg == REG_PC)
1977 reg = FAIL;
1978 else if (reg == FAIL
1979 && !strncasecmp (str, apsr_str, apsr_str_len)
1980 && !ISALPHA (*(str + apsr_str_len)))
1981 {
1982 reg = 15;
1983 str += apsr_str_len;
1984 }
1985
1986 if (reg == FAIL)
1987 {
1988 first_error (_("r0-r12, lr or APSR expected"));
1989 return FAIL;
1990 }
1991 }
1992 else /* etype == REGLIST_RN. */
1993 {
1994 if (reg == FAIL)
1995 {
1996 first_error (_(reg_expected_msgs[REGLIST_RN]));
1997 return FAIL;
1998 }
c19d1205 1999 }
a737bd4d 2000
c19d1205
ZW		 2001 if (in_range)
2002 {
2003 int i;
a737bd4d 2004
c19d1205
ZW		 2005 if (reg <= cur_reg)
2006 {
dcbf9037 2007 first_error (_("bad range in register list"));
c19d1205
ZW		 2008 return FAIL;
2009 }
40a18ebd 2010
c19d1205
ZW		 2011 for (i = cur_reg + 1; i < reg; i++)
2012 {
2013 if (range & (1 << i))
2014 as_tsktsk
2015 (_("Warning: duplicated register (r%d) in register list"),
2016 i);
2017 else
2018 range |= 1 << i;
2019 }
2020 in_range = 0;
2021 }
a737bd4d 2022
c19d1205
ZW		 2023 if (range & (1 << reg))
2024 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
2025 reg);
2026 else if (reg <= cur_reg)
2027 as_tsktsk (_("Warning: register range not in ascending order"));
a737bd4d 2028
c19d1205
ZW		 2029 range |= 1 << reg;
2030 cur_reg = reg;
2031 }
2032 while (skip_past_comma (&str) != FAIL
2033 || (in_range = 1, *str++ == '-'));
2034 str--;
a737bd4d 2035
d996d970 2036 if (skip_past_char (&str, '}') == FAIL)
c19d1205 2037 {
dcbf9037 2038 first_error (_("missing `}'"));
c19d1205
ZW		 2039 return FAIL;
2040 }
2041 }
4b5a202f 2042 else if (etype == REGLIST_RN)
c19d1205 2043 {
91d6fa6a 2044 expressionS exp;
40a18ebd 2045
91d6fa6a 2046 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
c19d1205 2047 return FAIL;
40a18ebd 2048
91d6fa6a 2049 if (exp.X_op == O_constant)
c19d1205 2050 {
91d6fa6a
NC		 2051 if (exp.X_add_number
2052 != (exp.X_add_number & 0x0000ffff))
c19d1205
ZW		 2053 {
2054 inst.error = _("invalid register mask");
2055 return FAIL;
2056 }
a737bd4d 2057
91d6fa6a 2058 if ((range & exp.X_add_number) != 0)
c19d1205 2059 {
91d6fa6a 2060 int regno = range & exp.X_add_number;
a737bd4d 2061
c19d1205
ZW		 2062 regno &= -regno;
2063 regno = (1 << regno) - 1;
2064 as_tsktsk
2065 (_("Warning: duplicated register (r%d) in register list"),
2066 regno);
2067 }
a737bd4d 2068
91d6fa6a 2069 range |= exp.X_add_number;
c19d1205
ZW		 2070 }
2071 else
2072 {
e2b0ab59 2073 if (inst.relocs[0].type != 0)
c19d1205
ZW		 2074 {
2075 inst.error = _("expression too complex");
2076 return FAIL;
2077 }
a737bd4d 2078
e2b0ab59
AV		 2079 memcpy (&inst.relocs[0].exp, &exp, sizeof (expressionS));
2080 inst.relocs[0].type = BFD_RELOC_ARM_MULTI;
2081 inst.relocs[0].pc_rel = 0;
c19d1205
ZW		 2082 }
2083 }
a737bd4d 2084
c19d1205
ZW		 2085 if (*str == '|' || *str == '+')
2086 {
2087 str++;
2088 another_range = 1;
2089 }
a737bd4d 2090 }
c19d1205 2091 while (another_range);
a737bd4d 2092
c19d1205
ZW		 2093 *strp = str;
2094 return range;
a737bd4d
NC		 2095}
2096
c19d1205
ZW		 2097/* Parse a VFP register list. If the string is invalid return FAIL.
2098 Otherwise return the number of registers, and set PBASE to the first
5287ad62
JB		 2099 register. Parses registers of type ETYPE.
2100 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
2101 - Q registers can be used to specify pairs of D registers
2102 - { } can be omitted from around a singleton register list
477330fc
RM		 2103 FIXME: This is not implemented, as it would require backtracking in
2104 some cases, e.g.:
2105 vtbl.8 d3,d4,d5
2106 This could be done (the meaning isn't really ambiguous), but doesn't
2107 fit in well with the current parsing framework.
dcbf9037
JB		 2108 - 32 D registers may be used (also true for VFPv3).
2109 FIXME: Types are ignored in these register lists, which is probably a
2110 bug. */
6057a28f 2111
c19d1205 2112static int
efd6b359
AV		 2113parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype,
2114 bfd_boolean *partial_match)
6057a28f 2115{
037e8744 2116 char *str = *ccp;
c19d1205
ZW		 2117 int base_reg;
2118 int new_base;
21d799b5 2119 enum arm_reg_type regtype = (enum arm_reg_type) 0;
5287ad62 2120 int max_regs = 0;
c19d1205
ZW		 2121 int count = 0;
2122 int warned = 0;
2123 unsigned long mask = 0;
a737bd4d 2124 int i;
efd6b359
AV		 2125 bfd_boolean vpr_seen = FALSE;
2126 bfd_boolean expect_vpr =
2127 (etype == REGLIST_VFP_S_VPR) || (etype == REGLIST_VFP_D_VPR);
6057a28f 2128
477330fc 2129 if (skip_past_char (&str, '{') == FAIL)
5287ad62
JB		 2130 {
2131 inst.error = _("expecting {");
2132 return FAIL;
2133 }
6057a28f 2134
5287ad62 2135 switch (etype)
c19d1205 2136 {
5287ad62 2137 case REGLIST_VFP_S:
efd6b359 2138 case REGLIST_VFP_S_VPR:
c19d1205
ZW		 2139 regtype = REG_TYPE_VFS;
2140 max_regs = 32;
5287ad62 2141 break;
5f4273c7 2142
5287ad62 2143 case REGLIST_VFP_D:
efd6b359 2144 case REGLIST_VFP_D_VPR:
5287ad62 2145 regtype = REG_TYPE_VFD;
b7fc2769 2146 break;
5f4273c7 2147
b7fc2769
JB		 2148 case REGLIST_NEON_D:
2149 regtype = REG_TYPE_NDQ;
2150 break;
4b5a202f
AV		 2151
2152 default:
2153 gas_assert (0);
b7fc2769
JB		 2154 }
2155
efd6b359 2156 if (etype != REGLIST_VFP_S && etype != REGLIST_VFP_S_VPR)
b7fc2769 2157 {
b1cc4aeb
PB		 2158 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2159 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
477330fc
RM		 2160 {
2161 max_regs = 32;
2162 if (thumb_mode)
2163 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
2164 fpu_vfp_ext_d32);
2165 else
2166 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
2167 fpu_vfp_ext_d32);
2168 }
5287ad62 2169 else
477330fc 2170 max_regs = 16;
c19d1205 2171 }
6057a28f 2172
c19d1205 2173 base_reg = max_regs;
efd6b359 2174 *partial_match = FALSE;
a737bd4d 2175
c19d1205
ZW		 2176 do
2177 {
5287ad62 2178 int setmask = 1, addregs = 1;
efd6b359
AV		 2179 const char vpr_str[] = "vpr";
2180 int vpr_str_len = strlen (vpr_str);
dcbf9037 2181
037e8744 2182 new_base = arm_typed_reg_parse (&str, regtype, &regtype, NULL);
dcbf9037 2183
efd6b359
AV		 2184 if (expect_vpr)
2185 {
2186 if (new_base == FAIL
2187 && !strncasecmp (str, vpr_str, vpr_str_len)
2188 && !ISALPHA (*(str + vpr_str_len))
2189 && !vpr_seen)
2190 {
2191 vpr_seen = TRUE;
2192 str += vpr_str_len;
2193 if (count == 0)
2194 base_reg = 0; /* Canonicalize VPR only on d0 with 0 regs. */
2195 }
2196 else if (vpr_seen)
2197 {
2198 first_error (_("VPR expected last"));
2199 return FAIL;
2200 }
2201 else if (new_base == FAIL)
2202 {
2203 if (regtype == REG_TYPE_VFS)
2204 first_error (_("VFP single precision register or VPR "
2205 "expected"));
2206 else /* regtype == REG_TYPE_VFD. */
2207 first_error (_("VFP/Neon double precision register or VPR "
2208 "expected"));
2209 return FAIL;
2210 }
2211 }
2212 else if (new_base == FAIL)
a737bd4d 2213 {
dcbf9037 2214 first_error (_(reg_expected_msgs[regtype]));
c19d1205
ZW		 2215 return FAIL;
2216 }
5f4273c7 2217
efd6b359
AV		 2218 *partial_match = TRUE;
2219 if (vpr_seen)
2220 continue;
2221
b7fc2769 2222 if (new_base >= max_regs)
477330fc
RM		 2223 {
2224 first_error (_("register out of range in list"));
2225 return FAIL;
2226 }
5f4273c7 2227
5287ad62
JB		 2228 /* Note: a value of 2 * n is returned for the register Q<n>. */
2229 if (regtype == REG_TYPE_NQ)
477330fc
RM		 2230 {
2231 setmask = 3;
2232 addregs = 2;
2233 }
5287ad62 2234
c19d1205
ZW		 2235 if (new_base < base_reg)
2236 base_reg = new_base;
a737bd4d 2237
5287ad62 2238 if (mask & (setmask << new_base))
c19d1205 2239 {
dcbf9037 2240 first_error (_("invalid register list"));
c19d1205 2241 return FAIL;
a737bd4d 2242 }
a737bd4d 2243
efd6b359 2244 if ((mask >> new_base) != 0 && ! warned && !vpr_seen)
c19d1205
ZW		 2245 {
2246 as_tsktsk (_("register list not in ascending order"));
2247 warned = 1;
2248 }
0bbf2aa4 2249
5287ad62
JB		 2250 mask |= setmask << new_base;
2251 count += addregs;
0bbf2aa4 2252
037e8744 2253 if (*str == '-') /* We have the start of a range expression */
c19d1205
ZW		 2254 {
2255 int high_range;
0bbf2aa4 2256
037e8744 2257 str++;
0bbf2aa4 2258
037e8744 2259 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
477330fc 2260 == FAIL)
c19d1205
ZW		 2261 {
2262 inst.error = gettext (reg_expected_msgs[regtype]);
2263 return FAIL;
2264 }
0bbf2aa4 2265
477330fc
RM		 2266 if (high_range >= max_regs)
2267 {
2268 first_error (_("register out of range in list"));
2269 return FAIL;
2270 }
b7fc2769 2271
477330fc
RM		 2272 if (regtype == REG_TYPE_NQ)
2273 high_range = high_range + 1;
5287ad62 2274
c19d1205
ZW		 2275 if (high_range <= new_base)
2276 {
2277 inst.error = _("register range not in ascending order");
2278 return FAIL;
2279 }
0bbf2aa4 2280
5287ad62 2281 for (new_base += addregs; new_base <= high_range; new_base += addregs)
0bbf2aa4 2282 {
5287ad62 2283 if (mask & (setmask << new_base))
0bbf2aa4 2284 {
c19d1205
ZW		 2285 inst.error = _("invalid register list");
2286 return FAIL;
0bbf2aa4 2287 }
c19d1205 2288
5287ad62
JB		 2289 mask |= setmask << new_base;
2290 count += addregs;
0bbf2aa4 2291 }
0bbf2aa4 2292 }
0bbf2aa4 2293 }
037e8744 2294 while (skip_past_comma (&str) != FAIL);
0bbf2aa4 2295
037e8744 2296 str++;
0bbf2aa4 2297
c19d1205 2298 /* Sanity check -- should have raised a parse error above. */
efd6b359 2299 if ((!vpr_seen && count == 0) || count > max_regs)
c19d1205
ZW		 2300 abort ();
2301
2302 *pbase = base_reg;
2303
efd6b359
AV		 2304 if (expect_vpr && !vpr_seen)
2305 {
2306 first_error (_("VPR expected last"));
2307 return FAIL;
2308 }
2309
c19d1205
ZW		 2310 /* Final test -- the registers must be consecutive. */
2311 mask >>= base_reg;
2312 for (i = 0; i < count; i++)
2313 {
2314 if ((mask & (1u << i)) == 0)
2315 {
2316 inst.error = _("non-contiguous register range");
2317 return FAIL;
2318 }
2319 }
2320
037e8744
JB		 2321 *ccp = str;
2322
c19d1205 2323 return count;
b99bd4ef
NC		 2324}
2325
dcbf9037
JB		 2326/* True if two alias types are the same. */
2327
c921be7d 2328static bfd_boolean
dcbf9037
JB		 2329neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
2330{
2331 if (!a && !b)
c921be7d 2332 return TRUE;
5f4273c7 2333
dcbf9037 2334 if (!a || !b)
c921be7d 2335 return FALSE;
dcbf9037
JB		 2336
2337 if (a->defined != b->defined)
c921be7d 2338 return FALSE;
5f4273c7 2339
dcbf9037
JB		 2340 if ((a->defined & NTA_HASTYPE) != 0
2341 && (a->eltype.type != b->eltype.type
477330fc 2342 || a->eltype.size != b->eltype.size))
c921be7d 2343 return FALSE;
dcbf9037
JB		 2344
2345 if ((a->defined & NTA_HASINDEX) != 0
2346 && (a->index != b->index))
c921be7d 2347 return FALSE;
5f4273c7 2348
c921be7d 2349 return TRUE;
dcbf9037
JB		 2350}
2351
5287ad62
JB		 2352/* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2353 The base register is put in *PBASE.
dcbf9037 2354 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
5287ad62
JB		 2355 the return value.
2356 The register stride (minus one) is put in bit 4 of the return value.
dcbf9037
JB		 2357 Bits [6:5] encode the list length (minus one).
2358 The type of the list elements is put in *ELTYPE, if non-NULL. */
5287ad62 2359
5287ad62 2360#define NEON_LANE(X) ((X) & 0xf)
dcbf9037 2361#define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
5287ad62
JB		 2362#define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2363
2364static int
dcbf9037 2365parse_neon_el_struct_list (char **str, unsigned *pbase,
35c228db 2366 int mve,
477330fc 2367 struct neon_type_el *eltype)
5287ad62
JB		 2368{
2369 char *ptr = *str;
2370 int base_reg = -1;
2371 int reg_incr = -1;
2372 int count = 0;
2373 int lane = -1;
2374 int leading_brace = 0;
2375 enum arm_reg_type rtype = REG_TYPE_NDQ;
35c228db
AV		 2376 const char *const incr_error = mve ? _("register stride must be 1") :
2377 _("register stride must be 1 or 2");
20203fb9 2378 const char *const type_error = _("mismatched element/structure types in list");
dcbf9037 2379 struct neon_typed_alias firsttype;
f85d59c3
KT		 2380 firsttype.defined = 0;
2381 firsttype.eltype.type = NT_invtype;
2382 firsttype.eltype.size = -1;
2383 firsttype.index = -1;
5f4273c7 2384
5287ad62
JB		 2385 if (skip_past_char (&ptr, '{') == SUCCESS)
2386 leading_brace = 1;
5f4273c7 2387
5287ad62
JB		 2388 do
2389 {
dcbf9037 2390 struct neon_typed_alias atype;
35c228db
AV		 2391 if (mve)
2392 rtype = REG_TYPE_MQ;
dcbf9037
JB		 2393 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
2394
5287ad62 2395 if (getreg == FAIL)
477330fc
RM		 2396 {
2397 first_error (_(reg_expected_msgs[rtype]));
2398 return FAIL;
2399 }
5f4273c7 2400
5287ad62 2401 if (base_reg == -1)
477330fc
RM		 2402 {
2403 base_reg = getreg;
2404 if (rtype == REG_TYPE_NQ)
2405 {
2406 reg_incr = 1;
2407 }
2408 firsttype = atype;
2409 }
5287ad62 2410 else if (reg_incr == -1)
477330fc
RM		 2411 {
2412 reg_incr = getreg - base_reg;
2413 if (reg_incr < 1 || reg_incr > 2)
2414 {
2415 first_error (_(incr_error));
2416 return FAIL;
2417 }
2418 }
5287ad62 2419 else if (getreg != base_reg + reg_incr * count)
477330fc
RM		 2420 {
2421 first_error (_(incr_error));
2422 return FAIL;
2423 }
dcbf9037 2424
c921be7d 2425 if (! neon_alias_types_same (&atype, &firsttype))
477330fc
RM		 2426 {
2427 first_error (_(type_error));
2428 return FAIL;
2429 }
5f4273c7 2430
5287ad62 2431 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
477330fc 2432 modes. */
5287ad62 2433 if (ptr[0] == '-')
477330fc
RM		 2434 {
2435 struct neon_typed_alias htype;
2436 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
2437 if (lane == -1)
2438 lane = NEON_INTERLEAVE_LANES;
2439 else if (lane != NEON_INTERLEAVE_LANES)
2440 {
2441 first_error (_(type_error));
2442 return FAIL;
2443 }
2444 if (reg_incr == -1)
2445 reg_incr = 1;
2446 else if (reg_incr != 1)
2447 {
2448 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2449 return FAIL;
2450 }
2451 ptr++;
2452 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2453 if (hireg == FAIL)
2454 {
2455 first_error (_(reg_expected_msgs[rtype]));
2456 return FAIL;
2457 }
2458 if (! neon_alias_types_same (&htype, &firsttype))
2459 {
2460 first_error (_(type_error));
2461 return FAIL;
2462 }
2463 count += hireg + dregs - getreg;
2464 continue;
2465 }
5f4273c7 2466
5287ad62
JB		 2467 /* If we're using Q registers, we can't use [] or [n] syntax. */
2468 if (rtype == REG_TYPE_NQ)
477330fc
RM		 2469 {
2470 count += 2;
2471 continue;
2472 }
5f4273c7 2473
dcbf9037 2474 if ((atype.defined & NTA_HASINDEX) != 0)
477330fc
RM		 2475 {
2476 if (lane == -1)
2477 lane = atype.index;
2478 else if (lane != atype.index)
2479 {
2480 first_error (_(type_error));
2481 return FAIL;
2482 }
2483 }
5287ad62 2484 else if (lane == -1)
477330fc 2485 lane = NEON_INTERLEAVE_LANES;
5287ad62 2486 else if (lane != NEON_INTERLEAVE_LANES)
477330fc
RM		 2487 {
2488 first_error (_(type_error));
2489 return FAIL;
2490 }
5287ad62
JB		 2491 count++;
2492 }
2493 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
5f4273c7 2494
5287ad62
JB		 2495 /* No lane set by [x]. We must be interleaving structures. */
2496 if (lane == -1)
2497 lane = NEON_INTERLEAVE_LANES;
5f4273c7 2498
5287ad62 2499 /* Sanity check. */
35c228db 2500 if (lane == -1 || base_reg == -1 || count < 1 || (!mve && count > 4)
5287ad62
JB		 2501 || (count > 1 && reg_incr == -1))
2502 {
dcbf9037 2503 first_error (_("error parsing element/structure list"));
5287ad62
JB		 2504 return FAIL;
2505 }
2506
2507 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2508 {
dcbf9037 2509 first_error (_("expected }"));
5287ad62
JB		 2510 return FAIL;
2511 }
5f4273c7 2512
5287ad62
JB		 2513 if (reg_incr == -1)
2514 reg_incr = 1;
2515
dcbf9037
JB		 2516 if (eltype)
2517 *eltype = firsttype.eltype;
2518
5287ad62
JB		 2519 *pbase = base_reg;
2520 *str = ptr;
5f4273c7 2521
5287ad62
JB		 2522 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2523}
2524
c19d1205
ZW		 2525/* Parse an explicit relocation suffix on an expression. This is
2526 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2527 arm_reloc_hsh contains no entries, so this function can only
2528 succeed if there is no () after the word. Returns -1 on error,
2529 BFD_RELOC_UNUSED if there wasn't any suffix. */
3da1d841 2530
c19d1205
ZW		 2531static int
2532parse_reloc (char **str)
b99bd4ef 2533{
c19d1205
ZW		 2534 struct reloc_entry *r;
2535 char *p, *q;
b99bd4ef 2536
c19d1205
ZW		 2537 if (**str != '(')
2538 return BFD_RELOC_UNUSED;
b99bd4ef 2539
c19d1205
ZW		 2540 p = *str + 1;
2541 q = p;
2542
2543 while (*q && *q != ')' && *q != ',')
2544 q++;
2545 if (*q != ')')
2546 return -1;
2547
21d799b5
NC		 2548 if ((r = (struct reloc_entry *)
2549 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
c19d1205
ZW		 2550 return -1;
2551
2552 *str = q + 1;
2553 return r->reloc;
b99bd4ef
NC		 2554}
2555
c19d1205
ZW		 2556/* Directives: register aliases. */
2557
dcbf9037 2558static struct reg_entry *
90ec0d68 2559insert_reg_alias (char *str, unsigned number, int type)
b99bd4ef 2560{
d3ce72d0 2561 struct reg_entry *new_reg;
c19d1205 2562 const char *name;
b99bd4ef 2563
d3ce72d0 2564 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
c19d1205 2565 {
d3ce72d0 2566 if (new_reg->builtin)
c19d1205 2567 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
b99bd4ef 2568
c19d1205
ZW		 2569 /* Only warn about a redefinition if it's not defined as the
2570 same register. */
d3ce72d0 2571 else if (new_reg->number != number || new_reg->type != type)
c19d1205 2572 as_warn (_("ignoring redefinition of register alias '%s'"), str);
69b97547 2573
d929913e 2574 return NULL;
c19d1205 2575 }
b99bd4ef 2576
c19d1205 2577 name = xstrdup (str);
325801bd 2578 new_reg = XNEW (struct reg_entry);
b99bd4ef 2579
d3ce72d0
NC		 2580 new_reg->name = name;
2581 new_reg->number = number;
2582 new_reg->type = type;
2583 new_reg->builtin = FALSE;
2584 new_reg->neon = NULL;
b99bd4ef 2585
d3ce72d0 2586 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
c19d1205 2587 abort ();
5f4273c7 2588
d3ce72d0 2589 return new_reg;
dcbf9037
JB		 2590}
2591
2592static void
2593insert_neon_reg_alias (char *str, int number, int type,
477330fc 2594 struct neon_typed_alias *atype)
dcbf9037
JB		 2595{
2596 struct reg_entry *reg = insert_reg_alias (str, number, type);
5f4273c7 2597
dcbf9037
JB		 2598 if (!reg)
2599 {
2600 first_error (_("attempt to redefine typed alias"));
2601 return;
2602 }
5f4273c7 2603
dcbf9037
JB		 2604 if (atype)
2605 {
325801bd 2606 reg->neon = XNEW (struct neon_typed_alias);
dcbf9037
JB		 2607 *reg->neon = *atype;
2608 }
c19d1205 2609}
b99bd4ef 2610
c19d1205 2611/* Look for the .req directive. This is of the form:
b99bd4ef 2612
c19d1205 2613 new_register_name .req existing_register_name
b99bd4ef 2614
c19d1205 2615 If we find one, or if it looks sufficiently like one that we want to
d929913e 2616 handle any error here, return TRUE. Otherwise return FALSE. */
b99bd4ef 2617
d929913e 2618static bfd_boolean
c19d1205
ZW		 2619create_register_alias (char * newname, char *p)
2620{
2621 struct reg_entry *old;
2622 char *oldname, *nbuf;
2623 size_t nlen;
b99bd4ef 2624
c19d1205
ZW		 2625 /* The input scrubber ensures that whitespace after the mnemonic is
2626 collapsed to single spaces. */
2627 oldname = p;
2628 if (strncmp (oldname, " .req ", 6) != 0)
d929913e 2629 return FALSE;
b99bd4ef 2630
c19d1205
ZW		 2631 oldname += 6;
2632 if (*oldname == '\0')
d929913e 2633 return FALSE;
b99bd4ef 2634
21d799b5 2635 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
c19d1205 2636 if (!old)
b99bd4ef 2637 {
c19d1205 2638 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
d929913e 2639 return TRUE;
b99bd4ef
NC		 2640 }
2641
c19d1205
ZW		 2642 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2643 the desired alias name, and p points to its end. If not, then
2644 the desired alias name is in the global original_case_string. */
2645#ifdef TC_CASE_SENSITIVE
2646 nlen = p - newname;
2647#else
2648 newname = original_case_string;
2649 nlen = strlen (newname);
2650#endif
b99bd4ef 2651
29a2809e 2652 nbuf = xmemdup0 (newname, nlen);
b99bd4ef 2653
c19d1205
ZW		 2654 /* Create aliases under the new name as stated; an all-lowercase
2655 version of the new name; and an all-uppercase version of the new
2656 name. */
d929913e
NC		 2657 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2658 {
2659 for (p = nbuf; *p; p++)
2660 *p = TOUPPER (*p);
c19d1205 2661
d929913e
NC		 2662 if (strncmp (nbuf, newname, nlen))
2663 {
2664 /* If this attempt to create an additional alias fails, do not bother
2665 trying to create the all-lower case alias. We will fail and issue
2666 a second, duplicate error message. This situation arises when the
2667 programmer does something like:
2668 foo .req r0
2669 Foo .req r1
2670 The second .req creates the "Foo" alias but then fails to create
5f4273c7 2671 the artificial FOO alias because it has already been created by the
d929913e
NC		 2672 first .req. */
2673 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
e1fa0163
NC		 2674 {
2675 free (nbuf);
2676 return TRUE;
2677 }
d929913e 2678 }
c19d1205 2679
d929913e
NC		 2680 for (p = nbuf; *p; p++)
2681 *p = TOLOWER (*p);
c19d1205 2682
d929913e
NC		 2683 if (strncmp (nbuf, newname, nlen))
2684 insert_reg_alias (nbuf, old->number, old->type);
2685 }
c19d1205 2686
e1fa0163 2687 free (nbuf);
d929913e 2688 return TRUE;
b99bd4ef
NC		 2689}
2690
dcbf9037
JB		 2691/* Create a Neon typed/indexed register alias using directives, e.g.:
2692 X .dn d5.s32[1]
2693 Y .qn 6.s16
2694 Z .dn d7
2695 T .dn Z[0]
2696 These typed registers can be used instead of the types specified after the
2697 Neon mnemonic, so long as all operands given have types. Types can also be
2698 specified directly, e.g.:
5f4273c7 2699 vadd d0.s32, d1.s32, d2.s32 */
dcbf9037 2700
c921be7d 2701static bfd_boolean
dcbf9037
JB		 2702create_neon_reg_alias (char *newname, char *p)
2703{
2704 enum arm_reg_type basetype;
2705 struct reg_entry *basereg;
2706 struct reg_entry mybasereg;
2707 struct neon_type ntype;
2708 struct neon_typed_alias typeinfo;
12d6b0b7 2709 char *namebuf, *nameend ATTRIBUTE_UNUSED;
dcbf9037 2710 int namelen;
5f4273c7 2711
dcbf9037
JB		 2712 typeinfo.defined = 0;
2713 typeinfo.eltype.type = NT_invtype;
2714 typeinfo.eltype.size = -1;
2715 typeinfo.index = -1;
5f4273c7 2716
dcbf9037 2717 nameend = p;
5f4273c7 2718
dcbf9037
JB		 2719 if (strncmp (p, " .dn ", 5) == 0)
2720 basetype = REG_TYPE_VFD;
2721 else if (strncmp (p, " .qn ", 5) == 0)
2722 basetype = REG_TYPE_NQ;
2723 else
c921be7d 2724 return FALSE;
5f4273c7 2725
dcbf9037 2726 p += 5;
5f4273c7 2727
dcbf9037 2728 if (*p == '\0')
c921be7d 2729 return FALSE;
5f4273c7 2730
dcbf9037
JB		 2731 basereg = arm_reg_parse_multi (&p);
2732
2733 if (basereg && basereg->type != basetype)
2734 {
2735 as_bad (_("bad type for register"));
c921be7d 2736 return FALSE;
dcbf9037
JB		 2737 }
2738
2739 if (basereg == NULL)
2740 {
2741 expressionS exp;
2742 /* Try parsing as an integer. */
2743 my_get_expression (&exp, &p, GE_NO_PREFIX);
2744 if (exp.X_op != O_constant)
477330fc
RM		 2745 {
2746 as_bad (_("expression must be constant"));
2747 return FALSE;
2748 }
dcbf9037
JB		 2749 basereg = &mybasereg;
2750 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
477330fc 2751 : exp.X_add_number;
dcbf9037
JB		 2752 basereg->neon = 0;
2753 }
2754
2755 if (basereg->neon)
2756 typeinfo = *basereg->neon;
2757
2758 if (parse_neon_type (&ntype, &p) == SUCCESS)
2759 {
2760 /* We got a type. */
2761 if (typeinfo.defined & NTA_HASTYPE)
477330fc
RM		 2762 {
2763 as_bad (_("can't redefine the type of a register alias"));
2764 return FALSE;
2765 }
5f4273c7 2766
dcbf9037
JB		 2767 typeinfo.defined |= NTA_HASTYPE;
2768 if (ntype.elems != 1)
477330fc
RM		 2769 {
2770 as_bad (_("you must specify a single type only"));
2771 return FALSE;
2772 }
dcbf9037
JB		 2773 typeinfo.eltype = ntype.el[0];
2774 }
5f4273c7 2775
dcbf9037
JB		 2776 if (skip_past_char (&p, '[') == SUCCESS)
2777 {
2778 expressionS exp;
2779 /* We got a scalar index. */
5f4273c7 2780
dcbf9037 2781 if (typeinfo.defined & NTA_HASINDEX)
477330fc
RM		 2782 {
2783 as_bad (_("can't redefine the index of a scalar alias"));
2784 return FALSE;
2785 }
5f4273c7 2786
dcbf9037 2787 my_get_expression (&exp, &p, GE_NO_PREFIX);
5f4273c7 2788
dcbf9037 2789 if (exp.X_op != O_constant)
477330fc
RM		 2790 {
2791 as_bad (_("scalar index must be constant"));
2792 return FALSE;
2793 }
5f4273c7 2794
dcbf9037
JB		 2795 typeinfo.defined |= NTA_HASINDEX;
2796 typeinfo.index = exp.X_add_number;
5f4273c7 2797
dcbf9037 2798 if (skip_past_char (&p, ']') == FAIL)
477330fc
RM		 2799 {
2800 as_bad (_("expecting ]"));
2801 return FALSE;
2802 }
dcbf9037
JB		 2803 }
2804
15735687
NS		 2805 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2806 the desired alias name, and p points to its end. If not, then
2807 the desired alias name is in the global original_case_string. */
2808#ifdef TC_CASE_SENSITIVE
dcbf9037 2809 namelen = nameend - newname;
15735687
NS		 2810#else
2811 newname = original_case_string;
2812 namelen = strlen (newname);
2813#endif
2814
29a2809e 2815 namebuf = xmemdup0 (newname, namelen);
5f4273c7 2816
dcbf9037 2817 insert_neon_reg_alias (namebuf, basereg->number, basetype,
477330fc 2818 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2819
dcbf9037
JB		 2820 /* Insert name in all uppercase. */
2821 for (p = namebuf; *p; p++)
2822 *p = TOUPPER (*p);
5f4273c7 2823
dcbf9037
JB		 2824 if (strncmp (namebuf, newname, namelen))
2825 insert_neon_reg_alias (namebuf, basereg->number, basetype,
477330fc 2826 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2827
dcbf9037
JB		 2828 /* Insert name in all lowercase. */
2829 for (p = namebuf; *p; p++)
2830 *p = TOLOWER (*p);
5f4273c7 2831
dcbf9037
JB		 2832 if (strncmp (namebuf, newname, namelen))
2833 insert_neon_reg_alias (namebuf, basereg->number, basetype,
477330fc 2834 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2835
e1fa0163 2836 free (namebuf);
c921be7d 2837 return TRUE;
dcbf9037
JB		 2838}
2839
c19d1205
ZW		 2840/* Should never be called, as .req goes between the alias and the
2841 register name, not at the beginning of the line. */
c921be7d 2842
b99bd4ef 2843static void
c19d1205 2844s_req (int a ATTRIBUTE_UNUSED)
b99bd4ef 2845{
c19d1205
ZW		 2846 as_bad (_("invalid syntax for .req directive"));
2847}
b99bd4ef 2848
dcbf9037
JB		 2849static void
2850s_dn (int a ATTRIBUTE_UNUSED)
2851{
2852 as_bad (_("invalid syntax for .dn directive"));
2853}
2854
2855static void
2856s_qn (int a ATTRIBUTE_UNUSED)
2857{
2858 as_bad (_("invalid syntax for .qn directive"));
2859}
2860
c19d1205
ZW		 2861/* The .unreq directive deletes an alias which was previously defined
2862 by .req. For example:
b99bd4ef 2863
c19d1205
ZW		 2864 my_alias .req r11
2865 .unreq my_alias */
b99bd4ef
NC		 2866
2867static void
c19d1205 2868s_unreq (int a ATTRIBUTE_UNUSED)
b99bd4ef 2869{
c19d1205
ZW		 2870 char * name;
2871 char saved_char;
b99bd4ef 2872
c19d1205
ZW		 2873 name = input_line_pointer;
2874
2875 while (*input_line_pointer != 0
2876 && *input_line_pointer != ' '
2877 && *input_line_pointer != '\n')
2878 ++input_line_pointer;
2879
2880 saved_char = *input_line_pointer;
2881 *input_line_pointer = 0;
2882
2883 if (!*name)
2884 as_bad (_("invalid syntax for .unreq directive"));
2885 else
2886 {
21d799b5 2887 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
477330fc 2888 name);
c19d1205
ZW		 2889
2890 if (!reg)
2891 as_bad (_("unknown register alias '%s'"), name);
2892 else if (reg->builtin)
a1727c1a 2893 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
c19d1205
ZW		 2894 name);
2895 else
2896 {
d929913e
NC		 2897 char * p;
2898 char * nbuf;
2899
db0bc284 2900 hash_delete (arm_reg_hsh, name, FALSE);
c19d1205 2901 free ((char *) reg->name);
9fbb53c7 2902 free (reg->neon);
c19d1205 2903 free (reg);
d929913e
NC		 2904
2905 /* Also locate the all upper case and all lower case versions.
2906 Do not complain if we cannot find one or the other as it
2907 was probably deleted above. */
5f4273c7 2908
d929913e
NC		 2909 nbuf = strdup (name);
2910 for (p = nbuf; *p; p++)
2911 *p = TOUPPER (*p);
21d799b5 2912 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
d929913e
NC		 2913 if (reg)
2914 {
db0bc284 2915 hash_delete (arm_reg_hsh, nbuf, FALSE);
d929913e 2916 free ((char *) reg->name);
9fbb53c7 2917 free (reg->neon);
d929913e
NC		 2918 free (reg);
2919 }
2920
2921 for (p = nbuf; *p; p++)
2922 *p = TOLOWER (*p);
21d799b5 2923 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
d929913e
NC		 2924 if (reg)
2925 {
db0bc284 2926 hash_delete (arm_reg_hsh, nbuf, FALSE);
d929913e 2927 free ((char *) reg->name);
9fbb53c7 2928 free (reg->neon);
d929913e
NC		 2929 free (reg);
2930 }
2931
2932 free (nbuf);
c19d1205
ZW		 2933 }
2934 }
b99bd4ef 2935
c19d1205 2936 *input_line_pointer = saved_char;
b99bd4ef
NC		 2937 demand_empty_rest_of_line ();
2938}
2939
c19d1205
ZW		 2940/* Directives: Instruction set selection. */
2941
2942#ifdef OBJ_ELF
2943/* This code is to handle mapping symbols as defined in the ARM ELF spec.
2944 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2945 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2946 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2947
cd000bff
DJ		 2948/* Create a new mapping symbol for the transition to STATE. */
2949
2950static void
2951make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
b99bd4ef 2952{
a737bd4d 2953 symbolS * symbolP;
c19d1205
ZW		 2954 const char * symname;
2955 int type;
b99bd4ef 2956
c19d1205 2957 switch (state)
b99bd4ef 2958 {
c19d1205
ZW		 2959 case MAP_DATA:
2960 symname = "$d";
2961 type = BSF_NO_FLAGS;
2962 break;
2963 case MAP_ARM:
2964 symname = "$a";
2965 type = BSF_NO_FLAGS;
2966 break;
2967 case MAP_THUMB:
2968 symname = "$t";
2969 type = BSF_NO_FLAGS;
2970 break;
c19d1205
ZW		 2971 default:
2972 abort ();
2973 }
2974
cd000bff 2975 symbolP = symbol_new (symname, now_seg, value, frag);
c19d1205
ZW		 2976 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2977
2978 switch (state)
2979 {
2980 case MAP_ARM:
2981 THUMB_SET_FUNC (symbolP, 0);
2982 ARM_SET_THUMB (symbolP, 0);
2983 ARM_SET_INTERWORK (symbolP, support_interwork);
2984 break;
2985
2986 case MAP_THUMB:
2987 THUMB_SET_FUNC (symbolP, 1);
2988 ARM_SET_THUMB (symbolP, 1);
2989 ARM_SET_INTERWORK (symbolP, support_interwork);
2990 break;
2991
2992 case MAP_DATA:
2993 default:
cd000bff
DJ		 2994 break;
2995 }
2996
2997 /* Save the mapping symbols for future reference. Also check that
2998 we do not place two mapping symbols at the same offset within a
2999 frag. We'll handle overlap between frags in
2de7820f
JZ		 3000 check_mapping_symbols.
3001
3002 If .fill or other data filling directive generates zero sized data,
3003 the mapping symbol for the following code will have the same value
3004 as the one generated for the data filling directive. In this case,
3005 we replace the old symbol with the new one at the same address. */
cd000bff
DJ		 3006 if (value == 0)
3007 {
2de7820f
JZ		 3008 if (frag->tc_frag_data.first_map != NULL)
3009 {
3010 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
3011 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
3012 }
cd000bff
DJ		 3013 frag->tc_frag_data.first_map = symbolP;
3014 }
3015 if (frag->tc_frag_data.last_map != NULL)
0f020cef
JZ		 3016 {
3017 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
0f020cef
JZ		 3018 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
3019 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
3020 }
cd000bff
DJ		 3021 frag->tc_frag_data.last_map = symbolP;
3022}
3023
3024/* We must sometimes convert a region marked as code to data during
3025 code alignment, if an odd number of bytes have to be padded. The
3026 code mapping symbol is pushed to an aligned address. */
3027
3028static void
3029insert_data_mapping_symbol (enum mstate state,
3030 valueT value, fragS *frag, offsetT bytes)
3031{
3032 /* If there was already a mapping symbol, remove it. */
3033 if (frag->tc_frag_data.last_map != NULL
3034 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
3035 {
3036 symbolS *symp = frag->tc_frag_data.last_map;
3037
3038 if (value == 0)
3039 {
3040 know (frag->tc_frag_data.first_map == symp);
3041 frag->tc_frag_data.first_map = NULL;
3042 }
3043 frag->tc_frag_data.last_map = NULL;
3044 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
c19d1205 3045 }
cd000bff
DJ		 3046
3047 make_mapping_symbol (MAP_DATA, value, frag);
3048 make_mapping_symbol (state, value + bytes, frag);
3049}
3050
3051static void mapping_state_2 (enum mstate state, int max_chars);
3052
3053/* Set the mapping state to STATE. Only call this when about to
3054 emit some STATE bytes to the file. */
3055
4e9aaefb 3056#define TRANSITION(from, to) (mapstate == (from) && state == (to))
cd000bff
DJ		 3057void
3058mapping_state (enum mstate state)
3059{
940b5ce0
DJ		 3060 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
3061
cd000bff
DJ		 3062 if (mapstate == state)
3063 /* The mapping symbol has already been emitted.
3064 There is nothing else to do. */
3065 return;
49c62a33
NC		 3066
3067 if (state == MAP_ARM || state == MAP_THUMB)
3068 /* PR gas/12931
3069 All ARM instructions require 4-byte alignment.
3070 (Almost) all Thumb instructions require 2-byte alignment.
3071
3072 When emitting instructions into any section, mark the section
3073 appropriately.
3074
3075 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
3076 but themselves require 2-byte alignment; this applies to some
33eaf5de 3077 PC- relative forms. However, these cases will involve implicit
49c62a33
NC		 3078 literal pool generation or an explicit .align >=2, both of
3079 which will cause the section to me marked with sufficient
3080 alignment. Thus, we don't handle those cases here. */
3081 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
3082
3083 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
4e9aaefb 3084 /* This case will be evaluated later. */
cd000bff 3085 return;
cd000bff
DJ		 3086
3087 mapping_state_2 (state, 0);
cd000bff
DJ		 3088}
3089
3090/* Same as mapping_state, but MAX_CHARS bytes have already been
3091 allocated. Put the mapping symbol that far back. */
3092
3093static void
3094mapping_state_2 (enum mstate state, int max_chars)
3095{
940b5ce0
DJ		 3096 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
3097
3098 if (!SEG_NORMAL (now_seg))
3099 return;
3100
cd000bff
DJ		 3101 if (mapstate == state)
3102 /* The mapping symbol has already been emitted.
3103 There is nothing else to do. */
3104 return;
3105
4e9aaefb
SA		 3106 if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
3107 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
3108 {
3109 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
3110 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
3111
3112 if (add_symbol)
3113 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
3114 }
3115
cd000bff
DJ		 3116 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
3117 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
c19d1205 3118}
4e9aaefb 3119#undef TRANSITION
c19d1205 3120#else
d3106081
NS		 3121#define mapping_state(x) ((void)0)
3122#define mapping_state_2(x, y) ((void)0)
c19d1205
ZW		 3123#endif
3124
3125/* Find the real, Thumb encoded start of a Thumb function. */
3126
4343666d 3127#ifdef OBJ_COFF
c19d1205
ZW		 3128static symbolS *
3129find_real_start (symbolS * symbolP)
3130{
3131 char * real_start;
3132 const char * name = S_GET_NAME (symbolP);
3133 symbolS * new_target;
3134
3135 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3136#define STUB_NAME ".real_start_of"
3137
3138 if (name == NULL)
3139 abort ();
3140
37f6032b
ZW		 3141 /* The compiler may generate BL instructions to local labels because
3142 it needs to perform a branch to a far away location. These labels
3143 do not have a corresponding ".real_start_of" label. We check
3144 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3145 the ".real_start_of" convention for nonlocal branches. */
3146 if (S_IS_LOCAL (symbolP) || name[0] == '.')
c19d1205
ZW		 3147 return symbolP;
3148
e1fa0163 3149 real_start = concat (STUB_NAME, name, NULL);
c19d1205 3150 new_target = symbol_find (real_start);
e1fa0163 3151 free (real_start);
c19d1205
ZW		 3152
3153 if (new_target == NULL)
3154 {
bd3ba5d1 3155 as_warn (_("Failed to find real start of function: %s\n"), name);
c19d1205
ZW		 3156 new_target = symbolP;
3157 }
3158
c19d1205
ZW		 3159 return new_target;
3160}
4343666d 3161#endif
c19d1205
ZW		 3162
3163static void
3164opcode_select (int width)
3165{
3166 switch (width)
3167 {
3168 case 16:
3169 if (! thumb_mode)
3170 {
e74cfd16 3171 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
c19d1205
ZW		 3172 as_bad (_("selected processor does not support THUMB opcodes"));
3173
3174 thumb_mode = 1;
3175 /* No need to force the alignment, since we will have been
3176 coming from ARM mode, which is word-aligned. */
3177 record_alignment (now_seg, 1);
3178 }
c19d1205
ZW		 3179 break;
3180
3181 case 32:
3182 if (thumb_mode)
3183 {
e74cfd16 3184 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
c19d1205
ZW		 3185 as_bad (_("selected processor does not support ARM opcodes"));
3186
3187 thumb_mode = 0;
3188
3189 if (!need_pass_2)
3190 frag_align (2, 0, 0);
3191
3192 record_alignment (now_seg, 1);
3193 }
c19d1205
ZW		 3194 break;
3195
3196 default:
3197 as_bad (_("invalid instruction size selected (%d)"), width);
3198 }
3199}
3200
3201static void
3202s_arm (int ignore ATTRIBUTE_UNUSED)
3203{
3204 opcode_select (32);
3205 demand_empty_rest_of_line ();
3206}
3207
3208static void
3209s_thumb (int ignore ATTRIBUTE_UNUSED)
3210{
3211 opcode_select (16);
3212 demand_empty_rest_of_line ();
3213}
3214
3215static void
3216s_code (int unused ATTRIBUTE_UNUSED)
3217{
3218 int temp;
3219
3220 temp = get_absolute_expression ();
3221 switch (temp)
3222 {
3223 case 16:
3224 case 32:
3225 opcode_select (temp);
3226 break;
3227
3228 default:
3229 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
3230 }
3231}
3232
3233static void
3234s_force_thumb (int ignore ATTRIBUTE_UNUSED)
3235{
3236 /* If we are not already in thumb mode go into it, EVEN if
3237 the target processor does not support thumb instructions.
3238 This is used by gcc/config/arm/lib1funcs.asm for example
3239 to compile interworking support functions even if the
3240 target processor should not support interworking. */
3241 if (! thumb_mode)
3242 {
3243 thumb_mode = 2;
3244 record_alignment (now_seg, 1);
3245 }
3246
3247 demand_empty_rest_of_line ();
3248}
3249
3250static void
3251s_thumb_func (int ignore ATTRIBUTE_UNUSED)
3252{
3253 s_thumb (0);
3254
3255 /* The following label is the name/address of the start of a Thumb function.
3256 We need to know this for the interworking support. */
3257 label_is_thumb_function_name = TRUE;
3258}
3259
3260/* Perform a .set directive, but also mark the alias as
3261 being a thumb function. */
3262
3263static void
3264s_thumb_set (int equiv)
3265{
3266 /* XXX the following is a duplicate of the code for s_set() in read.c
3267 We cannot just call that code as we need to get at the symbol that
3268 is created. */
3269 char * name;
3270 char delim;
3271 char * end_name;
3272 symbolS * symbolP;
3273
3274 /* Especial apologies for the random logic:
3275 This just grew, and could be parsed much more simply!
3276 Dean - in haste. */
d02603dc 3277 delim = get_symbol_name (& name);
c19d1205 3278 end_name = input_line_pointer;
d02603dc 3279 (void) restore_line_pointer (delim);
c19d1205
ZW		 3280
3281 if (*input_line_pointer != ',')
3282 {
3283 *end_name = 0;
3284 as_bad (_("expected comma after name \"%s\""), name);
b99bd4ef
NC		 3285 *end_name = delim;
3286 ignore_rest_of_line ();
3287 return;
3288 }
3289
3290 input_line_pointer++;
3291 *end_name = 0;
3292
3293 if (name[0] == '.' && name[1] == '\0')
3294 {
3295 /* XXX - this should not happen to .thumb_set. */
3296 abort ();
3297 }
3298
3299 if ((symbolP = symbol_find (name)) == NULL
3300 && (symbolP = md_undefined_symbol (name)) == NULL)
3301 {
3302#ifndef NO_LISTING
3303 /* When doing symbol listings, play games with dummy fragments living
3304 outside the normal fragment chain to record the file and line info
c19d1205 3305 for this symbol. */
b99bd4ef
NC		 3306 if (listing & LISTING_SYMBOLS)
3307 {
3308 extern struct list_info_struct * listing_tail;
21d799b5 3309 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
b99bd4ef
NC		 3310
3311 memset (dummy_frag, 0, sizeof (fragS));
3312 dummy_frag->fr_type = rs_fill;
3313 dummy_frag->line = listing_tail;
3314 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
3315 dummy_frag->fr_symbol = symbolP;
3316 }
3317 else
3318#endif
3319 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
3320
3321#ifdef OBJ_COFF
3322 /* "set" symbols are local unless otherwise specified. */
3323 SF_SET_LOCAL (symbolP);
3324#endif /* OBJ_COFF */
3325 } /* Make a new symbol. */
3326
3327 symbol_table_insert (symbolP);
3328
3329 * end_name = delim;
3330
3331 if (equiv
3332 && S_IS_DEFINED (symbolP)
3333 && S_GET_SEGMENT (symbolP) != reg_section)
3334 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
3335
3336 pseudo_set (symbolP);
3337
3338 demand_empty_rest_of_line ();
3339
c19d1205 3340 /* XXX Now we come to the Thumb specific bit of code. */
b99bd4ef
NC		 3341
3342 THUMB_SET_FUNC (symbolP, 1);
3343 ARM_SET_THUMB (symbolP, 1);
3344#if defined OBJ_ELF || defined OBJ_COFF
3345 ARM_SET_INTERWORK (symbolP, support_interwork);
3346#endif
3347}
3348
c19d1205 3349/* Directives: Mode selection. */
b99bd4ef 3350
c19d1205
ZW		 3351/* .syntax [unified|divided] - choose the new unified syntax
3352 (same for Arm and Thumb encoding, modulo slight differences in what
3353 can be represented) or the old divergent syntax for each mode. */
b99bd4ef 3354static void
c19d1205 3355s_syntax (int unused ATTRIBUTE_UNUSED)
b99bd4ef 3356{
c19d1205
ZW		 3357 char *name, delim;
3358
d02603dc 3359 delim = get_symbol_name (& name);
c19d1205
ZW		 3360
3361 if (!strcasecmp (name, "unified"))
3362 unified_syntax = TRUE;
3363 else if (!strcasecmp (name, "divided"))
3364 unified_syntax = FALSE;
3365 else
3366 {
3367 as_bad (_("unrecognized syntax mode \"%s\""), name);
3368 return;
3369 }
d02603dc 3370 (void) restore_line_pointer (delim);
b99bd4ef
NC		 3371 demand_empty_rest_of_line ();
3372}
3373
c19d1205
ZW		 3374/* Directives: sectioning and alignment. */
3375
c19d1205
ZW		 3376static void
3377s_bss (int ignore ATTRIBUTE_UNUSED)
b99bd4ef 3378{
c19d1205
ZW		 3379 /* We don't support putting frags in the BSS segment, we fake it by
3380 marking in_bss, then looking at s_skip for clues. */
3381 subseg_set (bss_section, 0);
3382 demand_empty_rest_of_line ();
cd000bff
DJ		 3383
3384#ifdef md_elf_section_change_hook
3385 md_elf_section_change_hook ();
3386#endif
c19d1205 3387}
b99bd4ef 3388
c19d1205
ZW		 3389static void
3390s_even (int ignore ATTRIBUTE_UNUSED)
3391{
3392 /* Never make frag if expect extra pass. */
3393 if (!need_pass_2)
3394 frag_align (1, 0, 0);
b99bd4ef 3395
c19d1205 3396 record_alignment (now_seg, 1);
b99bd4ef 3397
c19d1205 3398 demand_empty_rest_of_line ();
b99bd4ef
NC		 3399}
3400
2e6976a8
DG		 3401/* Directives: CodeComposer Studio. */
3402
3403/* .ref (for CodeComposer Studio syntax only). */
3404static void
3405s_ccs_ref (int unused ATTRIBUTE_UNUSED)
3406{
3407 if (codecomposer_syntax)
3408 ignore_rest_of_line ();
3409 else
3410 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3411}
3412
3413/* If name is not NULL, then it is used for marking the beginning of a
2b0f3761 3414 function, whereas if it is NULL then it means the function end. */
2e6976a8
DG		 3415static void
3416asmfunc_debug (const char * name)
3417{
3418 static const char * last_name = NULL;
3419
3420 if (name != NULL)
3421 {
3422 gas_assert (last_name == NULL);
3423 last_name = name;
3424
3425 if (debug_type == DEBUG_STABS)
3426 stabs_generate_asm_func (name, name);
3427 }
3428 else
3429 {
3430 gas_assert (last_name != NULL);
3431
3432 if (debug_type == DEBUG_STABS)
3433 stabs_generate_asm_endfunc (last_name, last_name);
3434
3435 last_name = NULL;
3436 }
3437}
3438
3439static void
3440s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED)
3441{
3442 if (codecomposer_syntax)
3443 {
3444 switch (asmfunc_state)
3445 {
3446 case OUTSIDE_ASMFUNC:
3447 asmfunc_state = WAITING_ASMFUNC_NAME;
3448 break;
3449
3450 case WAITING_ASMFUNC_NAME:
3451 as_bad (_(".asmfunc repeated."));
3452 break;
3453
3454 case WAITING_ENDASMFUNC:
3455 as_bad (_(".asmfunc without function."));
3456 break;
3457 }
3458 demand_empty_rest_of_line ();
3459 }
3460 else
3461 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3462}
3463
3464static void
3465s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED)
3466{
3467 if (codecomposer_syntax)
3468 {
3469 switch (asmfunc_state)
3470 {
3471 case OUTSIDE_ASMFUNC:
3472 as_bad (_(".endasmfunc without a .asmfunc."));
3473 break;
3474
3475 case WAITING_ASMFUNC_NAME:
3476 as_bad (_(".endasmfunc without function."));
3477 break;
3478
3479 case WAITING_ENDASMFUNC:
3480 asmfunc_state = OUTSIDE_ASMFUNC;
3481 asmfunc_debug (NULL);
3482 break;
3483 }
3484 demand_empty_rest_of_line ();
3485 }
3486 else
3487 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3488}
3489
3490static void
3491s_ccs_def (int name)
3492{
3493 if (codecomposer_syntax)
3494 s_globl (name);
3495 else
3496 as_bad (_(".def pseudo-op only available with -mccs flag."));
3497}
3498
c19d1205 3499/* Directives: Literal pools. */
a737bd4d 3500
c19d1205
ZW		 3501static literal_pool *
3502find_literal_pool (void)
a737bd4d 3503{
c19d1205 3504 literal_pool * pool;
a737bd4d 3505
c19d1205 3506 for (pool = list_of_pools; pool != NULL; pool = pool->next)
a737bd4d 3507 {
c19d1205
ZW		 3508 if (pool->section == now_seg
3509 && pool->sub_section == now_subseg)
3510 break;
a737bd4d
NC		 3511 }
3512
c19d1205 3513 return pool;
a737bd4d
NC		 3514}
3515
c19d1205
ZW		 3516static literal_pool *
3517find_or_make_literal_pool (void)
a737bd4d 3518{
c19d1205
ZW		 3519 /* Next literal pool ID number. */
3520 static unsigned int latest_pool_num = 1;
3521 literal_pool * pool;
a737bd4d 3522
c19d1205 3523 pool = find_literal_pool ();
a737bd4d 3524
c19d1205 3525 if (pool == NULL)
a737bd4d 3526 {
c19d1205 3527 /* Create a new pool. */
325801bd 3528 pool = XNEW (literal_pool);
c19d1205
ZW		 3529 if (! pool)
3530 return NULL;
a737bd4d 3531
c19d1205
ZW		 3532 pool->next_free_entry = 0;
3533 pool->section = now_seg;
3534 pool->sub_section = now_subseg;
3535 pool->next = list_of_pools;
3536 pool->symbol = NULL;
8335d6aa 3537 pool->alignment = 2;
c19d1205
ZW		 3538
3539 /* Add it to the list. */
3540 list_of_pools = pool;
a737bd4d 3541 }
a737bd4d 3542
c19d1205
ZW		 3543 /* New pools, and emptied pools, will have a NULL symbol. */
3544 if (pool->symbol == NULL)
a737bd4d 3545 {
c19d1205
ZW		 3546 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3547 (valueT) 0, &zero_address_frag);
3548 pool->id = latest_pool_num ++;
a737bd4d
NC		 3549 }
3550
c19d1205
ZW		 3551 /* Done. */
3552 return pool;
a737bd4d
NC		 3553}
3554
c19d1205 3555/* Add the literal in the global 'inst'
5f4273c7 3556 structure to the relevant literal pool. */
b99bd4ef
NC		 3557
3558static int
8335d6aa 3559add_to_lit_pool (unsigned int nbytes)
b99bd4ef 3560{
8335d6aa
JW		 3561#define PADDING_SLOT 0x1
3562#define LIT_ENTRY_SIZE_MASK 0xFF
c19d1205 3563 literal_pool * pool;
8335d6aa
JW		 3564 unsigned int entry, pool_size = 0;
3565 bfd_boolean padding_slot_p = FALSE;
e56c722b 3566 unsigned imm1 = 0;
8335d6aa
JW		 3567 unsigned imm2 = 0;
3568
3569 if (nbytes == 8)
3570 {
3571 imm1 = inst.operands[1].imm;
3572 imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg
e2b0ab59 3573 : inst.relocs[0].exp.X_unsigned ? 0
2569ceb0 3574 : ((bfd_int64_t) inst.operands[1].imm) >> 32);
8335d6aa
JW		 3575 if (target_big_endian)
3576 {
3577 imm1 = imm2;
3578 imm2 = inst.operands[1].imm;
3579 }
3580 }
b99bd4ef 3581
c19d1205
ZW		 3582 pool = find_or_make_literal_pool ();
3583
3584 /* Check if this literal value is already in the pool. */
3585 for (entry = 0; entry < pool->next_free_entry; entry ++)
b99bd4ef 3586 {
8335d6aa
JW		 3587 if (nbytes == 4)
3588 {
e2b0ab59
AV		 3589 if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op)
3590 && (inst.relocs[0].exp.X_op == O_constant)
8335d6aa 3591 && (pool->literals[entry].X_add_number
e2b0ab59 3592 == inst.relocs[0].exp.X_add_number)
8335d6aa
JW		 3593 && (pool->literals[entry].X_md == nbytes)
3594 && (pool->literals[entry].X_unsigned
e2b0ab59 3595 == inst.relocs[0].exp.X_unsigned))
8335d6aa
JW		 3596 break;
3597
e2b0ab59
AV		 3598 if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op)
3599 && (inst.relocs[0].exp.X_op == O_symbol)
8335d6aa 3600 && (pool->literals[entry].X_add_number
e2b0ab59 3601 == inst.relocs[0].exp.X_add_number)
8335d6aa 3602 && (pool->literals[entry].X_add_symbol
e2b0ab59 3603 == inst.relocs[0].exp.X_add_symbol)
8335d6aa 3604 && (pool->literals[entry].X_op_symbol
e2b0ab59 3605 == inst.relocs[0].exp.X_op_symbol)
8335d6aa
JW		 3606 && (pool->literals[entry].X_md == nbytes))
3607 break;
3608 }
3609 else if ((nbytes == 8)
3610 && !(pool_size & 0x7)
3611 && ((entry + 1) != pool->next_free_entry)
3612 && (pool->literals[entry].X_op == O_constant)
19f2f6a9 3613 && (pool->literals[entry].X_add_number == (offsetT) imm1)
8335d6aa 3614 && (pool->literals[entry].X_unsigned
e2b0ab59 3615 == inst.relocs[0].exp.X_unsigned)
8335d6aa 3616 && (pool->literals[entry + 1].X_op == O_constant)
19f2f6a9 3617 && (pool->literals[entry + 1].X_add_number == (offsetT) imm2)
8335d6aa 3618 && (pool->literals[entry + 1].X_unsigned
e2b0ab59 3619 == inst.relocs[0].exp.X_unsigned))
c19d1205
ZW		 3620 break;
3621
8335d6aa
JW		 3622 padding_slot_p = ((pool->literals[entry].X_md >> 8) == PADDING_SLOT);
3623 if (padding_slot_p && (nbytes == 4))
c19d1205 3624 break;
8335d6aa
JW		 3625
3626 pool_size += 4;
b99bd4ef
NC		 3627 }
3628
c19d1205
ZW		 3629 /* Do we need to create a new entry? */
3630 if (entry == pool->next_free_entry)
3631 {
3632 if (entry >= MAX_LITERAL_POOL_SIZE)
3633 {
3634 inst.error = _("literal pool overflow");
3635 return FAIL;
3636 }
3637
8335d6aa
JW		 3638 if (nbytes == 8)
3639 {
3640 /* For 8-byte entries, we align to an 8-byte boundary,
3641 and split it into two 4-byte entries, because on 32-bit
3642 host, 8-byte constants are treated as big num, thus
3643 saved in "generic_bignum" which will be overwritten
3644 by later assignments.
3645
3646 We also need to make sure there is enough space for
3647 the split.
3648
3649 We also check to make sure the literal operand is a
3650 constant number. */
e2b0ab59
AV		 3651 if (!(inst.relocs[0].exp.X_op == O_constant
3652 || inst.relocs[0].exp.X_op == O_big))
8335d6aa
JW		 3653 {
3654 inst.error = _("invalid type for literal pool");
3655 return FAIL;
3656 }
3657 else if (pool_size & 0x7)
3658 {
3659 if ((entry + 2) >= MAX_LITERAL_POOL_SIZE)
3660 {
3661 inst.error = _("literal pool overflow");
3662 return FAIL;
3663 }
3664
e2b0ab59 3665 pool->literals[entry] = inst.relocs[0].exp;
a6684f0d 3666 pool->literals[entry].X_op = O_constant;
8335d6aa
JW		 3667 pool->literals[entry].X_add_number = 0;
3668 pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4;
3669 pool->next_free_entry += 1;
3670 pool_size += 4;
3671 }
3672 else if ((entry + 1) >= MAX_LITERAL_POOL_SIZE)
3673 {
3674 inst.error = _("literal pool overflow");
3675 return FAIL;
3676 }
3677
e2b0ab59 3678 pool->literals[entry] = inst.relocs[0].exp;
8335d6aa
JW		 3679 pool->literals[entry].X_op = O_constant;
3680 pool->literals[entry].X_add_number = imm1;
e2b0ab59 3681 pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned;
8335d6aa 3682 pool->literals[entry++].X_md = 4;
e2b0ab59 3683 pool->literals[entry] = inst.relocs[0].exp;
8335d6aa
JW		 3684 pool->literals[entry].X_op = O_constant;
3685 pool->literals[entry].X_add_number = imm2;
e2b0ab59 3686 pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned;
8335d6aa
JW		 3687 pool->literals[entry].X_md = 4;
3688 pool->alignment = 3;
3689 pool->next_free_entry += 1;
3690 }
3691 else
3692 {
e2b0ab59 3693 pool->literals[entry] = inst.relocs[0].exp;
8335d6aa
JW		 3694 pool->literals[entry].X_md = 4;
3695 }
3696
a8040cf2
NC		 3697#ifdef OBJ_ELF
3698 /* PR ld/12974: Record the location of the first source line to reference
3699 this entry in the literal pool. If it turns out during linking that the
3700 symbol does not exist we will be able to give an accurate line number for
3701 the (first use of the) missing reference. */
3702 if (debug_type == DEBUG_DWARF2)
3703 dwarf2_where (pool->locs + entry);
3704#endif
c19d1205
ZW		 3705 pool->next_free_entry += 1;
3706 }
8335d6aa
JW		 3707 else if (padding_slot_p)
3708 {
e2b0ab59 3709 pool->literals[entry] = inst.relocs[0].exp;
8335d6aa
JW		 3710 pool->literals[entry].X_md = nbytes;
3711 }
b99bd4ef 3712
e2b0ab59
AV		 3713 inst.relocs[0].exp.X_op = O_symbol;
3714 inst.relocs[0].exp.X_add_number = pool_size;
3715 inst.relocs[0].exp.X_add_symbol = pool->symbol;
b99bd4ef 3716
c19d1205 3717 return SUCCESS;
b99bd4ef
NC		 3718}
3719
2e6976a8 3720bfd_boolean
2e57ce7b 3721tc_start_label_without_colon (void)
2e6976a8
DG		 3722{
3723 bfd_boolean ret = TRUE;
3724
3725 if (codecomposer_syntax && asmfunc_state == WAITING_ASMFUNC_NAME)
3726 {
2e57ce7b 3727 const char *label = input_line_pointer;
2e6976a8
DG		 3728
3729 while (!is_end_of_line[(int) label[-1]])
3730 --label;
3731
3732 if (*label == '.')
3733 {
3734 as_bad (_("Invalid label '%s'"), label);
3735 ret = FALSE;
3736 }
3737
3738 asmfunc_debug (label);
3739
3740 asmfunc_state = WAITING_ENDASMFUNC;
3741 }
3742
3743 return ret;
3744}
3745
c19d1205 3746/* Can't use symbol_new here, so have to create a symbol and then at
33eaf5de 3747 a later date assign it a value. That's what these functions do. */
e16bb312 3748
c19d1205
ZW		 3749static void
3750symbol_locate (symbolS * symbolP,
3751 const char * name, /* It is copied, the caller can modify. */
3752 segT segment, /* Segment identifier (SEG_<something>). */
3753 valueT valu, /* Symbol value. */
3754 fragS * frag) /* Associated fragment. */
3755{
e57e6ddc 3756 size_t name_length;
c19d1205 3757 char * preserved_copy_of_name;
e16bb312 3758
c19d1205
ZW		 3759 name_length = strlen (name) + 1; /* +1 for \0. */
3760 obstack_grow (&notes, name, name_length);
21d799b5 3761 preserved_copy_of_name = (char *) obstack_finish (&notes);
e16bb312 3762
c19d1205
ZW		 3763#ifdef tc_canonicalize_symbol_name
3764 preserved_copy_of_name =
3765 tc_canonicalize_symbol_name (preserved_copy_of_name);
3766#endif
b99bd4ef 3767
c19d1205 3768 S_SET_NAME (symbolP, preserved_copy_of_name);
b99bd4ef 3769
c19d1205
ZW		 3770 S_SET_SEGMENT (symbolP, segment);
3771 S_SET_VALUE (symbolP, valu);
3772 symbol_clear_list_pointers (symbolP);
b99bd4ef 3773
c19d1205 3774 symbol_set_frag (symbolP, frag);
b99bd4ef 3775
c19d1205
ZW		 3776 /* Link to end of symbol chain. */
3777 {
3778 extern int symbol_table_frozen;
b99bd4ef 3779
c19d1205
ZW		 3780 if (symbol_table_frozen)
3781 abort ();
3782 }
b99bd4ef 3783
c19d1205 3784 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
b99bd4ef 3785
c19d1205 3786 obj_symbol_new_hook (symbolP);
b99bd4ef 3787
c19d1205
ZW		 3788#ifdef tc_symbol_new_hook
3789 tc_symbol_new_hook (symbolP);
3790#endif
3791
3792#ifdef DEBUG_SYMS
3793 verify_symbol_chain (symbol_rootP, symbol_lastP);
3794#endif /* DEBUG_SYMS */
b99bd4ef
NC		 3795}
3796
c19d1205
ZW		 3797static void
3798s_ltorg (int ignored ATTRIBUTE_UNUSED)
b99bd4ef 3799{
c19d1205
ZW		 3800 unsigned int entry;
3801 literal_pool * pool;
3802 char sym_name[20];
b99bd4ef 3803
c19d1205
ZW		 3804 pool = find_literal_pool ();
3805 if (pool == NULL
3806 || pool->symbol == NULL
3807 || pool->next_free_entry == 0)
3808 return;
b99bd4ef 3809
c19d1205
ZW		 3810 /* Align pool as you have word accesses.
3811 Only make a frag if we have to. */
3812 if (!need_pass_2)
8335d6aa 3813 frag_align (pool->alignment, 0, 0);
b99bd4ef 3814
c19d1205 3815 record_alignment (now_seg, 2);
b99bd4ef 3816
aaca88ef 3817#ifdef OBJ_ELF
47fc6e36
WN		 3818 seg_info (now_seg)->tc_segment_info_data.mapstate = MAP_DATA;
3819 make_mapping_symbol (MAP_DATA, (valueT) frag_now_fix (), frag_now);
aaca88ef 3820#endif
c19d1205 3821 sprintf (sym_name, "$$lit_\002%x", pool->id);
b99bd4ef 3822
c19d1205
ZW		 3823 symbol_locate (pool->symbol, sym_name, now_seg,
3824 (valueT) frag_now_fix (), frag_now);
3825 symbol_table_insert (pool->symbol);
b99bd4ef 3826
c19d1205 3827 ARM_SET_THUMB (pool->symbol, thumb_mode);
b99bd4ef 3828
c19d1205
ZW		 3829#if defined OBJ_COFF || defined OBJ_ELF
3830 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3831#endif
6c43fab6 3832
c19d1205 3833 for (entry = 0; entry < pool->next_free_entry; entry ++)
a8040cf2
NC		 3834 {
3835#ifdef OBJ_ELF
3836 if (debug_type == DEBUG_DWARF2)
3837 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3838#endif
3839 /* First output the expression in the instruction to the pool. */
8335d6aa
JW		 3840 emit_expr (&(pool->literals[entry]),
3841 pool->literals[entry].X_md & LIT_ENTRY_SIZE_MASK);
a8040cf2 3842 }
b99bd4ef 3843
c19d1205
ZW		 3844 /* Mark the pool as empty. */
3845 pool->next_free_entry = 0;
3846 pool->symbol = NULL;
b99bd4ef
NC		 3847}
3848
c19d1205
ZW		 3849#ifdef OBJ_ELF
3850/* Forward declarations for functions below, in the MD interface
3851 section. */
3852static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3853static valueT create_unwind_entry (int);
3854static void start_unwind_section (const segT, int);
3855static void add_unwind_opcode (valueT, int);
3856static void flush_pending_unwind (void);
b99bd4ef 3857
c19d1205 3858/* Directives: Data. */
b99bd4ef 3859
c19d1205
ZW		 3860static void
3861s_arm_elf_cons (int nbytes)
3862{
3863 expressionS exp;
b99bd4ef 3864
c19d1205
ZW		 3865#ifdef md_flush_pending_output
3866 md_flush_pending_output ();
3867#endif
b99bd4ef 3868
c19d1205 3869 if (is_it_end_of_statement ())
b99bd4ef 3870 {
c19d1205
ZW		 3871 demand_empty_rest_of_line ();
3872 return;
b99bd4ef
NC		 3873 }
3874
c19d1205
ZW		 3875#ifdef md_cons_align
3876 md_cons_align (nbytes);
3877#endif
b99bd4ef 3878
c19d1205
ZW		 3879 mapping_state (MAP_DATA);
3880 do
b99bd4ef 3881 {
c19d1205
ZW		 3882 int reloc;
3883 char *base = input_line_pointer;
b99bd4ef 3884
c19d1205 3885 expression (& exp);
b99bd4ef 3886
c19d1205
ZW		 3887 if (exp.X_op != O_symbol)
3888 emit_expr (&exp, (unsigned int) nbytes);
3889 else
3890 {
3891 char *before_reloc = input_line_pointer;
3892 reloc = parse_reloc (&input_line_pointer);
3893 if (reloc == -1)
3894 {
3895 as_bad (_("unrecognized relocation suffix"));
3896 ignore_rest_of_line ();
3897 return;
3898 }
3899 else if (reloc == BFD_RELOC_UNUSED)
3900 emit_expr (&exp, (unsigned int) nbytes);
3901 else
3902 {
21d799b5 3903 reloc_howto_type *howto = (reloc_howto_type *)
477330fc
RM		 3904 bfd_reloc_type_lookup (stdoutput,
3905 (bfd_reloc_code_real_type) reloc);
c19d1205 3906 int size = bfd_get_reloc_size (howto);
b99bd4ef 3907
2fc8bdac
ZW		 3908 if (reloc == BFD_RELOC_ARM_PLT32)
3909 {
3910 as_bad (_("(plt) is only valid on branch targets"));
3911 reloc = BFD_RELOC_UNUSED;
3912 size = 0;
3913 }
3914
c19d1205 3915 if (size > nbytes)
992a06ee
AM		 3916 as_bad (ngettext ("%s relocations do not fit in %d byte",
3917 "%s relocations do not fit in %d bytes",
3918 nbytes),
c19d1205
ZW		 3919 howto->name, nbytes);
3920 else
3921 {
3922 /* We've parsed an expression stopping at O_symbol.
3923 But there may be more expression left now that we
3924 have parsed the relocation marker. Parse it again.
3925 XXX Surely there is a cleaner way to do this. */
3926 char *p = input_line_pointer;
3927 int offset;
325801bd 3928 char *save_buf = XNEWVEC (char, input_line_pointer - base);
e1fa0163 3929
c19d1205
ZW		 3930 memcpy (save_buf, base, input_line_pointer - base);
3931 memmove (base + (input_line_pointer - before_reloc),
3932 base, before_reloc - base);
3933
3934 input_line_pointer = base + (input_line_pointer-before_reloc);
3935 expression (&exp);
3936 memcpy (base, save_buf, p - base);
3937
3938 offset = nbytes - size;
4b1a927e
AM		 3939 p = frag_more (nbytes);
3940 memset (p, 0, nbytes);
c19d1205 3941 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
21d799b5 3942 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
e1fa0163 3943 free (save_buf);
c19d1205
ZW		 3944 }
3945 }
3946 }
b99bd4ef 3947 }
c19d1205 3948 while (*input_line_pointer++ == ',');
b99bd4ef 3949
c19d1205
ZW		 3950 /* Put terminator back into stream. */
3951 input_line_pointer --;
3952 demand_empty_rest_of_line ();
b99bd4ef
NC		 3953}
3954
c921be7d
NC		 3955/* Emit an expression containing a 32-bit thumb instruction.
3956 Implementation based on put_thumb32_insn. */
3957
3958static void
3959emit_thumb32_expr (expressionS * exp)
3960{
3961 expressionS exp_high = *exp;
3962
3963 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3964 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3965 exp->X_add_number &= 0xffff;
3966 emit_expr (exp, (unsigned int) THUMB_SIZE);
3967}
3968
3969/* Guess the instruction size based on the opcode. */
3970
3971static int
3972thumb_insn_size (int opcode)
3973{
3974 if ((unsigned int) opcode < 0xe800u)
3975 return 2;
3976 else if ((unsigned int) opcode >= 0xe8000000u)
3977 return 4;
3978 else
3979 return 0;
3980}
3981
3982static bfd_boolean
3983emit_insn (expressionS *exp, int nbytes)
3984{
3985 int size = 0;
3986
3987 if (exp->X_op == O_constant)
3988 {
3989 size = nbytes;
3990
3991 if (size == 0)
3992 size = thumb_insn_size (exp->X_add_number);
3993
3994 if (size != 0)
3995 {
3996 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3997 {
3998 as_bad (_(".inst.n operand too big. "\
3999 "Use .inst.w instead"));
4000 size = 0;
4001 }
4002 else
4003 {
5ee91343
AV		 4004 if (now_pred.state == AUTOMATIC_PRED_BLOCK)
4005 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN, 0);
c921be7d 4006 else
5ee91343 4007 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
c921be7d
NC		 4008
4009 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
4010 emit_thumb32_expr (exp);
4011 else
4012 emit_expr (exp, (unsigned int) size);
4013
4014 it_fsm_post_encode ();
4015 }
4016 }
4017 else
4018 as_bad (_("cannot determine Thumb instruction size. " \
4019 "Use .inst.n/.inst.w instead"));
4020 }
4021 else
4022 as_bad (_("constant expression required"));
4023
4024 return (size != 0);
4025}
4026
4027/* Like s_arm_elf_cons but do not use md_cons_align and
4028 set the mapping state to MAP_ARM/MAP_THUMB. */
4029
4030static void
4031s_arm_elf_inst (int nbytes)
4032{
4033 if (is_it_end_of_statement ())
4034 {
4035 demand_empty_rest_of_line ();
4036 return;
4037 }
4038
4039 /* Calling mapping_state () here will not change ARM/THUMB,
4040 but will ensure not to be in DATA state. */
4041
4042 if (thumb_mode)
4043 mapping_state (MAP_THUMB);
4044 else
4045 {
4046 if (nbytes != 0)
4047 {
4048 as_bad (_("width suffixes are invalid in ARM mode"));
4049 ignore_rest_of_line ();
4050 return;
4051 }
4052
4053 nbytes = 4;
4054
4055 mapping_state (MAP_ARM);
4056 }
4057
4058 do
4059 {
4060 expressionS exp;
4061
4062 expression (& exp);
4063
4064 if (! emit_insn (& exp, nbytes))
4065 {
4066 ignore_rest_of_line ();
4067 return;
4068 }
4069 }
4070 while (*input_line_pointer++ == ',');
4071
4072 /* Put terminator back into stream. */
4073 input_line_pointer --;
4074 demand_empty_rest_of_line ();
4075}
b99bd4ef 4076
c19d1205 4077/* Parse a .rel31 directive. */
b99bd4ef 4078
c19d1205
ZW		 4079static void
4080s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
4081{
4082 expressionS exp;
4083 char *p;
4084 valueT highbit;
b99bd4ef 4085
c19d1205
ZW		 4086 highbit = 0;
4087 if (*input_line_pointer == '1')
4088 highbit = 0x80000000;
4089 else if (*input_line_pointer != '0')
4090 as_bad (_("expected 0 or 1"));
b99bd4ef 4091
c19d1205
ZW		 4092 input_line_pointer++;
4093 if (*input_line_pointer != ',')
4094 as_bad (_("missing comma"));
4095 input_line_pointer++;
b99bd4ef 4096
c19d1205
ZW		 4097#ifdef md_flush_pending_output
4098 md_flush_pending_output ();
4099#endif
b99bd4ef 4100
c19d1205
ZW		 4101#ifdef md_cons_align
4102 md_cons_align (4);
4103#endif
b99bd4ef 4104
c19d1205 4105 mapping_state (MAP_DATA);
b99bd4ef 4106
c19d1205 4107 expression (&exp);
b99bd4ef 4108
c19d1205
ZW		 4109 p = frag_more (4);
4110 md_number_to_chars (p, highbit, 4);
4111 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
4112 BFD_RELOC_ARM_PREL31);
b99bd4ef 4113
c19d1205 4114 demand_empty_rest_of_line ();
b99bd4ef
NC		 4115}
4116
c19d1205 4117/* Directives: AEABI stack-unwind tables. */
b99bd4ef 4118
c19d1205 4119/* Parse an unwind_fnstart directive. Simply records the current location. */
b99bd4ef 4120
c19d1205
ZW		 4121static void
4122s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
4123{
4124 demand_empty_rest_of_line ();
921e5f0a
PB		 4125 if (unwind.proc_start)
4126 {
c921be7d 4127 as_bad (_("duplicate .fnstart directive"));
921e5f0a
PB		 4128 return;
4129 }
4130
c19d1205
ZW		 4131 /* Mark the start of the function. */
4132 unwind.proc_start = expr_build_dot ();
b99bd4ef 4133
c19d1205
ZW		 4134 /* Reset the rest of the unwind info. */
4135 unwind.opcode_count = 0;
4136 unwind.table_entry = NULL;
4137 unwind.personality_routine = NULL;
4138 unwind.personality_index = -1;
4139 unwind.frame_size = 0;
4140 unwind.fp_offset = 0;
fdfde340 4141 unwind.fp_reg = REG_SP;
c19d1205
ZW		 4142 unwind.fp_used = 0;
4143 unwind.sp_restored = 0;
4144}
b99bd4ef 4145
b99bd4ef 4146
c19d1205
ZW		 4147/* Parse a handlerdata directive. Creates the exception handling table entry
4148 for the function. */
b99bd4ef 4149
c19d1205
ZW		 4150static void
4151s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
4152{
4153 demand_empty_rest_of_line ();
921e5f0a 4154 if (!unwind.proc_start)
c921be7d 4155 as_bad (MISSING_FNSTART);
921e5f0a 4156
c19d1205 4157 if (unwind.table_entry)
6decc662 4158 as_bad (_("duplicate .handlerdata directive"));
f02232aa 4159
c19d1205
ZW		 4160 create_unwind_entry (1);
4161}
a737bd4d 4162
c19d1205 4163/* Parse an unwind_fnend directive. Generates the index table entry. */
b99bd4ef 4164
c19d1205
ZW		 4165static void
4166s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
4167{
4168 long where;
4169 char *ptr;
4170 valueT val;
940b5ce0 4171 unsigned int marked_pr_dependency;
f02232aa 4172
c19d1205 4173 demand_empty_rest_of_line ();
f02232aa 4174
921e5f0a
PB		 4175 if (!unwind.proc_start)
4176 {
c921be7d 4177 as_bad (_(".fnend directive without .fnstart"));
921e5f0a
PB		 4178 return;
4179 }
4180
c19d1205
ZW		 4181 /* Add eh table entry. */
4182 if (unwind.table_entry == NULL)
4183 val = create_unwind_entry (0);
4184 else
4185 val = 0;
f02232aa 4186
c19d1205
ZW		 4187 /* Add index table entry. This is two words. */
4188 start_unwind_section (unwind.saved_seg, 1);
4189 frag_align (2, 0, 0);
4190 record_alignment (now_seg, 2);
b99bd4ef 4191
c19d1205 4192 ptr = frag_more (8);
5011093d 4193 memset (ptr, 0, 8);
c19d1205 4194 where = frag_now_fix () - 8;
f02232aa 4195
c19d1205
ZW		 4196 /* Self relative offset of the function start. */
4197 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
4198 BFD_RELOC_ARM_PREL31);
f02232aa 4199
c19d1205
ZW		 4200 /* Indicate dependency on EHABI-defined personality routines to the
4201 linker, if it hasn't been done already. */
940b5ce0
DJ		 4202 marked_pr_dependency
4203 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
c19d1205
ZW		 4204 if (unwind.personality_index >= 0 && unwind.personality_index < 3
4205 && !(marked_pr_dependency & (1 << unwind.personality_index)))
4206 {
5f4273c7
NC		 4207 static const char *const name[] =
4208 {
4209 "__aeabi_unwind_cpp_pr0",
4210 "__aeabi_unwind_cpp_pr1",
4211 "__aeabi_unwind_cpp_pr2"
4212 };
c19d1205
ZW		 4213 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
4214 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
c19d1205 4215 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
940b5ce0 4216 |= 1 << unwind.personality_index;
c19d1205 4217 }
f02232aa 4218
c19d1205
ZW		 4219 if (val)
4220 /* Inline exception table entry. */
4221 md_number_to_chars (ptr + 4, val, 4);
4222 else
4223 /* Self relative offset of the table entry. */
4224 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
4225 BFD_RELOC_ARM_PREL31);
f02232aa 4226
c19d1205
ZW		 4227 /* Restore the original section. */
4228 subseg_set (unwind.saved_seg, unwind.saved_subseg);
921e5f0a
PB		 4229
4230 unwind.proc_start = NULL;
c19d1205 4231}
f02232aa 4232
f02232aa 4233
c19d1205 4234/* Parse an unwind_cantunwind directive. */
b99bd4ef 4235
c19d1205
ZW		 4236static void
4237s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
4238{
4239 demand_empty_rest_of_line ();
921e5f0a 4240 if (!unwind.proc_start)
c921be7d 4241 as_bad (MISSING_FNSTART);
921e5f0a 4242
c19d1205
ZW		 4243 if (unwind.personality_routine || unwind.personality_index != -1)
4244 as_bad (_("personality routine specified for cantunwind frame"));
b99bd4ef 4245
c19d1205
ZW		 4246 unwind.personality_index = -2;
4247}
b99bd4ef 4248
b99bd4ef 4249
c19d1205 4250/* Parse a personalityindex directive. */
b99bd4ef 4251
c19d1205
ZW		 4252static void
4253s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
4254{
4255 expressionS exp;
b99bd4ef 4256
921e5f0a 4257 if (!unwind.proc_start)
c921be7d 4258 as_bad (MISSING_FNSTART);
921e5f0a 4259
c19d1205
ZW		 4260 if (unwind.personality_routine || unwind.personality_index != -1)
4261 as_bad (_("duplicate .personalityindex directive"));
b99bd4ef 4262
c19d1205 4263 expression (&exp);
b99bd4ef 4264
c19d1205
ZW		 4265 if (exp.X_op != O_constant
4266 || exp.X_add_number < 0 || exp.X_add_number > 15)
b99bd4ef 4267 {
c19d1205
ZW		 4268 as_bad (_("bad personality routine number"));
4269 ignore_rest_of_line ();
4270 return;
b99bd4ef
NC		 4271 }
4272
c19d1205 4273 unwind.personality_index = exp.X_add_number;
b99bd4ef 4274
c19d1205
ZW		 4275 demand_empty_rest_of_line ();
4276}
e16bb312 4277
e16bb312 4278
c19d1205 4279/* Parse a personality directive. */
e16bb312 4280
c19d1205
ZW		 4281static void
4282s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
4283{
4284 char *name, *p, c;
a737bd4d 4285
921e5f0a 4286 if (!unwind.proc_start)
c921be7d 4287 as_bad (MISSING_FNSTART);
921e5f0a 4288
c19d1205
ZW		 4289 if (unwind.personality_routine || unwind.personality_index != -1)
4290 as_bad (_("duplicate .personality directive"));
a737bd4d 4291
d02603dc 4292 c = get_symbol_name (& name);
c19d1205 4293 p = input_line_pointer;
d02603dc
NC		 4294 if (c == '"')
4295 ++ input_line_pointer;
c19d1205
ZW		 4296 unwind.personality_routine = symbol_find_or_make (name);
4297 *p = c;
4298 demand_empty_rest_of_line ();
4299}
e16bb312 4300
e16bb312 4301
c19d1205 4302/* Parse a directive saving core registers. */
e16bb312 4303
c19d1205
ZW		 4304static void
4305s_arm_unwind_save_core (void)
e16bb312 4306{
c19d1205
ZW		 4307 valueT op;
4308 long range;
4309 int n;
e16bb312 4310
4b5a202f 4311 range = parse_reg_list (&input_line_pointer, REGLIST_RN);
c19d1205 4312 if (range == FAIL)
e16bb312 4313 {
c19d1205
ZW		 4314 as_bad (_("expected register list"));
4315 ignore_rest_of_line ();
4316 return;
4317 }
e16bb312 4318
c19d1205 4319 demand_empty_rest_of_line ();
e16bb312 4320
c19d1205
ZW		 4321 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4322 into .unwind_save {..., sp...}. We aren't bothered about the value of
4323 ip because it is clobbered by calls. */
4324 if (unwind.sp_restored && unwind.fp_reg == 12
4325 && (range & 0x3000) == 0x1000)
4326 {
4327 unwind.opcode_count--;
4328 unwind.sp_restored = 0;
4329 range = (range | 0x2000) & ~0x1000;
4330 unwind.pending_offset = 0;
4331 }
e16bb312 4332
01ae4198
DJ		 4333 /* Pop r4-r15. */
4334 if (range & 0xfff0)
c19d1205 4335 {
01ae4198
DJ		 4336 /* See if we can use the short opcodes. These pop a block of up to 8
4337 registers starting with r4, plus maybe r14. */
4338 for (n = 0; n < 8; n++)
4339 {
4340 /* Break at the first non-saved register. */
4341 if ((range & (1 << (n + 4))) == 0)
4342 break;
4343 }
4344 /* See if there are any other bits set. */
4345 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
4346 {
4347 /* Use the long form. */
4348 op = 0x8000 | ((range >> 4) & 0xfff);
4349 add_unwind_opcode (op, 2);
4350 }
0dd132b6 4351 else
01ae4198
DJ		 4352 {
4353 /* Use the short form. */
4354 if (range & 0x4000)
4355 op = 0xa8; /* Pop r14. */
4356 else
4357 op = 0xa0; /* Do not pop r14. */
4358 op |= (n - 1);
4359 add_unwind_opcode (op, 1);
4360 }
c19d1205 4361 }
0dd132b6 4362
c19d1205
ZW		 4363 /* Pop r0-r3. */
4364 if (range & 0xf)
4365 {
4366 op = 0xb100 | (range & 0xf);
4367 add_unwind_opcode (op, 2);
0dd132b6
NC		 4368 }
4369
c19d1205
ZW		 4370 /* Record the number of bytes pushed. */
4371 for (n = 0; n < 16; n++)
4372 {
4373 if (range & (1 << n))
4374 unwind.frame_size += 4;
4375 }
0dd132b6
NC		 4376}
4377
c19d1205
ZW		 4378
4379/* Parse a directive saving FPA registers. */
b99bd4ef
NC		 4380
4381static void
c19d1205 4382s_arm_unwind_save_fpa (int reg)
b99bd4ef 4383{
c19d1205
ZW		 4384 expressionS exp;
4385 int num_regs;
4386 valueT op;
b99bd4ef 4387
c19d1205
ZW		 4388 /* Get Number of registers to transfer. */
4389 if (skip_past_comma (&input_line_pointer) != FAIL)
4390 expression (&exp);
4391 else
4392 exp.X_op = O_illegal;
b99bd4ef 4393
c19d1205 4394 if (exp.X_op != O_constant)
b99bd4ef 4395 {
c19d1205
ZW		 4396 as_bad (_("expected , <constant>"));
4397 ignore_rest_of_line ();
b99bd4ef
NC		 4398 return;
4399 }
4400
c19d1205
ZW		 4401 num_regs = exp.X_add_number;
4402
4403 if (num_regs < 1 || num_regs > 4)
b99bd4ef 4404 {
c19d1205
ZW		 4405 as_bad (_("number of registers must be in the range [1:4]"));
4406 ignore_rest_of_line ();
b99bd4ef
NC		 4407 return;
4408 }
4409
c19d1205 4410 demand_empty_rest_of_line ();
b99bd4ef 4411
c19d1205
ZW		 4412 if (reg == 4)
4413 {
4414 /* Short form. */
4415 op = 0xb4 | (num_regs - 1);
4416 add_unwind_opcode (op, 1);
4417 }
b99bd4ef
NC		 4418 else
4419 {
c19d1205
ZW		 4420 /* Long form. */
4421 op = 0xc800 | (reg << 4) | (num_regs - 1);
4422 add_unwind_opcode (op, 2);
b99bd4ef 4423 }
c19d1205 4424 unwind.frame_size += num_regs * 12;
b99bd4ef
NC		 4425}
4426
c19d1205 4427
fa073d69
MS		 4428/* Parse a directive saving VFP registers for ARMv6 and above. */
4429
4430static void
4431s_arm_unwind_save_vfp_armv6 (void)
4432{
4433 int count;
4434 unsigned int start;
4435 valueT op;
4436 int num_vfpv3_regs = 0;
4437 int num_regs_below_16;
efd6b359 4438 bfd_boolean partial_match;
fa073d69 4439
efd6b359
AV		 4440 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D,
4441 &partial_match);
fa073d69
MS		 4442 if (count == FAIL)
4443 {
4444 as_bad (_("expected register list"));
4445 ignore_rest_of_line ();
4446 return;
4447 }
4448
4449 demand_empty_rest_of_line ();
4450
4451 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4452 than FSTMX/FLDMX-style ones). */
4453
4454 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4455 if (start >= 16)
4456 num_vfpv3_regs = count;
4457 else if (start + count > 16)
4458 num_vfpv3_regs = start + count - 16;
4459
4460 if (num_vfpv3_regs > 0)
4461 {
4462 int start_offset = start > 16 ? start - 16 : 0;
4463 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
4464 add_unwind_opcode (op, 2);
4465 }
4466
4467 /* Generate opcode for registers numbered in the range 0 .. 15. */
4468 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
9c2799c2 4469 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
fa073d69
MS		 4470 if (num_regs_below_16 > 0)
4471 {
4472 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
4473 add_unwind_opcode (op, 2);
4474 }
4475
4476 unwind.frame_size += count * 8;
4477}
4478
4479
4480/* Parse a directive saving VFP registers for pre-ARMv6. */
b99bd4ef
NC		 4481
4482static void
c19d1205 4483s_arm_unwind_save_vfp (void)
b99bd4ef 4484{
c19d1205 4485 int count;
ca3f61f7 4486 unsigned int reg;
c19d1205 4487 valueT op;
efd6b359 4488 bfd_boolean partial_match;
b99bd4ef 4489
efd6b359
AV		 4490 count = parse_vfp_reg_list (&input_line_pointer, &reg, REGLIST_VFP_D,
4491 &partial_match);
c19d1205 4492 if (count == FAIL)
b99bd4ef 4493 {
c19d1205
ZW		 4494 as_bad (_("expected register list"));
4495 ignore_rest_of_line ();
b99bd4ef
NC		 4496 return;
4497 }
4498
c19d1205 4499 demand_empty_rest_of_line ();
b99bd4ef 4500
c19d1205 4501 if (reg == 8)
b99bd4ef 4502 {
c19d1205
ZW		 4503 /* Short form. */
4504 op = 0xb8 | (count - 1);
4505 add_unwind_opcode (op, 1);
b99bd4ef 4506 }
c19d1205 4507 else
b99bd4ef 4508 {
c19d1205
ZW		 4509 /* Long form. */
4510 op = 0xb300 | (reg << 4) | (count - 1);
4511 add_unwind_opcode (op, 2);
b99bd4ef 4512 }
c19d1205
ZW		 4513 unwind.frame_size += count * 8 + 4;
4514}
b99bd4ef 4515
b99bd4ef 4516
c19d1205
ZW		 4517/* Parse a directive saving iWMMXt data registers. */
4518
4519static void
4520s_arm_unwind_save_mmxwr (void)
4521{
4522 int reg;
4523 int hi_reg;
4524 int i;
4525 unsigned mask = 0;
4526 valueT op;
b99bd4ef 4527
c19d1205
ZW		 4528 if (*input_line_pointer == '{')
4529 input_line_pointer++;
b99bd4ef 4530
c19d1205 4531 do
b99bd4ef 4532 {
dcbf9037 4533 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
b99bd4ef 4534
c19d1205 4535 if (reg == FAIL)
b99bd4ef 4536 {
9b7132d3 4537 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
c19d1205 4538 goto error;
b99bd4ef
NC		 4539 }
4540
c19d1205
ZW		 4541 if (mask >> reg)
4542 as_tsktsk (_("register list not in ascending order"));
4543 mask |= 1 << reg;
b99bd4ef 4544
c19d1205
ZW		 4545 if (*input_line_pointer == '-')
4546 {
4547 input_line_pointer++;
dcbf9037 4548 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
c19d1205
ZW		 4549 if (hi_reg == FAIL)
4550 {
9b7132d3 4551 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
c19d1205
ZW		 4552 goto error;
4553 }
4554 else if (reg >= hi_reg)
4555 {
4556 as_bad (_("bad register range"));
4557 goto error;
4558 }
4559 for (; reg < hi_reg; reg++)
4560 mask |= 1 << reg;
4561 }
4562 }
4563 while (skip_past_comma (&input_line_pointer) != FAIL);
b99bd4ef 4564
d996d970 4565 skip_past_char (&input_line_pointer, '}');
b99bd4ef 4566
c19d1205 4567 demand_empty_rest_of_line ();
b99bd4ef 4568
708587a4 4569 /* Generate any deferred opcodes because we're going to be looking at
c19d1205
ZW		 4570 the list. */
4571 flush_pending_unwind ();
b99bd4ef 4572
c19d1205 4573 for (i = 0; i < 16; i++)
b99bd4ef 4574 {
c19d1205
ZW		 4575 if (mask & (1 << i))
4576 unwind.frame_size += 8;
b99bd4ef
NC		 4577 }
4578
c19d1205
ZW		 4579 /* Attempt to combine with a previous opcode. We do this because gcc
4580 likes to output separate unwind directives for a single block of
4581 registers. */
4582 if (unwind.opcode_count > 0)
b99bd4ef 4583 {
c19d1205
ZW		 4584 i = unwind.opcodes[unwind.opcode_count - 1];
4585 if ((i & 0xf8) == 0xc0)
4586 {
4587 i &= 7;
4588 /* Only merge if the blocks are contiguous. */
4589 if (i < 6)
4590 {
4591 if ((mask & 0xfe00) == (1 << 9))
4592 {
4593 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
4594 unwind.opcode_count--;
4595 }
4596 }
4597 else if (i == 6 && unwind.opcode_count >= 2)
4598 {
4599 i = unwind.opcodes[unwind.opcode_count - 2];
4600 reg = i >> 4;
4601 i &= 0xf;
b99bd4ef 4602
c19d1205
ZW		 4603 op = 0xffff << (reg - 1);
4604 if (reg > 0
87a1fd79 4605 && ((mask & op) == (1u << (reg - 1))))
c19d1205
ZW		 4606 {
4607 op = (1 << (reg + i + 1)) - 1;
4608 op &= ~((1 << reg) - 1);
4609 mask |= op;
4610 unwind.opcode_count -= 2;
4611 }
4612 }
4613 }
b99bd4ef
NC		 4614 }
4615
c19d1205
ZW		 4616 hi_reg = 15;
4617 /* We want to generate opcodes in the order the registers have been
4618 saved, ie. descending order. */
4619 for (reg = 15; reg >= -1; reg--)
b99bd4ef 4620 {
c19d1205
ZW		 4621 /* Save registers in blocks. */
4622 if (reg < 0
4623 || !(mask & (1 << reg)))
4624 {
4625 /* We found an unsaved reg. Generate opcodes to save the
5f4273c7 4626 preceding block. */
c19d1205
ZW		 4627 if (reg != hi_reg)
4628 {
4629 if (reg == 9)
4630 {
4631 /* Short form. */
4632 op = 0xc0 | (hi_reg - 10);
4633 add_unwind_opcode (op, 1);
4634 }
4635 else
4636 {
4637 /* Long form. */
4638 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4639 add_unwind_opcode (op, 2);
4640 }
4641 }
4642 hi_reg = reg - 1;
4643 }
b99bd4ef
NC		 4644 }
4645
c19d1205 4646 return;
dc1e8a47 4647 error:
c19d1205 4648 ignore_rest_of_line ();
b99bd4ef
NC		 4649}
4650
4651static void
c19d1205 4652s_arm_unwind_save_mmxwcg (void)
b99bd4ef 4653{
c19d1205
ZW		 4654 int reg;
4655 int hi_reg;
4656 unsigned mask = 0;
4657 valueT op;
b99bd4ef 4658
c19d1205
ZW		 4659 if (*input_line_pointer == '{')
4660 input_line_pointer++;
b99bd4ef 4661
477330fc
RM		 4662 skip_whitespace (input_line_pointer);
4663
c19d1205 4664 do
b99bd4ef 4665 {
dcbf9037 4666 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
b99bd4ef 4667
c19d1205
ZW		 4668 if (reg == FAIL)
4669 {
9b7132d3 4670 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
c19d1205
ZW		 4671 goto error;
4672 }
b99bd4ef 4673
c19d1205
ZW		 4674 reg -= 8;
4675 if (mask >> reg)
4676 as_tsktsk (_("register list not in ascending order"));
4677 mask |= 1 << reg;
b99bd4ef 4678
c19d1205
ZW		 4679 if (*input_line_pointer == '-')
4680 {
4681 input_line_pointer++;
dcbf9037 4682 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
c19d1205
ZW		 4683 if (hi_reg == FAIL)
4684 {
9b7132d3 4685 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
c19d1205
ZW		 4686 goto error;
4687 }
4688 else if (reg >= hi_reg)
4689 {
4690 as_bad (_("bad register range"));
4691 goto error;
4692 }
4693 for (; reg < hi_reg; reg++)
4694 mask |= 1 << reg;
4695 }
b99bd4ef 4696 }
c19d1205 4697 while (skip_past_comma (&input_line_pointer) != FAIL);
b99bd4ef 4698
d996d970 4699 skip_past_char (&input_line_pointer, '}');
b99bd4ef 4700
c19d1205
ZW		 4701 demand_empty_rest_of_line ();
4702
708587a4 4703 /* Generate any deferred opcodes because we're going to be looking at
c19d1205
ZW		 4704 the list. */
4705 flush_pending_unwind ();
b99bd4ef 4706
c19d1205 4707 for (reg = 0; reg < 16; reg++)
b99bd4ef 4708 {
c19d1205
ZW		 4709 if (mask & (1 << reg))
4710 unwind.frame_size += 4;
b99bd4ef 4711 }
c19d1205
ZW		 4712 op = 0xc700 | mask;
4713 add_unwind_opcode (op, 2);
4714 return;
dc1e8a47 4715 error:
c19d1205 4716 ignore_rest_of_line ();
b99bd4ef
NC		 4717}
4718
c19d1205 4719
fa073d69
MS		 4720/* Parse an unwind_save directive.
4721 If the argument is non-zero, this is a .vsave directive. */
c19d1205 4722
b99bd4ef 4723static void
fa073d69 4724s_arm_unwind_save (int arch_v6)
b99bd4ef 4725{
c19d1205
ZW		 4726 char *peek;
4727 struct reg_entry *reg;
4728 bfd_boolean had_brace = FALSE;
b99bd4ef 4729
921e5f0a 4730 if (!unwind.proc_start)
c921be7d 4731 as_bad (MISSING_FNSTART);
921e5f0a 4732
c19d1205
ZW		 4733 /* Figure out what sort of save we have. */
4734 peek = input_line_pointer;
b99bd4ef 4735
c19d1205 4736 if (*peek == '{')
b99bd4ef 4737 {
c19d1205
ZW		 4738 had_brace = TRUE;
4739 peek++;
b99bd4ef
NC		 4740 }
4741
c19d1205 4742 reg = arm_reg_parse_multi (&peek);
b99bd4ef 4743
c19d1205 4744 if (!reg)
b99bd4ef 4745 {
c19d1205
ZW		 4746 as_bad (_("register expected"));
4747 ignore_rest_of_line ();
b99bd4ef
NC		 4748 return;
4749 }
4750
c19d1205 4751 switch (reg->type)
b99bd4ef 4752 {
c19d1205
ZW		 4753 case REG_TYPE_FN:
4754 if (had_brace)
4755 {
4756 as_bad (_("FPA .unwind_save does not take a register list"));
4757 ignore_rest_of_line ();
4758 return;
4759 }
93ac2687 4760 input_line_pointer = peek;
c19d1205 4761 s_arm_unwind_save_fpa (reg->number);
b99bd4ef 4762 return;
c19d1205 4763
1f5afe1c
NC		 4764 case REG_TYPE_RN:
4765 s_arm_unwind_save_core ();
4766 return;
4767
fa073d69
MS		 4768 case REG_TYPE_VFD:
4769 if (arch_v6)
477330fc 4770 s_arm_unwind_save_vfp_armv6 ();
fa073d69 4771 else
477330fc 4772 s_arm_unwind_save_vfp ();
fa073d69 4773 return;
1f5afe1c
NC		 4774
4775 case REG_TYPE_MMXWR:
4776 s_arm_unwind_save_mmxwr ();
4777 return;
4778
4779 case REG_TYPE_MMXWCG:
4780 s_arm_unwind_save_mmxwcg ();
4781 return;
c19d1205
ZW		 4782
4783 default:
4784 as_bad (_(".unwind_save does not support this kind of register"));
4785 ignore_rest_of_line ();
b99bd4ef 4786 }
c19d1205 4787}
b99bd4ef 4788
b99bd4ef 4789
c19d1205
ZW		 4790/* Parse an unwind_movsp directive. */
4791
4792static void
4793s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4794{
4795 int reg;
4796 valueT op;
4fa3602b 4797 int offset;
c19d1205 4798
921e5f0a 4799 if (!unwind.proc_start)
c921be7d 4800 as_bad (MISSING_FNSTART);
921e5f0a 4801
dcbf9037 4802 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
c19d1205 4803 if (reg == FAIL)
b99bd4ef 4804 {
9b7132d3 4805 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
c19d1205 4806 ignore_rest_of_line ();
b99bd4ef
NC		 4807 return;
4808 }
4fa3602b
PB		 4809
4810 /* Optional constant. */
4811 if (skip_past_comma (&input_line_pointer) != FAIL)
4812 {
4813 if (immediate_for_directive (&offset) == FAIL)
4814 return;
4815 }
4816 else
4817 offset = 0;
4818
c19d1205 4819 demand_empty_rest_of_line ();
b99bd4ef 4820
c19d1205 4821 if (reg == REG_SP || reg == REG_PC)
b99bd4ef 4822 {
c19d1205 4823 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
b99bd4ef
NC		 4824 return;
4825 }
4826
c19d1205
ZW		 4827 if (unwind.fp_reg != REG_SP)
4828 as_bad (_("unexpected .unwind_movsp directive"));
b99bd4ef 4829
c19d1205
ZW		 4830 /* Generate opcode to restore the value. */
4831 op = 0x90 | reg;
4832 add_unwind_opcode (op, 1);
4833
4834 /* Record the information for later. */
4835 unwind.fp_reg = reg;
4fa3602b 4836 unwind.fp_offset = unwind.frame_size - offset;
c19d1205 4837 unwind.sp_restored = 1;
b05fe5cf
ZW		 4838}
4839
c19d1205
ZW		 4840/* Parse an unwind_pad directive. */
4841
b05fe5cf 4842static void
c19d1205 4843s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
b05fe5cf 4844{
c19d1205 4845 int offset;
b05fe5cf 4846
921e5f0a 4847 if (!unwind.proc_start)
c921be7d 4848 as_bad (MISSING_FNSTART);
921e5f0a 4849
c19d1205
ZW		 4850 if (immediate_for_directive (&offset) == FAIL)
4851 return;
b99bd4ef 4852
c19d1205
ZW		 4853 if (offset & 3)
4854 {
4855 as_bad (_("stack increment must be multiple of 4"));
4856 ignore_rest_of_line ();
4857 return;
4858 }
b99bd4ef 4859
c19d1205
ZW		 4860 /* Don't generate any opcodes, just record the details for later. */
4861 unwind.frame_size += offset;
4862 unwind.pending_offset += offset;
4863
4864 demand_empty_rest_of_line ();
4865}
4866
4867/* Parse an unwind_setfp directive. */
4868
4869static void
4870s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
b99bd4ef 4871{
c19d1205
ZW		 4872 int sp_reg;
4873 int fp_reg;
4874 int offset;
4875
921e5f0a 4876 if (!unwind.proc_start)
c921be7d 4877 as_bad (MISSING_FNSTART);
921e5f0a 4878
dcbf9037 4879 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
c19d1205
ZW		 4880 if (skip_past_comma (&input_line_pointer) == FAIL)
4881 sp_reg = FAIL;
4882 else
dcbf9037 4883 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
b99bd4ef 4884
c19d1205
ZW		 4885 if (fp_reg == FAIL || sp_reg == FAIL)
4886 {
4887 as_bad (_("expected <reg>, <reg>"));
4888 ignore_rest_of_line ();
4889 return;
4890 }
b99bd4ef 4891
c19d1205
ZW		 4892 /* Optional constant. */
4893 if (skip_past_comma (&input_line_pointer) != FAIL)
4894 {
4895 if (immediate_for_directive (&offset) == FAIL)
4896 return;
4897 }
4898 else
4899 offset = 0;
a737bd4d 4900
c19d1205 4901 demand_empty_rest_of_line ();
a737bd4d 4902
fdfde340 4903 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
a737bd4d 4904 {
c19d1205
ZW		 4905 as_bad (_("register must be either sp or set by a previous"
4906 "unwind_movsp directive"));
4907 return;
a737bd4d
NC		 4908 }
4909
c19d1205
ZW		 4910 /* Don't generate any opcodes, just record the information for later. */
4911 unwind.fp_reg = fp_reg;
4912 unwind.fp_used = 1;
fdfde340 4913 if (sp_reg == REG_SP)
c19d1205
ZW		 4914 unwind.fp_offset = unwind.frame_size - offset;
4915 else
4916 unwind.fp_offset -= offset;
a737bd4d
NC		 4917}
4918
c19d1205
ZW		 4919/* Parse an unwind_raw directive. */
4920
4921static void
4922s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
a737bd4d 4923{
c19d1205 4924 expressionS exp;
708587a4 4925 /* This is an arbitrary limit. */
c19d1205
ZW		 4926 unsigned char op[16];
4927 int count;
a737bd4d 4928
921e5f0a 4929 if (!unwind.proc_start)
c921be7d 4930 as_bad (MISSING_FNSTART);
921e5f0a 4931
c19d1205
ZW		 4932 expression (&exp);
4933 if (exp.X_op == O_constant
4934 && skip_past_comma (&input_line_pointer) != FAIL)
a737bd4d 4935 {
c19d1205
ZW		 4936 unwind.frame_size += exp.X_add_number;
4937 expression (&exp);
4938 }
4939 else
4940 exp.X_op = O_illegal;
a737bd4d 4941
c19d1205
ZW		 4942 if (exp.X_op != O_constant)
4943 {
4944 as_bad (_("expected <offset>, <opcode>"));
4945 ignore_rest_of_line ();
4946 return;
4947 }
a737bd4d 4948
c19d1205 4949 count = 0;
a737bd4d 4950
c19d1205
ZW		 4951 /* Parse the opcode. */
4952 for (;;)
4953 {
4954 if (count >= 16)
4955 {
4956 as_bad (_("unwind opcode too long"));
4957 ignore_rest_of_line ();
a737bd4d 4958 }
c19d1205 4959 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
a737bd4d 4960 {
c19d1205
ZW		 4961 as_bad (_("invalid unwind opcode"));
4962 ignore_rest_of_line ();
4963 return;
a737bd4d 4964 }
c19d1205 4965 op[count++] = exp.X_add_number;
a737bd4d 4966
c19d1205
ZW		 4967 /* Parse the next byte. */
4968 if (skip_past_comma (&input_line_pointer) == FAIL)
4969 break;
a737bd4d 4970
c19d1205
ZW		 4971 expression (&exp);
4972 }
b99bd4ef 4973
c19d1205
ZW		 4974 /* Add the opcode bytes in reverse order. */
4975 while (count--)
4976 add_unwind_opcode (op[count], 1);
b99bd4ef 4977
c19d1205 4978 demand_empty_rest_of_line ();
b99bd4ef 4979}
ee065d83
PB		 4980
4981
4982/* Parse a .eabi_attribute directive. */
4983
4984static void
4985s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4986{
0420f52b 4987 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
ee3c0378 4988
3076e594 4989 if (tag >= 0 && tag < NUM_KNOWN_OBJ_ATTRIBUTES)
ee3c0378 4990 attributes_set_explicitly[tag] = 1;
ee065d83
PB		 4991}
4992
0855e32b
NS		 4993/* Emit a tls fix for the symbol. */
4994
4995static void
4996s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4997{
4998 char *p;
4999 expressionS exp;
5000#ifdef md_flush_pending_output
5001 md_flush_pending_output ();
5002#endif
5003
5004#ifdef md_cons_align
5005 md_cons_align (4);
5006#endif
5007
5008 /* Since we're just labelling the code, there's no need to define a
5009 mapping symbol. */
5010 expression (&exp);
5011 p = obstack_next_free (&frchain_now->frch_obstack);
5012 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
5013 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
5014 : BFD_RELOC_ARM_TLS_DESCSEQ);
5015}
cdf9ccec 5016#endif /* OBJ_ELF */
0855e32b 5017
ee065d83 5018static void s_arm_arch (int);
7a1d4c38 5019static void s_arm_object_arch (int);
ee065d83
PB		 5020static void s_arm_cpu (int);
5021static void s_arm_fpu (int);
69133863 5022static void s_arm_arch_extension (int);
b99bd4ef 5023
f0927246
NC		 5024#ifdef TE_PE
5025
5026static void
5f4273c7 5027pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
f0927246
NC		 5028{
5029 expressionS exp;
5030
5031 do
5032 {
5033 expression (&exp);
5034 if (exp.X_op == O_symbol)
5035 exp.X_op = O_secrel;
5036
5037 emit_expr (&exp, 4);
5038 }
5039 while (*input_line_pointer++ == ',');
5040
5041 input_line_pointer--;
5042 demand_empty_rest_of_line ();
5043}
5044#endif /* TE_PE */
5045
5312fe52
BW		 5046int
5047arm_is_largest_exponent_ok (int precision)
5048{
5049 /* precision == 1 ensures that this will only return
5050 true for 16 bit floats. */
5051 return (precision == 1) && (fp16_format == ARM_FP16_FORMAT_ALTERNATIVE);
5052}
5053
5054static void
5055set_fp16_format (int dummy ATTRIBUTE_UNUSED)
5056{
5057 char saved_char;
5058 char* name;
5059 enum fp_16bit_format new_format;
5060
5061 new_format = ARM_FP16_FORMAT_DEFAULT;
5062
5063 name = input_line_pointer;
5064 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
5065 input_line_pointer++;
5066
5067 saved_char = *input_line_pointer;
5068 *input_line_pointer = 0;
5069
5070 if (strcasecmp (name, "ieee") == 0)
5071 new_format = ARM_FP16_FORMAT_IEEE;
5072 else if (strcasecmp (name, "alternative") == 0)
5073 new_format = ARM_FP16_FORMAT_ALTERNATIVE;
5074 else
5075 {
5076 as_bad (_("unrecognised float16 format \"%s\""), name);
5077 goto cleanup;
5078 }
5079
5080 /* Only set fp16_format if it is still the default (aka not already
5081 been set yet). */
5082 if (fp16_format == ARM_FP16_FORMAT_DEFAULT)
5083 fp16_format = new_format;
5084 else
5085 {
5086 if (new_format != fp16_format)
5087 as_warn (_("float16 format cannot be set more than once, ignoring."));
5088 }
5089
dc1e8a47 5090 cleanup:
5312fe52
BW		 5091 *input_line_pointer = saved_char;
5092 ignore_rest_of_line ();
5093}
5094
c19d1205
ZW		 5095/* This table describes all the machine specific pseudo-ops the assembler
5096 has to support. The fields are:
5097 pseudo-op name without dot
5098 function to call to execute this pseudo-op
5099 Integer arg to pass to the function. */
b99bd4ef 5100
c19d1205 5101const pseudo_typeS md_pseudo_table[] =
b99bd4ef 5102{
c19d1205
ZW		 5103 /* Never called because '.req' does not start a line. */
5104 { "req", s_req, 0 },
dcbf9037
JB		 5105 /* Following two are likewise never called. */
5106 { "dn", s_dn, 0 },
5107 { "qn", s_qn, 0 },
c19d1205
ZW		 5108 { "unreq", s_unreq, 0 },
5109 { "bss", s_bss, 0 },
db2ed2e0 5110 { "align", s_align_ptwo, 2 },
c19d1205
ZW		 5111 { "arm", s_arm, 0 },
5112 { "thumb", s_thumb, 0 },
5113 { "code", s_code, 0 },
5114 { "force_thumb", s_force_thumb, 0 },
5115 { "thumb_func", s_thumb_func, 0 },
5116 { "thumb_set", s_thumb_set, 0 },
5117 { "even", s_even, 0 },
5118 { "ltorg", s_ltorg, 0 },
5119 { "pool", s_ltorg, 0 },
5120 { "syntax", s_syntax, 0 },
8463be01
PB		 5121 { "cpu", s_arm_cpu, 0 },
5122 { "arch", s_arm_arch, 0 },
7a1d4c38 5123 { "object_arch", s_arm_object_arch, 0 },
8463be01 5124 { "fpu", s_arm_fpu, 0 },
69133863 5125 { "arch_extension", s_arm_arch_extension, 0 },
c19d1205 5126#ifdef OBJ_ELF
c921be7d
NC		 5127 { "word", s_arm_elf_cons, 4 },
5128 { "long", s_arm_elf_cons, 4 },
5129 { "inst.n", s_arm_elf_inst, 2 },
5130 { "inst.w", s_arm_elf_inst, 4 },
5131 { "inst", s_arm_elf_inst, 0 },
5132 { "rel31", s_arm_rel31, 0 },
c19d1205
ZW		 5133 { "fnstart", s_arm_unwind_fnstart, 0 },
5134 { "fnend", s_arm_unwind_fnend, 0 },
5135 { "cantunwind", s_arm_unwind_cantunwind, 0 },
5136 { "personality", s_arm_unwind_personality, 0 },
5137 { "personalityindex", s_arm_unwind_personalityindex, 0 },
5138 { "handlerdata", s_arm_unwind_handlerdata, 0 },
5139 { "save", s_arm_unwind_save, 0 },
fa073d69 5140 { "vsave", s_arm_unwind_save, 1 },
c19d1205
ZW		 5141 { "movsp", s_arm_unwind_movsp, 0 },
5142 { "pad", s_arm_unwind_pad, 0 },
5143 { "setfp", s_arm_unwind_setfp, 0 },
5144 { "unwind_raw", s_arm_unwind_raw, 0 },
ee065d83 5145 { "eabi_attribute", s_arm_eabi_attribute, 0 },
0855e32b 5146 { "tlsdescseq", s_arm_tls_descseq, 0 },
c19d1205
ZW		 5147#else
5148 { "word", cons, 4},
f0927246
NC		 5149
5150 /* These are used for dwarf. */
5151 {"2byte", cons, 2},
5152 {"4byte", cons, 4},
5153 {"8byte", cons, 8},
5154 /* These are used for dwarf2. */
68d20676 5155 { "file", dwarf2_directive_file, 0 },
f0927246
NC		 5156 { "loc", dwarf2_directive_loc, 0 },
5157 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
c19d1205
ZW		 5158#endif
5159 { "extend", float_cons, 'x' },
5160 { "ldouble", float_cons, 'x' },
5161 { "packed", float_cons, 'p' },
27cce866 5162 { "bfloat16", float_cons, 'b' },
f0927246
NC		 5163#ifdef TE_PE
5164 {"secrel32", pe_directive_secrel, 0},
5165#endif
2e6976a8
DG		 5166
5167 /* These are for compatibility with CodeComposer Studio. */
5168 {"ref", s_ccs_ref, 0},
5169 {"def", s_ccs_def, 0},
5170 {"asmfunc", s_ccs_asmfunc, 0},
5171 {"endasmfunc", s_ccs_endasmfunc, 0},
5172
5312fe52
BW		 5173 {"float16", float_cons, 'h' },
5174 {"float16_format", set_fp16_format, 0 },
5175
c19d1205
ZW		 5176 { 0, 0, 0 }
5177};
5312fe52 5178
c19d1205 5179/* Parser functions used exclusively in instruction operands. */
b99bd4ef 5180
c19d1205
ZW		 5181/* Generic immediate-value read function for use in insn parsing.
5182 STR points to the beginning of the immediate (the leading #);
5183 VAL receives the value; if the value is outside [MIN, MAX]
5184 issue an error. PREFIX_OPT is true if the immediate prefix is
5185 optional. */
b99bd4ef 5186
c19d1205
ZW		 5187static int
5188parse_immediate (char **str, int *val, int min, int max,
5189 bfd_boolean prefix_opt)
5190{
5191 expressionS exp;
0198d5e6 5192
c19d1205
ZW		 5193 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
5194 if (exp.X_op != O_constant)
b99bd4ef 5195 {
c19d1205
ZW		 5196 inst.error = _("constant expression required");
5197 return FAIL;
5198 }
b99bd4ef 5199
c19d1205
ZW		 5200 if (exp.X_add_number < min || exp.X_add_number > max)
5201 {
5202 inst.error = _("immediate value out of range");
5203 return FAIL;
5204 }
b99bd4ef 5205
c19d1205
ZW		 5206 *val = exp.X_add_number;
5207 return SUCCESS;
5208}
b99bd4ef 5209
5287ad62 5210/* Less-generic immediate-value read function with the possibility of loading a
036dc3f7 5211 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5287ad62
JB		 5212 instructions. Puts the result directly in inst.operands[i]. */
5213
5214static int
8335d6aa
JW		 5215parse_big_immediate (char **str, int i, expressionS *in_exp,
5216 bfd_boolean allow_symbol_p)
5287ad62
JB		 5217{
5218 expressionS exp;
8335d6aa 5219 expressionS *exp_p = in_exp ? in_exp : &exp;
5287ad62
JB		 5220 char *ptr = *str;
5221
8335d6aa 5222 my_get_expression (exp_p, &ptr, GE_OPT_PREFIX_BIG);
5287ad62 5223
8335d6aa 5224 if (exp_p->X_op == O_constant)
036dc3f7 5225 {
8335d6aa 5226 inst.operands[i].imm = exp_p->X_add_number & 0xffffffff;
036dc3f7
PB		 5227 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5228 O_constant. We have to be careful not to break compilation for
5229 32-bit X_add_number, though. */
8335d6aa 5230 if ((exp_p->X_add_number & ~(offsetT)(0xffffffffU)) != 0)
036dc3f7 5231 {
8335d6aa
JW		 5232 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5233 inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16)
5234 & 0xffffffff);
036dc3f7
PB		 5235 inst.operands[i].regisimm = 1;
5236 }
5237 }
8335d6aa
JW		 5238 else if (exp_p->X_op == O_big
5239 && LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 32)
5287ad62
JB		 5240 {
5241 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
95b75c01 5242
5287ad62 5243 /* Bignums have their least significant bits in
477330fc
RM		 5244 generic_bignum[0]. Make sure we put 32 bits in imm and
5245 32 bits in reg, in a (hopefully) portable way. */
9c2799c2 5246 gas_assert (parts != 0);
95b75c01
NC		 5247
5248 /* Make sure that the number is not too big.
5249 PR 11972: Bignums can now be sign-extended to the
5250 size of a .octa so check that the out of range bits
5251 are all zero or all one. */
8335d6aa 5252 if (LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 64)
95b75c01
NC		 5253 {
5254 LITTLENUM_TYPE m = -1;
5255
5256 if (generic_bignum[parts * 2] != 0
5257 && generic_bignum[parts * 2] != m)
5258 return FAIL;
5259
8335d6aa 5260 for (j = parts * 2 + 1; j < (unsigned) exp_p->X_add_number; j++)
95b75c01
NC		 5261 if (generic_bignum[j] != generic_bignum[j-1])
5262 return FAIL;
5263 }
5264
5287ad62
JB		 5265 inst.operands[i].imm = 0;
5266 for (j = 0; j < parts; j++, idx++)
477330fc
RM		 5267 inst.operands[i].imm |= generic_bignum[idx]
5268 << (LITTLENUM_NUMBER_OF_BITS * j);
5287ad62
JB		 5269 inst.operands[i].reg = 0;
5270 for (j = 0; j < parts; j++, idx++)
477330fc
RM		 5271 inst.operands[i].reg |= generic_bignum[idx]
5272 << (LITTLENUM_NUMBER_OF_BITS * j);
5287ad62
JB		 5273 inst.operands[i].regisimm = 1;
5274 }
8335d6aa 5275 else if (!(exp_p->X_op == O_symbol && allow_symbol_p))
5287ad62 5276 return FAIL;
5f4273c7 5277
5287ad62
JB		 5278 *str = ptr;
5279
5280 return SUCCESS;
5281}
5282
c19d1205
ZW		 5283/* Returns the pseudo-register number of an FPA immediate constant,
5284 or FAIL if there isn't a valid constant here. */
b99bd4ef 5285
c19d1205
ZW		 5286static int
5287parse_fpa_immediate (char ** str)
5288{
5289 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5290 char * save_in;
5291 expressionS exp;
5292 int i;
5293 int j;
b99bd4ef 5294
c19d1205
ZW		 5295 /* First try and match exact strings, this is to guarantee
5296 that some formats will work even for cross assembly. */
b99bd4ef 5297
c19d1205
ZW		 5298 for (i = 0; fp_const[i]; i++)
5299 {
5300 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
b99bd4ef 5301 {
c19d1205 5302 char *start = *str;
b99bd4ef 5303
c19d1205
ZW		 5304 *str += strlen (fp_const[i]);
5305 if (is_end_of_line[(unsigned char) **str])
5306 return i + 8;
5307 *str = start;
5308 }
5309 }
b99bd4ef 5310
c19d1205
ZW		 5311 /* Just because we didn't get a match doesn't mean that the constant
5312 isn't valid, just that it is in a format that we don't
5313 automatically recognize. Try parsing it with the standard
5314 expression routines. */
b99bd4ef 5315
c19d1205 5316 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
b99bd4ef 5317
c19d1205
ZW		 5318 /* Look for a raw floating point number. */
5319 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
5320 && is_end_of_line[(unsigned char) *save_in])
5321 {
5322 for (i = 0; i < NUM_FLOAT_VALS; i++)
5323 {
5324 for (j = 0; j < MAX_LITTLENUMS; j++)
b99bd4ef 5325 {
c19d1205
ZW		 5326 if (words[j] != fp_values[i][j])
5327 break;
b99bd4ef
NC		 5328 }
5329
c19d1205 5330 if (j == MAX_LITTLENUMS)
b99bd4ef 5331 {
c19d1205
ZW		 5332 *str = save_in;
5333 return i + 8;
b99bd4ef
NC		 5334 }
5335 }
5336 }
b99bd4ef 5337
c19d1205
ZW		 5338 /* Try and parse a more complex expression, this will probably fail
5339 unless the code uses a floating point prefix (eg "0f"). */
5340 save_in = input_line_pointer;
5341 input_line_pointer = *str;
5342 if (expression (&exp) == absolute_section
5343 && exp.X_op == O_big
5344 && exp.X_add_number < 0)
5345 {
5346 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5347 Ditto for 15. */
ba592044
AM		 5348#define X_PRECISION 5
5349#define E_PRECISION 15L
5350 if (gen_to_words (words, X_PRECISION, E_PRECISION) == 0)
c19d1205
ZW		 5351 {
5352 for (i = 0; i < NUM_FLOAT_VALS; i++)
5353 {
5354 for (j = 0; j < MAX_LITTLENUMS; j++)
5355 {
5356 if (words[j] != fp_values[i][j])
5357 break;
5358 }
b99bd4ef 5359
c19d1205
ZW		 5360 if (j == MAX_LITTLENUMS)
5361 {
5362 *str = input_line_pointer;
5363 input_line_pointer = save_in;
5364 return i + 8;
5365 }
5366 }
5367 }
b99bd4ef
NC		 5368 }
5369
c19d1205
ZW		 5370 *str = input_line_pointer;
5371 input_line_pointer = save_in;
5372 inst.error = _("invalid FPA immediate expression");
5373 return FAIL;
b99bd4ef
NC		 5374}
5375
136da414
JB		 5376/* Returns 1 if a number has "quarter-precision" float format
5377 0baBbbbbbc defgh000 00000000 00000000. */
5378
5379static int
5380is_quarter_float (unsigned imm)
5381{
5382 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
5383 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
5384}
5385
aacf0b33
KT		 5386
5387/* Detect the presence of a floating point or integer zero constant,
5388 i.e. #0.0 or #0. */
5389
5390static bfd_boolean
5391parse_ifimm_zero (char **in)
5392{
5393 int error_code;
5394
5395 if (!is_immediate_prefix (**in))
3c6452ae
TP		 5396 {
5397 /* In unified syntax, all prefixes are optional. */
5398 if (!unified_syntax)
5399 return FALSE;
5400 }
5401 else
5402 ++*in;
0900a05b
JW		 5403
5404 /* Accept #0x0 as a synonym for #0. */
5405 if (strncmp (*in, "0x", 2) == 0)
5406 {
5407 int val;
5408 if (parse_immediate (in, &val, 0, 0, TRUE) == FAIL)
5409 return FALSE;
5410 return TRUE;
5411 }
5412
aacf0b33
KT		 5413 error_code = atof_generic (in, ".", EXP_CHARS,
5414 &generic_floating_point_number);
5415
5416 if (!error_code
5417 && generic_floating_point_number.sign == '+'
5418 && (generic_floating_point_number.low
5419 > generic_floating_point_number.leader))
5420 return TRUE;
5421
5422 return FALSE;
5423}
5424
136da414
JB		 5425/* Parse an 8-bit "quarter-precision" floating point number of the form:
5426 0baBbbbbbc defgh000 00000000 00000000.
c96612cc
JB		 5427 The zero and minus-zero cases need special handling, since they can't be
5428 encoded in the "quarter-precision" float format, but can nonetheless be
5429 loaded as integer constants. */
136da414
JB		 5430
5431static unsigned
5432parse_qfloat_immediate (char **ccp, int *immed)
5433{
5434 char *str = *ccp;
c96612cc 5435 char *fpnum;
136da414 5436 LITTLENUM_TYPE words[MAX_LITTLENUMS];
c96612cc 5437 int found_fpchar = 0;
5f4273c7 5438
136da414 5439 skip_past_char (&str, '#');
5f4273c7 5440
c96612cc
JB		 5441 /* We must not accidentally parse an integer as a floating-point number. Make
5442 sure that the value we parse is not an integer by checking for special
5443 characters '.' or 'e'.
5444 FIXME: This is a horrible hack, but doing better is tricky because type
5445 information isn't in a very usable state at parse time. */
5446 fpnum = str;
5447 skip_whitespace (fpnum);
5448
5449 if (strncmp (fpnum, "0x", 2) == 0)
5450 return FAIL;
5451 else
5452 {
5453 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
477330fc
RM		 5454 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
5455 {
5456 found_fpchar = 1;
5457 break;
5458 }
c96612cc
JB		 5459
5460 if (!found_fpchar)
477330fc 5461 return FAIL;
c96612cc 5462 }
5f4273c7 5463
136da414
JB		 5464 if ((str = atof_ieee (str, 's', words)) != NULL)
5465 {
5466 unsigned fpword = 0;
5467 int i;
5f4273c7 5468
136da414
JB		 5469 /* Our FP word must be 32 bits (single-precision FP). */
5470 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
477330fc
RM		 5471 {
5472 fpword <<= LITTLENUM_NUMBER_OF_BITS;
5473 fpword |= words[i];
5474 }
5f4273c7 5475
c96612cc 5476 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
477330fc 5477 *immed = fpword;
136da414 5478 else
477330fc 5479 return FAIL;
136da414
JB		 5480
5481 *ccp = str;
5f4273c7 5482
136da414
JB		 5483 return SUCCESS;
5484 }
5f4273c7 5485
136da414
JB		 5486 return FAIL;
5487}
5488
c19d1205
ZW		 5489/* Shift operands. */
5490enum shift_kind
b99bd4ef 5491{
f5f10c66 5492 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX, SHIFT_UXTW
c19d1205 5493};
b99bd4ef 5494
c19d1205
ZW		 5495struct asm_shift_name
5496{
5497 const char *name;
5498 enum shift_kind kind;
5499};
b99bd4ef 5500
c19d1205
ZW		 5501/* Third argument to parse_shift. */
5502enum parse_shift_mode
5503{
5504 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
5505 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
5506 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
5507 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
5508 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
f5f10c66 5509 SHIFT_UXTW_IMMEDIATE /* Shift must be UXTW immediate. */
c19d1205 5510};
b99bd4ef 5511
c19d1205
ZW		 5512/* Parse a <shift> specifier on an ARM data processing instruction.
5513 This has three forms:
b99bd4ef 5514
c19d1205
ZW		 5515 (LSL|LSR|ASL|ASR|ROR) Rs
5516 (LSL|LSR|ASL|ASR|ROR) #imm
5517 RRX
b99bd4ef 5518
c19d1205
ZW		 5519 Note that ASL is assimilated to LSL in the instruction encoding, and
5520 RRX to ROR #0 (which cannot be written as such). */
b99bd4ef 5521
c19d1205
ZW		 5522static int
5523parse_shift (char **str, int i, enum parse_shift_mode mode)
b99bd4ef 5524{
c19d1205
ZW		 5525 const struct asm_shift_name *shift_name;
5526 enum shift_kind shift;
5527 char *s = *str;
5528 char *p = s;
5529 int reg;
b99bd4ef 5530
c19d1205
ZW		 5531 for (p = *str; ISALPHA (*p); p++)
5532 ;
b99bd4ef 5533
c19d1205 5534 if (p == *str)
b99bd4ef 5535 {
c19d1205
ZW		 5536 inst.error = _("shift expression expected");
5537 return FAIL;
b99bd4ef
NC		 5538 }
5539
21d799b5 5540 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
477330fc 5541 p - *str);
c19d1205
ZW		 5542
5543 if (shift_name == NULL)
b99bd4ef 5544 {
c19d1205
ZW		 5545 inst.error = _("shift expression expected");
5546 return FAIL;
b99bd4ef
NC		 5547 }
5548
c19d1205 5549 shift = shift_name->kind;
b99bd4ef 5550
c19d1205
ZW		 5551 switch (mode)
5552 {
5553 case NO_SHIFT_RESTRICT:
f5f10c66
AV		 5554 case SHIFT_IMMEDIATE:
5555 if (shift == SHIFT_UXTW)
5556 {
5557 inst.error = _("'UXTW' not allowed here");
5558 return FAIL;
5559 }
5560 break;
b99bd4ef 5561
c19d1205
ZW		 5562 case SHIFT_LSL_OR_ASR_IMMEDIATE:
5563 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
5564 {
5565 inst.error = _("'LSL' or 'ASR' required");
5566 return FAIL;
5567 }
5568 break;
b99bd4ef 5569
c19d1205
ZW		 5570 case SHIFT_LSL_IMMEDIATE:
5571 if (shift != SHIFT_LSL)
5572 {
5573 inst.error = _("'LSL' required");
5574 return FAIL;
5575 }
5576 break;
b99bd4ef 5577
c19d1205
ZW		 5578 case SHIFT_ASR_IMMEDIATE:
5579 if (shift != SHIFT_ASR)
5580 {
5581 inst.error = _("'ASR' required");
5582 return FAIL;
5583 }
5584 break;
f5f10c66
AV		 5585 case SHIFT_UXTW_IMMEDIATE:
5586 if (shift != SHIFT_UXTW)
5587 {
5588 inst.error = _("'UXTW' required");
5589 return FAIL;
5590 }
5591 break;
b99bd4ef 5592
c19d1205
ZW		 5593 default: abort ();
5594 }
b99bd4ef 5595
c19d1205
ZW		 5596 if (shift != SHIFT_RRX)
5597 {
5598 /* Whitespace can appear here if the next thing is a bare digit. */
5599 skip_whitespace (p);
b99bd4ef 5600
c19d1205 5601 if (mode == NO_SHIFT_RESTRICT
dcbf9037 5602 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
c19d1205
ZW		 5603 {
5604 inst.operands[i].imm = reg;
5605 inst.operands[i].immisreg = 1;
5606 }
e2b0ab59 5607 else if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
c19d1205
ZW		 5608 return FAIL;
5609 }
5610 inst.operands[i].shift_kind = shift;
5611 inst.operands[i].shifted = 1;
5612 *str = p;
5613 return SUCCESS;
b99bd4ef
NC		 5614}
5615
c19d1205 5616/* Parse a <shifter_operand> for an ARM data processing instruction:
b99bd4ef 5617
c19d1205
ZW		 5618 #<immediate>
5619 #<immediate>, <rotate>
5620 <Rm>
5621 <Rm>, <shift>
b99bd4ef 5622
c19d1205
ZW		 5623 where <shift> is defined by parse_shift above, and <rotate> is a
5624 multiple of 2 between 0 and 30. Validation of immediate operands
55cf6793 5625 is deferred to md_apply_fix. */
b99bd4ef 5626
c19d1205
ZW		 5627static int
5628parse_shifter_operand (char **str, int i)
5629{
5630 int value;
91d6fa6a 5631 expressionS exp;
b99bd4ef 5632
dcbf9037 5633 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
c19d1205
ZW		 5634 {
5635 inst.operands[i].reg = value;
5636 inst.operands[i].isreg = 1;
b99bd4ef 5637
c19d1205 5638 /* parse_shift will override this if appropriate */
e2b0ab59
AV		 5639 inst.relocs[0].exp.X_op = O_constant;
5640 inst.relocs[0].exp.X_add_number = 0;
b99bd4ef 5641
c19d1205
ZW		 5642 if (skip_past_comma (str) == FAIL)
5643 return SUCCESS;
b99bd4ef 5644
c19d1205
ZW		 5645 /* Shift operation on register. */
5646 return parse_shift (str, i, NO_SHIFT_RESTRICT);
b99bd4ef
NC		 5647 }
5648
e2b0ab59 5649 if (my_get_expression (&inst.relocs[0].exp, str, GE_IMM_PREFIX))
c19d1205 5650 return FAIL;
b99bd4ef 5651
c19d1205 5652 if (skip_past_comma (str) == SUCCESS)
b99bd4ef 5653 {
c19d1205 5654 /* #x, y -- ie explicit rotation by Y. */
91d6fa6a 5655 if (my_get_expression (&exp, str, GE_NO_PREFIX))
c19d1205 5656 return FAIL;
b99bd4ef 5657
e2b0ab59 5658 if (exp.X_op != O_constant || inst.relocs[0].exp.X_op != O_constant)
c19d1205
ZW		 5659 {
5660 inst.error = _("constant expression expected");
5661 return FAIL;
5662 }
b99bd4ef 5663
91d6fa6a 5664 value = exp.X_add_number;
c19d1205
ZW		 5665 if (value < 0 || value > 30 || value % 2 != 0)
5666 {
5667 inst.error = _("invalid rotation");
5668 return FAIL;
5669 }
e2b0ab59
AV		 5670 if (inst.relocs[0].exp.X_add_number < 0
5671 || inst.relocs[0].exp.X_add_number > 255)
c19d1205
ZW		 5672 {
5673 inst.error = _("invalid constant");
5674 return FAIL;
5675 }
09d92015 5676
a415b1cd 5677 /* Encode as specified. */
e2b0ab59 5678 inst.operands[i].imm = inst.relocs[0].exp.X_add_number | value << 7;
a415b1cd 5679 return SUCCESS;
09d92015
MM		 5680 }
5681
e2b0ab59
AV		 5682 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
5683 inst.relocs[0].pc_rel = 0;
c19d1205 5684 return SUCCESS;
09d92015
MM		 5685}
5686
4962c51a
MS		 5687/* Group relocation information. Each entry in the table contains the
5688 textual name of the relocation as may appear in assembler source
5689 and must end with a colon.
5690 Along with this textual name are the relocation codes to be used if
5691 the corresponding instruction is an ALU instruction (ADD or SUB only),
5692 an LDR, an LDRS, or an LDC. */
5693
5694struct group_reloc_table_entry
5695{
5696 const char *name;
5697 int alu_code;
5698 int ldr_code;
5699 int ldrs_code;
5700 int ldc_code;
5701};
5702
5703typedef enum
5704{
5705 /* Varieties of non-ALU group relocation. */
5706
5707 GROUP_LDR,
5708 GROUP_LDRS,
35c228db
AV		 5709 GROUP_LDC,
5710 GROUP_MVE
4962c51a
MS		 5711} group_reloc_type;
5712
5713static struct group_reloc_table_entry group_reloc_table[] =
5714 { /* Program counter relative: */
5715 { "pc_g0_nc",
5716 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
5717 0, /* LDR */
5718 0, /* LDRS */
5719 0 }, /* LDC */
5720 { "pc_g0",
5721 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
5722 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
5723 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
5724 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
5725 { "pc_g1_nc",
5726 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
5727 0, /* LDR */
5728 0, /* LDRS */
5729 0 }, /* LDC */
5730 { "pc_g1",
5731 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
5732 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
5733 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
5734 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
5735 { "pc_g2",
5736 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
5737 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
5738 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
5739 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
5740 /* Section base relative */
5741 { "sb_g0_nc",
5742 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
5743 0, /* LDR */
5744 0, /* LDRS */
5745 0 }, /* LDC */
5746 { "sb_g0",
5747 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
5748 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
5749 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
5750 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
5751 { "sb_g1_nc",
5752 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
5753 0, /* LDR */
5754 0, /* LDRS */
5755 0 }, /* LDC */
5756 { "sb_g1",
5757 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
5758 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
5759 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
5760 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
5761 { "sb_g2",
5762 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
5763 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
5764 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
72d98d16
MG		 5765 BFD_RELOC_ARM_LDC_SB_G2 }, /* LDC */
5766 /* Absolute thumb alu relocations. */
5767 { "lower0_7",
5768 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC,/* ALU. */
5769 0, /* LDR. */
5770 0, /* LDRS. */
5771 0 }, /* LDC. */
5772 { "lower8_15",
5773 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC,/* ALU. */
5774 0, /* LDR. */
5775 0, /* LDRS. */
5776 0 }, /* LDC. */
5777 { "upper0_7",
5778 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC,/* ALU. */
5779 0, /* LDR. */
5780 0, /* LDRS. */
5781 0 }, /* LDC. */
5782 { "upper8_15",
5783 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC,/* ALU. */
5784 0, /* LDR. */
5785 0, /* LDRS. */
5786 0 } }; /* LDC. */
4962c51a
MS		 5787
5788/* Given the address of a pointer pointing to the textual name of a group
5789 relocation as may appear in assembler source, attempt to find its details
5790 in group_reloc_table. The pointer will be updated to the character after
5791 the trailing colon. On failure, FAIL will be returned; SUCCESS
5792 otherwise. On success, *entry will be updated to point at the relevant
5793 group_reloc_table entry. */
5794
5795static int
5796find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5797{
5798 unsigned int i;
5799 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5800 {
5801 int length = strlen (group_reloc_table[i].name);
5802
5f4273c7
NC		 5803 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5804 && (*str)[length] == ':')
477330fc
RM		 5805 {
5806 *out = &group_reloc_table[i];
5807 *str += (length + 1);
5808 return SUCCESS;
5809 }
4962c51a
MS		 5810 }
5811
5812 return FAIL;
5813}
5814
5815/* Parse a <shifter_operand> for an ARM data processing instruction
5816 (as for parse_shifter_operand) where group relocations are allowed:
5817
5818 #<immediate>
5819 #<immediate>, <rotate>
5820 #:<group_reloc>:<expression>
5821 <Rm>
5822 <Rm>, <shift>
5823
5824 where <group_reloc> is one of the strings defined in group_reloc_table.
5825 The hashes are optional.
5826
5827 Everything else is as for parse_shifter_operand. */
5828
5829static parse_operand_result
5830parse_shifter_operand_group_reloc (char **str, int i)
5831{
5832 /* Determine if we have the sequence of characters #: or just :
5833 coming next. If we do, then we check for a group relocation.
5834 If we don't, punt the whole lot to parse_shifter_operand. */
5835
5836 if (((*str)[0] == '#' && (*str)[1] == ':')
5837 || (*str)[0] == ':')
5838 {
5839 struct group_reloc_table_entry *entry;
5840
5841 if ((*str)[0] == '#')
477330fc 5842 (*str) += 2;
4962c51a 5843 else
477330fc 5844 (*str)++;
4962c51a
MS		 5845
5846 /* Try to parse a group relocation. Anything else is an error. */
5847 if (find_group_reloc_table_entry (str, &entry) == FAIL)
477330fc
RM		 5848 {
5849 inst.error = _("unknown group relocation");
5850 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5851 }
4962c51a
MS		 5852
5853 /* We now have the group relocation table entry corresponding to
477330fc 5854 the name in the assembler source. Next, we parse the expression. */
e2b0ab59 5855 if (my_get_expression (&inst.relocs[0].exp, str, GE_NO_PREFIX))
477330fc 5856 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4962c51a
MS		 5857
5858 /* Record the relocation type (always the ALU variant here). */
e2b0ab59
AV		 5859 inst.relocs[0].type = (bfd_reloc_code_real_type) entry->alu_code;
5860 gas_assert (inst.relocs[0].type != 0);
4962c51a
MS		 5861
5862 return PARSE_OPERAND_SUCCESS;
5863 }
5864 else
5865 return parse_shifter_operand (str, i) == SUCCESS
477330fc 5866 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
4962c51a
MS		 5867
5868 /* Never reached. */
5869}
5870
8e560766
MGD		 5871/* Parse a Neon alignment expression. Information is written to
5872 inst.operands[i]. We assume the initial ':' has been skipped.
fa94de6b 5873
8e560766
MGD		 5874 align .imm = align << 8, .immisalign=1, .preind=0 */
5875static parse_operand_result
5876parse_neon_alignment (char **str, int i)
5877{
5878 char *p = *str;
5879 expressionS exp;
5880
5881 my_get_expression (&exp, &p, GE_NO_PREFIX);
5882
5883 if (exp.X_op != O_constant)
5884 {
5885 inst.error = _("alignment must be constant");
5886 return PARSE_OPERAND_FAIL;
5887 }
5888
5889 inst.operands[i].imm = exp.X_add_number << 8;
5890 inst.operands[i].immisalign = 1;
5891 /* Alignments are not pre-indexes. */
5892 inst.operands[i].preind = 0;
5893
5894 *str = p;
5895 return PARSE_OPERAND_SUCCESS;
5896}
5897
c19d1205 5898/* Parse all forms of an ARM address expression. Information is written
e2b0ab59 5899 to inst.operands[i] and/or inst.relocs[0].
09d92015 5900
c19d1205 5901 Preindexed addressing (.preind=1):
09d92015 5902
e2b0ab59 5903 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
c19d1205
ZW		 5904 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5905 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
e2b0ab59 5906 .shift_kind=shift .relocs[0].exp=shift_imm
09d92015 5907
c19d1205 5908 These three may have a trailing ! which causes .writeback to be set also.
09d92015 5909
c19d1205 5910 Postindexed addressing (.postind=1, .writeback=1):
09d92015 5911
e2b0ab59 5912 [Rn], #offset .reg=Rn .relocs[0].exp=offset
c19d1205
ZW		 5913 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5914 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
e2b0ab59 5915 .shift_kind=shift .relocs[0].exp=shift_imm
09d92015 5916
c19d1205 5917 Unindexed addressing (.preind=0, .postind=0):
09d92015 5918
c19d1205 5919 [Rn], {option} .reg=Rn .imm=option .immisreg=0
09d92015 5920
c19d1205 5921 Other:
09d92015 5922
c19d1205 5923 [Rn]{!} shorthand for [Rn,#0]{!}
e2b0ab59
AV		 5924 =immediate .isreg=0 .relocs[0].exp=immediate
5925 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
09d92015 5926
c19d1205 5927 It is the caller's responsibility to check for addressing modes not
e2b0ab59 5928 supported by the instruction, and to set inst.relocs[0].type. */
c19d1205 5929
4962c51a
MS		 5930static parse_operand_result
5931parse_address_main (char **str, int i, int group_relocations,
477330fc 5932 group_reloc_type group_type)
09d92015 5933{
c19d1205
ZW		 5934 char *p = *str;
5935 int reg;
09d92015 5936
c19d1205 5937 if (skip_past_char (&p, '[') == FAIL)
09d92015 5938 {
c19d1205
ZW		 5939 if (skip_past_char (&p, '=') == FAIL)
5940 {
974da60d 5941 /* Bare address - translate to PC-relative offset. */
e2b0ab59 5942 inst.relocs[0].pc_rel = 1;
c19d1205
ZW		 5943 inst.operands[i].reg = REG_PC;
5944 inst.operands[i].isreg = 1;
5945 inst.operands[i].preind = 1;
09d92015 5946
e2b0ab59 5947 if (my_get_expression (&inst.relocs[0].exp, &p, GE_OPT_PREFIX_BIG))
8335d6aa
JW		 5948 return PARSE_OPERAND_FAIL;
5949 }
e2b0ab59 5950 else if (parse_big_immediate (&p, i, &inst.relocs[0].exp,
8335d6aa 5951 /*allow_symbol_p=*/TRUE))
4962c51a 5952 return PARSE_OPERAND_FAIL;
09d92015 5953
c19d1205 5954 *str = p;
4962c51a 5955 return PARSE_OPERAND_SUCCESS;
09d92015
MM		 5956 }
5957
8ab8155f
NC		 5958 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5959 skip_whitespace (p);
5960
f5f10c66
AV		 5961 if (group_type == GROUP_MVE)
5962 {
5963 enum arm_reg_type rtype = REG_TYPE_MQ;
5964 struct neon_type_el et;
5965 if ((reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
5966 {
5967 inst.operands[i].isquad = 1;
5968 }
5969 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5970 {
5971 inst.error = BAD_ADDR_MODE;
5972 return PARSE_OPERAND_FAIL;
5973 }
5974 }
5975 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
09d92015 5976 {
35c228db
AV		 5977 if (group_type == GROUP_MVE)
5978 inst.error = BAD_ADDR_MODE;
5979 else
5980 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
4962c51a 5981 return PARSE_OPERAND_FAIL;
09d92015 5982 }
c19d1205
ZW		 5983 inst.operands[i].reg = reg;
5984 inst.operands[i].isreg = 1;
09d92015 5985
c19d1205 5986 if (skip_past_comma (&p) == SUCCESS)
09d92015 5987 {
c19d1205 5988 inst.operands[i].preind = 1;
09d92015 5989
c19d1205
ZW		 5990 if (*p == '+') p++;
5991 else if (*p == '-') p++, inst.operands[i].negative = 1;
5992
f5f10c66
AV		 5993 enum arm_reg_type rtype = REG_TYPE_MQ;
5994 struct neon_type_el et;
5995 if (group_type == GROUP_MVE
5996 && (reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
5997 {
5998 inst.operands[i].immisreg = 2;
5999 inst.operands[i].imm = reg;
6000
6001 if (skip_past_comma (&p) == SUCCESS)
6002 {
6003 if (parse_shift (&p, i, SHIFT_UXTW_IMMEDIATE) == SUCCESS)
6004 {
6005 inst.operands[i].imm |= inst.relocs[0].exp.X_add_number << 5;
6006 inst.relocs[0].exp.X_add_number = 0;
6007 }
6008 else
6009 return PARSE_OPERAND_FAIL;
6010 }
6011 }
6012 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
09d92015 6013 {
c19d1205
ZW		 6014 inst.operands[i].imm = reg;
6015 inst.operands[i].immisreg = 1;
6016
6017 if (skip_past_comma (&p) == SUCCESS)
6018 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4962c51a 6019 return PARSE_OPERAND_FAIL;
c19d1205 6020 }
5287ad62 6021 else if (skip_past_char (&p, ':') == SUCCESS)
8e560766
MGD		 6022 {
6023 /* FIXME: '@' should be used here, but it's filtered out by generic
6024 code before we get to see it here. This may be subject to
6025 change. */
6026 parse_operand_result result = parse_neon_alignment (&p, i);
fa94de6b 6027
8e560766
MGD		 6028 if (result != PARSE_OPERAND_SUCCESS)
6029 return result;
6030 }
c19d1205
ZW		 6031 else
6032 {
6033 if (inst.operands[i].negative)
6034 {
6035 inst.operands[i].negative = 0;
6036 p--;
6037 }
4962c51a 6038
5f4273c7
NC		 6039 if (group_relocations
6040 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
4962c51a
MS		 6041 {
6042 struct group_reloc_table_entry *entry;
6043
477330fc
RM		 6044 /* Skip over the #: or : sequence. */
6045 if (*p == '#')
6046 p += 2;
6047 else
6048 p++;
4962c51a
MS		 6049
6050 /* Try to parse a group relocation. Anything else is an
477330fc 6051 error. */
4962c51a
MS		 6052 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
6053 {
6054 inst.error = _("unknown group relocation");
6055 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
6056 }
6057
6058 /* We now have the group relocation table entry corresponding to
6059 the name in the assembler source. Next, we parse the
477330fc 6060 expression. */
e2b0ab59 6061 if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX))
4962c51a
MS		 6062 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
6063
6064 /* Record the relocation type. */
477330fc
RM		 6065 switch (group_type)
6066 {
6067 case GROUP_LDR:
e2b0ab59
AV		 6068 inst.relocs[0].type
6069 = (bfd_reloc_code_real_type) entry->ldr_code;
477330fc 6070 break;
4962c51a 6071
477330fc 6072 case GROUP_LDRS:
e2b0ab59
AV		 6073 inst.relocs[0].type
6074 = (bfd_reloc_code_real_type) entry->ldrs_code;
477330fc 6075 break;
4962c51a 6076
477330fc 6077 case GROUP_LDC:
e2b0ab59
AV		 6078 inst.relocs[0].type
6079 = (bfd_reloc_code_real_type) entry->ldc_code;
477330fc 6080 break;
4962c51a 6081
477330fc
RM		 6082 default:
6083 gas_assert (0);
6084 }
4962c51a 6085
e2b0ab59 6086 if (inst.relocs[0].type == 0)
4962c51a
MS		 6087 {
6088 inst.error = _("this group relocation is not allowed on this instruction");
6089 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
6090 }
477330fc
RM		 6091 }
6092 else
26d97720
NS		 6093 {
6094 char *q = p;
0198d5e6 6095
e2b0ab59 6096 if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
26d97720
NS		 6097 return PARSE_OPERAND_FAIL;
6098 /* If the offset is 0, find out if it's a +0 or -0. */
e2b0ab59
AV		 6099 if (inst.relocs[0].exp.X_op == O_constant
6100 && inst.relocs[0].exp.X_add_number == 0)
26d97720
NS		 6101 {
6102 skip_whitespace (q);
6103 if (*q == '#')
6104 {
6105 q++;
6106 skip_whitespace (q);
6107 }
6108 if (*q == '-')
6109 inst.operands[i].negative = 1;
6110 }
6111 }
09d92015
MM		 6112 }
6113 }
8e560766
MGD		 6114 else if (skip_past_char (&p, ':') == SUCCESS)
6115 {
6116 /* FIXME: '@' should be used here, but it's filtered out by generic code
6117 before we get to see it here. This may be subject to change. */
6118 parse_operand_result result = parse_neon_alignment (&p, i);
fa94de6b 6119
8e560766
MGD		 6120 if (result != PARSE_OPERAND_SUCCESS)
6121 return result;
6122 }
09d92015 6123
c19d1205 6124 if (skip_past_char (&p, ']') == FAIL)
09d92015 6125 {
c19d1205 6126 inst.error = _("']' expected");
4962c51a 6127 return PARSE_OPERAND_FAIL;
09d92015
MM		 6128 }
6129
c19d1205
ZW		 6130 if (skip_past_char (&p, '!') == SUCCESS)
6131 inst.operands[i].writeback = 1;
09d92015 6132
c19d1205 6133 else if (skip_past_comma (&p) == SUCCESS)
09d92015 6134 {
c19d1205
ZW		 6135 if (skip_past_char (&p, '{') == SUCCESS)
6136 {
6137 /* [Rn], {expr} - unindexed, with option */
6138 if (parse_immediate (&p, &inst.operands[i].imm,
ca3f61f7 6139 0, 255, TRUE) == FAIL)
4962c51a 6140 return PARSE_OPERAND_FAIL;
09d92015 6141
c19d1205
ZW		 6142 if (skip_past_char (&p, '}') == FAIL)
6143 {
6144 inst.error = _("'}' expected at end of 'option' field");
4962c51a 6145 return PARSE_OPERAND_FAIL;
c19d1205
ZW		 6146 }
6147 if (inst.operands[i].preind)
6148 {
6149 inst.error = _("cannot combine index with option");
4962c51a 6150 return PARSE_OPERAND_FAIL;
c19d1205
ZW		 6151 }
6152 *str = p;
4962c51a 6153 return PARSE_OPERAND_SUCCESS;
09d92015 6154 }
c19d1205
ZW		 6155 else
6156 {
6157 inst.operands[i].postind = 1;
6158 inst.operands[i].writeback = 1;
09d92015 6159
c19d1205
ZW		 6160 if (inst.operands[i].preind)
6161 {
6162 inst.error = _("cannot combine pre- and post-indexing");
4962c51a 6163 return PARSE_OPERAND_FAIL;
c19d1205 6164 }
09d92015 6165
c19d1205
ZW		 6166 if (*p == '+') p++;
6167 else if (*p == '-') p++, inst.operands[i].negative = 1;
a737bd4d 6168
f5f10c66
AV		 6169 enum arm_reg_type rtype = REG_TYPE_MQ;
6170 struct neon_type_el et;
6171 if (group_type == GROUP_MVE
6172 && (reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
6173 {
6174 inst.operands[i].immisreg = 2;
6175 inst.operands[i].imm = reg;
6176 }
6177 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
c19d1205 6178 {
477330fc
RM		 6179 /* We might be using the immediate for alignment already. If we
6180 are, OR the register number into the low-order bits. */
6181 if (inst.operands[i].immisalign)
6182 inst.operands[i].imm |= reg;
6183 else
6184 inst.operands[i].imm = reg;
c19d1205 6185 inst.operands[i].immisreg = 1;
a737bd4d 6186
c19d1205
ZW		 6187 if (skip_past_comma (&p) == SUCCESS)
6188 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4962c51a 6189 return PARSE_OPERAND_FAIL;
c19d1205
ZW		 6190 }
6191 else
6192 {
26d97720 6193 char *q = p;
0198d5e6 6194
c19d1205
ZW		 6195 if (inst.operands[i].negative)
6196 {
6197 inst.operands[i].negative = 0;
6198 p--;
6199 }
e2b0ab59 6200 if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
4962c51a 6201 return PARSE_OPERAND_FAIL;
26d97720 6202 /* If the offset is 0, find out if it's a +0 or -0. */
e2b0ab59
AV		 6203 if (inst.relocs[0].exp.X_op == O_constant
6204 && inst.relocs[0].exp.X_add_number == 0)
26d97720
NS		 6205 {
6206 skip_whitespace (q);
6207 if (*q == '#')
6208 {
6209 q++;
6210 skip_whitespace (q);
6211 }
6212 if (*q == '-')
6213 inst.operands[i].negative = 1;
6214 }
c19d1205
ZW		 6215 }
6216 }
a737bd4d
NC		 6217 }
6218
c19d1205
ZW		 6219 /* If at this point neither .preind nor .postind is set, we have a
6220 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6221 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
6222 {
6223 inst.operands[i].preind = 1;
e2b0ab59
AV		 6224 inst.relocs[0].exp.X_op = O_constant;
6225 inst.relocs[0].exp.X_add_number = 0;
c19d1205
ZW		 6226 }
6227 *str = p;
4962c51a
MS		 6228 return PARSE_OPERAND_SUCCESS;
6229}
6230
6231static int
6232parse_address (char **str, int i)
6233{
21d799b5 6234 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
477330fc 6235 ? SUCCESS : FAIL;
4962c51a
MS		 6236}
6237
6238static parse_operand_result
6239parse_address_group_reloc (char **str, int i, group_reloc_type type)
6240{
6241 return parse_address_main (str, i, 1, type);
a737bd4d
NC		 6242}
6243
b6895b4f
PB		 6244/* Parse an operand for a MOVW or MOVT instruction. */
6245static int
6246parse_half (char **str)
6247{
6248 char * p;
5f4273c7 6249
b6895b4f
PB		 6250 p = *str;
6251 skip_past_char (&p, '#');
5f4273c7 6252 if (strncasecmp (p, ":lower16:", 9) == 0)
e2b0ab59 6253 inst.relocs[0].type = BFD_RELOC_ARM_MOVW;
b6895b4f 6254 else if (strncasecmp (p, ":upper16:", 9) == 0)
e2b0ab59 6255 inst.relocs[0].type = BFD_RELOC_ARM_MOVT;
b6895b4f 6256
e2b0ab59 6257 if (inst.relocs[0].type != BFD_RELOC_UNUSED)
b6895b4f
PB		 6258 {
6259 p += 9;
5f4273c7 6260 skip_whitespace (p);
b6895b4f
PB		 6261 }
6262
e2b0ab59 6263 if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX))
b6895b4f
PB		 6264 return FAIL;
6265
e2b0ab59 6266 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
b6895b4f 6267 {
e2b0ab59 6268 if (inst.relocs[0].exp.X_op != O_constant)
b6895b4f
PB		 6269 {
6270 inst.error = _("constant expression expected");
6271 return FAIL;
6272 }
e2b0ab59
AV		 6273 if (inst.relocs[0].exp.X_add_number < 0
6274 || inst.relocs[0].exp.X_add_number > 0xffff)
b6895b4f
PB		 6275 {
6276 inst.error = _("immediate value out of range");
6277 return FAIL;
6278 }
6279 }
6280 *str = p;
6281 return SUCCESS;
6282}
6283
c19d1205 6284/* Miscellaneous. */
a737bd4d 6285
c19d1205
ZW		 6286/* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6287 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6288static int
d2cd1205 6289parse_psr (char **str, bfd_boolean lhs)
09d92015 6290{
c19d1205
ZW		 6291 char *p;
6292 unsigned long psr_field;
62b3e311
PB		 6293 const struct asm_psr *psr;
6294 char *start;
d2cd1205 6295 bfd_boolean is_apsr = FALSE;
ac7f631b 6296 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
09d92015 6297
a4482bb6
NC		 6298 /* PR gas/12698: If the user has specified -march=all then m_profile will
6299 be TRUE, but we want to ignore it in this case as we are building for any
6300 CPU type, including non-m variants. */
823d2571 6301 if (ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any))
a4482bb6
NC		 6302 m_profile = FALSE;
6303
c19d1205
ZW		 6304 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6305 feature for ease of use and backwards compatibility. */
6306 p = *str;
62b3e311 6307 if (strncasecmp (p, "SPSR", 4) == 0)
d2cd1205
JB		 6308 {
6309 if (m_profile)
6310 goto unsupported_psr;
fa94de6b 6311
d2cd1205
JB		 6312 psr_field = SPSR_BIT;
6313 }
6314 else if (strncasecmp (p, "CPSR", 4) == 0)
6315 {
6316 if (m_profile)
6317 goto unsupported_psr;
6318
6319 psr_field = 0;
6320 }
6321 else if (strncasecmp (p, "APSR", 4) == 0)
6322 {
6323 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6324 and ARMv7-R architecture CPUs. */
6325 is_apsr = TRUE;
6326 psr_field = 0;
6327 }
6328 else if (m_profile)
62b3e311
PB		 6329 {
6330 start = p;
6331 do
6332 p++;
6333 while (ISALNUM (*p) || *p == '_');
6334
d2cd1205
JB		 6335 if (strncasecmp (start, "iapsr", 5) == 0
6336 || strncasecmp (start, "eapsr", 5) == 0
6337 || strncasecmp (start, "xpsr", 4) == 0
6338 || strncasecmp (start, "psr", 3) == 0)
6339 p = start + strcspn (start, "rR") + 1;
6340
21d799b5 6341 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
477330fc 6342 p - start);
d2cd1205 6343
62b3e311
PB		 6344 if (!psr)
6345 return FAIL;
09d92015 6346
d2cd1205
JB		 6347 /* If APSR is being written, a bitfield may be specified. Note that
6348 APSR itself is handled above. */
6349 if (psr->field <= 3)
6350 {
6351 psr_field = psr->field;
6352 is_apsr = TRUE;
6353 goto check_suffix;
6354 }
6355
62b3e311 6356 *str = p;
d2cd1205
JB		 6357 /* M-profile MSR instructions have the mask field set to "10", except
6358 *PSR variants which modify APSR, which may use a different mask (and
6359 have been handled already). Do that by setting the PSR_f field
6360 here. */
6361 return psr->field | (lhs ? PSR_f : 0);
62b3e311 6362 }
d2cd1205
JB		 6363 else
6364 goto unsupported_psr;
09d92015 6365
62b3e311 6366 p += 4;
dc1e8a47 6367 check_suffix:
c19d1205
ZW		 6368 if (*p == '_')
6369 {
6370 /* A suffix follows. */
c19d1205
ZW		 6371 p++;
6372 start = p;
a737bd4d 6373
c19d1205
ZW		 6374 do
6375 p++;
6376 while (ISALNUM (*p) || *p == '_');
a737bd4d 6377
d2cd1205
JB		 6378 if (is_apsr)
6379 {
6380 /* APSR uses a notation for bits, rather than fields. */
6381 unsigned int nzcvq_bits = 0;
6382 unsigned int g_bit = 0;
6383 char *bit;
fa94de6b 6384
d2cd1205
JB		 6385 for (bit = start; bit != p; bit++)
6386 {
6387 switch (TOLOWER (*bit))
477330fc 6388 {
d2cd1205
JB		 6389 case 'n':
6390 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
6391 break;
6392
6393 case 'z':
6394 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
6395 break;
6396
6397 case 'c':
6398 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
6399 break;
6400
6401 case 'v':
6402 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
6403 break;
fa94de6b 6404
d2cd1205
JB		 6405 case 'q':
6406 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
6407 break;
fa94de6b 6408
d2cd1205
JB		 6409 case 'g':
6410 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
6411 break;
fa94de6b 6412
d2cd1205
JB		 6413 default:
6414 inst.error = _("unexpected bit specified after APSR");
6415 return FAIL;
6416 }
6417 }
fa94de6b 6418
d2cd1205
JB		 6419 if (nzcvq_bits == 0x1f)
6420 psr_field |= PSR_f;
fa94de6b 6421
d2cd1205
JB		 6422 if (g_bit == 0x1)
6423 {
6424 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
477330fc 6425 {
d2cd1205
JB		 6426 inst.error = _("selected processor does not "
6427 "support DSP extension");
6428 return FAIL;
6429 }
6430
6431 psr_field |= PSR_s;
6432 }
fa94de6b 6433
d2cd1205
JB		 6434 if ((nzcvq_bits & 0x20) != 0
6435 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
6436 || (g_bit & 0x2) != 0)
6437 {
6438 inst.error = _("bad bitmask specified after APSR");
6439 return FAIL;
6440 }
6441 }
6442 else
477330fc 6443 {
d2cd1205 6444 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
477330fc 6445 p - start);
d2cd1205 6446 if (!psr)
477330fc 6447 goto error;
a737bd4d 6448
d2cd1205
JB		 6449 psr_field |= psr->field;
6450 }
a737bd4d 6451 }
c19d1205 6452 else
a737bd4d 6453 {
c19d1205
ZW		 6454 if (ISALNUM (*p))
6455 goto error; /* Garbage after "[CS]PSR". */
6456
d2cd1205 6457 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
477330fc 6458 is deprecated, but allow it anyway. */
d2cd1205
JB		 6459 if (is_apsr && lhs)
6460 {
6461 psr_field |= PSR_f;
6462 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6463 "deprecated"));
6464 }
6465 else if (!m_profile)
6466 /* These bits are never right for M-profile devices: don't set them
6467 (only code paths which read/write APSR reach here). */
6468 psr_field |= (PSR_c | PSR_f);
a737bd4d 6469 }
c19d1205
ZW		 6470 *str = p;
6471 return psr_field;
a737bd4d 6472
d2cd1205
JB		 6473 unsupported_psr:
6474 inst.error = _("selected processor does not support requested special "
6475 "purpose register");
6476 return FAIL;
6477
c19d1205
ZW		 6478 error:
6479 inst.error = _("flag for {c}psr instruction expected");
6480 return FAIL;
a737bd4d
NC		 6481}
6482
32c36c3c
AV		 6483static int
6484parse_sys_vldr_vstr (char **str)
6485{
6486 unsigned i;
6487 int val = FAIL;
6488 struct {
6489 const char *name;
6490 int regl;
6491 int regh;
6492 } sysregs[] = {
6493 {"FPSCR", 0x1, 0x0},
6494 {"FPSCR_nzcvqc", 0x2, 0x0},
6495 {"VPR", 0x4, 0x1},
6496 {"P0", 0x5, 0x1},
6497 {"FPCXTNS", 0x6, 0x1},
6498 {"FPCXTS", 0x7, 0x1}
6499 };
6500 char *op_end = strchr (*str, ',');
6501 size_t op_strlen = op_end - *str;
6502
6503 for (i = 0; i < sizeof (sysregs) / sizeof (sysregs[0]); i++)
6504 {
6505 if (!strncmp (*str, sysregs[i].name, op_strlen))
6506 {
6507 val = sysregs[i].regl | (sysregs[i].regh << 3);
6508 *str = op_end;
6509 break;
6510 }
6511 }
6512
6513 return val;
6514}
6515
c19d1205
ZW		 6516/* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6517 value suitable for splatting into the AIF field of the instruction. */
a737bd4d 6518
c19d1205
ZW		 6519static int
6520parse_cps_flags (char **str)
a737bd4d 6521{
c19d1205
ZW		 6522 int val = 0;
6523 int saw_a_flag = 0;
6524 char *s = *str;
a737bd4d 6525
c19d1205
ZW		 6526 for (;;)
6527 switch (*s++)
6528 {
6529 case '\0': case ',':
6530 goto done;
a737bd4d 6531
c19d1205
ZW		 6532 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
6533 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
6534 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
a737bd4d 6535
c19d1205
ZW		 6536 default:
6537 inst.error = _("unrecognized CPS flag");
6538 return FAIL;
6539 }
a737bd4d 6540
c19d1205
ZW		 6541 done:
6542 if (saw_a_flag == 0)
a737bd4d 6543 {
c19d1205
ZW		 6544 inst.error = _("missing CPS flags");
6545 return FAIL;
a737bd4d 6546 }
a737bd4d 6547
c19d1205
ZW		 6548 *str = s - 1;
6549 return val;
a737bd4d
NC		 6550}
6551
c19d1205
ZW		 6552/* Parse an endian specifier ("BE" or "LE", case insensitive);
6553 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
a737bd4d
NC		 6554
6555static int
c19d1205 6556parse_endian_specifier (char **str)
a737bd4d 6557{
c19d1205
ZW		 6558 int little_endian;
6559 char *s = *str;
a737bd4d 6560
c19d1205
ZW		 6561 if (strncasecmp (s, "BE", 2))
6562 little_endian = 0;
6563 else if (strncasecmp (s, "LE", 2))
6564 little_endian = 1;
6565 else
a737bd4d 6566 {
c19d1205 6567 inst.error = _("valid endian specifiers are be or le");
a737bd4d
NC		 6568 return FAIL;
6569 }
6570
c19d1205 6571 if (ISALNUM (s[2]) || s[2] == '_')
a737bd4d 6572 {
c19d1205 6573 inst.error = _("valid endian specifiers are be or le");
a737bd4d
NC		 6574 return FAIL;
6575 }
6576
c19d1205
ZW		 6577 *str = s + 2;
6578 return little_endian;
6579}
a737bd4d 6580
c19d1205
ZW		 6581/* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6582 value suitable for poking into the rotate field of an sxt or sxta
6583 instruction, or FAIL on error. */
6584
6585static int
6586parse_ror (char **str)
6587{
6588 int rot;
6589 char *s = *str;
6590
6591 if (strncasecmp (s, "ROR", 3) == 0)
6592 s += 3;
6593 else
a737bd4d 6594 {
c19d1205 6595 inst.error = _("missing rotation field after comma");
a737bd4d
NC		 6596 return FAIL;
6597 }
c19d1205
ZW		 6598
6599 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
6600 return FAIL;
6601
6602 switch (rot)
a737bd4d 6603 {
c19d1205
ZW		 6604 case 0: *str = s; return 0x0;
6605 case 8: *str = s; return 0x1;
6606 case 16: *str = s; return 0x2;
6607 case 24: *str = s; return 0x3;
6608
6609 default:
6610 inst.error = _("rotation can only be 0, 8, 16, or 24");
a737bd4d
NC		 6611 return FAIL;
6612 }
c19d1205 6613}
a737bd4d 6614
c19d1205
ZW		 6615/* Parse a conditional code (from conds[] below). The value returned is in the
6616 range 0 .. 14, or FAIL. */
6617static int
6618parse_cond (char **str)
6619{
c462b453 6620 char *q;
c19d1205 6621 const struct asm_cond *c;
c462b453
PB		 6622 int n;
6623 /* Condition codes are always 2 characters, so matching up to
6624 3 characters is sufficient. */
6625 char cond[3];
a737bd4d 6626
c462b453
PB		 6627 q = *str;
6628 n = 0;
6629 while (ISALPHA (*q) && n < 3)
6630 {
e07e6e58 6631 cond[n] = TOLOWER (*q);
c462b453
PB		 6632 q++;
6633 n++;
6634 }
a737bd4d 6635
21d799b5 6636 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
c19d1205 6637 if (!c)
a737bd4d 6638 {
c19d1205 6639 inst.error = _("condition required");
a737bd4d
NC		 6640 return FAIL;
6641 }
6642
c19d1205
ZW		 6643 *str = q;
6644 return c->value;
6645}
6646
62b3e311
PB		 6647/* Parse an option for a barrier instruction. Returns the encoding for the
6648 option, or FAIL. */
6649static int
6650parse_barrier (char **str)
6651{
6652 char *p, *q;
6653 const struct asm_barrier_opt *o;
6654
6655 p = q = *str;
6656 while (ISALPHA (*q))
6657 q++;
6658
21d799b5 6659 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
477330fc 6660 q - p);
62b3e311
PB		 6661 if (!o)
6662 return FAIL;
6663
e797f7e0
MGD		 6664 if (!mark_feature_used (&o->arch))
6665 return FAIL;
6666
62b3e311
PB		 6667 *str = q;
6668 return o->value;
6669}
6670
92e90b6e
PB		 6671/* Parse the operands of a table branch instruction. Similar to a memory
6672 operand. */
6673static int
6674parse_tb (char **str)
6675{
6676 char * p = *str;
6677 int reg;
6678
6679 if (skip_past_char (&p, '[') == FAIL)
ab1eb5fe
PB		 6680 {
6681 inst.error = _("'[' expected");
6682 return FAIL;
6683 }
92e90b6e 6684
dcbf9037 6685 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
92e90b6e
PB		 6686 {
6687 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6688 return FAIL;
6689 }
6690 inst.operands[0].reg = reg;
6691
6692 if (skip_past_comma (&p) == FAIL)
ab1eb5fe
PB		 6693 {
6694 inst.error = _("',' expected");
6695 return FAIL;
6696 }
5f4273c7 6697
dcbf9037 6698 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
92e90b6e
PB		 6699 {
6700 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6701 return FAIL;
6702 }
6703 inst.operands[0].imm = reg;
6704
6705 if (skip_past_comma (&p) == SUCCESS)
6706 {
6707 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
6708 return FAIL;
e2b0ab59 6709 if (inst.relocs[0].exp.X_add_number != 1)
92e90b6e
PB		 6710 {
6711 inst.error = _("invalid shift");
6712 return FAIL;
6713 }
6714 inst.operands[0].shifted = 1;
6715 }
6716
6717 if (skip_past_char (&p, ']') == FAIL)
6718 {
6719 inst.error = _("']' expected");
6720 return FAIL;
6721 }
6722 *str = p;
6723 return SUCCESS;
6724}
6725
5287ad62
JB		 6726/* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6727 information on the types the operands can take and how they are encoded.
037e8744
JB		 6728 Up to four operands may be read; this function handles setting the
6729 ".present" field for each read operand itself.
5287ad62
JB		 6730 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6731 else returns FAIL. */
6732
6733static int
6734parse_neon_mov (char **str, int *which_operand)
6735{
6736 int i = *which_operand, val;
6737 enum arm_reg_type rtype;
6738 char *ptr = *str;
dcbf9037 6739 struct neon_type_el optype;
5f4273c7 6740
57785aa2
AV		 6741 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6742 {
6743 /* Cases 17 or 19. */
6744 inst.operands[i].reg = val;
6745 inst.operands[i].isvec = 1;
6746 inst.operands[i].isscalar = 2;
6747 inst.operands[i].vectype = optype;
6748 inst.operands[i++].present = 1;
6749
6750 if (skip_past_comma (&ptr) == FAIL)
6751 goto wanted_comma;
6752
6753 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6754 {
6755 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6756 inst.operands[i].reg = val;
6757 inst.operands[i].isreg = 1;
6758 inst.operands[i].present = 1;
6759 }
6760 else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6761 {
6762 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6763 inst.operands[i].reg = val;
6764 inst.operands[i].isvec = 1;
6765 inst.operands[i].isscalar = 2;
6766 inst.operands[i].vectype = optype;
6767 inst.operands[i++].present = 1;
6768
6769 if (skip_past_comma (&ptr) == FAIL)
6770 goto wanted_comma;
6771
6772 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6773 goto wanted_arm;
6774
6775 inst.operands[i].reg = val;
6776 inst.operands[i].isreg = 1;
6777 inst.operands[i++].present = 1;
6778
6779 if (skip_past_comma (&ptr) == FAIL)
6780 goto wanted_comma;
6781
6782 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6783 goto wanted_arm;
6784
6785 inst.operands[i].reg = val;
6786 inst.operands[i].isreg = 1;
6787 inst.operands[i].present = 1;
6788 }
6789 else
6790 {
6791 first_error (_("expected ARM or MVE vector register"));
6792 return FAIL;
6793 }
6794 }
6795 else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_VFD)) != FAIL)
5287ad62
JB		 6796 {
6797 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6798 inst.operands[i].reg = val;
6799 inst.operands[i].isscalar = 1;
dcbf9037 6800 inst.operands[i].vectype = optype;
5287ad62
JB		 6801 inst.operands[i++].present = 1;
6802
6803 if (skip_past_comma (&ptr) == FAIL)
477330fc 6804 goto wanted_comma;
5f4273c7 6805
dcbf9037 6806 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
477330fc 6807 goto wanted_arm;
5f4273c7 6808
5287ad62
JB		 6809 inst.operands[i].reg = val;
6810 inst.operands[i].isreg = 1;
6811 inst.operands[i].present = 1;
6812 }
57785aa2
AV		 6813 else if (((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
6814 != FAIL)
6815 || ((val = arm_typed_reg_parse (&ptr, REG_TYPE_MQ, &rtype, &optype))
6816 != FAIL))
5287ad62
JB		 6817 {
6818 /* Cases 0, 1, 2, 3, 5 (D only). */
6819 if (skip_past_comma (&ptr) == FAIL)
477330fc 6820 goto wanted_comma;
5f4273c7 6821
5287ad62
JB		 6822 inst.operands[i].reg = val;
6823 inst.operands[i].isreg = 1;
6824 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
037e8744
JB		 6825 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6826 inst.operands[i].isvec = 1;
dcbf9037 6827 inst.operands[i].vectype = optype;
5287ad62
JB		 6828 inst.operands[i++].present = 1;
6829
dcbf9037 6830 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
477330fc
RM		 6831 {
6832 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6833 Case 13: VMOV <Sd>, <Rm> */
6834 inst.operands[i].reg = val;
6835 inst.operands[i].isreg = 1;
6836 inst.operands[i].present = 1;
6837
6838 if (rtype == REG_TYPE_NQ)
6839 {
6840 first_error (_("can't use Neon quad register here"));
6841 return FAIL;
6842 }
6843 else if (rtype != REG_TYPE_VFS)
6844 {
6845 i++;
6846 if (skip_past_comma (&ptr) == FAIL)
6847 goto wanted_comma;
6848 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6849 goto wanted_arm;
6850 inst.operands[i].reg = val;
6851 inst.operands[i].isreg = 1;
6852 inst.operands[i].present = 1;
6853 }
6854 }
c4a23bf8
SP		 6855 else if (((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
6856 &optype)) != FAIL)
6857 || ((val = arm_typed_reg_parse (&ptr, REG_TYPE_MQ, &rtype,
6858 &optype)) != FAIL))
477330fc
RM		 6859 {
6860 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6861 Case 1: VMOV<c><q> <Dd>, <Dm>
6862 Case 8: VMOV.F32 <Sd>, <Sm>
6863 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6864
6865 inst.operands[i].reg = val;
6866 inst.operands[i].isreg = 1;
6867 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6868 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6869 inst.operands[i].isvec = 1;
6870 inst.operands[i].vectype = optype;
6871 inst.operands[i].present = 1;
6872
6873 if (skip_past_comma (&ptr) == SUCCESS)
6874 {
6875 /* Case 15. */
6876 i++;
6877
6878 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6879 goto wanted_arm;
6880
6881 inst.operands[i].reg = val;
6882 inst.operands[i].isreg = 1;
6883 inst.operands[i++].present = 1;
6884
6885 if (skip_past_comma (&ptr) == FAIL)
6886 goto wanted_comma;
6887
6888 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6889 goto wanted_arm;
6890
6891 inst.operands[i].reg = val;
6892 inst.operands[i].isreg = 1;
6893 inst.operands[i].present = 1;
6894 }
6895 }
4641781c 6896 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
477330fc
RM		 6897 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6898 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6899 Case 10: VMOV.F32 <Sd>, #<imm>
6900 Case 11: VMOV.F64 <Dd>, #<imm> */
6901 inst.operands[i].immisfloat = 1;
8335d6aa
JW		 6902 else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/FALSE)
6903 == SUCCESS)
477330fc
RM		 6904 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6905 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6906 ;
5287ad62 6907 else
477330fc
RM		 6908 {
6909 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6910 return FAIL;
6911 }
5287ad62 6912 }
dcbf9037 6913 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5287ad62 6914 {
57785aa2 6915 /* Cases 6, 7, 16, 18. */
5287ad62
JB		 6916 inst.operands[i].reg = val;
6917 inst.operands[i].isreg = 1;
6918 inst.operands[i++].present = 1;
5f4273c7 6919
5287ad62 6920 if (skip_past_comma (&ptr) == FAIL)
477330fc 6921 goto wanted_comma;
5f4273c7 6922
57785aa2
AV		 6923 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6924 {
6925 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6926 inst.operands[i].reg = val;
6927 inst.operands[i].isscalar = 2;
6928 inst.operands[i].present = 1;
6929 inst.operands[i].vectype = optype;
6930 }
6931 else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_VFD)) != FAIL)
477330fc
RM		 6932 {
6933 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6934 inst.operands[i].reg = val;
6935 inst.operands[i].isscalar = 1;
6936 inst.operands[i].present = 1;
6937 inst.operands[i].vectype = optype;
6938 }
dcbf9037 6939 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
477330fc 6940 {
477330fc
RM		 6941 inst.operands[i].reg = val;
6942 inst.operands[i].isreg = 1;
6943 inst.operands[i++].present = 1;
6944
6945 if (skip_past_comma (&ptr) == FAIL)
6946 goto wanted_comma;
6947
6948 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
57785aa2 6949 != FAIL)
477330fc 6950 {
57785aa2 6951 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
477330fc 6952
477330fc
RM		 6953 inst.operands[i].reg = val;
6954 inst.operands[i].isreg = 1;
6955 inst.operands[i].isvec = 1;
57785aa2 6956 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
477330fc
RM		 6957 inst.operands[i].vectype = optype;
6958 inst.operands[i].present = 1;
57785aa2
AV		 6959
6960 if (rtype == REG_TYPE_VFS)
6961 {
6962 /* Case 14. */
6963 i++;
6964 if (skip_past_comma (&ptr) == FAIL)
6965 goto wanted_comma;
6966 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6967 &optype)) == FAIL)
6968 {
6969 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6970 return FAIL;
6971 }
6972 inst.operands[i].reg = val;
6973 inst.operands[i].isreg = 1;
6974 inst.operands[i].isvec = 1;
6975 inst.operands[i].issingle = 1;
6976 inst.operands[i].vectype = optype;
6977 inst.operands[i].present = 1;
6978 }
6979 }
6980 else
6981 {
6982 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ))
6983 != FAIL)
6984 {
6985 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6986 inst.operands[i].reg = val;
6987 inst.operands[i].isvec = 1;
6988 inst.operands[i].isscalar = 2;
6989 inst.operands[i].vectype = optype;
6990 inst.operands[i++].present = 1;
6991
6992 if (skip_past_comma (&ptr) == FAIL)
6993 goto wanted_comma;
6994
6995 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ))
6996 == FAIL)
6997 {
6998 first_error (_(reg_expected_msgs[REG_TYPE_MQ]));
6999 return FAIL;
7000 }
7001 inst.operands[i].reg = val;
7002 inst.operands[i].isvec = 1;
7003 inst.operands[i].isscalar = 2;
7004 inst.operands[i].vectype = optype;
7005 inst.operands[i].present = 1;
7006 }
7007 else
7008 {
7009 first_error (_("VFP single, double or MVE vector register"
7010 " expected"));
7011 return FAIL;
7012 }
477330fc
RM		 7013 }
7014 }
037e8744 7015 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
477330fc
RM		 7016 != FAIL)
7017 {
7018 /* Case 13. */
7019 inst.operands[i].reg = val;
7020 inst.operands[i].isreg = 1;
7021 inst.operands[i].isvec = 1;
7022 inst.operands[i].issingle = 1;
7023 inst.operands[i].vectype = optype;
7024 inst.operands[i].present = 1;
7025 }
5287ad62
JB		 7026 }
7027 else
7028 {
dcbf9037 7029 first_error (_("parse error"));
5287ad62
JB		 7030 return FAIL;
7031 }
7032
7033 /* Successfully parsed the operands. Update args. */
7034 *which_operand = i;
7035 *str = ptr;
7036 return SUCCESS;
7037
5f4273c7 7038 wanted_comma:
dcbf9037 7039 first_error (_("expected comma"));
5287ad62 7040 return FAIL;
5f4273c7
NC		 7041
7042 wanted_arm:
dcbf9037 7043 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
5287ad62 7044 return FAIL;
5287ad62
JB		 7045}
7046
5be8be5d
DG		 7047/* Use this macro when the operand constraints are different
7048 for ARM and THUMB (e.g. ldrd). */
7049#define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
7050 ((arm_operand) | ((thumb_operand) << 16))
7051
c19d1205
ZW		 7052/* Matcher codes for parse_operands. */
7053enum operand_parse_code
7054{
7055 OP_stop, /* end of line */
7056
7057 OP_RR, /* ARM register */
7058 OP_RRnpc, /* ARM register, not r15 */
5be8be5d 7059 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
c19d1205 7060 OP_RRnpcb, /* ARM register, not r15, in square brackets */
fa94de6b 7061 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
55881a11 7062 optional trailing ! */
c19d1205
ZW		 7063 OP_RRw, /* ARM register, not r15, optional trailing ! */
7064 OP_RCP, /* Coprocessor number */
7065 OP_RCN, /* Coprocessor register */
7066 OP_RF, /* FPA register */
7067 OP_RVS, /* VFP single precision register */
5287ad62
JB		 7068 OP_RVD, /* VFP double precision register (0..15) */
7069 OP_RND, /* Neon double precision register (0..31) */
5ee91343
AV		 7070 OP_RNDMQ, /* Neon double precision (0..31) or MVE vector register. */
7071 OP_RNDMQR, /* Neon double precision (0..31), MVE vector or ARM register.
7072 */
66d1f7cc
AV		 7073 OP_RNSDMQR, /* Neon single or double precision, MVE vector or ARM register.
7074 */
5287ad62 7075 OP_RNQ, /* Neon quad precision register */
5ee91343 7076 OP_RNQMQ, /* Neon quad or MVE vector register. */
037e8744 7077 OP_RVSD, /* VFP single or double precision register */
1b883319 7078 OP_RVSD_COND, /* VFP single, double precision register or condition code. */
dd9634d9 7079 OP_RVSDMQ, /* VFP single, double precision or MVE vector register. */
dec41383 7080 OP_RNSD, /* Neon single or double precision register */
5287ad62 7081 OP_RNDQ, /* Neon double or quad precision register */
5ee91343 7082 OP_RNDQMQ, /* Neon double, quad or MVE vector register. */
7df54120 7083 OP_RNDQMQR, /* Neon double, quad, MVE vector or ARM register. */
037e8744 7084 OP_RNSDQ, /* Neon single, double or quad precision register */
5287ad62 7085 OP_RNSC, /* Neon scalar D[X] */
c19d1205
ZW		 7086 OP_RVC, /* VFP control register */
7087 OP_RMF, /* Maverick F register */
7088 OP_RMD, /* Maverick D register */
7089 OP_RMFX, /* Maverick FX register */
7090 OP_RMDX, /* Maverick DX register */
7091 OP_RMAX, /* Maverick AX register */
7092 OP_RMDS, /* Maverick DSPSC register */
7093 OP_RIWR, /* iWMMXt wR register */
7094 OP_RIWC, /* iWMMXt wC register */
7095 OP_RIWG, /* iWMMXt wCG register */
7096 OP_RXA, /* XScale accumulator register */
7097
5aae9ae9 7098 OP_RNSDMQ, /* Neon single, double or MVE vector register */
5ee91343
AV		 7099 OP_RNSDQMQ, /* Neon single, double or quad register or MVE vector register
7100 */
7101 OP_RNSDQMQR, /* Neon single, double or quad register, MVE vector register or
7102 GPR (no SP/SP) */
a302e574 7103 OP_RMQ, /* MVE vector register. */
1b883319 7104 OP_RMQRZ, /* MVE vector or ARM register including ZR. */
35d1cfc2 7105 OP_RMQRR, /* MVE vector or ARM register. */
a302e574 7106
60f993ce
AV		 7107 /* New operands for Armv8.1-M Mainline. */
7108 OP_LR, /* ARM LR register */
a302e574
AV		 7109 OP_RRe, /* ARM register, only even numbered. */
7110 OP_RRo, /* ARM register, only odd numbered, not r13 or r15. */
60f993ce 7111 OP_RRnpcsp_I32, /* ARM register (no BadReg) or literal 1 .. 32 */
e39c1607 7112 OP_RR_ZR, /* ARM register or ZR but no PC */
60f993ce 7113
c19d1205 7114 OP_REGLST, /* ARM register list */
4b5a202f 7115 OP_CLRMLST, /* CLRM register list */
c19d1205
ZW		 7116 OP_VRSLST, /* VFP single-precision register list */
7117 OP_VRDLST, /* VFP double-precision register list */
037e8744 7118 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
5287ad62
JB		 7119 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
7120 OP_NSTRLST, /* Neon element/structure list */
efd6b359 7121 OP_VRSDVLST, /* VFP single or double-precision register list and VPR */
35c228db
AV		 7122 OP_MSTRLST2, /* MVE vector list with two elements. */
7123 OP_MSTRLST4, /* MVE vector list with four elements. */
5287ad62 7124
5287ad62 7125 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
037e8744 7126 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
aacf0b33 7127 OP_RSVD_FI0, /* VFP S or D reg, or floating point immediate zero. */
1b883319
AV		 7128 OP_RSVDMQ_FI0, /* VFP S, D, MVE vector register or floating point immediate
7129 zero. */
5287ad62 7130 OP_RR_RNSC, /* ARM reg or Neon scalar. */
dec41383 7131 OP_RNSD_RNSC, /* Neon S or D reg, or Neon scalar. */
037e8744 7132 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
886e1c73
AV		 7133 OP_RNSDQ_RNSC_MQ, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
7134 */
a8465a06
AV		 7135 OP_RNSDQ_RNSC_MQ_RR, /* Vector S, D or Q reg, or MVE vector reg , or Neon
7136 scalar, or ARM register. */
5287ad62 7137 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
42b16635
AV		 7138 OP_RNDQ_RNSC_RR, /* Neon D or Q reg, Neon scalar, or ARM register. */
7139 OP_RNDQMQ_RNSC_RR, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
7140 register. */
5d281bf0 7141 OP_RNDQMQ_RNSC, /* Neon D, Q or MVE vector reg, or Neon scalar. */
5287ad62
JB		 7142 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
7143 OP_VMOV, /* Neon VMOV operands. */
4316f0d2 7144 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
f601a00c
AV		 7145 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
7146 OP_RNDQMQ_Ibig,
5287ad62 7147 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
5150f0d8
AV		 7148 OP_RNDQMQ_I63b_RR, /* Neon D or Q reg, immediate for shift, MVE vector or
7149 ARM register. */
2d447fca 7150 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
32c36c3c 7151 OP_VLDR, /* VLDR operand. */
5287ad62
JB		 7152
7153 OP_I0, /* immediate zero */
c19d1205
ZW		 7154 OP_I7, /* immediate value 0 .. 7 */
7155 OP_I15, /* 0 .. 15 */
7156 OP_I16, /* 1 .. 16 */
5287ad62 7157 OP_I16z, /* 0 .. 16 */
c19d1205
ZW		 7158 OP_I31, /* 0 .. 31 */
7159 OP_I31w, /* 0 .. 31, optional trailing ! */
7160 OP_I32, /* 1 .. 32 */
5287ad62 7161 OP_I32z, /* 0 .. 32 */
08132bdd 7162 OP_I48_I64, /* 48 or 64 */
5287ad62 7163 OP_I63, /* 0 .. 63 */
c19d1205 7164 OP_I63s, /* -64 .. 63 */
5287ad62
JB		 7165 OP_I64, /* 1 .. 64 */
7166 OP_I64z, /* 0 .. 64 */
5aae9ae9 7167 OP_I127, /* 0 .. 127 */
c19d1205 7168 OP_I255, /* 0 .. 255 */
4934a27c 7169 OP_I511, /* 0 .. 511 */
5aae9ae9 7170 OP_I4095, /* 0 .. 4095 */
4934a27c 7171 OP_I8191, /* 0 .. 8191 */
c19d1205
ZW		 7172 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
7173 OP_I7b, /* 0 .. 7 */
7174 OP_I15b, /* 0 .. 15 */
7175 OP_I31b, /* 0 .. 31 */
7176
7177 OP_SH, /* shifter operand */
4962c51a 7178 OP_SHG, /* shifter operand with possible group relocation */
c19d1205 7179 OP_ADDR, /* Memory address expression (any mode) */
35c228db 7180 OP_ADDRMVE, /* Memory address expression for MVE's VSTR/VLDR. */
4962c51a
MS		 7181 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
7182 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
7183 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
c19d1205
ZW		 7184 OP_EXP, /* arbitrary expression */
7185 OP_EXPi, /* same, with optional immediate prefix */
7186 OP_EXPr, /* same, with optional relocation suffix */
e2b0ab59 7187 OP_EXPs, /* same, with optional non-first operand relocation suffix */
b6895b4f 7188 OP_HALF, /* 0 .. 65535 or low/high reloc. */
c28eeff2
SN		 7189 OP_IROT1, /* VCADD rotate immediate: 90, 270. */
7190 OP_IROT2, /* VCMLA rotate immediate: 0, 90, 180, 270. */
c19d1205
ZW		 7191
7192 OP_CPSF, /* CPS flags */
7193 OP_ENDI, /* Endianness specifier */
d2cd1205
JB		 7194 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
7195 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
c19d1205 7196 OP_COND, /* conditional code */
92e90b6e 7197 OP_TB, /* Table branch. */
c19d1205 7198
037e8744
JB		 7199 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
7200
c19d1205 7201 OP_RRnpc_I0, /* ARM register or literal 0 */
33eaf5de 7202 OP_RR_EXr, /* ARM register or expression with opt. reloc stuff. */
c19d1205
ZW		 7203 OP_RR_EXi, /* ARM register or expression with imm prefix */
7204 OP_RF_IF, /* FPA register or immediate */
7205 OP_RIWR_RIWC, /* iWMMXt R or C reg */
41adaa5c 7206 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
c19d1205
ZW		 7207
7208 /* Optional operands. */
7209 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
7210 OP_oI31b, /* 0 .. 31 */
5287ad62 7211 OP_oI32b, /* 1 .. 32 */
5f1af56b 7212 OP_oI32z, /* 0 .. 32 */
c19d1205
ZW		 7213 OP_oIffffb, /* 0 .. 65535 */
7214 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
7215
7216 OP_oRR, /* ARM register */
60f993ce 7217 OP_oLR, /* ARM LR register */
c19d1205 7218 OP_oRRnpc, /* ARM register, not the PC */
5be8be5d 7219 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
b6702015 7220 OP_oRRw, /* ARM register, not r15, optional trailing ! */
5287ad62
JB		 7221 OP_oRND, /* Optional Neon double precision register */
7222 OP_oRNQ, /* Optional Neon quad precision register */
5ee91343 7223 OP_oRNDQMQ, /* Optional Neon double, quad or MVE vector register. */
5287ad62 7224 OP_oRNDQ, /* Optional Neon double or quad precision register */
037e8744 7225 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
5ee91343
AV		 7226 OP_oRNSDQMQ, /* Optional single, double or quad register or MVE vector
7227 register. */
66d1f7cc
AV		 7228 OP_oRNSDMQ, /* Optional single, double register or MVE vector
7229 register. */
c19d1205
ZW		 7230 OP_oSHll, /* LSL immediate */
7231 OP_oSHar, /* ASR immediate */
7232 OP_oSHllar, /* LSL or ASR immediate */
7233 OP_oROR, /* ROR 0/8/16/24 */
52e7f43d 7234 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
c19d1205 7235
1b883319
AV		 7236 OP_oRMQRZ, /* optional MVE vector or ARM register including ZR. */
7237
5be8be5d
DG		 7238 /* Some pre-defined mixed (ARM/THUMB) operands. */
7239 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
7240 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
7241 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
7242
c19d1205
ZW		 7243 OP_FIRST_OPTIONAL = OP_oI7b
7244};
a737bd4d 7245
c19d1205
ZW		 7246/* Generic instruction operand parser. This does no encoding and no
7247 semantic validation; it merely squirrels values away in the inst
7248 structure. Returns SUCCESS or FAIL depending on whether the
7249 specified grammar matched. */
7250static int
5be8be5d 7251parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
c19d1205 7252{
5be8be5d 7253 unsigned const int *upat = pattern;
c19d1205
ZW		 7254 char *backtrack_pos = 0;
7255 const char *backtrack_error = 0;
99aad254 7256 int i, val = 0, backtrack_index = 0;
5287ad62 7257 enum arm_reg_type rtype;
4962c51a 7258 parse_operand_result result;
5be8be5d 7259 unsigned int op_parse_code;
efd6b359 7260 bfd_boolean partial_match;
c19d1205 7261
e07e6e58
NC		 7262#define po_char_or_fail(chr) \
7263 do \
7264 { \
7265 if (skip_past_char (&str, chr) == FAIL) \
477330fc 7266 goto bad_args; \
e07e6e58
NC		 7267 } \
7268 while (0)
c19d1205 7269
e07e6e58
NC		 7270#define po_reg_or_fail(regtype) \
7271 do \
dcbf9037 7272 { \
e07e6e58 7273 val = arm_typed_reg_parse (& str, regtype, & rtype, \
477330fc 7274 & inst.operands[i].vectype); \
e07e6e58 7275 if (val == FAIL) \
477330fc
RM		 7276 { \
7277 first_error (_(reg_expected_msgs[regtype])); \
7278 goto failure; \
7279 } \
e07e6e58
NC		 7280 inst.operands[i].reg = val; \
7281 inst.operands[i].isreg = 1; \
7282 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7283 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7284 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
477330fc
RM		 7285 || rtype == REG_TYPE_VFD \
7286 || rtype == REG_TYPE_NQ); \
1b883319 7287 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
dcbf9037 7288 } \
e07e6e58
NC		 7289 while (0)
7290
7291#define po_reg_or_goto(regtype, label) \
7292 do \
7293 { \
7294 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7295 & inst.operands[i].vectype); \
7296 if (val == FAIL) \
7297 goto label; \
dcbf9037 7298 \
e07e6e58
NC		 7299 inst.operands[i].reg = val; \
7300 inst.operands[i].isreg = 1; \
7301 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7302 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7303 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
477330fc 7304 || rtype == REG_TYPE_VFD \
e07e6e58 7305 || rtype == REG_TYPE_NQ); \
1b883319 7306 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
e07e6e58
NC		 7307 } \
7308 while (0)
7309
7310#define po_imm_or_fail(min, max, popt) \
7311 do \
7312 { \
7313 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7314 goto failure; \
7315 inst.operands[i].imm = val; \
7316 } \
7317 while (0)
7318
08132bdd
SP		 7319#define po_imm1_or_imm2_or_fail(imm1, imm2, popt) \
7320 do \
7321 { \
7322 expressionS exp; \
7323 my_get_expression (&exp, &str, popt); \
7324 if (exp.X_op != O_constant) \
7325 { \
7326 inst.error = _("constant expression required"); \
7327 goto failure; \
7328 } \
7329 if (exp.X_add_number != imm1 && exp.X_add_number != imm2) \
7330 { \
7331 inst.error = _("immediate value 48 or 64 expected"); \
7332 goto failure; \
7333 } \
7334 inst.operands[i].imm = exp.X_add_number; \
7335 } \
7336 while (0)
7337
57785aa2 7338#define po_scalar_or_goto(elsz, label, reg_type) \
e07e6e58
NC		 7339 do \
7340 { \
57785aa2
AV		 7341 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7342 reg_type); \
e07e6e58
NC		 7343 if (val == FAIL) \
7344 goto label; \
7345 inst.operands[i].reg = val; \
7346 inst.operands[i].isscalar = 1; \
7347 } \
7348 while (0)
7349
7350#define po_misc_or_fail(expr) \
7351 do \
7352 { \
7353 if (expr) \
7354 goto failure; \
7355 } \
7356 while (0)
7357
7358#define po_misc_or_fail_no_backtrack(expr) \
7359 do \
7360 { \
7361 result = expr; \
7362 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7363 backtrack_pos = 0; \
7364 if (result != PARSE_OPERAND_SUCCESS) \
7365 goto failure; \
7366 } \
7367 while (0)
4962c51a 7368
52e7f43d
RE		 7369#define po_barrier_or_imm(str) \
7370 do \
7371 { \
7372 val = parse_barrier (&str); \
ccb84d65
JB		 7373 if (val == FAIL && ! ISALPHA (*str)) \
7374 goto immediate; \
7375 if (val == FAIL \
7376 /* ISB can only take SY as an option. */ \
7377 || ((inst.instruction & 0xf0) == 0x60 \
7378 && val != 0xf)) \
52e7f43d 7379 { \
ccb84d65
JB		 7380 inst.error = _("invalid barrier type"); \
7381 backtrack_pos = 0; \
7382 goto failure; \
52e7f43d
RE		 7383 } \
7384 } \
7385 while (0)
7386
c19d1205
ZW		 7387 skip_whitespace (str);
7388
7389 for (i = 0; upat[i] != OP_stop; i++)
7390 {
5be8be5d
DG		 7391 op_parse_code = upat[i];
7392 if (op_parse_code >= 1<<16)
7393 op_parse_code = thumb ? (op_parse_code >> 16)
7394 : (op_parse_code & ((1<<16)-1));
7395
7396 if (op_parse_code >= OP_FIRST_OPTIONAL)
c19d1205
ZW		 7397 {
7398 /* Remember where we are in case we need to backtrack. */
c19d1205
ZW		 7399 backtrack_pos = str;
7400 backtrack_error = inst.error;
7401 backtrack_index = i;
7402 }
7403
b6702015 7404 if (i > 0 && (i > 1 || inst.operands[0].present))
c19d1205
ZW		 7405 po_char_or_fail (',');
7406
5be8be5d 7407 switch (op_parse_code)
c19d1205
ZW		 7408 {
7409 /* Registers */
7410 case OP_oRRnpc:
5be8be5d 7411 case OP_oRRnpcsp:
c19d1205 7412 case OP_RRnpc:
5be8be5d 7413 case OP_RRnpcsp:
c19d1205 7414 case OP_oRR:
a302e574
AV		 7415 case OP_RRe:
7416 case OP_RRo:
60f993ce
AV		 7417 case OP_LR:
7418 case OP_oLR:
c19d1205
ZW		 7419 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
7420 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
7421 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
7422 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
7423 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
7424 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
477330fc 7425 case OP_oRND:
66d1f7cc
AV		 7426 case OP_RNSDMQR:
7427 po_reg_or_goto (REG_TYPE_VFS, try_rndmqr);
7428 break;
7429 try_rndmqr:
5ee91343
AV		 7430 case OP_RNDMQR:
7431 po_reg_or_goto (REG_TYPE_RN, try_rndmq);
7432 break;
7433 try_rndmq:
7434 case OP_RNDMQ:
7435 po_reg_or_goto (REG_TYPE_MQ, try_rnd);
7436 break;
7437 try_rnd:
5287ad62 7438 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
cd2cf30b
PB		 7439 case OP_RVC:
7440 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
7441 break;
7442 /* Also accept generic coprocessor regs for unknown registers. */
7443 coproc_reg:
ba6cd17f
SD		 7444 po_reg_or_goto (REG_TYPE_CN, vpr_po);
7445 break;
7446 /* Also accept P0 or p0 for VPR.P0. Since P0 is already an
7447 existing register with a value of 0, this seems like the
7448 best way to parse P0. */
7449 vpr_po:
7450 if (strncasecmp (str, "P0", 2) == 0)
7451 {
7452 str += 2;
7453 inst.operands[i].isreg = 1;
7454 inst.operands[i].reg = 13;
7455 }
7456 else
7457 goto failure;
cd2cf30b 7458 break;
c19d1205
ZW		 7459 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
7460 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
7461 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
7462 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
7463 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
7464 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
7465 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
7466 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
7467 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
7468 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
477330fc 7469 case OP_oRNQ:
5ee91343
AV		 7470 case OP_RNQMQ:
7471 po_reg_or_goto (REG_TYPE_MQ, try_nq);
7472 break;
7473 try_nq:
5287ad62 7474 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
dec41383 7475 case OP_RNSD: po_reg_or_fail (REG_TYPE_NSD); break;
7df54120
AV		 7476 case OP_RNDQMQR:
7477 po_reg_or_goto (REG_TYPE_RN, try_rndqmq);
7478 break;
7479 try_rndqmq:
5ee91343
AV		 7480 case OP_oRNDQMQ:
7481 case OP_RNDQMQ:
7482 po_reg_or_goto (REG_TYPE_MQ, try_rndq);
7483 break;
7484 try_rndq:
477330fc 7485 case OP_oRNDQ:
5287ad62 7486 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
dd9634d9
AV		 7487 case OP_RVSDMQ:
7488 po_reg_or_goto (REG_TYPE_MQ, try_rvsd);
7489 break;
7490 try_rvsd:
477330fc 7491 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
1b883319
AV		 7492 case OP_RVSD_COND:
7493 po_reg_or_goto (REG_TYPE_VFSD, try_cond);
7494 break;
66d1f7cc 7495 case OP_oRNSDMQ:
5aae9ae9
MM		 7496 case OP_RNSDMQ:
7497 po_reg_or_goto (REG_TYPE_NSD, try_mq2);
7498 break;
7499 try_mq2:
7500 po_reg_or_fail (REG_TYPE_MQ);
7501 break;
477330fc
RM		 7502 case OP_oRNSDQ:
7503 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
5ee91343
AV		 7504 case OP_RNSDQMQR:
7505 po_reg_or_goto (REG_TYPE_RN, try_mq);
7506 break;
7507 try_mq:
7508 case OP_oRNSDQMQ:
7509 case OP_RNSDQMQ:
7510 po_reg_or_goto (REG_TYPE_MQ, try_nsdq2);
7511 break;
7512 try_nsdq2:
7513 po_reg_or_fail (REG_TYPE_NSDQ);
7514 inst.error = 0;
7515 break;
35d1cfc2
AV		 7516 case OP_RMQRR:
7517 po_reg_or_goto (REG_TYPE_RN, try_rmq);
7518 break;
7519 try_rmq:
a302e574
AV		 7520 case OP_RMQ:
7521 po_reg_or_fail (REG_TYPE_MQ);
7522 break;
477330fc
RM		 7523 /* Neon scalar. Using an element size of 8 means that some invalid
7524 scalars are accepted here, so deal with those in later code. */
57785aa2 7525 case OP_RNSC: po_scalar_or_goto (8, failure, REG_TYPE_VFD); break;
477330fc
RM		 7526
7527 case OP_RNDQ_I0:
7528 {
7529 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
7530 break;
7531 try_imm0:
7532 po_imm_or_fail (0, 0, TRUE);
7533 }
7534 break;
7535
7536 case OP_RVSD_I0:
7537 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
7538 break;
7539
1b883319
AV		 7540 case OP_RSVDMQ_FI0:
7541 po_reg_or_goto (REG_TYPE_MQ, try_rsvd_fi0);
7542 break;
7543 try_rsvd_fi0:
aacf0b33
KT		 7544 case OP_RSVD_FI0:
7545 {
7546 po_reg_or_goto (REG_TYPE_VFSD, try_ifimm0);
7547 break;
7548 try_ifimm0:
7549 if (parse_ifimm_zero (&str))
7550 inst.operands[i].imm = 0;
7551 else
7552 {
7553 inst.error
7554 = _("only floating point zero is allowed as immediate value");
7555 goto failure;
7556 }
7557 }
7558 break;
7559
477330fc
RM		 7560 case OP_RR_RNSC:
7561 {
57785aa2 7562 po_scalar_or_goto (8, try_rr, REG_TYPE_VFD);
477330fc
RM		 7563 break;
7564 try_rr:
7565 po_reg_or_fail (REG_TYPE_RN);
7566 }
7567 break;
7568
a8465a06
AV		 7569 case OP_RNSDQ_RNSC_MQ_RR:
7570 po_reg_or_goto (REG_TYPE_RN, try_rnsdq_rnsc_mq);
7571 break;
7572 try_rnsdq_rnsc_mq:
886e1c73
AV		 7573 case OP_RNSDQ_RNSC_MQ:
7574 po_reg_or_goto (REG_TYPE_MQ, try_rnsdq_rnsc);
7575 break;
7576 try_rnsdq_rnsc:
477330fc
RM		 7577 case OP_RNSDQ_RNSC:
7578 {
57785aa2
AV		 7579 po_scalar_or_goto (8, try_nsdq, REG_TYPE_VFD);
7580 inst.error = 0;
477330fc
RM		 7581 break;
7582 try_nsdq:
7583 po_reg_or_fail (REG_TYPE_NSDQ);
57785aa2 7584 inst.error = 0;
477330fc
RM		 7585 }
7586 break;
7587
dec41383
JW		 7588 case OP_RNSD_RNSC:
7589 {
57785aa2 7590 po_scalar_or_goto (8, try_s_scalar, REG_TYPE_VFD);
dec41383
JW		 7591 break;
7592 try_s_scalar:
57785aa2 7593 po_scalar_or_goto (4, try_nsd, REG_TYPE_VFS);
dec41383
JW		 7594 break;
7595 try_nsd:
7596 po_reg_or_fail (REG_TYPE_NSD);
7597 }
7598 break;
7599
42b16635
AV		 7600 case OP_RNDQMQ_RNSC_RR:
7601 po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc_rr);
7602 break;
7603 try_rndq_rnsc_rr:
7604 case OP_RNDQ_RNSC_RR:
7605 po_reg_or_goto (REG_TYPE_RN, try_rndq_rnsc);
7606 break;
5d281bf0
AV		 7607 case OP_RNDQMQ_RNSC:
7608 po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc);
7609 break;
7610 try_rndq_rnsc:
477330fc
RM		 7611 case OP_RNDQ_RNSC:
7612 {
57785aa2 7613 po_scalar_or_goto (8, try_ndq, REG_TYPE_VFD);
477330fc
RM		 7614 break;
7615 try_ndq:
7616 po_reg_or_fail (REG_TYPE_NDQ);
7617 }
7618 break;
7619
7620 case OP_RND_RNSC:
7621 {
57785aa2 7622 po_scalar_or_goto (8, try_vfd, REG_TYPE_VFD);
477330fc
RM		 7623 break;
7624 try_vfd:
7625 po_reg_or_fail (REG_TYPE_VFD);
7626 }
7627 break;
7628
7629 case OP_VMOV:
7630 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7631 not careful then bad things might happen. */
7632 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
7633 break;
7634
f601a00c
AV		 7635 case OP_RNDQMQ_Ibig:
7636 po_reg_or_goto (REG_TYPE_MQ, try_rndq_ibig);
7637 break;
7638 try_rndq_ibig:
477330fc
RM		 7639 case OP_RNDQ_Ibig:
7640 {
7641 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
7642 break;
7643 try_immbig:
7644 /* There's a possibility of getting a 64-bit immediate here, so
7645 we need special handling. */
8335d6aa
JW		 7646 if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/FALSE)
7647 == FAIL)
477330fc
RM		 7648 {
7649 inst.error = _("immediate value is out of range");
7650 goto failure;
7651 }
7652 }
7653 break;
7654
5150f0d8
AV		 7655 case OP_RNDQMQ_I63b_RR:
7656 po_reg_or_goto (REG_TYPE_MQ, try_rndq_i63b_rr);
7657 break;
7658 try_rndq_i63b_rr:
7659 po_reg_or_goto (REG_TYPE_RN, try_rndq_i63b);
7660 break;
7661 try_rndq_i63b:
477330fc
RM		 7662 case OP_RNDQ_I63b:
7663 {
7664 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
7665 break;
7666 try_shimm:
7667 po_imm_or_fail (0, 63, TRUE);
7668 }
7669 break;
c19d1205
ZW		 7670
7671 case OP_RRnpcb:
7672 po_char_or_fail ('[');
7673 po_reg_or_fail (REG_TYPE_RN);
7674 po_char_or_fail (']');
7675 break;
a737bd4d 7676
55881a11 7677 case OP_RRnpctw:
c19d1205 7678 case OP_RRw:
b6702015 7679 case OP_oRRw:
c19d1205
ZW		 7680 po_reg_or_fail (REG_TYPE_RN);
7681 if (skip_past_char (&str, '!') == SUCCESS)
7682 inst.operands[i].writeback = 1;
7683 break;
7684
7685 /* Immediates */
7686 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
7687 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
7688 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
477330fc 7689 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
c19d1205
ZW		 7690 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
7691 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
477330fc 7692 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
08132bdd 7693 case OP_I48_I64: po_imm1_or_imm2_or_fail (48, 64, FALSE); break;
c19d1205 7694 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
477330fc
RM		 7695 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
7696 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
7697 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
5aae9ae9 7698 case OP_I127: po_imm_or_fail ( 0, 127, FALSE); break;
c19d1205 7699 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
4934a27c 7700 case OP_I511: po_imm_or_fail ( 0, 511, FALSE); break;
5aae9ae9 7701 case OP_I4095: po_imm_or_fail ( 0, 4095, FALSE); break;
4934a27c 7702 case OP_I8191: po_imm_or_fail ( 0, 8191, FALSE); break;
c19d1205
ZW		 7703 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
7704 case OP_oI7b:
7705 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
7706 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
7707 case OP_oI31b:
7708 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
477330fc
RM		 7709 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
7710 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
c19d1205
ZW		 7711 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
7712
7713 /* Immediate variants */
7714 case OP_oI255c:
7715 po_char_or_fail ('{');
7716 po_imm_or_fail (0, 255, TRUE);
7717 po_char_or_fail ('}');
7718 break;
7719
7720 case OP_I31w:
7721 /* The expression parser chokes on a trailing !, so we have
7722 to find it first and zap it. */
7723 {
7724 char *s = str;
7725 while (*s && *s != ',')
7726 s++;
7727 if (s[-1] == '!')
7728 {
7729 s[-1] = '\0';
7730 inst.operands[i].writeback = 1;
7731 }
7732 po_imm_or_fail (0, 31, TRUE);
7733 if (str == s - 1)
7734 str = s;
7735 }
7736 break;
7737
7738 /* Expressions */
7739 case OP_EXPi: EXPi:
e2b0ab59 7740 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
c19d1205
ZW		 7741 GE_OPT_PREFIX));
7742 break;
7743
7744 case OP_EXP:
e2b0ab59 7745 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
c19d1205
ZW		 7746 GE_NO_PREFIX));
7747 break;
7748
7749 case OP_EXPr: EXPr:
e2b0ab59 7750 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
c19d1205 7751 GE_NO_PREFIX));
e2b0ab59 7752 if (inst.relocs[0].exp.X_op == O_symbol)
a737bd4d 7753 {
c19d1205
ZW		 7754 val = parse_reloc (&str);
7755 if (val == -1)
7756 {
7757 inst.error = _("unrecognized relocation suffix");
7758 goto failure;
7759 }
7760 else if (val != BFD_RELOC_UNUSED)
7761 {
7762 inst.operands[i].imm = val;
7763 inst.operands[i].hasreloc = 1;
7764 }
a737bd4d 7765 }
c19d1205 7766 break;
a737bd4d 7767
e2b0ab59
AV		 7768 case OP_EXPs:
7769 po_misc_or_fail (my_get_expression (&inst.relocs[i].exp, &str,
7770 GE_NO_PREFIX));
7771 if (inst.relocs[i].exp.X_op == O_symbol)
7772 {
7773 inst.operands[i].hasreloc = 1;
7774 }
7775 else if (inst.relocs[i].exp.X_op == O_constant)
7776 {
7777 inst.operands[i].imm = inst.relocs[i].exp.X_add_number;
7778 inst.operands[i].hasreloc = 0;
7779 }
7780 break;
7781
b6895b4f
PB		 7782 /* Operand for MOVW or MOVT. */
7783 case OP_HALF:
7784 po_misc_or_fail (parse_half (&str));
7785 break;
7786
e07e6e58 7787 /* Register or expression. */
c19d1205
ZW		 7788 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
7789 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
a737bd4d 7790
e07e6e58 7791 /* Register or immediate. */
c19d1205
ZW		 7792 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
7793 I0: po_imm_or_fail (0, 0, FALSE); break;
a737bd4d 7794
23d00a41
SD		 7795 case OP_RRnpcsp_I32: po_reg_or_goto (REG_TYPE_RN, I32); break;
7796 I32: po_imm_or_fail (1, 32, FALSE); break;
7797
c19d1205
ZW		 7798 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
7799 IF:
7800 if (!is_immediate_prefix (*str))
7801 goto bad_args;
7802 str++;
7803 val = parse_fpa_immediate (&str);
7804 if (val == FAIL)
7805 goto failure;
7806 /* FPA immediates are encoded as registers 8-15.
7807 parse_fpa_immediate has already applied the offset. */
7808 inst.operands[i].reg = val;
7809 inst.operands[i].isreg = 1;
7810 break;
09d92015 7811
2d447fca
JM		 7812 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
7813 I32z: po_imm_or_fail (0, 32, FALSE); break;
7814
e07e6e58 7815 /* Two kinds of register. */
c19d1205
ZW		 7816 case OP_RIWR_RIWC:
7817 {
7818 struct reg_entry *rege = arm_reg_parse_multi (&str);
97f87066
JM		 7819 if (!rege
7820 || (rege->type != REG_TYPE_MMXWR
7821 && rege->type != REG_TYPE_MMXWC
7822 && rege->type != REG_TYPE_MMXWCG))
c19d1205
ZW		 7823 {
7824 inst.error = _("iWMMXt data or control register expected");
7825 goto failure;
7826 }
7827 inst.operands[i].reg = rege->number;
7828 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
7829 }
7830 break;
09d92015 7831
41adaa5c
JM		 7832 case OP_RIWC_RIWG:
7833 {
7834 struct reg_entry *rege = arm_reg_parse_multi (&str);
7835 if (!rege
7836 || (rege->type != REG_TYPE_MMXWC
7837 && rege->type != REG_TYPE_MMXWCG))
7838 {
7839 inst.error = _("iWMMXt control register expected");
7840 goto failure;
7841 }
7842 inst.operands[i].reg = rege->number;
7843 inst.operands[i].isreg = 1;
7844 }
7845 break;
7846
c19d1205
ZW		 7847 /* Misc */
7848 case OP_CPSF: val = parse_cps_flags (&str); break;
7849 case OP_ENDI: val = parse_endian_specifier (&str); break;
7850 case OP_oROR: val = parse_ror (&str); break;
1b883319 7851 try_cond:
c19d1205 7852 case OP_COND: val = parse_cond (&str); break;
52e7f43d
RE		 7853 case OP_oBARRIER_I15:
7854 po_barrier_or_imm (str); break;
7855 immediate:
7856 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
477330fc 7857 goto failure;
52e7f43d 7858 break;
c19d1205 7859
fa94de6b 7860 case OP_wPSR:
d2cd1205 7861 case OP_rPSR:
90ec0d68
MGD		 7862 po_reg_or_goto (REG_TYPE_RNB, try_psr);
7863 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
7864 {
7865 inst.error = _("Banked registers are not available with this "
7866 "architecture.");
7867 goto failure;
7868 }
7869 break;
d2cd1205
JB		 7870 try_psr:
7871 val = parse_psr (&str, op_parse_code == OP_wPSR);
7872 break;
037e8744 7873
32c36c3c
AV		 7874 case OP_VLDR:
7875 po_reg_or_goto (REG_TYPE_VFSD, try_sysreg);
7876 break;
7877 try_sysreg:
7878 val = parse_sys_vldr_vstr (&str);
7879 break;
7880
477330fc
RM		 7881 case OP_APSR_RR:
7882 po_reg_or_goto (REG_TYPE_RN, try_apsr);
7883 break;
7884 try_apsr:
7885 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7886 instruction). */
7887 if (strncasecmp (str, "APSR_", 5) == 0)
7888 {
7889 unsigned found = 0;
7890 str += 5;
7891 while (found < 15)
7892 switch (*str++)
7893 {
7894 case 'c': found = (found & 1) ? 16 : found | 1; break;
7895 case 'n': found = (found & 2) ? 16 : found | 2; break;
7896 case 'z': found = (found & 4) ? 16 : found | 4; break;
7897 case 'v': found = (found & 8) ? 16 : found | 8; break;
7898 default: found = 16;
7899 }
7900 if (found != 15)
7901 goto failure;
7902 inst.operands[i].isvec = 1;
f7c21dc7
NC		 7903 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7904 inst.operands[i].reg = REG_PC;
477330fc
RM		 7905 }
7906 else
7907 goto failure;
7908 break;
037e8744 7909
92e90b6e
PB		 7910 case OP_TB:
7911 po_misc_or_fail (parse_tb (&str));
7912 break;
7913
e07e6e58 7914 /* Register lists. */
c19d1205 7915 case OP_REGLST:
4b5a202f 7916 val = parse_reg_list (&str, REGLIST_RN);
c19d1205
ZW		 7917 if (*str == '^')
7918 {
5e0d7f77 7919 inst.operands[i].writeback = 1;
c19d1205
ZW		 7920 str++;
7921 }
7922 break;
09d92015 7923
4b5a202f
AV		 7924 case OP_CLRMLST:
7925 val = parse_reg_list (&str, REGLIST_CLRM);
7926 break;
7927
c19d1205 7928 case OP_VRSLST:
efd6b359
AV		 7929 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S,
7930 &partial_match);
c19d1205 7931 break;
09d92015 7932
c19d1205 7933 case OP_VRDLST:
efd6b359
AV		 7934 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D,
7935 &partial_match);
c19d1205 7936 break;
a737bd4d 7937
477330fc
RM		 7938 case OP_VRSDLST:
7939 /* Allow Q registers too. */
7940 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
efd6b359 7941 REGLIST_NEON_D, &partial_match);
477330fc
RM		 7942 if (val == FAIL)
7943 {
7944 inst.error = NULL;
7945 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
efd6b359
AV		 7946 REGLIST_VFP_S, &partial_match);
7947 inst.operands[i].issingle = 1;
7948 }
7949 break;
7950
7951 case OP_VRSDVLST:
7952 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7953 REGLIST_VFP_D_VPR, &partial_match);
7954 if (val == FAIL && !partial_match)
7955 {
7956 inst.error = NULL;
7957 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7958 REGLIST_VFP_S_VPR, &partial_match);
477330fc
RM		 7959 inst.operands[i].issingle = 1;
7960 }
7961 break;
7962
7963 case OP_NRDLST:
7964 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
efd6b359 7965 REGLIST_NEON_D, &partial_match);
477330fc 7966 break;
5287ad62 7967
35c228db
AV		 7968 case OP_MSTRLST4:
7969 case OP_MSTRLST2:
7970 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
7971 1, &inst.operands[i].vectype);
7972 if (val != (((op_parse_code == OP_MSTRLST2) ? 3 : 7) << 5 | 0xe))
7973 goto failure;
7974 break;
5287ad62 7975 case OP_NSTRLST:
477330fc 7976 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
35c228db 7977 0, &inst.operands[i].vectype);
477330fc 7978 break;
5287ad62 7979
c19d1205 7980 /* Addressing modes */
35c228db
AV		 7981 case OP_ADDRMVE:
7982 po_misc_or_fail (parse_address_group_reloc (&str, i, GROUP_MVE));
7983 break;
7984
c19d1205
ZW		 7985 case OP_ADDR:
7986 po_misc_or_fail (parse_address (&str, i));
7987 break;
09d92015 7988
4962c51a
MS		 7989 case OP_ADDRGLDR:
7990 po_misc_or_fail_no_backtrack (
477330fc 7991 parse_address_group_reloc (&str, i, GROUP_LDR));
4962c51a
MS		 7992 break;
7993
7994 case OP_ADDRGLDRS:
7995 po_misc_or_fail_no_backtrack (
477330fc 7996 parse_address_group_reloc (&str, i, GROUP_LDRS));
4962c51a
MS		 7997 break;
7998
7999 case OP_ADDRGLDC:
8000 po_misc_or_fail_no_backtrack (
477330fc 8001 parse_address_group_reloc (&str, i, GROUP_LDC));
4962c51a
MS		 8002 break;
8003
c19d1205
ZW		 8004 case OP_SH:
8005 po_misc_or_fail (parse_shifter_operand (&str, i));
8006 break;
09d92015 8007
4962c51a
MS		 8008 case OP_SHG:
8009 po_misc_or_fail_no_backtrack (
477330fc 8010 parse_shifter_operand_group_reloc (&str, i));
4962c51a
MS		 8011 break;
8012
c19d1205
ZW		 8013 case OP_oSHll:
8014 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
8015 break;
09d92015 8016
c19d1205
ZW		 8017 case OP_oSHar:
8018 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
8019 break;
09d92015 8020
c19d1205
ZW		 8021 case OP_oSHllar:
8022 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
8023 break;
09d92015 8024
1b883319
AV		 8025 case OP_RMQRZ:
8026 case OP_oRMQRZ:
8027 po_reg_or_goto (REG_TYPE_MQ, try_rr_zr);
8028 break;
e39c1607
SD		 8029
8030 case OP_RR_ZR:
1b883319
AV		 8031 try_rr_zr:
8032 po_reg_or_goto (REG_TYPE_RN, ZR);
8033 break;
8034 ZR:
8035 po_reg_or_fail (REG_TYPE_ZR);
8036 break;
8037
c19d1205 8038 default:
5be8be5d 8039 as_fatal (_("unhandled operand code %d"), op_parse_code);
c19d1205 8040 }
09d92015 8041
c19d1205
ZW		 8042 /* Various value-based sanity checks and shared operations. We
8043 do not signal immediate failures for the register constraints;
8044 this allows a syntax error to take precedence. */
5be8be5d 8045 switch (op_parse_code)
c19d1205
ZW		 8046 {
8047 case OP_oRRnpc:
8048 case OP_RRnpc:
8049 case OP_RRnpcb:
8050 case OP_RRw:
b6702015 8051 case OP_oRRw:
c19d1205
ZW		 8052 case OP_RRnpc_I0:
8053 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
8054 inst.error = BAD_PC;
8055 break;
09d92015 8056
5be8be5d
DG		 8057 case OP_oRRnpcsp:
8058 case OP_RRnpcsp:
23d00a41 8059 case OP_RRnpcsp_I32:
5be8be5d
DG		 8060 if (inst.operands[i].isreg)
8061 {
8062 if (inst.operands[i].reg == REG_PC)
8063 inst.error = BAD_PC;
5c8ed6a4
JW		 8064 else if (inst.operands[i].reg == REG_SP
8065 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
8066 relaxed since ARMv8-A. */
8067 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
8068 {
8069 gas_assert (thumb);
8070 inst.error = BAD_SP;
8071 }
5be8be5d
DG		 8072 }
8073 break;
8074
55881a11 8075 case OP_RRnpctw:
fa94de6b
RM		 8076 if (inst.operands[i].isreg
8077 && inst.operands[i].reg == REG_PC
55881a11
MGD		 8078 && (inst.operands[i].writeback || thumb))
8079 inst.error = BAD_PC;
8080 break;
8081
1b883319 8082 case OP_RVSD_COND:
32c36c3c
AV		 8083 case OP_VLDR:
8084 if (inst.operands[i].isreg)
8085 break;
8086 /* fall through. */
1b883319 8087
c19d1205
ZW		 8088 case OP_CPSF:
8089 case OP_ENDI:
8090 case OP_oROR:
d2cd1205
JB		 8091 case OP_wPSR:
8092 case OP_rPSR:
c19d1205 8093 case OP_COND:
52e7f43d 8094 case OP_oBARRIER_I15:
c19d1205 8095 case OP_REGLST:
4b5a202f 8096 case OP_CLRMLST:
c19d1205
ZW		 8097 case OP_VRSLST:
8098 case OP_VRDLST:
477330fc 8099 case OP_VRSDLST:
efd6b359 8100 case OP_VRSDVLST:
477330fc
RM		 8101 case OP_NRDLST:
8102 case OP_NSTRLST:
35c228db
AV		 8103 case OP_MSTRLST2:
8104 case OP_MSTRLST4:
c19d1205
ZW		 8105 if (val == FAIL)
8106 goto failure;
8107 inst.operands[i].imm = val;
8108 break;
a737bd4d 8109
60f993ce
AV		 8110 case OP_LR:
8111 case OP_oLR:
8112 if (inst.operands[i].reg != REG_LR)
8113 inst.error = _("operand must be LR register");
8114 break;
8115
1b883319
AV		 8116 case OP_RMQRZ:
8117 case OP_oRMQRZ:
e39c1607 8118 case OP_RR_ZR:
1b883319
AV		 8119 if (!inst.operands[i].iszr && inst.operands[i].reg == REG_PC)
8120 inst.error = BAD_PC;
8121 break;
8122
a302e574
AV		 8123 case OP_RRe:
8124 if (inst.operands[i].isreg
8125 && (inst.operands[i].reg & 0x00000001) != 0)
8126 inst.error = BAD_ODD;
8127 break;
8128
8129 case OP_RRo:
8130 if (inst.operands[i].isreg)
8131 {
8132 if ((inst.operands[i].reg & 0x00000001) != 1)
8133 inst.error = BAD_EVEN;
8134 else if (inst.operands[i].reg == REG_SP)
8135 as_tsktsk (MVE_BAD_SP);
8136 else if (inst.operands[i].reg == REG_PC)
8137 inst.error = BAD_PC;
8138 }
8139 break;
8140
c19d1205
ZW		 8141 default:
8142 break;
8143 }
09d92015 8144
c19d1205
ZW		 8145 /* If we get here, this operand was successfully parsed. */
8146 inst.operands[i].present = 1;
8147 continue;
09d92015 8148
c19d1205 8149 bad_args:
09d92015 8150 inst.error = BAD_ARGS;
c19d1205
ZW		 8151
8152 failure:
8153 if (!backtrack_pos)
d252fdde
PB		 8154 {
8155 /* The parse routine should already have set inst.error, but set a
5f4273c7 8156 default here just in case. */
d252fdde 8157 if (!inst.error)
5ee91343 8158 inst.error = BAD_SYNTAX;
d252fdde
PB		 8159 return FAIL;
8160 }
c19d1205
ZW		 8161
8162 /* Do not backtrack over a trailing optional argument that
8163 absorbed some text. We will only fail again, with the
8164 'garbage following instruction' error message, which is
8165 probably less helpful than the current one. */
8166 if (backtrack_index == i && backtrack_pos != str
8167 && upat[i+1] == OP_stop)
d252fdde
PB		 8168 {
8169 if (!inst.error)
5ee91343 8170 inst.error = BAD_SYNTAX;
d252fdde
PB		 8171 return FAIL;
8172 }
c19d1205
ZW		 8173
8174 /* Try again, skipping the optional argument at backtrack_pos. */
8175 str = backtrack_pos;
8176 inst.error = backtrack_error;
8177 inst.operands[backtrack_index].present = 0;
8178 i = backtrack_index;
8179 backtrack_pos = 0;
09d92015 8180 }
09d92015 8181
c19d1205
ZW		 8182 /* Check that we have parsed all the arguments. */
8183 if (*str != '\0' && !inst.error)
8184 inst.error = _("garbage following instruction");
09d92015 8185
c19d1205 8186 return inst.error ? FAIL : SUCCESS;
09d92015
MM		 8187}
8188
c19d1205
ZW		 8189#undef po_char_or_fail
8190#undef po_reg_or_fail
8191#undef po_reg_or_goto
8192#undef po_imm_or_fail
5287ad62 8193#undef po_scalar_or_fail
52e7f43d 8194#undef po_barrier_or_imm
e07e6e58 8195
c19d1205 8196/* Shorthand macro for instruction encoding functions issuing errors. */
e07e6e58
NC		 8197#define constraint(expr, err) \
8198 do \
c19d1205 8199 { \
e07e6e58
NC		 8200 if (expr) \
8201 { \
8202 inst.error = err; \
8203 return; \
8204 } \
c19d1205 8205 } \
e07e6e58 8206 while (0)
c19d1205 8207
fdfde340
JM		 8208/* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
8209 instructions are unpredictable if these registers are used. This
5c8ed6a4
JW		 8210 is the BadReg predicate in ARM's Thumb-2 documentation.
8211
8212 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
8213 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
8214#define reject_bad_reg(reg) \
8215 do \
8216 if (reg == REG_PC) \
8217 { \
8218 inst.error = BAD_PC; \
8219 return; \
8220 } \
8221 else if (reg == REG_SP \
8222 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
8223 { \
8224 inst.error = BAD_SP; \
8225 return; \
8226 } \
fdfde340
JM		 8227 while (0)
8228
94206790
MM		 8229/* If REG is R13 (the stack pointer), warn that its use is
8230 deprecated. */
8231#define warn_deprecated_sp(reg) \
8232 do \
8233 if (warn_on_deprecated && reg == REG_SP) \
5c3696f8 8234 as_tsktsk (_("use of r13 is deprecated")); \
94206790
MM		 8235 while (0)
8236
c19d1205
ZW		 8237/* Functions for operand encoding. ARM, then Thumb. */
8238
d840c081 8239#define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
c19d1205 8240
9db2f6b4
RL		 8241/* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8242
8243 The only binary encoding difference is the Coprocessor number. Coprocessor
8244 9 is used for half-precision calculations or conversions. The format of the
2b0f3761 8245 instruction is the same as the equivalent Coprocessor 10 instruction that
9db2f6b4
RL		 8246 exists for Single-Precision operation. */
8247
8248static void
8249do_scalar_fp16_v82_encode (void)
8250{
5ee91343 8251 if (inst.cond < COND_ALWAYS)
9db2f6b4
RL		 8252 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8253 " the behaviour is UNPREDICTABLE"));
8254 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
8255 _(BAD_FP16));
8256
8257 inst.instruction = (inst.instruction & 0xfffff0ff) | 0x900;
8258 mark_feature_used (&arm_ext_fp16);
8259}
8260
c19d1205
ZW		 8261/* If VAL can be encoded in the immediate field of an ARM instruction,
8262 return the encoded form. Otherwise, return FAIL. */
8263
8264static unsigned int
8265encode_arm_immediate (unsigned int val)
09d92015 8266{
c19d1205
ZW		 8267 unsigned int a, i;
8268
4f1d6205
L		 8269 if (val <= 0xff)
8270 return val;
8271
8272 for (i = 2; i < 32; i += 2)
c19d1205
ZW		 8273 if ((a = rotate_left (val, i)) <= 0xff)
8274 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
8275
8276 return FAIL;
09d92015
MM		 8277}
8278
c19d1205
ZW		 8279/* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8280 return the encoded form. Otherwise, return FAIL. */
8281static unsigned int
8282encode_thumb32_immediate (unsigned int val)
09d92015 8283{
c19d1205 8284 unsigned int a, i;
09d92015 8285
9c3c69f2 8286 if (val <= 0xff)
c19d1205 8287 return val;
a737bd4d 8288
9c3c69f2 8289 for (i = 1; i <= 24; i++)
09d92015 8290 {
9c3c69f2
PB		 8291 a = val >> i;
8292 if ((val & ~(0xff << i)) == 0)
8293 return ((val >> i) & 0x7f) | ((32 - i) << 7);
09d92015 8294 }
a737bd4d 8295
c19d1205
ZW		 8296 a = val & 0xff;
8297 if (val == ((a << 16) | a))
8298 return 0x100 | a;
8299 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
8300 return 0x300 | a;
09d92015 8301
c19d1205
ZW		 8302 a = val & 0xff00;
8303 if (val == ((a << 16) | a))
8304 return 0x200 | (a >> 8);
a737bd4d 8305
c19d1205 8306 return FAIL;
09d92015 8307}
5287ad62 8308/* Encode a VFP SP or DP register number into inst.instruction. */
09d92015
MM		 8309
8310static void
5287ad62
JB		 8311encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
8312{
8313 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
8314 && reg > 15)
8315 {
b1cc4aeb 8316 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
477330fc
RM		 8317 {
8318 if (thumb_mode)
8319 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
8320 fpu_vfp_ext_d32);
8321 else
8322 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
8323 fpu_vfp_ext_d32);
8324 }
5287ad62 8325 else
477330fc
RM		 8326 {
8327 first_error (_("D register out of range for selected VFP version"));
8328 return;
8329 }
5287ad62
JB		 8330 }
8331
c19d1205 8332 switch (pos)
09d92015 8333 {
c19d1205
ZW		 8334 case VFP_REG_Sd:
8335 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
8336 break;
8337
8338 case VFP_REG_Sn:
8339 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
8340 break;
8341
8342 case VFP_REG_Sm:
8343 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
8344 break;
8345
5287ad62
JB		 8346 case VFP_REG_Dd:
8347 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
8348 break;
5f4273c7 8349
5287ad62
JB		 8350 case VFP_REG_Dn:
8351 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
8352 break;
5f4273c7 8353
5287ad62
JB		 8354 case VFP_REG_Dm:
8355 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
8356 break;
8357
c19d1205
ZW		 8358 default:
8359 abort ();
09d92015 8360 }
09d92015
MM		 8361}
8362
c19d1205 8363/* Encode a <shift> in an ARM-format instruction. The immediate,
55cf6793 8364 if any, is handled by md_apply_fix. */
09d92015 8365static void
c19d1205 8366encode_arm_shift (int i)
09d92015 8367{
008a97ef
RL		 8368 /* register-shifted register. */
8369 if (inst.operands[i].immisreg)
8370 {
bf355b69
MR		 8371 int op_index;
8372 for (op_index = 0; op_index <= i; ++op_index)
008a97ef 8373 {
5689c942
RL		 8374 /* Check the operand only when it's presented. In pre-UAL syntax,
8375 if the destination register is the same as the first operand, two
8376 register form of the instruction can be used. */
bf355b69
MR		 8377 if (inst.operands[op_index].present && inst.operands[op_index].isreg
8378 && inst.operands[op_index].reg == REG_PC)
008a97ef
RL		 8379 as_warn (UNPRED_REG ("r15"));
8380 }
8381
8382 if (inst.operands[i].imm == REG_PC)
8383 as_warn (UNPRED_REG ("r15"));
8384 }
8385
c19d1205
ZW		 8386 if (inst.operands[i].shift_kind == SHIFT_RRX)
8387 inst.instruction |= SHIFT_ROR << 5;
8388 else
09d92015 8389 {
c19d1205
ZW		 8390 inst.instruction |= inst.operands[i].shift_kind << 5;
8391 if (inst.operands[i].immisreg)
8392 {
8393 inst.instruction |= SHIFT_BY_REG;
8394 inst.instruction |= inst.operands[i].imm << 8;
8395 }
8396 else
e2b0ab59 8397 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
09d92015 8398 }
c19d1205 8399}
09d92015 8400
c19d1205
ZW		 8401static void
8402encode_arm_shifter_operand (int i)
8403{
8404 if (inst.operands[i].isreg)
09d92015 8405 {
c19d1205
ZW		 8406 inst.instruction |= inst.operands[i].reg;
8407 encode_arm_shift (i);
09d92015 8408 }
c19d1205 8409 else
a415b1cd
JB		 8410 {
8411 inst.instruction |= INST_IMMEDIATE;
e2b0ab59 8412 if (inst.relocs[0].type != BFD_RELOC_ARM_IMMEDIATE)
a415b1cd
JB		 8413 inst.instruction |= inst.operands[i].imm;
8414 }
09d92015
MM		 8415}
8416
c19d1205 8417/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
09d92015 8418static void
c19d1205 8419encode_arm_addr_mode_common (int i, bfd_boolean is_t)
09d92015 8420{
2b2f5df9
NC		 8421 /* PR 14260:
8422 Generate an error if the operand is not a register. */
8423 constraint (!inst.operands[i].isreg,
8424 _("Instruction does not support =N addresses"));
8425
c19d1205 8426 inst.instruction |= inst.operands[i].reg << 16;
a737bd4d 8427
c19d1205 8428 if (inst.operands[i].preind)
09d92015 8429 {
c19d1205
ZW		 8430 if (is_t)
8431 {
8432 inst.error = _("instruction does not accept preindexed addressing");
8433 return;
8434 }
8435 inst.instruction |= PRE_INDEX;
8436 if (inst.operands[i].writeback)
8437 inst.instruction |= WRITE_BACK;
09d92015 8438
c19d1205
ZW		 8439 }
8440 else if (inst.operands[i].postind)
8441 {
9c2799c2 8442 gas_assert (inst.operands[i].writeback);
c19d1205
ZW		 8443 if (is_t)
8444 inst.instruction |= WRITE_BACK;
8445 }
8446 else /* unindexed - only for coprocessor */
09d92015 8447 {
c19d1205 8448 inst.error = _("instruction does not accept unindexed addressing");
09d92015
MM		 8449 return;
8450 }
8451
c19d1205
ZW		 8452 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
8453 && (((inst.instruction & 0x000f0000) >> 16)
8454 == ((inst.instruction & 0x0000f000) >> 12)))
8455 as_warn ((inst.instruction & LOAD_BIT)
8456 ? _("destination register same as write-back base")
8457 : _("source register same as write-back base"));
09d92015
MM		 8458}
8459
c19d1205
ZW		 8460/* inst.operands[i] was set up by parse_address. Encode it into an
8461 ARM-format mode 2 load or store instruction. If is_t is true,
8462 reject forms that cannot be used with a T instruction (i.e. not
8463 post-indexed). */
a737bd4d 8464static void
c19d1205 8465encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
09d92015 8466{
5be8be5d
DG		 8467 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
8468
c19d1205 8469 encode_arm_addr_mode_common (i, is_t);
a737bd4d 8470
c19d1205 8471 if (inst.operands[i].immisreg)
09d92015 8472 {
5be8be5d
DG		 8473 constraint ((inst.operands[i].imm == REG_PC
8474 || (is_pc && inst.operands[i].writeback)),
8475 BAD_PC_ADDRESSING);
c19d1205
ZW		 8476 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
8477 inst.instruction |= inst.operands[i].imm;
8478 if (!inst.operands[i].negative)
8479 inst.instruction |= INDEX_UP;
8480 if (inst.operands[i].shifted)
8481 {
8482 if (inst.operands[i].shift_kind == SHIFT_RRX)
8483 inst.instruction |= SHIFT_ROR << 5;
8484 else
8485 {
8486 inst.instruction |= inst.operands[i].shift_kind << 5;
e2b0ab59 8487 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
c19d1205
ZW		 8488 }
8489 }
09d92015 8490 }
e2b0ab59 8491 else /* immediate offset in inst.relocs[0] */
09d92015 8492 {
e2b0ab59 8493 if (is_pc && !inst.relocs[0].pc_rel)
5be8be5d
DG		 8494 {
8495 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
23a10334
JZ		 8496
8497 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8498 cannot use PC in addressing.
8499 PC cannot be used in writeback addressing, either. */
8500 constraint ((is_t || inst.operands[i].writeback),
5be8be5d 8501 BAD_PC_ADDRESSING);
23a10334 8502
dc5ec521 8503 /* Use of PC in str is deprecated for ARMv7. */
23a10334
JZ		 8504 if (warn_on_deprecated
8505 && !is_load
8506 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
5c3696f8 8507 as_tsktsk (_("use of PC in this instruction is deprecated"));
5be8be5d
DG		 8508 }
8509
e2b0ab59 8510 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
26d97720
NS		 8511 {
8512 /* Prefer + for zero encoded value. */
8513 if (!inst.operands[i].negative)
8514 inst.instruction |= INDEX_UP;
e2b0ab59 8515 inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM;
26d97720 8516 }
09d92015 8517 }
09d92015
MM		 8518}
8519
c19d1205
ZW		 8520/* inst.operands[i] was set up by parse_address. Encode it into an
8521 ARM-format mode 3 load or store instruction. Reject forms that
8522 cannot be used with such instructions. If is_t is true, reject
8523 forms that cannot be used with a T instruction (i.e. not
8524 post-indexed). */
8525static void
8526encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
09d92015 8527{
c19d1205 8528 if (inst.operands[i].immisreg && inst.operands[i].shifted)
09d92015 8529 {
c19d1205
ZW		 8530 inst.error = _("instruction does not accept scaled register index");
8531 return;
09d92015 8532 }
a737bd4d 8533
c19d1205 8534 encode_arm_addr_mode_common (i, is_t);
a737bd4d 8535
c19d1205
ZW		 8536 if (inst.operands[i].immisreg)
8537 {
5be8be5d 8538 constraint ((inst.operands[i].imm == REG_PC
eb9f3f00 8539 || (is_t && inst.operands[i].reg == REG_PC)),
5be8be5d 8540 BAD_PC_ADDRESSING);
eb9f3f00
JB		 8541 constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback,
8542 BAD_PC_WRITEBACK);
c19d1205
ZW		 8543 inst.instruction |= inst.operands[i].imm;
8544 if (!inst.operands[i].negative)
8545 inst.instruction |= INDEX_UP;
8546 }
e2b0ab59 8547 else /* immediate offset in inst.relocs[0] */
c19d1205 8548 {
e2b0ab59 8549 constraint ((inst.operands[i].reg == REG_PC && !inst.relocs[0].pc_rel
5be8be5d
DG		 8550 && inst.operands[i].writeback),
8551 BAD_PC_WRITEBACK);
c19d1205 8552 inst.instruction |= HWOFFSET_IMM;
e2b0ab59 8553 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
26d97720
NS		 8554 {
8555 /* Prefer + for zero encoded value. */
8556 if (!inst.operands[i].negative)
8557 inst.instruction |= INDEX_UP;
8558
e2b0ab59 8559 inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM8;
26d97720 8560 }
c19d1205 8561 }
a737bd4d
NC		 8562}
8563
8335d6aa
JW		 8564/* Write immediate bits [7:0] to the following locations:
8565
8566 |28/24|23 19|18 16|15 4|3 0|
8567 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8568
8569 This function is used by VMOV/VMVN/VORR/VBIC. */
8570
8571static void
8572neon_write_immbits (unsigned immbits)
8573{
8574 inst.instruction |= immbits & 0xf;
8575 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
8576 inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24);
8577}
8578
8579/* Invert low-order SIZE bits of XHI:XLO. */
8580
8581static void
8582neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
8583{
8584 unsigned immlo = xlo ? *xlo : 0;
8585 unsigned immhi = xhi ? *xhi : 0;
8586
8587 switch (size)
8588 {
8589 case 8:
8590 immlo = (~immlo) & 0xff;
8591 break;
8592
8593 case 16:
8594 immlo = (~immlo) & 0xffff;
8595 break;
8596
8597 case 64:
8598 immhi = (~immhi) & 0xffffffff;
8599 /* fall through. */
8600
8601 case 32:
8602 immlo = (~immlo) & 0xffffffff;
8603 break;
8604
8605 default:
8606 abort ();
8607 }
8608
8609 if (xlo)
8610 *xlo = immlo;
8611
8612 if (xhi)
8613 *xhi = immhi;
8614}
8615
8616/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8617 A, B, C, D. */
09d92015 8618
c19d1205 8619static int
8335d6aa 8620neon_bits_same_in_bytes (unsigned imm)
09d92015 8621{
8335d6aa
JW		 8622 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
8623 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
8624 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
8625 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
8626}
a737bd4d 8627
8335d6aa 8628/* For immediate of above form, return 0bABCD. */
09d92015 8629
8335d6aa
JW		 8630static unsigned
8631neon_squash_bits (unsigned imm)
8632{
8633 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
8634 | ((imm & 0x01000000) >> 21);
8635}
8636
8637/* Compress quarter-float representation to 0b...000 abcdefgh. */
8638
8639static unsigned
8640neon_qfloat_bits (unsigned imm)
8641{
8642 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
8643}
8644
8645/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8646 the instruction. *OP is passed as the initial value of the op field, and
8647 may be set to a different value depending on the constant (i.e.
8648 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8649 MVN). If the immediate looks like a repeated pattern then also
8650 try smaller element sizes. */
8651
8652static int
8653neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
8654 unsigned *immbits, int *op, int size,
8655 enum neon_el_type type)
8656{
8657 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8658 float. */
8659 if (type == NT_float && !float_p)
8660 return FAIL;
8661
8662 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
09d92015 8663 {
8335d6aa
JW		 8664 if (size != 32 || *op == 1)
8665 return FAIL;
8666 *immbits = neon_qfloat_bits (immlo);
8667 return 0xf;
8668 }
8669
8670 if (size == 64)
8671 {
8672 if (neon_bits_same_in_bytes (immhi)
8673 && neon_bits_same_in_bytes (immlo))
c19d1205 8674 {
8335d6aa
JW		 8675 if (*op == 1)
8676 return FAIL;
8677 *immbits = (neon_squash_bits (immhi) << 4)
8678 | neon_squash_bits (immlo);
8679 *op = 1;
8680 return 0xe;
c19d1205 8681 }
a737bd4d 8682
8335d6aa
JW		 8683 if (immhi != immlo)
8684 return FAIL;
8685 }
a737bd4d 8686
8335d6aa 8687 if (size >= 32)
09d92015 8688 {
8335d6aa 8689 if (immlo == (immlo & 0x000000ff))
c19d1205 8690 {
8335d6aa
JW		 8691 *immbits = immlo;
8692 return 0x0;
c19d1205 8693 }
8335d6aa 8694 else if (immlo == (immlo & 0x0000ff00))
c19d1205 8695 {
8335d6aa
JW		 8696 *immbits = immlo >> 8;
8697 return 0x2;
c19d1205 8698 }
8335d6aa
JW		 8699 else if (immlo == (immlo & 0x00ff0000))
8700 {
8701 *immbits = immlo >> 16;
8702 return 0x4;
8703 }
8704 else if (immlo == (immlo & 0xff000000))
8705 {
8706 *immbits = immlo >> 24;
8707 return 0x6;
8708 }
8709 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
8710 {
8711 *immbits = (immlo >> 8) & 0xff;
8712 return 0xc;
8713 }
8714 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
8715 {
8716 *immbits = (immlo >> 16) & 0xff;
8717 return 0xd;
8718 }
8719
8720 if ((immlo & 0xffff) != (immlo >> 16))
8721 return FAIL;
8722 immlo &= 0xffff;
09d92015 8723 }
a737bd4d 8724
8335d6aa 8725 if (size >= 16)
4962c51a 8726 {
8335d6aa
JW		 8727 if (immlo == (immlo & 0x000000ff))
8728 {
8729 *immbits = immlo;
8730 return 0x8;
8731 }
8732 else if (immlo == (immlo & 0x0000ff00))
8733 {
8734 *immbits = immlo >> 8;
8735 return 0xa;
8736 }
8737
8738 if ((immlo & 0xff) != (immlo >> 8))
8739 return FAIL;
8740 immlo &= 0xff;
4962c51a
MS		 8741 }
8742
8335d6aa
JW		 8743 if (immlo == (immlo & 0x000000ff))
8744 {
8745 /* Don't allow MVN with 8-bit immediate. */
8746 if (*op == 1)
8747 return FAIL;
8748 *immbits = immlo;
8749 return 0xe;
8750 }
26d97720 8751
8335d6aa 8752 return FAIL;
c19d1205 8753}
a737bd4d 8754
5fc177c8 8755#if defined BFD_HOST_64_BIT
ba592044
AM		 8756/* Returns TRUE if double precision value V may be cast
8757 to single precision without loss of accuracy. */
8758
8759static bfd_boolean
5fc177c8 8760is_double_a_single (bfd_int64_t v)
ba592044 8761{
5fc177c8 8762 int exp = (int)((v >> 52) & 0x7FF);
8fe3f3d6 8763 bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL);
ba592044
AM		 8764
8765 return (exp == 0 || exp == 0x7FF
8766 || (exp >= 1023 - 126 && exp <= 1023 + 127))
8767 && (mantissa & 0x1FFFFFFFl) == 0;
8768}
8769
3739860c 8770/* Returns a double precision value casted to single precision
ba592044
AM		 8771 (ignoring the least significant bits in exponent and mantissa). */
8772
8773static int
5fc177c8 8774double_to_single (bfd_int64_t v)
ba592044
AM		 8775{
8776 int sign = (int) ((v >> 63) & 1l);
5fc177c8 8777 int exp = (int) ((v >> 52) & 0x7FF);
8fe3f3d6 8778 bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL);
ba592044
AM		 8779
8780 if (exp == 0x7FF)
8781 exp = 0xFF;
8782 else
8783 {
8784 exp = exp - 1023 + 127;
8785 if (exp >= 0xFF)
8786 {
8787 /* Infinity. */
8788 exp = 0x7F;
8789 mantissa = 0;
8790 }
8791 else if (exp < 0)
8792 {
8793 /* No denormalized numbers. */
8794 exp = 0;
8795 mantissa = 0;
8796 }
8797 }
8798 mantissa >>= 29;
8799 return (sign << 31) | (exp << 23) | mantissa;
8800}
5fc177c8 8801#endif /* BFD_HOST_64_BIT */
ba592044 8802
8335d6aa
JW		 8803enum lit_type
8804{
8805 CONST_THUMB,
8806 CONST_ARM,
8807 CONST_VEC
8808};
8809
ba592044
AM		 8810static void do_vfp_nsyn_opcode (const char *);
8811
e2b0ab59 8812/* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
c19d1205
ZW		 8813 Determine whether it can be performed with a move instruction; if
8814 it can, convert inst.instruction to that move instruction and
c921be7d
NC		 8815 return TRUE; if it can't, convert inst.instruction to a literal-pool
8816 load and return FALSE. If this is not a valid thing to do in the
8817 current context, set inst.error and return TRUE.
a737bd4d 8818
c19d1205
ZW		 8819 inst.operands[i] describes the destination register. */
8820
c921be7d 8821static bfd_boolean
8335d6aa 8822move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
c19d1205 8823{
53365c0d 8824 unsigned long tbit;
8335d6aa
JW		 8825 bfd_boolean thumb_p = (t == CONST_THUMB);
8826 bfd_boolean arm_p = (t == CONST_ARM);
53365c0d
PB		 8827
8828 if (thumb_p)
8829 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
8830 else
8831 tbit = LOAD_BIT;
8832
8833 if ((inst.instruction & tbit) == 0)
09d92015 8834 {
c19d1205 8835 inst.error = _("invalid pseudo operation");
c921be7d 8836 return TRUE;
09d92015 8837 }
ba592044 8838
e2b0ab59
AV		 8839 if (inst.relocs[0].exp.X_op != O_constant
8840 && inst.relocs[0].exp.X_op != O_symbol
8841 && inst.relocs[0].exp.X_op != O_big)
09d92015
MM		 8842 {
8843 inst.error = _("constant expression expected");
c921be7d 8844 return TRUE;
09d92015 8845 }
ba592044 8846
e2b0ab59
AV		 8847 if (inst.relocs[0].exp.X_op == O_constant
8848 || inst.relocs[0].exp.X_op == O_big)
8335d6aa 8849 {
5fc177c8
NC		 8850#if defined BFD_HOST_64_BIT
8851 bfd_int64_t v;
8852#else
ba592044 8853 offsetT v;
5fc177c8 8854#endif
e2b0ab59 8855 if (inst.relocs[0].exp.X_op == O_big)
8335d6aa 8856 {
ba592044
AM		 8857 LITTLENUM_TYPE w[X_PRECISION];
8858 LITTLENUM_TYPE * l;
8859
e2b0ab59 8860 if (inst.relocs[0].exp.X_add_number == -1)
8335d6aa 8861 {
ba592044
AM		 8862 gen_to_words (w, X_PRECISION, E_PRECISION);
8863 l = w;
8864 /* FIXME: Should we check words w[2..5] ? */
8335d6aa 8865 }
ba592044
AM		 8866 else
8867 l = generic_bignum;
3739860c 8868
5fc177c8
NC		 8869#if defined BFD_HOST_64_BIT
8870 v =
8871 ((((((((bfd_int64_t) l[3] & LITTLENUM_MASK)
8872 << LITTLENUM_NUMBER_OF_BITS)
8873 | ((bfd_int64_t) l[2] & LITTLENUM_MASK))
8874 << LITTLENUM_NUMBER_OF_BITS)
8875 | ((bfd_int64_t) l[1] & LITTLENUM_MASK))
8876 << LITTLENUM_NUMBER_OF_BITS)
8877 | ((bfd_int64_t) l[0] & LITTLENUM_MASK));
8878#else
ba592044
AM		 8879 v = ((l[1] & LITTLENUM_MASK) << LITTLENUM_NUMBER_OF_BITS)
8880 | (l[0] & LITTLENUM_MASK);
5fc177c8 8881#endif
8335d6aa 8882 }
ba592044 8883 else
e2b0ab59 8884 v = inst.relocs[0].exp.X_add_number;
ba592044
AM		 8885
8886 if (!inst.operands[i].issingle)
8335d6aa 8887 {
12569877 8888 if (thumb_p)
8335d6aa 8889 {
53445554
TP		 8890 /* LDR should not use lead in a flag-setting instruction being
8891 chosen so we do not check whether movs can be used. */
12569877 8892
53445554 8893 if ((ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
ff8646ee 8894 || ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
53445554
TP		 8895 && inst.operands[i].reg != 13
8896 && inst.operands[i].reg != 15)
12569877 8897 {
fc289b0a
TP		 8898 /* Check if on thumb2 it can be done with a mov.w, mvn or
8899 movw instruction. */
12569877
AM		 8900 unsigned int newimm;
8901 bfd_boolean isNegated;
8902
8903 newimm = encode_thumb32_immediate (v);
8904 if (newimm != (unsigned int) FAIL)
8905 isNegated = FALSE;
8906 else
8907 {
582cfe03 8908 newimm = encode_thumb32_immediate (~v);
12569877
AM		 8909 if (newimm != (unsigned int) FAIL)
8910 isNegated = TRUE;
8911 }
8912
fc289b0a
TP		 8913 /* The number can be loaded with a mov.w or mvn
8914 instruction. */
ff8646ee
TP		 8915 if (newimm != (unsigned int) FAIL
8916 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
12569877 8917 {
fc289b0a 8918 inst.instruction = (0xf04f0000 /* MOV.W. */
582cfe03 8919 | (inst.operands[i].reg << 8));
fc289b0a 8920 /* Change to MOVN. */
582cfe03 8921 inst.instruction |= (isNegated ? 0x200000 : 0);
12569877
AM		 8922 inst.instruction |= (newimm & 0x800) << 15;
8923 inst.instruction |= (newimm & 0x700) << 4;
8924 inst.instruction |= (newimm & 0x0ff);
8925 return TRUE;
8926 }
fc289b0a 8927 /* The number can be loaded with a movw instruction. */
ff8646ee
TP		 8928 else if ((v & ~0xFFFF) == 0
8929 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
3739860c 8930 {
582cfe03 8931 int imm = v & 0xFFFF;
12569877 8932
582cfe03 8933 inst.instruction = 0xf2400000; /* MOVW. */
12569877
AM		 8934 inst.instruction |= (inst.operands[i].reg << 8);
8935 inst.instruction |= (imm & 0xf000) << 4;
8936 inst.instruction |= (imm & 0x0800) << 15;
8937 inst.instruction |= (imm & 0x0700) << 4;
8938 inst.instruction |= (imm & 0x00ff);
8fe9a076
AV		 8939 /* In case this replacement is being done on Armv8-M
8940 Baseline we need to make sure to disable the
8941 instruction size check, as otherwise GAS will reject
8942 the use of this T32 instruction. */
8943 inst.size_req = 0;
12569877
AM		 8944 return TRUE;
8945 }
8946 }
8335d6aa 8947 }
12569877 8948 else if (arm_p)
ba592044
AM		 8949 {
8950 int value = encode_arm_immediate (v);
12569877 8951
ba592044
AM		 8952 if (value != FAIL)
8953 {
8954 /* This can be done with a mov instruction. */
8955 inst.instruction &= LITERAL_MASK;
8956 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
8957 inst.instruction |= value & 0xfff;
8958 return TRUE;
8959 }
8335d6aa 8960
ba592044
AM		 8961 value = encode_arm_immediate (~ v);
8962 if (value != FAIL)
8963 {
8964 /* This can be done with a mvn instruction. */
8965 inst.instruction &= LITERAL_MASK;
8966 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
8967 inst.instruction |= value & 0xfff;
8968 return TRUE;
8969 }
8970 }
934c2632 8971 else if (t == CONST_VEC && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
8335d6aa 8972 {
ba592044
AM		 8973 int op = 0;
8974 unsigned immbits = 0;
8975 unsigned immlo = inst.operands[1].imm;
8976 unsigned immhi = inst.operands[1].regisimm
8977 ? inst.operands[1].reg
e2b0ab59 8978 : inst.relocs[0].exp.X_unsigned
ba592044
AM		 8979 ? 0
8980 : ((bfd_int64_t)((int) immlo)) >> 32;
8981 int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
8982 &op, 64, NT_invtype);
8983
8984 if (cmode == FAIL)
8985 {
8986 neon_invert_size (&immlo, &immhi, 64);
8987 op = !op;
8988 cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
8989 &op, 64, NT_invtype);
8990 }
8991
8992 if (cmode != FAIL)
8993 {
8994 inst.instruction = (inst.instruction & VLDR_VMOV_SAME)
8995 | (1 << 23)
8996 | (cmode << 8)
8997 | (op << 5)
8998 | (1 << 4);
8999
9000 /* Fill other bits in vmov encoding for both thumb and arm. */
9001 if (thumb_mode)
eff0bc54 9002 inst.instruction |= (0x7U << 29) | (0xF << 24);
ba592044 9003 else
eff0bc54 9004 inst.instruction |= (0xFU << 28) | (0x1 << 25);
ba592044
AM		 9005 neon_write_immbits (immbits);
9006 return TRUE;
9007 }
8335d6aa
JW		 9008 }
9009 }
8335d6aa 9010
ba592044
AM		 9011 if (t == CONST_VEC)
9012 {
9013 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
9014 if (inst.operands[i].issingle
9015 && is_quarter_float (inst.operands[1].imm)
9016 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3xd))
8335d6aa 9017 {
ba592044
AM		 9018 inst.operands[1].imm =
9019 neon_qfloat_bits (v);
9020 do_vfp_nsyn_opcode ("fconsts");
9021 return TRUE;
8335d6aa 9022 }
5fc177c8
NC		 9023
9024 /* If our host does not support a 64-bit type then we cannot perform
9025 the following optimization. This mean that there will be a
9026 discrepancy between the output produced by an assembler built for
9027 a 32-bit-only host and the output produced from a 64-bit host, but
9028 this cannot be helped. */
9029#if defined BFD_HOST_64_BIT
ba592044
AM		 9030 else if (!inst.operands[1].issingle
9031 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
8335d6aa 9032 {
ba592044
AM		 9033 if (is_double_a_single (v)
9034 && is_quarter_float (double_to_single (v)))
9035 {
9036 inst.operands[1].imm =
9037 neon_qfloat_bits (double_to_single (v));
9038 do_vfp_nsyn_opcode ("fconstd");
9039 return TRUE;
9040 }
8335d6aa 9041 }
5fc177c8 9042#endif
8335d6aa
JW		 9043 }
9044 }
9045
9046 if (add_to_lit_pool ((!inst.operands[i].isvec
9047 || inst.operands[i].issingle) ? 4 : 8) == FAIL)
9048 return TRUE;
9049
9050 inst.operands[1].reg = REG_PC;
9051 inst.operands[1].isreg = 1;
9052 inst.operands[1].preind = 1;
e2b0ab59
AV		 9053 inst.relocs[0].pc_rel = 1;
9054 inst.relocs[0].type = (thumb_p
8335d6aa
JW		 9055 ? BFD_RELOC_ARM_THUMB_OFFSET
9056 : (mode_3
9057 ? BFD_RELOC_ARM_HWLITERAL
9058 : BFD_RELOC_ARM_LITERAL));
9059 return FALSE;
9060}
9061
9062/* inst.operands[i] was set up by parse_address. Encode it into an
9063 ARM-format instruction. Reject all forms which cannot be encoded
9064 into a coprocessor load/store instruction. If wb_ok is false,
9065 reject use of writeback; if unind_ok is false, reject use of
9066 unindexed addressing. If reloc_override is not 0, use it instead
9067 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
9068 (in which case it is preserved). */
9069
9070static int
9071encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
9072{
9073 if (!inst.operands[i].isreg)
9074 {
99b2a2dd
NC		 9075 /* PR 18256 */
9076 if (! inst.operands[0].isvec)
9077 {
9078 inst.error = _("invalid co-processor operand");
9079 return FAIL;
9080 }
8335d6aa
JW		 9081 if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/FALSE))
9082 return SUCCESS;
9083 }
9084
9085 inst.instruction |= inst.operands[i].reg << 16;
9086
9087 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
9088
9089 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
9090 {
9091 gas_assert (!inst.operands[i].writeback);
9092 if (!unind_ok)
9093 {
9094 inst.error = _("instruction does not support unindexed addressing");
9095 return FAIL;
9096 }
9097 inst.instruction |= inst.operands[i].imm;
9098 inst.instruction |= INDEX_UP;
9099 return SUCCESS;
9100 }
9101
9102 if (inst.operands[i].preind)
9103 inst.instruction |= PRE_INDEX;
9104
9105 if (inst.operands[i].writeback)
09d92015 9106 {
8335d6aa 9107 if (inst.operands[i].reg == REG_PC)
c19d1205 9108 {
8335d6aa
JW		 9109 inst.error = _("pc may not be used with write-back");
9110 return FAIL;
c19d1205 9111 }
8335d6aa 9112 if (!wb_ok)
c19d1205 9113 {
8335d6aa
JW		 9114 inst.error = _("instruction does not support writeback");
9115 return FAIL;
c19d1205 9116 }
8335d6aa 9117 inst.instruction |= WRITE_BACK;
09d92015
MM		 9118 }
9119
8335d6aa 9120 if (reloc_override)
e2b0ab59
AV		 9121 inst.relocs[0].type = (bfd_reloc_code_real_type) reloc_override;
9122 else if ((inst.relocs[0].type < BFD_RELOC_ARM_ALU_PC_G0_NC
9123 || inst.relocs[0].type > BFD_RELOC_ARM_LDC_SB_G2)
9124 && inst.relocs[0].type != BFD_RELOC_ARM_LDR_PC_G0)
c19d1205 9125 {
8335d6aa 9126 if (thumb_mode)
e2b0ab59 9127 inst.relocs[0].type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
8335d6aa 9128 else
e2b0ab59 9129 inst.relocs[0].type = BFD_RELOC_ARM_CP_OFF_IMM;
c19d1205 9130 }
8335d6aa
JW		 9131
9132 /* Prefer + for zero encoded value. */
9133 if (!inst.operands[i].negative)
9134 inst.instruction |= INDEX_UP;
9135
9136 return SUCCESS;
09d92015
MM		 9137}
9138
5f4273c7 9139/* Functions for instruction encoding, sorted by sub-architecture.
c19d1205
ZW		 9140 First some generics; their names are taken from the conventional
9141 bit positions for register arguments in ARM format instructions. */
09d92015 9142
a737bd4d 9143static void
c19d1205 9144do_noargs (void)
09d92015 9145{
c19d1205 9146}
a737bd4d 9147
c19d1205
ZW		 9148static void
9149do_rd (void)
9150{
9151 inst.instruction |= inst.operands[0].reg << 12;
9152}
a737bd4d 9153
16a1fa25
TP		 9154static void
9155do_rn (void)
9156{
9157 inst.instruction |= inst.operands[0].reg << 16;
9158}
9159
c19d1205
ZW		 9160static void
9161do_rd_rm (void)
9162{
9163 inst.instruction |= inst.operands[0].reg << 12;
9164 inst.instruction |= inst.operands[1].reg;
9165}
09d92015 9166
9eb6c0f1
MGD		 9167static void
9168do_rm_rn (void)
9169{
9170 inst.instruction |= inst.operands[0].reg;
9171 inst.instruction |= inst.operands[1].reg << 16;
9172}
9173
c19d1205
ZW		 9174static void
9175do_rd_rn (void)
9176{
9177 inst.instruction |= inst.operands[0].reg << 12;
9178 inst.instruction |= inst.operands[1].reg << 16;
9179}
a737bd4d 9180
c19d1205
ZW		 9181static void
9182do_rn_rd (void)
9183{
9184 inst.instruction |= inst.operands[0].reg << 16;
9185 inst.instruction |= inst.operands[1].reg << 12;
9186}
09d92015 9187
4ed7ed8d
TP		 9188static void
9189do_tt (void)
9190{
9191 inst.instruction |= inst.operands[0].reg << 8;
9192 inst.instruction |= inst.operands[1].reg << 16;
9193}
9194
59d09be6
MGD		 9195static bfd_boolean
9196check_obsolete (const arm_feature_set *feature, const char *msg)
9197{
9198 if (ARM_CPU_IS_ANY (cpu_variant))
9199 {
5c3696f8 9200 as_tsktsk ("%s", msg);
59d09be6
MGD		 9201 return TRUE;
9202 }
9203 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
9204 {
9205 as_bad ("%s", msg);
9206 return TRUE;
9207 }
9208
9209 return FALSE;
9210}
9211
c19d1205
ZW		 9212static void
9213do_rd_rm_rn (void)
9214{
9a64e435 9215 unsigned Rn = inst.operands[2].reg;
708587a4 9216 /* Enforce restrictions on SWP instruction. */
9a64e435 9217 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
56adecf4
DG		 9218 {
9219 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
9220 _("Rn must not overlap other operands"));
9221
59d09be6
MGD		 9222 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
9223 */
9224 if (!check_obsolete (&arm_ext_v8,
9225 _("swp{b} use is obsoleted for ARMv8 and later"))
9226 && warn_on_deprecated
9227 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
5c3696f8 9228 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
56adecf4 9229 }
59d09be6 9230
c19d1205
ZW		 9231 inst.instruction |= inst.operands[0].reg << 12;
9232 inst.instruction |= inst.operands[1].reg;
9a64e435 9233 inst.instruction |= Rn << 16;
c19d1205 9234}
09d92015 9235
c19d1205
ZW		 9236static void
9237do_rd_rn_rm (void)
9238{
9239 inst.instruction |= inst.operands[0].reg << 12;
9240 inst.instruction |= inst.operands[1].reg << 16;
9241 inst.instruction |= inst.operands[2].reg;
9242}
a737bd4d 9243
c19d1205
ZW		 9244static void
9245do_rm_rd_rn (void)
9246{
5be8be5d 9247 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
e2b0ab59
AV		 9248 constraint (((inst.relocs[0].exp.X_op != O_constant
9249 && inst.relocs[0].exp.X_op != O_illegal)
9250 || inst.relocs[0].exp.X_add_number != 0),
5be8be5d 9251 BAD_ADDR_MODE);
c19d1205
ZW		 9252 inst.instruction |= inst.operands[0].reg;
9253 inst.instruction |= inst.operands[1].reg << 12;
9254 inst.instruction |= inst.operands[2].reg << 16;
9255}
09d92015 9256
c19d1205
ZW		 9257static void
9258do_imm0 (void)
9259{
9260 inst.instruction |= inst.operands[0].imm;
9261}
09d92015 9262
c19d1205
ZW		 9263static void
9264do_rd_cpaddr (void)
9265{
9266 inst.instruction |= inst.operands[0].reg << 12;
9267 encode_arm_cp_address (1, TRUE, TRUE, 0);
09d92015 9268}
a737bd4d 9269
c19d1205
ZW		 9270/* ARM instructions, in alphabetical order by function name (except
9271 that wrapper functions appear immediately after the function they
9272 wrap). */
09d92015 9273
c19d1205
ZW		 9274/* This is a pseudo-op of the form "adr rd, label" to be converted
9275 into a relative address of the form "add rd, pc, #label-.-8". */
09d92015
MM		 9276
9277static void
c19d1205 9278do_adr (void)
09d92015 9279{
c19d1205 9280 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
a737bd4d 9281
c19d1205
ZW		 9282 /* Frag hacking will turn this into a sub instruction if the offset turns
9283 out to be negative. */
e2b0ab59
AV		 9284 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
9285 inst.relocs[0].pc_rel = 1;
9286 inst.relocs[0].exp.X_add_number -= 8;
52a86f84 9287
fc6141f0 9288 if (support_interwork
e2b0ab59
AV		 9289 && inst.relocs[0].exp.X_op == O_symbol
9290 && inst.relocs[0].exp.X_add_symbol != NULL
9291 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
9292 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
9293 inst.relocs[0].exp.X_add_number |= 1;
c19d1205 9294}
b99bd4ef 9295
c19d1205
ZW		 9296/* This is a pseudo-op of the form "adrl rd, label" to be converted
9297 into a relative address of the form:
9298 add rd, pc, #low(label-.-8)"
9299 add rd, rd, #high(label-.-8)" */
b99bd4ef 9300
c19d1205
ZW		 9301static void
9302do_adrl (void)
9303{
9304 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
a737bd4d 9305
c19d1205
ZW		 9306 /* Frag hacking will turn this into a sub instruction if the offset turns
9307 out to be negative. */
e2b0ab59
AV		 9308 inst.relocs[0].type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
9309 inst.relocs[0].pc_rel = 1;
c19d1205 9310 inst.size = INSN_SIZE * 2;
e2b0ab59 9311 inst.relocs[0].exp.X_add_number -= 8;
52a86f84 9312
fc6141f0 9313 if (support_interwork
e2b0ab59
AV		 9314 && inst.relocs[0].exp.X_op == O_symbol
9315 && inst.relocs[0].exp.X_add_symbol != NULL
9316 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
9317 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
9318 inst.relocs[0].exp.X_add_number |= 1;
b99bd4ef
NC		 9319}
9320
b99bd4ef 9321static void
c19d1205 9322do_arit (void)
b99bd4ef 9323{
e2b0ab59
AV		 9324 constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9325 && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
a9f02af8 9326 THUMB1_RELOC_ONLY);
c19d1205
ZW		 9327 if (!inst.operands[1].present)
9328 inst.operands[1].reg = inst.operands[0].reg;
9329 inst.instruction |= inst.operands[0].reg << 12;
9330 inst.instruction |= inst.operands[1].reg << 16;
9331 encode_arm_shifter_operand (2);
9332}
b99bd4ef 9333
62b3e311
PB		 9334static void
9335do_barrier (void)
9336{
9337 if (inst.operands[0].present)
ccb84d65 9338 inst.instruction |= inst.operands[0].imm;
62b3e311
PB		 9339 else
9340 inst.instruction |= 0xf;
9341}
9342
c19d1205
ZW		 9343static void
9344do_bfc (void)
9345{
9346 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
9347 constraint (msb > 32, _("bit-field extends past end of register"));
9348 /* The instruction encoding stores the LSB and MSB,
9349 not the LSB and width. */
9350 inst.instruction |= inst.operands[0].reg << 12;
9351 inst.instruction |= inst.operands[1].imm << 7;
9352 inst.instruction |= (msb - 1) << 16;
9353}
b99bd4ef 9354
c19d1205
ZW		 9355static void
9356do_bfi (void)
9357{
9358 unsigned int msb;
b99bd4ef 9359
c19d1205
ZW		 9360 /* #0 in second position is alternative syntax for bfc, which is
9361 the same instruction but with REG_PC in the Rm field. */
9362 if (!inst.operands[1].isreg)
9363 inst.operands[1].reg = REG_PC;
b99bd4ef 9364
c19d1205
ZW		 9365 msb = inst.operands[2].imm + inst.operands[3].imm;
9366 constraint (msb > 32, _("bit-field extends past end of register"));
9367 /* The instruction encoding stores the LSB and MSB,
9368 not the LSB and width. */
9369 inst.instruction |= inst.operands[0].reg << 12;
9370 inst.instruction |= inst.operands[1].reg;
9371 inst.instruction |= inst.operands[2].imm << 7;
9372 inst.instruction |= (msb - 1) << 16;
b99bd4ef
NC		 9373}
9374
b99bd4ef 9375static void
c19d1205 9376do_bfx (void)
b99bd4ef 9377{
c19d1205
ZW		 9378 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
9379 _("bit-field extends past end of register"));
9380 inst.instruction |= inst.operands[0].reg << 12;
9381 inst.instruction |= inst.operands[1].reg;
9382 inst.instruction |= inst.operands[2].imm << 7;
9383 inst.instruction |= (inst.operands[3].imm - 1) << 16;
9384}
09d92015 9385
c19d1205
ZW		 9386/* ARM V5 breakpoint instruction (argument parse)
9387 BKPT <16 bit unsigned immediate>
9388 Instruction is not conditional.
9389 The bit pattern given in insns[] has the COND_ALWAYS condition,
9390 and it is an error if the caller tried to override that. */
b99bd4ef 9391
c19d1205
ZW		 9392static void
9393do_bkpt (void)
9394{
9395 /* Top 12 of 16 bits to bits 19:8. */
9396 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
09d92015 9397
c19d1205
ZW		 9398 /* Bottom 4 of 16 bits to bits 3:0. */
9399 inst.instruction |= inst.operands[0].imm & 0xf;
9400}
09d92015 9401
c19d1205
ZW		 9402static void
9403encode_branch (int default_reloc)
9404{
9405 if (inst.operands[0].hasreloc)
9406 {
0855e32b
NS		 9407 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
9408 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
9409 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
e2b0ab59 9410 inst.relocs[0].type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
0855e32b
NS		 9411 ? BFD_RELOC_ARM_PLT32
9412 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
c19d1205 9413 }
b99bd4ef 9414 else
e2b0ab59
AV		 9415 inst.relocs[0].type = (bfd_reloc_code_real_type) default_reloc;
9416 inst.relocs[0].pc_rel = 1;
b99bd4ef
NC		 9417}
9418
b99bd4ef 9419static void
c19d1205 9420do_branch (void)
b99bd4ef 9421{
39b41c9c
PB		 9422#ifdef OBJ_ELF
9423 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
9424 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
9425 else
9426#endif
9427 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
9428}
9429
9430static void
9431do_bl (void)
9432{
9433#ifdef OBJ_ELF
9434 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
9435 {
9436 if (inst.cond == COND_ALWAYS)
9437 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
9438 else
9439 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
9440 }
9441 else
9442#endif
9443 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
c19d1205 9444}
b99bd4ef 9445
c19d1205
ZW		 9446/* ARM V5 branch-link-exchange instruction (argument parse)
9447 BLX <target_addr> ie BLX(1)
9448 BLX{<condition>} <Rm> ie BLX(2)
9449 Unfortunately, there are two different opcodes for this mnemonic.
9450 So, the insns[].value is not used, and the code here zaps values
9451 into inst.instruction.
9452 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
b99bd4ef 9453
c19d1205
ZW		 9454static void
9455do_blx (void)
9456{
9457 if (inst.operands[0].isreg)
b99bd4ef 9458 {
c19d1205
ZW		 9459 /* Arg is a register; the opcode provided by insns[] is correct.
9460 It is not illegal to do "blx pc", just useless. */
9461 if (inst.operands[0].reg == REG_PC)
9462 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
b99bd4ef 9463
c19d1205
ZW		 9464 inst.instruction |= inst.operands[0].reg;
9465 }
9466 else
b99bd4ef 9467 {
c19d1205 9468 /* Arg is an address; this instruction cannot be executed
267bf995
RR		 9469 conditionally, and the opcode must be adjusted.
9470 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9471 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
c19d1205 9472 constraint (inst.cond != COND_ALWAYS, BAD_COND);
2fc8bdac 9473 inst.instruction = 0xfa000000;
267bf995 9474 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
b99bd4ef 9475 }
c19d1205
ZW		 9476}
9477
9478static void
9479do_bx (void)
9480{
845b51d6
PB		 9481 bfd_boolean want_reloc;
9482
c19d1205
ZW		 9483 if (inst.operands[0].reg == REG_PC)
9484 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
b99bd4ef 9485
c19d1205 9486 inst.instruction |= inst.operands[0].reg;
845b51d6
PB		 9487 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9488 it is for ARMv4t or earlier. */
9489 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
4d354d8b
TP		 9490 if (!ARM_FEATURE_ZERO (selected_object_arch)
9491 && !ARM_CPU_HAS_FEATURE (selected_object_arch, arm_ext_v5))
845b51d6
PB		 9492 want_reloc = TRUE;
9493
5ad34203 9494#ifdef OBJ_ELF
845b51d6 9495 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
5ad34203 9496#endif
584206db 9497 want_reloc = FALSE;
845b51d6
PB		 9498
9499 if (want_reloc)
e2b0ab59 9500 inst.relocs[0].type = BFD_RELOC_ARM_V4BX;
09d92015
MM		 9501}
9502
c19d1205
ZW		 9503
9504/* ARM v5TEJ. Jump to Jazelle code. */
a737bd4d
NC		 9505
9506static void
c19d1205 9507do_bxj (void)
a737bd4d 9508{
c19d1205
ZW		 9509 if (inst.operands[0].reg == REG_PC)
9510 as_tsktsk (_("use of r15 in bxj is not really useful"));
9511
9512 inst.instruction |= inst.operands[0].reg;
a737bd4d
NC		 9513}
9514
c19d1205
ZW		 9515/* Co-processor data operation:
9516 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9517 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9518static void
9519do_cdp (void)
9520{
9521 inst.instruction |= inst.operands[0].reg << 8;
9522 inst.instruction |= inst.operands[1].imm << 20;
9523 inst.instruction |= inst.operands[2].reg << 12;
9524 inst.instruction |= inst.operands[3].reg << 16;
9525 inst.instruction |= inst.operands[4].reg;
9526 inst.instruction |= inst.operands[5].imm << 5;
9527}
a737bd4d
NC		 9528
9529static void
c19d1205 9530do_cmp (void)
a737bd4d 9531{
c19d1205
ZW		 9532 inst.instruction |= inst.operands[0].reg << 16;
9533 encode_arm_shifter_operand (1);
a737bd4d
NC		 9534}
9535
c19d1205
ZW		 9536/* Transfer between coprocessor and ARM registers.
9537 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9538 MRC2
9539 MCR{cond}
9540 MCR2
9541
9542 No special properties. */
09d92015 9543
dcbd0d71
MGD		 9544struct deprecated_coproc_regs_s
9545{
9546 unsigned cp;
9547 int opc1;
9548 unsigned crn;
9549 unsigned crm;
9550 int opc2;
9551 arm_feature_set deprecated;
9552 arm_feature_set obsoleted;
9553 const char *dep_msg;
9554 const char *obs_msg;
9555};
9556
9557#define DEPR_ACCESS_V8 \
9558 N_("This coprocessor register access is deprecated in ARMv8")
9559
9560/* Table of all deprecated coprocessor registers. */
9561static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
9562{
9563 {15, 0, 7, 10, 5, /* CP15DMB. */
823d2571 9564 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
dcbd0d71
MGD		 9565 DEPR_ACCESS_V8, NULL},
9566 {15, 0, 7, 10, 4, /* CP15DSB. */
823d2571 9567 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
dcbd0d71
MGD		 9568 DEPR_ACCESS_V8, NULL},
9569 {15, 0, 7, 5, 4, /* CP15ISB. */
823d2571 9570 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
dcbd0d71
MGD		 9571 DEPR_ACCESS_V8, NULL},
9572 {14, 6, 1, 0, 0, /* TEEHBR. */
823d2571 9573 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
dcbd0d71
MGD		 9574 DEPR_ACCESS_V8, NULL},
9575 {14, 6, 0, 0, 0, /* TEECR. */
823d2571 9576 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
dcbd0d71
MGD		 9577 DEPR_ACCESS_V8, NULL},
9578};
9579
9580#undef DEPR_ACCESS_V8
9581
9582static const size_t deprecated_coproc_reg_count =
9583 sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
9584
09d92015 9585static void
c19d1205 9586do_co_reg (void)
09d92015 9587{
fdfde340 9588 unsigned Rd;
dcbd0d71 9589 size_t i;
fdfde340
JM		 9590
9591 Rd = inst.operands[2].reg;
9592 if (thumb_mode)
9593 {
9594 if (inst.instruction == 0xee000010
9595 || inst.instruction == 0xfe000010)
9596 /* MCR, MCR2 */
9597 reject_bad_reg (Rd);
5c8ed6a4 9598 else if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
fdfde340
JM		 9599 /* MRC, MRC2 */
9600 constraint (Rd == REG_SP, BAD_SP);
9601 }
9602 else
9603 {
9604 /* MCR */
9605 if (inst.instruction == 0xe000010)
9606 constraint (Rd == REG_PC, BAD_PC);
9607 }
9608
dcbd0d71
MGD		 9609 for (i = 0; i < deprecated_coproc_reg_count; ++i)
9610 {
9611 const struct deprecated_coproc_regs_s *r =
9612 deprecated_coproc_regs + i;
9613
9614 if (inst.operands[0].reg == r->cp
9615 && inst.operands[1].imm == r->opc1
9616 && inst.operands[3].reg == r->crn
9617 && inst.operands[4].reg == r->crm
9618 && inst.operands[5].imm == r->opc2)
9619 {
b10bf8c5 9620 if (! ARM_CPU_IS_ANY (cpu_variant)
477330fc 9621 && warn_on_deprecated
dcbd0d71 9622 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
5c3696f8 9623 as_tsktsk ("%s", r->dep_msg);
dcbd0d71
MGD		 9624 }
9625 }
fdfde340 9626
c19d1205
ZW		 9627 inst.instruction |= inst.operands[0].reg << 8;
9628 inst.instruction |= inst.operands[1].imm << 21;
fdfde340 9629 inst.instruction |= Rd << 12;
c19d1205
ZW		 9630 inst.instruction |= inst.operands[3].reg << 16;
9631 inst.instruction |= inst.operands[4].reg;
9632 inst.instruction |= inst.operands[5].imm << 5;
9633}
09d92015 9634
c19d1205
ZW		 9635/* Transfer between coprocessor register and pair of ARM registers.
9636 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9637 MCRR2
9638 MRRC{cond}
9639 MRRC2
b99bd4ef 9640
c19d1205 9641 Two XScale instructions are special cases of these:
09d92015 9642
c19d1205
ZW		 9643 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9644 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
b99bd4ef 9645
5f4273c7 9646 Result unpredictable if Rd or Rn is R15. */
a737bd4d 9647
c19d1205
ZW		 9648static void
9649do_co_reg2c (void)
9650{
fdfde340
JM		 9651 unsigned Rd, Rn;
9652
9653 Rd = inst.operands[2].reg;
9654 Rn = inst.operands[3].reg;
9655
9656 if (thumb_mode)
9657 {
9658 reject_bad_reg (Rd);
9659 reject_bad_reg (Rn);
9660 }
9661 else
9662 {
9663 constraint (Rd == REG_PC, BAD_PC);
9664 constraint (Rn == REG_PC, BAD_PC);
9665 }
9666
873f10f0
TC		 9667 /* Only check the MRRC{2} variants. */
9668 if ((inst.instruction & 0x0FF00000) == 0x0C500000)
9669 {
9670 /* If Rd == Rn, error that the operation is
9671 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9672 constraint (Rd == Rn, BAD_OVERLAP);
9673 }
9674
c19d1205
ZW		 9675 inst.instruction |= inst.operands[0].reg << 8;
9676 inst.instruction |= inst.operands[1].imm << 4;
fdfde340
JM		 9677 inst.instruction |= Rd << 12;
9678 inst.instruction |= Rn << 16;
c19d1205 9679 inst.instruction |= inst.operands[4].reg;
b99bd4ef
NC		 9680}
9681
c19d1205
ZW		 9682static void
9683do_cpsi (void)
9684{
9685 inst.instruction |= inst.operands[0].imm << 6;
a028a6f5
PB		 9686 if (inst.operands[1].present)
9687 {
9688 inst.instruction |= CPSI_MMOD;
9689 inst.instruction |= inst.operands[1].imm;
9690 }
c19d1205 9691}
b99bd4ef 9692
62b3e311
PB		 9693static void
9694do_dbg (void)
9695{
9696 inst.instruction |= inst.operands[0].imm;
9697}
9698
eea54501
MGD		 9699static void
9700do_div (void)
9701{
9702 unsigned Rd, Rn, Rm;
9703
9704 Rd = inst.operands[0].reg;
9705 Rn = (inst.operands[1].present
9706 ? inst.operands[1].reg : Rd);
9707 Rm = inst.operands[2].reg;
9708
9709 constraint ((Rd == REG_PC), BAD_PC);
9710 constraint ((Rn == REG_PC), BAD_PC);
9711 constraint ((Rm == REG_PC), BAD_PC);
9712
9713 inst.instruction |= Rd << 16;
9714 inst.instruction |= Rn << 0;
9715 inst.instruction |= Rm << 8;
9716}
9717
b99bd4ef 9718static void
c19d1205 9719do_it (void)
b99bd4ef 9720{
c19d1205 9721 /* There is no IT instruction in ARM mode. We
e07e6e58
NC		 9722 process it to do the validation as if in
9723 thumb mode, just in case the code gets
9724 assembled for thumb using the unified syntax. */
9725
c19d1205 9726 inst.size = 0;
e07e6e58
NC		 9727 if (unified_syntax)
9728 {
5ee91343
AV		 9729 set_pred_insn_type (IT_INSN);
9730 now_pred.mask = (inst.instruction & 0xf) | 0x10;
9731 now_pred.cc = inst.operands[0].imm;
e07e6e58 9732 }
09d92015 9733}
b99bd4ef 9734
6530b175
NC		 9735/* If there is only one register in the register list,
9736 then return its register number. Otherwise return -1. */
9737static int
9738only_one_reg_in_list (int range)
9739{
9740 int i = ffs (range) - 1;
9741 return (i > 15 || range != (1 << i)) ? -1 : i;
9742}
9743
09d92015 9744static void
6530b175 9745encode_ldmstm(int from_push_pop_mnem)
ea6ef066 9746{
c19d1205
ZW		 9747 int base_reg = inst.operands[0].reg;
9748 int range = inst.operands[1].imm;
6530b175 9749 int one_reg;
ea6ef066 9750
c19d1205
ZW		 9751 inst.instruction |= base_reg << 16;
9752 inst.instruction |= range;
ea6ef066 9753
c19d1205
ZW		 9754 if (inst.operands[1].writeback)
9755 inst.instruction |= LDM_TYPE_2_OR_3;
09d92015 9756
c19d1205 9757 if (inst.operands[0].writeback)
ea6ef066 9758 {
c19d1205
ZW		 9759 inst.instruction |= WRITE_BACK;
9760 /* Check for unpredictable uses of writeback. */
9761 if (inst.instruction & LOAD_BIT)
09d92015 9762 {
c19d1205
ZW		 9763 /* Not allowed in LDM type 2. */
9764 if ((inst.instruction & LDM_TYPE_2_OR_3)
9765 && ((range & (1 << REG_PC)) == 0))
9766 as_warn (_("writeback of base register is UNPREDICTABLE"));
9767 /* Only allowed if base reg not in list for other types. */
9768 else if (range & (1 << base_reg))
9769 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9770 }
9771 else /* STM. */
9772 {
9773 /* Not allowed for type 2. */
9774 if (inst.instruction & LDM_TYPE_2_OR_3)
9775 as_warn (_("writeback of base register is UNPREDICTABLE"));
9776 /* Only allowed if base reg not in list, or first in list. */
9777 else if ((range & (1 << base_reg))
9778 && (range & ((1 << base_reg) - 1)))
9779 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
09d92015 9780 }
ea6ef066 9781 }
6530b175
NC		 9782
9783 /* If PUSH/POP has only one register, then use the A2 encoding. */
9784 one_reg = only_one_reg_in_list (range);
9785 if (from_push_pop_mnem && one_reg >= 0)
9786 {
9787 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
9788
4f588891
NC		 9789 if (is_push && one_reg == 13 /* SP */)
9790 /* PR 22483: The A2 encoding cannot be used when
9791 pushing the stack pointer as this is UNPREDICTABLE. */
9792 return;
9793
6530b175
NC		 9794 inst.instruction &= A_COND_MASK;
9795 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
9796 inst.instruction |= one_reg << 12;
9797 }
9798}
9799
9800static void
9801do_ldmstm (void)
9802{
9803 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
a737bd4d
NC		 9804}
9805
c19d1205
ZW		 9806/* ARMv5TE load-consecutive (argument parse)
9807 Mode is like LDRH.
9808
9809 LDRccD R, mode
9810 STRccD R, mode. */
9811
a737bd4d 9812static void
c19d1205 9813do_ldrd (void)
a737bd4d 9814{
c19d1205 9815 constraint (inst.operands[0].reg % 2 != 0,
c56791bb 9816 _("first transfer register must be even"));
c19d1205
ZW		 9817 constraint (inst.operands[1].present
9818 && inst.operands[1].reg != inst.operands[0].reg + 1,
c56791bb 9819 _("can only transfer two consecutive registers"));
c19d1205
ZW		 9820 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
9821 constraint (!inst.operands[2].isreg, _("'[' expected"));
a737bd4d 9822
c19d1205
ZW		 9823 if (!inst.operands[1].present)
9824 inst.operands[1].reg = inst.operands[0].reg + 1;
5f4273c7 9825
c56791bb
RE		 9826 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9827 register and the first register written; we have to diagnose
9828 overlap between the base and the second register written here. */
ea6ef066 9829
c56791bb
RE		 9830 if (inst.operands[2].reg == inst.operands[1].reg
9831 && (inst.operands[2].writeback || inst.operands[2].postind))
9832 as_warn (_("base register written back, and overlaps "
9833 "second transfer register"));
b05fe5cf 9834
c56791bb
RE		 9835 if (!(inst.instruction & V4_STR_BIT))
9836 {
c19d1205 9837 /* For an index-register load, the index register must not overlap the
c56791bb
RE		 9838 destination (even if not write-back). */
9839 if (inst.operands[2].immisreg
9840 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
9841 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
9842 as_warn (_("index register overlaps transfer register"));
b05fe5cf 9843 }
c19d1205
ZW		 9844 inst.instruction |= inst.operands[0].reg << 12;
9845 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
b05fe5cf
ZW		 9846}
9847
9848static void
c19d1205 9849do_ldrex (void)
b05fe5cf 9850{
c19d1205
ZW		 9851 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
9852 || inst.operands[1].postind || inst.operands[1].writeback
9853 || inst.operands[1].immisreg || inst.operands[1].shifted
01cfc07f
NC		 9854 || inst.operands[1].negative
9855 /* This can arise if the programmer has written
9856 strex rN, rM, foo
9857 or if they have mistakenly used a register name as the last
9858 operand, eg:
9859 strex rN, rM, rX
9860 It is very difficult to distinguish between these two cases
9861 because "rX" might actually be a label. ie the register
9862 name has been occluded by a symbol of the same name. So we
9863 just generate a general 'bad addressing mode' type error
9864 message and leave it up to the programmer to discover the
9865 true cause and fix their mistake. */
9866 || (inst.operands[1].reg == REG_PC),
9867 BAD_ADDR_MODE);
b05fe5cf 9868
e2b0ab59
AV		 9869 constraint (inst.relocs[0].exp.X_op != O_constant
9870 || inst.relocs[0].exp.X_add_number != 0,
c19d1205 9871 _("offset must be zero in ARM encoding"));
b05fe5cf 9872
5be8be5d
DG		 9873 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
9874
c19d1205
ZW		 9875 inst.instruction |= inst.operands[0].reg << 12;
9876 inst.instruction |= inst.operands[1].reg << 16;
e2b0ab59 9877 inst.relocs[0].type = BFD_RELOC_UNUSED;
b05fe5cf
ZW		 9878}
9879
9880static void
c19d1205 9881do_ldrexd (void)
b05fe5cf 9882{
c19d1205
ZW		 9883 constraint (inst.operands[0].reg % 2 != 0,
9884 _("even register required"));
9885 constraint (inst.operands[1].present
9886 && inst.operands[1].reg != inst.operands[0].reg + 1,
9887 _("can only load two consecutive registers"));
9888 /* If op 1 were present and equal to PC, this function wouldn't
9889 have been called in the first place. */
9890 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
b05fe5cf 9891
c19d1205
ZW		 9892 inst.instruction |= inst.operands[0].reg << 12;
9893 inst.instruction |= inst.operands[2].reg << 16;
b05fe5cf
ZW		 9894}
9895
1be5fd2e
NC		 9896/* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9897 which is not a multiple of four is UNPREDICTABLE. */
9898static void
9899check_ldr_r15_aligned (void)
9900{
9901 constraint (!(inst.operands[1].immisreg)
9902 && (inst.operands[0].reg == REG_PC
9903 && inst.operands[1].reg == REG_PC
e2b0ab59 9904 && (inst.relocs[0].exp.X_add_number & 0x3)),
de194d85 9905 _("ldr to register 15 must be 4-byte aligned"));
1be5fd2e
NC		 9906}
9907
b05fe5cf 9908static void
c19d1205 9909do_ldst (void)
b05fe5cf 9910{
c19d1205
ZW		 9911 inst.instruction |= inst.operands[0].reg << 12;
9912 if (!inst.operands[1].isreg)
8335d6aa 9913 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/FALSE))
b05fe5cf 9914 return;
c19d1205 9915 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
1be5fd2e 9916 check_ldr_r15_aligned ();
b05fe5cf
ZW		 9917}
9918
9919static void
c19d1205 9920do_ldstt (void)
b05fe5cf 9921{
c19d1205
ZW		 9922 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9923 reject [Rn,...]. */
9924 if (inst.operands[1].preind)
b05fe5cf 9925 {
e2b0ab59
AV		 9926 constraint (inst.relocs[0].exp.X_op != O_constant
9927 || inst.relocs[0].exp.X_add_number != 0,
c19d1205 9928 _("this instruction requires a post-indexed address"));
b05fe5cf 9929
c19d1205
ZW		 9930 inst.operands[1].preind = 0;
9931 inst.operands[1].postind = 1;
9932 inst.operands[1].writeback = 1;
b05fe5cf 9933 }
c19d1205
ZW		 9934 inst.instruction |= inst.operands[0].reg << 12;
9935 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
9936}
b05fe5cf 9937
c19d1205 9938/* Halfword and signed-byte load/store operations. */
b05fe5cf 9939
c19d1205
ZW		 9940static void
9941do_ldstv4 (void)
9942{
ff4a8d2b 9943 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
c19d1205
ZW		 9944 inst.instruction |= inst.operands[0].reg << 12;
9945 if (!inst.operands[1].isreg)
8335d6aa 9946 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/TRUE))
b05fe5cf 9947 return;
c19d1205 9948 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
b05fe5cf
ZW		 9949}
9950
9951static void
c19d1205 9952do_ldsttv4 (void)
b05fe5cf 9953{
c19d1205
ZW		 9954 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9955 reject [Rn,...]. */
9956 if (inst.operands[1].preind)
b05fe5cf 9957 {
e2b0ab59
AV		 9958 constraint (inst.relocs[0].exp.X_op != O_constant
9959 || inst.relocs[0].exp.X_add_number != 0,
c19d1205 9960 _("this instruction requires a post-indexed address"));
b05fe5cf 9961
c19d1205
ZW		 9962 inst.operands[1].preind = 0;
9963 inst.operands[1].postind = 1;
9964 inst.operands[1].writeback = 1;
b05fe5cf 9965 }
c19d1205
ZW		 9966 inst.instruction |= inst.operands[0].reg << 12;
9967 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
9968}
b05fe5cf 9969
c19d1205
ZW		 9970/* Co-processor register load/store.
9971 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9972static void
9973do_lstc (void)
9974{
9975 inst.instruction |= inst.operands[0].reg << 8;
9976 inst.instruction |= inst.operands[1].reg << 12;
9977 encode_arm_cp_address (2, TRUE, TRUE, 0);
b05fe5cf
ZW		 9978}
9979
b05fe5cf 9980static void
c19d1205 9981do_mlas (void)
b05fe5cf 9982{
8fb9d7b9 9983 /* This restriction does not apply to mls (nor to mla in v6 or later). */
c19d1205 9984 if (inst.operands[0].reg == inst.operands[1].reg
8fb9d7b9 9985 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
c19d1205 9986 && !(inst.instruction & 0x00400000))
8fb9d7b9 9987 as_tsktsk (_("Rd and Rm should be different in mla"));
b05fe5cf 9988
c19d1205
ZW		 9989 inst.instruction |= inst.operands[0].reg << 16;
9990 inst.instruction |= inst.operands[1].reg;
9991 inst.instruction |= inst.operands[2].reg << 8;
9992 inst.instruction |= inst.operands[3].reg << 12;
c19d1205 9993}
b05fe5cf 9994
c19d1205
ZW		 9995static void
9996do_mov (void)
9997{
e2b0ab59
AV		 9998 constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9999 && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
a9f02af8 10000 THUMB1_RELOC_ONLY);
c19d1205
ZW		 10001 inst.instruction |= inst.operands[0].reg << 12;
10002 encode_arm_shifter_operand (1);
10003}
b05fe5cf 10004
c19d1205
ZW		 10005/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
10006static void
10007do_mov16 (void)
10008{
b6895b4f
PB		 10009 bfd_vma imm;
10010 bfd_boolean top;
10011
10012 top = (inst.instruction & 0x00400000) != 0;
e2b0ab59 10013 constraint (top && inst.relocs[0].type == BFD_RELOC_ARM_MOVW,
33eaf5de 10014 _(":lower16: not allowed in this instruction"));
e2b0ab59 10015 constraint (!top && inst.relocs[0].type == BFD_RELOC_ARM_MOVT,
33eaf5de 10016 _(":upper16: not allowed in this instruction"));
c19d1205 10017 inst.instruction |= inst.operands[0].reg << 12;
e2b0ab59 10018 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
b6895b4f 10019 {
e2b0ab59 10020 imm = inst.relocs[0].exp.X_add_number;
b6895b4f
PB		 10021 /* The value is in two pieces: 0:11, 16:19. */
10022 inst.instruction |= (imm & 0x00000fff);
10023 inst.instruction |= (imm & 0x0000f000) << 4;
10024 }
b05fe5cf 10025}
b99bd4ef 10026
037e8744
JB		 10027static int
10028do_vfp_nsyn_mrs (void)
10029{
10030 if (inst.operands[0].isvec)
10031 {
10032 if (inst.operands[1].reg != 1)
477330fc 10033 first_error (_("operand 1 must be FPSCR"));
037e8744
JB		 10034 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
10035 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
10036 do_vfp_nsyn_opcode ("fmstat");
10037 }
10038 else if (inst.operands[1].isvec)
10039 do_vfp_nsyn_opcode ("fmrx");
10040 else
10041 return FAIL;
5f4273c7 10042
037e8744
JB		 10043 return SUCCESS;
10044}
10045
10046static int
10047do_vfp_nsyn_msr (void)
10048{
10049 if (inst.operands[0].isvec)
10050 do_vfp_nsyn_opcode ("fmxr");
10051 else
10052 return FAIL;
10053
10054 return SUCCESS;
10055}
10056
f7c21dc7
NC		 10057static void
10058do_vmrs (void)
10059{
10060 unsigned Rt = inst.operands[0].reg;
fa94de6b 10061
16d02dc9 10062 if (thumb_mode && Rt == REG_SP)
f7c21dc7
NC		 10063 {
10064 inst.error = BAD_SP;
10065 return;
10066 }
10067
ba6cd17f
SD		 10068 switch (inst.operands[1].reg)
10069 {
10070 /* MVFR2 is only valid for Armv8-A. */
10071 case 5:
10072 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
10073 _(BAD_FPU));
10074 break;
10075
10076 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10077 case 1: /* fpscr. */
10078 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
10079 || ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)),
10080 _(BAD_FPU));
10081 break;
10082
10083 case 14: /* fpcxt_ns. */
10084 case 15: /* fpcxt_s. */
10085 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main),
10086 _("selected processor does not support instruction"));
10087 break;
10088
10089 case 2: /* fpscr_nzcvqc. */
10090 case 12: /* vpr. */
10091 case 13: /* p0. */
10092 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main)
10093 || (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
10094 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)),
10095 _("selected processor does not support instruction"));
10096 if (inst.operands[0].reg != 2
10097 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
10098 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10099 break;
10100
10101 default:
10102 break;
10103 }
40c7d507 10104
f7c21dc7 10105 /* APSR_ sets isvec. All other refs to PC are illegal. */
16d02dc9 10106 if (!inst.operands[0].isvec && Rt == REG_PC)
f7c21dc7
NC		 10107 {
10108 inst.error = BAD_PC;
10109 return;
10110 }
10111
16d02dc9
JB		 10112 /* If we get through parsing the register name, we just insert the number
10113 generated into the instruction without further validation. */
10114 inst.instruction |= (inst.operands[1].reg << 16);
f7c21dc7
NC		 10115 inst.instruction |= (Rt << 12);
10116}
10117
10118static void
10119do_vmsr (void)
10120{
10121 unsigned Rt = inst.operands[1].reg;
fa94de6b 10122
f7c21dc7
NC		 10123 if (thumb_mode)
10124 reject_bad_reg (Rt);
10125 else if (Rt == REG_PC)
10126 {
10127 inst.error = BAD_PC;
10128 return;
10129 }
10130
ba6cd17f
SD		 10131 switch (inst.operands[0].reg)
10132 {
10133 /* MVFR2 is only valid for Armv8-A. */
10134 case 5:
10135 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
10136 _(BAD_FPU));
10137 break;
10138
10139 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10140 case 1: /* fpcr. */
10141 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
10142 || ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)),
10143 _(BAD_FPU));
10144 break;
10145
10146 case 14: /* fpcxt_ns. */
10147 case 15: /* fpcxt_s. */
10148 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main),
10149 _("selected processor does not support instruction"));
10150 break;
10151
10152 case 2: /* fpscr_nzcvqc. */
10153 case 12: /* vpr. */
10154 case 13: /* p0. */
10155 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main)
10156 || (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
10157 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)),
10158 _("selected processor does not support instruction"));
10159 if (inst.operands[0].reg != 2
10160 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
10161 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10162 break;
10163
10164 default:
10165 break;
10166 }
40c7d507 10167
16d02dc9
JB		 10168 /* If we get through parsing the register name, we just insert the number
10169 generated into the instruction without further validation. */
10170 inst.instruction |= (inst.operands[0].reg << 16);
f7c21dc7
NC		 10171 inst.instruction |= (Rt << 12);
10172}
10173
b99bd4ef 10174static void
c19d1205 10175do_mrs (void)
b99bd4ef 10176{
90ec0d68
MGD		 10177 unsigned br;
10178
037e8744
JB		 10179 if (do_vfp_nsyn_mrs () == SUCCESS)
10180 return;
10181
ff4a8d2b 10182 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
c19d1205 10183 inst.instruction |= inst.operands[0].reg << 12;
90ec0d68
MGD		 10184
10185 if (inst.operands[1].isreg)
10186 {
10187 br = inst.operands[1].reg;
806ab1c0 10188 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf0000))
90ec0d68
MGD		 10189 as_bad (_("bad register for mrs"));
10190 }
10191 else
10192 {
10193 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10194 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
10195 != (PSR_c|PSR_f),
d2cd1205 10196 _("'APSR', 'CPSR' or 'SPSR' expected"));
90ec0d68
MGD		 10197 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
10198 }
10199
10200 inst.instruction |= br;
c19d1205 10201}
b99bd4ef 10202
c19d1205
ZW		 10203/* Two possible forms:
10204 "{C|S}PSR_<field>, Rm",
10205 "{C|S}PSR_f, #expression". */
b99bd4ef 10206
c19d1205
ZW		 10207static void
10208do_msr (void)
10209{
037e8744
JB		 10210 if (do_vfp_nsyn_msr () == SUCCESS)
10211 return;
10212
c19d1205
ZW		 10213 inst.instruction |= inst.operands[0].imm;
10214 if (inst.operands[1].isreg)
10215 inst.instruction |= inst.operands[1].reg;
10216 else
b99bd4ef 10217 {
c19d1205 10218 inst.instruction |= INST_IMMEDIATE;
e2b0ab59
AV		 10219 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
10220 inst.relocs[0].pc_rel = 0;
b99bd4ef 10221 }
b99bd4ef
NC		 10222}
10223
c19d1205
ZW		 10224static void
10225do_mul (void)
a737bd4d 10226{
ff4a8d2b
NC		 10227 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
10228
c19d1205
ZW		 10229 if (!inst.operands[2].present)
10230 inst.operands[2].reg = inst.operands[0].reg;
10231 inst.instruction |= inst.operands[0].reg << 16;
10232 inst.instruction |= inst.operands[1].reg;
10233 inst.instruction |= inst.operands[2].reg << 8;
a737bd4d 10234
8fb9d7b9
MS		 10235 if (inst.operands[0].reg == inst.operands[1].reg
10236 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
10237 as_tsktsk (_("Rd and Rm should be different in mul"));
a737bd4d
NC		 10238}
10239
c19d1205
ZW		 10240/* Long Multiply Parser
10241 UMULL RdLo, RdHi, Rm, Rs
10242 SMULL RdLo, RdHi, Rm, Rs
10243 UMLAL RdLo, RdHi, Rm, Rs
10244 SMLAL RdLo, RdHi, Rm, Rs. */
b99bd4ef
NC		 10245
10246static void
c19d1205 10247do_mull (void)
b99bd4ef 10248{
c19d1205
ZW		 10249 inst.instruction |= inst.operands[0].reg << 12;
10250 inst.instruction |= inst.operands[1].reg << 16;
10251 inst.instruction |= inst.operands[2].reg;
10252 inst.instruction |= inst.operands[3].reg << 8;
b99bd4ef 10253
682b27ad
PB		 10254 /* rdhi and rdlo must be different. */
10255 if (inst.operands[0].reg == inst.operands[1].reg)
10256 as_tsktsk (_("rdhi and rdlo must be different"));
10257
10258 /* rdhi, rdlo and rm must all be different before armv6. */
10259 if ((inst.operands[0].reg == inst.operands[2].reg
c19d1205 10260 || inst.operands[1].reg == inst.operands[2].reg)
682b27ad 10261 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
c19d1205
ZW		 10262 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
10263}
b99bd4ef 10264
c19d1205
ZW		 10265static void
10266do_nop (void)
10267{
e7495e45
NS		 10268 if (inst.operands[0].present
10269 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
c19d1205
ZW		 10270 {
10271 /* Architectural NOP hints are CPSR sets with no bits selected. */
10272 inst.instruction &= 0xf0000000;
e7495e45
NS		 10273 inst.instruction |= 0x0320f000;
10274 if (inst.operands[0].present)
10275 inst.instruction |= inst.operands[0].imm;
c19d1205 10276 }
b99bd4ef
NC		 10277}
10278
c19d1205
ZW		 10279/* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
10280 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
10281 Condition defaults to COND_ALWAYS.
10282 Error if Rd, Rn or Rm are R15. */
b99bd4ef
NC		 10283
10284static void
c19d1205 10285do_pkhbt (void)
b99bd4ef 10286{
c19d1205
ZW		 10287 inst.instruction |= inst.operands[0].reg << 12;
10288 inst.instruction |= inst.operands[1].reg << 16;
10289 inst.instruction |= inst.operands[2].reg;
10290 if (inst.operands[3].present)
10291 encode_arm_shift (3);
10292}
b99bd4ef 10293
c19d1205 10294/* ARM V6 PKHTB (Argument Parse). */
b99bd4ef 10295
c19d1205
ZW		 10296static void
10297do_pkhtb (void)
10298{
10299 if (!inst.operands[3].present)
b99bd4ef 10300 {
c19d1205
ZW		 10301 /* If the shift specifier is omitted, turn the instruction
10302 into pkhbt rd, rm, rn. */
10303 inst.instruction &= 0xfff00010;
10304 inst.instruction |= inst.operands[0].reg << 12;
10305 inst.instruction |= inst.operands[1].reg;
10306 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC		 10307 }
10308 else
10309 {
c19d1205
ZW		 10310 inst.instruction |= inst.operands[0].reg << 12;
10311 inst.instruction |= inst.operands[1].reg << 16;
10312 inst.instruction |= inst.operands[2].reg;
10313 encode_arm_shift (3);
b99bd4ef
NC		 10314 }
10315}
10316
c19d1205 10317/* ARMv5TE: Preload-Cache
60e5ef9f 10318 MP Extensions: Preload for write
c19d1205 10319
60e5ef9f 10320 PLD(W) <addr_mode>
c19d1205
ZW		 10321
10322 Syntactically, like LDR with B=1, W=0, L=1. */
b99bd4ef
NC		 10323
10324static void
c19d1205 10325do_pld (void)
b99bd4ef 10326{
c19d1205
ZW		 10327 constraint (!inst.operands[0].isreg,
10328 _("'[' expected after PLD mnemonic"));
10329 constraint (inst.operands[0].postind,
10330 _("post-indexed expression used in preload instruction"));
10331 constraint (inst.operands[0].writeback,
10332 _("writeback used in preload instruction"));
10333 constraint (!inst.operands[0].preind,
10334 _("unindexed addressing used in preload instruction"));
c19d1205
ZW		 10335 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
10336}
b99bd4ef 10337
62b3e311
PB		 10338/* ARMv7: PLI <addr_mode> */
10339static void
10340do_pli (void)
10341{
10342 constraint (!inst.operands[0].isreg,
10343 _("'[' expected after PLI mnemonic"));
10344 constraint (inst.operands[0].postind,
10345 _("post-indexed expression used in preload instruction"));
10346 constraint (inst.operands[0].writeback,
10347 _("writeback used in preload instruction"));
10348 constraint (!inst.operands[0].preind,
10349 _("unindexed addressing used in preload instruction"));
10350 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
10351 inst.instruction &= ~PRE_INDEX;
10352}
10353
c19d1205
ZW		 10354static void
10355do_push_pop (void)
10356{
5e0d7f77
MP		 10357 constraint (inst.operands[0].writeback,
10358 _("push/pop do not support {reglist}^"));
c19d1205
ZW		 10359 inst.operands[1] = inst.operands[0];
10360 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
10361 inst.operands[0].isreg = 1;
10362 inst.operands[0].writeback = 1;
10363 inst.operands[0].reg = REG_SP;
6530b175 10364 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
c19d1205 10365}
b99bd4ef 10366
c19d1205
ZW		 10367/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10368 word at the specified address and the following word
10369 respectively.
10370 Unconditionally executed.
10371 Error if Rn is R15. */
b99bd4ef 10372
c19d1205
ZW		 10373static void
10374do_rfe (void)
10375{
10376 inst.instruction |= inst.operands[0].reg << 16;
10377 if (inst.operands[0].writeback)
10378 inst.instruction |= WRITE_BACK;
10379}
b99bd4ef 10380
c19d1205 10381/* ARM V6 ssat (argument parse). */
b99bd4ef 10382
c19d1205
ZW		 10383static void
10384do_ssat (void)
10385{
10386 inst.instruction |= inst.operands[0].reg << 12;
10387 inst.instruction |= (inst.operands[1].imm - 1) << 16;
10388 inst.instruction |= inst.operands[2].reg;
b99bd4ef 10389
c19d1205
ZW		 10390 if (inst.operands[3].present)
10391 encode_arm_shift (3);
b99bd4ef
NC		 10392}
10393
c19d1205 10394/* ARM V6 usat (argument parse). */
b99bd4ef
NC		 10395
10396static void
c19d1205 10397do_usat (void)
b99bd4ef 10398{
c19d1205
ZW		 10399 inst.instruction |= inst.operands[0].reg << 12;
10400 inst.instruction |= inst.operands[1].imm << 16;
10401 inst.instruction |= inst.operands[2].reg;
b99bd4ef 10402
c19d1205
ZW		 10403 if (inst.operands[3].present)
10404 encode_arm_shift (3);
b99bd4ef
NC		 10405}
10406
c19d1205 10407/* ARM V6 ssat16 (argument parse). */
09d92015
MM		 10408
10409static void
c19d1205 10410do_ssat16 (void)
09d92015 10411{
c19d1205
ZW		 10412 inst.instruction |= inst.operands[0].reg << 12;
10413 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
10414 inst.instruction |= inst.operands[2].reg;
09d92015
MM		 10415}
10416
c19d1205
ZW		 10417static void
10418do_usat16 (void)
a737bd4d 10419{
c19d1205
ZW		 10420 inst.instruction |= inst.operands[0].reg << 12;
10421 inst.instruction |= inst.operands[1].imm << 16;
10422 inst.instruction |= inst.operands[2].reg;
10423}
a737bd4d 10424
c19d1205
ZW		 10425/* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10426 preserving the other bits.
a737bd4d 10427
c19d1205
ZW		 10428 setend <endian_specifier>, where <endian_specifier> is either
10429 BE or LE. */
a737bd4d 10430
c19d1205
ZW		 10431static void
10432do_setend (void)
10433{
12e37cbc
MGD		 10434 if (warn_on_deprecated
10435 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
5c3696f8 10436 as_tsktsk (_("setend use is deprecated for ARMv8"));
12e37cbc 10437
c19d1205
ZW		 10438 if (inst.operands[0].imm)
10439 inst.instruction |= 0x200;
a737bd4d
NC		 10440}
10441
10442static void
c19d1205 10443do_shift (void)
a737bd4d 10444{
c19d1205
ZW		 10445 unsigned int Rm = (inst.operands[1].present
10446 ? inst.operands[1].reg
10447 : inst.operands[0].reg);
a737bd4d 10448
c19d1205
ZW		 10449 inst.instruction |= inst.operands[0].reg << 12;
10450 inst.instruction |= Rm;
10451 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
a737bd4d 10452 {
c19d1205
ZW		 10453 inst.instruction |= inst.operands[2].reg << 8;
10454 inst.instruction |= SHIFT_BY_REG;
94342ec3
NC		 10455 /* PR 12854: Error on extraneous shifts. */
10456 constraint (inst.operands[2].shifted,
10457 _("extraneous shift as part of operand to shift insn"));
a737bd4d
NC		 10458 }
10459 else
e2b0ab59 10460 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
a737bd4d
NC		 10461}
10462
09d92015 10463static void
3eb17e6b 10464do_smc (void)
09d92015 10465{
ba85f98c
BW		 10466 unsigned int value = inst.relocs[0].exp.X_add_number;
10467 constraint (value > 0xf, _("immediate too large (bigger than 0xF)"));
10468
e2b0ab59
AV		 10469 inst.relocs[0].type = BFD_RELOC_ARM_SMC;
10470 inst.relocs[0].pc_rel = 0;
09d92015
MM		 10471}
10472
90ec0d68
MGD		 10473static void
10474do_hvc (void)
10475{
e2b0ab59
AV		 10476 inst.relocs[0].type = BFD_RELOC_ARM_HVC;
10477 inst.relocs[0].pc_rel = 0;
90ec0d68
MGD		 10478}
10479
09d92015 10480static void
c19d1205 10481do_swi (void)
09d92015 10482{
e2b0ab59
AV		 10483 inst.relocs[0].type = BFD_RELOC_ARM_SWI;
10484 inst.relocs[0].pc_rel = 0;
09d92015
MM		 10485}
10486
ddfded2f
MW		 10487static void
10488do_setpan (void)
10489{
10490 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
10491 _("selected processor does not support SETPAN instruction"));
10492
10493 inst.instruction |= ((inst.operands[0].imm & 1) << 9);
10494}
10495
10496static void
10497do_t_setpan (void)
10498{
10499 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
10500 _("selected processor does not support SETPAN instruction"));
10501
10502 inst.instruction |= (inst.operands[0].imm << 3);
10503}
10504
c19d1205
ZW		 10505/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10506 SMLAxy{cond} Rd,Rm,Rs,Rn
10507 SMLAWy{cond} Rd,Rm,Rs,Rn
10508 Error if any register is R15. */
e16bb312 10509
c19d1205
ZW		 10510static void
10511do_smla (void)
e16bb312 10512{
c19d1205
ZW		 10513 inst.instruction |= inst.operands[0].reg << 16;
10514 inst.instruction |= inst.operands[1].reg;
10515 inst.instruction |= inst.operands[2].reg << 8;
10516 inst.instruction |= inst.operands[3].reg << 12;
10517}
a737bd4d 10518
c19d1205
ZW		 10519/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10520 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10521 Error if any register is R15.
10522 Warning if Rdlo == Rdhi. */
a737bd4d 10523
c19d1205
ZW		 10524static void
10525do_smlal (void)
10526{
10527 inst.instruction |= inst.operands[0].reg << 12;
10528 inst.instruction |= inst.operands[1].reg << 16;
10529 inst.instruction |= inst.operands[2].reg;
10530 inst.instruction |= inst.operands[3].reg << 8;
a737bd4d 10531
c19d1205
ZW		 10532 if (inst.operands[0].reg == inst.operands[1].reg)
10533 as_tsktsk (_("rdhi and rdlo must be different"));
10534}
a737bd4d 10535
c19d1205
ZW		 10536/* ARM V5E (El Segundo) signed-multiply (argument parse)
10537 SMULxy{cond} Rd,Rm,Rs
10538 Error if any register is R15. */
a737bd4d 10539
c19d1205
ZW		 10540static void
10541do_smul (void)
10542{
10543 inst.instruction |= inst.operands[0].reg << 16;
10544 inst.instruction |= inst.operands[1].reg;
10545 inst.instruction |= inst.operands[2].reg << 8;
10546}
a737bd4d 10547
b6702015
PB		 10548/* ARM V6 srs (argument parse). The variable fields in the encoding are
10549 the same for both ARM and Thumb-2. */
a737bd4d 10550
c19d1205
ZW		 10551static void
10552do_srs (void)
10553{
b6702015
PB		 10554 int reg;
10555
10556 if (inst.operands[0].present)
10557 {
10558 reg = inst.operands[0].reg;
fdfde340 10559 constraint (reg != REG_SP, _("SRS base register must be r13"));
b6702015
PB		 10560 }
10561 else
fdfde340 10562 reg = REG_SP;
b6702015
PB		 10563
10564 inst.instruction |= reg << 16;
10565 inst.instruction |= inst.operands[1].imm;
10566 if (inst.operands[0].writeback || inst.operands[1].writeback)
c19d1205
ZW		 10567 inst.instruction |= WRITE_BACK;
10568}
a737bd4d 10569
c19d1205 10570/* ARM V6 strex (argument parse). */
a737bd4d 10571
c19d1205
ZW		 10572static void
10573do_strex (void)
10574{
10575 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10576 || inst.operands[2].postind || inst.operands[2].writeback
10577 || inst.operands[2].immisreg || inst.operands[2].shifted
01cfc07f
NC		 10578 || inst.operands[2].negative
10579 /* See comment in do_ldrex(). */
10580 || (inst.operands[2].reg == REG_PC),
10581 BAD_ADDR_MODE);
a737bd4d 10582
c19d1205
ZW		 10583 constraint (inst.operands[0].reg == inst.operands[1].reg
10584 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
a737bd4d 10585
e2b0ab59
AV		 10586 constraint (inst.relocs[0].exp.X_op != O_constant
10587 || inst.relocs[0].exp.X_add_number != 0,
c19d1205 10588 _("offset must be zero in ARM encoding"));
a737bd4d 10589
c19d1205
ZW		 10590 inst.instruction |= inst.operands[0].reg << 12;
10591 inst.instruction |= inst.operands[1].reg;
10592 inst.instruction |= inst.operands[2].reg << 16;
e2b0ab59 10593 inst.relocs[0].type = BFD_RELOC_UNUSED;
e16bb312
NC		 10594}
10595
877807f8
NC		 10596static void
10597do_t_strexbh (void)
10598{
10599 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10600 || inst.operands[2].postind || inst.operands[2].writeback
10601 || inst.operands[2].immisreg || inst.operands[2].shifted
10602 || inst.operands[2].negative,
10603 BAD_ADDR_MODE);
10604
10605 constraint (inst.operands[0].reg == inst.operands[1].reg
10606 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10607
10608 do_rm_rd_rn ();
10609}
10610
e16bb312 10611static void
c19d1205 10612do_strexd (void)
e16bb312 10613{
c19d1205
ZW		 10614 constraint (inst.operands[1].reg % 2 != 0,
10615 _("even register required"));
10616 constraint (inst.operands[2].present
10617 && inst.operands[2].reg != inst.operands[1].reg + 1,
10618 _("can only store two consecutive registers"));
10619 /* If op 2 were present and equal to PC, this function wouldn't
10620 have been called in the first place. */
10621 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
e16bb312 10622
c19d1205
ZW		 10623 constraint (inst.operands[0].reg == inst.operands[1].reg
10624 || inst.operands[0].reg == inst.operands[1].reg + 1
10625 || inst.operands[0].reg == inst.operands[3].reg,
10626 BAD_OVERLAP);
e16bb312 10627
c19d1205
ZW		 10628 inst.instruction |= inst.operands[0].reg << 12;
10629 inst.instruction |= inst.operands[1].reg;
10630 inst.instruction |= inst.operands[3].reg << 16;
e16bb312
NC		 10631}
10632
9eb6c0f1
MGD		 10633/* ARM V8 STRL. */
10634static void
4b8c8c02 10635do_stlex (void)
9eb6c0f1
MGD		 10636{
10637 constraint (inst.operands[0].reg == inst.operands[1].reg
10638 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10639
10640 do_rd_rm_rn ();
10641}
10642
10643static void
4b8c8c02 10644do_t_stlex (void)
9eb6c0f1
MGD		 10645{
10646 constraint (inst.operands[0].reg == inst.operands[1].reg
10647 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10648
10649 do_rm_rd_rn ();
10650}
10651
c19d1205
ZW		 10652/* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10653 extends it to 32-bits, and adds the result to a value in another
10654 register. You can specify a rotation by 0, 8, 16, or 24 bits
10655 before extracting the 16-bit value.
10656 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10657 Condition defaults to COND_ALWAYS.
10658 Error if any register uses R15. */
10659
e16bb312 10660static void
c19d1205 10661do_sxtah (void)
e16bb312 10662{
c19d1205
ZW		 10663 inst.instruction |= inst.operands[0].reg << 12;
10664 inst.instruction |= inst.operands[1].reg << 16;
10665 inst.instruction |= inst.operands[2].reg;
10666 inst.instruction |= inst.operands[3].imm << 10;
10667}
e16bb312 10668
c19d1205 10669/* ARM V6 SXTH.
e16bb312 10670
c19d1205
ZW		 10671 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10672 Condition defaults to COND_ALWAYS.
10673 Error if any register uses R15. */
e16bb312
NC		 10674
10675static void
c19d1205 10676do_sxth (void)
e16bb312 10677{
c19d1205
ZW		 10678 inst.instruction |= inst.operands[0].reg << 12;
10679 inst.instruction |= inst.operands[1].reg;
10680 inst.instruction |= inst.operands[2].imm << 10;
e16bb312 10681}
c19d1205
ZW		 10682\f
10683/* VFP instructions. In a logical order: SP variant first, monad
10684 before dyad, arithmetic then move then load/store. */
e16bb312
NC		 10685
10686static void
c19d1205 10687do_vfp_sp_monadic (void)
e16bb312 10688{
57785aa2
AV		 10689 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10690 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10691 _(BAD_FPU));
10692
5287ad62
JB		 10693 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10694 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
e16bb312
NC		 10695}
10696
10697static void
c19d1205 10698do_vfp_sp_dyadic (void)
e16bb312 10699{
5287ad62
JB		 10700 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10701 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
10702 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
e16bb312
NC		 10703}
10704
10705static void
c19d1205 10706do_vfp_sp_compare_z (void)
e16bb312 10707{
5287ad62 10708 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
e16bb312
NC		 10709}
10710
10711static void
c19d1205 10712do_vfp_dp_sp_cvt (void)
e16bb312 10713{
5287ad62
JB		 10714 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10715 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
e16bb312
NC		 10716}
10717
10718static void
c19d1205 10719do_vfp_sp_dp_cvt (void)
e16bb312 10720{
5287ad62
JB		 10721 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10722 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
e16bb312
NC		 10723}
10724
10725static void
c19d1205 10726do_vfp_reg_from_sp (void)
e16bb312 10727{
57785aa2
AV		 10728 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10729 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10730 _(BAD_FPU));
10731
c19d1205 10732 inst.instruction |= inst.operands[0].reg << 12;
5287ad62 10733 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
e16bb312
NC		 10734}
10735
10736static void
c19d1205 10737do_vfp_reg2_from_sp2 (void)
e16bb312 10738{
c19d1205
ZW		 10739 constraint (inst.operands[2].imm != 2,
10740 _("only two consecutive VFP SP registers allowed here"));
10741 inst.instruction |= inst.operands[0].reg << 12;
10742 inst.instruction |= inst.operands[1].reg << 16;
5287ad62 10743 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
e16bb312
NC		 10744}
10745
10746static void
c19d1205 10747do_vfp_sp_from_reg (void)
e16bb312 10748{
57785aa2
AV		 10749 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10750 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10751 _(BAD_FPU));
10752
5287ad62 10753 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
c19d1205 10754 inst.instruction |= inst.operands[1].reg << 12;
e16bb312
NC		 10755}
10756
10757static void
c19d1205 10758do_vfp_sp2_from_reg2 (void)
e16bb312 10759{
c19d1205
ZW		 10760 constraint (inst.operands[0].imm != 2,
10761 _("only two consecutive VFP SP registers allowed here"));
5287ad62 10762 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
c19d1205
ZW		 10763 inst.instruction |= inst.operands[1].reg << 12;
10764 inst.instruction |= inst.operands[2].reg << 16;
e16bb312
NC		 10765}
10766
10767static void
c19d1205 10768do_vfp_sp_ldst (void)
e16bb312 10769{
5287ad62 10770 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
c19d1205 10771 encode_arm_cp_address (1, FALSE, TRUE, 0);
e16bb312
NC		 10772}
10773
10774static void
c19d1205 10775do_vfp_dp_ldst (void)
e16bb312 10776{
5287ad62 10777 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
c19d1205 10778 encode_arm_cp_address (1, FALSE, TRUE, 0);
e16bb312
NC		 10779}
10780
c19d1205 10781
e16bb312 10782static void
c19d1205 10783vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
e16bb312 10784{
c19d1205
ZW		 10785 if (inst.operands[0].writeback)
10786 inst.instruction |= WRITE_BACK;
10787 else
10788 constraint (ldstm_type != VFP_LDSTMIA,
10789 _("this addressing mode requires base-register writeback"));
10790 inst.instruction |= inst.operands[0].reg << 16;
5287ad62 10791 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
c19d1205 10792 inst.instruction |= inst.operands[1].imm;
e16bb312
NC		 10793}
10794
10795static void
c19d1205 10796vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
e16bb312 10797{
c19d1205 10798 int count;
e16bb312 10799
c19d1205
ZW		 10800 if (inst.operands[0].writeback)
10801 inst.instruction |= WRITE_BACK;
10802 else
10803 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
10804 _("this addressing mode requires base-register writeback"));
e16bb312 10805
c19d1205 10806 inst.instruction |= inst.operands[0].reg << 16;
5287ad62 10807 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
e16bb312 10808
c19d1205
ZW		 10809 count = inst.operands[1].imm << 1;
10810 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
10811 count += 1;
e16bb312 10812
c19d1205 10813 inst.instruction |= count;
e16bb312
NC		 10814}
10815
10816static void
c19d1205 10817do_vfp_sp_ldstmia (void)
e16bb312 10818{
c19d1205 10819 vfp_sp_ldstm (VFP_LDSTMIA);
e16bb312
NC		 10820}
10821
10822static void
c19d1205 10823do_vfp_sp_ldstmdb (void)
e16bb312 10824{
c19d1205 10825 vfp_sp_ldstm (VFP_LDSTMDB);
e16bb312
NC		 10826}
10827
10828static void
c19d1205 10829do_vfp_dp_ldstmia (void)
e16bb312 10830{
c19d1205 10831 vfp_dp_ldstm (VFP_LDSTMIA);
e16bb312
NC		 10832}
10833
10834static void
c19d1205 10835do_vfp_dp_ldstmdb (void)
e16bb312 10836{
c19d1205 10837 vfp_dp_ldstm (VFP_LDSTMDB);
e16bb312
NC		 10838}
10839
10840static void
c19d1205 10841do_vfp_xp_ldstmia (void)
e16bb312 10842{
c19d1205
ZW		 10843 vfp_dp_ldstm (VFP_LDSTMIAX);
10844}
e16bb312 10845
c19d1205
ZW		 10846static void
10847do_vfp_xp_ldstmdb (void)
10848{
10849 vfp_dp_ldstm (VFP_LDSTMDBX);
e16bb312 10850}
5287ad62
JB		 10851
10852static void
10853do_vfp_dp_rd_rm (void)
10854{
57785aa2
AV		 10855 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
10856 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10857 _(BAD_FPU));
10858
5287ad62
JB		 10859 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10860 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
10861}
10862
10863static void
10864do_vfp_dp_rn_rd (void)
10865{
10866 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
10867 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10868}
10869
10870static void
10871do_vfp_dp_rd_rn (void)
10872{
10873 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10874 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
10875}
10876
10877static void
10878do_vfp_dp_rd_rn_rm (void)
10879{
57785aa2
AV		 10880 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
10881 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10882 _(BAD_FPU));
10883
5287ad62
JB		 10884 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10885 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
10886 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
10887}
10888
10889static void
10890do_vfp_dp_rd (void)
10891{
10892 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10893}
10894
10895static void
10896do_vfp_dp_rm_rd_rn (void)
10897{
57785aa2
AV		 10898 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
10899 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10900 _(BAD_FPU));
10901
5287ad62
JB		 10902 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
10903 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10904 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
10905}
10906
10907/* VFPv3 instructions. */
10908static void
10909do_vfp_sp_const (void)
10910{
10911 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
00249aaa
PB		 10912 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
10913 inst.instruction |= (inst.operands[1].imm & 0x0f);
5287ad62
JB		 10914}
10915
10916static void
10917do_vfp_dp_const (void)
10918{
10919 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
00249aaa
PB		 10920 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
10921 inst.instruction |= (inst.operands[1].imm & 0x0f);
5287ad62
JB		 10922}
10923
10924static void
10925vfp_conv (int srcsize)
10926{
5f1af56b
MGD		 10927 int immbits = srcsize - inst.operands[1].imm;
10928
fa94de6b
RM		 10929 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
10930 {
5f1af56b 10931 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
477330fc 10932 i.e. immbits must be in range 0 - 16. */
5f1af56b
MGD		 10933 inst.error = _("immediate value out of range, expected range [0, 16]");
10934 return;
10935 }
fa94de6b 10936 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
5f1af56b
MGD		 10937 {
10938 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
477330fc 10939 i.e. immbits must be in range 0 - 31. */
5f1af56b
MGD		 10940 inst.error = _("immediate value out of range, expected range [1, 32]");
10941 return;
10942 }
10943
5287ad62
JB		 10944 inst.instruction |= (immbits & 1) << 5;
10945 inst.instruction |= (immbits >> 1);
10946}
10947
10948static void
10949do_vfp_sp_conv_16 (void)
10950{
10951 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10952 vfp_conv (16);
10953}
10954
10955static void
10956do_vfp_dp_conv_16 (void)
10957{
10958 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10959 vfp_conv (16);
10960}
10961
10962static void
10963do_vfp_sp_conv_32 (void)
10964{
10965 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10966 vfp_conv (32);
10967}
10968
10969static void
10970do_vfp_dp_conv_32 (void)
10971{
10972 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10973 vfp_conv (32);
10974}
c19d1205
ZW		 10975\f
10976/* FPA instructions. Also in a logical order. */
e16bb312 10977
c19d1205
ZW		 10978static void
10979do_fpa_cmp (void)
10980{
10981 inst.instruction |= inst.operands[0].reg << 16;
10982 inst.instruction |= inst.operands[1].reg;
10983}
b99bd4ef
NC		 10984
10985static void
c19d1205 10986do_fpa_ldmstm (void)
b99bd4ef 10987{
c19d1205
ZW		 10988 inst.instruction |= inst.operands[0].reg << 12;
10989 switch (inst.operands[1].imm)
10990 {
10991 case 1: inst.instruction |= CP_T_X; break;
10992 case 2: inst.instruction |= CP_T_Y; break;
10993 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
10994 case 4: break;
10995 default: abort ();
10996 }
b99bd4ef 10997
c19d1205
ZW		 10998 if (inst.instruction & (PRE_INDEX | INDEX_UP))
10999 {
11000 /* The instruction specified "ea" or "fd", so we can only accept
11001 [Rn]{!}. The instruction does not really support stacking or
11002 unstacking, so we have to emulate these by setting appropriate
11003 bits and offsets. */
e2b0ab59
AV		 11004 constraint (inst.relocs[0].exp.X_op != O_constant
11005 || inst.relocs[0].exp.X_add_number != 0,
c19d1205 11006 _("this instruction does not support indexing"));
b99bd4ef 11007
c19d1205 11008 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
e2b0ab59 11009 inst.relocs[0].exp.X_add_number = 12 * inst.operands[1].imm;
b99bd4ef 11010
c19d1205 11011 if (!(inst.instruction & INDEX_UP))
e2b0ab59 11012 inst.relocs[0].exp.X_add_number = -inst.relocs[0].exp.X_add_number;
b99bd4ef 11013
c19d1205
ZW		 11014 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
11015 {
11016 inst.operands[2].preind = 0;
11017 inst.operands[2].postind = 1;
11018 }
11019 }
b99bd4ef 11020
c19d1205 11021 encode_arm_cp_address (2, TRUE, TRUE, 0);
b99bd4ef 11022}
c19d1205
ZW		 11023\f
11024/* iWMMXt instructions: strictly in alphabetical order. */
b99bd4ef 11025
c19d1205
ZW		 11026static void
11027do_iwmmxt_tandorc (void)
11028{
11029 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
11030}
b99bd4ef 11031
c19d1205
ZW		 11032static void
11033do_iwmmxt_textrc (void)
11034{
11035 inst.instruction |= inst.operands[0].reg << 12;
11036 inst.instruction |= inst.operands[1].imm;
11037}
b99bd4ef
NC		 11038
11039static void
c19d1205 11040do_iwmmxt_textrm (void)
b99bd4ef 11041{
c19d1205
ZW		 11042 inst.instruction |= inst.operands[0].reg << 12;
11043 inst.instruction |= inst.operands[1].reg << 16;
11044 inst.instruction |= inst.operands[2].imm;
11045}
b99bd4ef 11046
c19d1205
ZW		 11047static void
11048do_iwmmxt_tinsr (void)
11049{
11050 inst.instruction |= inst.operands[0].reg << 16;
11051 inst.instruction |= inst.operands[1].reg << 12;
11052 inst.instruction |= inst.operands[2].imm;
11053}
b99bd4ef 11054
c19d1205
ZW		 11055static void
11056do_iwmmxt_tmia (void)
11057{
11058 inst.instruction |= inst.operands[0].reg << 5;
11059 inst.instruction |= inst.operands[1].reg;
11060 inst.instruction |= inst.operands[2].reg << 12;
11061}
b99bd4ef 11062
c19d1205
ZW		 11063static void
11064do_iwmmxt_waligni (void)
11065{
11066 inst.instruction |= inst.operands[0].reg << 12;
11067 inst.instruction |= inst.operands[1].reg << 16;
11068 inst.instruction |= inst.operands[2].reg;
11069 inst.instruction |= inst.operands[3].imm << 20;
11070}
b99bd4ef 11071
2d447fca
JM		 11072static void
11073do_iwmmxt_wmerge (void)
11074{
11075 inst.instruction |= inst.operands[0].reg << 12;
11076 inst.instruction |= inst.operands[1].reg << 16;
11077 inst.instruction |= inst.operands[2].reg;
11078 inst.instruction |= inst.operands[3].imm << 21;
11079}
11080
c19d1205
ZW		 11081static void
11082do_iwmmxt_wmov (void)
11083{
11084 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
11085 inst.instruction |= inst.operands[0].reg << 12;
11086 inst.instruction |= inst.operands[1].reg << 16;
11087 inst.instruction |= inst.operands[1].reg;
11088}
b99bd4ef 11089
c19d1205
ZW		 11090static void
11091do_iwmmxt_wldstbh (void)
11092{
8f06b2d8 11093 int reloc;
c19d1205 11094 inst.instruction |= inst.operands[0].reg << 12;
8f06b2d8
PB		 11095 if (thumb_mode)
11096 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
11097 else
11098 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
11099 encode_arm_cp_address (1, TRUE, FALSE, reloc);
b99bd4ef
NC		 11100}
11101
c19d1205
ZW		 11102static void
11103do_iwmmxt_wldstw (void)
11104{
11105 /* RIWR_RIWC clears .isreg for a control register. */
11106 if (!inst.operands[0].isreg)
11107 {
11108 constraint (inst.cond != COND_ALWAYS, BAD_COND);
11109 inst.instruction |= 0xf0000000;
11110 }
b99bd4ef 11111
c19d1205
ZW		 11112 inst.instruction |= inst.operands[0].reg << 12;
11113 encode_arm_cp_address (1, TRUE, TRUE, 0);
11114}
b99bd4ef
NC		 11115
11116static void
c19d1205 11117do_iwmmxt_wldstd (void)
b99bd4ef 11118{
c19d1205 11119 inst.instruction |= inst.operands[0].reg << 12;
2d447fca
JM		 11120 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
11121 && inst.operands[1].immisreg)
11122 {
11123 inst.instruction &= ~0x1a000ff;
eff0bc54 11124 inst.instruction |= (0xfU << 28);
2d447fca
JM		 11125 if (inst.operands[1].preind)
11126 inst.instruction |= PRE_INDEX;
11127 if (!inst.operands[1].negative)
11128 inst.instruction |= INDEX_UP;
11129 if (inst.operands[1].writeback)
11130 inst.instruction |= WRITE_BACK;
11131 inst.instruction |= inst.operands[1].reg << 16;
e2b0ab59 11132 inst.instruction |= inst.relocs[0].exp.X_add_number << 4;
2d447fca
JM		 11133 inst.instruction |= inst.operands[1].imm;
11134 }
11135 else
11136 encode_arm_cp_address (1, TRUE, FALSE, 0);
c19d1205 11137}
b99bd4ef 11138
c19d1205
ZW		 11139static void
11140do_iwmmxt_wshufh (void)
11141{
11142 inst.instruction |= inst.operands[0].reg << 12;
11143 inst.instruction |= inst.operands[1].reg << 16;
11144 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
11145 inst.instruction |= (inst.operands[2].imm & 0x0f);
11146}
b99bd4ef 11147
c19d1205
ZW		 11148static void
11149do_iwmmxt_wzero (void)
11150{
11151 /* WZERO reg is an alias for WANDN reg, reg, reg. */
11152 inst.instruction |= inst.operands[0].reg;
11153 inst.instruction |= inst.operands[0].reg << 12;
11154 inst.instruction |= inst.operands[0].reg << 16;
11155}
2d447fca
JM		 11156
11157static void
11158do_iwmmxt_wrwrwr_or_imm5 (void)
11159{
11160 if (inst.operands[2].isreg)
11161 do_rd_rn_rm ();
11162 else {
11163 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
11164 _("immediate operand requires iWMMXt2"));
11165 do_rd_rn ();
11166 if (inst.operands[2].imm == 0)
11167 {
11168 switch ((inst.instruction >> 20) & 0xf)
11169 {
11170 case 4:
11171 case 5:
11172 case 6:
5f4273c7 11173 case 7:
2d447fca
JM		 11174 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
11175 inst.operands[2].imm = 16;
11176 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
11177 break;
11178 case 8:
11179 case 9:
11180 case 10:
11181 case 11:
11182 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
11183 inst.operands[2].imm = 32;
11184 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
11185 break;
11186 case 12:
11187 case 13:
11188 case 14:
11189 case 15:
11190 {
11191 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
11192 unsigned long wrn;
11193 wrn = (inst.instruction >> 16) & 0xf;
11194 inst.instruction &= 0xff0fff0f;
11195 inst.instruction |= wrn;
11196 /* Bail out here; the instruction is now assembled. */
11197 return;
11198 }
11199 }
11200 }
11201 /* Map 32 -> 0, etc. */
11202 inst.operands[2].imm &= 0x1f;
eff0bc54 11203 inst.instruction |= (0xfU << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
2d447fca
JM		 11204 }
11205}
c19d1205
ZW		 11206\f
11207/* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
11208 operations first, then control, shift, and load/store. */
b99bd4ef 11209
c19d1205 11210/* Insns like "foo X,Y,Z". */
b99bd4ef 11211
c19d1205
ZW		 11212static void
11213do_mav_triple (void)
11214{
11215 inst.instruction |= inst.operands[0].reg << 16;
11216 inst.instruction |= inst.operands[1].reg;
11217 inst.instruction |= inst.operands[2].reg << 12;
11218}
b99bd4ef 11219
c19d1205
ZW		 11220/* Insns like "foo W,X,Y,Z".
11221 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
a737bd4d 11222
c19d1205
ZW		 11223static void
11224do_mav_quad (void)
11225{
11226 inst.instruction |= inst.operands[0].reg << 5;
11227 inst.instruction |= inst.operands[1].reg << 12;
11228 inst.instruction |= inst.operands[2].reg << 16;
11229 inst.instruction |= inst.operands[3].reg;
a737bd4d
NC		 11230}
11231
c19d1205
ZW		 11232/* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
11233static void
11234do_mav_dspsc (void)
a737bd4d 11235{
c19d1205
ZW		 11236 inst.instruction |= inst.operands[1].reg << 12;
11237}
a737bd4d 11238
c19d1205
ZW		 11239/* Maverick shift immediate instructions.
11240 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
11241 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
a737bd4d 11242
c19d1205
ZW		 11243static void
11244do_mav_shift (void)
11245{
11246 int imm = inst.operands[2].imm;
a737bd4d 11247
c19d1205
ZW		 11248 inst.instruction |= inst.operands[0].reg << 12;
11249 inst.instruction |= inst.operands[1].reg << 16;
a737bd4d 11250
c19d1205
ZW		 11251 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
11252 Bits 5-7 of the insn should have bits 4-6 of the immediate.
11253 Bit 4 should be 0. */
11254 imm = (imm & 0xf) | ((imm & 0x70) << 1);
a737bd4d 11255
c19d1205
ZW		 11256 inst.instruction |= imm;
11257}
11258\f
11259/* XScale instructions. Also sorted arithmetic before move. */
a737bd4d 11260
c19d1205
ZW		 11261/* Xscale multiply-accumulate (argument parse)
11262 MIAcc acc0,Rm,Rs
11263 MIAPHcc acc0,Rm,Rs
11264 MIAxycc acc0,Rm,Rs. */
a737bd4d 11265
c19d1205
ZW		 11266static void
11267do_xsc_mia (void)
11268{
11269 inst.instruction |= inst.operands[1].reg;
11270 inst.instruction |= inst.operands[2].reg << 12;
11271}
a737bd4d 11272
c19d1205 11273/* Xscale move-accumulator-register (argument parse)
a737bd4d 11274
c19d1205 11275 MARcc acc0,RdLo,RdHi. */
b99bd4ef 11276
c19d1205
ZW		 11277static void
11278do_xsc_mar (void)
11279{
11280 inst.instruction |= inst.operands[1].reg << 12;
11281 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC		 11282}
11283
c19d1205 11284/* Xscale move-register-accumulator (argument parse)
b99bd4ef 11285
c19d1205 11286 MRAcc RdLo,RdHi,acc0. */
b99bd4ef
NC		 11287
11288static void
c19d1205 11289do_xsc_mra (void)
b99bd4ef 11290{
c19d1205
ZW		 11291 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
11292 inst.instruction |= inst.operands[0].reg << 12;
11293 inst.instruction |= inst.operands[1].reg << 16;
11294}
11295\f
11296/* Encoding functions relevant only to Thumb. */
b99bd4ef 11297
c19d1205
ZW		 11298/* inst.operands[i] is a shifted-register operand; encode
11299 it into inst.instruction in the format used by Thumb32. */
11300
11301static void
11302encode_thumb32_shifted_operand (int i)
11303{
e2b0ab59 11304 unsigned int value = inst.relocs[0].exp.X_add_number;
c19d1205 11305 unsigned int shift = inst.operands[i].shift_kind;
b99bd4ef 11306
9c3c69f2
PB		 11307 constraint (inst.operands[i].immisreg,
11308 _("shift by register not allowed in thumb mode"));
c19d1205
ZW		 11309 inst.instruction |= inst.operands[i].reg;
11310 if (shift == SHIFT_RRX)
11311 inst.instruction |= SHIFT_ROR << 4;
11312 else
b99bd4ef 11313 {
e2b0ab59 11314 constraint (inst.relocs[0].exp.X_op != O_constant,
c19d1205
ZW		 11315 _("expression too complex"));
11316
11317 constraint (value > 32
11318 || (value == 32 && (shift == SHIFT_LSL
11319 || shift == SHIFT_ROR)),
11320 _("shift expression is too large"));
11321
11322 if (value == 0)
11323 shift = SHIFT_LSL;
11324 else if (value == 32)
11325 value = 0;
11326
11327 inst.instruction |= shift << 4;
11328 inst.instruction |= (value & 0x1c) << 10;
11329 inst.instruction |= (value & 0x03) << 6;
b99bd4ef 11330 }
c19d1205 11331}
b99bd4ef 11332
b99bd4ef 11333
c19d1205
ZW		 11334/* inst.operands[i] was set up by parse_address. Encode it into a
11335 Thumb32 format load or store instruction. Reject forms that cannot
11336 be used with such instructions. If is_t is true, reject forms that
11337 cannot be used with a T instruction; if is_d is true, reject forms
5be8be5d
DG		 11338 that cannot be used with a D instruction. If it is a store insn,
11339 reject PC in Rn. */
b99bd4ef 11340
c19d1205
ZW		 11341static void
11342encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
11343{
5be8be5d 11344 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
c19d1205
ZW		 11345
11346 constraint (!inst.operands[i].isreg,
53365c0d 11347 _("Instruction does not support =N addresses"));
b99bd4ef 11348
c19d1205
ZW		 11349 inst.instruction |= inst.operands[i].reg << 16;
11350 if (inst.operands[i].immisreg)
b99bd4ef 11351 {
5be8be5d 11352 constraint (is_pc, BAD_PC_ADDRESSING);
c19d1205
ZW		 11353 constraint (is_t || is_d, _("cannot use register index with this instruction"));
11354 constraint (inst.operands[i].negative,
11355 _("Thumb does not support negative register indexing"));
11356 constraint (inst.operands[i].postind,
11357 _("Thumb does not support register post-indexing"));
11358 constraint (inst.operands[i].writeback,
11359 _("Thumb does not support register indexing with writeback"));
11360 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
11361 _("Thumb supports only LSL in shifted register indexing"));
b99bd4ef 11362
f40d1643 11363 inst.instruction |= inst.operands[i].imm;
c19d1205 11364 if (inst.operands[i].shifted)
b99bd4ef 11365 {
e2b0ab59 11366 constraint (inst.relocs[0].exp.X_op != O_constant,
c19d1205 11367 _("expression too complex"));
e2b0ab59
AV		 11368 constraint (inst.relocs[0].exp.X_add_number < 0
11369 || inst.relocs[0].exp.X_add_number > 3,
c19d1205 11370 _("shift out of range"));
e2b0ab59 11371 inst.instruction |= inst.relocs[0].exp.X_add_number << 4;
c19d1205 11372 }
e2b0ab59 11373 inst.relocs[0].type = BFD_RELOC_UNUSED;
c19d1205
ZW		 11374 }
11375 else if (inst.operands[i].preind)
11376 {
5be8be5d 11377 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
f40d1643 11378 constraint (is_t && inst.operands[i].writeback,
c19d1205 11379 _("cannot use writeback with this instruction"));
4755303e
WN		 11380 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0),
11381 BAD_PC_ADDRESSING);
c19d1205
ZW		 11382
11383 if (is_d)
11384 {
11385 inst.instruction |= 0x01000000;
11386 if (inst.operands[i].writeback)
11387 inst.instruction |= 0x00200000;
b99bd4ef 11388 }
c19d1205 11389 else
b99bd4ef 11390 {
c19d1205
ZW		 11391 inst.instruction |= 0x00000c00;
11392 if (inst.operands[i].writeback)
11393 inst.instruction |= 0x00000100;
b99bd4ef 11394 }
e2b0ab59 11395 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM;
b99bd4ef 11396 }
c19d1205 11397 else if (inst.operands[i].postind)
b99bd4ef 11398 {
9c2799c2 11399 gas_assert (inst.operands[i].writeback);
c19d1205
ZW		 11400 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
11401 constraint (is_t, _("cannot use post-indexing with this instruction"));
11402
11403 if (is_d)
11404 inst.instruction |= 0x00200000;
11405 else
11406 inst.instruction |= 0x00000900;
e2b0ab59 11407 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM;
c19d1205
ZW		 11408 }
11409 else /* unindexed - only for coprocessor */
11410 inst.error = _("instruction does not accept unindexed addressing");
11411}
11412
e39c1607 11413/* Table of Thumb instructions which exist in 16- and/or 32-bit
c19d1205
ZW		 11414 encodings (the latter only in post-V6T2 cores). The index is the
11415 value used in the insns table below. When there is more than one
11416 possible 16-bit encoding for the instruction, this table always
0110f2b8
PB		 11417 holds variant (1).
11418 Also contains several pseudo-instructions used during relaxation. */
c19d1205 11419#define T16_32_TAB \
21d799b5
NC		 11420 X(_adc, 4140, eb400000), \
11421 X(_adcs, 4140, eb500000), \
11422 X(_add, 1c00, eb000000), \
11423 X(_adds, 1c00, eb100000), \
11424 X(_addi, 0000, f1000000), \
11425 X(_addis, 0000, f1100000), \
11426 X(_add_pc,000f, f20f0000), \
11427 X(_add_sp,000d, f10d0000), \
11428 X(_adr, 000f, f20f0000), \
11429 X(_and, 4000, ea000000), \
11430 X(_ands, 4000, ea100000), \
11431 X(_asr, 1000, fa40f000), \
11432 X(_asrs, 1000, fa50f000), \
11433 X(_b, e000, f000b000), \
11434 X(_bcond, d000, f0008000), \
4389b29a 11435 X(_bf, 0000, f040e001), \
f6b2b12d 11436 X(_bfcsel,0000, f000e001), \
f1c7f421 11437 X(_bfx, 0000, f060e001), \
65d1bc05 11438 X(_bfl, 0000, f000c001), \
f1c7f421 11439 X(_bflx, 0000, f070e001), \
21d799b5
NC		 11440 X(_bic, 4380, ea200000), \
11441 X(_bics, 4380, ea300000), \
e39c1607
SD		 11442 X(_cinc, 0000, ea509000), \
11443 X(_cinv, 0000, ea50a000), \
21d799b5
NC		 11444 X(_cmn, 42c0, eb100f00), \
11445 X(_cmp, 2800, ebb00f00), \
e39c1607 11446 X(_cneg, 0000, ea50b000), \
21d799b5
NC		 11447 X(_cpsie, b660, f3af8400), \
11448 X(_cpsid, b670, f3af8600), \
11449 X(_cpy, 4600, ea4f0000), \
e39c1607
SD		 11450 X(_csel, 0000, ea508000), \
11451 X(_cset, 0000, ea5f900f), \
11452 X(_csetm, 0000, ea5fa00f), \
11453 X(_csinc, 0000, ea509000), \
11454 X(_csinv, 0000, ea50a000), \
11455 X(_csneg, 0000, ea50b000), \
21d799b5 11456 X(_dec_sp,80dd, f1ad0d00), \
60f993ce 11457 X(_dls, 0000, f040e001), \
1f6234a3 11458 X(_dlstp, 0000, f000e001), \
21d799b5
NC		 11459 X(_eor, 4040, ea800000), \
11460 X(_eors, 4040, ea900000), \
11461 X(_inc_sp,00dd, f10d0d00), \
1f6234a3 11462 X(_lctp, 0000, f00fe001), \
21d799b5
NC		 11463 X(_ldmia, c800, e8900000), \
11464 X(_ldr, 6800, f8500000), \
11465 X(_ldrb, 7800, f8100000), \
11466 X(_ldrh, 8800, f8300000), \
11467 X(_ldrsb, 5600, f9100000), \
11468 X(_ldrsh, 5e00, f9300000), \
11469 X(_ldr_pc,4800, f85f0000), \
11470 X(_ldr_pc2,4800, f85f0000), \
11471 X(_ldr_sp,9800, f85d0000), \
60f993ce 11472 X(_le, 0000, f00fc001), \
1f6234a3 11473 X(_letp, 0000, f01fc001), \
21d799b5
NC		 11474 X(_lsl, 0000, fa00f000), \
11475 X(_lsls, 0000, fa10f000), \
11476 X(_lsr, 0800, fa20f000), \
11477 X(_lsrs, 0800, fa30f000), \
11478 X(_mov, 2000, ea4f0000), \
11479 X(_movs, 2000, ea5f0000), \
11480 X(_mul, 4340, fb00f000), \
11481 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11482 X(_mvn, 43c0, ea6f0000), \
11483 X(_mvns, 43c0, ea7f0000), \
11484 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11485 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11486 X(_orr, 4300, ea400000), \
11487 X(_orrs, 4300, ea500000), \
11488 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11489 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11490 X(_rev, ba00, fa90f080), \
11491 X(_rev16, ba40, fa90f090), \
11492 X(_revsh, bac0, fa90f0b0), \
11493 X(_ror, 41c0, fa60f000), \
11494 X(_rors, 41c0, fa70f000), \
11495 X(_sbc, 4180, eb600000), \
11496 X(_sbcs, 4180, eb700000), \
11497 X(_stmia, c000, e8800000), \
11498 X(_str, 6000, f8400000), \
11499 X(_strb, 7000, f8000000), \
11500 X(_strh, 8000, f8200000), \
11501 X(_str_sp,9000, f84d0000), \
11502 X(_sub, 1e00, eba00000), \
11503 X(_subs, 1e00, ebb00000), \
11504 X(_subi, 8000, f1a00000), \
11505 X(_subis, 8000, f1b00000), \
11506 X(_sxtb, b240, fa4ff080), \
11507 X(_sxth, b200, fa0ff080), \
11508 X(_tst, 4200, ea100f00), \
11509 X(_uxtb, b2c0, fa5ff080), \
11510 X(_uxth, b280, fa1ff080), \
11511 X(_nop, bf00, f3af8000), \
11512 X(_yield, bf10, f3af8001), \
11513 X(_wfe, bf20, f3af8002), \
11514 X(_wfi, bf30, f3af8003), \
60f993ce 11515 X(_wls, 0000, f040c001), \
1f6234a3 11516 X(_wlstp, 0000, f000c001), \
53c4b28b 11517 X(_sev, bf40, f3af8004), \
74db7efb
NC		 11518 X(_sevl, bf50, f3af8005), \
11519 X(_udf, de00, f7f0a000)
c19d1205
ZW		 11520
11521/* To catch errors in encoding functions, the codes are all offset by
11522 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11523 as 16-bit instructions. */
21d799b5 11524#define X(a,b,c) T_MNEM##a
c19d1205
ZW		 11525enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
11526#undef X
11527
11528#define X(a,b,c) 0x##b
11529static const unsigned short thumb_op16[] = { T16_32_TAB };
11530#define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11531#undef X
11532
11533#define X(a,b,c) 0x##c
11534static const unsigned int thumb_op32[] = { T16_32_TAB };
c921be7d
NC		 11535#define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11536#define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
c19d1205
ZW		 11537#undef X
11538#undef T16_32_TAB
11539
11540/* Thumb instruction encoders, in alphabetical order. */
11541
92e90b6e 11542/* ADDW or SUBW. */
c921be7d 11543
92e90b6e
PB		 11544static void
11545do_t_add_sub_w (void)
11546{
11547 int Rd, Rn;
11548
11549 Rd = inst.operands[0].reg;
11550 Rn = inst.operands[1].reg;
11551
539d4391
NC		 11552 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11553 is the SP-{plus,minus}-immediate form of the instruction. */
11554 if (Rn == REG_SP)
11555 constraint (Rd == REG_PC, BAD_PC);
11556 else
11557 reject_bad_reg (Rd);
fdfde340 11558
92e90b6e 11559 inst.instruction |= (Rn << 16) | (Rd << 8);
e2b0ab59 11560 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12;
92e90b6e
PB		 11561}
11562
c19d1205 11563/* Parse an add or subtract instruction. We get here with inst.instruction
33eaf5de 11564 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
c19d1205
ZW		 11565
11566static void
11567do_t_add_sub (void)
11568{
11569 int Rd, Rs, Rn;
11570
11571 Rd = inst.operands[0].reg;
11572 Rs = (inst.operands[1].present
11573 ? inst.operands[1].reg /* Rd, Rs, foo */
11574 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11575
e07e6e58 11576 if (Rd == REG_PC)
5ee91343 11577 set_pred_insn_type_last ();
e07e6e58 11578
c19d1205
ZW		 11579 if (unified_syntax)
11580 {
0110f2b8
PB		 11581 bfd_boolean flags;
11582 bfd_boolean narrow;
11583 int opcode;
11584
11585 flags = (inst.instruction == T_MNEM_adds
11586 || inst.instruction == T_MNEM_subs);
11587 if (flags)
5ee91343 11588 narrow = !in_pred_block ();
0110f2b8 11589 else
5ee91343 11590 narrow = in_pred_block ();
c19d1205 11591 if (!inst.operands[2].isreg)
b99bd4ef 11592 {
16805f35
PB		 11593 int add;
11594
5c8ed6a4
JW		 11595 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11596 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
fdfde340 11597
16805f35
PB		 11598 add = (inst.instruction == T_MNEM_add
11599 || inst.instruction == T_MNEM_adds);
0110f2b8
PB		 11600 opcode = 0;
11601 if (inst.size_req != 4)
11602 {
0110f2b8 11603 /* Attempt to use a narrow opcode, with relaxation if
477330fc 11604 appropriate. */
0110f2b8
PB		 11605 if (Rd == REG_SP && Rs == REG_SP && !flags)
11606 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
11607 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
11608 opcode = T_MNEM_add_sp;
11609 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
11610 opcode = T_MNEM_add_pc;
11611 else if (Rd <= 7 && Rs <= 7 && narrow)
11612 {
11613 if (flags)
11614 opcode = add ? T_MNEM_addis : T_MNEM_subis;
11615 else
11616 opcode = add ? T_MNEM_addi : T_MNEM_subi;
11617 }
11618 if (opcode)
11619 {
11620 inst.instruction = THUMB_OP16(opcode);
11621 inst.instruction |= (Rd << 4) | Rs;
e2b0ab59
AV		 11622 if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11623 || (inst.relocs[0].type
11624 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC))
a9f02af8
MG		 11625 {
11626 if (inst.size_req == 2)
e2b0ab59 11627 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
a9f02af8
MG		 11628 else
11629 inst.relax = opcode;
11630 }
0110f2b8
PB		 11631 }
11632 else
11633 constraint (inst.size_req == 2, BAD_HIREG);
11634 }
11635 if (inst.size_req == 4
11636 || (inst.size_req != 2 && !opcode))
11637 {
e2b0ab59
AV		 11638 constraint ((inst.relocs[0].type
11639 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC)
11640 && (inst.relocs[0].type
11641 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) ,
a9f02af8 11642 THUMB1_RELOC_ONLY);
efd81785
PB		 11643 if (Rd == REG_PC)
11644 {
fdfde340 11645 constraint (add, BAD_PC);
efd81785
PB		 11646 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
11647 _("only SUBS PC, LR, #const allowed"));
e2b0ab59 11648 constraint (inst.relocs[0].exp.X_op != O_constant,
efd81785 11649 _("expression too complex"));
e2b0ab59
AV		 11650 constraint (inst.relocs[0].exp.X_add_number < 0
11651 || inst.relocs[0].exp.X_add_number > 0xff,
efd81785
PB		 11652 _("immediate value out of range"));
11653 inst.instruction = T2_SUBS_PC_LR
e2b0ab59
AV		 11654 | inst.relocs[0].exp.X_add_number;
11655 inst.relocs[0].type = BFD_RELOC_UNUSED;
efd81785
PB		 11656 return;
11657 }
11658 else if (Rs == REG_PC)
16805f35
PB		 11659 {
11660 /* Always use addw/subw. */
11661 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
e2b0ab59 11662 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12;
16805f35
PB		 11663 }
11664 else
11665 {
11666 inst.instruction = THUMB_OP32 (inst.instruction);
11667 inst.instruction = (inst.instruction & 0xe1ffffff)
11668 | 0x10000000;
11669 if (flags)
e2b0ab59 11670 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
16805f35 11671 else
e2b0ab59 11672 inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_IMM;
16805f35 11673 }
dc4503c6
PB		 11674 inst.instruction |= Rd << 8;
11675 inst.instruction |= Rs << 16;
0110f2b8 11676 }
b99bd4ef 11677 }
c19d1205
ZW		 11678 else
11679 {
e2b0ab59 11680 unsigned int value = inst.relocs[0].exp.X_add_number;
5f4cb198
NC		 11681 unsigned int shift = inst.operands[2].shift_kind;
11682
c19d1205
ZW		 11683 Rn = inst.operands[2].reg;
11684 /* See if we can do this with a 16-bit instruction. */
11685 if (!inst.operands[2].shifted && inst.size_req != 4)
11686 {
e27ec89e
PB		 11687 if (Rd > 7 || Rs > 7 || Rn > 7)
11688 narrow = FALSE;
11689
11690 if (narrow)
c19d1205 11691 {
e27ec89e
PB		 11692 inst.instruction = ((inst.instruction == T_MNEM_adds
11693 || inst.instruction == T_MNEM_add)
c19d1205
ZW		 11694 ? T_OPCODE_ADD_R3
11695 : T_OPCODE_SUB_R3);
11696 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
11697 return;
11698 }
b99bd4ef 11699
7e806470 11700 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
c19d1205 11701 {
7e806470
PB		 11702 /* Thumb-1 cores (except v6-M) require at least one high
11703 register in a narrow non flag setting add. */
11704 if (Rd > 7 || Rn > 7
11705 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
11706 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
c19d1205 11707 {
7e806470
PB		 11708 if (Rd == Rn)
11709 {
11710 Rn = Rs;
11711 Rs = Rd;
11712 }
c19d1205
ZW		 11713 inst.instruction = T_OPCODE_ADD_HI;
11714 inst.instruction |= (Rd & 8) << 4;
11715 inst.instruction |= (Rd & 7);
11716 inst.instruction |= Rn << 3;
11717 return;
11718 }
c19d1205
ZW		 11719 }
11720 }
c921be7d 11721
fdfde340 11722 constraint (Rd == REG_PC, BAD_PC);
5c8ed6a4
JW		 11723 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11724 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
fdfde340
JM		 11725 constraint (Rs == REG_PC, BAD_PC);
11726 reject_bad_reg (Rn);
11727
c19d1205
ZW		 11728 /* If we get here, it can't be done in 16 bits. */
11729 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
11730 _("shift must be constant"));
11731 inst.instruction = THUMB_OP32 (inst.instruction);
11732 inst.instruction |= Rd << 8;
11733 inst.instruction |= Rs << 16;
5f4cb198
NC		 11734 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
11735 _("shift value over 3 not allowed in thumb mode"));
11736 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
11737 _("only LSL shift allowed in thumb mode"));
c19d1205
ZW		 11738 encode_thumb32_shifted_operand (2);
11739 }
11740 }
11741 else
11742 {
11743 constraint (inst.instruction == T_MNEM_adds
11744 || inst.instruction == T_MNEM_subs,
11745 BAD_THUMB32);
b99bd4ef 11746
c19d1205 11747 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
b99bd4ef 11748 {
c19d1205
ZW		 11749 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
11750 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
11751 BAD_HIREG);
11752
11753 inst.instruction = (inst.instruction == T_MNEM_add
11754 ? 0x0000 : 0x8000);
11755 inst.instruction |= (Rd << 4) | Rs;
e2b0ab59 11756 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
b99bd4ef
NC		 11757 return;
11758 }
11759
c19d1205
ZW		 11760 Rn = inst.operands[2].reg;
11761 constraint (inst.operands[2].shifted, _("unshifted register required"));
b99bd4ef 11762
c19d1205
ZW		 11763 /* We now have Rd, Rs, and Rn set to registers. */
11764 if (Rd > 7 || Rs > 7 || Rn > 7)
b99bd4ef 11765 {
c19d1205
ZW		 11766 /* Can't do this for SUB. */
11767 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
11768 inst.instruction = T_OPCODE_ADD_HI;
11769 inst.instruction |= (Rd & 8) << 4;
11770 inst.instruction |= (Rd & 7);
11771 if (Rs == Rd)
11772 inst.instruction |= Rn << 3;
11773 else if (Rn == Rd)
11774 inst.instruction |= Rs << 3;
11775 else
11776 constraint (1, _("dest must overlap one source register"));
11777 }
11778 else
11779 {
11780 inst.instruction = (inst.instruction == T_MNEM_add
11781 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
11782 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
b99bd4ef 11783 }
b99bd4ef 11784 }
b99bd4ef
NC		 11785}
11786
c19d1205
ZW		 11787static void
11788do_t_adr (void)
11789{
fdfde340
JM		 11790 unsigned Rd;
11791
11792 Rd = inst.operands[0].reg;
11793 reject_bad_reg (Rd);
11794
11795 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
0110f2b8
PB		 11796 {
11797 /* Defer to section relaxation. */
11798 inst.relax = inst.instruction;
11799 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340 11800 inst.instruction |= Rd << 4;
0110f2b8
PB		 11801 }
11802 else if (unified_syntax && inst.size_req != 2)
e9f89963 11803 {
0110f2b8 11804 /* Generate a 32-bit opcode. */
e9f89963 11805 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340 11806 inst.instruction |= Rd << 8;
e2b0ab59
AV		 11807 inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_PC12;
11808 inst.relocs[0].pc_rel = 1;
e9f89963
PB		 11809 }
11810 else
11811 {
0110f2b8 11812 /* Generate a 16-bit opcode. */
e9f89963 11813 inst.instruction = THUMB_OP16 (inst.instruction);
e2b0ab59
AV		 11814 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
11815 inst.relocs[0].exp.X_add_number -= 4; /* PC relative adjust. */
11816 inst.relocs[0].pc_rel = 1;
fdfde340 11817 inst.instruction |= Rd << 4;
e9f89963 11818 }
52a86f84 11819
e2b0ab59
AV		 11820 if (inst.relocs[0].exp.X_op == O_symbol
11821 && inst.relocs[0].exp.X_add_symbol != NULL
11822 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
11823 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
11824 inst.relocs[0].exp.X_add_number += 1;
c19d1205 11825}
b99bd4ef 11826
c19d1205
ZW		 11827/* Arithmetic instructions for which there is just one 16-bit
11828 instruction encoding, and it allows only two low registers.
11829 For maximal compatibility with ARM syntax, we allow three register
11830 operands even when Thumb-32 instructions are not available, as long
11831 as the first two are identical. For instance, both "sbc r0,r1" and
11832 "sbc r0,r0,r1" are allowed. */
b99bd4ef 11833static void
c19d1205 11834do_t_arit3 (void)
b99bd4ef 11835{
c19d1205 11836 int Rd, Rs, Rn;
b99bd4ef 11837
c19d1205
ZW		 11838 Rd = inst.operands[0].reg;
11839 Rs = (inst.operands[1].present
11840 ? inst.operands[1].reg /* Rd, Rs, foo */
11841 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11842 Rn = inst.operands[2].reg;
b99bd4ef 11843
fdfde340
JM		 11844 reject_bad_reg (Rd);
11845 reject_bad_reg (Rs);
11846 if (inst.operands[2].isreg)
11847 reject_bad_reg (Rn);
11848
c19d1205 11849 if (unified_syntax)
b99bd4ef 11850 {
c19d1205
ZW		 11851 if (!inst.operands[2].isreg)
11852 {
11853 /* For an immediate, we always generate a 32-bit opcode;
11854 section relaxation will shrink it later if possible. */
11855 inst.instruction = THUMB_OP32 (inst.instruction);
11856 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11857 inst.instruction |= Rd << 8;
11858 inst.instruction |= Rs << 16;
e2b0ab59 11859 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
c19d1205
ZW		 11860 }
11861 else
11862 {
e27ec89e
PB		 11863 bfd_boolean narrow;
11864
c19d1205 11865 /* See if we can do this with a 16-bit instruction. */
e27ec89e 11866 if (THUMB_SETS_FLAGS (inst.instruction))
5ee91343 11867 narrow = !in_pred_block ();
e27ec89e 11868 else
5ee91343 11869 narrow = in_pred_block ();
e27ec89e
PB		 11870
11871 if (Rd > 7 || Rn > 7 || Rs > 7)
11872 narrow = FALSE;
11873 if (inst.operands[2].shifted)
11874 narrow = FALSE;
11875 if (inst.size_req == 4)
11876 narrow = FALSE;
11877
11878 if (narrow
c19d1205
ZW		 11879 && Rd == Rs)
11880 {
11881 inst.instruction = THUMB_OP16 (inst.instruction);
11882 inst.instruction |= Rd;
11883 inst.instruction |= Rn << 3;
11884 return;
11885 }
b99bd4ef 11886
c19d1205
ZW		 11887 /* If we get here, it can't be done in 16 bits. */
11888 constraint (inst.operands[2].shifted
11889 && inst.operands[2].immisreg,
11890 _("shift must be constant"));
11891 inst.instruction = THUMB_OP32 (inst.instruction);
11892 inst.instruction |= Rd << 8;
11893 inst.instruction |= Rs << 16;
11894 encode_thumb32_shifted_operand (2);
11895 }
a737bd4d 11896 }
c19d1205 11897 else
b99bd4ef 11898 {
c19d1205
ZW		 11899 /* On its face this is a lie - the instruction does set the
11900 flags. However, the only supported mnemonic in this mode
11901 says it doesn't. */
11902 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
a737bd4d 11903
c19d1205
ZW		 11904 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
11905 _("unshifted register required"));
11906 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
11907 constraint (Rd != Rs,
11908 _("dest and source1 must be the same register"));
a737bd4d 11909
c19d1205
ZW		 11910 inst.instruction = THUMB_OP16 (inst.instruction);
11911 inst.instruction |= Rd;
11912 inst.instruction |= Rn << 3;
b99bd4ef 11913 }
a737bd4d 11914}
b99bd4ef 11915
c19d1205
ZW		 11916/* Similarly, but for instructions where the arithmetic operation is
11917 commutative, so we can allow either of them to be different from
11918 the destination operand in a 16-bit instruction. For instance, all
11919 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11920 accepted. */
11921static void
11922do_t_arit3c (void)
a737bd4d 11923{
c19d1205 11924 int Rd, Rs, Rn;
b99bd4ef 11925
c19d1205
ZW		 11926 Rd = inst.operands[0].reg;
11927 Rs = (inst.operands[1].present
11928 ? inst.operands[1].reg /* Rd, Rs, foo */
11929 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11930 Rn = inst.operands[2].reg;
c921be7d 11931
fdfde340
JM		 11932 reject_bad_reg (Rd);
11933 reject_bad_reg (Rs);
11934 if (inst.operands[2].isreg)
11935 reject_bad_reg (Rn);
a737bd4d 11936
c19d1205 11937 if (unified_syntax)
a737bd4d 11938 {
c19d1205 11939 if (!inst.operands[2].isreg)
b99bd4ef 11940 {
c19d1205
ZW		 11941 /* For an immediate, we always generate a 32-bit opcode;
11942 section relaxation will shrink it later if possible. */
11943 inst.instruction = THUMB_OP32 (inst.instruction);
11944 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11945 inst.instruction |= Rd << 8;
11946 inst.instruction |= Rs << 16;
e2b0ab59 11947 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
b99bd4ef 11948 }
c19d1205 11949 else
a737bd4d 11950 {
e27ec89e
PB		 11951 bfd_boolean narrow;
11952
c19d1205 11953 /* See if we can do this with a 16-bit instruction. */
e27ec89e 11954 if (THUMB_SETS_FLAGS (inst.instruction))
5ee91343 11955 narrow = !in_pred_block ();
e27ec89e 11956 else
5ee91343 11957 narrow = in_pred_block ();
e27ec89e
PB		 11958
11959 if (Rd > 7 || Rn > 7 || Rs > 7)
11960 narrow = FALSE;
11961 if (inst.operands[2].shifted)
11962 narrow = FALSE;
11963 if (inst.size_req == 4)
11964 narrow = FALSE;
11965
11966 if (narrow)
a737bd4d 11967 {
c19d1205 11968 if (Rd == Rs)
a737bd4d 11969 {
c19d1205
ZW		 11970 inst.instruction = THUMB_OP16 (inst.instruction);
11971 inst.instruction |= Rd;
11972 inst.instruction |= Rn << 3;
11973 return;
a737bd4d 11974 }
c19d1205 11975 if (Rd == Rn)
a737bd4d 11976 {
c19d1205
ZW		 11977 inst.instruction = THUMB_OP16 (inst.instruction);
11978 inst.instruction |= Rd;
11979 inst.instruction |= Rs << 3;
11980 return;
a737bd4d
NC		 11981 }
11982 }
c19d1205
ZW		 11983
11984 /* If we get here, it can't be done in 16 bits. */
11985 constraint (inst.operands[2].shifted
11986 && inst.operands[2].immisreg,
11987 _("shift must be constant"));
11988 inst.instruction = THUMB_OP32 (inst.instruction);
11989 inst.instruction |= Rd << 8;
11990 inst.instruction |= Rs << 16;
11991 encode_thumb32_shifted_operand (2);
a737bd4d 11992 }
b99bd4ef 11993 }
c19d1205
ZW		 11994 else
11995 {
11996 /* On its face this is a lie - the instruction does set the
11997 flags. However, the only supported mnemonic in this mode
11998 says it doesn't. */
11999 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
a737bd4d 12000
c19d1205
ZW		 12001 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
12002 _("unshifted register required"));
12003 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
12004
12005 inst.instruction = THUMB_OP16 (inst.instruction);
12006 inst.instruction |= Rd;
12007
12008 if (Rd == Rs)
12009 inst.instruction |= Rn << 3;
12010 else if (Rd == Rn)
12011 inst.instruction |= Rs << 3;
12012 else
12013 constraint (1, _("dest must overlap one source register"));
12014 }
a737bd4d
NC		 12015}
12016
c19d1205
ZW		 12017static void
12018do_t_bfc (void)
a737bd4d 12019{
fdfde340 12020 unsigned Rd;
c19d1205
ZW		 12021 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
12022 constraint (msb > 32, _("bit-field extends past end of register"));
12023 /* The instruction encoding stores the LSB and MSB,
12024 not the LSB and width. */
fdfde340
JM		 12025 Rd = inst.operands[0].reg;
12026 reject_bad_reg (Rd);
12027 inst.instruction |= Rd << 8;
c19d1205
ZW		 12028 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
12029 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
12030 inst.instruction |= msb - 1;
b99bd4ef
NC		 12031}
12032
c19d1205
ZW		 12033static void
12034do_t_bfi (void)
b99bd4ef 12035{
fdfde340 12036 int Rd, Rn;
c19d1205 12037 unsigned int msb;
b99bd4ef 12038
fdfde340
JM		 12039 Rd = inst.operands[0].reg;
12040 reject_bad_reg (Rd);
12041
c19d1205
ZW		 12042 /* #0 in second position is alternative syntax for bfc, which is
12043 the same instruction but with REG_PC in the Rm field. */
12044 if (!inst.operands[1].isreg)
fdfde340
JM		 12045 Rn = REG_PC;
12046 else
12047 {
12048 Rn = inst.operands[1].reg;
12049 reject_bad_reg (Rn);
12050 }
b99bd4ef 12051
c19d1205
ZW		 12052 msb = inst.operands[2].imm + inst.operands[3].imm;
12053 constraint (msb > 32, _("bit-field extends past end of register"));
12054 /* The instruction encoding stores the LSB and MSB,
12055 not the LSB and width. */
fdfde340
JM		 12056 inst.instruction |= Rd << 8;
12057 inst.instruction |= Rn << 16;
c19d1205
ZW		 12058 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
12059 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
12060 inst.instruction |= msb - 1;
b99bd4ef
NC		 12061}
12062
c19d1205
ZW		 12063static void
12064do_t_bfx (void)
b99bd4ef 12065{
fdfde340
JM		 12066 unsigned Rd, Rn;
12067
12068 Rd = inst.operands[0].reg;
12069 Rn = inst.operands[1].reg;
12070
12071 reject_bad_reg (Rd);
12072 reject_bad_reg (Rn);
12073
c19d1205
ZW		 12074 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
12075 _("bit-field extends past end of register"));
fdfde340
JM		 12076 inst.instruction |= Rd << 8;
12077 inst.instruction |= Rn << 16;
c19d1205
ZW		 12078 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
12079 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
12080 inst.instruction |= inst.operands[3].imm - 1;
12081}
b99bd4ef 12082
c19d1205
ZW		 12083/* ARM V5 Thumb BLX (argument parse)
12084 BLX <target_addr> which is BLX(1)
12085 BLX <Rm> which is BLX(2)
12086 Unfortunately, there are two different opcodes for this mnemonic.
12087 So, the insns[].value is not used, and the code here zaps values
12088 into inst.instruction.
b99bd4ef 12089
c19d1205
ZW		 12090 ??? How to take advantage of the additional two bits of displacement
12091 available in Thumb32 mode? Need new relocation? */
b99bd4ef 12092
c19d1205
ZW		 12093static void
12094do_t_blx (void)
12095{
5ee91343 12096 set_pred_insn_type_last ();
e07e6e58 12097
c19d1205 12098 if (inst.operands[0].isreg)
fdfde340
JM		 12099 {
12100 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
12101 /* We have a register, so this is BLX(2). */
12102 inst.instruction |= inst.operands[0].reg << 3;
12103 }
b99bd4ef
NC		 12104 else
12105 {
c19d1205 12106 /* No register. This must be BLX(1). */
2fc8bdac 12107 inst.instruction = 0xf000e800;
0855e32b 12108 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
b99bd4ef
NC		 12109 }
12110}
12111
c19d1205
ZW		 12112static void
12113do_t_branch (void)
b99bd4ef 12114{
0110f2b8 12115 int opcode;
dfa9f0d5 12116 int cond;
2fe88214 12117 bfd_reloc_code_real_type reloc;
dfa9f0d5 12118
e07e6e58 12119 cond = inst.cond;
5ee91343 12120 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN);
e07e6e58 12121
5ee91343 12122 if (in_pred_block ())
dfa9f0d5
PB		 12123 {
12124 /* Conditional branches inside IT blocks are encoded as unconditional
477330fc 12125 branches. */
dfa9f0d5 12126 cond = COND_ALWAYS;
dfa9f0d5
PB		 12127 }
12128 else
12129 cond = inst.cond;
12130
12131 if (cond != COND_ALWAYS)
0110f2b8
PB		 12132 opcode = T_MNEM_bcond;
12133 else
12134 opcode = inst.instruction;
12135
12d6b0b7
RS		 12136 if (unified_syntax
12137 && (inst.size_req == 4
10960bfb
PB		 12138 || (inst.size_req != 2
12139 && (inst.operands[0].hasreloc
e2b0ab59 12140 || inst.relocs[0].exp.X_op == O_constant))))
c19d1205 12141 {
0110f2b8 12142 inst.instruction = THUMB_OP32(opcode);
dfa9f0d5 12143 if (cond == COND_ALWAYS)
9ae92b05 12144 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
c19d1205
ZW		 12145 else
12146 {
ff8646ee
TP		 12147 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2),
12148 _("selected architecture does not support "
12149 "wide conditional branch instruction"));
12150
9c2799c2 12151 gas_assert (cond != 0xF);
dfa9f0d5 12152 inst.instruction |= cond << 22;
9ae92b05 12153 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
c19d1205
ZW		 12154 }
12155 }
b99bd4ef
NC		 12156 else
12157 {
0110f2b8 12158 inst.instruction = THUMB_OP16(opcode);
dfa9f0d5 12159 if (cond == COND_ALWAYS)
9ae92b05 12160 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
c19d1205 12161 else
b99bd4ef 12162 {
dfa9f0d5 12163 inst.instruction |= cond << 8;
9ae92b05 12164 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
b99bd4ef 12165 }
0110f2b8
PB		 12166 /* Allow section relaxation. */
12167 if (unified_syntax && inst.size_req != 2)
12168 inst.relax = opcode;
b99bd4ef 12169 }
e2b0ab59
AV		 12170 inst.relocs[0].type = reloc;
12171 inst.relocs[0].pc_rel = 1;
b99bd4ef
NC		 12172}
12173
8884b720 12174/* Actually do the work for Thumb state bkpt and hlt. The only difference
bacebabc 12175 between the two is the maximum immediate allowed - which is passed in
8884b720 12176 RANGE. */
b99bd4ef 12177static void
8884b720 12178do_t_bkpt_hlt1 (int range)
b99bd4ef 12179{
dfa9f0d5
PB		 12180 constraint (inst.cond != COND_ALWAYS,
12181 _("instruction is always unconditional"));
c19d1205 12182 if (inst.operands[0].present)
b99bd4ef 12183 {
8884b720 12184 constraint (inst.operands[0].imm > range,
c19d1205
ZW		 12185 _("immediate value out of range"));
12186 inst.instruction |= inst.operands[0].imm;
b99bd4ef 12187 }
8884b720 12188
5ee91343 12189 set_pred_insn_type (NEUTRAL_IT_INSN);
8884b720
MGD		 12190}
12191
12192static void
12193do_t_hlt (void)
12194{
12195 do_t_bkpt_hlt1 (63);
12196}
12197
12198static void
12199do_t_bkpt (void)
12200{
12201 do_t_bkpt_hlt1 (255);
b99bd4ef
NC		 12202}
12203
12204static void
c19d1205 12205do_t_branch23 (void)
b99bd4ef 12206{
5ee91343 12207 set_pred_insn_type_last ();
0855e32b 12208 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
fa94de6b 12209
0855e32b
NS		 12210 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
12211 this file. We used to simply ignore the PLT reloc type here --
12212 the branch encoding is now needed to deal with TLSCALL relocs.
12213 So if we see a PLT reloc now, put it back to how it used to be to
12214 keep the preexisting behaviour. */
e2b0ab59
AV		 12215 if (inst.relocs[0].type == BFD_RELOC_ARM_PLT32)
12216 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH23;
90e4755a 12217
4343666d 12218#if defined(OBJ_COFF)
c19d1205
ZW		 12219 /* If the destination of the branch is a defined symbol which does not have
12220 the THUMB_FUNC attribute, then we must be calling a function which has
12221 the (interfacearm) attribute. We look for the Thumb entry point to that
12222 function and change the branch to refer to that function instead. */
e2b0ab59
AV		 12223 if ( inst.relocs[0].exp.X_op == O_symbol
12224 && inst.relocs[0].exp.X_add_symbol != NULL
12225 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
12226 && ! THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
12227 inst.relocs[0].exp.X_add_symbol
12228 = find_real_start (inst.relocs[0].exp.X_add_symbol);
4343666d 12229#endif
90e4755a
RE		 12230}
12231
12232static void
c19d1205 12233do_t_bx (void)
90e4755a 12234{
5ee91343 12235 set_pred_insn_type_last ();
c19d1205
ZW		 12236 inst.instruction |= inst.operands[0].reg << 3;
12237 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
12238 should cause the alignment to be checked once it is known. This is
12239 because BX PC only works if the instruction is word aligned. */
12240}
90e4755a 12241
c19d1205
ZW		 12242static void
12243do_t_bxj (void)
12244{
fdfde340 12245 int Rm;
90e4755a 12246
5ee91343 12247 set_pred_insn_type_last ();
fdfde340
JM		 12248 Rm = inst.operands[0].reg;
12249 reject_bad_reg (Rm);
12250 inst.instruction |= Rm << 16;
90e4755a
RE		 12251}
12252
12253static void
c19d1205 12254do_t_clz (void)
90e4755a 12255{
fdfde340
JM		 12256 unsigned Rd;
12257 unsigned Rm;
12258
12259 Rd = inst.operands[0].reg;
12260 Rm = inst.operands[1].reg;
12261
12262 reject_bad_reg (Rd);
12263 reject_bad_reg (Rm);
12264
12265 inst.instruction |= Rd << 8;
12266 inst.instruction |= Rm << 16;
12267 inst.instruction |= Rm;
c19d1205 12268}
90e4755a 12269
e39c1607
SD		 12270/* For the Armv8.1-M conditional instructions. */
12271static void
12272do_t_cond (void)
12273{
12274 unsigned Rd, Rn, Rm;
12275 signed int cond;
12276
12277 constraint (inst.cond != COND_ALWAYS, BAD_COND);
12278
12279 Rd = inst.operands[0].reg;
12280 switch (inst.instruction)
12281 {
12282 case T_MNEM_csinc:
12283 case T_MNEM_csinv:
12284 case T_MNEM_csneg:
12285 case T_MNEM_csel:
12286 Rn = inst.operands[1].reg;
12287 Rm = inst.operands[2].reg;
12288 cond = inst.operands[3].imm;
12289 constraint (Rn == REG_SP, BAD_SP);
12290 constraint (Rm == REG_SP, BAD_SP);
12291 break;
12292
12293 case T_MNEM_cinc:
12294 case T_MNEM_cinv:
12295 case T_MNEM_cneg:
12296 Rn = inst.operands[1].reg;
12297 cond = inst.operands[2].imm;
12298 /* Invert the last bit to invert the cond. */
12299 cond = TOGGLE_BIT (cond, 0);
12300 constraint (Rn == REG_SP, BAD_SP);
12301 Rm = Rn;
12302 break;
12303
12304 case T_MNEM_csetm:
12305 case T_MNEM_cset:
12306 cond = inst.operands[1].imm;
12307 /* Invert the last bit to invert the cond. */
12308 cond = TOGGLE_BIT (cond, 0);
12309 Rn = REG_PC;
12310 Rm = REG_PC;
12311 break;
12312
12313 default: abort ();
12314 }
12315
12316 set_pred_insn_type (OUTSIDE_PRED_INSN);
12317 inst.instruction = THUMB_OP32 (inst.instruction);
12318 inst.instruction |= Rd << 8;
12319 inst.instruction |= Rn << 16;
12320 inst.instruction |= Rm;
12321 inst.instruction |= cond << 4;
12322}
12323
91d8b670
JG		 12324static void
12325do_t_csdb (void)
12326{
5ee91343 12327 set_pred_insn_type (OUTSIDE_PRED_INSN);
91d8b670
JG		 12328}
12329
dfa9f0d5
PB		 12330static void
12331do_t_cps (void)
12332{
5ee91343 12333 set_pred_insn_type (OUTSIDE_PRED_INSN);
dfa9f0d5
PB		 12334 inst.instruction |= inst.operands[0].imm;
12335}
12336
c19d1205
ZW		 12337static void
12338do_t_cpsi (void)
12339{
5ee91343 12340 set_pred_insn_type (OUTSIDE_PRED_INSN);
c19d1205 12341 if (unified_syntax
62b3e311
PB		 12342 && (inst.operands[1].present || inst.size_req == 4)
12343 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
90e4755a 12344 {
c19d1205
ZW		 12345 unsigned int imod = (inst.instruction & 0x0030) >> 4;
12346 inst.instruction = 0xf3af8000;
12347 inst.instruction |= imod << 9;
12348 inst.instruction |= inst.operands[0].imm << 5;
12349 if (inst.operands[1].present)
12350 inst.instruction |= 0x100 | inst.operands[1].imm;
90e4755a 12351 }
c19d1205 12352 else
90e4755a 12353 {
62b3e311
PB		 12354 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
12355 && (inst.operands[0].imm & 4),
12356 _("selected processor does not support 'A' form "
12357 "of this instruction"));
12358 constraint (inst.operands[1].present || inst.size_req == 4,
c19d1205
ZW		 12359 _("Thumb does not support the 2-argument "
12360 "form of this instruction"));
12361 inst.instruction |= inst.operands[0].imm;
90e4755a 12362 }
90e4755a
RE		 12363}
12364
c19d1205
ZW		 12365/* THUMB CPY instruction (argument parse). */
12366
90e4755a 12367static void
c19d1205 12368do_t_cpy (void)
90e4755a 12369{
c19d1205 12370 if (inst.size_req == 4)
90e4755a 12371 {
c19d1205
ZW		 12372 inst.instruction = THUMB_OP32 (T_MNEM_mov);
12373 inst.instruction |= inst.operands[0].reg << 8;
12374 inst.instruction |= inst.operands[1].reg;
90e4755a 12375 }
c19d1205 12376 else
90e4755a 12377 {
c19d1205
ZW		 12378 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
12379 inst.instruction |= (inst.operands[0].reg & 0x7);
12380 inst.instruction |= inst.operands[1].reg << 3;
90e4755a 12381 }
90e4755a
RE		 12382}
12383
90e4755a 12384static void
25fe350b 12385do_t_cbz (void)
90e4755a 12386{
5ee91343 12387 set_pred_insn_type (OUTSIDE_PRED_INSN);
c19d1205
ZW		 12388 constraint (inst.operands[0].reg > 7, BAD_HIREG);
12389 inst.instruction |= inst.operands[0].reg;
e2b0ab59
AV		 12390 inst.relocs[0].pc_rel = 1;
12391 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH7;
c19d1205 12392}
90e4755a 12393
62b3e311
PB		 12394static void
12395do_t_dbg (void)
12396{
12397 inst.instruction |= inst.operands[0].imm;
12398}
12399
12400static void
12401do_t_div (void)
12402{
fdfde340
JM		 12403 unsigned Rd, Rn, Rm;
12404
12405 Rd = inst.operands[0].reg;
12406 Rn = (inst.operands[1].present
12407 ? inst.operands[1].reg : Rd);
12408 Rm = inst.operands[2].reg;
12409
12410 reject_bad_reg (Rd);
12411 reject_bad_reg (Rn);
12412 reject_bad_reg (Rm);
12413
12414 inst.instruction |= Rd << 8;
12415 inst.instruction |= Rn << 16;
12416 inst.instruction |= Rm;
62b3e311
PB		 12417}
12418
c19d1205
ZW		 12419static void
12420do_t_hint (void)
12421{
12422 if (unified_syntax && inst.size_req == 4)
12423 inst.instruction = THUMB_OP32 (inst.instruction);
12424 else
12425 inst.instruction = THUMB_OP16 (inst.instruction);
12426}
90e4755a 12427
c19d1205
ZW		 12428static void
12429do_t_it (void)
12430{
12431 unsigned int cond = inst.operands[0].imm;
e27ec89e 12432
5ee91343
AV		 12433 set_pred_insn_type (IT_INSN);
12434 now_pred.mask = (inst.instruction & 0xf) | 0x10;
12435 now_pred.cc = cond;
12436 now_pred.warn_deprecated = FALSE;
12437 now_pred.type = SCALAR_PRED;
e27ec89e
PB		 12438
12439 /* If the condition is a negative condition, invert the mask. */
c19d1205 12440 if ((cond & 0x1) == 0x0)
90e4755a 12441 {
c19d1205 12442 unsigned int mask = inst.instruction & 0x000f;
90e4755a 12443
c19d1205 12444 if ((mask & 0x7) == 0)
5a01bb1d
MGD		 12445 {
12446 /* No conversion needed. */
5ee91343 12447 now_pred.block_length = 1;
5a01bb1d 12448 }
c19d1205 12449 else if ((mask & 0x3) == 0)
5a01bb1d
MGD		 12450 {
12451 mask ^= 0x8;
5ee91343 12452 now_pred.block_length = 2;
5a01bb1d 12453 }
e27ec89e 12454 else if ((mask & 0x1) == 0)
5a01bb1d
MGD		 12455 {
12456 mask ^= 0xC;
5ee91343 12457 now_pred.block_length = 3;
5a01bb1d 12458 }
c19d1205 12459 else
5a01bb1d
MGD		 12460 {
12461 mask ^= 0xE;
5ee91343 12462 now_pred.block_length = 4;
5a01bb1d 12463 }
90e4755a 12464
e27ec89e
PB		 12465 inst.instruction &= 0xfff0;
12466 inst.instruction |= mask;
c19d1205 12467 }
90e4755a 12468
c19d1205
ZW		 12469 inst.instruction |= cond << 4;
12470}
90e4755a 12471
3c707909
PB		 12472/* Helper function used for both push/pop and ldm/stm. */
12473static void
4b5a202f
AV		 12474encode_thumb2_multi (bfd_boolean do_io, int base, unsigned mask,
12475 bfd_boolean writeback)
3c707909 12476{
4b5a202f 12477 bfd_boolean load, store;
3c707909 12478
4b5a202f
AV		 12479 gas_assert (base != -1 || !do_io);
12480 load = do_io && ((inst.instruction & (1 << 20)) != 0);
12481 store = do_io && !load;
3c707909
PB		 12482
12483 if (mask & (1 << 13))
12484 inst.error = _("SP not allowed in register list");
1e5b0379 12485
4b5a202f 12486 if (do_io && (mask & (1 << base)) != 0
1e5b0379
NC		 12487 && writeback)
12488 inst.error = _("having the base register in the register list when "
12489 "using write back is UNPREDICTABLE");
12490
3c707909
PB		 12491 if (load)
12492 {
e07e6e58 12493 if (mask & (1 << 15))
477330fc
RM		 12494 {
12495 if (mask & (1 << 14))
12496 inst.error = _("LR and PC should not both be in register list");
12497 else
5ee91343 12498 set_pred_insn_type_last ();
477330fc 12499 }
3c707909 12500 }
4b5a202f 12501 else if (store)
3c707909
PB		 12502 {
12503 if (mask & (1 << 15))
12504 inst.error = _("PC not allowed in register list");
3c707909
PB		 12505 }
12506
4b5a202f 12507 if (do_io && ((mask & (mask - 1)) == 0))
3c707909
PB		 12508 {
12509 /* Single register transfers implemented as str/ldr. */
12510 if (writeback)
12511 {
12512 if (inst.instruction & (1 << 23))
12513 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
12514 else
12515 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
12516 }
12517 else
12518 {
12519 if (inst.instruction & (1 << 23))
12520 inst.instruction = 0x00800000; /* ia -> [base] */
12521 else
12522 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
12523 }
12524
12525 inst.instruction |= 0xf8400000;
12526 if (load)
12527 inst.instruction |= 0x00100000;
12528
5f4273c7 12529 mask = ffs (mask) - 1;
3c707909
PB		 12530 mask <<= 12;
12531 }
12532 else if (writeback)
12533 inst.instruction |= WRITE_BACK;
12534
12535 inst.instruction |= mask;
4b5a202f
AV		 12536 if (do_io)
12537 inst.instruction |= base << 16;
3c707909
PB		 12538}
12539
c19d1205
ZW		 12540static void
12541do_t_ldmstm (void)
12542{
12543 /* This really doesn't seem worth it. */
e2b0ab59 12544 constraint (inst.relocs[0].type != BFD_RELOC_UNUSED,
c19d1205
ZW		 12545 _("expression too complex"));
12546 constraint (inst.operands[1].writeback,
12547 _("Thumb load/store multiple does not support {reglist}^"));
90e4755a 12548
c19d1205
ZW		 12549 if (unified_syntax)
12550 {
3c707909
PB		 12551 bfd_boolean narrow;
12552 unsigned mask;
12553
12554 narrow = FALSE;
c19d1205
ZW		 12555 /* See if we can use a 16-bit instruction. */
12556 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
12557 && inst.size_req != 4
3c707909 12558 && !(inst.operands[1].imm & ~0xff))
90e4755a 12559 {
3c707909 12560 mask = 1 << inst.operands[0].reg;
90e4755a 12561
eab4f823 12562 if (inst.operands[0].reg <= 7)
90e4755a 12563 {
3c707909 12564 if (inst.instruction == T_MNEM_stmia
eab4f823
MGD		 12565 ? inst.operands[0].writeback
12566 : (inst.operands[0].writeback
12567 == !(inst.operands[1].imm & mask)))
477330fc 12568 {
eab4f823
MGD		 12569 if (inst.instruction == T_MNEM_stmia
12570 && (inst.operands[1].imm & mask)
12571 && (inst.operands[1].imm & (mask - 1)))
12572 as_warn (_("value stored for r%d is UNKNOWN"),
12573 inst.operands[0].reg);
3c707909 12574
eab4f823
MGD		 12575 inst.instruction = THUMB_OP16 (inst.instruction);
12576 inst.instruction |= inst.operands[0].reg << 8;
12577 inst.instruction |= inst.operands[1].imm;
12578 narrow = TRUE;
12579 }
12580 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
12581 {
12582 /* This means 1 register in reg list one of 3 situations:
12583 1. Instruction is stmia, but without writeback.
12584 2. lmdia without writeback, but with Rn not in
477330fc 12585 reglist.
eab4f823
MGD		 12586 3. ldmia with writeback, but with Rn in reglist.
12587 Case 3 is UNPREDICTABLE behaviour, so we handle
12588 case 1 and 2 which can be converted into a 16-bit
12589 str or ldr. The SP cases are handled below. */
12590 unsigned long opcode;
12591 /* First, record an error for Case 3. */
12592 if (inst.operands[1].imm & mask
12593 && inst.operands[0].writeback)
fa94de6b 12594 inst.error =
eab4f823
MGD		 12595 _("having the base register in the register list when "
12596 "using write back is UNPREDICTABLE");
fa94de6b
RM		 12597
12598 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
eab4f823
MGD		 12599 : T_MNEM_ldr);
12600 inst.instruction = THUMB_OP16 (opcode);
12601 inst.instruction |= inst.operands[0].reg << 3;
12602 inst.instruction |= (ffs (inst.operands[1].imm)-1);
12603 narrow = TRUE;
12604 }
90e4755a 12605 }
eab4f823 12606 else if (inst.operands[0] .reg == REG_SP)
90e4755a 12607 {
eab4f823
MGD		 12608 if (inst.operands[0].writeback)
12609 {
fa94de6b 12610 inst.instruction =
eab4f823 12611 THUMB_OP16 (inst.instruction == T_MNEM_stmia
477330fc 12612 ? T_MNEM_push : T_MNEM_pop);
eab4f823 12613 inst.instruction |= inst.operands[1].imm;
477330fc 12614 narrow = TRUE;
eab4f823
MGD		 12615 }
12616 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
12617 {
fa94de6b 12618 inst.instruction =
eab4f823 12619 THUMB_OP16 (inst.instruction == T_MNEM_stmia
477330fc 12620 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
eab4f823 12621 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
477330fc 12622 narrow = TRUE;
eab4f823 12623 }
90e4755a 12624 }
3c707909
PB		 12625 }
12626
12627 if (!narrow)
12628 {
c19d1205
ZW		 12629 if (inst.instruction < 0xffff)
12630 inst.instruction = THUMB_OP32 (inst.instruction);
3c707909 12631
4b5a202f
AV		 12632 encode_thumb2_multi (TRUE /* do_io */, inst.operands[0].reg,
12633 inst.operands[1].imm,
12634 inst.operands[0].writeback);
90e4755a
RE		 12635 }
12636 }
c19d1205 12637 else
90e4755a 12638 {
c19d1205
ZW		 12639 constraint (inst.operands[0].reg > 7
12640 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
1198ca51
PB		 12641 constraint (inst.instruction != T_MNEM_ldmia
12642 && inst.instruction != T_MNEM_stmia,
12643 _("Thumb-2 instruction only valid in unified syntax"));
c19d1205 12644 if (inst.instruction == T_MNEM_stmia)
f03698e6 12645 {
c19d1205
ZW		 12646 if (!inst.operands[0].writeback)
12647 as_warn (_("this instruction will write back the base register"));
12648 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
12649 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
1e5b0379 12650 as_warn (_("value stored for r%d is UNKNOWN"),
c19d1205 12651 inst.operands[0].reg);
f03698e6 12652 }
c19d1205 12653 else
90e4755a 12654 {
c19d1205
ZW		 12655 if (!inst.operands[0].writeback
12656 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
12657 as_warn (_("this instruction will write back the base register"));
12658 else if (inst.operands[0].writeback
12659 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
12660 as_warn (_("this instruction will not write back the base register"));
90e4755a
RE		 12661 }
12662
c19d1205
ZW		 12663 inst.instruction = THUMB_OP16 (inst.instruction);
12664 inst.instruction |= inst.operands[0].reg << 8;
12665 inst.instruction |= inst.operands[1].imm;
12666 }
12667}
e28cd48c 12668
c19d1205
ZW		 12669static void
12670do_t_ldrex (void)
12671{
12672 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
12673 || inst.operands[1].postind || inst.operands[1].writeback
12674 || inst.operands[1].immisreg || inst.operands[1].shifted
12675 || inst.operands[1].negative,
01cfc07f 12676 BAD_ADDR_MODE);
e28cd48c 12677
5be8be5d
DG		 12678 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
12679
c19d1205
ZW		 12680 inst.instruction |= inst.operands[0].reg << 12;
12681 inst.instruction |= inst.operands[1].reg << 16;
e2b0ab59 12682 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8;
c19d1205 12683}
e28cd48c 12684
c19d1205
ZW		 12685static void
12686do_t_ldrexd (void)
12687{
12688 if (!inst.operands[1].present)
1cac9012 12689 {
c19d1205
ZW		 12690 constraint (inst.operands[0].reg == REG_LR,
12691 _("r14 not allowed as first register "
12692 "when second register is omitted"));
12693 inst.operands[1].reg = inst.operands[0].reg + 1;
b99bd4ef 12694 }
c19d1205
ZW		 12695 constraint (inst.operands[0].reg == inst.operands[1].reg,
12696 BAD_OVERLAP);
b99bd4ef 12697
c19d1205
ZW		 12698 inst.instruction |= inst.operands[0].reg << 12;
12699 inst.instruction |= inst.operands[1].reg << 8;
12700 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC		 12701}
12702
12703static void
c19d1205 12704do_t_ldst (void)
b99bd4ef 12705{
0110f2b8
PB		 12706 unsigned long opcode;
12707 int Rn;
12708
e07e6e58
NC		 12709 if (inst.operands[0].isreg
12710 && !inst.operands[0].preind
12711 && inst.operands[0].reg == REG_PC)
5ee91343 12712 set_pred_insn_type_last ();
e07e6e58 12713
0110f2b8 12714 opcode = inst.instruction;
c19d1205 12715 if (unified_syntax)
b99bd4ef 12716 {
53365c0d
PB		 12717 if (!inst.operands[1].isreg)
12718 {
12719 if (opcode <= 0xffff)
12720 inst.instruction = THUMB_OP32 (opcode);
8335d6aa 12721 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
53365c0d
PB		 12722 return;
12723 }
0110f2b8
PB		 12724 if (inst.operands[1].isreg
12725 && !inst.operands[1].writeback
c19d1205
ZW		 12726 && !inst.operands[1].shifted && !inst.operands[1].postind
12727 && !inst.operands[1].negative && inst.operands[0].reg <= 7
0110f2b8
PB		 12728 && opcode <= 0xffff
12729 && inst.size_req != 4)
c19d1205 12730 {
0110f2b8
PB		 12731 /* Insn may have a 16-bit form. */
12732 Rn = inst.operands[1].reg;
12733 if (inst.operands[1].immisreg)
12734 {
12735 inst.instruction = THUMB_OP16 (opcode);
5f4273c7 12736 /* [Rn, Rik] */
0110f2b8
PB		 12737 if (Rn <= 7 && inst.operands[1].imm <= 7)
12738 goto op16;
5be8be5d
DG		 12739 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
12740 reject_bad_reg (inst.operands[1].imm);
0110f2b8
PB		 12741 }
12742 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
12743 && opcode != T_MNEM_ldrsb)
12744 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
12745 || (Rn == REG_SP && opcode == T_MNEM_str))
12746 {
12747 /* [Rn, #const] */
12748 if (Rn > 7)
12749 {
12750 if (Rn == REG_PC)
12751 {
e2b0ab59 12752 if (inst.relocs[0].pc_rel)
0110f2b8
PB		 12753 opcode = T_MNEM_ldr_pc2;
12754 else
12755 opcode = T_MNEM_ldr_pc;
12756 }
12757 else
12758 {
12759 if (opcode == T_MNEM_ldr)
12760 opcode = T_MNEM_ldr_sp;
12761 else
12762 opcode = T_MNEM_str_sp;
12763 }
12764 inst.instruction = inst.operands[0].reg << 8;
12765 }
12766 else
12767 {
12768 inst.instruction = inst.operands[0].reg;
12769 inst.instruction |= inst.operands[1].reg << 3;
12770 }
12771 inst.instruction |= THUMB_OP16 (opcode);
12772 if (inst.size_req == 2)
e2b0ab59 12773 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
0110f2b8
PB		 12774 else
12775 inst.relax = opcode;
12776 return;
12777 }
c19d1205 12778 }
0110f2b8 12779 /* Definitely a 32-bit variant. */
5be8be5d 12780
8d67f500
NC		 12781 /* Warning for Erratum 752419. */
12782 if (opcode == T_MNEM_ldr
12783 && inst.operands[0].reg == REG_SP
12784 && inst.operands[1].writeback == 1
12785 && !inst.operands[1].immisreg)
12786 {
12787 if (no_cpu_selected ()
12788 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
477330fc
RM		 12789 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
12790 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
8d67f500
NC		 12791 as_warn (_("This instruction may be unpredictable "
12792 "if executed on M-profile cores "
12793 "with interrupts enabled."));
12794 }
12795
5be8be5d 12796 /* Do some validations regarding addressing modes. */
1be5fd2e 12797 if (inst.operands[1].immisreg)
5be8be5d
DG		 12798 reject_bad_reg (inst.operands[1].imm);
12799
1be5fd2e
NC		 12800 constraint (inst.operands[1].writeback == 1
12801 && inst.operands[0].reg == inst.operands[1].reg,
12802 BAD_OVERLAP);
12803
0110f2b8 12804 inst.instruction = THUMB_OP32 (opcode);
c19d1205
ZW		 12805 inst.instruction |= inst.operands[0].reg << 12;
12806 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
1be5fd2e 12807 check_ldr_r15_aligned ();
b99bd4ef
NC		 12808 return;
12809 }
12810
c19d1205
ZW		 12811 constraint (inst.operands[0].reg > 7, BAD_HIREG);
12812
12813 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
b99bd4ef 12814 {
c19d1205
ZW		 12815 /* Only [Rn,Rm] is acceptable. */
12816 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
12817 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
12818 || inst.operands[1].postind || inst.operands[1].shifted
12819 || inst.operands[1].negative,
12820 _("Thumb does not support this addressing mode"));
12821 inst.instruction = THUMB_OP16 (inst.instruction);
12822 goto op16;
b99bd4ef 12823 }
5f4273c7 12824
c19d1205
ZW		 12825 inst.instruction = THUMB_OP16 (inst.instruction);
12826 if (!inst.operands[1].isreg)
8335d6aa 12827 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
c19d1205 12828 return;
b99bd4ef 12829
c19d1205
ZW		 12830 constraint (!inst.operands[1].preind
12831 || inst.operands[1].shifted
12832 || inst.operands[1].writeback,
12833 _("Thumb does not support this addressing mode"));
12834 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
90e4755a 12835 {
c19d1205
ZW		 12836 constraint (inst.instruction & 0x0600,
12837 _("byte or halfword not valid for base register"));
12838 constraint (inst.operands[1].reg == REG_PC
12839 && !(inst.instruction & THUMB_LOAD_BIT),
12840 _("r15 based store not allowed"));
12841 constraint (inst.operands[1].immisreg,
12842 _("invalid base register for register offset"));
b99bd4ef 12843
c19d1205
ZW		 12844 if (inst.operands[1].reg == REG_PC)
12845 inst.instruction = T_OPCODE_LDR_PC;
12846 else if (inst.instruction & THUMB_LOAD_BIT)
12847 inst.instruction = T_OPCODE_LDR_SP;
12848 else
12849 inst.instruction = T_OPCODE_STR_SP;
b99bd4ef 12850
c19d1205 12851 inst.instruction |= inst.operands[0].reg << 8;
e2b0ab59 12852 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
c19d1205
ZW		 12853 return;
12854 }
90e4755a 12855
c19d1205
ZW		 12856 constraint (inst.operands[1].reg > 7, BAD_HIREG);
12857 if (!inst.operands[1].immisreg)
12858 {
12859 /* Immediate offset. */
12860 inst.instruction |= inst.operands[0].reg;
12861 inst.instruction |= inst.operands[1].reg << 3;
e2b0ab59 12862 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
c19d1205
ZW		 12863 return;
12864 }
90e4755a 12865
c19d1205
ZW		 12866 /* Register offset. */
12867 constraint (inst.operands[1].imm > 7, BAD_HIREG);
12868 constraint (inst.operands[1].negative,
12869 _("Thumb does not support this addressing mode"));
90e4755a 12870
c19d1205
ZW		 12871 op16:
12872 switch (inst.instruction)
12873 {
12874 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
12875 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
12876 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
12877 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
12878 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
12879 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
12880 case 0x5600 /* ldrsb */:
12881 case 0x5e00 /* ldrsh */: break;
12882 default: abort ();
12883 }
90e4755a 12884
c19d1205
ZW		 12885 inst.instruction |= inst.operands[0].reg;
12886 inst.instruction |= inst.operands[1].reg << 3;
12887 inst.instruction |= inst.operands[1].imm << 6;
12888}
90e4755a 12889
c19d1205
ZW		 12890static void
12891do_t_ldstd (void)
12892{
12893 if (!inst.operands[1].present)
b99bd4ef 12894 {
c19d1205
ZW		 12895 inst.operands[1].reg = inst.operands[0].reg + 1;
12896 constraint (inst.operands[0].reg == REG_LR,
12897 _("r14 not allowed here"));
bd340a04 12898 constraint (inst.operands[0].reg == REG_R12,
477330fc 12899 _("r12 not allowed here"));
b99bd4ef 12900 }
bd340a04
MGD		 12901
12902 if (inst.operands[2].writeback
12903 && (inst.operands[0].reg == inst.operands[2].reg
12904 || inst.operands[1].reg == inst.operands[2].reg))
12905 as_warn (_("base register written back, and overlaps "
477330fc 12906 "one of transfer registers"));
bd340a04 12907
c19d1205
ZW		 12908 inst.instruction |= inst.operands[0].reg << 12;
12909 inst.instruction |= inst.operands[1].reg << 8;
12910 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
b99bd4ef
NC		 12911}
12912
c19d1205
ZW		 12913static void
12914do_t_ldstt (void)
12915{
12916 inst.instruction |= inst.operands[0].reg << 12;
12917 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
12918}
a737bd4d 12919
b99bd4ef 12920static void
c19d1205 12921do_t_mla (void)
b99bd4ef 12922{
fdfde340 12923 unsigned Rd, Rn, Rm, Ra;
c921be7d 12924
fdfde340
JM		 12925 Rd = inst.operands[0].reg;
12926 Rn = inst.operands[1].reg;
12927 Rm = inst.operands[2].reg;
12928 Ra = inst.operands[3].reg;
12929
12930 reject_bad_reg (Rd);
12931 reject_bad_reg (Rn);
12932 reject_bad_reg (Rm);
12933 reject_bad_reg (Ra);
12934
12935 inst.instruction |= Rd << 8;
12936 inst.instruction |= Rn << 16;
12937 inst.instruction |= Rm;
12938 inst.instruction |= Ra << 12;
c19d1205 12939}
b99bd4ef 12940
c19d1205
ZW		 12941static void
12942do_t_mlal (void)
12943{
fdfde340
JM		 12944 unsigned RdLo, RdHi, Rn, Rm;
12945
12946 RdLo = inst.operands[0].reg;
12947 RdHi = inst.operands[1].reg;
12948 Rn = inst.operands[2].reg;
12949 Rm = inst.operands[3].reg;
12950
12951 reject_bad_reg (RdLo);
12952 reject_bad_reg (RdHi);
12953 reject_bad_reg (Rn);
12954 reject_bad_reg (Rm);
12955
12956 inst.instruction |= RdLo << 12;
12957 inst.instruction |= RdHi << 8;
12958 inst.instruction |= Rn << 16;
12959 inst.instruction |= Rm;
c19d1205 12960}
b99bd4ef 12961
c19d1205
ZW		 12962static void
12963do_t_mov_cmp (void)
12964{
fdfde340
JM		 12965 unsigned Rn, Rm;
12966
12967 Rn = inst.operands[0].reg;
12968 Rm = inst.operands[1].reg;
12969
e07e6e58 12970 if (Rn == REG_PC)
5ee91343 12971 set_pred_insn_type_last ();
e07e6e58 12972
c19d1205 12973 if (unified_syntax)
b99bd4ef 12974 {
c19d1205
ZW		 12975 int r0off = (inst.instruction == T_MNEM_mov
12976 || inst.instruction == T_MNEM_movs) ? 8 : 16;
0110f2b8 12977 unsigned long opcode;
3d388997
PB		 12978 bfd_boolean narrow;
12979 bfd_boolean low_regs;
12980
fdfde340 12981 low_regs = (Rn <= 7 && Rm <= 7);
0110f2b8 12982 opcode = inst.instruction;
5ee91343 12983 if (in_pred_block ())
0110f2b8 12984 narrow = opcode != T_MNEM_movs;
3d388997 12985 else
0110f2b8 12986 narrow = opcode != T_MNEM_movs || low_regs;
3d388997
PB		 12987 if (inst.size_req == 4
12988 || inst.operands[1].shifted)
12989 narrow = FALSE;
12990
efd81785
PB		 12991 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12992 if (opcode == T_MNEM_movs && inst.operands[1].isreg
12993 && !inst.operands[1].shifted
fdfde340
JM		 12994 && Rn == REG_PC
12995 && Rm == REG_LR)
efd81785
PB		 12996 {
12997 inst.instruction = T2_SUBS_PC_LR;
12998 return;
12999 }
13000
fdfde340
JM		 13001 if (opcode == T_MNEM_cmp)
13002 {
13003 constraint (Rn == REG_PC, BAD_PC);
94206790
MM		 13004 if (narrow)
13005 {
13006 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
13007 but valid. */
13008 warn_deprecated_sp (Rm);
13009 /* R15 was documented as a valid choice for Rm in ARMv6,
13010 but as UNPREDICTABLE in ARMv7. ARM's proprietary
13011 tools reject R15, so we do too. */
13012 constraint (Rm == REG_PC, BAD_PC);
13013 }
13014 else
13015 reject_bad_reg (Rm);
fdfde340
JM		 13016 }
13017 else if (opcode == T_MNEM_mov
13018 || opcode == T_MNEM_movs)
13019 {
13020 if (inst.operands[1].isreg)
13021 {
13022 if (opcode == T_MNEM_movs)
13023 {
13024 reject_bad_reg (Rn);
13025 reject_bad_reg (Rm);
13026 }
76fa04a4
MGD		 13027 else if (narrow)
13028 {
13029 /* This is mov.n. */
13030 if ((Rn == REG_SP || Rn == REG_PC)
13031 && (Rm == REG_SP || Rm == REG_PC))
13032 {
5c3696f8 13033 as_tsktsk (_("Use of r%u as a source register is "
76fa04a4
MGD		 13034 "deprecated when r%u is the destination "
13035 "register."), Rm, Rn);
13036 }
13037 }
13038 else
13039 {
13040 /* This is mov.w. */
13041 constraint (Rn == REG_PC, BAD_PC);
13042 constraint (Rm == REG_PC, BAD_PC);
5c8ed6a4
JW		 13043 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
13044 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
76fa04a4 13045 }
fdfde340
JM		 13046 }
13047 else
13048 reject_bad_reg (Rn);
13049 }
13050
c19d1205
ZW		 13051 if (!inst.operands[1].isreg)
13052 {
0110f2b8 13053 /* Immediate operand. */
5ee91343 13054 if (!in_pred_block () && opcode == T_MNEM_mov)
0110f2b8
PB		 13055 narrow = 0;
13056 if (low_regs && narrow)
13057 {
13058 inst.instruction = THUMB_OP16 (opcode);
fdfde340 13059 inst.instruction |= Rn << 8;
e2b0ab59
AV		 13060 if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
13061 || inst.relocs[0].type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
72d98d16 13062 {
a9f02af8 13063 if (inst.size_req == 2)
e2b0ab59 13064 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM;
a9f02af8
MG		 13065 else
13066 inst.relax = opcode;
72d98d16 13067 }
0110f2b8
PB		 13068 }
13069 else
13070 {
e2b0ab59
AV		 13071 constraint ((inst.relocs[0].type
13072 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC)
13073 && (inst.relocs[0].type
13074 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) ,
a9f02af8
MG		 13075 THUMB1_RELOC_ONLY);
13076
0110f2b8
PB		 13077 inst.instruction = THUMB_OP32 (inst.instruction);
13078 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
fdfde340 13079 inst.instruction |= Rn << r0off;
e2b0ab59 13080 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
0110f2b8 13081 }
c19d1205 13082 }
728ca7c9
PB		 13083 else if (inst.operands[1].shifted && inst.operands[1].immisreg
13084 && (inst.instruction == T_MNEM_mov
13085 || inst.instruction == T_MNEM_movs))
13086 {
13087 /* Register shifts are encoded as separate shift instructions. */
13088 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
13089
5ee91343 13090 if (in_pred_block ())
728ca7c9
PB		 13091 narrow = !flags;
13092 else
13093 narrow = flags;
13094
13095 if (inst.size_req == 4)
13096 narrow = FALSE;
13097
13098 if (!low_regs || inst.operands[1].imm > 7)
13099 narrow = FALSE;
13100
fdfde340 13101 if (Rn != Rm)
728ca7c9
PB		 13102 narrow = FALSE;
13103
13104 switch (inst.operands[1].shift_kind)
13105 {
13106 case SHIFT_LSL:
13107 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
13108 break;
13109 case SHIFT_ASR:
13110 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
13111 break;
13112 case SHIFT_LSR:
13113 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
13114 break;
13115 case SHIFT_ROR:
13116 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
13117 break;
13118 default:
5f4273c7 13119 abort ();
728ca7c9
PB		 13120 }
13121
13122 inst.instruction = opcode;
13123 if (narrow)
13124 {
fdfde340 13125 inst.instruction |= Rn;
728ca7c9
PB		 13126 inst.instruction |= inst.operands[1].imm << 3;
13127 }
13128 else
13129 {
13130 if (flags)
13131 inst.instruction |= CONDS_BIT;
13132
fdfde340
JM		 13133 inst.instruction |= Rn << 8;
13134 inst.instruction |= Rm << 16;
728ca7c9
PB		 13135 inst.instruction |= inst.operands[1].imm;
13136 }
13137 }
3d388997 13138 else if (!narrow)
c19d1205 13139 {
728ca7c9
PB		 13140 /* Some mov with immediate shift have narrow variants.
13141 Register shifts are handled above. */
13142 if (low_regs && inst.operands[1].shifted
13143 && (inst.instruction == T_MNEM_mov
13144 || inst.instruction == T_MNEM_movs))
13145 {
5ee91343 13146 if (in_pred_block ())
728ca7c9
PB		 13147 narrow = (inst.instruction == T_MNEM_mov);
13148 else
13149 narrow = (inst.instruction == T_MNEM_movs);
13150 }
13151
13152 if (narrow)
13153 {
13154 switch (inst.operands[1].shift_kind)
13155 {
13156 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
13157 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
13158 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
13159 default: narrow = FALSE; break;
13160 }
13161 }
13162
13163 if (narrow)
13164 {
fdfde340
JM		 13165 inst.instruction |= Rn;
13166 inst.instruction |= Rm << 3;
e2b0ab59 13167 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
728ca7c9
PB		 13168 }
13169 else
13170 {
13171 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340 13172 inst.instruction |= Rn << r0off;
728ca7c9
PB		 13173 encode_thumb32_shifted_operand (1);
13174 }
c19d1205
ZW		 13175 }
13176 else
13177 switch (inst.instruction)
13178 {
13179 case T_MNEM_mov:
837b3435 13180 /* In v4t or v5t a move of two lowregs produces unpredictable
c6400f8a
MGD		 13181 results. Don't allow this. */
13182 if (low_regs)
13183 {
13184 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
13185 "MOV Rd, Rs with two low registers is not "
13186 "permitted on this architecture");
fa94de6b 13187 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
c6400f8a
MGD		 13188 arm_ext_v6);
13189 }
13190
c19d1205 13191 inst.instruction = T_OPCODE_MOV_HR;
fdfde340
JM		 13192 inst.instruction |= (Rn & 0x8) << 4;
13193 inst.instruction |= (Rn & 0x7);
13194 inst.instruction |= Rm << 3;
c19d1205 13195 break;
b99bd4ef 13196
c19d1205
ZW		 13197 case T_MNEM_movs:
13198 /* We know we have low registers at this point.
941a8a52
MGD		 13199 Generate LSLS Rd, Rs, #0. */
13200 inst.instruction = T_OPCODE_LSL_I;
fdfde340
JM		 13201 inst.instruction |= Rn;
13202 inst.instruction |= Rm << 3;
c19d1205
ZW		 13203 break;
13204
13205 case T_MNEM_cmp:
3d388997 13206 if (low_regs)
c19d1205
ZW		 13207 {
13208 inst.instruction = T_OPCODE_CMP_LR;
fdfde340
JM		 13209 inst.instruction |= Rn;
13210 inst.instruction |= Rm << 3;
c19d1205
ZW		 13211 }
13212 else
13213 {
13214 inst.instruction = T_OPCODE_CMP_HR;
fdfde340
JM		 13215 inst.instruction |= (Rn & 0x8) << 4;
13216 inst.instruction |= (Rn & 0x7);
13217 inst.instruction |= Rm << 3;
c19d1205
ZW		 13218 }
13219 break;
13220 }
b99bd4ef
NC		 13221 return;
13222 }
13223
c19d1205 13224 inst.instruction = THUMB_OP16 (inst.instruction);
539d4391
NC		 13225
13226 /* PR 10443: Do not silently ignore shifted operands. */
13227 constraint (inst.operands[1].shifted,
13228 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
13229
c19d1205 13230 if (inst.operands[1].isreg)
b99bd4ef 13231 {
fdfde340 13232 if (Rn < 8 && Rm < 8)
b99bd4ef 13233 {
c19d1205
ZW		 13234 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
13235 since a MOV instruction produces unpredictable results. */
13236 if (inst.instruction == T_OPCODE_MOV_I8)
13237 inst.instruction = T_OPCODE_ADD_I3;
b99bd4ef 13238 else
c19d1205 13239 inst.instruction = T_OPCODE_CMP_LR;
b99bd4ef 13240
fdfde340
JM		 13241 inst.instruction |= Rn;
13242 inst.instruction |= Rm << 3;
b99bd4ef
NC		 13243 }
13244 else
13245 {
c19d1205
ZW		 13246 if (inst.instruction == T_OPCODE_MOV_I8)
13247 inst.instruction = T_OPCODE_MOV_HR;
13248 else
13249 inst.instruction = T_OPCODE_CMP_HR;
13250 do_t_cpy ();
b99bd4ef
NC		 13251 }
13252 }
c19d1205 13253 else
b99bd4ef 13254 {
fdfde340 13255 constraint (Rn > 7,
c19d1205 13256 _("only lo regs allowed with immediate"));
fdfde340 13257 inst.instruction |= Rn << 8;
e2b0ab59 13258 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM;
c19d1205
ZW		 13259 }
13260}
b99bd4ef 13261
c19d1205
ZW		 13262static void
13263do_t_mov16 (void)
13264{
fdfde340 13265 unsigned Rd;
b6895b4f
PB		 13266 bfd_vma imm;
13267 bfd_boolean top;
13268
13269 top = (inst.instruction & 0x00800000) != 0;
e2b0ab59 13270 if (inst.relocs[0].type == BFD_RELOC_ARM_MOVW)
b6895b4f 13271 {
33eaf5de 13272 constraint (top, _(":lower16: not allowed in this instruction"));
e2b0ab59 13273 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVW;
b6895b4f 13274 }
e2b0ab59 13275 else if (inst.relocs[0].type == BFD_RELOC_ARM_MOVT)
b6895b4f 13276 {
33eaf5de 13277 constraint (!top, _(":upper16: not allowed in this instruction"));
e2b0ab59 13278 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVT;
b6895b4f
PB		 13279 }
13280
fdfde340
JM		 13281 Rd = inst.operands[0].reg;
13282 reject_bad_reg (Rd);
13283
13284 inst.instruction |= Rd << 8;
e2b0ab59 13285 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
b6895b4f 13286 {
e2b0ab59 13287 imm = inst.relocs[0].exp.X_add_number;
b6895b4f
PB		 13288 inst.instruction |= (imm & 0xf000) << 4;
13289 inst.instruction |= (imm & 0x0800) << 15;
13290 inst.instruction |= (imm & 0x0700) << 4;
13291 inst.instruction |= (imm & 0x00ff);
13292 }
c19d1205 13293}
b99bd4ef 13294
c19d1205
ZW		 13295static void
13296do_t_mvn_tst (void)
13297{
fdfde340 13298 unsigned Rn, Rm;
c921be7d 13299
fdfde340
JM		 13300 Rn = inst.operands[0].reg;
13301 Rm = inst.operands[1].reg;
13302
13303 if (inst.instruction == T_MNEM_cmp
13304 || inst.instruction == T_MNEM_cmn)
13305 constraint (Rn == REG_PC, BAD_PC);
13306 else
13307 reject_bad_reg (Rn);
13308 reject_bad_reg (Rm);
13309
c19d1205
ZW		 13310 if (unified_syntax)
13311 {
13312 int r0off = (inst.instruction == T_MNEM_mvn
13313 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
3d388997
PB		 13314 bfd_boolean narrow;
13315
13316 if (inst.size_req == 4
13317 || inst.instruction > 0xffff
13318 || inst.operands[1].shifted
fdfde340 13319 || Rn > 7 || Rm > 7)
3d388997 13320 narrow = FALSE;
fe8b4cc3
KT		 13321 else if (inst.instruction == T_MNEM_cmn
13322 || inst.instruction == T_MNEM_tst)
3d388997
PB		 13323 narrow = TRUE;
13324 else if (THUMB_SETS_FLAGS (inst.instruction))
5ee91343 13325 narrow = !in_pred_block ();
3d388997 13326 else
5ee91343 13327 narrow = in_pred_block ();
3d388997 13328
c19d1205 13329 if (!inst.operands[1].isreg)
b99bd4ef 13330 {
c19d1205
ZW		 13331 /* For an immediate, we always generate a 32-bit opcode;
13332 section relaxation will shrink it later if possible. */
13333 if (inst.instruction < 0xffff)
13334 inst.instruction = THUMB_OP32 (inst.instruction);
13335 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
fdfde340 13336 inst.instruction |= Rn << r0off;
e2b0ab59 13337 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
b99bd4ef 13338 }
c19d1205 13339 else
b99bd4ef 13340 {
c19d1205 13341 /* See if we can do this with a 16-bit instruction. */
3d388997 13342 if (narrow)
b99bd4ef 13343 {
c19d1205 13344 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM		 13345 inst.instruction |= Rn;
13346 inst.instruction |= Rm << 3;
b99bd4ef 13347 }
c19d1205 13348 else
b99bd4ef 13349 {
c19d1205
ZW		 13350 constraint (inst.operands[1].shifted
13351 && inst.operands[1].immisreg,
13352 _("shift must be constant"));
13353 if (inst.instruction < 0xffff)
13354 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340 13355 inst.instruction |= Rn << r0off;
c19d1205 13356 encode_thumb32_shifted_operand (1);
b99bd4ef 13357 }
b99bd4ef
NC		 13358 }
13359 }
13360 else
13361 {
c19d1205
ZW		 13362 constraint (inst.instruction > 0xffff
13363 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
13364 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
13365 _("unshifted register required"));
fdfde340 13366 constraint (Rn > 7 || Rm > 7,
c19d1205 13367 BAD_HIREG);
b99bd4ef 13368
c19d1205 13369 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM		 13370 inst.instruction |= Rn;
13371 inst.instruction |= Rm << 3;
b99bd4ef 13372 }
b99bd4ef
NC		 13373}
13374
b05fe5cf 13375static void
c19d1205 13376do_t_mrs (void)
b05fe5cf 13377{
fdfde340 13378 unsigned Rd;
037e8744
JB		 13379
13380 if (do_vfp_nsyn_mrs () == SUCCESS)
13381 return;
13382
90ec0d68
MGD		 13383 Rd = inst.operands[0].reg;
13384 reject_bad_reg (Rd);
13385 inst.instruction |= Rd << 8;
13386
13387 if (inst.operands[1].isreg)
62b3e311 13388 {
90ec0d68
MGD		 13389 unsigned br = inst.operands[1].reg;
13390 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
13391 as_bad (_("bad register for mrs"));
13392
13393 inst.instruction |= br & (0xf << 16);
13394 inst.instruction |= (br & 0x300) >> 4;
13395 inst.instruction |= (br & SPSR_BIT) >> 2;
62b3e311
PB		 13396 }
13397 else
13398 {
90ec0d68 13399 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
5f4273c7 13400
d2cd1205 13401 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
1a43faaf
NC		 13402 {
13403 /* PR gas/12698: The constraint is only applied for m_profile.
13404 If the user has specified -march=all, we want to ignore it as
13405 we are building for any CPU type, including non-m variants. */
823d2571
TG		 13406 bfd_boolean m_profile =
13407 !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
1a43faaf
NC		 13408 constraint ((flags != 0) && m_profile, _("selected processor does "
13409 "not support requested special purpose register"));
13410 }
90ec0d68 13411 else
d2cd1205
JB		 13412 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13413 devices). */
13414 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
13415 _("'APSR', 'CPSR' or 'SPSR' expected"));
fdfde340 13416
90ec0d68
MGD		 13417 inst.instruction |= (flags & SPSR_BIT) >> 2;
13418 inst.instruction |= inst.operands[1].imm & 0xff;
13419 inst.instruction |= 0xf0000;
13420 }
c19d1205 13421}
b05fe5cf 13422
c19d1205
ZW		 13423static void
13424do_t_msr (void)
13425{
62b3e311 13426 int flags;
fdfde340 13427 unsigned Rn;
62b3e311 13428
037e8744
JB		 13429 if (do_vfp_nsyn_msr () == SUCCESS)
13430 return;
13431
c19d1205
ZW		 13432 constraint (!inst.operands[1].isreg,
13433 _("Thumb encoding does not support an immediate here"));
90ec0d68
MGD		 13434
13435 if (inst.operands[0].isreg)
13436 flags = (int)(inst.operands[0].reg);
13437 else
13438 flags = inst.operands[0].imm;
13439
d2cd1205 13440 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
62b3e311 13441 {
d2cd1205
JB		 13442 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
13443
1a43faaf 13444 /* PR gas/12698: The constraint is only applied for m_profile.
477330fc
RM		 13445 If the user has specified -march=all, we want to ignore it as
13446 we are building for any CPU type, including non-m variants. */
823d2571
TG		 13447 bfd_boolean m_profile =
13448 !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
1a43faaf 13449 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
477330fc
RM		 13450 && (bits & ~(PSR_s | PSR_f)) != 0)
13451 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
13452 && bits != PSR_f)) && m_profile,
13453 _("selected processor does not support requested special "
13454 "purpose register"));
62b3e311
PB		 13455 }
13456 else
d2cd1205
JB		 13457 constraint ((flags & 0xff) != 0, _("selected processor does not support "
13458 "requested special purpose register"));
c921be7d 13459
fdfde340
JM		 13460 Rn = inst.operands[1].reg;
13461 reject_bad_reg (Rn);
13462
62b3e311 13463 inst.instruction |= (flags & SPSR_BIT) >> 2;
90ec0d68
MGD		 13464 inst.instruction |= (flags & 0xf0000) >> 8;
13465 inst.instruction |= (flags & 0x300) >> 4;
62b3e311 13466 inst.instruction |= (flags & 0xff);
fdfde340 13467 inst.instruction |= Rn << 16;
c19d1205 13468}
b05fe5cf 13469
c19d1205
ZW		 13470static void
13471do_t_mul (void)
13472{
17828f45 13473 bfd_boolean narrow;
fdfde340 13474 unsigned Rd, Rn, Rm;
17828f45 13475
c19d1205
ZW		 13476 if (!inst.operands[2].present)
13477 inst.operands[2].reg = inst.operands[0].reg;
b05fe5cf 13478
fdfde340
JM		 13479 Rd = inst.operands[0].reg;
13480 Rn = inst.operands[1].reg;
13481 Rm = inst.operands[2].reg;
13482
17828f45 13483 if (unified_syntax)
b05fe5cf 13484 {
17828f45 13485 if (inst.size_req == 4
fdfde340
JM		 13486 || (Rd != Rn
13487 && Rd != Rm)
13488 || Rn > 7
13489 || Rm > 7)
17828f45
JM		 13490 narrow = FALSE;
13491 else if (inst.instruction == T_MNEM_muls)
5ee91343 13492 narrow = !in_pred_block ();
17828f45 13493 else
5ee91343 13494 narrow = in_pred_block ();
b05fe5cf 13495 }
c19d1205 13496 else
b05fe5cf 13497 {
17828f45 13498 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
fdfde340 13499 constraint (Rn > 7 || Rm > 7,
c19d1205 13500 BAD_HIREG);
17828f45
JM		 13501 narrow = TRUE;
13502 }
b05fe5cf 13503
17828f45
JM		 13504 if (narrow)
13505 {
13506 /* 16-bit MULS/Conditional MUL. */
c19d1205 13507 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340 13508 inst.instruction |= Rd;
b05fe5cf 13509
fdfde340
JM		 13510 if (Rd == Rn)
13511 inst.instruction |= Rm << 3;
13512 else if (Rd == Rm)
13513 inst.instruction |= Rn << 3;
c19d1205
ZW		 13514 else
13515 constraint (1, _("dest must overlap one source register"));
13516 }
17828f45
JM		 13517 else
13518 {
e07e6e58
NC		 13519 constraint (inst.instruction != T_MNEM_mul,
13520 _("Thumb-2 MUL must not set flags"));
17828f45
JM		 13521 /* 32-bit MUL. */
13522 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340
JM		 13523 inst.instruction |= Rd << 8;
13524 inst.instruction |= Rn << 16;
13525 inst.instruction |= Rm << 0;
13526
13527 reject_bad_reg (Rd);
13528 reject_bad_reg (Rn);
13529 reject_bad_reg (Rm);
17828f45 13530 }
c19d1205 13531}
b05fe5cf 13532
c19d1205
ZW		 13533static void
13534do_t_mull (void)
13535{
fdfde340 13536 unsigned RdLo, RdHi, Rn, Rm;
b05fe5cf 13537
fdfde340
JM		 13538 RdLo = inst.operands[0].reg;
13539 RdHi = inst.operands[1].reg;
13540 Rn = inst.operands[2].reg;
13541 Rm = inst.operands[3].reg;
13542
13543 reject_bad_reg (RdLo);
13544 reject_bad_reg (RdHi);
13545 reject_bad_reg (Rn);
13546 reject_bad_reg (Rm);
13547
13548 inst.instruction |= RdLo << 12;
13549 inst.instruction |= RdHi << 8;
13550 inst.instruction |= Rn << 16;
13551 inst.instruction |= Rm;
13552
13553 if (RdLo == RdHi)
c19d1205
ZW		 13554 as_tsktsk (_("rdhi and rdlo must be different"));
13555}
b05fe5cf 13556
c19d1205
ZW		 13557static void
13558do_t_nop (void)
13559{
5ee91343 13560 set_pred_insn_type (NEUTRAL_IT_INSN);
e07e6e58 13561
c19d1205
ZW		 13562 if (unified_syntax)
13563 {
13564 if (inst.size_req == 4 || inst.operands[0].imm > 15)
b05fe5cf 13565 {
c19d1205
ZW		 13566 inst.instruction = THUMB_OP32 (inst.instruction);
13567 inst.instruction |= inst.operands[0].imm;
13568 }
13569 else
13570 {
bc2d1808
NC		 13571 /* PR9722: Check for Thumb2 availability before
13572 generating a thumb2 nop instruction. */
afa62d5e 13573 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
bc2d1808
NC		 13574 {
13575 inst.instruction = THUMB_OP16 (inst.instruction);
13576 inst.instruction |= inst.operands[0].imm << 4;
13577 }
13578 else
13579 inst.instruction = 0x46c0;
c19d1205
ZW		 13580 }
13581 }
13582 else
13583 {
13584 constraint (inst.operands[0].present,
13585 _("Thumb does not support NOP with hints"));
13586 inst.instruction = 0x46c0;
13587 }
13588}
b05fe5cf 13589
c19d1205
ZW		 13590static void
13591do_t_neg (void)
13592{
13593 if (unified_syntax)
13594 {
3d388997
PB		 13595 bfd_boolean narrow;
13596
13597 if (THUMB_SETS_FLAGS (inst.instruction))
5ee91343 13598 narrow = !in_pred_block ();
3d388997 13599 else
5ee91343 13600 narrow = in_pred_block ();
3d388997
PB		 13601 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
13602 narrow = FALSE;
13603 if (inst.size_req == 4)
13604 narrow = FALSE;
13605
13606 if (!narrow)
c19d1205
ZW		 13607 {
13608 inst.instruction = THUMB_OP32 (inst.instruction);
13609 inst.instruction |= inst.operands[0].reg << 8;
13610 inst.instruction |= inst.operands[1].reg << 16;
b05fe5cf
ZW		 13611 }
13612 else
13613 {
c19d1205
ZW		 13614 inst.instruction = THUMB_OP16 (inst.instruction);
13615 inst.instruction |= inst.operands[0].reg;
13616 inst.instruction |= inst.operands[1].reg << 3;
b05fe5cf
ZW		 13617 }
13618 }
13619 else
13620 {
c19d1205
ZW		 13621 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
13622 BAD_HIREG);
13623 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
13624
13625 inst.instruction = THUMB_OP16 (inst.instruction);
13626 inst.instruction |= inst.operands[0].reg;
13627 inst.instruction |= inst.operands[1].reg << 3;
13628 }
13629}
13630
1c444d06
JM		 13631static void
13632do_t_orn (void)
13633{
13634 unsigned Rd, Rn;
13635
13636 Rd = inst.operands[0].reg;
13637 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
13638
fdfde340
JM		 13639 reject_bad_reg (Rd);
13640 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13641 reject_bad_reg (Rn);
13642
1c444d06
JM		 13643 inst.instruction |= Rd << 8;
13644 inst.instruction |= Rn << 16;
13645
13646 if (!inst.operands[2].isreg)
13647 {
13648 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
e2b0ab59 13649 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
1c444d06
JM		 13650 }
13651 else
13652 {
13653 unsigned Rm;
13654
13655 Rm = inst.operands[2].reg;
fdfde340 13656 reject_bad_reg (Rm);
1c444d06
JM		 13657
13658 constraint (inst.operands[2].shifted
13659 && inst.operands[2].immisreg,
13660 _("shift must be constant"));
13661 encode_thumb32_shifted_operand (2);
13662 }
13663}
13664
c19d1205
ZW		 13665static void
13666do_t_pkhbt (void)
13667{
fdfde340
JM		 13668 unsigned Rd, Rn, Rm;
13669
13670 Rd = inst.operands[0].reg;
13671 Rn = inst.operands[1].reg;
13672 Rm = inst.operands[2].reg;
13673
13674 reject_bad_reg (Rd);
13675 reject_bad_reg (Rn);
13676 reject_bad_reg (Rm);
13677
13678 inst.instruction |= Rd << 8;
13679 inst.instruction |= Rn << 16;
13680 inst.instruction |= Rm;
c19d1205
ZW		 13681 if (inst.operands[3].present)
13682 {
e2b0ab59
AV		 13683 unsigned int val = inst.relocs[0].exp.X_add_number;
13684 constraint (inst.relocs[0].exp.X_op != O_constant,
c19d1205
ZW		 13685 _("expression too complex"));
13686 inst.instruction |= (val & 0x1c) << 10;
13687 inst.instruction |= (val & 0x03) << 6;
b05fe5cf 13688 }
c19d1205 13689}
b05fe5cf 13690
c19d1205
ZW		 13691static void
13692do_t_pkhtb (void)
13693{
13694 if (!inst.operands[3].present)
1ef52f49
NC		 13695 {
13696 unsigned Rtmp;
13697
13698 inst.instruction &= ~0x00000020;
13699
13700 /* PR 10168. Swap the Rm and Rn registers. */
13701 Rtmp = inst.operands[1].reg;
13702 inst.operands[1].reg = inst.operands[2].reg;
13703 inst.operands[2].reg = Rtmp;
13704 }
c19d1205 13705 do_t_pkhbt ();
b05fe5cf
ZW		 13706}
13707
c19d1205
ZW		 13708static void
13709do_t_pld (void)
13710{
fdfde340
JM		 13711 if (inst.operands[0].immisreg)
13712 reject_bad_reg (inst.operands[0].imm);
13713
c19d1205
ZW		 13714 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
13715}
b05fe5cf 13716
c19d1205
ZW		 13717static void
13718do_t_push_pop (void)
b99bd4ef 13719{
e9f89963 13720 unsigned mask;
5f4273c7 13721
c19d1205
ZW		 13722 constraint (inst.operands[0].writeback,
13723 _("push/pop do not support {reglist}^"));
e2b0ab59 13724 constraint (inst.relocs[0].type != BFD_RELOC_UNUSED,
c19d1205 13725 _("expression too complex"));
b99bd4ef 13726
e9f89963 13727 mask = inst.operands[0].imm;
d3bfe16e 13728 if (inst.size_req != 4 && (mask & ~0xff) == 0)
3c707909 13729 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
d3bfe16e 13730 else if (inst.size_req != 4
c6025a80 13731 && (mask & ~0xff) == (1U << (inst.instruction == T_MNEM_push
d3bfe16e 13732 ? REG_LR : REG_PC)))
b99bd4ef 13733 {
c19d1205
ZW		 13734 inst.instruction = THUMB_OP16 (inst.instruction);
13735 inst.instruction |= THUMB_PP_PC_LR;
3c707909 13736 inst.instruction |= mask & 0xff;
c19d1205
ZW		 13737 }
13738 else if (unified_syntax)
13739 {
3c707909 13740 inst.instruction = THUMB_OP32 (inst.instruction);
4b5a202f
AV		 13741 encode_thumb2_multi (TRUE /* do_io */, 13, mask, TRUE);
13742 }
13743 else
13744 {
13745 inst.error = _("invalid register list to push/pop instruction");
13746 return;
c19d1205 13747 }
4b5a202f
AV		 13748}
13749
13750static void
13751do_t_clrm (void)
13752{
13753 if (unified_syntax)
13754 encode_thumb2_multi (FALSE /* do_io */, -1, inst.operands[0].imm, FALSE);
c19d1205
ZW		 13755 else
13756 {
13757 inst.error = _("invalid register list to push/pop instruction");
13758 return;
13759 }
c19d1205 13760}
b99bd4ef 13761
efd6b359
AV		 13762static void
13763do_t_vscclrm (void)
13764{
13765 if (inst.operands[0].issingle)
13766 {
13767 inst.instruction |= (inst.operands[0].reg & 0x1) << 22;
13768 inst.instruction |= (inst.operands[0].reg & 0x1e) << 11;
13769 inst.instruction |= inst.operands[0].imm;
13770 }
13771 else
13772 {
13773 inst.instruction |= (inst.operands[0].reg & 0x10) << 18;
13774 inst.instruction |= (inst.operands[0].reg & 0xf) << 12;
13775 inst.instruction |= 1 << 8;
13776 inst.instruction |= inst.operands[0].imm << 1;
13777 }
13778}
13779
c19d1205
ZW		 13780static void
13781do_t_rbit (void)
13782{
fdfde340
JM		 13783 unsigned Rd, Rm;
13784
13785 Rd = inst.operands[0].reg;
13786 Rm = inst.operands[1].reg;
13787
13788 reject_bad_reg (Rd);
13789 reject_bad_reg (Rm);
13790
13791 inst.instruction |= Rd << 8;
13792 inst.instruction |= Rm << 16;
13793 inst.instruction |= Rm;
c19d1205 13794}
b99bd4ef 13795
c19d1205
ZW		 13796static void
13797do_t_rev (void)
13798{
fdfde340
JM		 13799 unsigned Rd, Rm;
13800
13801 Rd = inst.operands[0].reg;
13802 Rm = inst.operands[1].reg;
13803
13804 reject_bad_reg (Rd);
13805 reject_bad_reg (Rm);
13806
13807 if (Rd <= 7 && Rm <= 7
c19d1205
ZW		 13808 && inst.size_req != 4)
13809 {
13810 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM		 13811 inst.instruction |= Rd;
13812 inst.instruction |= Rm << 3;
c19d1205
ZW		 13813 }
13814 else if (unified_syntax)
13815 {
13816 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340
JM		 13817 inst.instruction |= Rd << 8;
13818 inst.instruction |= Rm << 16;
13819 inst.instruction |= Rm;
c19d1205
ZW		 13820 }
13821 else
13822 inst.error = BAD_HIREG;
13823}
b99bd4ef 13824
1c444d06
JM		 13825static void
13826do_t_rrx (void)
13827{
13828 unsigned Rd, Rm;
13829
13830 Rd = inst.operands[0].reg;
13831 Rm = inst.operands[1].reg;
13832
fdfde340
JM		 13833 reject_bad_reg (Rd);
13834 reject_bad_reg (Rm);
c921be7d 13835
1c444d06
JM		 13836 inst.instruction |= Rd << 8;
13837 inst.instruction |= Rm;
13838}
13839
c19d1205
ZW		 13840static void
13841do_t_rsb (void)
13842{
fdfde340 13843 unsigned Rd, Rs;
b99bd4ef 13844
c19d1205
ZW		 13845 Rd = inst.operands[0].reg;
13846 Rs = (inst.operands[1].present
13847 ? inst.operands[1].reg /* Rd, Rs, foo */
13848 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
b99bd4ef 13849
fdfde340
JM		 13850 reject_bad_reg (Rd);
13851 reject_bad_reg (Rs);
13852 if (inst.operands[2].isreg)
13853 reject_bad_reg (inst.operands[2].reg);
13854
c19d1205
ZW		 13855 inst.instruction |= Rd << 8;
13856 inst.instruction |= Rs << 16;
13857 if (!inst.operands[2].isreg)
13858 {
026d3abb
PB		 13859 bfd_boolean narrow;
13860
13861 if ((inst.instruction & 0x00100000) != 0)
5ee91343 13862 narrow = !in_pred_block ();
026d3abb 13863 else
5ee91343 13864 narrow = in_pred_block ();
026d3abb
PB		 13865
13866 if (Rd > 7 || Rs > 7)
13867 narrow = FALSE;
13868
13869 if (inst.size_req == 4 || !unified_syntax)
13870 narrow = FALSE;
13871
e2b0ab59
AV		 13872 if (inst.relocs[0].exp.X_op != O_constant
13873 || inst.relocs[0].exp.X_add_number != 0)
026d3abb
PB		 13874 narrow = FALSE;
13875
13876 /* Turn rsb #0 into 16-bit neg. We should probably do this via
477330fc 13877 relaxation, but it doesn't seem worth the hassle. */
026d3abb
PB		 13878 if (narrow)
13879 {
e2b0ab59 13880 inst.relocs[0].type = BFD_RELOC_UNUSED;
026d3abb
PB		 13881 inst.instruction = THUMB_OP16 (T_MNEM_negs);
13882 inst.instruction |= Rs << 3;
13883 inst.instruction |= Rd;
13884 }
13885 else
13886 {
13887 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
e2b0ab59 13888 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
026d3abb 13889 }
c19d1205
ZW		 13890 }
13891 else
13892 encode_thumb32_shifted_operand (2);
13893}
b99bd4ef 13894
c19d1205
ZW		 13895static void
13896do_t_setend (void)
13897{
12e37cbc
MGD		 13898 if (warn_on_deprecated
13899 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
5c3696f8 13900 as_tsktsk (_("setend use is deprecated for ARMv8"));
12e37cbc 13901
5ee91343 13902 set_pred_insn_type (OUTSIDE_PRED_INSN);
c19d1205
ZW		 13903 if (inst.operands[0].imm)
13904 inst.instruction |= 0x8;
13905}
b99bd4ef 13906
c19d1205
ZW		 13907static void
13908do_t_shift (void)
13909{
13910 if (!inst.operands[1].present)
13911 inst.operands[1].reg = inst.operands[0].reg;
13912
13913 if (unified_syntax)
13914 {
3d388997
PB		 13915 bfd_boolean narrow;
13916 int shift_kind;
13917
13918 switch (inst.instruction)
13919 {
13920 case T_MNEM_asr:
13921 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
13922 case T_MNEM_lsl:
13923 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
13924 case T_MNEM_lsr:
13925 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
13926 case T_MNEM_ror:
13927 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
13928 default: abort ();
13929 }
13930
13931 if (THUMB_SETS_FLAGS (inst.instruction))
5ee91343 13932 narrow = !in_pred_block ();
3d388997 13933 else
5ee91343 13934 narrow = in_pred_block ();
3d388997
PB		 13935 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
13936 narrow = FALSE;
13937 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
13938 narrow = FALSE;
13939 if (inst.operands[2].isreg
13940 && (inst.operands[1].reg != inst.operands[0].reg
13941 || inst.operands[2].reg > 7))
13942 narrow = FALSE;
13943 if (inst.size_req == 4)
13944 narrow = FALSE;
13945
fdfde340
JM		 13946 reject_bad_reg (inst.operands[0].reg);
13947 reject_bad_reg (inst.operands[1].reg);
c921be7d 13948
3d388997 13949 if (!narrow)
c19d1205
ZW		 13950 {
13951 if (inst.operands[2].isreg)
b99bd4ef 13952 {
fdfde340 13953 reject_bad_reg (inst.operands[2].reg);
c19d1205
ZW		 13954 inst.instruction = THUMB_OP32 (inst.instruction);
13955 inst.instruction |= inst.operands[0].reg << 8;
13956 inst.instruction |= inst.operands[1].reg << 16;
13957 inst.instruction |= inst.operands[2].reg;
94342ec3
NC		 13958
13959 /* PR 12854: Error on extraneous shifts. */
13960 constraint (inst.operands[2].shifted,
13961 _("extraneous shift as part of operand to shift insn"));
c19d1205
ZW		 13962 }
13963 else
13964 {
13965 inst.operands[1].shifted = 1;
3d388997 13966 inst.operands[1].shift_kind = shift_kind;
c19d1205
ZW		 13967 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
13968 ? T_MNEM_movs : T_MNEM_mov);
13969 inst.instruction |= inst.operands[0].reg << 8;
13970 encode_thumb32_shifted_operand (1);
13971 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
e2b0ab59 13972 inst.relocs[0].type = BFD_RELOC_UNUSED;
b99bd4ef
NC		 13973 }
13974 }
13975 else
13976 {
c19d1205 13977 if (inst.operands[2].isreg)
b99bd4ef 13978 {
3d388997 13979 switch (shift_kind)
b99bd4ef 13980 {
3d388997
PB		 13981 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
13982 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
13983 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
13984 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
c19d1205 13985 default: abort ();
b99bd4ef 13986 }
5f4273c7 13987
c19d1205
ZW		 13988 inst.instruction |= inst.operands[0].reg;
13989 inst.instruction |= inst.operands[2].reg << 3;
af199b06
NC		 13990
13991 /* PR 12854: Error on extraneous shifts. */
13992 constraint (inst.operands[2].shifted,
13993 _("extraneous shift as part of operand to shift insn"));
b99bd4ef
NC		 13994 }
13995 else
13996 {
3d388997 13997 switch (shift_kind)
b99bd4ef 13998 {
3d388997
PB		 13999 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
14000 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
14001 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
c19d1205 14002 default: abort ();
b99bd4ef 14003 }
e2b0ab59 14004 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
c19d1205
ZW		 14005 inst.instruction |= inst.operands[0].reg;
14006 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef
NC		 14007 }
14008 }
c19d1205
ZW		 14009 }
14010 else
14011 {
14012 constraint (inst.operands[0].reg > 7
14013 || inst.operands[1].reg > 7, BAD_HIREG);
14014 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
b99bd4ef 14015
c19d1205
ZW		 14016 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
14017 {
14018 constraint (inst.operands[2].reg > 7, BAD_HIREG);
14019 constraint (inst.operands[0].reg != inst.operands[1].reg,
14020 _("source1 and dest must be same register"));
b99bd4ef 14021
c19d1205
ZW		 14022 switch (inst.instruction)
14023 {
14024 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
14025 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
14026 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
14027 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
14028 default: abort ();
14029 }
5f4273c7 14030
c19d1205
ZW		 14031 inst.instruction |= inst.operands[0].reg;
14032 inst.instruction |= inst.operands[2].reg << 3;
af199b06
NC		 14033
14034 /* PR 12854: Error on extraneous shifts. */
14035 constraint (inst.operands[2].shifted,
14036 _("extraneous shift as part of operand to shift insn"));
c19d1205
ZW		 14037 }
14038 else
b99bd4ef 14039 {
c19d1205
ZW		 14040 switch (inst.instruction)
14041 {
14042 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
14043 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
14044 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
14045 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
14046 default: abort ();
14047 }
e2b0ab59 14048 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
c19d1205
ZW		 14049 inst.instruction |= inst.operands[0].reg;
14050 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef
NC		 14051 }
14052 }
b99bd4ef
NC		 14053}
14054
14055static void
c19d1205 14056do_t_simd (void)
b99bd4ef 14057{
fdfde340
JM		 14058 unsigned Rd, Rn, Rm;
14059
14060 Rd = inst.operands[0].reg;
14061 Rn = inst.operands[1].reg;
14062 Rm = inst.operands[2].reg;
14063
14064 reject_bad_reg (Rd);
14065 reject_bad_reg (Rn);
14066 reject_bad_reg (Rm);
14067
14068 inst.instruction |= Rd << 8;
14069 inst.instruction |= Rn << 16;
14070 inst.instruction |= Rm;
c19d1205 14071}
b99bd4ef 14072
03ee1b7f
NC		 14073static void
14074do_t_simd2 (void)
14075{
14076 unsigned Rd, Rn, Rm;
14077
14078 Rd = inst.operands[0].reg;
14079 Rm = inst.operands[1].reg;
14080 Rn = inst.operands[2].reg;
14081
14082 reject_bad_reg (Rd);
14083 reject_bad_reg (Rn);
14084 reject_bad_reg (Rm);
14085
14086 inst.instruction |= Rd << 8;
14087 inst.instruction |= Rn << 16;
14088 inst.instruction |= Rm;
14089}
14090
c19d1205 14091static void
3eb17e6b 14092do_t_smc (void)
c19d1205 14093{
e2b0ab59 14094 unsigned int value = inst.relocs[0].exp.X_add_number;
f4c65163
MGD		 14095 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
14096 _("SMC is not permitted on this architecture"));
e2b0ab59 14097 constraint (inst.relocs[0].exp.X_op != O_constant,
c19d1205 14098 _("expression too complex"));
ba85f98c
BW		 14099 constraint (value > 0xf, _("immediate too large (bigger than 0xF)"));
14100
e2b0ab59 14101 inst.relocs[0].type = BFD_RELOC_UNUSED;
c19d1205 14102 inst.instruction |= (value & 0x000f) << 16;
ba85f98c 14103
24382199 14104 /* PR gas/15623: SMC instructions must be last in an IT block. */
5ee91343 14105 set_pred_insn_type_last ();
c19d1205 14106}
b99bd4ef 14107
90ec0d68
MGD		 14108static void
14109do_t_hvc (void)
14110{
e2b0ab59 14111 unsigned int value = inst.relocs[0].exp.X_add_number;
90ec0d68 14112
e2b0ab59 14113 inst.relocs[0].type = BFD_RELOC_UNUSED;
90ec0d68
MGD		 14114 inst.instruction |= (value & 0x0fff);
14115 inst.instruction |= (value & 0xf000) << 4;
14116}
14117
c19d1205 14118static void
3a21c15a 14119do_t_ssat_usat (int bias)
c19d1205 14120{
fdfde340
JM		 14121 unsigned Rd, Rn;
14122
14123 Rd = inst.operands[0].reg;
14124 Rn = inst.operands[2].reg;
14125
14126 reject_bad_reg (Rd);
14127 reject_bad_reg (Rn);
14128
14129 inst.instruction |= Rd << 8;
3a21c15a 14130 inst.instruction |= inst.operands[1].imm - bias;
fdfde340 14131 inst.instruction |= Rn << 16;
b99bd4ef 14132
c19d1205 14133 if (inst.operands[3].present)
b99bd4ef 14134 {
e2b0ab59 14135 offsetT shift_amount = inst.relocs[0].exp.X_add_number;
3a21c15a 14136
e2b0ab59 14137 inst.relocs[0].type = BFD_RELOC_UNUSED;
3a21c15a 14138
e2b0ab59 14139 constraint (inst.relocs[0].exp.X_op != O_constant,
c19d1205 14140 _("expression too complex"));
b99bd4ef 14141
3a21c15a 14142 if (shift_amount != 0)
6189168b 14143 {
3a21c15a
NC		 14144 constraint (shift_amount > 31,
14145 _("shift expression is too large"));
14146
c19d1205 14147 if (inst.operands[3].shift_kind == SHIFT_ASR)
3a21c15a
NC		 14148 inst.instruction |= 0x00200000; /* sh bit. */
14149
14150 inst.instruction |= (shift_amount & 0x1c) << 10;
14151 inst.instruction |= (shift_amount & 0x03) << 6;
6189168b
NC		 14152 }
14153 }
b99bd4ef 14154}
c921be7d 14155
3a21c15a
NC		 14156static void
14157do_t_ssat (void)
14158{
14159 do_t_ssat_usat (1);
14160}
b99bd4ef 14161
0dd132b6 14162static void
c19d1205 14163do_t_ssat16 (void)
0dd132b6 14164{
fdfde340
JM		 14165 unsigned Rd, Rn;
14166
14167 Rd = inst.operands[0].reg;
14168 Rn = inst.operands[2].reg;
14169
14170 reject_bad_reg (Rd);
14171 reject_bad_reg (Rn);
14172
14173 inst.instruction |= Rd << 8;
c19d1205 14174 inst.instruction |= inst.operands[1].imm - 1;
fdfde340 14175 inst.instruction |= Rn << 16;
c19d1205 14176}
0dd132b6 14177
c19d1205
ZW		 14178static void
14179do_t_strex (void)
14180{
14181 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
14182 || inst.operands[2].postind || inst.operands[2].writeback
14183 || inst.operands[2].immisreg || inst.operands[2].shifted
14184 || inst.operands[2].negative,
01cfc07f 14185 BAD_ADDR_MODE);
0dd132b6 14186
5be8be5d
DG		 14187 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
14188
c19d1205
ZW		 14189 inst.instruction |= inst.operands[0].reg << 8;
14190 inst.instruction |= inst.operands[1].reg << 12;
14191 inst.instruction |= inst.operands[2].reg << 16;
e2b0ab59 14192 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8;
0dd132b6
NC		 14193}
14194
b99bd4ef 14195static void
c19d1205 14196do_t_strexd (void)
b99bd4ef 14197{
c19d1205
ZW		 14198 if (!inst.operands[2].present)
14199 inst.operands[2].reg = inst.operands[1].reg + 1;
b99bd4ef 14200
c19d1205
ZW		 14201 constraint (inst.operands[0].reg == inst.operands[1].reg
14202 || inst.operands[0].reg == inst.operands[2].reg
f8a8e9d6 14203 || inst.operands[0].reg == inst.operands[3].reg,
c19d1205 14204 BAD_OVERLAP);
b99bd4ef 14205
c19d1205
ZW		 14206 inst.instruction |= inst.operands[0].reg;
14207 inst.instruction |= inst.operands[1].reg << 12;
14208 inst.instruction |= inst.operands[2].reg << 8;
14209 inst.instruction |= inst.operands[3].reg << 16;
b99bd4ef
NC		 14210}
14211
14212static void
c19d1205 14213do_t_sxtah (void)
b99bd4ef 14214{
fdfde340
JM		 14215 unsigned Rd, Rn, Rm;
14216
14217 Rd = inst.operands[0].reg;
14218 Rn = inst.operands[1].reg;
14219 Rm = inst.operands[2].reg;
14220
14221 reject_bad_reg (Rd);
14222 reject_bad_reg (Rn);
14223 reject_bad_reg (Rm);
14224
14225 inst.instruction |= Rd << 8;
14226 inst.instruction |= Rn << 16;
14227 inst.instruction |= Rm;
c19d1205
ZW		 14228 inst.instruction |= inst.operands[3].imm << 4;
14229}
b99bd4ef 14230
c19d1205
ZW		 14231static void
14232do_t_sxth (void)
14233{
fdfde340
JM		 14234 unsigned Rd, Rm;
14235
14236 Rd = inst.operands[0].reg;
14237 Rm = inst.operands[1].reg;
14238
14239 reject_bad_reg (Rd);
14240 reject_bad_reg (Rm);
c921be7d
NC		 14241
14242 if (inst.instruction <= 0xffff
14243 && inst.size_req != 4
fdfde340 14244 && Rd <= 7 && Rm <= 7
c19d1205 14245 && (!inst.operands[2].present || inst.operands[2].imm == 0))
b99bd4ef 14246 {
c19d1205 14247 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM		 14248 inst.instruction |= Rd;
14249 inst.instruction |= Rm << 3;
b99bd4ef 14250 }
c19d1205 14251 else if (unified_syntax)
b99bd4ef 14252 {
c19d1205
ZW		 14253 if (inst.instruction <= 0xffff)
14254 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340
JM		 14255 inst.instruction |= Rd << 8;
14256 inst.instruction |= Rm;
c19d1205 14257 inst.instruction |= inst.operands[2].imm << 4;
b99bd4ef 14258 }
c19d1205 14259 else
b99bd4ef 14260 {
c19d1205
ZW		 14261 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
14262 _("Thumb encoding does not support rotation"));
14263 constraint (1, BAD_HIREG);
b99bd4ef 14264 }
c19d1205 14265}
b99bd4ef 14266
c19d1205
ZW		 14267static void
14268do_t_swi (void)
14269{
e2b0ab59 14270 inst.relocs[0].type = BFD_RELOC_ARM_SWI;
c19d1205 14271}
b99bd4ef 14272
92e90b6e
PB		 14273static void
14274do_t_tb (void)
14275{
fdfde340 14276 unsigned Rn, Rm;
92e90b6e
PB		 14277 int half;
14278
14279 half = (inst.instruction & 0x10) != 0;
5ee91343 14280 set_pred_insn_type_last ();
dfa9f0d5
PB		 14281 constraint (inst.operands[0].immisreg,
14282 _("instruction requires register index"));
fdfde340
JM		 14283
14284 Rn = inst.operands[0].reg;
14285 Rm = inst.operands[0].imm;
c921be7d 14286
5c8ed6a4
JW		 14287 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
14288 constraint (Rn == REG_SP, BAD_SP);
fdfde340
JM		 14289 reject_bad_reg (Rm);
14290
92e90b6e
PB		 14291 constraint (!half && inst.operands[0].shifted,
14292 _("instruction does not allow shifted index"));
fdfde340 14293 inst.instruction |= (Rn << 16) | Rm;
92e90b6e
PB		 14294}
14295
74db7efb
NC		 14296static void
14297do_t_udf (void)
14298{
14299 if (!inst.operands[0].present)
14300 inst.operands[0].imm = 0;
14301
14302 if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4)
14303 {
14304 constraint (inst.size_req == 2,
14305 _("immediate value out of range"));
14306 inst.instruction = THUMB_OP32 (inst.instruction);
14307 inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4;
14308 inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0;
14309 }
14310 else
14311 {
14312 inst.instruction = THUMB_OP16 (inst.instruction);
14313 inst.instruction |= inst.operands[0].imm;
14314 }
14315
5ee91343 14316 set_pred_insn_type (NEUTRAL_IT_INSN);
74db7efb
NC		 14317}
14318
14319
c19d1205
ZW		 14320static void
14321do_t_usat (void)
14322{
3a21c15a 14323 do_t_ssat_usat (0);
b99bd4ef
NC		 14324}
14325
14326static void
c19d1205 14327do_t_usat16 (void)
b99bd4ef 14328{
fdfde340
JM		 14329 unsigned Rd, Rn;
14330
14331 Rd = inst.operands[0].reg;
14332 Rn = inst.operands[2].reg;
14333
14334 reject_bad_reg (Rd);
14335 reject_bad_reg (Rn);
14336
14337 inst.instruction |= Rd << 8;
c19d1205 14338 inst.instruction |= inst.operands[1].imm;
fdfde340 14339 inst.instruction |= Rn << 16;
b99bd4ef 14340}
c19d1205 14341
e12437dc
AV		 14342/* Checking the range of the branch offset (VAL) with NBITS bits
14343 and IS_SIGNED signedness. Also checks the LSB to be 0. */
14344static int
14345v8_1_branch_value_check (int val, int nbits, int is_signed)
14346{
14347 gas_assert (nbits > 0 && nbits <= 32);
14348 if (is_signed)
14349 {
14350 int cmp = (1 << (nbits - 1));
14351 if ((val < -cmp) || (val >= cmp) || (val & 0x01))
14352 return FAIL;
14353 }
14354 else
14355 {
14356 if ((val <= 0) || (val >= (1 << nbits)) || (val & 0x1))
14357 return FAIL;
14358 }
14359 return SUCCESS;
14360}
14361
4389b29a
AV		 14362/* For branches in Armv8.1-M Mainline. */
14363static void
14364do_t_branch_future (void)
14365{
14366 unsigned long insn = inst.instruction;
14367
14368 inst.instruction = THUMB_OP32 (inst.instruction);
14369 if (inst.operands[0].hasreloc == 0)
14370 {
14371 if (v8_1_branch_value_check (inst.operands[0].imm, 5, FALSE) == FAIL)
14372 as_bad (BAD_BRANCH_OFF);
14373
14374 inst.instruction |= ((inst.operands[0].imm & 0x1f) >> 1) << 23;
14375 }
14376 else
14377 {
14378 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH5;
14379 inst.relocs[0].pc_rel = 1;
14380 }
14381
14382 switch (insn)
14383 {
14384 case T_MNEM_bf:
14385 if (inst.operands[1].hasreloc == 0)
14386 {
14387 int val = inst.operands[1].imm;
14388 if (v8_1_branch_value_check (inst.operands[1].imm, 17, TRUE) == FAIL)
14389 as_bad (BAD_BRANCH_OFF);
14390
14391 int immA = (val & 0x0001f000) >> 12;
14392 int immB = (val & 0x00000ffc) >> 2;
14393 int immC = (val & 0x00000002) >> 1;
14394 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14395 }
14396 else
14397 {
14398 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF17;
14399 inst.relocs[1].pc_rel = 1;
14400 }
14401 break;
14402
65d1bc05
AV		 14403 case T_MNEM_bfl:
14404 if (inst.operands[1].hasreloc == 0)
14405 {
14406 int val = inst.operands[1].imm;
14407 if (v8_1_branch_value_check (inst.operands[1].imm, 19, TRUE) == FAIL)
14408 as_bad (BAD_BRANCH_OFF);
14409
14410 int immA = (val & 0x0007f000) >> 12;
14411 int immB = (val & 0x00000ffc) >> 2;
14412 int immC = (val & 0x00000002) >> 1;
14413 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14414 }
14415 else
14416 {
14417 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF19;
14418 inst.relocs[1].pc_rel = 1;
14419 }
14420 break;
14421
f6b2b12d
AV		 14422 case T_MNEM_bfcsel:
14423 /* Operand 1. */
14424 if (inst.operands[1].hasreloc == 0)
14425 {
14426 int val = inst.operands[1].imm;
14427 int immA = (val & 0x00001000) >> 12;
14428 int immB = (val & 0x00000ffc) >> 2;
14429 int immC = (val & 0x00000002) >> 1;
14430 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14431 }
14432 else
14433 {
14434 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF13;
14435 inst.relocs[1].pc_rel = 1;
14436 }
14437
14438 /* Operand 2. */
14439 if (inst.operands[2].hasreloc == 0)
14440 {
14441 constraint ((inst.operands[0].hasreloc != 0), BAD_ARGS);
14442 int val2 = inst.operands[2].imm;
14443 int val0 = inst.operands[0].imm & 0x1f;
14444 int diff = val2 - val0;
14445 if (diff == 4)
14446 inst.instruction |= 1 << 17; /* T bit. */
14447 else if (diff != 2)
14448 as_bad (_("out of range label-relative fixup value"));
14449 }
14450 else
14451 {
14452 constraint ((inst.operands[0].hasreloc == 0), BAD_ARGS);
14453 inst.relocs[2].type = BFD_RELOC_THUMB_PCREL_BFCSEL;
14454 inst.relocs[2].pc_rel = 1;
14455 }
14456
14457 /* Operand 3. */
14458 constraint (inst.cond != COND_ALWAYS, BAD_COND);
14459 inst.instruction |= (inst.operands[3].imm & 0xf) << 18;
14460 break;
14461
f1c7f421
AV		 14462 case T_MNEM_bfx:
14463 case T_MNEM_bflx:
14464 inst.instruction |= inst.operands[1].reg << 16;
14465 break;
14466
4389b29a
AV		 14467 default: abort ();
14468 }
14469}
14470
60f993ce
AV		 14471/* Helper function for do_t_loloop to handle relocations. */
14472static void
14473v8_1_loop_reloc (int is_le)
14474{
14475 if (inst.relocs[0].exp.X_op == O_constant)
14476 {
14477 int value = inst.relocs[0].exp.X_add_number;
14478 value = (is_le) ? -value : value;
14479
14480 if (v8_1_branch_value_check (value, 12, FALSE) == FAIL)
14481 as_bad (BAD_BRANCH_OFF);
14482
14483 int imml, immh;
14484
14485 immh = (value & 0x00000ffc) >> 2;
14486 imml = (value & 0x00000002) >> 1;
14487
14488 inst.instruction |= (imml << 11) | (immh << 1);
14489 }
14490 else
14491 {
14492 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_LOOP12;
14493 inst.relocs[0].pc_rel = 1;
14494 }
14495}
14496
08132bdd
SP		 14497/* For shifts with four operands in MVE. */
14498static void
14499do_mve_scalar_shift1 (void)
14500{
14501 unsigned int value = inst.operands[2].imm;
14502
14503 inst.instruction |= inst.operands[0].reg << 16;
14504 inst.instruction |= inst.operands[1].reg << 8;
14505
14506 /* Setting the bit for saturation. */
14507 inst.instruction |= ((value == 64) ? 0: 1) << 7;
14508
14509 /* Assuming Rm is already checked not to be 11x1. */
14510 constraint (inst.operands[3].reg == inst.operands[0].reg, BAD_OVERLAP);
14511 constraint (inst.operands[3].reg == inst.operands[1].reg, BAD_OVERLAP);
14512 inst.instruction |= inst.operands[3].reg << 12;
14513}
14514
23d00a41
SD		 14515/* For shifts in MVE. */
14516static void
14517do_mve_scalar_shift (void)
14518{
14519 if (!inst.operands[2].present)
14520 {
14521 inst.operands[2] = inst.operands[1];
14522 inst.operands[1].reg = 0xf;
14523 }
14524
14525 inst.instruction |= inst.operands[0].reg << 16;
14526 inst.instruction |= inst.operands[1].reg << 8;
14527
14528 if (inst.operands[2].isreg)
14529 {
14530 /* Assuming Rm is already checked not to be 11x1. */
14531 constraint (inst.operands[2].reg == inst.operands[0].reg, BAD_OVERLAP);
14532 constraint (inst.operands[2].reg == inst.operands[1].reg, BAD_OVERLAP);
14533 inst.instruction |= inst.operands[2].reg << 12;
14534 }
14535 else
14536 {
14537 /* Assuming imm is already checked as [1,32]. */
14538 unsigned int value = inst.operands[2].imm;
14539 inst.instruction |= (value & 0x1c) << 10;
14540 inst.instruction |= (value & 0x03) << 6;
14541 /* Change last 4 bits from 0xd to 0xf. */
14542 inst.instruction |= 0x2;
14543 }
14544}
14545
a302e574
AV		 14546/* MVE instruction encoder helpers. */
14547#define M_MNEM_vabav 0xee800f01
14548#define M_MNEM_vmladav 0xeef00e00
14549#define M_MNEM_vmladava 0xeef00e20
14550#define M_MNEM_vmladavx 0xeef01e00
14551#define M_MNEM_vmladavax 0xeef01e20
14552#define M_MNEM_vmlsdav 0xeef00e01
14553#define M_MNEM_vmlsdava 0xeef00e21
14554#define M_MNEM_vmlsdavx 0xeef01e01
14555#define M_MNEM_vmlsdavax 0xeef01e21
886e1c73
AV		 14556#define M_MNEM_vmullt 0xee011e00
14557#define M_MNEM_vmullb 0xee010e00
efd0b310 14558#define M_MNEM_vctp 0xf000e801
35c228db
AV		 14559#define M_MNEM_vst20 0xfc801e00
14560#define M_MNEM_vst21 0xfc801e20
14561#define M_MNEM_vst40 0xfc801e01
14562#define M_MNEM_vst41 0xfc801e21
14563#define M_MNEM_vst42 0xfc801e41
14564#define M_MNEM_vst43 0xfc801e61
14565#define M_MNEM_vld20 0xfc901e00
14566#define M_MNEM_vld21 0xfc901e20
14567#define M_MNEM_vld40 0xfc901e01
14568#define M_MNEM_vld41 0xfc901e21
14569#define M_MNEM_vld42 0xfc901e41
14570#define M_MNEM_vld43 0xfc901e61
f5f10c66
AV		 14571#define M_MNEM_vstrb 0xec000e00
14572#define M_MNEM_vstrh 0xec000e10
14573#define M_MNEM_vstrw 0xec000e40
14574#define M_MNEM_vstrd 0xec000e50
14575#define M_MNEM_vldrb 0xec100e00
14576#define M_MNEM_vldrh 0xec100e10
14577#define M_MNEM_vldrw 0xec100e40
14578#define M_MNEM_vldrd 0xec100e50
57785aa2
AV		 14579#define M_MNEM_vmovlt 0xeea01f40
14580#define M_MNEM_vmovlb 0xeea00f40
14581#define M_MNEM_vmovnt 0xfe311e81
14582#define M_MNEM_vmovnb 0xfe310e81
c2dafc2a
AV		 14583#define M_MNEM_vadc 0xee300f00
14584#define M_MNEM_vadci 0xee301f00
14585#define M_MNEM_vbrsr 0xfe011e60
26c1e780
AV		 14586#define M_MNEM_vaddlv 0xee890f00
14587#define M_MNEM_vaddlva 0xee890f20
14588#define M_MNEM_vaddv 0xeef10f00
14589#define M_MNEM_vaddva 0xeef10f20
b409bdb6
AV		 14590#define M_MNEM_vddup 0xee011f6e
14591#define M_MNEM_vdwdup 0xee011f60
14592#define M_MNEM_vidup 0xee010f6e
14593#define M_MNEM_viwdup 0xee010f60
13ccd4c0
AV		 14594#define M_MNEM_vmaxv 0xeee20f00
14595#define M_MNEM_vmaxav 0xeee00f00
14596#define M_MNEM_vminv 0xeee20f80
14597#define M_MNEM_vminav 0xeee00f80
93925576
AV		 14598#define M_MNEM_vmlaldav 0xee800e00
14599#define M_MNEM_vmlaldava 0xee800e20
14600#define M_MNEM_vmlaldavx 0xee801e00
14601#define M_MNEM_vmlaldavax 0xee801e20
14602#define M_MNEM_vmlsldav 0xee800e01
14603#define M_MNEM_vmlsldava 0xee800e21
14604#define M_MNEM_vmlsldavx 0xee801e01
14605#define M_MNEM_vmlsldavax 0xee801e21
14606#define M_MNEM_vrmlaldavhx 0xee801f00
14607#define M_MNEM_vrmlaldavhax 0xee801f20
14608#define M_MNEM_vrmlsldavh 0xfe800e01
14609#define M_MNEM_vrmlsldavha 0xfe800e21
14610#define M_MNEM_vrmlsldavhx 0xfe801e01
14611#define M_MNEM_vrmlsldavhax 0xfe801e21
1be7aba3
AV		 14612#define M_MNEM_vqmovnt 0xee331e01
14613#define M_MNEM_vqmovnb 0xee330e01
14614#define M_MNEM_vqmovunt 0xee311e81
14615#define M_MNEM_vqmovunb 0xee310e81
4aa88b50
AV		 14616#define M_MNEM_vshrnt 0xee801fc1
14617#define M_MNEM_vshrnb 0xee800fc1
14618#define M_MNEM_vrshrnt 0xfe801fc1
14619#define M_MNEM_vqshrnt 0xee801f40
14620#define M_MNEM_vqshrnb 0xee800f40
14621#define M_MNEM_vqshrunt 0xee801fc0
14622#define M_MNEM_vqshrunb 0xee800fc0
14623#define M_MNEM_vrshrnb 0xfe800fc1
14624#define M_MNEM_vqrshrnt 0xee801f41
14625#define M_MNEM_vqrshrnb 0xee800f41
14626#define M_MNEM_vqrshrunt 0xfe801fc0
14627#define M_MNEM_vqrshrunb 0xfe800fc0
a302e574 14628
aab2c27d
MM		 14629/* Bfloat16 instruction encoder helpers. */
14630#define B_MNEM_vfmat 0xfc300850
14631#define B_MNEM_vfmab 0xfc300810
14632
5287ad62 14633/* Neon instruction encoder helpers. */
5f4273c7 14634
5287ad62 14635/* Encodings for the different types for various Neon opcodes. */
b99bd4ef 14636
5287ad62
JB		 14637/* An "invalid" code for the following tables. */
14638#define N_INV -1u
14639
14640struct neon_tab_entry
b99bd4ef 14641{
5287ad62
JB		 14642 unsigned integer;
14643 unsigned float_or_poly;
14644 unsigned scalar_or_imm;
14645};
5f4273c7 14646
5287ad62
JB		 14647/* Map overloaded Neon opcodes to their respective encodings. */
14648#define NEON_ENC_TAB \
14649 X(vabd, 0x0000700, 0x1200d00, N_INV), \
5ee91343 14650 X(vabdl, 0x0800700, N_INV, N_INV), \
5287ad62
JB		 14651 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14652 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14653 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14654 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14655 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14656 X(vadd, 0x0000800, 0x0000d00, N_INV), \
5ee91343 14657 X(vaddl, 0x0800000, N_INV, N_INV), \
5287ad62 14658 X(vsub, 0x1000800, 0x0200d00, N_INV), \
5ee91343 14659 X(vsubl, 0x0800200, N_INV, N_INV), \
5287ad62
JB		 14660 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14661 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14662 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14663 /* Register variants of the following two instructions are encoded as
e07e6e58 14664 vcge / vcgt with the operands reversed. */ \
92559b5b
PB		 14665 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14666 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
62f3b8c8
PB		 14667 X(vfma, N_INV, 0x0000c10, N_INV), \
14668 X(vfms, N_INV, 0x0200c10, N_INV), \
5287ad62
JB		 14669 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14670 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14671 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14672 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14673 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14674 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14675 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14676 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14677 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14678 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14679 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
d6b4b13e
MW		 14680 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14681 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
5287ad62
JB		 14682 X(vshl, 0x0000400, N_INV, 0x0800510), \
14683 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14684 X(vand, 0x0000110, N_INV, 0x0800030), \
14685 X(vbic, 0x0100110, N_INV, 0x0800030), \
14686 X(veor, 0x1000110, N_INV, N_INV), \
14687 X(vorn, 0x0300110, N_INV, 0x0800010), \
14688 X(vorr, 0x0200110, N_INV, 0x0800010), \
14689 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14690 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14691 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14692 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14693 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14694 X(vst1, 0x0000000, 0x0800000, N_INV), \
14695 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14696 X(vst2, 0x0000100, 0x0800100, N_INV), \
14697 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14698 X(vst3, 0x0000200, 0x0800200, N_INV), \
14699 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14700 X(vst4, 0x0000300, 0x0800300, N_INV), \
14701 X(vmovn, 0x1b20200, N_INV, N_INV), \
14702 X(vtrn, 0x1b20080, N_INV, N_INV), \
14703 X(vqmovn, 0x1b20200, N_INV, N_INV), \
037e8744
JB		 14704 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14705 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
e6655fda
PB		 14706 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14707 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
62f3b8c8
PB		 14708 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14709 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
037e8744
JB		 14710 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14711 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14712 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
33399f07
MGD		 14713 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14714 X(vseleq, 0xe000a00, N_INV, N_INV), \
14715 X(vselvs, 0xe100a00, N_INV, N_INV), \
14716 X(vselge, 0xe200a00, N_INV, N_INV), \
73924fbc
MGD		 14717 X(vselgt, 0xe300a00, N_INV, N_INV), \
14718 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
7e8e6784 14719 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
30bdf752
MGD		 14720 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14721 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
91ff7894 14722 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
48adcd8e 14723 X(aes, 0x3b00300, N_INV, N_INV), \
3c9017d2
MGD		 14724 X(sha3op, 0x2000c00, N_INV, N_INV), \
14725 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14726 X(sha2op, 0x3ba0380, N_INV, N_INV)
5287ad62
JB		 14727
14728enum neon_opc
14729{
14730#define X(OPC,I,F,S) N_MNEM_##OPC
14731NEON_ENC_TAB
14732#undef X
14733};
b99bd4ef 14734
5287ad62
JB		 14735static const struct neon_tab_entry neon_enc_tab[] =
14736{
14737#define X(OPC,I,F,S) { (I), (F), (S) }
14738NEON_ENC_TAB
14739#undef X
14740};
b99bd4ef 14741
88714cb8
DG		 14742/* Do not use these macros; instead, use NEON_ENCODE defined below. */
14743#define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14744#define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14745#define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14746#define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14747#define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14748#define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14749#define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14750#define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14751#define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14752#define NEON_ENC_SINGLE_(X) \
037e8744 14753 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
88714cb8 14754#define NEON_ENC_DOUBLE_(X) \
037e8744 14755 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
33399f07
MGD		 14756#define NEON_ENC_FPV8_(X) \
14757 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
5287ad62 14758
88714cb8
DG		 14759#define NEON_ENCODE(type, inst) \
14760 do \
14761 { \
14762 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14763 inst.is_neon = 1; \
14764 } \
14765 while (0)
14766
14767#define check_neon_suffixes \
14768 do \
14769 { \
14770 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14771 { \
14772 as_bad (_("invalid neon suffix for non neon instruction")); \
14773 return; \
14774 } \
14775 } \
14776 while (0)
14777
037e8744
JB		 14778/* Define shapes for instruction operands. The following mnemonic characters
14779 are used in this table:
5287ad62 14780
037e8744 14781 F - VFP S<n> register
5287ad62
JB		 14782 D - Neon D<n> register
14783 Q - Neon Q<n> register
14784 I - Immediate
14785 S - Scalar
14786 R - ARM register
14787 L - D<n> register list
5f4273c7 14788
037e8744
JB		 14789 This table is used to generate various data:
14790 - enumerations of the form NS_DDR to be used as arguments to
14791 neon_select_shape.
14792 - a table classifying shapes into single, double, quad, mixed.
5f4273c7 14793 - a table used to drive neon_select_shape. */
b99bd4ef 14794
037e8744 14795#define NEON_SHAPE_DEF \
93925576 14796 X(4, (R, R, Q, Q), QUAD), \
b409bdb6 14797 X(4, (Q, R, R, I), QUAD), \
57785aa2
AV		 14798 X(4, (R, R, S, S), QUAD), \
14799 X(4, (S, S, R, R), QUAD), \
b409bdb6 14800 X(3, (Q, R, I), QUAD), \
1b883319
AV		 14801 X(3, (I, Q, Q), QUAD), \
14802 X(3, (I, Q, R), QUAD), \
a302e574 14803 X(3, (R, Q, Q), QUAD), \
037e8744
JB		 14804 X(3, (D, D, D), DOUBLE), \
14805 X(3, (Q, Q, Q), QUAD), \
14806 X(3, (D, D, I), DOUBLE), \
14807 X(3, (Q, Q, I), QUAD), \
14808 X(3, (D, D, S), DOUBLE), \
14809 X(3, (Q, Q, S), QUAD), \
5ee91343 14810 X(3, (Q, Q, R), QUAD), \
26c1e780
AV		 14811 X(3, (R, R, Q), QUAD), \
14812 X(2, (R, Q), QUAD), \
037e8744
JB		 14813 X(2, (D, D), DOUBLE), \
14814 X(2, (Q, Q), QUAD), \
14815 X(2, (D, S), DOUBLE), \
14816 X(2, (Q, S), QUAD), \
14817 X(2, (D, R), DOUBLE), \
14818 X(2, (Q, R), QUAD), \
14819 X(2, (D, I), DOUBLE), \
14820 X(2, (Q, I), QUAD), \
5aae9ae9
MM		 14821 X(3, (P, F, I), SINGLE), \
14822 X(3, (P, D, I), DOUBLE), \
14823 X(3, (P, Q, I), QUAD), \
14824 X(4, (P, F, F, I), SINGLE), \
14825 X(4, (P, D, D, I), DOUBLE), \
14826 X(4, (P, Q, Q, I), QUAD), \
14827 X(5, (P, F, F, F, I), SINGLE), \
14828 X(5, (P, D, D, D, I), DOUBLE), \
14829 X(5, (P, Q, Q, Q, I), QUAD), \
037e8744
JB		 14830 X(3, (D, L, D), DOUBLE), \
14831 X(2, (D, Q), MIXED), \
14832 X(2, (Q, D), MIXED), \
14833 X(3, (D, Q, I), MIXED), \
14834 X(3, (Q, D, I), MIXED), \
14835 X(3, (Q, D, D), MIXED), \
14836 X(3, (D, Q, Q), MIXED), \
14837 X(3, (Q, Q, D), MIXED), \
14838 X(3, (Q, D, S), MIXED), \
14839 X(3, (D, Q, S), MIXED), \
14840 X(4, (D, D, D, I), DOUBLE), \
14841 X(4, (Q, Q, Q, I), QUAD), \
c28eeff2
SN		 14842 X(4, (D, D, S, I), DOUBLE), \
14843 X(4, (Q, Q, S, I), QUAD), \
037e8744
JB		 14844 X(2, (F, F), SINGLE), \
14845 X(3, (F, F, F), SINGLE), \
14846 X(2, (F, I), SINGLE), \
14847 X(2, (F, D), MIXED), \
14848 X(2, (D, F), MIXED), \
14849 X(3, (F, F, I), MIXED), \
14850 X(4, (R, R, F, F), SINGLE), \
14851 X(4, (F, F, R, R), SINGLE), \
14852 X(3, (D, R, R), DOUBLE), \
14853 X(3, (R, R, D), DOUBLE), \
14854 X(2, (S, R), SINGLE), \
14855 X(2, (R, S), SINGLE), \
14856 X(2, (F, R), SINGLE), \
d54af2d0 14857 X(2, (R, F), SINGLE), \
1f6234a3
AV		 14858/* Used for MVE tail predicated loop instructions. */\
14859 X(2, (R, R), QUAD), \
d54af2d0
RL		 14860/* Half float shape supported so far. */\
14861 X (2, (H, D), MIXED), \
14862 X (2, (D, H), MIXED), \
14863 X (2, (H, F), MIXED), \
14864 X (2, (F, H), MIXED), \
14865 X (2, (H, H), HALF), \
14866 X (2, (H, R), HALF), \
14867 X (2, (R, H), HALF), \
14868 X (2, (H, I), HALF), \
14869 X (3, (H, H, H), HALF), \
14870 X (3, (H, F, I), MIXED), \
dec41383
JW		 14871 X (3, (F, H, I), MIXED), \
14872 X (3, (D, H, H), MIXED), \
14873 X (3, (D, H, S), MIXED)
037e8744
JB		 14874
14875#define S2(A,B) NS_##A##B
14876#define S3(A,B,C) NS_##A##B##C
14877#define S4(A,B,C,D) NS_##A##B##C##D
5aae9ae9 14878#define S5(A,B,C,D,E) NS_##A##B##C##D##E
037e8744
JB		 14879
14880#define X(N, L, C) S##N L
14881
5287ad62
JB		 14882enum neon_shape
14883{
037e8744
JB		 14884 NEON_SHAPE_DEF,
14885 NS_NULL
5287ad62 14886};
b99bd4ef 14887
037e8744
JB		 14888#undef X
14889#undef S2
14890#undef S3
14891#undef S4
5aae9ae9 14892#undef S5
037e8744
JB		 14893
14894enum neon_shape_class
14895{
d54af2d0 14896 SC_HALF,
037e8744
JB		 14897 SC_SINGLE,
14898 SC_DOUBLE,
14899 SC_QUAD,
14900 SC_MIXED
14901};
14902
14903#define X(N, L, C) SC_##C
14904
14905static enum neon_shape_class neon_shape_class[] =
14906{
14907 NEON_SHAPE_DEF
14908};
14909
14910#undef X
14911
14912enum neon_shape_el
14913{
d54af2d0 14914 SE_H,
037e8744
JB		 14915 SE_F,
14916 SE_D,
14917 SE_Q,
14918 SE_I,
14919 SE_S,
14920 SE_R,
5aae9ae9
MM		 14921 SE_L,
14922 SE_P
037e8744
JB		 14923};
14924
14925/* Register widths of above. */
14926static unsigned neon_shape_el_size[] =
14927{
d54af2d0 14928 16,
037e8744
JB		 14929 32,
14930 64,
14931 128,
14932 0,
14933 32,
14934 32,
5aae9ae9 14935 0,
037e8744
JB		 14936 0
14937};
14938
14939struct neon_shape_info
14940{
14941 unsigned els;
14942 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
14943};
14944
14945#define S2(A,B) { SE_##A, SE_##B }
14946#define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14947#define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
5aae9ae9 14948#define S5(A,B,C,D,E) { SE_##A, SE_##B, SE_##C, SE_##D, SE_##E }
037e8744
JB		 14949
14950#define X(N, L, C) { N, S##N L }
14951
14952static struct neon_shape_info neon_shape_tab[] =
14953{
14954 NEON_SHAPE_DEF
14955};
14956
14957#undef X
14958#undef S2
14959#undef S3
14960#undef S4
5aae9ae9 14961#undef S5
037e8744 14962
5287ad62
JB		 14963/* Bit masks used in type checking given instructions.
14964 'N_EQK' means the type must be the same as (or based on in some way) the key
14965 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14966 set, various other bits can be set as well in order to modify the meaning of
14967 the type constraint. */
14968
14969enum neon_type_mask
14970{
8e79c3df
CM		 14971 N_S8 = 0x0000001,
14972 N_S16 = 0x0000002,
14973 N_S32 = 0x0000004,
14974 N_S64 = 0x0000008,
14975 N_U8 = 0x0000010,
14976 N_U16 = 0x0000020,
14977 N_U32 = 0x0000040,
14978 N_U64 = 0x0000080,
14979 N_I8 = 0x0000100,
14980 N_I16 = 0x0000200,
14981 N_I32 = 0x0000400,
14982 N_I64 = 0x0000800,
14983 N_8 = 0x0001000,
14984 N_16 = 0x0002000,
14985 N_32 = 0x0004000,
14986 N_64 = 0x0008000,
14987 N_P8 = 0x0010000,
14988 N_P16 = 0x0020000,
14989 N_F16 = 0x0040000,
14990 N_F32 = 0x0080000,
14991 N_F64 = 0x0100000,
4f51b4bd 14992 N_P64 = 0x0200000,
aab2c27d 14993 N_BF16 = 0x0400000,
c921be7d
NC		 14994 N_KEY = 0x1000000, /* Key element (main type specifier). */
14995 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
8e79c3df 14996 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
91ff7894 14997 N_UNT = 0x8000000, /* Must be explicitly untyped. */
c921be7d
NC		 14998 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
14999 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
15000 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
15001 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
15002 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
15003 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
15004 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
5287ad62 15005 N_UTYP = 0,
4f51b4bd 15006 N_MAX_NONSPECIAL = N_P64
5287ad62
JB		 15007};
15008
dcbf9037
JB		 15009#define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
15010
5287ad62
JB		 15011#define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
15012#define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
15013#define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
cc933301
JW		 15014#define N_S_32 (N_S8 | N_S16 | N_S32)
15015#define N_F_16_32 (N_F16 | N_F32)
15016#define N_SUF_32 (N_SU_32 | N_F_16_32)
5287ad62 15017#define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
cc933301 15018#define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
d54af2d0 15019#define N_F_ALL (N_F16 | N_F32 | N_F64)
5ee91343
AV		 15020#define N_I_MVE (N_I8 | N_I16 | N_I32)
15021#define N_F_MVE (N_F16 | N_F32)
15022#define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
5287ad62
JB		 15023
15024/* Pass this as the first type argument to neon_check_type to ignore types
15025 altogether. */
15026#define N_IGNORE_TYPE (N_KEY | N_EQK)
15027
037e8744
JB		 15028/* Select a "shape" for the current instruction (describing register types or
15029 sizes) from a list of alternatives. Return NS_NULL if the current instruction
15030 doesn't fit. For non-polymorphic shapes, checking is usually done as a
15031 function of operand parsing, so this function doesn't need to be called.
15032 Shapes should be listed in order of decreasing length. */
5287ad62
JB		 15033
15034static enum neon_shape
037e8744 15035neon_select_shape (enum neon_shape shape, ...)
5287ad62 15036{
037e8744
JB		 15037 va_list ap;
15038 enum neon_shape first_shape = shape;
5287ad62
JB		 15039
15040 /* Fix missing optional operands. FIXME: we don't know at this point how
15041 many arguments we should have, so this makes the assumption that we have
15042 > 1. This is true of all current Neon opcodes, I think, but may not be
15043 true in the future. */
15044 if (!inst.operands[1].present)
15045 inst.operands[1] = inst.operands[0];
15046
037e8744 15047 va_start (ap, shape);
5f4273c7 15048
21d799b5 15049 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
037e8744
JB		 15050 {
15051 unsigned j;
15052 int matches = 1;
15053
15054 for (j = 0; j < neon_shape_tab[shape].els; j++)
477330fc
RM		 15055 {
15056 if (!inst.operands[j].present)
15057 {
15058 matches = 0;
15059 break;
15060 }
15061
15062 switch (neon_shape_tab[shape].el[j])
15063 {
d54af2d0
RL		 15064 /* If a .f16, .16, .u16, .s16 type specifier is given over
15065 a VFP single precision register operand, it's essentially
15066 means only half of the register is used.
15067
15068 If the type specifier is given after the mnemonics, the
15069 information is stored in inst.vectype. If the type specifier
15070 is given after register operand, the information is stored
15071 in inst.operands[].vectype.
15072
15073 When there is only one type specifier, and all the register
15074 operands are the same type of hardware register, the type
15075 specifier applies to all register operands.
15076
15077 If no type specifier is given, the shape is inferred from
15078 operand information.
15079
15080 for example:
15081 vadd.f16 s0, s1, s2: NS_HHH
15082 vabs.f16 s0, s1: NS_HH
15083 vmov.f16 s0, r1: NS_HR
15084 vmov.f16 r0, s1: NS_RH
15085 vcvt.f16 r0, s1: NS_RH
15086 vcvt.f16.s32 s2, s2, #29: NS_HFI
15087 vcvt.f16.s32 s2, s2: NS_HF
15088 */
15089 case SE_H:
15090 if (!(inst.operands[j].isreg
15091 && inst.operands[j].isvec
15092 && inst.operands[j].issingle
15093 && !inst.operands[j].isquad
15094 && ((inst.vectype.elems == 1
15095 && inst.vectype.el[0].size == 16)
15096 || (inst.vectype.elems > 1
15097 && inst.vectype.el[j].size == 16)
15098 || (inst.vectype.elems == 0
15099 && inst.operands[j].vectype.type != NT_invtype
15100 && inst.operands[j].vectype.size == 16))))
15101 matches = 0;
15102 break;
15103
477330fc
RM		 15104 case SE_F:
15105 if (!(inst.operands[j].isreg
15106 && inst.operands[j].isvec
15107 && inst.operands[j].issingle
d54af2d0
RL		 15108 && !inst.operands[j].isquad
15109 && ((inst.vectype.elems == 1 && inst.vectype.el[0].size == 32)
15110 || (inst.vectype.elems > 1 && inst.vectype.el[j].size == 32)
15111 || (inst.vectype.elems == 0
15112 && (inst.operands[j].vectype.size == 32
15113 || inst.operands[j].vectype.type == NT_invtype)))))
477330fc
RM		 15114 matches = 0;
15115 break;
15116
15117 case SE_D:
15118 if (!(inst.operands[j].isreg
15119 && inst.operands[j].isvec
15120 && !inst.operands[j].isquad
15121 && !inst.operands[j].issingle))
15122 matches = 0;
15123 break;
15124
15125 case SE_R:
15126 if (!(inst.operands[j].isreg
15127 && !inst.operands[j].isvec))
15128 matches = 0;
15129 break;
15130
15131 case SE_Q:
15132 if (!(inst.operands[j].isreg
15133 && inst.operands[j].isvec
15134 && inst.operands[j].isquad
15135 && !inst.operands[j].issingle))
15136 matches = 0;
15137 break;
15138
15139 case SE_I:
15140 if (!(!inst.operands[j].isreg
15141 && !inst.operands[j].isscalar))
15142 matches = 0;
15143 break;
15144
15145 case SE_S:
15146 if (!(!inst.operands[j].isreg
15147 && inst.operands[j].isscalar))
15148 matches = 0;
15149 break;
15150
5aae9ae9 15151 case SE_P:
477330fc
RM		 15152 case SE_L:
15153 break;
15154 }
3fde54a2
JZ		 15155 if (!matches)
15156 break;
477330fc 15157 }
ad6cec43
MGD		 15158 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
15159 /* We've matched all the entries in the shape table, and we don't
15160 have any left over operands which have not been matched. */
477330fc 15161 break;
037e8744 15162 }
5f4273c7 15163
037e8744 15164 va_end (ap);
5287ad62 15165
037e8744
JB		 15166 if (shape == NS_NULL && first_shape != NS_NULL)
15167 first_error (_("invalid instruction shape"));
5287ad62 15168
037e8744
JB		 15169 return shape;
15170}
5287ad62 15171
037e8744
JB		 15172/* True if SHAPE is predominantly a quadword operation (most of the time, this
15173 means the Q bit should be set). */
15174
15175static int
15176neon_quad (enum neon_shape shape)
15177{
15178 return neon_shape_class[shape] == SC_QUAD;
5287ad62 15179}
037e8744 15180
5287ad62
JB		 15181static void
15182neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
477330fc 15183 unsigned *g_size)
5287ad62
JB		 15184{
15185 /* Allow modification to be made to types which are constrained to be
15186 based on the key element, based on bits set alongside N_EQK. */
15187 if ((typebits & N_EQK) != 0)
15188 {
15189 if ((typebits & N_HLF) != 0)
15190 *g_size /= 2;
15191 else if ((typebits & N_DBL) != 0)
15192 *g_size *= 2;
15193 if ((typebits & N_SGN) != 0)
15194 *g_type = NT_signed;
15195 else if ((typebits & N_UNS) != 0)
477330fc 15196 *g_type = NT_unsigned;
5287ad62 15197 else if ((typebits & N_INT) != 0)
477330fc 15198 *g_type = NT_integer;
5287ad62 15199 else if ((typebits & N_FLT) != 0)
477330fc 15200 *g_type = NT_float;
dcbf9037 15201 else if ((typebits & N_SIZ) != 0)
477330fc 15202 *g_type = NT_untyped;
5287ad62
JB		 15203 }
15204}
5f4273c7 15205
5287ad62
JB		 15206/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
15207 operand type, i.e. the single type specified in a Neon instruction when it
15208 is the only one given. */
15209
15210static struct neon_type_el
15211neon_type_promote (struct neon_type_el *key, unsigned thisarg)
15212{
15213 struct neon_type_el dest = *key;
5f4273c7 15214
9c2799c2 15215 gas_assert ((thisarg & N_EQK) != 0);
5f4273c7 15216
5287ad62
JB		 15217 neon_modify_type_size (thisarg, &dest.type, &dest.size);
15218
15219 return dest;
15220}
15221
15222/* Convert Neon type and size into compact bitmask representation. */
15223
15224static enum neon_type_mask
15225type_chk_of_el_type (enum neon_el_type type, unsigned size)
15226{
15227 switch (type)
15228 {
15229 case NT_untyped:
15230 switch (size)
477330fc
RM		 15231 {
15232 case 8: return N_8;
15233 case 16: return N_16;
15234 case 32: return N_32;
15235 case 64: return N_64;
15236 default: ;
15237 }
5287ad62
JB		 15238 break;
15239
15240 case NT_integer:
15241 switch (size)
477330fc
RM		 15242 {
15243 case 8: return N_I8;
15244 case 16: return N_I16;
15245 case 32: return N_I32;
15246 case 64: return N_I64;
15247 default: ;
15248 }
5287ad62
JB		 15249 break;
15250
15251 case NT_float:
037e8744 15252 switch (size)
477330fc 15253 {
8e79c3df 15254 case 16: return N_F16;
477330fc
RM		 15255 case 32: return N_F32;
15256 case 64: return N_F64;
15257 default: ;
15258 }
5287ad62
JB		 15259 break;
15260
15261 case NT_poly:
15262 switch (size)
477330fc
RM		 15263 {
15264 case 8: return N_P8;
15265 case 16: return N_P16;
4f51b4bd 15266 case 64: return N_P64;
477330fc
RM		 15267 default: ;
15268 }
5287ad62
JB		 15269 break;
15270
15271 case NT_signed:
15272 switch (size)
477330fc
RM		 15273 {
15274 case 8: return N_S8;
15275 case 16: return N_S16;
15276 case 32: return N_S32;
15277 case 64: return N_S64;
15278 default: ;
15279 }
5287ad62
JB		 15280 break;
15281
15282 case NT_unsigned:
15283 switch (size)
477330fc
RM		 15284 {
15285 case 8: return N_U8;
15286 case 16: return N_U16;
15287 case 32: return N_U32;
15288 case 64: return N_U64;
15289 default: ;
15290 }
5287ad62
JB		 15291 break;
15292
aab2c27d
MM		 15293 case NT_bfloat:
15294 if (size == 16) return N_BF16;
15295 break;
15296
5287ad62
JB		 15297 default: ;
15298 }
5f4273c7 15299
5287ad62
JB		 15300 return N_UTYP;
15301}
15302
15303/* Convert compact Neon bitmask type representation to a type and size. Only
15304 handles the case where a single bit is set in the mask. */
15305
dcbf9037 15306static int
5287ad62 15307el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
477330fc 15308 enum neon_type_mask mask)
5287ad62 15309{
dcbf9037
JB		 15310 if ((mask & N_EQK) != 0)
15311 return FAIL;
15312
5287ad62
JB		 15313 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
15314 *size = 8;
aab2c27d
MM		 15315 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16 | N_BF16))
15316 != 0)
5287ad62 15317 *size = 16;
dcbf9037 15318 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
5287ad62 15319 *size = 32;
4f51b4bd 15320 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0)
5287ad62 15321 *size = 64;
dcbf9037
JB		 15322 else
15323 return FAIL;
15324
5287ad62
JB		 15325 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
15326 *type = NT_signed;
dcbf9037 15327 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
5287ad62 15328 *type = NT_unsigned;
dcbf9037 15329 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
5287ad62 15330 *type = NT_integer;
dcbf9037 15331 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
5287ad62 15332 *type = NT_untyped;
4f51b4bd 15333 else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
5287ad62 15334 *type = NT_poly;
d54af2d0 15335 else if ((mask & (N_F_ALL)) != 0)
5287ad62 15336 *type = NT_float;
aab2c27d
MM		 15337 else if ((mask & (N_BF16)) != 0)
15338 *type = NT_bfloat;
dcbf9037
JB		 15339 else
15340 return FAIL;
5f4273c7 15341
dcbf9037 15342 return SUCCESS;
5287ad62
JB		 15343}
15344
15345/* Modify a bitmask of allowed types. This is only needed for type
15346 relaxation. */
15347
15348static unsigned
15349modify_types_allowed (unsigned allowed, unsigned mods)
15350{
15351 unsigned size;
15352 enum neon_el_type type;
15353 unsigned destmask;
15354 int i;
5f4273c7 15355
5287ad62 15356 destmask = 0;
5f4273c7 15357
5287ad62
JB		 15358 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
15359 {
21d799b5 15360 if (el_type_of_type_chk (&type, &size,
477330fc
RM		 15361 (enum neon_type_mask) (allowed & i)) == SUCCESS)
15362 {
15363 neon_modify_type_size (mods, &type, &size);
15364 destmask |= type_chk_of_el_type (type, size);
15365 }
5287ad62 15366 }
5f4273c7 15367
5287ad62
JB		 15368 return destmask;
15369}
15370
15371/* Check type and return type classification.
15372 The manual states (paraphrase): If one datatype is given, it indicates the
15373 type given in:
15374 - the second operand, if there is one
15375 - the operand, if there is no second operand
15376 - the result, if there are no operands.
15377 This isn't quite good enough though, so we use a concept of a "key" datatype
15378 which is set on a per-instruction basis, which is the one which matters when
15379 only one data type is written.
15380 Note: this function has side-effects (e.g. filling in missing operands). All
037e8744 15381 Neon instructions should call it before performing bit encoding. */
5287ad62
JB		 15382
15383static struct neon_type_el
15384neon_check_type (unsigned els, enum neon_shape ns, ...)
15385{
15386 va_list ap;
15387 unsigned i, pass, key_el = 0;
15388 unsigned types[NEON_MAX_TYPE_ELS];
15389 enum neon_el_type k_type = NT_invtype;
15390 unsigned k_size = -1u;
15391 struct neon_type_el badtype = {NT_invtype, -1};
15392 unsigned key_allowed = 0;
15393
15394 /* Optional registers in Neon instructions are always (not) in operand 1.
15395 Fill in the missing operand here, if it was omitted. */
15396 if (els > 1 && !inst.operands[1].present)
15397 inst.operands[1] = inst.operands[0];
15398
15399 /* Suck up all the varargs. */
15400 va_start (ap, ns);
15401 for (i = 0; i < els; i++)
15402 {
15403 unsigned thisarg = va_arg (ap, unsigned);
15404 if (thisarg == N_IGNORE_TYPE)
477330fc
RM		 15405 {
15406 va_end (ap);
15407 return badtype;
15408 }
5287ad62
JB		 15409 types[i] = thisarg;
15410 if ((thisarg & N_KEY) != 0)
477330fc 15411 key_el = i;
5287ad62
JB		 15412 }
15413 va_end (ap);
15414
dcbf9037
JB		 15415 if (inst.vectype.elems > 0)
15416 for (i = 0; i < els; i++)
15417 if (inst.operands[i].vectype.type != NT_invtype)
477330fc
RM		 15418 {
15419 first_error (_("types specified in both the mnemonic and operands"));
15420 return badtype;
15421 }
dcbf9037 15422
5287ad62
JB		 15423 /* Duplicate inst.vectype elements here as necessary.
15424 FIXME: No idea if this is exactly the same as the ARM assembler,
15425 particularly when an insn takes one register and one non-register
15426 operand. */
15427 if (inst.vectype.elems == 1 && els > 1)
15428 {
15429 unsigned j;
15430 inst.vectype.elems = els;
15431 inst.vectype.el[key_el] = inst.vectype.el[0];
15432 for (j = 0; j < els; j++)
477330fc
RM		 15433 if (j != key_el)
15434 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
15435 types[j]);
dcbf9037
JB		 15436 }
15437 else if (inst.vectype.elems == 0 && els > 0)
15438 {
15439 unsigned j;
15440 /* No types were given after the mnemonic, so look for types specified
477330fc
RM		 15441 after each operand. We allow some flexibility here; as long as the
15442 "key" operand has a type, we can infer the others. */
dcbf9037 15443 for (j = 0; j < els; j++)
477330fc
RM		 15444 if (inst.operands[j].vectype.type != NT_invtype)
15445 inst.vectype.el[j] = inst.operands[j].vectype;
dcbf9037
JB		 15446
15447 if (inst.operands[key_el].vectype.type != NT_invtype)
477330fc
RM		 15448 {
15449 for (j = 0; j < els; j++)
15450 if (inst.operands[j].vectype.type == NT_invtype)
15451 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
15452 types[j]);
15453 }
dcbf9037 15454 else
477330fc
RM		 15455 {
15456 first_error (_("operand types can't be inferred"));
15457 return badtype;
15458 }
5287ad62
JB		 15459 }
15460 else if (inst.vectype.elems != els)
15461 {
dcbf9037 15462 first_error (_("type specifier has the wrong number of parts"));
5287ad62
JB		 15463 return badtype;
15464 }
15465
15466 for (pass = 0; pass < 2; pass++)
15467 {
15468 for (i = 0; i < els; i++)
477330fc
RM		 15469 {
15470 unsigned thisarg = types[i];
15471 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
15472 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
15473 enum neon_el_type g_type = inst.vectype.el[i].type;
15474 unsigned g_size = inst.vectype.el[i].size;
15475
15476 /* Decay more-specific signed & unsigned types to sign-insensitive
5287ad62 15477 integer types if sign-specific variants are unavailable. */
477330fc 15478 if ((g_type == NT_signed || g_type == NT_unsigned)
5287ad62
JB		 15479 && (types_allowed & N_SU_ALL) == 0)
15480 g_type = NT_integer;
15481
477330fc 15482 /* If only untyped args are allowed, decay any more specific types to
5287ad62
JB		 15483 them. Some instructions only care about signs for some element
15484 sizes, so handle that properly. */
477330fc 15485 if (((types_allowed & N_UNT) == 0)
91ff7894
MGD		 15486 && ((g_size == 8 && (types_allowed & N_8) != 0)
15487 || (g_size == 16 && (types_allowed & N_16) != 0)
15488 || (g_size == 32 && (types_allowed & N_32) != 0)
15489 || (g_size == 64 && (types_allowed & N_64) != 0)))
5287ad62
JB		 15490 g_type = NT_untyped;
15491
477330fc
RM		 15492 if (pass == 0)
15493 {
15494 if ((thisarg & N_KEY) != 0)
15495 {
15496 k_type = g_type;
15497 k_size = g_size;
15498 key_allowed = thisarg & ~N_KEY;
cc933301
JW		 15499
15500 /* Check architecture constraint on FP16 extension. */
15501 if (k_size == 16
15502 && k_type == NT_float
15503 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
15504 {
15505 inst.error = _(BAD_FP16);
15506 return badtype;
15507 }
477330fc
RM		 15508 }
15509 }
15510 else
15511 {
15512 if ((thisarg & N_VFP) != 0)
15513 {
15514 enum neon_shape_el regshape;
15515 unsigned regwidth, match;
99b253c5
NC		 15516
15517 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15518 if (ns == NS_NULL)
15519 {
15520 first_error (_("invalid instruction shape"));
15521 return badtype;
15522 }
477330fc
RM		 15523 regshape = neon_shape_tab[ns].el[i];
15524 regwidth = neon_shape_el_size[regshape];
15525
15526 /* In VFP mode, operands must match register widths. If we
15527 have a key operand, use its width, else use the width of
15528 the current operand. */
15529 if (k_size != -1u)
15530 match = k_size;
15531 else
15532 match = g_size;
15533
9db2f6b4
RL		 15534 /* FP16 will use a single precision register. */
15535 if (regwidth == 32 && match == 16)
15536 {
15537 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
15538 match = regwidth;
15539 else
15540 {
15541 inst.error = _(BAD_FP16);
15542 return badtype;
15543 }
15544 }
15545
477330fc
RM		 15546 if (regwidth != match)
15547 {
15548 first_error (_("operand size must match register width"));
15549 return badtype;
15550 }
15551 }
15552
15553 if ((thisarg & N_EQK) == 0)
15554 {
15555 unsigned given_type = type_chk_of_el_type (g_type, g_size);
15556
15557 if ((given_type & types_allowed) == 0)
15558 {
a302e574 15559 first_error (BAD_SIMD_TYPE);
477330fc
RM		 15560 return badtype;
15561 }
15562 }
15563 else
15564 {
15565 enum neon_el_type mod_k_type = k_type;
15566 unsigned mod_k_size = k_size;
15567 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
15568 if (g_type != mod_k_type || g_size != mod_k_size)
15569 {
15570 first_error (_("inconsistent types in Neon instruction"));
15571 return badtype;
15572 }
15573 }
15574 }
15575 }
5287ad62
JB		 15576 }
15577
15578 return inst.vectype.el[key_el];
15579}
15580
037e8744 15581/* Neon-style VFP instruction forwarding. */
5287ad62 15582
037e8744
JB		 15583/* Thumb VFP instructions have 0xE in the condition field. */
15584
15585static void
15586do_vfp_cond_or_thumb (void)
5287ad62 15587{
88714cb8
DG		 15588 inst.is_neon = 1;
15589
5287ad62 15590 if (thumb_mode)
037e8744 15591 inst.instruction |= 0xe0000000;
5287ad62 15592 else
037e8744 15593 inst.instruction |= inst.cond << 28;
5287ad62
JB		 15594}
15595
037e8744
JB		 15596/* Look up and encode a simple mnemonic, for use as a helper function for the
15597 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15598 etc. It is assumed that operand parsing has already been done, and that the
15599 operands are in the form expected by the given opcode (this isn't necessarily
15600 the same as the form in which they were parsed, hence some massaging must
15601 take place before this function is called).
15602 Checks current arch version against that in the looked-up opcode. */
5287ad62 15603
037e8744
JB		 15604static void
15605do_vfp_nsyn_opcode (const char *opname)
5287ad62 15606{
037e8744 15607 const struct asm_opcode *opcode;
5f4273c7 15608
21d799b5 15609 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
5287ad62 15610
037e8744
JB		 15611 if (!opcode)
15612 abort ();
5287ad62 15613
037e8744 15614 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
477330fc
RM		 15615 thumb_mode ? *opcode->tvariant : *opcode->avariant),
15616 _(BAD_FPU));
5287ad62 15617
88714cb8
DG		 15618 inst.is_neon = 1;
15619
037e8744
JB		 15620 if (thumb_mode)
15621 {
15622 inst.instruction = opcode->tvalue;
15623 opcode->tencode ();
15624 }
15625 else
15626 {
15627 inst.instruction = (inst.cond << 28) | opcode->avalue;
15628 opcode->aencode ();
15629 }
15630}
5287ad62
JB		 15631
15632static void
037e8744 15633do_vfp_nsyn_add_sub (enum neon_shape rs)
5287ad62 15634{
037e8744
JB		 15635 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
15636
9db2f6b4 15637 if (rs == NS_FFF || rs == NS_HHH)
037e8744
JB		 15638 {
15639 if (is_add)
477330fc 15640 do_vfp_nsyn_opcode ("fadds");
037e8744 15641 else
477330fc 15642 do_vfp_nsyn_opcode ("fsubs");
9db2f6b4
RL		 15643
15644 /* ARMv8.2 fp16 instruction. */
15645 if (rs == NS_HHH)
15646 do_scalar_fp16_v82_encode ();
037e8744
JB		 15647 }
15648 else
15649 {
15650 if (is_add)
477330fc 15651 do_vfp_nsyn_opcode ("faddd");
037e8744 15652 else
477330fc 15653 do_vfp_nsyn_opcode ("fsubd");
037e8744
JB		 15654 }
15655}
15656
15657/* Check operand types to see if this is a VFP instruction, and if so call
15658 PFN (). */
15659
15660static int
15661try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
15662{
15663 enum neon_shape rs;
15664 struct neon_type_el et;
15665
15666 switch (args)
15667 {
15668 case 2:
9db2f6b4
RL		 15669 rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
15670 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
037e8744 15671 break;
5f4273c7 15672
037e8744 15673 case 3:
9db2f6b4
RL		 15674 rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
15675 et = neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
15676 N_F_ALL | N_KEY | N_VFP);
037e8744
JB		 15677 break;
15678
15679 default:
15680 abort ();
15681 }
15682
15683 if (et.type != NT_invtype)
15684 {
15685 pfn (rs);
15686 return SUCCESS;
15687 }
037e8744 15688
99b253c5 15689 inst.error = NULL;
037e8744
JB		 15690 return FAIL;
15691}
15692
15693static void
15694do_vfp_nsyn_mla_mls (enum neon_shape rs)
15695{
15696 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
5f4273c7 15697
9db2f6b4 15698 if (rs == NS_FFF || rs == NS_HHH)
037e8744
JB		 15699 {
15700 if (is_mla)
477330fc 15701 do_vfp_nsyn_opcode ("fmacs");
037e8744 15702 else
477330fc 15703 do_vfp_nsyn_opcode ("fnmacs");
9db2f6b4
RL		 15704
15705 /* ARMv8.2 fp16 instruction. */
15706 if (rs == NS_HHH)
15707 do_scalar_fp16_v82_encode ();
037e8744
JB		 15708 }
15709 else
15710 {
15711 if (is_mla)
477330fc 15712 do_vfp_nsyn_opcode ("fmacd");
037e8744 15713 else
477330fc 15714 do_vfp_nsyn_opcode ("fnmacd");
037e8744
JB		 15715 }
15716}
15717
62f3b8c8
PB		 15718static void
15719do_vfp_nsyn_fma_fms (enum neon_shape rs)
15720{
15721 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
15722
9db2f6b4 15723 if (rs == NS_FFF || rs == NS_HHH)
62f3b8c8
PB		 15724 {
15725 if (is_fma)
477330fc 15726 do_vfp_nsyn_opcode ("ffmas");
62f3b8c8 15727 else
477330fc 15728 do_vfp_nsyn_opcode ("ffnmas");
9db2f6b4
RL		 15729
15730 /* ARMv8.2 fp16 instruction. */
15731 if (rs == NS_HHH)
15732 do_scalar_fp16_v82_encode ();
62f3b8c8
PB		 15733 }
15734 else
15735 {
15736 if (is_fma)
477330fc 15737 do_vfp_nsyn_opcode ("ffmad");
62f3b8c8 15738 else
477330fc 15739 do_vfp_nsyn_opcode ("ffnmad");
62f3b8c8
PB		 15740 }
15741}
15742
037e8744
JB		 15743static void
15744do_vfp_nsyn_mul (enum neon_shape rs)
15745{
9db2f6b4
RL		 15746 if (rs == NS_FFF || rs == NS_HHH)
15747 {
15748 do_vfp_nsyn_opcode ("fmuls");
15749
15750 /* ARMv8.2 fp16 instruction. */
15751 if (rs == NS_HHH)
15752 do_scalar_fp16_v82_encode ();
15753 }
037e8744
JB		 15754 else
15755 do_vfp_nsyn_opcode ("fmuld");
15756}
15757
15758static void
15759do_vfp_nsyn_abs_neg (enum neon_shape rs)
15760{
15761 int is_neg = (inst.instruction & 0x80) != 0;
9db2f6b4 15762 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_VFP | N_KEY);
037e8744 15763
9db2f6b4 15764 if (rs == NS_FF || rs == NS_HH)
037e8744
JB		 15765 {
15766 if (is_neg)
477330fc 15767 do_vfp_nsyn_opcode ("fnegs");
037e8744 15768 else
477330fc 15769 do_vfp_nsyn_opcode ("fabss");
9db2f6b4
RL		 15770
15771 /* ARMv8.2 fp16 instruction. */
15772 if (rs == NS_HH)
15773 do_scalar_fp16_v82_encode ();
037e8744
JB		 15774 }
15775 else
15776 {
15777 if (is_neg)
477330fc 15778 do_vfp_nsyn_opcode ("fnegd");
037e8744 15779 else
477330fc 15780 do_vfp_nsyn_opcode ("fabsd");
037e8744
JB		 15781 }
15782}
15783
15784/* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15785 insns belong to Neon, and are handled elsewhere. */
15786
15787static void
15788do_vfp_nsyn_ldm_stm (int is_dbmode)
15789{
15790 int is_ldm = (inst.instruction & (1 << 20)) != 0;
15791 if (is_ldm)
15792 {
15793 if (is_dbmode)
477330fc 15794 do_vfp_nsyn_opcode ("fldmdbs");
037e8744 15795 else
477330fc 15796 do_vfp_nsyn_opcode ("fldmias");
037e8744
JB		 15797 }
15798 else
15799 {
15800 if (is_dbmode)
477330fc 15801 do_vfp_nsyn_opcode ("fstmdbs");
037e8744 15802 else
477330fc 15803 do_vfp_nsyn_opcode ("fstmias");
037e8744
JB		 15804 }
15805}
15806
037e8744
JB		 15807static void
15808do_vfp_nsyn_sqrt (void)
15809{
9db2f6b4
RL		 15810 enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
15811 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
5f4273c7 15812
9db2f6b4
RL		 15813 if (rs == NS_FF || rs == NS_HH)
15814 {
15815 do_vfp_nsyn_opcode ("fsqrts");
15816
15817 /* ARMv8.2 fp16 instruction. */
15818 if (rs == NS_HH)
15819 do_scalar_fp16_v82_encode ();
15820 }
037e8744
JB		 15821 else
15822 do_vfp_nsyn_opcode ("fsqrtd");
15823}
15824
15825static void
15826do_vfp_nsyn_div (void)
15827{
9db2f6b4 15828 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
037e8744 15829 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
9db2f6b4 15830 N_F_ALL | N_KEY | N_VFP);
5f4273c7 15831
9db2f6b4
RL		 15832 if (rs == NS_FFF || rs == NS_HHH)
15833 {
15834 do_vfp_nsyn_opcode ("fdivs");
15835
15836 /* ARMv8.2 fp16 instruction. */
15837 if (rs == NS_HHH)
15838 do_scalar_fp16_v82_encode ();
15839 }
037e8744
JB		 15840 else
15841 do_vfp_nsyn_opcode ("fdivd");
15842}
15843
15844static void
15845do_vfp_nsyn_nmul (void)
15846{
9db2f6b4 15847 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
037e8744 15848 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
9db2f6b4 15849 N_F_ALL | N_KEY | N_VFP);
5f4273c7 15850
9db2f6b4 15851 if (rs == NS_FFF || rs == NS_HHH)
037e8744 15852 {
88714cb8 15853 NEON_ENCODE (SINGLE, inst);
037e8744 15854 do_vfp_sp_dyadic ();
9db2f6b4
RL		 15855
15856 /* ARMv8.2 fp16 instruction. */
15857 if (rs == NS_HHH)
15858 do_scalar_fp16_v82_encode ();
037e8744
JB		 15859 }
15860 else
15861 {
88714cb8 15862 NEON_ENCODE (DOUBLE, inst);
037e8744
JB		 15863 do_vfp_dp_rd_rn_rm ();
15864 }
15865 do_vfp_cond_or_thumb ();
9db2f6b4 15866
037e8744
JB		 15867}
15868
1b883319
AV		 15869/* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15870 (0, 1, 2, 3). */
15871
15872static unsigned
15873neon_logbits (unsigned x)
15874{
15875 return ffs (x) - 4;
15876}
15877
15878#define LOW4(R) ((R) & 0xf)
15879#define HI1(R) (((R) >> 4) & 1)
5aae9ae9
MM		 15880#define LOW1(R) ((R) & 0x1)
15881#define HI4(R) (((R) >> 1) & 0xf)
1b883319
AV		 15882
15883static unsigned
15884mve_get_vcmp_vpt_cond (struct neon_type_el et)
15885{
15886 switch (et.type)
15887 {
15888 default:
15889 first_error (BAD_EL_TYPE);
15890 return 0;
15891 case NT_float:
15892 switch (inst.operands[0].imm)
15893 {
15894 default:
15895 first_error (_("invalid condition"));
15896 return 0;
15897 case 0x0:
15898 /* eq. */
15899 return 0;
15900 case 0x1:
15901 /* ne. */
15902 return 1;
15903 case 0xa:
15904 /* ge/ */
15905 return 4;
15906 case 0xb:
15907 /* lt. */
15908 return 5;
15909 case 0xc:
15910 /* gt. */
15911 return 6;
15912 case 0xd:
15913 /* le. */
15914 return 7;
15915 }
15916 case NT_integer:
15917 /* only accept eq and ne. */
15918 if (inst.operands[0].imm > 1)
15919 {
15920 first_error (_("invalid condition"));
15921 return 0;
15922 }
15923 return inst.operands[0].imm;
15924 case NT_unsigned:
15925 if (inst.operands[0].imm == 0x2)
15926 return 2;
15927 else if (inst.operands[0].imm == 0x8)
15928 return 3;
15929 else
15930 {
15931 first_error (_("invalid condition"));
15932 return 0;
15933 }
15934 case NT_signed:
15935 switch (inst.operands[0].imm)
15936 {
15937 default:
15938 first_error (_("invalid condition"));
15939 return 0;
15940 case 0xa:
15941 /* ge. */
15942 return 4;
15943 case 0xb:
15944 /* lt. */
15945 return 5;
15946 case 0xc:
15947 /* gt. */
15948 return 6;
15949 case 0xd:
15950 /* le. */
15951 return 7;
15952 }
15953 }
15954 /* Should be unreachable. */
15955 abort ();
15956}
15957
efd0b310
SP		 15958/* For VCTP (create vector tail predicate) in MVE. */
15959static void
15960do_mve_vctp (void)
15961{
15962 int dt = 0;
15963 unsigned size = 0x0;
15964
15965 if (inst.cond > COND_ALWAYS)
15966 inst.pred_insn_type = INSIDE_VPT_INSN;
15967 else
15968 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15969
15970 /* This is a typical MVE instruction which has no type but have size 8, 16,
15971 32 and 64. For instructions with no type, inst.vectype.el[j].type is set
15972 to NT_untyped and size is updated in inst.vectype.el[j].size. */
15973 if ((inst.operands[0].present) && (inst.vectype.el[0].type == NT_untyped))
15974 dt = inst.vectype.el[0].size;
15975
15976 /* Setting this does not indicate an actual NEON instruction, but only
15977 indicates that the mnemonic accepts neon-style type suffixes. */
15978 inst.is_neon = 1;
15979
15980 switch (dt)
15981 {
15982 case 8:
15983 break;
15984 case 16:
15985 size = 0x1; break;
15986 case 32:
15987 size = 0x2; break;
15988 case 64:
15989 size = 0x3; break;
15990 default:
15991 first_error (_("Type is not allowed for this instruction"));
15992 }
15993 inst.instruction |= size << 20;
15994 inst.instruction |= inst.operands[0].reg << 16;
15995}
15996
1b883319
AV		 15997static void
15998do_mve_vpt (void)
15999{
16000 /* We are dealing with a vector predicated block. */
16001 if (inst.operands[0].present)
16002 {
16003 enum neon_shape rs = neon_select_shape (NS_IQQ, NS_IQR, NS_NULL);
16004 struct neon_type_el et
16005 = neon_check_type (3, rs, N_EQK, N_KEY | N_F_MVE | N_I_MVE | N_SU_32,
16006 N_EQK);
16007
16008 unsigned fcond = mve_get_vcmp_vpt_cond (et);
16009
16010 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
16011
16012 if (et.type == NT_invtype)
16013 return;
16014
16015 if (et.type == NT_float)
16016 {
16017 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext),
16018 BAD_FPU);
16019 constraint (et.size != 16 && et.size != 32, BAD_EL_TYPE);
16020 inst.instruction |= (et.size == 16) << 28;
16021 inst.instruction |= 0x3 << 20;
16022 }
16023 else
16024 {
16025 constraint (et.size != 8 && et.size != 16 && et.size != 32,
16026 BAD_EL_TYPE);
16027 inst.instruction |= 1 << 28;
16028 inst.instruction |= neon_logbits (et.size) << 20;
16029 }
16030
16031 if (inst.operands[2].isquad)
16032 {
16033 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16034 inst.instruction |= LOW4 (inst.operands[2].reg);
16035 inst.instruction |= (fcond & 0x2) >> 1;
16036 }
16037 else
16038 {
16039 if (inst.operands[2].reg == REG_SP)
16040 as_tsktsk (MVE_BAD_SP);
16041 inst.instruction |= 1 << 6;
16042 inst.instruction |= (fcond & 0x2) << 4;
16043 inst.instruction |= inst.operands[2].reg;
16044 }
16045 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16046 inst.instruction |= (fcond & 0x4) << 10;
16047 inst.instruction |= (fcond & 0x1) << 7;
16048
16049 }
16050 set_pred_insn_type (VPT_INSN);
16051 now_pred.cc = 0;
16052 now_pred.mask = ((inst.instruction & 0x00400000) >> 19)
16053 | ((inst.instruction & 0xe000) >> 13);
16054 now_pred.warn_deprecated = FALSE;
16055 now_pred.type = VECTOR_PRED;
16056 inst.is_neon = 1;
16057}
16058
16059static void
16060do_mve_vcmp (void)
16061{
16062 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
16063 if (!inst.operands[1].isreg || !inst.operands[1].isquad)
16064 first_error (_(reg_expected_msgs[REG_TYPE_MQ]));
16065 if (!inst.operands[2].present)
16066 first_error (_("MVE vector or ARM register expected"));
16067 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
16068
16069 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
16070 if ((inst.instruction & 0xffffffff) == N_MNEM_vcmpe
16071 && inst.operands[1].isquad)
16072 {
16073 inst.instruction = N_MNEM_vcmp;
16074 inst.cond = 0x10;
16075 }
16076
16077 if (inst.cond > COND_ALWAYS)
16078 inst.pred_insn_type = INSIDE_VPT_INSN;
16079 else
16080 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16081
16082 enum neon_shape rs = neon_select_shape (NS_IQQ, NS_IQR, NS_NULL);
16083 struct neon_type_el et
16084 = neon_check_type (3, rs, N_EQK, N_KEY | N_F_MVE | N_I_MVE | N_SU_32,
16085 N_EQK);
16086
16087 constraint (rs == NS_IQR && inst.operands[2].reg == REG_PC
16088 && !inst.operands[2].iszr, BAD_PC);
16089
16090 unsigned fcond = mve_get_vcmp_vpt_cond (et);
16091
16092 inst.instruction = 0xee010f00;
16093 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16094 inst.instruction |= (fcond & 0x4) << 10;
16095 inst.instruction |= (fcond & 0x1) << 7;
16096 if (et.type == NT_float)
16097 {
16098 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext),
16099 BAD_FPU);
16100 inst.instruction |= (et.size == 16) << 28;
16101 inst.instruction |= 0x3 << 20;
16102 }
16103 else
16104 {
16105 inst.instruction |= 1 << 28;
16106 inst.instruction |= neon_logbits (et.size) << 20;
16107 }
16108 if (inst.operands[2].isquad)
16109 {
16110 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16111 inst.instruction |= (fcond & 0x2) >> 1;
16112 inst.instruction |= LOW4 (inst.operands[2].reg);
16113 }
16114 else
16115 {
16116 if (inst.operands[2].reg == REG_SP)
16117 as_tsktsk (MVE_BAD_SP);
16118 inst.instruction |= 1 << 6;
16119 inst.instruction |= (fcond & 0x2) << 4;
16120 inst.instruction |= inst.operands[2].reg;
16121 }
16122
16123 inst.is_neon = 1;
16124 return;
16125}
16126
935295b5
AV		 16127static void
16128do_mve_vmaxa_vmina (void)
16129{
16130 if (inst.cond > COND_ALWAYS)
16131 inst.pred_insn_type = INSIDE_VPT_INSN;
16132 else
16133 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16134
16135 enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL);
16136 struct neon_type_el et
16137 = neon_check_type (2, rs, N_EQK, N_KEY | N_S8 | N_S16 | N_S32);
16138
16139 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16140 inst.instruction |= neon_logbits (et.size) << 18;
16141 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16142 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16143 inst.instruction |= LOW4 (inst.operands[1].reg);
16144 inst.is_neon = 1;
16145}
16146
f30ee27c
AV		 16147static void
16148do_mve_vfmas (void)
16149{
16150 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
16151 struct neon_type_el et
16152 = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK, N_EQK);
16153
16154 if (inst.cond > COND_ALWAYS)
16155 inst.pred_insn_type = INSIDE_VPT_INSN;
16156 else
16157 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16158
16159 if (inst.operands[2].reg == REG_SP)
16160 as_tsktsk (MVE_BAD_SP);
16161 else if (inst.operands[2].reg == REG_PC)
16162 as_tsktsk (MVE_BAD_PC);
16163
16164 inst.instruction |= (et.size == 16) << 28;
16165 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16166 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16167 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16168 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16169 inst.instruction |= inst.operands[2].reg;
16170 inst.is_neon = 1;
16171}
16172
b409bdb6
AV		 16173static void
16174do_mve_viddup (void)
16175{
16176 if (inst.cond > COND_ALWAYS)
16177 inst.pred_insn_type = INSIDE_VPT_INSN;
16178 else
16179 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16180
16181 unsigned imm = inst.relocs[0].exp.X_add_number;
16182 constraint (imm != 1 && imm != 2 && imm != 4 && imm != 8,
16183 _("immediate must be either 1, 2, 4 or 8"));
16184
16185 enum neon_shape rs;
16186 struct neon_type_el et;
16187 unsigned Rm;
16188 if (inst.instruction == M_MNEM_vddup || inst.instruction == M_MNEM_vidup)
16189 {
16190 rs = neon_select_shape (NS_QRI, NS_NULL);
16191 et = neon_check_type (2, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK);
16192 Rm = 7;
16193 }
16194 else
16195 {
16196 constraint ((inst.operands[2].reg % 2) != 1, BAD_EVEN);
16197 if (inst.operands[2].reg == REG_SP)
16198 as_tsktsk (MVE_BAD_SP);
16199 else if (inst.operands[2].reg == REG_PC)
16200 first_error (BAD_PC);
16201
16202 rs = neon_select_shape (NS_QRRI, NS_NULL);
16203 et = neon_check_type (3, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK, N_EQK);
16204 Rm = inst.operands[2].reg >> 1;
16205 }
16206 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16207 inst.instruction |= neon_logbits (et.size) << 20;
16208 inst.instruction |= inst.operands[1].reg << 16;
16209 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16210 inst.instruction |= (imm > 2) << 7;
16211 inst.instruction |= Rm << 1;
16212 inst.instruction |= (imm == 2 || imm == 8);
16213 inst.is_neon = 1;
16214}
16215
2d78f95b
AV		 16216static void
16217do_mve_vmlas (void)
16218{
16219 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
16220 struct neon_type_el et
16221 = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
16222
16223 if (inst.operands[2].reg == REG_PC)
16224 as_tsktsk (MVE_BAD_PC);
16225 else if (inst.operands[2].reg == REG_SP)
16226 as_tsktsk (MVE_BAD_SP);
16227
16228 if (inst.cond > COND_ALWAYS)
16229 inst.pred_insn_type = INSIDE_VPT_INSN;
16230 else
16231 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16232
16233 inst.instruction |= (et.type == NT_unsigned) << 28;
16234 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16235 inst.instruction |= neon_logbits (et.size) << 20;
16236 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16237 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16238 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16239 inst.instruction |= inst.operands[2].reg;
16240 inst.is_neon = 1;
16241}
16242
acca5630
AV		 16243static void
16244do_mve_vshll (void)
16245{
16246 struct neon_type_el et
16247 = neon_check_type (2, NS_QQI, N_EQK, N_S8 | N_U8 | N_S16 | N_U16 | N_KEY);
16248
16249 if (inst.cond > COND_ALWAYS)
16250 inst.pred_insn_type = INSIDE_VPT_INSN;
16251 else
16252 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16253
16254 int imm = inst.operands[2].imm;
16255 constraint (imm < 1 || (unsigned)imm > et.size,
16256 _("immediate value out of range"));
16257
16258 if ((unsigned)imm == et.size)
16259 {
16260 inst.instruction |= neon_logbits (et.size) << 18;
16261 inst.instruction |= 0x110001;
16262 }
16263 else
16264 {
16265 inst.instruction |= (et.size + imm) << 16;
16266 inst.instruction |= 0x800140;
16267 }
16268
16269 inst.instruction |= (et.type == NT_unsigned) << 28;
16270 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16271 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16272 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16273 inst.instruction |= LOW4 (inst.operands[1].reg);
16274 inst.is_neon = 1;
16275}
16276
16277static void
16278do_mve_vshlc (void)
16279{
16280 if (inst.cond > COND_ALWAYS)
16281 inst.pred_insn_type = INSIDE_VPT_INSN;
16282 else
16283 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16284
16285 if (inst.operands[1].reg == REG_PC)
16286 as_tsktsk (MVE_BAD_PC);
16287 else if (inst.operands[1].reg == REG_SP)
16288 as_tsktsk (MVE_BAD_SP);
16289
16290 int imm = inst.operands[2].imm;
16291 constraint (imm < 1 || imm > 32, _("immediate value out of range"));
16292
16293 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16294 inst.instruction |= (imm & 0x1f) << 16;
16295 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16296 inst.instruction |= inst.operands[1].reg;
16297 inst.is_neon = 1;
16298}
16299
4aa88b50
AV		 16300static void
16301do_mve_vshrn (void)
16302{
16303 unsigned types;
16304 switch (inst.instruction)
16305 {
16306 case M_MNEM_vshrnt:
16307 case M_MNEM_vshrnb:
16308 case M_MNEM_vrshrnt:
16309 case M_MNEM_vrshrnb:
16310 types = N_I16 | N_I32;
16311 break;
16312 case M_MNEM_vqshrnt:
16313 case M_MNEM_vqshrnb:
16314 case M_MNEM_vqrshrnt:
16315 case M_MNEM_vqrshrnb:
16316 types = N_U16 | N_U32 | N_S16 | N_S32;
16317 break;
16318 case M_MNEM_vqshrunt:
16319 case M_MNEM_vqshrunb:
16320 case M_MNEM_vqrshrunt:
16321 case M_MNEM_vqrshrunb:
16322 types = N_S16 | N_S32;
16323 break;
16324 default:
16325 abort ();
16326 }
16327
16328 struct neon_type_el et = neon_check_type (2, NS_QQI, N_EQK, types | N_KEY);
16329
16330 if (inst.cond > COND_ALWAYS)
16331 inst.pred_insn_type = INSIDE_VPT_INSN;
16332 else
16333 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16334
16335 unsigned Qd = inst.operands[0].reg;
16336 unsigned Qm = inst.operands[1].reg;
16337 unsigned imm = inst.operands[2].imm;
16338 constraint (imm < 1 || ((unsigned) imm) > (et.size / 2),
16339 et.size == 16
16340 ? _("immediate operand expected in the range [1,8]")
16341 : _("immediate operand expected in the range [1,16]"));
16342
16343 inst.instruction |= (et.type == NT_unsigned) << 28;
16344 inst.instruction |= HI1 (Qd) << 22;
16345 inst.instruction |= (et.size - imm) << 16;
16346 inst.instruction |= LOW4 (Qd) << 12;
16347 inst.instruction |= HI1 (Qm) << 5;
16348 inst.instruction |= LOW4 (Qm);
16349 inst.is_neon = 1;
16350}
16351
1be7aba3
AV		 16352static void
16353do_mve_vqmovn (void)
16354{
16355 struct neon_type_el et;
16356 if (inst.instruction == M_MNEM_vqmovnt
16357 || inst.instruction == M_MNEM_vqmovnb)
16358 et = neon_check_type (2, NS_QQ, N_EQK,
16359 N_U16 | N_U32 | N_S16 | N_S32 | N_KEY);
16360 else
16361 et = neon_check_type (2, NS_QQ, N_EQK, N_S16 | N_S32 | N_KEY);
16362
16363 if (inst.cond > COND_ALWAYS)
16364 inst.pred_insn_type = INSIDE_VPT_INSN;
16365 else
16366 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16367
16368 inst.instruction |= (et.type == NT_unsigned) << 28;
16369 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16370 inst.instruction |= (et.size == 32) << 18;
16371 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16372 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16373 inst.instruction |= LOW4 (inst.operands[1].reg);
16374 inst.is_neon = 1;
16375}
16376
3063888e
AV		 16377static void
16378do_mve_vpsel (void)
16379{
16380 neon_select_shape (NS_QQQ, NS_NULL);
16381
16382 if (inst.cond > COND_ALWAYS)
16383 inst.pred_insn_type = INSIDE_VPT_INSN;
16384 else
16385 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16386
16387 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16388 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16389 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16390 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16391 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16392 inst.instruction |= LOW4 (inst.operands[2].reg);
16393 inst.is_neon = 1;
16394}
16395
16396static void
16397do_mve_vpnot (void)
16398{
16399 if (inst.cond > COND_ALWAYS)
16400 inst.pred_insn_type = INSIDE_VPT_INSN;
16401 else
16402 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16403}
16404
935295b5
AV		 16405static void
16406do_mve_vmaxnma_vminnma (void)
16407{
16408 enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL);
16409 struct neon_type_el et
16410 = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY);
16411
16412 if (inst.cond > COND_ALWAYS)
16413 inst.pred_insn_type = INSIDE_VPT_INSN;
16414 else
16415 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16416
16417 inst.instruction |= (et.size == 16) << 28;
16418 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16419 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16420 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16421 inst.instruction |= LOW4 (inst.operands[1].reg);
16422 inst.is_neon = 1;
16423}
16424
5d281bf0
AV		 16425static void
16426do_mve_vcmul (void)
16427{
16428 enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL);
16429 struct neon_type_el et
16430 = neon_check_type (3, rs, N_EQK, N_EQK, N_F_MVE | N_KEY);
16431
16432 if (inst.cond > COND_ALWAYS)
16433 inst.pred_insn_type = INSIDE_VPT_INSN;
16434 else
16435 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16436
16437 unsigned rot = inst.relocs[0].exp.X_add_number;
16438 constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,
16439 _("immediate out of range"));
16440
16441 if (et.size == 32 && (inst.operands[0].reg == inst.operands[1].reg
16442 || inst.operands[0].reg == inst.operands[2].reg))
16443 as_tsktsk (BAD_MVE_SRCDEST);
16444
16445 inst.instruction |= (et.size == 32) << 28;
16446 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16447 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16448 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16449 inst.instruction |= (rot > 90) << 12;
16450 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16451 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16452 inst.instruction |= LOW4 (inst.operands[2].reg);
16453 inst.instruction |= (rot == 90 || rot == 270);
16454 inst.is_neon = 1;
16455}
16456
1f6234a3
AV		 16457/* To handle the Low Overhead Loop instructions
16458 in Armv8.1-M Mainline and MVE. */
16459static void
16460do_t_loloop (void)
16461{
16462 unsigned long insn = inst.instruction;
16463
16464 inst.instruction = THUMB_OP32 (inst.instruction);
16465
16466 if (insn == T_MNEM_lctp)
16467 return;
16468
16469 set_pred_insn_type (MVE_OUTSIDE_PRED_INSN);
16470
16471 if (insn == T_MNEM_wlstp || insn == T_MNEM_dlstp)
16472 {
16473 struct neon_type_el et
16474 = neon_check_type (2, NS_RR, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
16475 inst.instruction |= neon_logbits (et.size) << 20;
16476 inst.is_neon = 1;
16477 }
16478
16479 switch (insn)
16480 {
16481 case T_MNEM_letp:
16482 constraint (!inst.operands[0].present,
16483 _("expected LR"));
16484 /* fall through. */
16485 case T_MNEM_le:
16486 /* le <label>. */
16487 if (!inst.operands[0].present)
16488 inst.instruction |= 1 << 21;
16489
16490 v8_1_loop_reloc (TRUE);
16491 break;
16492
16493 case T_MNEM_wls:
16494 case T_MNEM_wlstp:
16495 v8_1_loop_reloc (FALSE);
16496 /* fall through. */
16497 case T_MNEM_dlstp:
16498 case T_MNEM_dls:
16499 constraint (inst.operands[1].isreg != 1, BAD_ARGS);
16500
16501 if (insn == T_MNEM_wlstp || insn == T_MNEM_dlstp)
16502 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
16503 else if (inst.operands[1].reg == REG_PC)
16504 as_tsktsk (MVE_BAD_PC);
16505 if (inst.operands[1].reg == REG_SP)
16506 as_tsktsk (MVE_BAD_SP);
16507
16508 inst.instruction |= (inst.operands[1].reg << 16);
16509 break;
16510
16511 default:
16512 abort ();
16513 }
16514}
16515
16516
037e8744
JB		 16517static void
16518do_vfp_nsyn_cmp (void)
16519{
9db2f6b4 16520 enum neon_shape rs;
1b883319
AV		 16521 if (!inst.operands[0].isreg)
16522 {
16523 do_mve_vcmp ();
16524 return;
16525 }
16526 else
16527 {
16528 constraint (inst.operands[2].present, BAD_SYNTAX);
16529 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd),
16530 BAD_FPU);
16531 }
16532
037e8744
JB		 16533 if (inst.operands[1].isreg)
16534 {
9db2f6b4
RL		 16535 rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
16536 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
5f4273c7 16537
9db2f6b4 16538 if (rs == NS_FF || rs == NS_HH)
477330fc
RM		 16539 {
16540 NEON_ENCODE (SINGLE, inst);
16541 do_vfp_sp_monadic ();
16542 }
037e8744 16543 else
477330fc
RM		 16544 {
16545 NEON_ENCODE (DOUBLE, inst);
16546 do_vfp_dp_rd_rm ();
16547 }
037e8744
JB		 16548 }
16549 else
16550 {
9db2f6b4
RL		 16551 rs = neon_select_shape (NS_HI, NS_FI, NS_DI, NS_NULL);
16552 neon_check_type (2, rs, N_F_ALL | N_KEY | N_VFP, N_EQK);
037e8744
JB		 16553
16554 switch (inst.instruction & 0x0fffffff)
477330fc
RM		 16555 {
16556 case N_MNEM_vcmp:
16557 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
16558 break;
16559 case N_MNEM_vcmpe:
16560 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
16561 break;
16562 default:
16563 abort ();
16564 }
5f4273c7 16565
9db2f6b4 16566 if (rs == NS_FI || rs == NS_HI)
477330fc
RM		 16567 {
16568 NEON_ENCODE (SINGLE, inst);
16569 do_vfp_sp_compare_z ();
16570 }
037e8744 16571 else
477330fc
RM		 16572 {
16573 NEON_ENCODE (DOUBLE, inst);
16574 do_vfp_dp_rd ();
16575 }
037e8744
JB		 16576 }
16577 do_vfp_cond_or_thumb ();
9db2f6b4
RL		 16578
16579 /* ARMv8.2 fp16 instruction. */
16580 if (rs == NS_HI || rs == NS_HH)
16581 do_scalar_fp16_v82_encode ();
037e8744
JB		 16582}
16583
16584static void
16585nsyn_insert_sp (void)
16586{
16587 inst.operands[1] = inst.operands[0];
16588 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
fdfde340 16589 inst.operands[0].reg = REG_SP;
037e8744
JB		 16590 inst.operands[0].isreg = 1;
16591 inst.operands[0].writeback = 1;
16592 inst.operands[0].present = 1;
16593}
16594
037e8744
JB		 16595/* Fix up Neon data-processing instructions, ORing in the correct bits for
16596 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16597
88714cb8
DG		 16598static void
16599neon_dp_fixup (struct arm_it* insn)
037e8744 16600{
88714cb8
DG		 16601 unsigned int i = insn->instruction;
16602 insn->is_neon = 1;
16603
037e8744
JB		 16604 if (thumb_mode)
16605 {
16606 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16607 if (i & (1 << 24))
477330fc 16608 i |= 1 << 28;
5f4273c7 16609
037e8744 16610 i &= ~(1 << 24);
5f4273c7 16611
037e8744
JB		 16612 i |= 0xef000000;
16613 }
16614 else
16615 i |= 0xf2000000;
5f4273c7 16616
88714cb8 16617 insn->instruction = i;
037e8744
JB		 16618}
16619
5ee91343 16620static void
7df54120 16621mve_encode_qqr (int size, int U, int fp)
5ee91343
AV		 16622{
16623 if (inst.operands[2].reg == REG_SP)
16624 as_tsktsk (MVE_BAD_SP);
16625 else if (inst.operands[2].reg == REG_PC)
16626 as_tsktsk (MVE_BAD_PC);
16627
16628 if (fp)
16629 {
16630 /* vadd. */
16631 if (((unsigned)inst.instruction) == 0xd00)
16632 inst.instruction = 0xee300f40;
16633 /* vsub. */
16634 else if (((unsigned)inst.instruction) == 0x200d00)
16635 inst.instruction = 0xee301f40;
a8465a06
AV		 16636 /* vmul. */
16637 else if (((unsigned)inst.instruction) == 0x1000d10)
16638 inst.instruction = 0xee310e60;
5ee91343
AV		 16639
16640 /* Setting size which is 1 for F16 and 0 for F32. */
16641 inst.instruction |= (size == 16) << 28;
16642 }
16643 else
16644 {
16645 /* vadd. */
16646 if (((unsigned)inst.instruction) == 0x800)
16647 inst.instruction = 0xee010f40;
16648 /* vsub. */
16649 else if (((unsigned)inst.instruction) == 0x1000800)
16650 inst.instruction = 0xee011f40;
7df54120
AV		 16651 /* vhadd. */
16652 else if (((unsigned)inst.instruction) == 0)
16653 inst.instruction = 0xee000f40;
16654 /* vhsub. */
16655 else if (((unsigned)inst.instruction) == 0x200)
16656 inst.instruction = 0xee001f40;
a8465a06
AV		 16657 /* vmla. */
16658 else if (((unsigned)inst.instruction) == 0x900)
16659 inst.instruction = 0xee010e40;
16660 /* vmul. */
16661 else if (((unsigned)inst.instruction) == 0x910)
16662 inst.instruction = 0xee011e60;
16663 /* vqadd. */
16664 else if (((unsigned)inst.instruction) == 0x10)
16665 inst.instruction = 0xee000f60;
16666 /* vqsub. */
16667 else if (((unsigned)inst.instruction) == 0x210)
16668 inst.instruction = 0xee001f60;
42b16635
AV		 16669 /* vqrdmlah. */
16670 else if (((unsigned)inst.instruction) == 0x3000b10)
16671 inst.instruction = 0xee000e40;
16672 /* vqdmulh. */
16673 else if (((unsigned)inst.instruction) == 0x0000b00)
16674 inst.instruction = 0xee010e60;
16675 /* vqrdmulh. */
16676 else if (((unsigned)inst.instruction) == 0x1000b00)
16677 inst.instruction = 0xfe010e60;
7df54120
AV		 16678
16679 /* Set U-bit. */
16680 inst.instruction |= U << 28;
16681
5ee91343
AV		 16682 /* Setting bits for size. */
16683 inst.instruction |= neon_logbits (size) << 20;
16684 }
16685 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16686 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16687 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16688 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16689 inst.instruction |= inst.operands[2].reg;
16690 inst.is_neon = 1;
16691}
16692
a302e574
AV		 16693static void
16694mve_encode_rqq (unsigned bit28, unsigned size)
16695{
16696 inst.instruction |= bit28 << 28;
16697 inst.instruction |= neon_logbits (size) << 20;
16698 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16699 inst.instruction |= inst.operands[0].reg << 12;
16700 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16701 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16702 inst.instruction |= LOW4 (inst.operands[2].reg);
16703 inst.is_neon = 1;
16704}
16705
886e1c73
AV		 16706static void
16707mve_encode_qqq (int ubit, int size)
16708{
16709
16710 inst.instruction |= (ubit != 0) << 28;
16711 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16712 inst.instruction |= neon_logbits (size) << 20;
16713 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16714 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16715 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16716 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16717 inst.instruction |= LOW4 (inst.operands[2].reg);
16718
16719 inst.is_neon = 1;
16720}
16721
26c1e780
AV		 16722static void
16723mve_encode_rq (unsigned bit28, unsigned size)
16724{
16725 inst.instruction |= bit28 << 28;
16726 inst.instruction |= neon_logbits (size) << 18;
16727 inst.instruction |= inst.operands[0].reg << 12;
16728 inst.instruction |= LOW4 (inst.operands[1].reg);
16729 inst.is_neon = 1;
16730}
886e1c73 16731
93925576
AV		 16732static void
16733mve_encode_rrqq (unsigned U, unsigned size)
16734{
16735 constraint (inst.operands[3].reg > 14, MVE_BAD_QREG);
16736
16737 inst.instruction |= U << 28;
16738 inst.instruction |= (inst.operands[1].reg >> 1) << 20;
16739 inst.instruction |= LOW4 (inst.operands[2].reg) << 16;
16740 inst.instruction |= (size == 32) << 16;
16741 inst.instruction |= inst.operands[0].reg << 12;
16742 inst.instruction |= HI1 (inst.operands[2].reg) << 7;
16743 inst.instruction |= inst.operands[3].reg;
16744 inst.is_neon = 1;
16745}
16746
aab2c27d
MM		 16747/* Helper function for neon_three_same handling the operands. */
16748static void
16749neon_three_args (int isquad)
16750{
16751 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16752 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16753 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16754 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16755 inst.instruction |= LOW4 (inst.operands[2].reg);
16756 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16757 inst.instruction |= (isquad != 0) << 6;
16758 inst.is_neon = 1;
16759}
16760
037e8744
JB		 16761/* Encode insns with bit pattern:
16762
16763 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16764 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
5f4273c7 16765
037e8744
JB		 16766 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16767 different meaning for some instruction. */
16768
16769static void
16770neon_three_same (int isquad, int ubit, int size)
16771{
aab2c27d 16772 neon_three_args (isquad);
037e8744
JB		 16773 inst.instruction |= (ubit != 0) << 24;
16774 if (size != -1)
16775 inst.instruction |= neon_logbits (size) << 20;
5f4273c7 16776
88714cb8 16777 neon_dp_fixup (&inst);
037e8744
JB		 16778}
16779
16780/* Encode instructions of the form:
16781
16782 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16783 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
5287ad62
JB		 16784
16785 Don't write size if SIZE == -1. */
16786
16787static void
16788neon_two_same (int qbit, int ubit, int size)
16789{
16790 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16791 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16792 inst.instruction |= LOW4 (inst.operands[1].reg);
16793 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16794 inst.instruction |= (qbit != 0) << 6;
16795 inst.instruction |= (ubit != 0) << 24;
16796
16797 if (size != -1)
16798 inst.instruction |= neon_logbits (size) << 18;
16799
88714cb8 16800 neon_dp_fixup (&inst);
5287ad62
JB		 16801}
16802
7df54120
AV		 16803enum vfp_or_neon_is_neon_bits
16804{
16805NEON_CHECK_CC = 1,
16806NEON_CHECK_ARCH = 2,
16807NEON_CHECK_ARCH8 = 4
16808};
16809
16810/* Call this function if an instruction which may have belonged to the VFP or
16811 Neon instruction sets, but turned out to be a Neon instruction (due to the
16812 operand types involved, etc.). We have to check and/or fix-up a couple of
16813 things:
16814
16815 - Make sure the user hasn't attempted to make a Neon instruction
16816 conditional.
16817 - Alter the value in the condition code field if necessary.
16818 - Make sure that the arch supports Neon instructions.
16819
16820 Which of these operations take place depends on bits from enum
16821 vfp_or_neon_is_neon_bits.
16822
16823 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16824 current instruction's condition is COND_ALWAYS, the condition field is
16825 changed to inst.uncond_value. This is necessary because instructions shared
16826 between VFP and Neon may be conditional for the VFP variants only, and the
16827 unconditional Neon version must have, e.g., 0xF in the condition field. */
16828
16829static int
16830vfp_or_neon_is_neon (unsigned check)
16831{
16832/* Conditions are always legal in Thumb mode (IT blocks). */
16833if (!thumb_mode && (check & NEON_CHECK_CC))
16834 {
16835 if (inst.cond != COND_ALWAYS)
16836 {
16837 first_error (_(BAD_COND));
16838 return FAIL;
16839 }
16840 if (inst.uncond_value != -1)
16841 inst.instruction |= inst.uncond_value << 28;
16842 }
16843
16844
16845 if (((check & NEON_CHECK_ARCH) && !mark_feature_used (&fpu_neon_ext_v1))
16846 || ((check & NEON_CHECK_ARCH8)
16847 && !mark_feature_used (&fpu_neon_ext_armv8)))
16848 {
16849 first_error (_(BAD_FPU));
16850 return FAIL;
16851 }
16852
16853return SUCCESS;
16854}
16855
64c350f2
AV		 16856
16857/* Return TRUE if the SIMD instruction is available for the current
16858 cpu_variant. FP is set to TRUE if this is a SIMD floating-point
16859 instruction. CHECK contains th. CHECK contains the set of bits to pass to
16860 vfp_or_neon_is_neon for the NEON specific checks. */
16861
16862static bfd_boolean
7df54120
AV		 16863check_simd_pred_availability (int fp, unsigned check)
16864{
16865if (inst.cond > COND_ALWAYS)
16866 {
16867 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16868 {
16869 inst.error = BAD_FPU;
64c350f2 16870 return FALSE;
7df54120
AV		 16871 }
16872 inst.pred_insn_type = INSIDE_VPT_INSN;
16873 }
16874else if (inst.cond < COND_ALWAYS)
16875 {
16876 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16877 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16878 else if (vfp_or_neon_is_neon (check) == FAIL)
64c350f2 16879 return FALSE;
7df54120
AV		 16880 }
16881else
16882 {
16883 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fp ? mve_fp_ext : mve_ext)
16884 && vfp_or_neon_is_neon (check) == FAIL)
64c350f2 16885 return FALSE;
7df54120
AV		 16886
16887 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16888 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16889 }
64c350f2 16890return TRUE;
7df54120
AV		 16891}
16892
5287ad62
JB		 16893/* Neon instruction encoders, in approximate order of appearance. */
16894
16895static void
16896do_neon_dyadic_i_su (void)
16897{
64c350f2 16898 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
7df54120
AV		 16899 return;
16900
16901 enum neon_shape rs;
16902 struct neon_type_el et;
16903 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16904 rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
16905 else
16906 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16907
16908 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_32 | N_KEY);
16909
16910
16911 if (rs != NS_QQR)
16912 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16913 else
16914 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
5287ad62
JB		 16915}
16916
16917static void
16918do_neon_dyadic_i64_su (void)
16919{
64c350f2 16920 if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
a8465a06
AV		 16921 return;
16922 enum neon_shape rs;
16923 struct neon_type_el et;
16924 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16925 {
16926 rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
16927 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
16928 }
16929 else
16930 {
16931 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16932 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_ALL | N_KEY);
16933 }
16934 if (rs == NS_QQR)
16935 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
16936 else
16937 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
5287ad62
JB		 16938}
16939
16940static void
16941neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
477330fc 16942 unsigned immbits)
5287ad62
JB		 16943{
16944 unsigned size = et.size >> 3;
16945 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16946 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16947 inst.instruction |= LOW4 (inst.operands[1].reg);
16948 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16949 inst.instruction |= (isquad != 0) << 6;
16950 inst.instruction |= immbits << 16;
16951 inst.instruction |= (size >> 3) << 7;
16952 inst.instruction |= (size & 0x7) << 19;
16953 if (write_ubit)
16954 inst.instruction |= (uval != 0) << 24;
16955
88714cb8 16956 neon_dp_fixup (&inst);
5287ad62
JB		 16957}
16958
16959static void
5150f0d8 16960do_neon_shl (void)
5287ad62 16961{
64c350f2 16962 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
5150f0d8
AV		 16963 return;
16964
5287ad62
JB		 16965 if (!inst.operands[2].isreg)
16966 {
5150f0d8
AV		 16967 enum neon_shape rs;
16968 struct neon_type_el et;
16969 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16970 {
16971 rs = neon_select_shape (NS_QQI, NS_NULL);
16972 et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_MVE);
16973 }
16974 else
16975 {
16976 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
16977 et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
16978 }
cb3b1e65
JB		 16979 int imm = inst.operands[2].imm;
16980
16981 constraint (imm < 0 || (unsigned)imm >= et.size,
16982 _("immediate out of range for shift"));
88714cb8 16983 NEON_ENCODE (IMMED, inst);
cb3b1e65 16984 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
5287ad62
JB		 16985 }
16986 else
16987 {
5150f0d8
AV		 16988 enum neon_shape rs;
16989 struct neon_type_el et;
16990 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16991 {
16992 rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
16993 et = neon_check_type (3, rs, N_EQK, N_SU_MVE | N_KEY, N_EQK | N_EQK);
16994 }
16995 else
16996 {
16997 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16998 et = neon_check_type (3, rs, N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
16999 }
17000
17001
17002 if (rs == NS_QQR)
17003 {
17004 constraint (inst.operands[0].reg != inst.operands[1].reg,
17005 _("invalid instruction shape"));
17006 if (inst.operands[2].reg == REG_SP)
17007 as_tsktsk (MVE_BAD_SP);
17008 else if (inst.operands[2].reg == REG_PC)
17009 as_tsktsk (MVE_BAD_PC);
17010
17011 inst.instruction = 0xee311e60;
17012 inst.instruction |= (et.type == NT_unsigned) << 28;
17013 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17014 inst.instruction |= neon_logbits (et.size) << 18;
17015 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17016 inst.instruction |= inst.operands[2].reg;
17017 inst.is_neon = 1;
17018 }
17019 else
17020 {
17021 unsigned int tmp;
17022
17023 /* VSHL/VQSHL 3-register variants have syntax such as:
17024 vshl.xx Dd, Dm, Dn
17025 whereas other 3-register operations encoded by neon_three_same have
17026 syntax like:
17027 vadd.xx Dd, Dn, Dm
17028 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
17029 operands[2].reg here. */
17030 tmp = inst.operands[2].reg;
17031 inst.operands[2].reg = inst.operands[1].reg;
17032 inst.operands[1].reg = tmp;
17033 NEON_ENCODE (INTEGER, inst);
17034 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
17035 }
5287ad62
JB		 17036 }
17037}
17038
17039static void
5150f0d8 17040do_neon_qshl (void)
5287ad62 17041{
64c350f2 17042 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
5150f0d8
AV		 17043 return;
17044
5287ad62
JB		 17045 if (!inst.operands[2].isreg)
17046 {
5150f0d8
AV		 17047 enum neon_shape rs;
17048 struct neon_type_el et;
17049 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17050 {
17051 rs = neon_select_shape (NS_QQI, NS_NULL);
17052 et = neon_check_type (2, rs, N_EQK, N_KEY | N_SU_MVE);
17053 }
17054 else
17055 {
17056 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
17057 et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
17058 }
cb3b1e65 17059 int imm = inst.operands[2].imm;
627907b7 17060
cb3b1e65
JB		 17061 constraint (imm < 0 || (unsigned)imm >= et.size,
17062 _("immediate out of range for shift"));
88714cb8 17063 NEON_ENCODE (IMMED, inst);
cb3b1e65 17064 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, imm);
5287ad62
JB		 17065 }
17066 else
17067 {
5150f0d8
AV		 17068 enum neon_shape rs;
17069 struct neon_type_el et;
627907b7 17070
5150f0d8
AV		 17071 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17072 {
17073 rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
17074 et = neon_check_type (3, rs, N_EQK, N_SU_MVE | N_KEY, N_EQK | N_EQK);
17075 }
17076 else
17077 {
17078 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17079 et = neon_check_type (3, rs, N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
17080 }
17081
17082 if (rs == NS_QQR)
17083 {
17084 constraint (inst.operands[0].reg != inst.operands[1].reg,
17085 _("invalid instruction shape"));
17086 if (inst.operands[2].reg == REG_SP)
17087 as_tsktsk (MVE_BAD_SP);
17088 else if (inst.operands[2].reg == REG_PC)
17089 as_tsktsk (MVE_BAD_PC);
17090
17091 inst.instruction = 0xee311ee0;
17092 inst.instruction |= (et.type == NT_unsigned) << 28;
17093 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17094 inst.instruction |= neon_logbits (et.size) << 18;
17095 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17096 inst.instruction |= inst.operands[2].reg;
17097 inst.is_neon = 1;
17098 }
17099 else
17100 {
17101 unsigned int tmp;
17102
17103 /* See note in do_neon_shl. */
17104 tmp = inst.operands[2].reg;
17105 inst.operands[2].reg = inst.operands[1].reg;
17106 inst.operands[1].reg = tmp;
17107 NEON_ENCODE (INTEGER, inst);
17108 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
17109 }
5287ad62
JB		 17110 }
17111}
17112
627907b7
JB		 17113static void
17114do_neon_rshl (void)
17115{
64c350f2 17116 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
1be7aba3
AV		 17117 return;
17118
17119 enum neon_shape rs;
17120 struct neon_type_el et;
17121 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17122 {
17123 rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
17124 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
17125 }
17126 else
17127 {
17128 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17129 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_ALL | N_KEY);
17130 }
17131
627907b7
JB		 17132 unsigned int tmp;
17133
1be7aba3
AV		 17134 if (rs == NS_QQR)
17135 {
17136 if (inst.operands[2].reg == REG_PC)
17137 as_tsktsk (MVE_BAD_PC);
17138 else if (inst.operands[2].reg == REG_SP)
17139 as_tsktsk (MVE_BAD_SP);
17140
17141 constraint (inst.operands[0].reg != inst.operands[1].reg,
17142 _("invalid instruction shape"));
17143
17144 if (inst.instruction == 0x0000510)
17145 /* We are dealing with vqrshl. */
17146 inst.instruction = 0xee331ee0;
17147 else
17148 /* We are dealing with vrshl. */
17149 inst.instruction = 0xee331e60;
17150
17151 inst.instruction |= (et.type == NT_unsigned) << 28;
17152 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17153 inst.instruction |= neon_logbits (et.size) << 18;
17154 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17155 inst.instruction |= inst.operands[2].reg;
17156 inst.is_neon = 1;
17157 }
17158 else
17159 {
17160 tmp = inst.operands[2].reg;
17161 inst.operands[2].reg = inst.operands[1].reg;
17162 inst.operands[1].reg = tmp;
17163 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
17164 }
627907b7
JB		 17165}
17166
5287ad62
JB		 17167static int
17168neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
17169{
036dc3f7
PB		 17170 /* Handle .I8 pseudo-instructions. */
17171 if (size == 8)
5287ad62 17172 {
5287ad62 17173 /* Unfortunately, this will make everything apart from zero out-of-range.
477330fc
RM		 17174 FIXME is this the intended semantics? There doesn't seem much point in
17175 accepting .I8 if so. */
5287ad62
JB		 17176 immediate |= immediate << 8;
17177 size = 16;
036dc3f7
PB		 17178 }
17179
17180 if (size >= 32)
17181 {
17182 if (immediate == (immediate & 0x000000ff))
17183 {
17184 *immbits = immediate;
17185 return 0x1;
17186 }
17187 else if (immediate == (immediate & 0x0000ff00))
17188 {
17189 *immbits = immediate >> 8;
17190 return 0x3;
17191 }
17192 else if (immediate == (immediate & 0x00ff0000))
17193 {
17194 *immbits = immediate >> 16;
17195 return 0x5;
17196 }
17197 else if (immediate == (immediate & 0xff000000))
17198 {
17199 *immbits = immediate >> 24;
17200 return 0x7;
17201 }
17202 if ((immediate & 0xffff) != (immediate >> 16))
17203 goto bad_immediate;
17204 immediate &= 0xffff;
5287ad62
JB		 17205 }
17206
17207 if (immediate == (immediate & 0x000000ff))
17208 {
17209 *immbits = immediate;
036dc3f7 17210 return 0x9;
5287ad62
JB		 17211 }
17212 else if (immediate == (immediate & 0x0000ff00))
17213 {
17214 *immbits = immediate >> 8;
036dc3f7 17215 return 0xb;
5287ad62
JB		 17216 }
17217
17218 bad_immediate:
dcbf9037 17219 first_error (_("immediate value out of range"));
5287ad62
JB		 17220 return FAIL;
17221}
17222
5287ad62
JB		 17223static void
17224do_neon_logic (void)
17225{
17226 if (inst.operands[2].present && inst.operands[2].isreg)
17227 {
037e8744 17228 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
f601a00c 17229 if (rs == NS_QQQ
64c350f2
AV		 17230 && !check_simd_pred_availability (FALSE,
17231 NEON_CHECK_ARCH | NEON_CHECK_CC))
f601a00c
AV		 17232 return;
17233 else if (rs != NS_QQQ
17234 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
17235 first_error (BAD_FPU);
17236
5287ad62
JB		 17237 neon_check_type (3, rs, N_IGNORE_TYPE);
17238 /* U bit and size field were set as part of the bitmask. */
88714cb8 17239 NEON_ENCODE (INTEGER, inst);
037e8744 17240 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB		 17241 }
17242 else
17243 {
4316f0d2
DG		 17244 const int three_ops_form = (inst.operands[2].present
17245 && !inst.operands[2].isreg);
17246 const int immoperand = (three_ops_form ? 2 : 1);
17247 enum neon_shape rs = (three_ops_form
17248 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
17249 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
f601a00c
AV		 17250 /* Because neon_select_shape makes the second operand a copy of the first
17251 if the second operand is not present. */
17252 if (rs == NS_QQI
64c350f2
AV		 17253 && !check_simd_pred_availability (FALSE,
17254 NEON_CHECK_ARCH | NEON_CHECK_CC))
f601a00c
AV		 17255 return;
17256 else if (rs != NS_QQI
17257 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
17258 first_error (BAD_FPU);
17259
17260 struct neon_type_el et;
17261 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17262 et = neon_check_type (2, rs, N_I32 | N_I16 | N_KEY, N_EQK);
17263 else
17264 et = neon_check_type (2, rs, N_I8 | N_I16 | N_I32 | N_I64 | N_F32
17265 | N_KEY, N_EQK);
17266
17267 if (et.type == NT_invtype)
17268 return;
21d799b5 17269 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
5287ad62
JB		 17270 unsigned immbits;
17271 int cmode;
5f4273c7 17272
5f4273c7 17273
4316f0d2
DG		 17274 if (three_ops_form)
17275 constraint (inst.operands[0].reg != inst.operands[1].reg,
17276 _("first and second operands shall be the same register"));
17277
88714cb8 17278 NEON_ENCODE (IMMED, inst);
5287ad62 17279
4316f0d2 17280 immbits = inst.operands[immoperand].imm;
036dc3f7
PB		 17281 if (et.size == 64)
17282 {
17283 /* .i64 is a pseudo-op, so the immediate must be a repeating
17284 pattern. */
4316f0d2
DG		 17285 if (immbits != (inst.operands[immoperand].regisimm ?
17286 inst.operands[immoperand].reg : 0))
036dc3f7
PB		 17287 {
17288 /* Set immbits to an invalid constant. */
17289 immbits = 0xdeadbeef;
17290 }
17291 }
17292
5287ad62 17293 switch (opcode)
477330fc
RM		 17294 {
17295 case N_MNEM_vbic:
17296 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
17297 break;
17298
17299 case N_MNEM_vorr:
17300 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
17301 break;
17302
17303 case N_MNEM_vand:
17304 /* Pseudo-instruction for VBIC. */
17305 neon_invert_size (&immbits, 0, et.size);
17306 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
17307 break;
17308
17309 case N_MNEM_vorn:
17310 /* Pseudo-instruction for VORR. */
17311 neon_invert_size (&immbits, 0, et.size);
17312 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
17313 break;
17314
17315 default:
17316 abort ();
17317 }
5287ad62
JB		 17318
17319 if (cmode == FAIL)
477330fc 17320 return;
5287ad62 17321
037e8744 17322 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 17323 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17324 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17325 inst.instruction |= cmode << 8;
17326 neon_write_immbits (immbits);
5f4273c7 17327
88714cb8 17328 neon_dp_fixup (&inst);
5287ad62
JB		 17329 }
17330}
17331
17332static void
17333do_neon_bitfield (void)
17334{
037e8744 17335 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
dcbf9037 17336 neon_check_type (3, rs, N_IGNORE_TYPE);
037e8744 17337 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB		 17338}
17339
17340static void
dcbf9037 17341neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
477330fc 17342 unsigned destbits)
5287ad62 17343{
5ee91343 17344 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
dcbf9037 17345 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
477330fc 17346 types | N_KEY);
5287ad62
JB		 17347 if (et.type == NT_float)
17348 {
88714cb8 17349 NEON_ENCODE (FLOAT, inst);
5ee91343 17350 if (rs == NS_QQR)
7df54120 17351 mve_encode_qqr (et.size, 0, 1);
5ee91343
AV		 17352 else
17353 neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
5287ad62
JB		 17354 }
17355 else
17356 {
88714cb8 17357 NEON_ENCODE (INTEGER, inst);
5ee91343 17358 if (rs == NS_QQR)
a8465a06 17359 mve_encode_qqr (et.size, et.type == ubit_meaning, 0);
5ee91343
AV		 17360 else
17361 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
5287ad62
JB		 17362 }
17363}
17364
5287ad62
JB		 17365
17366static void
17367do_neon_dyadic_if_su_d (void)
17368{
17369 /* This version only allow D registers, but that constraint is enforced during
17370 operand parsing so we don't need to do anything extra here. */
dcbf9037 17371 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
5287ad62
JB		 17372}
17373
5287ad62
JB		 17374static void
17375do_neon_dyadic_if_i_d (void)
17376{
428e3f1f
PB		 17377 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17378 affected if we specify unsigned args. */
17379 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
5287ad62
JB		 17380}
17381
f5f10c66
AV		 17382static void
17383do_mve_vstr_vldr_QI (int size, int elsize, int load)
17384{
17385 constraint (size < 32, BAD_ADDR_MODE);
17386 constraint (size != elsize, BAD_EL_TYPE);
17387 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
17388 constraint (!inst.operands[1].preind, BAD_ADDR_MODE);
17389 constraint (load && inst.operands[0].reg == inst.operands[1].reg,
17390 _("destination register and offset register may not be the"
17391 " same"));
17392
17393 int imm = inst.relocs[0].exp.X_add_number;
17394 int add = 1;
17395 if (imm < 0)
17396 {
17397 add = 0;
17398 imm = -imm;
17399 }
17400 constraint ((imm % (size / 8) != 0)
17401 || imm > (0x7f << neon_logbits (size)),
17402 (size == 32) ? _("immediate must be a multiple of 4 in the"
17403 " range of +/-[0,508]")
17404 : _("immediate must be a multiple of 8 in the"
17405 " range of +/-[0,1016]"));
17406 inst.instruction |= 0x11 << 24;
17407 inst.instruction |= add << 23;
17408 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17409 inst.instruction |= inst.operands[1].writeback << 21;
17410 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17411 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17412 inst.instruction |= 1 << 12;
17413 inst.instruction |= (size == 64) << 8;
17414 inst.instruction &= 0xffffff00;
17415 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
17416 inst.instruction |= imm >> neon_logbits (size);
17417}
17418
17419static void
17420do_mve_vstr_vldr_RQ (int size, int elsize, int load)
17421{
17422 unsigned os = inst.operands[1].imm >> 5;
e449ea97 17423 unsigned type = inst.vectype.el[0].type;
f5f10c66
AV		 17424 constraint (os != 0 && size == 8,
17425 _("can not shift offsets when accessing less than half-word"));
17426 constraint (os && os != neon_logbits (size),
17427 _("shift immediate must be 1, 2 or 3 for half-word, word"
17428 " or double-word accesses respectively"));
17429 if (inst.operands[1].reg == REG_PC)
17430 as_tsktsk (MVE_BAD_PC);
17431
17432 switch (size)
17433 {
17434 case 8:
17435 constraint (elsize >= 64, BAD_EL_TYPE);
17436 break;
17437 case 16:
17438 constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE);
17439 break;
17440 case 32:
17441 case 64:
17442 constraint (elsize != size, BAD_EL_TYPE);
17443 break;
17444 default:
17445 break;
17446 }
17447 constraint (inst.operands[1].writeback || !inst.operands[1].preind,
17448 BAD_ADDR_MODE);
17449 if (load)
17450 {
17451 constraint (inst.operands[0].reg == (inst.operands[1].imm & 0x1f),
17452 _("destination register and offset register may not be"
17453 " the same"));
e449ea97
SP		 17454 constraint (size == elsize && type == NT_signed, BAD_EL_TYPE);
17455 constraint (size != elsize && type != NT_unsigned && type != NT_signed,
f5f10c66 17456 BAD_EL_TYPE);
e449ea97 17457 inst.instruction |= ((size == elsize) || (type == NT_unsigned)) << 28;
f5f10c66
AV		 17458 }
17459 else
17460 {
e449ea97 17461 constraint (type != NT_untyped, BAD_EL_TYPE);
f5f10c66
AV		 17462 }
17463
17464 inst.instruction |= 1 << 23;
17465 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17466 inst.instruction |= inst.operands[1].reg << 16;
17467 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17468 inst.instruction |= neon_logbits (elsize) << 7;
17469 inst.instruction |= HI1 (inst.operands[1].imm) << 5;
17470 inst.instruction |= LOW4 (inst.operands[1].imm);
17471 inst.instruction |= !!os;
17472}
17473
17474static void
17475do_mve_vstr_vldr_RI (int size, int elsize, int load)
17476{
17477 enum neon_el_type type = inst.vectype.el[0].type;
17478
17479 constraint (size >= 64, BAD_ADDR_MODE);
17480 switch (size)
17481 {
17482 case 16:
17483 constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE);
17484 break;
17485 case 32:
17486 constraint (elsize != size, BAD_EL_TYPE);
17487 break;
17488 default:
17489 break;
17490 }
17491 if (load)
17492 {
17493 constraint (elsize != size && type != NT_unsigned
17494 && type != NT_signed, BAD_EL_TYPE);
17495 }
17496 else
17497 {
17498 constraint (elsize != size && type != NT_untyped, BAD_EL_TYPE);
17499 }
17500
17501 int imm = inst.relocs[0].exp.X_add_number;
17502 int add = 1;
17503 if (imm < 0)
17504 {
17505 add = 0;
17506 imm = -imm;
17507 }
17508
17509 if ((imm % (size / 8) != 0) || imm > (0x7f << neon_logbits (size)))
17510 {
17511 switch (size)
17512 {
17513 case 8:
17514 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17515 break;
17516 case 16:
17517 constraint (1, _("immediate must be a multiple of 2 in the"
17518 " range of +/-[0,254]"));
17519 break;
17520 case 32:
17521 constraint (1, _("immediate must be a multiple of 4 in the"
17522 " range of +/-[0,508]"));
17523 break;
17524 }
17525 }
17526
17527 if (size != elsize)
17528 {
17529 constraint (inst.operands[1].reg > 7, BAD_HIREG);
17530 constraint (inst.operands[0].reg > 14,
17531 _("MVE vector register in the range [Q0..Q7] expected"));
17532 inst.instruction |= (load && type == NT_unsigned) << 28;
17533 inst.instruction |= (size == 16) << 19;
17534 inst.instruction |= neon_logbits (elsize) << 7;
17535 }
17536 else
17537 {
17538 if (inst.operands[1].reg == REG_PC)
17539 as_tsktsk (MVE_BAD_PC);
17540 else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback)
17541 as_tsktsk (MVE_BAD_SP);
17542 inst.instruction |= 1 << 12;
17543 inst.instruction |= neon_logbits (size) << 7;
17544 }
17545 inst.instruction |= inst.operands[1].preind << 24;
17546 inst.instruction |= add << 23;
17547 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17548 inst.instruction |= inst.operands[1].writeback << 21;
17549 inst.instruction |= inst.operands[1].reg << 16;
17550 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17551 inst.instruction &= 0xffffff80;
17552 inst.instruction |= imm >> neon_logbits (size);
17553
17554}
17555
17556static void
17557do_mve_vstr_vldr (void)
17558{
17559 unsigned size;
17560 int load = 0;
17561
17562 if (inst.cond > COND_ALWAYS)
17563 inst.pred_insn_type = INSIDE_VPT_INSN;
17564 else
17565 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17566
17567 switch (inst.instruction)
17568 {
17569 default:
17570 gas_assert (0);
17571 break;
17572 case M_MNEM_vldrb:
17573 load = 1;
17574 /* fall through. */
17575 case M_MNEM_vstrb:
17576 size = 8;
17577 break;
17578 case M_MNEM_vldrh:
17579 load = 1;
17580 /* fall through. */
17581 case M_MNEM_vstrh:
17582 size = 16;
17583 break;
17584 case M_MNEM_vldrw:
17585 load = 1;
17586 /* fall through. */
17587 case M_MNEM_vstrw:
17588 size = 32;
17589 break;
17590 case M_MNEM_vldrd:
17591 load = 1;
17592 /* fall through. */
17593 case M_MNEM_vstrd:
17594 size = 64;
17595 break;
17596 }
17597 unsigned elsize = inst.vectype.el[0].size;
17598
17599 if (inst.operands[1].isquad)
17600 {
17601 /* We are dealing with [Q, imm]{!} cases. */
17602 do_mve_vstr_vldr_QI (size, elsize, load);
17603 }
17604 else
17605 {
17606 if (inst.operands[1].immisreg == 2)
17607 {
17608 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17609 do_mve_vstr_vldr_RQ (size, elsize, load);
17610 }
17611 else if (!inst.operands[1].immisreg)
17612 {
17613 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17614 do_mve_vstr_vldr_RI (size, elsize, load);
17615 }
17616 else
17617 constraint (1, BAD_ADDR_MODE);
17618 }
17619
17620 inst.is_neon = 1;
17621}
17622
35c228db
AV		 17623static void
17624do_mve_vst_vld (void)
17625{
17626 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17627 return;
17628
17629 constraint (!inst.operands[1].preind || inst.relocs[0].exp.X_add_symbol != 0
17630 || inst.relocs[0].exp.X_add_number != 0
17631 || inst.operands[1].immisreg != 0,
17632 BAD_ADDR_MODE);
17633 constraint (inst.vectype.el[0].size > 32, BAD_EL_TYPE);
17634 if (inst.operands[1].reg == REG_PC)
17635 as_tsktsk (MVE_BAD_PC);
17636 else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback)
17637 as_tsktsk (MVE_BAD_SP);
17638
17639
17640 /* These instructions are one of the "exceptions" mentioned in
17641 handle_pred_state. They are MVE instructions that are not VPT compatible
17642 and do not accept a VPT code, thus appending such a code is a syntax
17643 error. */
17644 if (inst.cond > COND_ALWAYS)
17645 first_error (BAD_SYNTAX);
17646 /* If we append a scalar condition code we can set this to
17647 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17648 else if (inst.cond < COND_ALWAYS)
17649 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17650 else
17651 inst.pred_insn_type = MVE_UNPREDICABLE_INSN;
17652
17653 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17654 inst.instruction |= inst.operands[1].writeback << 21;
17655 inst.instruction |= inst.operands[1].reg << 16;
17656 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17657 inst.instruction |= neon_logbits (inst.vectype.el[0].size) << 7;
17658 inst.is_neon = 1;
17659}
17660
26c1e780
AV		 17661static void
17662do_mve_vaddlv (void)
17663{
17664 enum neon_shape rs = neon_select_shape (NS_RRQ, NS_NULL);
17665 struct neon_type_el et
17666 = neon_check_type (3, rs, N_EQK, N_EQK, N_S32 | N_U32 | N_KEY);
17667
17668 if (et.type == NT_invtype)
17669 first_error (BAD_EL_TYPE);
17670
17671 if (inst.cond > COND_ALWAYS)
17672 inst.pred_insn_type = INSIDE_VPT_INSN;
17673 else
17674 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17675
17676 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
17677
17678 inst.instruction |= (et.type == NT_unsigned) << 28;
17679 inst.instruction |= inst.operands[1].reg << 19;
17680 inst.instruction |= inst.operands[0].reg << 12;
17681 inst.instruction |= inst.operands[2].reg;
17682 inst.is_neon = 1;
17683}
17684
5287ad62 17685static void
5ee91343 17686do_neon_dyadic_if_su (void)
5287ad62 17687{
5ee91343
AV		 17688 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
17689 struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
17690 N_SUF_32 | N_KEY);
17691
935295b5
AV		 17692 constraint ((inst.instruction == ((unsigned) N_MNEM_vmax)
17693 || inst.instruction == ((unsigned) N_MNEM_vmin))
17694 && et.type == NT_float
17695 && !ARM_CPU_HAS_FEATURE (cpu_variant,fpu_neon_ext_v1), BAD_FPU);
17696
64c350f2
AV		 17697 if (!check_simd_pred_availability (et.type == NT_float,
17698 NEON_CHECK_ARCH | NEON_CHECK_CC))
037e8744
JB		 17699 return;
17700
5ee91343
AV		 17701 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
17702}
17703
17704static void
17705do_neon_addsub_if_i (void)
17706{
17707 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
17708 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
037e8744
JB		 17709 return;
17710
5ee91343
AV		 17711 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
17712 struct neon_type_el et = neon_check_type (3, rs, N_EQK,
17713 N_EQK, N_IF_32 | N_I64 | N_KEY);
17714
17715 constraint (rs == NS_QQR && et.size == 64, BAD_FPU);
17716 /* If we are parsing Q registers and the element types match MVE, which NEON
17717 also supports, then we must check whether this is an instruction that can
17718 be used by both MVE/NEON. This distinction can be made based on whether
17719 they are predicated or not. */
17720 if ((rs == NS_QQQ || rs == NS_QQR) && et.size != 64)
17721 {
64c350f2
AV		 17722 if (!check_simd_pred_availability (et.type == NT_float,
17723 NEON_CHECK_ARCH | NEON_CHECK_CC))
5ee91343
AV		 17724 return;
17725 }
17726 else
17727 {
17728 /* If they are either in a D register or are using an unsupported. */
17729 if (rs != NS_QQR
17730 && vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
17731 return;
17732 }
17733
5287ad62
JB		 17734 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17735 affected if we specify unsigned args. */
dcbf9037 17736 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
5287ad62
JB		 17737}
17738
17739/* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17740 result to be:
17741 V<op> A,B (A is operand 0, B is operand 2)
17742 to mean:
17743 V<op> A,B,A
17744 not:
17745 V<op> A,B,B
17746 so handle that case specially. */
17747
17748static void
17749neon_exchange_operands (void)
17750{
5287ad62
JB		 17751 if (inst.operands[1].present)
17752 {
e1fa0163
NC		 17753 void *scratch = xmalloc (sizeof (inst.operands[0]));
17754
5287ad62
JB		 17755 /* Swap operands[1] and operands[2]. */
17756 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
17757 inst.operands[1] = inst.operands[2];
17758 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
e1fa0163 17759 free (scratch);
5287ad62
JB		 17760 }
17761 else
17762 {
17763 inst.operands[1] = inst.operands[2];
17764 inst.operands[2] = inst.operands[0];
17765 }
17766}
17767
17768static void
17769neon_compare (unsigned regtypes, unsigned immtypes, int invert)
17770{
17771 if (inst.operands[2].isreg)
17772 {
17773 if (invert)
477330fc 17774 neon_exchange_operands ();
dcbf9037 17775 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
5287ad62
JB		 17776 }
17777 else
17778 {
037e8744 17779 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
dcbf9037 17780 struct neon_type_el et = neon_check_type (2, rs,
477330fc 17781 N_EQK | N_SIZ, immtypes | N_KEY);
5287ad62 17782
88714cb8 17783 NEON_ENCODE (IMMED, inst);
5287ad62
JB		 17784 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17785 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17786 inst.instruction |= LOW4 (inst.operands[1].reg);
17787 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 17788 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 17789 inst.instruction |= (et.type == NT_float) << 10;
17790 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 17791
88714cb8 17792 neon_dp_fixup (&inst);
5287ad62
JB		 17793 }
17794}
17795
17796static void
17797do_neon_cmp (void)
17798{
cc933301 17799 neon_compare (N_SUF_32, N_S_32 | N_F_16_32, FALSE);
5287ad62
JB		 17800}
17801
17802static void
17803do_neon_cmp_inv (void)
17804{
cc933301 17805 neon_compare (N_SUF_32, N_S_32 | N_F_16_32, TRUE);
5287ad62
JB		 17806}
17807
17808static void
17809do_neon_ceq (void)
17810{
17811 neon_compare (N_IF_32, N_IF_32, FALSE);
17812}
17813
17814/* For multiply instructions, we have the possibility of 16-bit or 32-bit
17815 scalars, which are encoded in 5 bits, M : Rm.
17816 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17817 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
c604a79a
JW		 17818 index in M.
17819
17820 Dot Product instructions are similar to multiply instructions except elsize
17821 should always be 32.
17822
17823 This function translates SCALAR, which is GAS's internal encoding of indexed
17824 scalar register, to raw encoding. There is also register and index range
17825 check based on ELSIZE. */
5287ad62
JB		 17826
17827static unsigned
17828neon_scalar_for_mul (unsigned scalar, unsigned elsize)
17829{
dcbf9037
JB		 17830 unsigned regno = NEON_SCALAR_REG (scalar);
17831 unsigned elno = NEON_SCALAR_INDEX (scalar);
5287ad62
JB		 17832
17833 switch (elsize)
17834 {
17835 case 16:
17836 if (regno > 7 || elno > 3)
477330fc 17837 goto bad_scalar;
5287ad62 17838 return regno | (elno << 3);
5f4273c7 17839
5287ad62
JB		 17840 case 32:
17841 if (regno > 15 || elno > 1)
477330fc 17842 goto bad_scalar;
5287ad62
JB		 17843 return regno | (elno << 4);
17844
17845 default:
17846 bad_scalar:
dcbf9037 17847 first_error (_("scalar out of range for multiply instruction"));
5287ad62
JB		 17848 }
17849
17850 return 0;
17851}
17852
17853/* Encode multiply / multiply-accumulate scalar instructions. */
17854
17855static void
17856neon_mul_mac (struct neon_type_el et, int ubit)
17857{
dcbf9037
JB		 17858 unsigned scalar;
17859
17860 /* Give a more helpful error message if we have an invalid type. */
17861 if (et.type == NT_invtype)
17862 return;
5f4273c7 17863
dcbf9037 17864 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
5287ad62
JB		 17865 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17866 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17867 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17868 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
17869 inst.instruction |= LOW4 (scalar);
17870 inst.instruction |= HI1 (scalar) << 5;
17871 inst.instruction |= (et.type == NT_float) << 8;
17872 inst.instruction |= neon_logbits (et.size) << 20;
17873 inst.instruction |= (ubit != 0) << 24;
17874
88714cb8 17875 neon_dp_fixup (&inst);
5287ad62
JB		 17876}
17877
17878static void
17879do_neon_mac_maybe_scalar (void)
17880{
037e8744
JB		 17881 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
17882 return;
17883
64c350f2 17884 if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
037e8744
JB		 17885 return;
17886
5287ad62
JB		 17887 if (inst.operands[2].isscalar)
17888 {
a8465a06 17889 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
037e8744 17890 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
5287ad62 17891 struct neon_type_el et = neon_check_type (3, rs,
589a7d88 17892 N_EQK, N_EQK, N_I16 | N_I32 | N_F_16_32 | N_KEY);
88714cb8 17893 NEON_ENCODE (SCALAR, inst);
037e8744 17894 neon_mul_mac (et, neon_quad (rs));
5287ad62 17895 }
a8465a06
AV		 17896 else if (!inst.operands[2].isvec)
17897 {
17898 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
17899
17900 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
17901 neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
17902
17903 neon_dyadic_misc (NT_unsigned, N_SU_MVE, 0);
17904 }
5287ad62 17905 else
428e3f1f 17906 {
a8465a06 17907 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
428e3f1f
PB		 17908 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17909 affected if we specify unsigned args. */
17910 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
17911 }
5287ad62
JB		 17912}
17913
aab2c27d
MM		 17914static void
17915do_bfloat_vfma (void)
17916{
17917 constraint (!mark_feature_used (&fpu_neon_ext_armv8), _(BAD_FPU));
17918 constraint (!mark_feature_used (&arm_ext_bf16), _(BAD_BF16));
17919 enum neon_shape rs;
17920 int t_bit = 0;
17921
17922 if (inst.instruction != B_MNEM_vfmab)
17923 {
17924 t_bit = 1;
17925 inst.instruction = B_MNEM_vfmat;
17926 }
17927
17928 if (inst.operands[2].isscalar)
17929 {
17930 rs = neon_select_shape (NS_QQS, NS_NULL);
17931 neon_check_type (3, rs, N_EQK, N_EQK, N_BF16 | N_KEY);
17932
17933 inst.instruction |= (1 << 25);
17934 int index = inst.operands[2].reg & 0xf;
17935 constraint (!(index < 4), _("index must be in the range 0 to 3"));
17936 inst.operands[2].reg >>= 4;
17937 constraint (!(inst.operands[2].reg < 8),
17938 _("indexed register must be less than 8"));
17939 neon_three_args (t_bit);
17940 inst.instruction |= ((index & 1) << 3);
17941 inst.instruction |= ((index & 2) << 4);
17942 }
17943 else
17944 {
17945 rs = neon_select_shape (NS_QQQ, NS_NULL);
17946 neon_check_type (3, rs, N_EQK, N_EQK, N_BF16 | N_KEY);
17947 neon_three_args (t_bit);
17948 }
17949
17950}
17951
62f3b8c8
PB		 17952static void
17953do_neon_fmac (void)
17954{
d58196e0
AV		 17955 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_fma)
17956 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
62f3b8c8
PB		 17957 return;
17958
64c350f2 17959 if (!check_simd_pred_availability (TRUE, NEON_CHECK_CC | NEON_CHECK_ARCH))
62f3b8c8
PB		 17960 return;
17961
d58196e0
AV		 17962 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
17963 {
17964 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
17965 struct neon_type_el et = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK,
17966 N_EQK);
17967
17968 if (rs == NS_QQR)
17969 {
aab2c27d 17970
d58196e0
AV		 17971 if (inst.operands[2].reg == REG_SP)
17972 as_tsktsk (MVE_BAD_SP);
17973 else if (inst.operands[2].reg == REG_PC)
17974 as_tsktsk (MVE_BAD_PC);
17975
17976 inst.instruction = 0xee310e40;
17977 inst.instruction |= (et.size == 16) << 28;
17978 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17979 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17980 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17981 inst.instruction |= HI1 (inst.operands[1].reg) << 6;
17982 inst.instruction |= inst.operands[2].reg;
17983 inst.is_neon = 1;
17984 return;
17985 }
17986 }
17987 else
17988 {
17989 constraint (!inst.operands[2].isvec, BAD_FPU);
17990 }
17991
62f3b8c8
PB		 17992 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
17993}
17994
aab2c27d
MM		 17995static void
17996do_mve_vfma (void)
17997{
17998 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_bf16) &&
17999 inst.cond == COND_ALWAYS)
18000 {
18001 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
18002 inst.instruction = N_MNEM_vfma;
18003 inst.pred_insn_type = INSIDE_VPT_INSN;
18004 inst.cond = 0xf;
18005 return do_neon_fmac();
18006 }
18007 else
18008 {
18009 do_bfloat_vfma();
18010 }
18011}
18012
5287ad62
JB		 18013static void
18014do_neon_tst (void)
18015{
037e8744 18016 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB		 18017 struct neon_type_el et = neon_check_type (3, rs,
18018 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
037e8744 18019 neon_three_same (neon_quad (rs), 0, et.size);
5287ad62
JB		 18020}
18021
18022/* VMUL with 3 registers allows the P8 type. The scalar version supports the
18023 same types as the MAC equivalents. The polynomial type for this instruction
18024 is encoded the same as the integer type. */
18025
18026static void
18027do_neon_mul (void)
18028{
037e8744
JB		 18029 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
18030 return;
18031
64c350f2 18032 if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
037e8744
JB		 18033 return;
18034
5287ad62 18035 if (inst.operands[2].isscalar)
a8465a06
AV		 18036 {
18037 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
18038 do_neon_mac_maybe_scalar ();
18039 }
5287ad62 18040 else
a8465a06
AV		 18041 {
18042 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18043 {
18044 enum neon_shape rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
18045 struct neon_type_el et
18046 = neon_check_type (3, rs, N_EQK, N_EQK, N_I_MVE | N_F_MVE | N_KEY);
18047 if (et.type == NT_float)
18048 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext),
18049 BAD_FPU);
18050
18051 neon_dyadic_misc (NT_float, N_I_MVE | N_F_MVE, 0);
18052 }
18053 else
18054 {
18055 constraint (!inst.operands[2].isvec, BAD_FPU);
18056 neon_dyadic_misc (NT_poly,
18057 N_I8 | N_I16 | N_I32 | N_F16 | N_F32 | N_P8, 0);
18058 }
18059 }
5287ad62
JB		 18060}
18061
18062static void
18063do_neon_qdmulh (void)
18064{
64c350f2 18065 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
42b16635
AV		 18066 return;
18067
5287ad62
JB		 18068 if (inst.operands[2].isscalar)
18069 {
42b16635 18070 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
037e8744 18071 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
5287ad62 18072 struct neon_type_el et = neon_check_type (3, rs,
477330fc 18073 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
88714cb8 18074 NEON_ENCODE (SCALAR, inst);
037e8744 18075 neon_mul_mac (et, neon_quad (rs));
5287ad62
JB		 18076 }
18077 else
18078 {
42b16635
AV		 18079 enum neon_shape rs;
18080 struct neon_type_el et;
18081 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18082 {
18083 rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
18084 et = neon_check_type (3, rs,
18085 N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
18086 }
18087 else
18088 {
18089 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
18090 et = neon_check_type (3, rs,
18091 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
18092 }
18093
88714cb8 18094 NEON_ENCODE (INTEGER, inst);
42b16635
AV		 18095 if (rs == NS_QQR)
18096 mve_encode_qqr (et.size, 0, 0);
18097 else
18098 /* The U bit (rounding) comes from bit mask. */
18099 neon_three_same (neon_quad (rs), 0, et.size);
5287ad62
JB		 18100 }
18101}
18102
26c1e780
AV		 18103static void
18104do_mve_vaddv (void)
18105{
18106 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
18107 struct neon_type_el et
18108 = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
18109
18110 if (et.type == NT_invtype)
18111 first_error (BAD_EL_TYPE);
18112
18113 if (inst.cond > COND_ALWAYS)
18114 inst.pred_insn_type = INSIDE_VPT_INSN;
18115 else
18116 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18117
18118 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
18119
18120 mve_encode_rq (et.type == NT_unsigned, et.size);
18121}
18122
7df54120
AV		 18123static void
18124do_mve_vhcadd (void)
18125{
18126 enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL);
18127 struct neon_type_el et
18128 = neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
18129
18130 if (inst.cond > COND_ALWAYS)
18131 inst.pred_insn_type = INSIDE_VPT_INSN;
18132 else
18133 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18134
18135 unsigned rot = inst.relocs[0].exp.X_add_number;
18136 constraint (rot != 90 && rot != 270, _("immediate out of range"));
18137
18138 if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg)
18139 as_tsktsk (_("Warning: 32-bit element size and same first and third "
18140 "operand makes instruction UNPREDICTABLE"));
18141
18142 mve_encode_qqq (0, et.size);
18143 inst.instruction |= (rot == 270) << 12;
18144 inst.is_neon = 1;
18145}
18146
35d1cfc2
AV		 18147static void
18148do_mve_vqdmull (void)
18149{
18150 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
18151 struct neon_type_el et
18152 = neon_check_type (3, rs, N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
18153
18154 if (et.size == 32
18155 && (inst.operands[0].reg == inst.operands[1].reg
18156 || (rs == NS_QQQ && inst.operands[0].reg == inst.operands[2].reg)))
18157 as_tsktsk (BAD_MVE_SRCDEST);
18158
18159 if (inst.cond > COND_ALWAYS)
18160 inst.pred_insn_type = INSIDE_VPT_INSN;
18161 else
18162 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18163
18164 if (rs == NS_QQQ)
18165 {
18166 mve_encode_qqq (et.size == 32, 64);
18167 inst.instruction |= 1;
18168 }
18169 else
18170 {
18171 mve_encode_qqr (64, et.size == 32, 0);
18172 inst.instruction |= 0x3 << 5;
18173 }
18174}
18175
c2dafc2a
AV		 18176static void
18177do_mve_vadc (void)
18178{
18179 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
18180 struct neon_type_el et
18181 = neon_check_type (3, rs, N_KEY | N_I32, N_EQK, N_EQK);
18182
18183 if (et.type == NT_invtype)
18184 first_error (BAD_EL_TYPE);
18185
18186 if (inst.cond > COND_ALWAYS)
18187 inst.pred_insn_type = INSIDE_VPT_INSN;
18188 else
18189 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18190
18191 mve_encode_qqq (0, 64);
18192}
18193
18194static void
18195do_mve_vbrsr (void)
18196{
18197 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
18198 struct neon_type_el et
18199 = neon_check_type (3, rs, N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
18200
18201 if (inst.cond > COND_ALWAYS)
18202 inst.pred_insn_type = INSIDE_VPT_INSN;
18203 else
18204 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18205
7df54120 18206 mve_encode_qqr (et.size, 0, 0);
c2dafc2a
AV		 18207}
18208
18209static void
18210do_mve_vsbc (void)
18211{
18212 neon_check_type (3, NS_QQQ, N_EQK, N_EQK, N_I32 | N_KEY);
18213
18214 if (inst.cond > COND_ALWAYS)
18215 inst.pred_insn_type = INSIDE_VPT_INSN;
18216 else
18217 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18218
18219 mve_encode_qqq (1, 64);
18220}
18221
2d78f95b
AV		 18222static void
18223do_mve_vmulh (void)
18224{
18225 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
18226 struct neon_type_el et
18227 = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
18228
18229 if (inst.cond > COND_ALWAYS)
18230 inst.pred_insn_type = INSIDE_VPT_INSN;
18231 else
18232 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18233
18234 mve_encode_qqq (et.type == NT_unsigned, et.size);
18235}
18236
42b16635
AV		 18237static void
18238do_mve_vqdmlah (void)
18239{
18240 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
18241 struct neon_type_el et
23d188c7 18242 = neon_check_type (3, rs, N_EQK, N_EQK, N_S_32 | N_KEY);
42b16635
AV		 18243
18244 if (inst.cond > COND_ALWAYS)
18245 inst.pred_insn_type = INSIDE_VPT_INSN;
18246 else
18247 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18248
18249 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
18250}
8b8b22a4
AV		 18251
18252static void
18253do_mve_vqdmladh (void)
18254{
18255 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
18256 struct neon_type_el et
18257 = neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
18258
18259 if (inst.cond > COND_ALWAYS)
18260 inst.pred_insn_type = INSIDE_VPT_INSN;
18261 else
18262 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18263
8b8b22a4
AV		 18264 mve_encode_qqq (0, et.size);
18265}
18266
18267
886e1c73
AV		 18268static void
18269do_mve_vmull (void)
18270{
18271
18272 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_DDS,
18273 NS_QQS, NS_QQQ, NS_QQR, NS_NULL);
fe05f369 18274 if (inst.cond == COND_ALWAYS
886e1c73
AV		 18275 && ((unsigned)inst.instruction) == M_MNEM_vmullt)
18276 {
fe05f369 18277
886e1c73
AV		 18278 if (rs == NS_QQQ)
18279 {
fe05f369 18280 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
886e1c73
AV		 18281 goto neon_vmul;
18282 }
18283 else
18284 goto neon_vmul;
18285 }
18286
18287 constraint (rs != NS_QQQ, BAD_FPU);
18288 struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
18289 N_SU_32 | N_P8 | N_P16 | N_KEY);
18290
18291 /* We are dealing with MVE's vmullt. */
18292 if (et.size == 32
18293 && (inst.operands[0].reg == inst.operands[1].reg
18294 || inst.operands[0].reg == inst.operands[2].reg))
18295 as_tsktsk (BAD_MVE_SRCDEST);
18296
18297 if (inst.cond > COND_ALWAYS)
18298 inst.pred_insn_type = INSIDE_VPT_INSN;
18299 else
18300 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18301
18302 if (et.type == NT_poly)
18303 mve_encode_qqq (neon_logbits (et.size), 64);
18304 else
18305 mve_encode_qqq (et.type == NT_unsigned, et.size);
18306
18307 return;
18308
dc1e8a47 18309 neon_vmul:
886e1c73
AV		 18310 inst.instruction = N_MNEM_vmul;
18311 inst.cond = 0xb;
18312 if (thumb_mode)
18313 inst.pred_insn_type = INSIDE_IT_INSN;
18314 do_neon_mul ();
18315}
18316
a302e574
AV		 18317static void
18318do_mve_vabav (void)
18319{
18320 enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL);
18321
18322 if (rs == NS_NULL)
18323 return;
18324
18325 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18326 return;
18327
18328 struct neon_type_el et = neon_check_type (2, NS_NULL, N_EQK, N_KEY | N_S8
18329 | N_S16 | N_S32 | N_U8 | N_U16
18330 | N_U32);
18331
18332 if (inst.cond > COND_ALWAYS)
18333 inst.pred_insn_type = INSIDE_VPT_INSN;
18334 else
18335 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18336
18337 mve_encode_rqq (et.type == NT_unsigned, et.size);
18338}
18339
18340static void
18341do_mve_vmladav (void)
18342{
18343 enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL);
18344 struct neon_type_el et = neon_check_type (3, rs,
18345 N_EQK, N_EQK, N_SU_MVE | N_KEY);
18346
18347 if (et.type == NT_unsigned
18348 && (inst.instruction == M_MNEM_vmladavx
18349 || inst.instruction == M_MNEM_vmladavax
18350 || inst.instruction == M_MNEM_vmlsdav
18351 || inst.instruction == M_MNEM_vmlsdava
18352 || inst.instruction == M_MNEM_vmlsdavx
18353 || inst.instruction == M_MNEM_vmlsdavax))
18354 first_error (BAD_SIMD_TYPE);
18355
18356 constraint (inst.operands[2].reg > 14,
18357 _("MVE vector register in the range [Q0..Q7] expected"));
18358
18359 if (inst.cond > COND_ALWAYS)
18360 inst.pred_insn_type = INSIDE_VPT_INSN;
18361 else
18362 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18363
18364 if (inst.instruction == M_MNEM_vmlsdav
18365 || inst.instruction == M_MNEM_vmlsdava
18366 || inst.instruction == M_MNEM_vmlsdavx
18367 || inst.instruction == M_MNEM_vmlsdavax)
18368 inst.instruction |= (et.size == 8) << 28;
18369 else
18370 inst.instruction |= (et.size == 8) << 8;
18371
18372 mve_encode_rqq (et.type == NT_unsigned, 64);
18373 inst.instruction |= (et.size == 32) << 16;
18374}
18375
93925576
AV		 18376static void
18377do_mve_vmlaldav (void)
18378{
18379 enum neon_shape rs = neon_select_shape (NS_RRQQ, NS_NULL);
18380 struct neon_type_el et
18381 = neon_check_type (4, rs, N_EQK, N_EQK, N_EQK,
18382 N_S16 | N_S32 | N_U16 | N_U32 | N_KEY);
18383
18384 if (et.type == NT_unsigned
18385 && (inst.instruction == M_MNEM_vmlsldav
18386 || inst.instruction == M_MNEM_vmlsldava
18387 || inst.instruction == M_MNEM_vmlsldavx
18388 || inst.instruction == M_MNEM_vmlsldavax))
18389 first_error (BAD_SIMD_TYPE);
18390
18391 if (inst.cond > COND_ALWAYS)
18392 inst.pred_insn_type = INSIDE_VPT_INSN;
18393 else
18394 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18395
18396 mve_encode_rrqq (et.type == NT_unsigned, et.size);
18397}
18398
18399static void
18400do_mve_vrmlaldavh (void)
18401{
18402 struct neon_type_el et;
18403 if (inst.instruction == M_MNEM_vrmlsldavh
18404 || inst.instruction == M_MNEM_vrmlsldavha
18405 || inst.instruction == M_MNEM_vrmlsldavhx
18406 || inst.instruction == M_MNEM_vrmlsldavhax)
18407 {
18408 et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, N_S32 | N_KEY);
18409 if (inst.operands[1].reg == REG_SP)
18410 as_tsktsk (MVE_BAD_SP);
18411 }
18412 else
18413 {
18414 if (inst.instruction == M_MNEM_vrmlaldavhx
18415 || inst.instruction == M_MNEM_vrmlaldavhax)
18416 et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, N_S32 | N_KEY);
18417 else
18418 et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK,
18419 N_U32 | N_S32 | N_KEY);
18420 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
18421 with vmax/min instructions, making the use of SP in assembly really
18422 nonsensical, so instead of issuing a warning like we do for other uses
18423 of SP for the odd register operand we error out. */
18424 constraint (inst.operands[1].reg == REG_SP, BAD_SP);
18425 }
18426
18427 /* Make sure we still check the second operand is an odd one and that PC is
18428 disallowed. This because we are parsing for any GPR operand, to be able
18429 to distinguish between giving a warning or an error for SP as described
18430 above. */
18431 constraint ((inst.operands[1].reg % 2) != 1, BAD_EVEN);
18432 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
18433
18434 if (inst.cond > COND_ALWAYS)
18435 inst.pred_insn_type = INSIDE_VPT_INSN;
18436 else
18437 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18438
18439 mve_encode_rrqq (et.type == NT_unsigned, 0);
18440}
18441
18442
8cd78170
AV		 18443static void
18444do_mve_vmaxnmv (void)
18445{
18446 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
18447 struct neon_type_el et
18448 = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY);
18449
18450 if (inst.cond > COND_ALWAYS)
18451 inst.pred_insn_type = INSIDE_VPT_INSN;
18452 else
18453 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18454
18455 if (inst.operands[0].reg == REG_SP)
18456 as_tsktsk (MVE_BAD_SP);
18457 else if (inst.operands[0].reg == REG_PC)
18458 as_tsktsk (MVE_BAD_PC);
18459
18460 mve_encode_rq (et.size == 16, 64);
18461}
18462
13ccd4c0
AV		 18463static void
18464do_mve_vmaxv (void)
18465{
18466 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
18467 struct neon_type_el et;
18468
18469 if (inst.instruction == M_MNEM_vmaxv || inst.instruction == M_MNEM_vminv)
18470 et = neon_check_type (2, rs, N_EQK, N_SU_MVE | N_KEY);
18471 else
18472 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
18473
18474 if (inst.cond > COND_ALWAYS)
18475 inst.pred_insn_type = INSIDE_VPT_INSN;
18476 else
18477 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18478
18479 if (inst.operands[0].reg == REG_SP)
18480 as_tsktsk (MVE_BAD_SP);
18481 else if (inst.operands[0].reg == REG_PC)
18482 as_tsktsk (MVE_BAD_PC);
18483
18484 mve_encode_rq (et.type == NT_unsigned, et.size);
18485}
18486
18487
643afb90
MW		 18488static void
18489do_neon_qrdmlah (void)
18490{
64c350f2 18491 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
42b16635
AV		 18492 return;
18493 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
643afb90 18494 {
42b16635
AV		 18495 /* Check we're on the correct architecture. */
18496 if (!mark_feature_used (&fpu_neon_ext_armv8))
18497 inst.error
18498 = _("instruction form not available on this architecture.");
18499 else if (!mark_feature_used (&fpu_neon_ext_v8_1))
18500 {
18501 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
18502 record_feature_use (&fpu_neon_ext_v8_1);
18503 }
18504 if (inst.operands[2].isscalar)
18505 {
18506 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
18507 struct neon_type_el et = neon_check_type (3, rs,
18508 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
18509 NEON_ENCODE (SCALAR, inst);
18510 neon_mul_mac (et, neon_quad (rs));
18511 }
18512 else
18513 {
18514 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
18515 struct neon_type_el et = neon_check_type (3, rs,
18516 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
18517 NEON_ENCODE (INTEGER, inst);
18518 /* The U bit (rounding) comes from bit mask. */
18519 neon_three_same (neon_quad (rs), 0, et.size);
18520 }
643afb90
MW		 18521 }
18522 else
18523 {
42b16635
AV		 18524 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
18525 struct neon_type_el et
23d188c7 18526 = neon_check_type (3, rs, N_EQK, N_EQK, N_S_32 | N_KEY);
42b16635 18527
643afb90 18528 NEON_ENCODE (INTEGER, inst);
42b16635 18529 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
643afb90
MW		 18530 }
18531}
18532
5287ad62
JB		 18533static void
18534do_neon_fcmp_absolute (void)
18535{
037e8744 18536 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
cc933301
JW		 18537 struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK,
18538 N_F_16_32 | N_KEY);
5287ad62 18539 /* Size field comes from bit mask. */
cc933301 18540 neon_three_same (neon_quad (rs), 1, et.size == 16 ? (int) et.size : -1);
5287ad62
JB		 18541}
18542
18543static void
18544do_neon_fcmp_absolute_inv (void)
18545{
18546 neon_exchange_operands ();
18547 do_neon_fcmp_absolute ();
18548}
18549
18550static void
18551do_neon_step (void)
18552{
037e8744 18553 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
cc933301
JW		 18554 struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK,
18555 N_F_16_32 | N_KEY);
18556 neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
5287ad62
JB		 18557}
18558
18559static void
18560do_neon_abs_neg (void)
18561{
037e8744
JB		 18562 enum neon_shape rs;
18563 struct neon_type_el et;
5f4273c7 18564
037e8744
JB		 18565 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
18566 return;
18567
037e8744 18568 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
cc933301 18569 et = neon_check_type (2, rs, N_EQK, N_S_32 | N_F_16_32 | N_KEY);
5f4273c7 18570
64c350f2
AV		 18571 if (!check_simd_pred_availability (et.type == NT_float,
18572 NEON_CHECK_ARCH | NEON_CHECK_CC))
485dee97
AV		 18573 return;
18574
5287ad62
JB		 18575 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18576 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18577 inst.instruction |= LOW4 (inst.operands[1].reg);
18578 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 18579 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 18580 inst.instruction |= (et.type == NT_float) << 10;
18581 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 18582
88714cb8 18583 neon_dp_fixup (&inst);
5287ad62
JB		 18584}
18585
18586static void
18587do_neon_sli (void)
18588{
64c350f2 18589 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
4401c241
AV		 18590 return;
18591
18592 enum neon_shape rs;
18593 struct neon_type_el et;
18594 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18595 {
18596 rs = neon_select_shape (NS_QQI, NS_NULL);
18597 et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_KEY);
18598 }
18599 else
18600 {
18601 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
18602 et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
18603 }
18604
18605
5287ad62
JB		 18606 int imm = inst.operands[2].imm;
18607 constraint (imm < 0 || (unsigned)imm >= et.size,
477330fc 18608 _("immediate out of range for insert"));
037e8744 18609 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
5287ad62
JB		 18610}
18611
18612static void
18613do_neon_sri (void)
18614{
64c350f2 18615 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
4401c241
AV		 18616 return;
18617
18618 enum neon_shape rs;
18619 struct neon_type_el et;
18620 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18621 {
18622 rs = neon_select_shape (NS_QQI, NS_NULL);
18623 et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_KEY);
18624 }
18625 else
18626 {
18627 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
18628 et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
18629 }
18630
5287ad62
JB		 18631 int imm = inst.operands[2].imm;
18632 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 18633 _("immediate out of range for insert"));
037e8744 18634 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
5287ad62
JB		 18635}
18636
18637static void
18638do_neon_qshlu_imm (void)
18639{
64c350f2 18640 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
5150f0d8
AV		 18641 return;
18642
18643 enum neon_shape rs;
18644 struct neon_type_el et;
18645 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18646 {
18647 rs = neon_select_shape (NS_QQI, NS_NULL);
18648 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
18649 }
18650 else
18651 {
18652 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
18653 et = neon_check_type (2, rs, N_EQK | N_UNS,
18654 N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
18655 }
18656
5287ad62
JB		 18657 int imm = inst.operands[2].imm;
18658 constraint (imm < 0 || (unsigned)imm >= et.size,
477330fc 18659 _("immediate out of range for shift"));
5287ad62
JB		 18660 /* Only encodes the 'U present' variant of the instruction.
18661 In this case, signed types have OP (bit 8) set to 0.
18662 Unsigned types have OP set to 1. */
18663 inst.instruction |= (et.type == NT_unsigned) << 8;
18664 /* The rest of the bits are the same as other immediate shifts. */
037e8744 18665 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
5287ad62
JB		 18666}
18667
18668static void
18669do_neon_qmovn (void)
18670{
18671 struct neon_type_el et = neon_check_type (2, NS_DQ,
18672 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
18673 /* Saturating move where operands can be signed or unsigned, and the
18674 destination has the same signedness. */
88714cb8 18675 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 18676 if (et.type == NT_unsigned)
18677 inst.instruction |= 0xc0;
18678 else
18679 inst.instruction |= 0x80;
18680 neon_two_same (0, 1, et.size / 2);
18681}
18682
18683static void
18684do_neon_qmovun (void)
18685{
18686 struct neon_type_el et = neon_check_type (2, NS_DQ,
18687 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
18688 /* Saturating move with unsigned results. Operands must be signed. */
88714cb8 18689 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 18690 neon_two_same (0, 1, et.size / 2);
18691}
18692
18693static void
18694do_neon_rshift_sat_narrow (void)
18695{
18696 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18697 or unsigned. If operands are unsigned, results must also be unsigned. */
18698 struct neon_type_el et = neon_check_type (2, NS_DQI,
18699 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
18700 int imm = inst.operands[2].imm;
18701 /* This gets the bounds check, size encoding and immediate bits calculation
18702 right. */
18703 et.size /= 2;
5f4273c7 18704
5287ad62
JB		 18705 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18706 VQMOVN.I<size> <Dd>, <Qm>. */
18707 if (imm == 0)
18708 {
18709 inst.operands[2].present = 0;
18710 inst.instruction = N_MNEM_vqmovn;
18711 do_neon_qmovn ();
18712 return;
18713 }
5f4273c7 18714
5287ad62 18715 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 18716 _("immediate out of range"));
5287ad62
JB		 18717 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
18718}
18719
18720static void
18721do_neon_rshift_sat_narrow_u (void)
18722{
18723 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18724 or unsigned. If operands are unsigned, results must also be unsigned. */
18725 struct neon_type_el et = neon_check_type (2, NS_DQI,
18726 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
18727 int imm = inst.operands[2].imm;
18728 /* This gets the bounds check, size encoding and immediate bits calculation
18729 right. */
18730 et.size /= 2;
18731
18732 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18733 VQMOVUN.I<size> <Dd>, <Qm>. */
18734 if (imm == 0)
18735 {
18736 inst.operands[2].present = 0;
18737 inst.instruction = N_MNEM_vqmovun;
18738 do_neon_qmovun ();
18739 return;
18740 }
18741
18742 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 18743 _("immediate out of range"));
5287ad62
JB		 18744 /* FIXME: The manual is kind of unclear about what value U should have in
18745 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18746 must be 1. */
18747 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
18748}
18749
18750static void
18751do_neon_movn (void)
18752{
18753 struct neon_type_el et = neon_check_type (2, NS_DQ,
18754 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
88714cb8 18755 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 18756 neon_two_same (0, 1, et.size / 2);
18757}
18758
18759static void
18760do_neon_rshift_narrow (void)
18761{
18762 struct neon_type_el et = neon_check_type (2, NS_DQI,
18763 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
18764 int imm = inst.operands[2].imm;
18765 /* This gets the bounds check, size encoding and immediate bits calculation
18766 right. */
18767 et.size /= 2;
5f4273c7 18768
5287ad62
JB		 18769 /* If immediate is zero then we are a pseudo-instruction for
18770 VMOVN.I<size> <Dd>, <Qm> */
18771 if (imm == 0)
18772 {
18773 inst.operands[2].present = 0;
18774 inst.instruction = N_MNEM_vmovn;
18775 do_neon_movn ();
18776 return;
18777 }
5f4273c7 18778
5287ad62 18779 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 18780 _("immediate out of range for narrowing operation"));
5287ad62
JB		 18781 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
18782}
18783
18784static void
18785do_neon_shll (void)
18786{
18787 /* FIXME: Type checking when lengthening. */
18788 struct neon_type_el et = neon_check_type (2, NS_QDI,
18789 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
18790 unsigned imm = inst.operands[2].imm;
18791
18792 if (imm == et.size)
18793 {
18794 /* Maximum shift variant. */
88714cb8 18795 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 18796 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18797 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18798 inst.instruction |= LOW4 (inst.operands[1].reg);
18799 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18800 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 18801
88714cb8 18802 neon_dp_fixup (&inst);
5287ad62
JB		 18803 }
18804 else
18805 {
18806 /* A more-specific type check for non-max versions. */
18807 et = neon_check_type (2, NS_QDI,
477330fc 18808 N_EQK | N_DBL, N_SU_32 | N_KEY);
88714cb8 18809 NEON_ENCODE (IMMED, inst);
5287ad62
JB		 18810 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
18811 }
18812}
18813
037e8744 18814/* Check the various types for the VCVT instruction, and return which version
5287ad62
JB		 18815 the current instruction is. */
18816
6b9a8b67
MGD		 18817#define CVT_FLAVOUR_VAR \
18818 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18819 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18820 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18821 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18822 /* Half-precision conversions. */ \
cc933301
JW		 18823 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18824 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18825 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18826 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
6b9a8b67
MGD		 18827 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18828 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
9db2f6b4
RL		 18829 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18830 Compared with single/double precision variants, only the co-processor \
18831 field is different, so the encoding flow is reused here. */ \
18832 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18833 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18834 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18835 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
aab2c27d 18836 CVT_VAR (bf16_f32, N_BF16, N_F32, whole_reg, NULL, NULL, NULL) \
6b9a8b67
MGD		 18837 /* VFP instructions. */ \
18838 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18839 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18840 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18841 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18842 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18843 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18844 /* VFP instructions with bitshift. */ \
18845 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18846 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18847 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18848 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18849 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18850 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18851 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18852 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18853
18854#define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18855 neon_cvt_flavour_##C,
18856
18857/* The different types of conversions we can do. */
18858enum neon_cvt_flavour
18859{
18860 CVT_FLAVOUR_VAR
18861 neon_cvt_flavour_invalid,
18862 neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64
18863};
18864
18865#undef CVT_VAR
18866
18867static enum neon_cvt_flavour
18868get_neon_cvt_flavour (enum neon_shape rs)
5287ad62 18869{
6b9a8b67
MGD		 18870#define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18871 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18872 if (et.type != NT_invtype) \
18873 { \
18874 inst.error = NULL; \
18875 return (neon_cvt_flavour_##C); \
5287ad62 18876 }
6b9a8b67 18877
5287ad62 18878 struct neon_type_el et;
037e8744 18879 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
477330fc 18880 || rs == NS_FF) ? N_VFP : 0;
037e8744
JB		 18881 /* The instruction versions which take an immediate take one register
18882 argument, which is extended to the width of the full register. Thus the
18883 "source" and "destination" registers must have the same width. Hack that
18884 here by making the size equal to the key (wider, in this case) operand. */
18885 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
5f4273c7 18886
6b9a8b67
MGD		 18887 CVT_FLAVOUR_VAR;
18888
18889 return neon_cvt_flavour_invalid;
5287ad62
JB		 18890#undef CVT_VAR
18891}
18892
7e8e6784
MGD		 18893enum neon_cvt_mode
18894{
18895 neon_cvt_mode_a,
18896 neon_cvt_mode_n,
18897 neon_cvt_mode_p,
18898 neon_cvt_mode_m,
18899 neon_cvt_mode_z,
30bdf752
MGD		 18900 neon_cvt_mode_x,
18901 neon_cvt_mode_r
7e8e6784
MGD		 18902};
18903
037e8744
JB		 18904/* Neon-syntax VFP conversions. */
18905
5287ad62 18906static void
6b9a8b67 18907do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
5287ad62 18908{
037e8744 18909 const char *opname = 0;
5f4273c7 18910
d54af2d0
RL		 18911 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI
18912 || rs == NS_FHI || rs == NS_HFI)
5287ad62 18913 {
037e8744
JB		 18914 /* Conversions with immediate bitshift. */
18915 const char *enc[] =
477330fc 18916 {
6b9a8b67
MGD		 18917#define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18918 CVT_FLAVOUR_VAR
18919 NULL
18920#undef CVT_VAR
477330fc 18921 };
037e8744 18922
6b9a8b67 18923 if (flavour < (int) ARRAY_SIZE (enc))
477330fc
RM		 18924 {
18925 opname = enc[flavour];
18926 constraint (inst.operands[0].reg != inst.operands[1].reg,
18927 _("operands 0 and 1 must be the same register"));
18928 inst.operands[1] = inst.operands[2];
18929 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
18930 }
5287ad62
JB		 18931 }
18932 else
18933 {
037e8744
JB		 18934 /* Conversions without bitshift. */
18935 const char *enc[] =
477330fc 18936 {
6b9a8b67
MGD		 18937#define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18938 CVT_FLAVOUR_VAR
18939 NULL
18940#undef CVT_VAR
477330fc 18941 };
037e8744 18942
6b9a8b67 18943 if (flavour < (int) ARRAY_SIZE (enc))
477330fc 18944 opname = enc[flavour];
037e8744
JB		 18945 }
18946
18947 if (opname)
18948 do_vfp_nsyn_opcode (opname);
9db2f6b4
RL		 18949
18950 /* ARMv8.2 fp16 VCVT instruction. */
18951 if (flavour == neon_cvt_flavour_s32_f16
18952 || flavour == neon_cvt_flavour_u32_f16
18953 || flavour == neon_cvt_flavour_f16_u32
18954 || flavour == neon_cvt_flavour_f16_s32)
18955 do_scalar_fp16_v82_encode ();
037e8744
JB		 18956}
18957
18958static void
18959do_vfp_nsyn_cvtz (void)
18960{
d54af2d0 18961 enum neon_shape rs = neon_select_shape (NS_FH, NS_FF, NS_FD, NS_NULL);
6b9a8b67 18962 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
037e8744
JB		 18963 const char *enc[] =
18964 {
6b9a8b67
MGD		 18965#define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18966 CVT_FLAVOUR_VAR
18967 NULL
18968#undef CVT_VAR
037e8744
JB		 18969 };
18970
6b9a8b67 18971 if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
037e8744
JB		 18972 do_vfp_nsyn_opcode (enc[flavour]);
18973}
f31fef98 18974
037e8744 18975static void
bacebabc 18976do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
7e8e6784
MGD		 18977 enum neon_cvt_mode mode)
18978{
18979 int sz, op;
18980 int rm;
18981
a715796b
TG		 18982 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18983 D register operands. */
18984 if (flavour == neon_cvt_flavour_s32_f64
18985 || flavour == neon_cvt_flavour_u32_f64)
18986 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
18987 _(BAD_FPU));
18988
9db2f6b4
RL		 18989 if (flavour == neon_cvt_flavour_s32_f16
18990 || flavour == neon_cvt_flavour_u32_f16)
18991 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
18992 _(BAD_FP16));
18993
5ee91343 18994 set_pred_insn_type (OUTSIDE_PRED_INSN);
7e8e6784
MGD		 18995
18996 switch (flavour)
18997 {
18998 case neon_cvt_flavour_s32_f64:
18999 sz = 1;
827f64ff 19000 op = 1;
7e8e6784
MGD		 19001 break;
19002 case neon_cvt_flavour_s32_f32:
19003 sz = 0;
19004 op = 1;
19005 break;
9db2f6b4
RL		 19006 case neon_cvt_flavour_s32_f16:
19007 sz = 0;
19008 op = 1;
19009 break;
7e8e6784
MGD		 19010 case neon_cvt_flavour_u32_f64:
19011 sz = 1;
19012 op = 0;
19013 break;
19014 case neon_cvt_flavour_u32_f32:
19015 sz = 0;
19016 op = 0;
19017 break;
9db2f6b4
RL		 19018 case neon_cvt_flavour_u32_f16:
19019 sz = 0;
19020 op = 0;
19021 break;
7e8e6784
MGD		 19022 default:
19023 first_error (_("invalid instruction shape"));
19024 return;
19025 }
19026
19027 switch (mode)
19028 {
19029 case neon_cvt_mode_a: rm = 0; break;
19030 case neon_cvt_mode_n: rm = 1; break;
19031 case neon_cvt_mode_p: rm = 2; break;
19032 case neon_cvt_mode_m: rm = 3; break;
19033 default: first_error (_("invalid rounding mode")); return;
19034 }
19035
19036 NEON_ENCODE (FPV8, inst);
19037 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
19038 encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
19039 inst.instruction |= sz << 8;
9db2f6b4
RL		 19040
19041 /* ARMv8.2 fp16 VCVT instruction. */
19042 if (flavour == neon_cvt_flavour_s32_f16
19043 ||flavour == neon_cvt_flavour_u32_f16)
19044 do_scalar_fp16_v82_encode ();
7e8e6784
MGD		 19045 inst.instruction |= op << 7;
19046 inst.instruction |= rm << 16;
19047 inst.instruction |= 0xf0000000;
19048 inst.is_neon = TRUE;
19049}
19050
19051static void
19052do_neon_cvt_1 (enum neon_cvt_mode mode)
037e8744
JB		 19053{
19054 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
d54af2d0
RL		 19055 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ,
19056 NS_FH, NS_HF, NS_FHI, NS_HFI,
19057 NS_NULL);
6b9a8b67 19058 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
037e8744 19059
cc933301
JW		 19060 if (flavour == neon_cvt_flavour_invalid)
19061 return;
19062
e3e535bc 19063 /* PR11109: Handle round-to-zero for VCVT conversions. */
7e8e6784 19064 if (mode == neon_cvt_mode_z
e3e535bc 19065 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
cc933301
JW		 19066 && (flavour == neon_cvt_flavour_s16_f16
19067 || flavour == neon_cvt_flavour_u16_f16
19068 || flavour == neon_cvt_flavour_s32_f32
bacebabc
RM		 19069 || flavour == neon_cvt_flavour_u32_f32
19070 || flavour == neon_cvt_flavour_s32_f64
6b9a8b67 19071 || flavour == neon_cvt_flavour_u32_f64)
e3e535bc
NC		 19072 && (rs == NS_FD || rs == NS_FF))
19073 {
19074 do_vfp_nsyn_cvtz ();
19075 return;
19076 }
19077
9db2f6b4
RL		 19078 /* ARMv8.2 fp16 VCVT conversions. */
19079 if (mode == neon_cvt_mode_z
19080 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16)
19081 && (flavour == neon_cvt_flavour_s32_f16
19082 || flavour == neon_cvt_flavour_u32_f16)
19083 && (rs == NS_FH))
19084 {
19085 do_vfp_nsyn_cvtz ();
19086 do_scalar_fp16_v82_encode ();
19087 return;
19088 }
19089
037e8744 19090 /* VFP rather than Neon conversions. */
6b9a8b67 19091 if (flavour >= neon_cvt_flavour_first_fp)
037e8744 19092 {
7e8e6784
MGD		 19093 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
19094 do_vfp_nsyn_cvt (rs, flavour);
19095 else
19096 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
19097
037e8744
JB		 19098 return;
19099 }
19100
19101 switch (rs)
19102 {
037e8744 19103 case NS_QQI:
dd9634d9
AV		 19104 if (mode == neon_cvt_mode_z
19105 && (flavour == neon_cvt_flavour_f16_s16
19106 || flavour == neon_cvt_flavour_f16_u16
19107 || flavour == neon_cvt_flavour_s16_f16
19108 || flavour == neon_cvt_flavour_u16_f16
19109 || flavour == neon_cvt_flavour_f32_u32
19110 || flavour == neon_cvt_flavour_f32_s32
19111 || flavour == neon_cvt_flavour_s32_f32
19112 || flavour == neon_cvt_flavour_u32_f32))
19113 {
64c350f2
AV		 19114 if (!check_simd_pred_availability (TRUE,
19115 NEON_CHECK_CC | NEON_CHECK_ARCH))
dd9634d9
AV		 19116 return;
19117 }
19118 else if (mode == neon_cvt_mode_n)
19119 {
19120 /* We are dealing with vcvt with the 'ne' condition. */
19121 inst.cond = 0x1;
19122 inst.instruction = N_MNEM_vcvt;
19123 do_neon_cvt_1 (neon_cvt_mode_z);
19124 return;
19125 }
19126 /* fall through. */
19127 case NS_DDI:
037e8744 19128 {
477330fc 19129 unsigned immbits;
cc933301
JW		 19130 unsigned enctab[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
19131 0x0000100, 0x1000100, 0x0, 0x1000000};
35997600 19132
dd9634d9
AV		 19133 if ((rs != NS_QQI || !ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
19134 && vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
19135 return;
19136
19137 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
19138 {
19139 constraint (inst.operands[2].present && inst.operands[2].imm == 0,
19140 _("immediate value out of range"));
19141 switch (flavour)
19142 {
19143 case neon_cvt_flavour_f16_s16:
19144 case neon_cvt_flavour_f16_u16:
19145 case neon_cvt_flavour_s16_f16:
19146 case neon_cvt_flavour_u16_f16:
19147 constraint (inst.operands[2].imm > 16,
19148 _("immediate value out of range"));
19149 break;
19150 case neon_cvt_flavour_f32_u32:
19151 case neon_cvt_flavour_f32_s32:
19152 case neon_cvt_flavour_s32_f32:
19153 case neon_cvt_flavour_u32_f32:
19154 constraint (inst.operands[2].imm > 32,
19155 _("immediate value out of range"));
19156 break;
19157 default:
19158 inst.error = BAD_FPU;
19159 return;
19160 }
19161 }
037e8744 19162
477330fc
RM		 19163 /* Fixed-point conversion with #0 immediate is encoded as an
19164 integer conversion. */
19165 if (inst.operands[2].present && inst.operands[2].imm == 0)
19166 goto int_encode;
477330fc
RM		 19167 NEON_ENCODE (IMMED, inst);
19168 if (flavour != neon_cvt_flavour_invalid)
19169 inst.instruction |= enctab[flavour];
19170 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19171 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19172 inst.instruction |= LOW4 (inst.operands[1].reg);
19173 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19174 inst.instruction |= neon_quad (rs) << 6;
19175 inst.instruction |= 1 << 21;
cc933301
JW		 19176 if (flavour < neon_cvt_flavour_s16_f16)
19177 {
19178 inst.instruction |= 1 << 21;
19179 immbits = 32 - inst.operands[2].imm;
19180 inst.instruction |= immbits << 16;
19181 }
19182 else
19183 {
19184 inst.instruction |= 3 << 20;
19185 immbits = 16 - inst.operands[2].imm;
19186 inst.instruction |= immbits << 16;
19187 inst.instruction &= ~(1 << 9);
19188 }
477330fc
RM		 19189
19190 neon_dp_fixup (&inst);
037e8744
JB		 19191 }
19192 break;
19193
037e8744 19194 case NS_QQ:
dd9634d9
AV		 19195 if ((mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
19196 || mode == neon_cvt_mode_m || mode == neon_cvt_mode_p)
19197 && (flavour == neon_cvt_flavour_s16_f16
19198 || flavour == neon_cvt_flavour_u16_f16
19199 || flavour == neon_cvt_flavour_s32_f32
19200 || flavour == neon_cvt_flavour_u32_f32))
19201 {
64c350f2
AV		 19202 if (!check_simd_pred_availability (TRUE,
19203 NEON_CHECK_CC | NEON_CHECK_ARCH8))
dd9634d9
AV		 19204 return;
19205 }
19206 else if (mode == neon_cvt_mode_z
19207 && (flavour == neon_cvt_flavour_f16_s16
19208 || flavour == neon_cvt_flavour_f16_u16
19209 || flavour == neon_cvt_flavour_s16_f16
19210 || flavour == neon_cvt_flavour_u16_f16
19211 || flavour == neon_cvt_flavour_f32_u32
19212 || flavour == neon_cvt_flavour_f32_s32
19213 || flavour == neon_cvt_flavour_s32_f32
19214 || flavour == neon_cvt_flavour_u32_f32))
19215 {
64c350f2
AV		 19216 if (!check_simd_pred_availability (TRUE,
19217 NEON_CHECK_CC | NEON_CHECK_ARCH))
dd9634d9
AV		 19218 return;
19219 }
19220 /* fall through. */
19221 case NS_DD:
7e8e6784
MGD		 19222 if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
19223 {
7e8e6784 19224
dd9634d9 19225 NEON_ENCODE (FLOAT, inst);
64c350f2
AV		 19226 if (!check_simd_pred_availability (TRUE,
19227 NEON_CHECK_CC | NEON_CHECK_ARCH8))
7e8e6784
MGD		 19228 return;
19229
19230 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19231 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19232 inst.instruction |= LOW4 (inst.operands[1].reg);
19233 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19234 inst.instruction |= neon_quad (rs) << 6;
cc933301
JW		 19235 inst.instruction |= (flavour == neon_cvt_flavour_u16_f16
19236 || flavour == neon_cvt_flavour_u32_f32) << 7;
7e8e6784 19237 inst.instruction |= mode << 8;
cc933301
JW		 19238 if (flavour == neon_cvt_flavour_u16_f16
19239 || flavour == neon_cvt_flavour_s16_f16)
19240 /* Mask off the original size bits and reencode them. */
19241 inst.instruction = ((inst.instruction & 0xfff3ffff) | (1 << 18));
19242
7e8e6784
MGD		 19243 if (thumb_mode)
19244 inst.instruction |= 0xfc000000;
19245 else
19246 inst.instruction |= 0xf0000000;
19247 }
19248 else
19249 {
037e8744 19250 int_encode:
7e8e6784 19251 {
cc933301
JW		 19252 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080,
19253 0x100, 0x180, 0x0, 0x080};
037e8744 19254
7e8e6784 19255 NEON_ENCODE (INTEGER, inst);
037e8744 19256
dd9634d9
AV		 19257 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
19258 {
19259 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
19260 return;
19261 }
037e8744 19262
7e8e6784
MGD		 19263 if (flavour != neon_cvt_flavour_invalid)
19264 inst.instruction |= enctab[flavour];
037e8744 19265
7e8e6784
MGD		 19266 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19267 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19268 inst.instruction |= LOW4 (inst.operands[1].reg);
19269 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19270 inst.instruction |= neon_quad (rs) << 6;
cc933301
JW		 19271 if (flavour >= neon_cvt_flavour_s16_f16
19272 && flavour <= neon_cvt_flavour_f16_u16)
19273 /* Half precision. */
19274 inst.instruction |= 1 << 18;
19275 else
19276 inst.instruction |= 2 << 18;
037e8744 19277
7e8e6784
MGD		 19278 neon_dp_fixup (&inst);
19279 }
19280 }
19281 break;
037e8744 19282
8e79c3df
CM		 19283 /* Half-precision conversions for Advanced SIMD -- neon. */
19284 case NS_QD:
19285 case NS_DQ:
bc52d49c
MM		 19286 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
19287 return;
8e79c3df
CM		 19288
19289 if ((rs == NS_DQ)
19290 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
19291 {
19292 as_bad (_("operand size must match register width"));
19293 break;
19294 }
19295
19296 if ((rs == NS_QD)
19297 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
19298 {
19299 as_bad (_("operand size must match register width"));
19300 break;
19301 }
19302
19303 if (rs == NS_DQ)
aab2c27d
MM		 19304 {
19305 if (flavour == neon_cvt_flavour_bf16_f32)
19306 {
19307 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH8) == FAIL)
19308 return;
19309 constraint (!mark_feature_used (&arm_ext_bf16), _(BAD_BF16));
19310 /* VCVT.bf16.f32. */
19311 inst.instruction = 0x11b60640;
19312 }
19313 else
19314 /* VCVT.f16.f32. */
19315 inst.instruction = 0x3b60600;
19316 }
8e79c3df 19317 else
aab2c27d 19318 /* VCVT.f32.f16. */
8e79c3df
CM		 19319 inst.instruction = 0x3b60700;
19320
19321 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19322 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19323 inst.instruction |= LOW4 (inst.operands[1].reg);
19324 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
88714cb8 19325 neon_dp_fixup (&inst);
8e79c3df
CM		 19326 break;
19327
037e8744
JB		 19328 default:
19329 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
7e8e6784
MGD		 19330 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
19331 do_vfp_nsyn_cvt (rs, flavour);
19332 else
19333 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
5287ad62 19334 }
5287ad62
JB		 19335}
19336
e3e535bc
NC		 19337static void
19338do_neon_cvtr (void)
19339{
7e8e6784 19340 do_neon_cvt_1 (neon_cvt_mode_x);
e3e535bc
NC		 19341}
19342
19343static void
19344do_neon_cvt (void)
19345{
7e8e6784
MGD		 19346 do_neon_cvt_1 (neon_cvt_mode_z);
19347}
19348
19349static void
19350do_neon_cvta (void)
19351{
19352 do_neon_cvt_1 (neon_cvt_mode_a);
19353}
19354
19355static void
19356do_neon_cvtn (void)
19357{
19358 do_neon_cvt_1 (neon_cvt_mode_n);
19359}
19360
19361static void
19362do_neon_cvtp (void)
19363{
19364 do_neon_cvt_1 (neon_cvt_mode_p);
19365}
19366
19367static void
19368do_neon_cvtm (void)
19369{
19370 do_neon_cvt_1 (neon_cvt_mode_m);
e3e535bc
NC		 19371}
19372
8e79c3df 19373static void
c70a8987 19374do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double)
8e79c3df 19375{
c70a8987
MGD		 19376 if (is_double)
19377 mark_feature_used (&fpu_vfp_ext_armv8);
8e79c3df 19378
c70a8987
MGD		 19379 encode_arm_vfp_reg (inst.operands[0].reg,
19380 (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd);
19381 encode_arm_vfp_reg (inst.operands[1].reg,
19382 (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm);
19383 inst.instruction |= to ? 0x10000 : 0;
19384 inst.instruction |= t ? 0x80 : 0;
19385 inst.instruction |= is_double ? 0x100 : 0;
19386 do_vfp_cond_or_thumb ();
19387}
8e79c3df 19388
c70a8987
MGD		 19389static void
19390do_neon_cvttb_1 (bfd_boolean t)
19391{
d54af2d0 19392 enum neon_shape rs = neon_select_shape (NS_HF, NS_HD, NS_FH, NS_FF, NS_FD,
dd9634d9 19393 NS_DF, NS_DH, NS_QQ, NS_QQI, NS_NULL);
8e79c3df 19394
c70a8987
MGD		 19395 if (rs == NS_NULL)
19396 return;
dd9634d9
AV		 19397 else if (rs == NS_QQ || rs == NS_QQI)
19398 {
19399 int single_to_half = 0;
64c350f2 19400 if (!check_simd_pred_availability (TRUE, NEON_CHECK_ARCH))
dd9634d9
AV		 19401 return;
19402
19403 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
19404
19405 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
19406 && (flavour == neon_cvt_flavour_u16_f16
19407 || flavour == neon_cvt_flavour_s16_f16
19408 || flavour == neon_cvt_flavour_f16_s16
19409 || flavour == neon_cvt_flavour_f16_u16
19410 || flavour == neon_cvt_flavour_u32_f32
19411 || flavour == neon_cvt_flavour_s32_f32
19412 || flavour == neon_cvt_flavour_f32_s32
19413 || flavour == neon_cvt_flavour_f32_u32))
19414 {
19415 inst.cond = 0xf;
19416 inst.instruction = N_MNEM_vcvt;
19417 set_pred_insn_type (INSIDE_VPT_INSN);
19418 do_neon_cvt_1 (neon_cvt_mode_z);
19419 return;
19420 }
19421 else if (rs == NS_QQ && flavour == neon_cvt_flavour_f32_f16)
19422 single_to_half = 1;
19423 else if (rs == NS_QQ && flavour != neon_cvt_flavour_f16_f32)
19424 {
19425 first_error (BAD_FPU);
19426 return;
19427 }
19428
19429 inst.instruction = 0xee3f0e01;
19430 inst.instruction |= single_to_half << 28;
19431 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19432 inst.instruction |= LOW4 (inst.operands[0].reg) << 13;
19433 inst.instruction |= t << 12;
19434 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19435 inst.instruction |= LOW4 (inst.operands[1].reg) << 1;
19436 inst.is_neon = 1;
19437 }
c70a8987
MGD		 19438 else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
19439 {
19440 inst.error = NULL;
19441 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
19442 }
19443 else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
19444 {
19445 inst.error = NULL;
19446 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE);
19447 }
19448 else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
19449 {
a715796b
TG		 19450 /* The VCVTB and VCVTT instructions with D-register operands
19451 don't work for SP only targets. */
19452 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
19453 _(BAD_FPU));
19454
c70a8987
MGD		 19455 inst.error = NULL;
19456 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
19457 }
19458 else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
19459 {
a715796b
TG		 19460 /* The VCVTB and VCVTT instructions with D-register operands
19461 don't work for SP only targets. */
19462 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
19463 _(BAD_FPU));
19464
c70a8987
MGD		 19465 inst.error = NULL;
19466 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
19467 }
aab2c27d
MM		 19468 else if (neon_check_type (2, rs, N_BF16 | N_VFP, N_F32).type != NT_invtype)
19469 {
19470 constraint (!mark_feature_used (&arm_ext_bf16), _(BAD_BF16));
19471 inst.error = NULL;
19472 inst.instruction |= (1 << 8);
19473 inst.instruction &= ~(1 << 9);
19474 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
19475 }
c70a8987
MGD		 19476 else
19477 return;
19478}
19479
19480static void
19481do_neon_cvtb (void)
19482{
19483 do_neon_cvttb_1 (FALSE);
8e79c3df
CM		 19484}
19485
19486
19487static void
19488do_neon_cvtt (void)
19489{
c70a8987 19490 do_neon_cvttb_1 (TRUE);
8e79c3df
CM		 19491}
19492
5287ad62
JB		 19493static void
19494neon_move_immediate (void)
19495{
037e8744
JB		 19496 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
19497 struct neon_type_el et = neon_check_type (2, rs,
19498 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
5287ad62 19499 unsigned immlo, immhi = 0, immbits;
c96612cc 19500 int op, cmode, float_p;
5287ad62 19501
037e8744 19502 constraint (et.type == NT_invtype,
477330fc 19503 _("operand size must be specified for immediate VMOV"));
037e8744 19504
5287ad62
JB		 19505 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
19506 op = (inst.instruction & (1 << 5)) != 0;
19507
19508 immlo = inst.operands[1].imm;
19509 if (inst.operands[1].regisimm)
19510 immhi = inst.operands[1].reg;
19511
19512 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
477330fc 19513 _("immediate has bits set outside the operand size"));
5287ad62 19514
c96612cc
JB		 19515 float_p = inst.operands[1].immisfloat;
19516
19517 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
477330fc 19518 et.size, et.type)) == FAIL)
5287ad62
JB		 19519 {
19520 /* Invert relevant bits only. */
19521 neon_invert_size (&immlo, &immhi, et.size);
19522 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
477330fc
RM		 19523 with one or the other; those cases are caught by
19524 neon_cmode_for_move_imm. */
5287ad62 19525 op = !op;
c96612cc
JB		 19526 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
19527 &op, et.size, et.type)) == FAIL)
477330fc
RM		 19528 {
19529 first_error (_("immediate out of range"));
19530 return;
19531 }
5287ad62
JB		 19532 }
19533
19534 inst.instruction &= ~(1 << 5);
19535 inst.instruction |= op << 5;
19536
19537 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19538 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
037e8744 19539 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 19540 inst.instruction |= cmode << 8;
19541
19542 neon_write_immbits (immbits);
19543}
19544
19545static void
19546do_neon_mvn (void)
19547{
64c350f2 19548 if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
1a186d29
AV		 19549 return;
19550
5287ad62
JB		 19551 if (inst.operands[1].isreg)
19552 {
1a186d29
AV		 19553 enum neon_shape rs;
19554 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19555 rs = neon_select_shape (NS_QQ, NS_NULL);
19556 else
19557 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5f4273c7 19558
88714cb8 19559 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 19560 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19561 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19562 inst.instruction |= LOW4 (inst.operands[1].reg);
19563 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 19564 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 19565 }
19566 else
19567 {
88714cb8 19568 NEON_ENCODE (IMMED, inst);
5287ad62
JB		 19569 neon_move_immediate ();
19570 }
19571
88714cb8 19572 neon_dp_fixup (&inst);
1a186d29
AV		 19573
19574 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19575 {
19576 constraint (!inst.operands[1].isreg && !inst.operands[0].isquad, BAD_FPU);
1a186d29 19577 }
5287ad62
JB		 19578}
19579
19580/* Encode instructions of form:
19581
19582 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
5f4273c7 19583 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
5287ad62
JB		 19584
19585static void
19586neon_mixed_length (struct neon_type_el et, unsigned size)
19587{
19588 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19589 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19590 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
19591 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
19592 inst.instruction |= LOW4 (inst.operands[2].reg);
19593 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
19594 inst.instruction |= (et.type == NT_unsigned) << 24;
19595 inst.instruction |= neon_logbits (size) << 20;
5f4273c7 19596
88714cb8 19597 neon_dp_fixup (&inst);
5287ad62
JB		 19598}
19599
19600static void
19601do_neon_dyadic_long (void)
19602{
66d1f7cc 19603 enum neon_shape rs = neon_select_shape (NS_QDD, NS_HHH, NS_FFF, NS_DDD, NS_NULL);
5ee91343
AV		 19604 if (rs == NS_QDD)
19605 {
19606 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH | NEON_CHECK_CC) == FAIL)
19607 return;
19608
19609 NEON_ENCODE (INTEGER, inst);
19610 /* FIXME: Type checking for lengthening op. */
19611 struct neon_type_el et = neon_check_type (3, NS_QDD,
19612 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
19613 neon_mixed_length (et, et.size);
19614 }
19615 else if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
19616 && (inst.cond == 0xf || inst.cond == 0x10))
19617 {
19618 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19619 in an IT block with le/lt conditions. */
19620
19621 if (inst.cond == 0xf)
19622 inst.cond = 0xb;
19623 else if (inst.cond == 0x10)
19624 inst.cond = 0xd;
19625
19626 inst.pred_insn_type = INSIDE_IT_INSN;
19627
19628 if (inst.instruction == N_MNEM_vaddl)
19629 {
19630 inst.instruction = N_MNEM_vadd;
19631 do_neon_addsub_if_i ();
19632 }
19633 else if (inst.instruction == N_MNEM_vsubl)
19634 {
19635 inst.instruction = N_MNEM_vsub;
19636 do_neon_addsub_if_i ();
19637 }
19638 else if (inst.instruction == N_MNEM_vabdl)
19639 {
19640 inst.instruction = N_MNEM_vabd;
19641 do_neon_dyadic_if_su ();
19642 }
19643 }
19644 else
19645 first_error (BAD_FPU);
5287ad62
JB		 19646}
19647
19648static void
19649do_neon_abal (void)
19650{
19651 struct neon_type_el et = neon_check_type (3, NS_QDD,
19652 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
19653 neon_mixed_length (et, et.size);
19654}
19655
19656static void
19657neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
19658{
19659 if (inst.operands[2].isscalar)
19660 {
dcbf9037 19661 struct neon_type_el et = neon_check_type (3, NS_QDS,
477330fc 19662 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
88714cb8 19663 NEON_ENCODE (SCALAR, inst);
5287ad62
JB		 19664 neon_mul_mac (et, et.type == NT_unsigned);
19665 }
19666 else
19667 {
19668 struct neon_type_el et = neon_check_type (3, NS_QDD,
477330fc 19669 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
88714cb8 19670 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 19671 neon_mixed_length (et, et.size);
19672 }
19673}
19674
19675static void
19676do_neon_mac_maybe_scalar_long (void)
19677{
19678 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
19679}
19680
dec41383
JW		 19681/* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19682 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19683
19684static unsigned
19685neon_scalar_for_fmac_fp16_long (unsigned scalar, unsigned quad_p)
19686{
19687 unsigned regno = NEON_SCALAR_REG (scalar);
19688 unsigned elno = NEON_SCALAR_INDEX (scalar);
19689
19690 if (quad_p)
19691 {
19692 if (regno > 7 || elno > 3)
19693 goto bad_scalar;
19694
19695 return ((regno & 0x7)
19696 | ((elno & 0x1) << 3)
19697 | (((elno >> 1) & 0x1) << 5));
19698 }
19699 else
19700 {
19701 if (regno > 15 || elno > 1)
19702 goto bad_scalar;
19703
19704 return (((regno & 0x1) << 5)
19705 | ((regno >> 1) & 0x7)
19706 | ((elno & 0x1) << 3));
19707 }
19708
dc1e8a47 19709 bad_scalar:
dec41383
JW		 19710 first_error (_("scalar out of range for multiply instruction"));
19711 return 0;
19712}
19713
19714static void
19715do_neon_fmac_maybe_scalar_long (int subtype)
19716{
19717 enum neon_shape rs;
19718 int high8;
19719 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19720 field (bits[21:20]) has different meaning. For scalar index variant, it's
19721 used to differentiate add and subtract, otherwise it's with fixed value
19722 0x2. */
19723 int size = -1;
19724
dec41383
JW		 19725 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19726 be a scalar index register. */
19727 if (inst.operands[2].isscalar)
19728 {
19729 high8 = 0xfe000000;
19730 if (subtype)
19731 size = 16;
19732 rs = neon_select_shape (NS_DHS, NS_QDS, NS_NULL);
19733 }
19734 else
19735 {
19736 high8 = 0xfc000000;
19737 size = 32;
19738 if (subtype)
19739 inst.instruction |= (0x1 << 23);
19740 rs = neon_select_shape (NS_DHH, NS_QDD, NS_NULL);
19741 }
19742
aab2c27d
MM		 19743
19744 if (inst.cond != COND_ALWAYS)
19745 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19746 "behaviour is UNPREDICTABLE"));
19747
19748 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16_fml),
19749 _(BAD_FP16));
19750
19751 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
19752 _(BAD_FPU));
dec41383
JW		 19753
19754 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19755 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19756 so we simply pass -1 as size. */
19757 unsigned quad_p = (rs == NS_QDD || rs == NS_QDS);
19758 neon_three_same (quad_p, 0, size);
19759
19760 /* Undo neon_dp_fixup. Redo the high eight bits. */
19761 inst.instruction &= 0x00ffffff;
19762 inst.instruction |= high8;
19763
dec41383
JW		 19764 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19765 whether the instruction is in Q form and whether Vm is a scalar indexed
19766 operand. */
19767 if (inst.operands[2].isscalar)
19768 {
19769 unsigned rm
19770 = neon_scalar_for_fmac_fp16_long (inst.operands[2].reg, quad_p);
19771 inst.instruction &= 0xffffffd0;
19772 inst.instruction |= rm;
19773
19774 if (!quad_p)
19775 {
19776 /* Redo Rn as well. */
19777 inst.instruction &= 0xfff0ff7f;
19778 inst.instruction |= HI4 (inst.operands[1].reg) << 16;
19779 inst.instruction |= LOW1 (inst.operands[1].reg) << 7;
19780 }
19781 }
19782 else if (!quad_p)
19783 {
19784 /* Redo Rn and Rm. */
19785 inst.instruction &= 0xfff0ff50;
19786 inst.instruction |= HI4 (inst.operands[1].reg) << 16;
19787 inst.instruction |= LOW1 (inst.operands[1].reg) << 7;
19788 inst.instruction |= HI4 (inst.operands[2].reg);
19789 inst.instruction |= LOW1 (inst.operands[2].reg) << 5;
19790 }
19791}
19792
19793static void
19794do_neon_vfmal (void)
19795{
19796 return do_neon_fmac_maybe_scalar_long (0);
19797}
19798
19799static void
19800do_neon_vfmsl (void)
19801{
19802 return do_neon_fmac_maybe_scalar_long (1);
19803}
19804
5287ad62
JB		 19805static void
19806do_neon_dyadic_wide (void)
19807{
19808 struct neon_type_el et = neon_check_type (3, NS_QQD,
19809 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
19810 neon_mixed_length (et, et.size);
19811}
19812
19813static void
19814do_neon_dyadic_narrow (void)
19815{
19816 struct neon_type_el et = neon_check_type (3, NS_QDD,
19817 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
428e3f1f
PB		 19818 /* Operand sign is unimportant, and the U bit is part of the opcode,
19819 so force the operand type to integer. */
19820 et.type = NT_integer;
5287ad62
JB		 19821 neon_mixed_length (et, et.size / 2);
19822}
19823
19824static void
19825do_neon_mul_sat_scalar_long (void)
19826{
19827 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
19828}
19829
19830static void
19831do_neon_vmull (void)
19832{
19833 if (inst.operands[2].isscalar)
19834 do_neon_mac_maybe_scalar_long ();
19835 else
19836 {
19837 struct neon_type_el et = neon_check_type (3, NS_QDD,
477330fc 19838 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY);
4f51b4bd 19839
5287ad62 19840 if (et.type == NT_poly)
477330fc 19841 NEON_ENCODE (POLY, inst);
5287ad62 19842 else
477330fc 19843 NEON_ENCODE (INTEGER, inst);
4f51b4bd
MGD		 19844
19845 /* For polynomial encoding the U bit must be zero, and the size must
19846 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19847 obviously, as 0b10). */
19848 if (et.size == 64)
19849 {
19850 /* Check we're on the correct architecture. */
19851 if (!mark_feature_used (&fpu_crypto_ext_armv8))
19852 inst.error =
19853 _("Instruction form not available on this architecture.");
19854
19855 et.size = 32;
19856 }
19857
5287ad62
JB		 19858 neon_mixed_length (et, et.size);
19859 }
19860}
19861
19862static void
19863do_neon_ext (void)
19864{
037e8744 19865 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
5287ad62
JB		 19866 struct neon_type_el et = neon_check_type (3, rs,
19867 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
19868 unsigned imm = (inst.operands[3].imm * et.size) / 8;
35997600
NC		 19869
19870 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
19871 _("shift out of range"));
5287ad62
JB		 19872 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19873 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19874 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
19875 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
19876 inst.instruction |= LOW4 (inst.operands[2].reg);
19877 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
037e8744 19878 inst.instruction |= neon_quad (rs) << 6;
5287ad62 19879 inst.instruction |= imm << 8;
5f4273c7 19880
88714cb8 19881 neon_dp_fixup (&inst);
5287ad62
JB		 19882}
19883
19884static void
19885do_neon_rev (void)
19886{
64c350f2 19887 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
4401c241
AV		 19888 return;
19889
19890 enum neon_shape rs;
19891 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19892 rs = neon_select_shape (NS_QQ, NS_NULL);
19893 else
19894 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19895
5287ad62
JB		 19896 struct neon_type_el et = neon_check_type (2, rs,
19897 N_EQK, N_8 | N_16 | N_32 | N_KEY);
4401c241 19898
5287ad62
JB		 19899 unsigned op = (inst.instruction >> 7) & 3;
19900 /* N (width of reversed regions) is encoded as part of the bitmask. We
19901 extract it here to check the elements to be reversed are smaller.
19902 Otherwise we'd get a reserved instruction. */
19903 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
4401c241
AV		 19904
19905 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) && elsize == 64
19906 && inst.operands[0].reg == inst.operands[1].reg)
19907 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19908 " operands makes instruction UNPREDICTABLE"));
19909
9c2799c2 19910 gas_assert (elsize != 0);
5287ad62 19911 constraint (et.size >= elsize,
477330fc 19912 _("elements must be smaller than reversal region"));
037e8744 19913 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 19914}
19915
19916static void
19917do_neon_dup (void)
19918{
19919 if (inst.operands[1].isscalar)
19920 {
b409bdb6
AV		 19921 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1),
19922 BAD_FPU);
037e8744 19923 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
dcbf9037 19924 struct neon_type_el et = neon_check_type (2, rs,
477330fc 19925 N_EQK, N_8 | N_16 | N_32 | N_KEY);
5287ad62 19926 unsigned sizebits = et.size >> 3;
dcbf9037 19927 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
5287ad62 19928 int logsize = neon_logbits (et.size);
dcbf9037 19929 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
037e8744
JB		 19930
19931 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
477330fc 19932 return;
037e8744 19933
88714cb8 19934 NEON_ENCODE (SCALAR, inst);
5287ad62
JB		 19935 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19936 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19937 inst.instruction |= LOW4 (dm);
19938 inst.instruction |= HI1 (dm) << 5;
037e8744 19939 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 19940 inst.instruction |= x << 17;
19941 inst.instruction |= sizebits << 16;
5f4273c7 19942
88714cb8 19943 neon_dp_fixup (&inst);
5287ad62
JB		 19944 }
19945 else
19946 {
037e8744
JB		 19947 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
19948 struct neon_type_el et = neon_check_type (2, rs,
477330fc 19949 N_8 | N_16 | N_32 | N_KEY, N_EQK);
b409bdb6
AV		 19950 if (rs == NS_QR)
19951 {
64c350f2 19952 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH))
b409bdb6
AV		 19953 return;
19954 }
19955 else
19956 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1),
19957 BAD_FPU);
19958
19959 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19960 {
19961 if (inst.operands[1].reg == REG_SP)
19962 as_tsktsk (MVE_BAD_SP);
19963 else if (inst.operands[1].reg == REG_PC)
19964 as_tsktsk (MVE_BAD_PC);
19965 }
19966
5287ad62 19967 /* Duplicate ARM register to lanes of vector. */
88714cb8 19968 NEON_ENCODE (ARMREG, inst);
5287ad62 19969 switch (et.size)
477330fc
RM		 19970 {
19971 case 8: inst.instruction |= 0x400000; break;
19972 case 16: inst.instruction |= 0x000020; break;
19973 case 32: inst.instruction |= 0x000000; break;
19974 default: break;
19975 }
5287ad62
JB		 19976 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
19977 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
19978 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
037e8744 19979 inst.instruction |= neon_quad (rs) << 21;
5287ad62 19980 /* The encoding for this instruction is identical for the ARM and Thumb
477330fc 19981 variants, except for the condition field. */
037e8744 19982 do_vfp_cond_or_thumb ();
5287ad62
JB		 19983 }
19984}
19985
57785aa2
AV		 19986static void
19987do_mve_mov (int toQ)
19988{
19989 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19990 return;
19991 if (inst.cond > COND_ALWAYS)
19992 inst.pred_insn_type = MVE_UNPREDICABLE_INSN;
19993
19994 unsigned Rt = 0, Rt2 = 1, Q0 = 2, Q1 = 3;
19995 if (toQ)
19996 {
19997 Q0 = 0;
19998 Q1 = 1;
19999 Rt = 2;
20000 Rt2 = 3;
20001 }
20002
20003 constraint (inst.operands[Q0].reg != inst.operands[Q1].reg + 2,
20004 _("Index one must be [2,3] and index two must be two less than"
20005 " index one."));
20006 constraint (inst.operands[Rt].reg == inst.operands[Rt2].reg,
20007 _("General purpose registers may not be the same"));
20008 constraint (inst.operands[Rt].reg == REG_SP
20009 || inst.operands[Rt2].reg == REG_SP,
20010 BAD_SP);
20011 constraint (inst.operands[Rt].reg == REG_PC
20012 || inst.operands[Rt2].reg == REG_PC,
20013 BAD_PC);
20014
20015 inst.instruction = 0xec000f00;
20016 inst.instruction |= HI1 (inst.operands[Q1].reg / 32) << 23;
20017 inst.instruction |= !!toQ << 20;
20018 inst.instruction |= inst.operands[Rt2].reg << 16;
20019 inst.instruction |= LOW4 (inst.operands[Q1].reg / 32) << 13;
20020 inst.instruction |= (inst.operands[Q1].reg % 4) << 4;
20021 inst.instruction |= inst.operands[Rt].reg;
20022}
20023
20024static void
20025do_mve_movn (void)
20026{
20027 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20028 return;
20029
20030 if (inst.cond > COND_ALWAYS)
20031 inst.pred_insn_type = INSIDE_VPT_INSN;
20032 else
20033 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
20034
20035 struct neon_type_el et = neon_check_type (2, NS_QQ, N_EQK, N_I16 | N_I32
20036 | N_KEY);
20037
20038 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20039 inst.instruction |= (neon_logbits (et.size) - 1) << 18;
20040 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20041 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
20042 inst.instruction |= LOW4 (inst.operands[1].reg);
20043 inst.is_neon = 1;
20044
20045}
20046
5287ad62
JB		 20047/* VMOV has particularly many variations. It can be one of:
20048 0. VMOV<c><q> <Qd>, <Qm>
20049 1. VMOV<c><q> <Dd>, <Dm>
20050 (Register operations, which are VORR with Rm = Rn.)
20051 2. VMOV<c><q>.<dt> <Qd>, #<imm>
20052 3. VMOV<c><q>.<dt> <Dd>, #<imm>
20053 (Immediate loads.)
20054 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
20055 (ARM register to scalar.)
20056 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
20057 (Two ARM registers to vector.)
20058 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
20059 (Scalar to ARM register.)
20060 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
20061 (Vector to two ARM registers.)
037e8744
JB		 20062 8. VMOV.F32 <Sd>, <Sm>
20063 9. VMOV.F64 <Dd>, <Dm>
20064 (VFP register moves.)
20065 10. VMOV.F32 <Sd>, #imm
20066 11. VMOV.F64 <Dd>, #imm
20067 (VFP float immediate load.)
20068 12. VMOV <Rd>, <Sm>
20069 (VFP single to ARM reg.)
20070 13. VMOV <Sd>, <Rm>
20071 (ARM reg to VFP single.)
20072 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
20073 (Two ARM regs to two VFP singles.)
20074 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
20075 (Two VFP singles to two ARM regs.)
57785aa2
AV		 20076 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
20077 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
20078 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
20079 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
5f4273c7 20080
037e8744
JB		 20081 These cases can be disambiguated using neon_select_shape, except cases 1/9
20082 and 3/11 which depend on the operand type too.
5f4273c7 20083
5287ad62 20084 All the encoded bits are hardcoded by this function.
5f4273c7 20085
b7fc2769
JB		 20086 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
20087 Cases 5, 7 may be used with VFPv2 and above.
5f4273c7 20088
5287ad62 20089 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
5f4273c7 20090 can specify a type where it doesn't make sense to, and is ignored). */
5287ad62
JB		 20091
20092static void
20093do_neon_mov (void)
20094{
57785aa2
AV		 20095 enum neon_shape rs = neon_select_shape (NS_RRSS, NS_SSRR, NS_RRFF, NS_FFRR,
20096 NS_DRR, NS_RRD, NS_QQ, NS_DD, NS_QI,
20097 NS_DI, NS_SR, NS_RS, NS_FF, NS_FI,
20098 NS_RF, NS_FR, NS_HR, NS_RH, NS_HI,
20099 NS_NULL);
037e8744
JB		 20100 struct neon_type_el et;
20101 const char *ldconst = 0;
5287ad62 20102
037e8744 20103 switch (rs)
5287ad62 20104 {
037e8744
JB		 20105 case NS_DD: /* case 1/9. */
20106 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
20107 /* It is not an error here if no type is given. */
20108 inst.error = NULL;
1c1e0fe5
SP		 20109
20110 /* In MVE we interpret the following instructions as same, so ignoring
20111 the following type (float) and size (64) checks.
20112 a: VMOV<c><q> <Dd>, <Dm>
20113 b: VMOV<c><q>.F64 <Dd>, <Dm>. */
20114 if ((et.type == NT_float && et.size == 64)
20115 || (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)))
477330fc
RM		 20116 {
20117 do_vfp_nsyn_opcode ("fcpyd");
20118 break;
20119 }
037e8744 20120 /* fall through. */
5287ad62 20121
037e8744
JB		 20122 case NS_QQ: /* case 0/1. */
20123 {
64c350f2
AV		 20124 if (!check_simd_pred_availability (FALSE,
20125 NEON_CHECK_CC | NEON_CHECK_ARCH))
477330fc
RM		 20126 return;
20127 /* The architecture manual I have doesn't explicitly state which
20128 value the U bit should have for register->register moves, but
20129 the equivalent VORR instruction has U = 0, so do that. */
20130 inst.instruction = 0x0200110;
20131 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20132 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20133 inst.instruction |= LOW4 (inst.operands[1].reg);
20134 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
20135 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
20136 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
20137 inst.instruction |= neon_quad (rs) << 6;
20138
20139 neon_dp_fixup (&inst);
037e8744
JB		 20140 }
20141 break;
5f4273c7 20142
037e8744
JB		 20143 case NS_DI: /* case 3/11. */
20144 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
20145 inst.error = NULL;
20146 if (et.type == NT_float && et.size == 64)
477330fc
RM		 20147 {
20148 /* case 11 (fconstd). */
20149 ldconst = "fconstd";
20150 goto encode_fconstd;
20151 }
037e8744
JB		 20152 /* fall through. */
20153
20154 case NS_QI: /* case 2/3. */
64c350f2
AV		 20155 if (!check_simd_pred_availability (FALSE,
20156 NEON_CHECK_CC | NEON_CHECK_ARCH))
477330fc 20157 return;
037e8744
JB		 20158 inst.instruction = 0x0800010;
20159 neon_move_immediate ();
88714cb8 20160 neon_dp_fixup (&inst);
5287ad62 20161 break;
5f4273c7 20162
037e8744
JB		 20163 case NS_SR: /* case 4. */
20164 {
477330fc
RM		 20165 unsigned bcdebits = 0;
20166 int logsize;
20167 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
20168 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
037e8744 20169
05ac0ffb
JB		 20170 /* .<size> is optional here, defaulting to .32. */
20171 if (inst.vectype.elems == 0
20172 && inst.operands[0].vectype.type == NT_invtype
20173 && inst.operands[1].vectype.type == NT_invtype)
20174 {
20175 inst.vectype.el[0].type = NT_untyped;
20176 inst.vectype.el[0].size = 32;
20177 inst.vectype.elems = 1;
20178 }
20179
477330fc
RM		 20180 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
20181 logsize = neon_logbits (et.size);
20182
57785aa2
AV		 20183 if (et.size != 32)
20184 {
20185 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
20186 && vfp_or_neon_is_neon (NEON_CHECK_ARCH) == FAIL)
20187 return;
20188 }
20189 else
20190 {
20191 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
20192 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
20193 _(BAD_FPU));
20194 }
20195
20196 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20197 {
20198 if (inst.operands[1].reg == REG_SP)
20199 as_tsktsk (MVE_BAD_SP);
20200 else if (inst.operands[1].reg == REG_PC)
20201 as_tsktsk (MVE_BAD_PC);
20202 }
20203 unsigned size = inst.operands[0].isscalar == 1 ? 64 : 128;
20204
477330fc 20205 constraint (et.type == NT_invtype, _("bad type for scalar"));
57785aa2
AV		 20206 constraint (x >= size / et.size, _("scalar index out of range"));
20207
477330fc
RM		 20208
20209 switch (et.size)
20210 {
20211 case 8: bcdebits = 0x8; break;
20212 case 16: bcdebits = 0x1; break;
20213 case 32: bcdebits = 0x0; break;
20214 default: ;
20215 }
20216
57785aa2 20217 bcdebits |= (x & ((1 << (3-logsize)) - 1)) << logsize;
477330fc
RM		 20218
20219 inst.instruction = 0xe000b10;
20220 do_vfp_cond_or_thumb ();
20221 inst.instruction |= LOW4 (dn) << 16;
20222 inst.instruction |= HI1 (dn) << 7;
20223 inst.instruction |= inst.operands[1].reg << 12;
20224 inst.instruction |= (bcdebits & 3) << 5;
57785aa2
AV		 20225 inst.instruction |= ((bcdebits >> 2) & 3) << 21;
20226 inst.instruction |= (x >> (3-logsize)) << 16;
037e8744
JB		 20227 }
20228 break;
5f4273c7 20229
037e8744 20230 case NS_DRR: /* case 5 (fmdrr). */
57785aa2
AV		 20231 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
20232 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
477330fc 20233 _(BAD_FPU));
b7fc2769 20234
037e8744
JB		 20235 inst.instruction = 0xc400b10;
20236 do_vfp_cond_or_thumb ();
20237 inst.instruction |= LOW4 (inst.operands[0].reg);
20238 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
20239 inst.instruction |= inst.operands[1].reg << 12;
20240 inst.instruction |= inst.operands[2].reg << 16;
20241 break;
5f4273c7 20242
037e8744
JB		 20243 case NS_RS: /* case 6. */
20244 {
477330fc
RM		 20245 unsigned logsize;
20246 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
20247 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
20248 unsigned abcdebits = 0;
037e8744 20249
05ac0ffb
JB		 20250 /* .<dt> is optional here, defaulting to .32. */
20251 if (inst.vectype.elems == 0
20252 && inst.operands[0].vectype.type == NT_invtype
20253 && inst.operands[1].vectype.type == NT_invtype)
20254 {
20255 inst.vectype.el[0].type = NT_untyped;
20256 inst.vectype.el[0].size = 32;
20257 inst.vectype.elems = 1;
20258 }
20259
91d6fa6a
NC		 20260 et = neon_check_type (2, NS_NULL,
20261 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
477330fc
RM		 20262 logsize = neon_logbits (et.size);
20263
57785aa2
AV		 20264 if (et.size != 32)
20265 {
20266 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
20267 && vfp_or_neon_is_neon (NEON_CHECK_CC
20268 | NEON_CHECK_ARCH) == FAIL)
20269 return;
20270 }
20271 else
20272 {
20273 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
20274 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
20275 _(BAD_FPU));
20276 }
20277
20278 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20279 {
20280 if (inst.operands[0].reg == REG_SP)
20281 as_tsktsk (MVE_BAD_SP);
20282 else if (inst.operands[0].reg == REG_PC)
20283 as_tsktsk (MVE_BAD_PC);
20284 }
20285
20286 unsigned size = inst.operands[1].isscalar == 1 ? 64 : 128;
20287
477330fc 20288 constraint (et.type == NT_invtype, _("bad type for scalar"));
57785aa2 20289 constraint (x >= size / et.size, _("scalar index out of range"));
477330fc
RM		 20290
20291 switch (et.size)
20292 {
20293 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
20294 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
20295 case 32: abcdebits = 0x00; break;
20296 default: ;
20297 }
20298
57785aa2 20299 abcdebits |= (x & ((1 << (3-logsize)) - 1)) << logsize;
477330fc
RM		 20300 inst.instruction = 0xe100b10;
20301 do_vfp_cond_or_thumb ();
20302 inst.instruction |= LOW4 (dn) << 16;
20303 inst.instruction |= HI1 (dn) << 7;
20304 inst.instruction |= inst.operands[0].reg << 12;
20305 inst.instruction |= (abcdebits & 3) << 5;
20306 inst.instruction |= (abcdebits >> 2) << 21;
57785aa2 20307 inst.instruction |= (x >> (3-logsize)) << 16;
037e8744
JB		 20308 }
20309 break;
5f4273c7 20310
037e8744 20311 case NS_RRD: /* case 7 (fmrrd). */
57785aa2
AV		 20312 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
20313 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
477330fc 20314 _(BAD_FPU));
037e8744
JB		 20315
20316 inst.instruction = 0xc500b10;
20317 do_vfp_cond_or_thumb ();
20318 inst.instruction |= inst.operands[0].reg << 12;
20319 inst.instruction |= inst.operands[1].reg << 16;
20320 inst.instruction |= LOW4 (inst.operands[2].reg);
20321 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
20322 break;
5f4273c7 20323
037e8744
JB		 20324 case NS_FF: /* case 8 (fcpys). */
20325 do_vfp_nsyn_opcode ("fcpys");
20326 break;
5f4273c7 20327
9db2f6b4 20328 case NS_HI:
037e8744
JB		 20329 case NS_FI: /* case 10 (fconsts). */
20330 ldconst = "fconsts";
4ef4710f 20331 encode_fconstd:
58ed5c38
TC		 20332 if (!inst.operands[1].immisfloat)
20333 {
4ef4710f 20334 unsigned new_imm;
58ed5c38 20335 /* Immediate has to fit in 8 bits so float is enough. */
4ef4710f
NC		 20336 float imm = (float) inst.operands[1].imm;
20337 memcpy (&new_imm, &imm, sizeof (float));
20338 /* But the assembly may have been written to provide an integer
20339 bit pattern that equates to a float, so check that the
20340 conversion has worked. */
20341 if (is_quarter_float (new_imm))
20342 {
20343 if (is_quarter_float (inst.operands[1].imm))
20344 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
20345
20346 inst.operands[1].imm = new_imm;
20347 inst.operands[1].immisfloat = 1;
20348 }
58ed5c38
TC		 20349 }
20350
037e8744 20351 if (is_quarter_float (inst.operands[1].imm))
477330fc
RM		 20352 {
20353 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
20354 do_vfp_nsyn_opcode (ldconst);
9db2f6b4
RL		 20355
20356 /* ARMv8.2 fp16 vmov.f16 instruction. */
20357 if (rs == NS_HI)
20358 do_scalar_fp16_v82_encode ();
477330fc 20359 }
5287ad62 20360 else
477330fc 20361 first_error (_("immediate out of range"));
037e8744 20362 break;
5f4273c7 20363
9db2f6b4 20364 case NS_RH:
037e8744
JB		 20365 case NS_RF: /* case 12 (fmrs). */
20366 do_vfp_nsyn_opcode ("fmrs");
9db2f6b4
RL		 20367 /* ARMv8.2 fp16 vmov.f16 instruction. */
20368 if (rs == NS_RH)
20369 do_scalar_fp16_v82_encode ();
037e8744 20370 break;
5f4273c7 20371
9db2f6b4 20372 case NS_HR:
037e8744
JB		 20373 case NS_FR: /* case 13 (fmsr). */
20374 do_vfp_nsyn_opcode ("fmsr");
9db2f6b4
RL		 20375 /* ARMv8.2 fp16 vmov.f16 instruction. */
20376 if (rs == NS_HR)
20377 do_scalar_fp16_v82_encode ();
037e8744 20378 break;
5f4273c7 20379
57785aa2
AV		 20380 case NS_RRSS:
20381 do_mve_mov (0);
20382 break;
20383 case NS_SSRR:
20384 do_mve_mov (1);
20385 break;
20386
037e8744
JB		 20387 /* The encoders for the fmrrs and fmsrr instructions expect three operands
20388 (one of which is a list), but we have parsed four. Do some fiddling to
20389 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
20390 expect. */
20391 case NS_RRFF: /* case 14 (fmrrs). */
57785aa2
AV		 20392 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
20393 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
20394 _(BAD_FPU));
037e8744 20395 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
477330fc 20396 _("VFP registers must be adjacent"));
037e8744
JB		 20397 inst.operands[2].imm = 2;
20398 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
20399 do_vfp_nsyn_opcode ("fmrrs");
20400 break;
5f4273c7 20401
037e8744 20402 case NS_FFRR: /* case 15 (fmsrr). */
57785aa2
AV		 20403 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
20404 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
20405 _(BAD_FPU));
037e8744 20406 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
477330fc 20407 _("VFP registers must be adjacent"));
037e8744
JB		 20408 inst.operands[1] = inst.operands[2];
20409 inst.operands[2] = inst.operands[3];
20410 inst.operands[0].imm = 2;
20411 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
20412 do_vfp_nsyn_opcode ("fmsrr");
5287ad62 20413 break;
5f4273c7 20414
4c261dff
NC		 20415 case NS_NULL:
20416 /* neon_select_shape has determined that the instruction
20417 shape is wrong and has already set the error message. */
20418 break;
20419
5287ad62
JB		 20420 default:
20421 abort ();
20422 }
20423}
20424
57785aa2
AV		 20425static void
20426do_mve_movl (void)
20427{
20428 if (!(inst.operands[0].present && inst.operands[0].isquad
20429 && inst.operands[1].present && inst.operands[1].isquad
20430 && !inst.operands[2].present))
20431 {
20432 inst.instruction = 0;
20433 inst.cond = 0xb;
20434 if (thumb_mode)
20435 set_pred_insn_type (INSIDE_IT_INSN);
20436 do_neon_mov ();
20437 return;
20438 }
20439
20440 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20441 return;
20442
20443 if (inst.cond != COND_ALWAYS)
20444 inst.pred_insn_type = INSIDE_VPT_INSN;
20445
20446 struct neon_type_el et = neon_check_type (2, NS_QQ, N_EQK, N_S8 | N_U8
20447 | N_S16 | N_U16 | N_KEY);
20448
20449 inst.instruction |= (et.type == NT_unsigned) << 28;
20450 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20451 inst.instruction |= (neon_logbits (et.size) + 1) << 19;
20452 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20453 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
20454 inst.instruction |= LOW4 (inst.operands[1].reg);
20455 inst.is_neon = 1;
20456}
20457
5287ad62
JB		 20458static void
20459do_neon_rshift_round_imm (void)
20460{
64c350f2 20461 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
4401c241
AV		 20462 return;
20463
20464 enum neon_shape rs;
20465 struct neon_type_el et;
20466
20467 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20468 {
20469 rs = neon_select_shape (NS_QQI, NS_NULL);
20470 et = neon_check_type (2, rs, N_EQK, N_SU_MVE | N_KEY);
20471 }
20472 else
20473 {
20474 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
20475 et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
20476 }
5287ad62
JB		 20477 int imm = inst.operands[2].imm;
20478
20479 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
20480 if (imm == 0)
20481 {
20482 inst.operands[2].present = 0;
20483 do_neon_mov ();
20484 return;
20485 }
20486
20487 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 20488 _("immediate out of range for shift"));
037e8744 20489 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
477330fc 20490 et.size - imm);
5287ad62
JB		 20491}
20492
9db2f6b4
RL		 20493static void
20494do_neon_movhf (void)
20495{
20496 enum neon_shape rs = neon_select_shape (NS_HH, NS_NULL);
20497 constraint (rs != NS_HH, _("invalid suffix"));
20498
7bdf778b
ASDV		 20499 if (inst.cond != COND_ALWAYS)
20500 {
20501 if (thumb_mode)
20502 {
20503 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
20504 " the behaviour is UNPREDICTABLE"));
20505 }
20506 else
20507 {
20508 inst.error = BAD_COND;
20509 return;
20510 }
20511 }
20512
9db2f6b4
RL		 20513 do_vfp_sp_monadic ();
20514
20515 inst.is_neon = 1;
20516 inst.instruction |= 0xf0000000;
20517}
20518
5287ad62
JB		 20519static void
20520do_neon_movl (void)
20521{
20522 struct neon_type_el et = neon_check_type (2, NS_QD,
20523 N_EQK | N_DBL, N_SU_32 | N_KEY);
20524 unsigned sizebits = et.size >> 3;
20525 inst.instruction |= sizebits << 19;
20526 neon_two_same (0, et.type == NT_unsigned, -1);
20527}
20528
20529static void
20530do_neon_trn (void)
20531{
037e8744 20532 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 20533 struct neon_type_el et = neon_check_type (2, rs,
20534 N_EQK, N_8 | N_16 | N_32 | N_KEY);
88714cb8 20535 NEON_ENCODE (INTEGER, inst);
037e8744 20536 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 20537}
20538
20539static void
20540do_neon_zip_uzp (void)
20541{
037e8744 20542 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 20543 struct neon_type_el et = neon_check_type (2, rs,
20544 N_EQK, N_8 | N_16 | N_32 | N_KEY);
20545 if (rs == NS_DD && et.size == 32)
20546 {
20547 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
20548 inst.instruction = N_MNEM_vtrn;
20549 do_neon_trn ();
20550 return;
20551 }
037e8744 20552 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 20553}
20554
20555static void
20556do_neon_sat_abs_neg (void)
20557{
64c350f2 20558 if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
1a186d29
AV		 20559 return;
20560
20561 enum neon_shape rs;
20562 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20563 rs = neon_select_shape (NS_QQ, NS_NULL);
20564 else
20565 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 20566 struct neon_type_el et = neon_check_type (2, rs,
20567 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
037e8744 20568 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 20569}
20570
20571static void
20572do_neon_pair_long (void)
20573{
037e8744 20574 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 20575 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
20576 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
20577 inst.instruction |= (et.type == NT_unsigned) << 7;
037e8744 20578 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 20579}
20580
20581static void
20582do_neon_recip_est (void)
20583{
037e8744 20584 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62 20585 struct neon_type_el et = neon_check_type (2, rs,
cc933301 20586 N_EQK | N_FLT, N_F_16_32 | N_U32 | N_KEY);
5287ad62 20587 inst.instruction |= (et.type == NT_float) << 8;
037e8744 20588 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 20589}
20590
20591static void
20592do_neon_cls (void)
20593{
64c350f2 20594 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
f30ee27c
AV		 20595 return;
20596
20597 enum neon_shape rs;
20598 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20599 rs = neon_select_shape (NS_QQ, NS_NULL);
20600 else
20601 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20602
5287ad62
JB		 20603 struct neon_type_el et = neon_check_type (2, rs,
20604 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
037e8744 20605 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 20606}
20607
20608static void
20609do_neon_clz (void)
20610{
64c350f2 20611 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
f30ee27c
AV		 20612 return;
20613
20614 enum neon_shape rs;
20615 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20616 rs = neon_select_shape (NS_QQ, NS_NULL);
20617 else
20618 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20619
5287ad62
JB		 20620 struct neon_type_el et = neon_check_type (2, rs,
20621 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
037e8744 20622 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 20623}
20624
20625static void
20626do_neon_cnt (void)
20627{
037e8744 20628 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 20629 struct neon_type_el et = neon_check_type (2, rs,
20630 N_EQK | N_INT, N_8 | N_KEY);
037e8744 20631 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 20632}
20633
20634static void
20635do_neon_swp (void)
20636{
037e8744
JB		 20637 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20638 neon_two_same (neon_quad (rs), 1, -1);
5287ad62
JB		 20639}
20640
20641static void
20642do_neon_tbl_tbx (void)
20643{
20644 unsigned listlenbits;
dcbf9037 20645 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
5f4273c7 20646
5287ad62
JB		 20647 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
20648 {
dcbf9037 20649 first_error (_("bad list length for table lookup"));
5287ad62
JB		 20650 return;
20651 }
5f4273c7 20652
5287ad62
JB		 20653 listlenbits = inst.operands[1].imm - 1;
20654 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20655 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20656 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
20657 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
20658 inst.instruction |= LOW4 (inst.operands[2].reg);
20659 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
20660 inst.instruction |= listlenbits << 8;
5f4273c7 20661
88714cb8 20662 neon_dp_fixup (&inst);
5287ad62
JB		 20663}
20664
20665static void
20666do_neon_ldm_stm (void)
20667{
ef8f595f
MI		 20668 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
20669 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
20670 _(BAD_FPU));
5287ad62
JB		 20671 /* P, U and L bits are part of bitmask. */
20672 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
20673 unsigned offsetbits = inst.operands[1].imm * 2;
20674
037e8744
JB		 20675 if (inst.operands[1].issingle)
20676 {
20677 do_vfp_nsyn_ldm_stm (is_dbmode);
20678 return;
20679 }
20680
5287ad62 20681 constraint (is_dbmode && !inst.operands[0].writeback,
477330fc 20682 _("writeback (!) must be used for VLDMDB and VSTMDB"));
5287ad62
JB		 20683
20684 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
477330fc
RM		 20685 _("register list must contain at least 1 and at most 16 "
20686 "registers"));
5287ad62
JB		 20687
20688 inst.instruction |= inst.operands[0].reg << 16;
20689 inst.instruction |= inst.operands[0].writeback << 21;
20690 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
20691 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
20692
20693 inst.instruction |= offsetbits;
5f4273c7 20694
037e8744 20695 do_vfp_cond_or_thumb ();
5287ad62
JB		 20696}
20697
ef8f595f
MI		 20698static void
20699do_vfp_nsyn_pop (void)
20700{
20701 nsyn_insert_sp ();
20702 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) {
20703 return do_vfp_nsyn_opcode ("vldm");
20704 }
20705
20706 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd),
20707 _(BAD_FPU));
20708
20709 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
20710 _("register list must contain at least 1 and at most 16 "
20711 "registers"));
20712
20713 if (inst.operands[1].issingle)
20714 do_vfp_nsyn_opcode ("fldmias");
20715 else
20716 do_vfp_nsyn_opcode ("fldmiad");
20717}
20718
20719static void
20720do_vfp_nsyn_push (void)
20721{
20722 nsyn_insert_sp ();
20723 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)) {
20724 return do_vfp_nsyn_opcode ("vstmdb");
20725 }
20726
20727 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd),
20728 _(BAD_FPU));
20729
20730 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
20731 _("register list must contain at least 1 and at most 16 "
20732 "registers"));
20733
20734 if (inst.operands[1].issingle)
20735 do_vfp_nsyn_opcode ("fstmdbs");
20736 else
20737 do_vfp_nsyn_opcode ("fstmdbd");
20738}
20739
20740
5287ad62
JB		 20741static void
20742do_neon_ldr_str (void)
20743{
5287ad62 20744 int is_ldr = (inst.instruction & (1 << 20)) != 0;
5f4273c7 20745
6844b2c2
MGD		 20746 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20747 And is UNPREDICTABLE in thumb mode. */
fa94de6b 20748 if (!is_ldr
6844b2c2 20749 && inst.operands[1].reg == REG_PC
ba86b375 20750 && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode))
6844b2c2 20751 {
94dcf8bf 20752 if (thumb_mode)
6844b2c2 20753 inst.error = _("Use of PC here is UNPREDICTABLE");
94dcf8bf 20754 else if (warn_on_deprecated)
5c3696f8 20755 as_tsktsk (_("Use of PC here is deprecated"));
6844b2c2
MGD		 20756 }
20757
037e8744
JB		 20758 if (inst.operands[0].issingle)
20759 {
cd2f129f 20760 if (is_ldr)
477330fc 20761 do_vfp_nsyn_opcode ("flds");
cd2f129f 20762 else
477330fc 20763 do_vfp_nsyn_opcode ("fsts");
9db2f6b4
RL		 20764
20765 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20766 if (inst.vectype.el[0].size == 16)
20767 do_scalar_fp16_v82_encode ();
5287ad62
JB		 20768 }
20769 else
5287ad62 20770 {
cd2f129f 20771 if (is_ldr)
477330fc 20772 do_vfp_nsyn_opcode ("fldd");
5287ad62 20773 else
477330fc 20774 do_vfp_nsyn_opcode ("fstd");
5287ad62 20775 }
5287ad62
JB		 20776}
20777
32c36c3c
AV		 20778static void
20779do_t_vldr_vstr_sysreg (void)
20780{
20781 int fp_vldr_bitno = 20, sysreg_vldr_bitno = 20;
20782 bfd_boolean is_vldr = ((inst.instruction & (1 << fp_vldr_bitno)) != 0);
20783
20784 /* Use of PC is UNPREDICTABLE. */
20785 if (inst.operands[1].reg == REG_PC)
20786 inst.error = _("Use of PC here is UNPREDICTABLE");
20787
20788 if (inst.operands[1].immisreg)
20789 inst.error = _("instruction does not accept register index");
20790
20791 if (!inst.operands[1].isreg)
20792 inst.error = _("instruction does not accept PC-relative addressing");
20793
20794 if (abs (inst.operands[1].imm) >= (1 << 7))
20795 inst.error = _("immediate value out of range");
20796
20797 inst.instruction = 0xec000f80;
20798 if (is_vldr)
20799 inst.instruction |= 1 << sysreg_vldr_bitno;
20800 encode_arm_cp_address (1, TRUE, FALSE, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM);
20801 inst.instruction |= (inst.operands[0].imm & 0x7) << 13;
20802 inst.instruction |= (inst.operands[0].imm & 0x8) << 19;
20803}
20804
20805static void
20806do_vldr_vstr (void)
20807{
20808 bfd_boolean sysreg_op = !inst.operands[0].isreg;
20809
20810 /* VLDR/VSTR (System Register). */
20811 if (sysreg_op)
20812 {
20813 if (!mark_feature_used (&arm_ext_v8_1m_main))
20814 as_bad (_("Instruction not permitted on this architecture"));
20815
20816 do_t_vldr_vstr_sysreg ();
20817 }
20818 /* VLDR/VSTR. */
20819 else
20820 {
ef8f595f
MI		 20821 if (!mark_feature_used (&fpu_vfp_ext_v1xd)
20822 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
32c36c3c
AV		 20823 as_bad (_("Instruction not permitted on this architecture"));
20824 do_neon_ldr_str ();
20825 }
20826}
20827
5287ad62
JB		 20828/* "interleave" version also handles non-interleaving register VLD1/VST1
20829 instructions. */
20830
20831static void
20832do_neon_ld_st_interleave (void)
20833{
037e8744 20834 struct neon_type_el et = neon_check_type (1, NS_NULL,
477330fc 20835 N_8 | N_16 | N_32 | N_64);
5287ad62
JB		 20836 unsigned alignbits = 0;
20837 unsigned idx;
20838 /* The bits in this table go:
20839 0: register stride of one (0) or two (1)
20840 1,2: register list length, minus one (1, 2, 3, 4).
20841 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20842 We use -1 for invalid entries. */
20843 const int typetable[] =
20844 {
20845 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20846 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20847 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20848 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20849 };
20850 int typebits;
20851
dcbf9037
JB		 20852 if (et.type == NT_invtype)
20853 return;
20854
5287ad62
JB		 20855 if (inst.operands[1].immisalign)
20856 switch (inst.operands[1].imm >> 8)
20857 {
20858 case 64: alignbits = 1; break;
20859 case 128:
477330fc 20860 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
e23c0ad8 20861 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
477330fc
RM		 20862 goto bad_alignment;
20863 alignbits = 2;
20864 break;
5287ad62 20865 case 256:
477330fc
RM		 20866 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
20867 goto bad_alignment;
20868 alignbits = 3;
20869 break;
5287ad62
JB		 20870 default:
20871 bad_alignment:
477330fc
RM		 20872 first_error (_("bad alignment"));
20873 return;
5287ad62
JB		 20874 }
20875
20876 inst.instruction |= alignbits << 4;
20877 inst.instruction |= neon_logbits (et.size) << 6;
20878
20879 /* Bits [4:6] of the immediate in a list specifier encode register stride
20880 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20881 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20882 up the right value for "type" in a table based on this value and the given
20883 list style, then stick it back. */
20884 idx = ((inst.operands[0].imm >> 4) & 7)
477330fc 20885 | (((inst.instruction >> 8) & 3) << 3);
5287ad62
JB		 20886
20887 typebits = typetable[idx];
5f4273c7 20888
5287ad62 20889 constraint (typebits == -1, _("bad list type for instruction"));
1d50d57c 20890 constraint (((inst.instruction >> 8) & 3) && et.size == 64,
35c228db 20891 BAD_EL_TYPE);
5287ad62
JB		 20892
20893 inst.instruction &= ~0xf00;
20894 inst.instruction |= typebits << 8;
20895}
20896
20897/* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20898 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20899 otherwise. The variable arguments are a list of pairs of legal (size, align)
20900 values, terminated with -1. */
20901
20902static int
aa8a0863 20903neon_alignment_bit (int size, int align, int *do_alignment, ...)
5287ad62
JB		 20904{
20905 va_list ap;
20906 int result = FAIL, thissize, thisalign;
5f4273c7 20907
5287ad62
JB		 20908 if (!inst.operands[1].immisalign)
20909 {
aa8a0863 20910 *do_alignment = 0;
5287ad62
JB		 20911 return SUCCESS;
20912 }
5f4273c7 20913
aa8a0863 20914 va_start (ap, do_alignment);
5287ad62
JB		 20915
20916 do
20917 {
20918 thissize = va_arg (ap, int);
20919 if (thissize == -1)
477330fc 20920 break;
5287ad62
JB		 20921 thisalign = va_arg (ap, int);
20922
20923 if (size == thissize && align == thisalign)
477330fc 20924 result = SUCCESS;
5287ad62
JB		 20925 }
20926 while (result != SUCCESS);
20927
20928 va_end (ap);
20929
20930 if (result == SUCCESS)
aa8a0863 20931 *do_alignment = 1;
5287ad62 20932 else
dcbf9037 20933 first_error (_("unsupported alignment for instruction"));
5f4273c7 20934
5287ad62
JB		 20935 return result;
20936}
20937
20938static void
20939do_neon_ld_st_lane (void)
20940{
037e8744 20941 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
aa8a0863 20942 int align_good, do_alignment = 0;
5287ad62
JB		 20943 int logsize = neon_logbits (et.size);
20944 int align = inst.operands[1].imm >> 8;
20945 int n = (inst.instruction >> 8) & 3;
20946 int max_el = 64 / et.size;
5f4273c7 20947
dcbf9037
JB		 20948 if (et.type == NT_invtype)
20949 return;
5f4273c7 20950
5287ad62 20951 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
477330fc 20952 _("bad list length"));
5287ad62 20953 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
477330fc 20954 _("scalar index out of range"));
5287ad62 20955 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
477330fc
RM		 20956 && et.size == 8,
20957 _("stride of 2 unavailable when element size is 8"));
5f4273c7 20958
5287ad62
JB		 20959 switch (n)
20960 {
20961 case 0: /* VLD1 / VST1. */
aa8a0863 20962 align_good = neon_alignment_bit (et.size, align, &do_alignment, 16, 16,
477330fc 20963 32, 32, -1);
5287ad62 20964 if (align_good == FAIL)
477330fc 20965 return;
aa8a0863 20966 if (do_alignment)
477330fc
RM		 20967 {
20968 unsigned alignbits = 0;
20969 switch (et.size)
20970 {
20971 case 16: alignbits = 0x1; break;
20972 case 32: alignbits = 0x3; break;
20973 default: ;
20974 }
20975 inst.instruction |= alignbits << 4;
20976 }
5287ad62
JB		 20977 break;
20978
20979 case 1: /* VLD2 / VST2. */
aa8a0863
TS		 20980 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 16,
20981 16, 32, 32, 64, -1);
5287ad62 20982 if (align_good == FAIL)
477330fc 20983 return;
aa8a0863 20984 if (do_alignment)
477330fc 20985 inst.instruction |= 1 << 4;
5287ad62
JB		 20986 break;
20987
20988 case 2: /* VLD3 / VST3. */
20989 constraint (inst.operands[1].immisalign,
477330fc 20990 _("can't use alignment with this instruction"));
5287ad62
JB		 20991 break;
20992
20993 case 3: /* VLD4 / VST4. */
aa8a0863 20994 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32,
477330fc 20995 16, 64, 32, 64, 32, 128, -1);
5287ad62 20996 if (align_good == FAIL)
477330fc 20997 return;
aa8a0863 20998 if (do_alignment)
477330fc
RM		 20999 {
21000 unsigned alignbits = 0;
21001 switch (et.size)
21002 {
21003 case 8: alignbits = 0x1; break;
21004 case 16: alignbits = 0x1; break;
21005 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
21006 default: ;
21007 }
21008 inst.instruction |= alignbits << 4;
21009 }
5287ad62
JB		 21010 break;
21011
21012 default: ;
21013 }
21014
21015 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
21016 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
21017 inst.instruction |= 1 << (4 + logsize);
5f4273c7 21018
5287ad62
JB		 21019 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
21020 inst.instruction |= logsize << 10;
21021}
21022
21023/* Encode single n-element structure to all lanes VLD<n> instructions. */
21024
21025static void
21026do_neon_ld_dup (void)
21027{
037e8744 21028 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
aa8a0863 21029 int align_good, do_alignment = 0;
5287ad62 21030
dcbf9037
JB		 21031 if (et.type == NT_invtype)
21032 return;
21033
5287ad62
JB		 21034 switch ((inst.instruction >> 8) & 3)
21035 {
21036 case 0: /* VLD1. */
9c2799c2 21037 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
5287ad62 21038 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
aa8a0863 21039 &do_alignment, 16, 16, 32, 32, -1);
5287ad62 21040 if (align_good == FAIL)
477330fc 21041 return;
5287ad62 21042 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
477330fc
RM		 21043 {
21044 case 1: break;
21045 case 2: inst.instruction |= 1 << 5; break;
21046 default: first_error (_("bad list length")); return;
21047 }
5287ad62
JB		 21048 inst.instruction |= neon_logbits (et.size) << 6;
21049 break;
21050
21051 case 1: /* VLD2. */
21052 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
aa8a0863
TS		 21053 &do_alignment, 8, 16, 16, 32, 32, 64,
21054 -1);
5287ad62 21055 if (align_good == FAIL)
477330fc 21056 return;
5287ad62 21057 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
477330fc 21058 _("bad list length"));
5287ad62 21059 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
477330fc 21060 inst.instruction |= 1 << 5;
5287ad62
JB		 21061 inst.instruction |= neon_logbits (et.size) << 6;
21062 break;
21063
21064 case 2: /* VLD3. */
21065 constraint (inst.operands[1].immisalign,
477330fc 21066 _("can't use alignment with this instruction"));
5287ad62 21067 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
477330fc 21068 _("bad list length"));
5287ad62 21069 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
477330fc 21070 inst.instruction |= 1 << 5;
5287ad62
JB		 21071 inst.instruction |= neon_logbits (et.size) << 6;
21072 break;
21073
21074 case 3: /* VLD4. */
21075 {
477330fc 21076 int align = inst.operands[1].imm >> 8;
aa8a0863 21077 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32,
477330fc
RM		 21078 16, 64, 32, 64, 32, 128, -1);
21079 if (align_good == FAIL)
21080 return;
21081 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
21082 _("bad list length"));
21083 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
21084 inst.instruction |= 1 << 5;
21085 if (et.size == 32 && align == 128)
21086 inst.instruction |= 0x3 << 6;
21087 else
21088 inst.instruction |= neon_logbits (et.size) << 6;
5287ad62
JB		 21089 }
21090 break;
21091
21092 default: ;
21093 }
21094
aa8a0863 21095 inst.instruction |= do_alignment << 4;
5287ad62
JB		 21096}
21097
21098/* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
21099 apart from bits [11:4]. */
21100
21101static void
21102do_neon_ldx_stx (void)
21103{
b1a769ed
DG		 21104 if (inst.operands[1].isreg)
21105 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
21106
5287ad62
JB		 21107 switch (NEON_LANE (inst.operands[0].imm))
21108 {
21109 case NEON_INTERLEAVE_LANES:
88714cb8 21110 NEON_ENCODE (INTERLV, inst);
5287ad62
JB		 21111 do_neon_ld_st_interleave ();
21112 break;
5f4273c7 21113
5287ad62 21114 case NEON_ALL_LANES:
88714cb8 21115 NEON_ENCODE (DUP, inst);
2d51fb74
JB		 21116 if (inst.instruction == N_INV)
21117 {
21118 first_error ("only loads support such operands");
21119 break;
21120 }
5287ad62
JB		 21121 do_neon_ld_dup ();
21122 break;
5f4273c7 21123
5287ad62 21124 default:
88714cb8 21125 NEON_ENCODE (LANE, inst);
5287ad62
JB		 21126 do_neon_ld_st_lane ();
21127 }
21128
21129 /* L bit comes from bit mask. */
21130 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21131 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21132 inst.instruction |= inst.operands[1].reg << 16;
5f4273c7 21133
5287ad62
JB		 21134 if (inst.operands[1].postind)
21135 {
21136 int postreg = inst.operands[1].imm & 0xf;
21137 constraint (!inst.operands[1].immisreg,
477330fc 21138 _("post-index must be a register"));
5287ad62 21139 constraint (postreg == 0xd || postreg == 0xf,
477330fc 21140 _("bad register for post-index"));
5287ad62
JB		 21141 inst.instruction |= postreg;
21142 }
4f2374c7 21143 else
5287ad62 21144 {
4f2374c7 21145 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
e2b0ab59
AV		 21146 constraint (inst.relocs[0].exp.X_op != O_constant
21147 || inst.relocs[0].exp.X_add_number != 0,
4f2374c7
WN		 21148 BAD_ADDR_MODE);
21149
21150 if (inst.operands[1].writeback)
21151 {
21152 inst.instruction |= 0xd;
21153 }
21154 else
21155 inst.instruction |= 0xf;
5287ad62 21156 }
5f4273c7 21157
5287ad62
JB		 21158 if (thumb_mode)
21159 inst.instruction |= 0xf9000000;
21160 else
21161 inst.instruction |= 0xf4000000;
21162}
33399f07
MGD		 21163
21164/* FP v8. */
21165static void
21166do_vfp_nsyn_fpv8 (enum neon_shape rs)
21167{
a715796b
TG		 21168 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21169 D register operands. */
21170 if (neon_shape_class[rs] == SC_DOUBLE)
21171 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
21172 _(BAD_FPU));
21173
33399f07
MGD		 21174 NEON_ENCODE (FPV8, inst);
21175
9db2f6b4
RL		 21176 if (rs == NS_FFF || rs == NS_HHH)
21177 {
21178 do_vfp_sp_dyadic ();
21179
21180 /* ARMv8.2 fp16 instruction. */
21181 if (rs == NS_HHH)
21182 do_scalar_fp16_v82_encode ();
21183 }
33399f07
MGD		 21184 else
21185 do_vfp_dp_rd_rn_rm ();
21186
21187 if (rs == NS_DDD)
21188 inst.instruction |= 0x100;
21189
21190 inst.instruction |= 0xf0000000;
21191}
21192
21193static void
21194do_vsel (void)
21195{
5ee91343 21196 set_pred_insn_type (OUTSIDE_PRED_INSN);
33399f07
MGD		 21197
21198 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
21199 first_error (_("invalid instruction shape"));
21200}
21201
73924fbc
MGD		 21202static void
21203do_vmaxnm (void)
21204{
935295b5
AV		 21205 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
21206 set_pred_insn_type (OUTSIDE_PRED_INSN);
73924fbc
MGD		 21207
21208 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
21209 return;
21210
64c350f2 21211 if (!check_simd_pred_availability (TRUE, NEON_CHECK_CC | NEON_CHECK_ARCH8))
73924fbc
MGD		 21212 return;
21213
cc933301 21214 neon_dyadic_misc (NT_untyped, N_F_16_32, 0);
73924fbc
MGD		 21215}
21216
30bdf752
MGD		 21217static void
21218do_vrint_1 (enum neon_cvt_mode mode)
21219{
9db2f6b4 21220 enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_QQ, NS_NULL);
30bdf752
MGD		 21221 struct neon_type_el et;
21222
21223 if (rs == NS_NULL)
21224 return;
21225
a715796b
TG		 21226 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21227 D register operands. */
21228 if (neon_shape_class[rs] == SC_DOUBLE)
21229 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
21230 _(BAD_FPU));
21231
9db2f6b4
RL		 21232 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY
21233 | N_VFP);
30bdf752
MGD		 21234 if (et.type != NT_invtype)
21235 {
21236 /* VFP encodings. */
21237 if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
21238 || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m)
5ee91343 21239 set_pred_insn_type (OUTSIDE_PRED_INSN);
30bdf752
MGD		 21240
21241 NEON_ENCODE (FPV8, inst);
9db2f6b4 21242 if (rs == NS_FF || rs == NS_HH)
30bdf752
MGD		 21243 do_vfp_sp_monadic ();
21244 else
21245 do_vfp_dp_rd_rm ();
21246
21247 switch (mode)
21248 {
21249 case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
21250 case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
21251 case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
21252 case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
21253 case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
21254 case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
21255 case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
21256 default: abort ();
21257 }
21258
21259 inst.instruction |= (rs == NS_DD) << 8;
21260 do_vfp_cond_or_thumb ();
9db2f6b4
RL		 21261
21262 /* ARMv8.2 fp16 vrint instruction. */
21263 if (rs == NS_HH)
21264 do_scalar_fp16_v82_encode ();
30bdf752
MGD		 21265 }
21266 else
21267 {
21268 /* Neon encodings (or something broken...). */
21269 inst.error = NULL;
cc933301 21270 et = neon_check_type (2, rs, N_EQK, N_F_16_32 | N_KEY);
30bdf752
MGD		 21271
21272 if (et.type == NT_invtype)
21273 return;
21274
64c350f2
AV		 21275 if (!check_simd_pred_availability (TRUE,
21276 NEON_CHECK_CC | NEON_CHECK_ARCH8))
30bdf752
MGD		 21277 return;
21278
a710b305
AV		 21279 NEON_ENCODE (FLOAT, inst);
21280
30bdf752
MGD		 21281 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21282 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21283 inst.instruction |= LOW4 (inst.operands[1].reg);
21284 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
21285 inst.instruction |= neon_quad (rs) << 6;
cc933301
JW		 21286 /* Mask off the original size bits and reencode them. */
21287 inst.instruction = ((inst.instruction & 0xfff3ffff)
21288 | neon_logbits (et.size) << 18);
21289
30bdf752
MGD		 21290 switch (mode)
21291 {
21292 case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
21293 case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
21294 case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
21295 case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
21296 case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
21297 case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
21298 case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
21299 default: abort ();
21300 }
21301
21302 if (thumb_mode)
21303 inst.instruction |= 0xfc000000;
21304 else
21305 inst.instruction |= 0xf0000000;
21306 }
21307}
21308
21309static void
21310do_vrintx (void)
21311{
21312 do_vrint_1 (neon_cvt_mode_x);
21313}
21314
21315static void
21316do_vrintz (void)
21317{
21318 do_vrint_1 (neon_cvt_mode_z);
21319}
21320
21321static void
21322do_vrintr (void)
21323{
21324 do_vrint_1 (neon_cvt_mode_r);
21325}
21326
21327static void
21328do_vrinta (void)
21329{
21330 do_vrint_1 (neon_cvt_mode_a);
21331}
21332
21333static void
21334do_vrintn (void)
21335{
21336 do_vrint_1 (neon_cvt_mode_n);
21337}
21338
21339static void
21340do_vrintp (void)
21341{
21342 do_vrint_1 (neon_cvt_mode_p);
21343}
21344
21345static void
21346do_vrintm (void)
21347{
21348 do_vrint_1 (neon_cvt_mode_m);
21349}
21350
c28eeff2
SN		 21351static unsigned
21352neon_scalar_for_vcmla (unsigned opnd, unsigned elsize)
21353{
21354 unsigned regno = NEON_SCALAR_REG (opnd);
21355 unsigned elno = NEON_SCALAR_INDEX (opnd);
21356
21357 if (elsize == 16 && elno < 2 && regno < 16)
21358 return regno | (elno << 4);
21359 else if (elsize == 32 && elno == 0)
21360 return regno;
21361
21362 first_error (_("scalar out of range"));
21363 return 0;
21364}
21365
21366static void
21367do_vcmla (void)
21368{
5d281bf0
AV		 21369 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)
21370 && (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8)
21371 || !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU));
e2b0ab59
AV		 21372 constraint (inst.relocs[0].exp.X_op != O_constant,
21373 _("expression too complex"));
21374 unsigned rot = inst.relocs[0].exp.X_add_number;
c28eeff2
SN		 21375 constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,
21376 _("immediate out of range"));
21377 rot /= 90;
5d281bf0 21378
64c350f2
AV		 21379 if (!check_simd_pred_availability (TRUE,
21380 NEON_CHECK_ARCH8 | NEON_CHECK_CC))
5d281bf0
AV		 21381 return;
21382
c28eeff2
SN		 21383 if (inst.operands[2].isscalar)
21384 {
5d281bf0
AV		 21385 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
21386 first_error (_("invalid instruction shape"));
c28eeff2
SN		 21387 enum neon_shape rs = neon_select_shape (NS_DDSI, NS_QQSI, NS_NULL);
21388 unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
21389 N_KEY | N_F16 | N_F32).size;
21390 unsigned m = neon_scalar_for_vcmla (inst.operands[2].reg, size);
21391 inst.is_neon = 1;
21392 inst.instruction = 0xfe000800;
21393 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21394 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21395 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
21396 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
21397 inst.instruction |= LOW4 (m);
21398 inst.instruction |= HI1 (m) << 5;
21399 inst.instruction |= neon_quad (rs) << 6;
21400 inst.instruction |= rot << 20;
21401 inst.instruction |= (size == 32) << 23;
21402 }
21403 else
21404 {
5d281bf0
AV		 21405 enum neon_shape rs;
21406 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
21407 rs = neon_select_shape (NS_QQQI, NS_NULL);
21408 else
21409 rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
21410
c28eeff2
SN		 21411 unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
21412 N_KEY | N_F16 | N_F32).size;
5d281bf0
AV		 21413 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext) && size == 32
21414 && (inst.operands[0].reg == inst.operands[1].reg
21415 || inst.operands[0].reg == inst.operands[2].reg))
21416 as_tsktsk (BAD_MVE_SRCDEST);
21417
c28eeff2
SN		 21418 neon_three_same (neon_quad (rs), 0, -1);
21419 inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
21420 inst.instruction |= 0xfc200800;
21421 inst.instruction |= rot << 23;
21422 inst.instruction |= (size == 32) << 20;
21423 }
21424}
21425
21426static void
21427do_vcadd (void)
21428{
5d281bf0
AV		 21429 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
21430 && (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8)
21431 || !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU));
e2b0ab59
AV		 21432 constraint (inst.relocs[0].exp.X_op != O_constant,
21433 _("expression too complex"));
5d281bf0 21434
e2b0ab59 21435 unsigned rot = inst.relocs[0].exp.X_add_number;
c28eeff2 21436 constraint (rot != 90 && rot != 270, _("immediate out of range"));
5d281bf0
AV		 21437 enum neon_shape rs;
21438 struct neon_type_el et;
21439 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
21440 {
21441 rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
21442 et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32);
21443 }
21444 else
21445 {
21446 rs = neon_select_shape (NS_QQQI, NS_NULL);
21447 et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32 | N_I8
21448 | N_I16 | N_I32);
21449 if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg)
21450 as_tsktsk (_("Warning: 32-bit element size and same first and third "
21451 "operand makes instruction UNPREDICTABLE"));
21452 }
21453
21454 if (et.type == NT_invtype)
21455 return;
21456
64c350f2
AV		 21457 if (!check_simd_pred_availability (et.type == NT_float,
21458 NEON_CHECK_ARCH8 | NEON_CHECK_CC))
5d281bf0
AV		 21459 return;
21460
21461 if (et.type == NT_float)
21462 {
21463 neon_three_same (neon_quad (rs), 0, -1);
21464 inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
21465 inst.instruction |= 0xfc800800;
21466 inst.instruction |= (rot == 270) << 24;
21467 inst.instruction |= (et.size == 32) << 20;
21468 }
21469 else
21470 {
21471 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
21472 inst.instruction = 0xfe000f00;
21473 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21474 inst.instruction |= neon_logbits (et.size) << 20;
21475 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
21476 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21477 inst.instruction |= (rot == 270) << 12;
21478 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
21479 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
21480 inst.instruction |= LOW4 (inst.operands[2].reg);
21481 inst.is_neon = 1;
21482 }
c28eeff2
SN		 21483}
21484
c604a79a
JW		 21485/* Dot Product instructions encoding support. */
21486
21487static void
21488do_neon_dotproduct (int unsigned_p)
21489{
21490 enum neon_shape rs;
21491 unsigned scalar_oprd2 = 0;
21492 int high8;
21493
21494 if (inst.cond != COND_ALWAYS)
21495 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
21496 "is UNPREDICTABLE"));
21497
21498 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
21499 _(BAD_FPU));
21500
21501 /* Dot Product instructions are in three-same D/Q register format or the third
21502 operand can be a scalar index register. */
21503 if (inst.operands[2].isscalar)
21504 {
21505 scalar_oprd2 = neon_scalar_for_mul (inst.operands[2].reg, 32);
21506 high8 = 0xfe000000;
21507 rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
21508 }
21509 else
21510 {
21511 high8 = 0xfc000000;
21512 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
21513 }
21514
21515 if (unsigned_p)
21516 neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_U8);
21517 else
21518 neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_S8);
21519
21520 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
21521 Product instruction, so we pass 0 as the "ubit" parameter. And the
21522 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
21523 neon_three_same (neon_quad (rs), 0, 32);
21524
21525 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
21526 different NEON three-same encoding. */
21527 inst.instruction &= 0x00ffffff;
21528 inst.instruction |= high8;
21529 /* Encode 'U' bit which indicates signedness. */
21530 inst.instruction |= (unsigned_p ? 1 : 0) << 4;
21531 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
21532 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
21533 the instruction encoding. */
21534 if (inst.operands[2].isscalar)
21535 {
21536 inst.instruction &= 0xffffffd0;
21537 inst.instruction |= LOW4 (scalar_oprd2);
21538 inst.instruction |= HI1 (scalar_oprd2) << 5;
21539 }
21540}
21541
21542/* Dot Product instructions for signed integer. */
21543
21544static void
21545do_neon_dotproduct_s (void)
21546{
21547 return do_neon_dotproduct (0);
21548}
21549
21550/* Dot Product instructions for unsigned integer. */
21551
21552static void
21553do_neon_dotproduct_u (void)
21554{
21555 return do_neon_dotproduct (1);
21556}
21557
616ce08e
MM		 21558static void
21559do_vusdot (void)
21560{
21561 enum neon_shape rs;
21562 set_pred_insn_type (OUTSIDE_PRED_INSN);
21563 if (inst.operands[2].isscalar)
21564 {
21565 rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
21566 neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_KEY);
21567
21568 inst.instruction |= (1 << 25);
21569 int index = inst.operands[2].reg & 0xf;
21570 constraint ((index != 1 && index != 0), _("index must be 0 or 1"));
21571 inst.operands[2].reg >>= 4;
21572 constraint (!(inst.operands[2].reg < 16),
21573 _("indexed register must be less than 16"));
21574 neon_three_args (rs == NS_QQS);
21575 inst.instruction |= (index << 5);
21576 }
21577 else
21578 {
21579 inst.instruction |= (1 << 21);
21580 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
21581 neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_KEY);
21582 neon_three_args (rs == NS_QQQ);
21583 }
21584}
21585
21586static void
21587do_vsudot (void)
21588{
21589 enum neon_shape rs;
21590 set_pred_insn_type (OUTSIDE_PRED_INSN);
21591 if (inst.operands[2].isscalar)
21592 {
21593 rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
21594 neon_check_type (3, rs, N_EQK, N_EQK, N_U8 | N_KEY);
21595
21596 inst.instruction |= (1 << 25);
21597 int index = inst.operands[2].reg & 0xf;
21598 constraint ((index != 1 && index != 0), _("index must be 0 or 1"));
21599 inst.operands[2].reg >>= 4;
21600 constraint (!(inst.operands[2].reg < 16),
21601 _("indexed register must be less than 16"));
21602 neon_three_args (rs == NS_QQS);
21603 inst.instruction |= (index << 5);
21604 }
21605}
21606
21607static void
21608do_vsmmla (void)
21609{
21610 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
21611 neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_KEY);
21612
21613 set_pred_insn_type (OUTSIDE_PRED_INSN);
21614
21615 neon_three_args (1);
21616
21617}
21618
21619static void
21620do_vummla (void)
21621{
21622 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
21623 neon_check_type (3, rs, N_EQK, N_EQK, N_U8 | N_KEY);
21624
21625 set_pred_insn_type (OUTSIDE_PRED_INSN);
21626
21627 neon_three_args (1);
21628
21629}
21630
4934a27c
MM		 21631static void
21632check_cde_operand (size_t index, int is_dual)
21633{
21634 unsigned Rx = inst.operands[index].reg;
21635 bfd_boolean isvec = inst.operands[index].isvec;
21636 if (is_dual == 0 && thumb_mode)
21637 constraint (
21638 !((Rx <= 14 && Rx != 13) || (Rx == REG_PC && isvec)),
21639 _("Register must be r0-r14 except r13, or APSR_nzcv."));
21640 else
21641 constraint ( !((Rx <= 10 && Rx % 2 == 0 )),
21642 _("Register must be an even register between r0-r10."));
21643}
21644
21645static bfd_boolean
21646cde_coproc_enabled (unsigned coproc)
21647{
21648 switch (coproc)
21649 {
21650 case 0: return mark_feature_used (&arm_ext_cde0);
21651 case 1: return mark_feature_used (&arm_ext_cde1);
21652 case 2: return mark_feature_used (&arm_ext_cde2);
21653 case 3: return mark_feature_used (&arm_ext_cde3);
21654 case 4: return mark_feature_used (&arm_ext_cde4);
21655 case 5: return mark_feature_used (&arm_ext_cde5);
21656 case 6: return mark_feature_used (&arm_ext_cde6);
21657 case 7: return mark_feature_used (&arm_ext_cde7);
21658 default: return FALSE;
21659 }
21660}
21661
21662#define cde_coproc_pos 8
21663static void
21664cde_handle_coproc (void)
21665{
21666 unsigned coproc = inst.operands[0].reg;
21667 constraint (coproc > 7, _("CDE Coprocessor must be in range 0-7"));
21668 constraint (!(cde_coproc_enabled (coproc)), BAD_CDE_COPROC);
21669 inst.instruction |= coproc << cde_coproc_pos;
21670}
21671#undef cde_coproc_pos
21672
21673static void
21674cxn_handle_predication (bfd_boolean is_accum)
21675{
cceb53b8
MM		 21676 if (is_accum && conditional_insn ())
21677 set_pred_insn_type (INSIDE_IT_INSN);
21678 else if (conditional_insn ())
21679 /* conditional_insn essentially checks for a suffix, not whether the
21680 instruction is inside an IT block or not.
21681 The non-accumulator versions should not have suffixes. */
4934a27c 21682 inst.error = BAD_SYNTAX;
4934a27c
MM		 21683 else
21684 set_pred_insn_type (OUTSIDE_PRED_INSN);
21685}
21686
21687static void
21688do_custom_instruction_1 (int is_dual, bfd_boolean is_accum)
21689{
21690
21691 constraint (!mark_feature_used (&arm_ext_cde), _(BAD_CDE));
21692
21693 unsigned imm, Rd;
21694
21695 Rd = inst.operands[1].reg;
21696 check_cde_operand (1, is_dual);
21697
21698 if (is_dual == 1)
21699 {
21700 constraint (inst.operands[2].reg != Rd + 1,
21701 _("cx1d requires consecutive destination registers."));
21702 imm = inst.operands[3].imm;
21703 }
21704 else if (is_dual == 0)
21705 imm = inst.operands[2].imm;
21706 else
21707 abort ();
21708
21709 inst.instruction |= Rd << 12;
21710 inst.instruction |= (imm & 0x1F80) << 9;
21711 inst.instruction |= (imm & 0x0040) << 1;
21712 inst.instruction |= (imm & 0x003f);
21713
21714 cde_handle_coproc ();
21715 cxn_handle_predication (is_accum);
21716}
21717
21718static void
21719do_custom_instruction_2 (int is_dual, bfd_boolean is_accum)
21720{
21721
21722 constraint (!mark_feature_used (&arm_ext_cde), _(BAD_CDE));
21723
21724 unsigned imm, Rd, Rn;
21725
21726 Rd = inst.operands[1].reg;
21727
21728 if (is_dual == 1)
21729 {
21730 constraint (inst.operands[2].reg != Rd + 1,
21731 _("cx2d requires consecutive destination registers."));
21732 imm = inst.operands[4].imm;
21733 Rn = inst.operands[3].reg;
21734 }
21735 else if (is_dual == 0)
21736 {
21737 imm = inst.operands[3].imm;
21738 Rn = inst.operands[2].reg;
21739 }
21740 else
21741 abort ();
21742
21743 check_cde_operand (2 + is_dual, /* is_dual = */0);
21744 check_cde_operand (1, is_dual);
21745
21746 inst.instruction |= Rd << 12;
21747 inst.instruction |= Rn << 16;
21748
21749 inst.instruction |= (imm & 0x0380) << 13;
21750 inst.instruction |= (imm & 0x0040) << 1;
21751 inst.instruction |= (imm & 0x003f);
21752
21753 cde_handle_coproc ();
21754 cxn_handle_predication (is_accum);
21755}
21756
21757static void
21758do_custom_instruction_3 (int is_dual, bfd_boolean is_accum)
21759{
21760
21761 constraint (!mark_feature_used (&arm_ext_cde), _(BAD_CDE));
21762
21763 unsigned imm, Rd, Rn, Rm;
21764
21765 Rd = inst.operands[1].reg;
21766
21767 if (is_dual == 1)
21768 {
21769 constraint (inst.operands[2].reg != Rd + 1,
21770 _("cx3d requires consecutive destination registers."));
21771 imm = inst.operands[5].imm;
21772 Rn = inst.operands[3].reg;
21773 Rm = inst.operands[4].reg;
21774 }
21775 else if (is_dual == 0)
21776 {
21777 imm = inst.operands[4].imm;
21778 Rn = inst.operands[2].reg;
21779 Rm = inst.operands[3].reg;
21780 }
21781 else
21782 abort ();
21783
21784 check_cde_operand (1, is_dual);
21785 check_cde_operand (2 + is_dual, /* is_dual = */0);
21786 check_cde_operand (3 + is_dual, /* is_dual = */0);
21787
21788 inst.instruction |= Rd;
21789 inst.instruction |= Rn << 16;
21790 inst.instruction |= Rm << 12;
21791
21792 inst.instruction |= (imm & 0x0038) << 17;
21793 inst.instruction |= (imm & 0x0004) << 5;
21794 inst.instruction |= (imm & 0x0003) << 4;
21795
21796 cde_handle_coproc ();
21797 cxn_handle_predication (is_accum);
21798}
21799
21800static void
21801do_cx1 (void)
21802{
21803 return do_custom_instruction_1 (0, 0);
21804}
21805
21806static void
21807do_cx1a (void)
21808{
21809 return do_custom_instruction_1 (0, 1);
21810}
21811
21812static void
21813do_cx1d (void)
21814{
21815 return do_custom_instruction_1 (1, 0);
21816}
21817
21818static void
21819do_cx1da (void)
21820{
21821 return do_custom_instruction_1 (1, 1);
21822}
21823
21824static void
21825do_cx2 (void)
21826{
21827 return do_custom_instruction_2 (0, 0);
21828}
21829
21830static void
21831do_cx2a (void)
21832{
21833 return do_custom_instruction_2 (0, 1);
21834}
21835
21836static void
21837do_cx2d (void)
21838{
21839 return do_custom_instruction_2 (1, 0);
21840}
21841
21842static void
21843do_cx2da (void)
21844{
21845 return do_custom_instruction_2 (1, 1);
21846}
21847
21848static void
21849do_cx3 (void)
21850{
21851 return do_custom_instruction_3 (0, 0);
21852}
21853
21854static void
21855do_cx3a (void)
21856{
21857 return do_custom_instruction_3 (0, 1);
21858}
21859
21860static void
21861do_cx3d (void)
21862{
21863 return do_custom_instruction_3 (1, 0);
21864}
21865
21866static void
21867do_cx3da (void)
21868{
21869 return do_custom_instruction_3 (1, 1);
21870}
21871
5aae9ae9
MM		 21872static void
21873vcx_assign_vec_d (unsigned regnum)
21874{
21875 inst.instruction |= HI4 (regnum) << 12;
21876 inst.instruction |= LOW1 (regnum) << 22;
21877}
21878
21879static void
21880vcx_assign_vec_m (unsigned regnum)
21881{
21882 inst.instruction |= HI4 (regnum);
21883 inst.instruction |= LOW1 (regnum) << 5;
21884}
21885
21886static void
21887vcx_assign_vec_n (unsigned regnum)
21888{
21889 inst.instruction |= HI4 (regnum) << 16;
21890 inst.instruction |= LOW1 (regnum) << 7;
21891}
21892
21893enum vcx_reg_type {
21894 q_reg,
21895 d_reg,
21896 s_reg
21897};
21898
21899static enum vcx_reg_type
21900vcx_get_reg_type (enum neon_shape ns)
21901{
21902 gas_assert (ns == NS_PQI
21903 || ns == NS_PDI
21904 || ns == NS_PFI
21905 || ns == NS_PQQI
21906 || ns == NS_PDDI
21907 || ns == NS_PFFI
21908 || ns == NS_PQQQI
21909 || ns == NS_PDDDI
21910 || ns == NS_PFFFI);
21911 if (ns == NS_PQI || ns == NS_PQQI || ns == NS_PQQQI)
21912 return q_reg;
21913 if (ns == NS_PDI || ns == NS_PDDI || ns == NS_PDDDI)
21914 return d_reg;
21915 return s_reg;
21916}
21917
21918#define vcx_size_pos 24
21919#define vcx_vec_pos 6
21920static unsigned
21921vcx_handle_shape (enum vcx_reg_type reg_type)
21922{
21923 unsigned mult = 2;
21924 if (reg_type == q_reg)
21925 inst.instruction |= 1 << vcx_vec_pos;
21926 else if (reg_type == d_reg)
21927 inst.instruction |= 1 << vcx_size_pos;
21928 else
21929 mult = 1;
21930 /* NOTE:
21931 The documentation says that the Q registers are encoded as 2*N in the D:Vd
21932 bits (or equivalent for N and M registers).
21933 Similarly the D registers are encoded as N in D:Vd bits.
21934 While the S registers are encoded as N in the Vd:D bits.
21935
21936 Taking into account the maximum values of these registers we can see a
21937 nicer pattern for calculation:
21938 Q -> 7, D -> 15, S -> 31
21939
21940 If we say that everything is encoded in the Vd:D bits, then we can say
21941 that Q is encoded as 4*N, and D is encoded as 2*N.
21942 This way the bits will end up the same, and calculation is simpler.
21943 (calculation is now:
21944 1. Multiply by a number determined by the register letter.
21945 2. Encode resulting number in Vd:D bits.)
21946
21947 This is made a little more complicated by automatic handling of 'Q'
21948 registers elsewhere, which means the register number is already 2*N where
21949 N is the number the user wrote after the register letter.
21950 */
21951 return mult;
21952}
21953#undef vcx_vec_pos
21954#undef vcx_size_pos
21955
21956static void
21957vcx_ensure_register_in_range (unsigned R, enum vcx_reg_type reg_type)
21958{
21959 if (reg_type == q_reg)
21960 {
21961 gas_assert (R % 2 == 0);
21962 constraint (R >= 16, _("'q' register must be in range 0-7"));
21963 }
21964 else if (reg_type == d_reg)
21965 constraint (R >= 16, _("'d' register must be in range 0-15"));
21966 else
21967 constraint (R >= 32, _("'s' register must be in range 0-31"));
21968}
21969
21970static void (*vcx_assign_vec[3]) (unsigned) = {
21971 vcx_assign_vec_d,
21972 vcx_assign_vec_m,
21973 vcx_assign_vec_n
21974};
21975
21976static void
21977vcx_handle_register_arguments (unsigned num_registers,
21978 enum vcx_reg_type reg_type)
21979{
1ed818b4 21980 unsigned R, i;
5aae9ae9 21981 unsigned reg_mult = vcx_handle_shape (reg_type);
1ed818b4 21982 for (i = 0; i < num_registers; i++)
5aae9ae9
MM		 21983 {
21984 R = inst.operands[i+1].reg;
21985 vcx_ensure_register_in_range (R, reg_type);
21986 if (num_registers == 3 && i > 0)
21987 {
21988 if (i == 2)
21989 vcx_assign_vec[1] (R * reg_mult);
21990 else
21991 vcx_assign_vec[2] (R * reg_mult);
21992 continue;
21993 }
21994 vcx_assign_vec[i](R * reg_mult);
21995 }
21996}
21997
21998static void
21999vcx_handle_insn_block (enum vcx_reg_type reg_type)
22000{
22001 if (reg_type == q_reg)
22002 if (inst.cond > COND_ALWAYS)
22003 inst.pred_insn_type = INSIDE_VPT_INSN;
22004 else
22005 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
22006 else if (inst.cond == COND_ALWAYS)
22007 inst.pred_insn_type = OUTSIDE_PRED_INSN;
22008 else
22009 inst.error = BAD_NOT_IT;
22010}
22011
22012static void
22013vcx_handle_common_checks (unsigned num_args, enum neon_shape rs)
22014{
22015 constraint (!mark_feature_used (&arm_ext_cde), _(BAD_CDE));
22016 cde_handle_coproc ();
22017 enum vcx_reg_type reg_type = vcx_get_reg_type (rs);
22018 vcx_handle_register_arguments (num_args, reg_type);
22019 vcx_handle_insn_block (reg_type);
22020 if (reg_type == q_reg)
22021 constraint (!mark_feature_used (&mve_ext),
22022 _("vcx instructions with Q registers require MVE"));
22023 else
22024 constraint (!(ARM_FSET_CPU_SUBSET (armv8m_fp, cpu_variant)
22025 && mark_feature_used (&armv8m_fp))
22026 && !mark_feature_used (&mve_ext),
22027 _("vcx instructions with S or D registers require either MVE"
22028 " or Armv8-M floating point etension."));
22029}
22030
22031static void
22032do_vcx1 (void)
22033{
22034 enum neon_shape rs = neon_select_shape (NS_PQI, NS_PDI, NS_PFI, NS_NULL);
22035 vcx_handle_common_checks (1, rs);
22036
22037 unsigned imm = inst.operands[2].imm;
22038 inst.instruction |= (imm & 0x03f);
22039 inst.instruction |= (imm & 0x040) << 1;
22040 inst.instruction |= (imm & 0x780) << 9;
22041 if (rs != NS_PQI)
22042 constraint (imm >= 2048,
22043 _("vcx1 with S or D registers takes immediate within 0-2047"));
22044 inst.instruction |= (imm & 0x800) << 13;
22045}
22046
22047static void
22048do_vcx2 (void)
22049{
22050 enum neon_shape rs = neon_select_shape (NS_PQQI, NS_PDDI, NS_PFFI, NS_NULL);
22051 vcx_handle_common_checks (2, rs);
22052
22053 unsigned imm = inst.operands[3].imm;
22054 inst.instruction |= (imm & 0x01) << 4;
22055 inst.instruction |= (imm & 0x02) << 6;
22056 inst.instruction |= (imm & 0x3c) << 14;
22057 if (rs != NS_PQQI)
22058 constraint (imm >= 64,
22059 _("vcx2 with S or D registers takes immediate within 0-63"));
22060 inst.instruction |= (imm & 0x40) << 18;
22061}
22062
22063static void
22064do_vcx3 (void)
22065{
22066 enum neon_shape rs = neon_select_shape (NS_PQQQI, NS_PDDDI, NS_PFFFI, NS_NULL);
22067 vcx_handle_common_checks (3, rs);
22068
22069 unsigned imm = inst.operands[4].imm;
22070 inst.instruction |= (imm & 0x1) << 4;
22071 inst.instruction |= (imm & 0x6) << 19;
22072 if (rs != NS_PQQQI)
22073 constraint (imm >= 8,
22074 _("vcx2 with S or D registers takes immediate within 0-7"));
22075 inst.instruction |= (imm & 0x8) << 21;
22076}
22077
91ff7894
MGD		 22078/* Crypto v1 instructions. */
22079static void
22080do_crypto_2op_1 (unsigned elttype, int op)
22081{
5ee91343 22082 set_pred_insn_type (OUTSIDE_PRED_INSN);
91ff7894
MGD		 22083
22084 if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type
22085 == NT_invtype)
22086 return;
22087
22088 inst.error = NULL;
22089
22090 NEON_ENCODE (INTEGER, inst);
22091 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
22092 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
22093 inst.instruction |= LOW4 (inst.operands[1].reg);
22094 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
22095 if (op != -1)
22096 inst.instruction |= op << 6;
22097
22098 if (thumb_mode)
22099 inst.instruction |= 0xfc000000;
22100 else
22101 inst.instruction |= 0xf0000000;
22102}
22103
48adcd8e
MGD		 22104static void
22105do_crypto_3op_1 (int u, int op)
22106{
5ee91343 22107 set_pred_insn_type (OUTSIDE_PRED_INSN);
48adcd8e
MGD		 22108
22109 if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
22110 N_32 | N_UNT | N_KEY).type == NT_invtype)
22111 return;
22112
22113 inst.error = NULL;
22114
22115 NEON_ENCODE (INTEGER, inst);
22116 neon_three_same (1, u, 8 << op);
22117}
22118
91ff7894
MGD		 22119static void
22120do_aese (void)
22121{
22122 do_crypto_2op_1 (N_8, 0);
22123}
22124
22125static void
22126do_aesd (void)
22127{
22128 do_crypto_2op_1 (N_8, 1);
22129}
22130
22131static void
22132do_aesmc (void)
22133{
22134 do_crypto_2op_1 (N_8, 2);
22135}
22136
22137static void
22138do_aesimc (void)
22139{
22140 do_crypto_2op_1 (N_8, 3);
22141}
22142
48adcd8e
MGD		 22143static void
22144do_sha1c (void)
22145{
22146 do_crypto_3op_1 (0, 0);
22147}
22148
22149static void
22150do_sha1p (void)
22151{
22152 do_crypto_3op_1 (0, 1);
22153}
22154
22155static void
22156do_sha1m (void)
22157{
22158 do_crypto_3op_1 (0, 2);
22159}
22160
22161static void
22162do_sha1su0 (void)
22163{
22164 do_crypto_3op_1 (0, 3);
22165}
91ff7894 22166
48adcd8e
MGD		 22167static void
22168do_sha256h (void)
22169{
22170 do_crypto_3op_1 (1, 0);
22171}
22172
22173static void
22174do_sha256h2 (void)
22175{
22176 do_crypto_3op_1 (1, 1);
22177}
22178
22179static void
22180do_sha256su1 (void)
22181{
22182 do_crypto_3op_1 (1, 2);
22183}
3c9017d2
MGD		 22184
22185static void
22186do_sha1h (void)
22187{
22188 do_crypto_2op_1 (N_32, -1);
22189}
22190
22191static void
22192do_sha1su1 (void)
22193{
22194 do_crypto_2op_1 (N_32, 0);
22195}
22196
22197static void
22198do_sha256su0 (void)
22199{
22200 do_crypto_2op_1 (N_32, 1);
22201}
dd5181d5
KT		 22202
22203static void
22204do_crc32_1 (unsigned int poly, unsigned int sz)
22205{
22206 unsigned int Rd = inst.operands[0].reg;
22207 unsigned int Rn = inst.operands[1].reg;
22208 unsigned int Rm = inst.operands[2].reg;
22209
5ee91343 22210 set_pred_insn_type (OUTSIDE_PRED_INSN);
dd5181d5
KT		 22211 inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12);
22212 inst.instruction |= LOW4 (Rn) << 16;
22213 inst.instruction |= LOW4 (Rm);
22214 inst.instruction |= sz << (thumb_mode ? 4 : 21);
22215 inst.instruction |= poly << (thumb_mode ? 20 : 9);
22216
22217 if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC)
22218 as_warn (UNPRED_REG ("r15"));
dd5181d5
KT		 22219}
22220
22221static void
22222do_crc32b (void)
22223{
22224 do_crc32_1 (0, 0);
22225}
22226
22227static void
22228do_crc32h (void)
22229{
22230 do_crc32_1 (0, 1);
22231}
22232
22233static void
22234do_crc32w (void)
22235{
22236 do_crc32_1 (0, 2);
22237}
22238
22239static void
22240do_crc32cb (void)
22241{
22242 do_crc32_1 (1, 0);
22243}
22244
22245static void
22246do_crc32ch (void)
22247{
22248 do_crc32_1 (1, 1);
22249}
22250
22251static void
22252do_crc32cw (void)
22253{
22254 do_crc32_1 (1, 2);
22255}
22256
49e8a725
SN		 22257static void
22258do_vjcvt (void)
22259{
22260 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
22261 _(BAD_FPU));
22262 neon_check_type (2, NS_FD, N_S32, N_F64);
22263 do_vfp_sp_dp_cvt ();
22264 do_vfp_cond_or_thumb ();
22265}
22266
aab2c27d
MM		 22267static void
22268do_vdot (void)
22269{
22270 enum neon_shape rs;
22271 constraint (!mark_feature_used (&fpu_neon_ext_armv8), _(BAD_FPU));
22272 set_pred_insn_type (OUTSIDE_PRED_INSN);
22273 if (inst.operands[2].isscalar)
22274 {
22275 rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
22276 neon_check_type (3, rs, N_EQK, N_EQK, N_BF16 | N_KEY);
22277
22278 inst.instruction |= (1 << 25);
22279 int index = inst.operands[2].reg & 0xf;
22280 constraint ((index != 1 && index != 0), _("index must be 0 or 1"));
22281 inst.operands[2].reg >>= 4;
22282 constraint (!(inst.operands[2].reg < 16),
22283 _("indexed register must be less than 16"));
22284 neon_three_args (rs == NS_QQS);
22285 inst.instruction |= (index << 5);
22286 }
22287 else
22288 {
22289 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
22290 neon_check_type (3, rs, N_EQK, N_EQK, N_BF16 | N_KEY);
22291 neon_three_args (rs == NS_QQQ);
22292 }
22293}
22294
22295static void
22296do_vmmla (void)
22297{
22298 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
22299 neon_check_type (3, rs, N_EQK, N_EQK, N_BF16 | N_KEY);
22300
22301 constraint (!mark_feature_used (&fpu_neon_ext_armv8), _(BAD_FPU));
22302 set_pred_insn_type (OUTSIDE_PRED_INSN);
22303
22304 neon_three_args (1);
22305}
22306
5287ad62
JB		 22307\f
22308/* Overall per-instruction processing. */
22309
22310/* We need to be able to fix up arbitrary expressions in some statements.
22311 This is so that we can handle symbols that are an arbitrary distance from
22312 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
22313 which returns part of an address in a form which will be valid for
22314 a data instruction. We do this by pushing the expression into a symbol
22315 in the expr_section, and creating a fix for that. */
22316
22317static void
22318fix_new_arm (fragS * frag,
22319 int where,
22320 short int size,
22321 expressionS * exp,
22322 int pc_rel,
22323 int reloc)
22324{
22325 fixS * new_fix;
22326
22327 switch (exp->X_op)
22328 {
22329 case O_constant:
6e7ce2cd
PB		 22330 if (pc_rel)
22331 {
22332 /* Create an absolute valued symbol, so we have something to
477330fc
RM		 22333 refer to in the object file. Unfortunately for us, gas's
22334 generic expression parsing will already have folded out
22335 any use of .set foo/.type foo %function that may have
22336 been used to set type information of the target location,
22337 that's being specified symbolically. We have to presume
22338 the user knows what they are doing. */
6e7ce2cd
PB		 22339 char name[16 + 8];
22340 symbolS *symbol;
22341
22342 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
22343
22344 symbol = symbol_find_or_make (name);
22345 S_SET_SEGMENT (symbol, absolute_section);
22346 symbol_set_frag (symbol, &zero_address_frag);
22347 S_SET_VALUE (symbol, exp->X_add_number);
22348 exp->X_op = O_symbol;
22349 exp->X_add_symbol = symbol;
22350 exp->X_add_number = 0;
22351 }
22352 /* FALLTHROUGH */
5287ad62
JB		 22353 case O_symbol:
22354 case O_add:
22355 case O_subtract:
21d799b5 22356 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
477330fc 22357 (enum bfd_reloc_code_real) reloc);
5287ad62
JB		 22358 break;
22359
22360 default:
21d799b5 22361 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
477330fc 22362 pc_rel, (enum bfd_reloc_code_real) reloc);
5287ad62
JB		 22363 break;
22364 }
22365
22366 /* Mark whether the fix is to a THUMB instruction, or an ARM
22367 instruction. */
22368 new_fix->tc_fix_data = thumb_mode;
22369}
22370
22371/* Create a frg for an instruction requiring relaxation. */
22372static void
22373output_relax_insn (void)
22374{
22375 char * to;
22376 symbolS *sym;
0110f2b8
PB		 22377 int offset;
22378
6e1cb1a6
PB		 22379 /* The size of the instruction is unknown, so tie the debug info to the
22380 start of the instruction. */
22381 dwarf2_emit_insn (0);
6e1cb1a6 22382
e2b0ab59 22383 switch (inst.relocs[0].exp.X_op)
0110f2b8
PB		 22384 {
22385 case O_symbol:
e2b0ab59
AV		 22386 sym = inst.relocs[0].exp.X_add_symbol;
22387 offset = inst.relocs[0].exp.X_add_number;
0110f2b8
PB		 22388 break;
22389 case O_constant:
22390 sym = NULL;
e2b0ab59 22391 offset = inst.relocs[0].exp.X_add_number;
0110f2b8
PB		 22392 break;
22393 default:
e2b0ab59 22394 sym = make_expr_symbol (&inst.relocs[0].exp);
0110f2b8
PB		 22395 offset = 0;
22396 break;
22397 }
22398 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
22399 inst.relax, sym, offset, NULL/*offset, opcode*/);
22400 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
0110f2b8
PB		 22401}
22402
22403/* Write a 32-bit thumb instruction to buf. */
22404static void
22405put_thumb32_insn (char * buf, unsigned long insn)
22406{
22407 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
22408 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
22409}
22410
b99bd4ef 22411static void
c19d1205 22412output_inst (const char * str)
b99bd4ef 22413{
c19d1205 22414 char * to = NULL;
b99bd4ef 22415
c19d1205 22416 if (inst.error)
b99bd4ef 22417 {
c19d1205 22418 as_bad ("%s -- `%s'", inst.error, str);
b99bd4ef
NC		 22419 return;
22420 }
5f4273c7
NC		 22421 if (inst.relax)
22422 {
22423 output_relax_insn ();
0110f2b8 22424 return;
5f4273c7 22425 }
c19d1205
ZW		 22426 if (inst.size == 0)
22427 return;
b99bd4ef 22428
c19d1205 22429 to = frag_more (inst.size);
8dc2430f
NC		 22430 /* PR 9814: Record the thumb mode into the current frag so that we know
22431 what type of NOP padding to use, if necessary. We override any previous
22432 setting so that if the mode has changed then the NOPS that we use will
22433 match the encoding of the last instruction in the frag. */
cd000bff 22434 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
c19d1205
ZW		 22435
22436 if (thumb_mode && (inst.size > THUMB_SIZE))
b99bd4ef 22437 {
9c2799c2 22438 gas_assert (inst.size == (2 * THUMB_SIZE));
0110f2b8 22439 put_thumb32_insn (to, inst.instruction);
b99bd4ef 22440 }
c19d1205 22441 else if (inst.size > INSN_SIZE)
b99bd4ef 22442 {
9c2799c2 22443 gas_assert (inst.size == (2 * INSN_SIZE));
c19d1205
ZW		 22444 md_number_to_chars (to, inst.instruction, INSN_SIZE);
22445 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
b99bd4ef 22446 }
c19d1205
ZW		 22447 else
22448 md_number_to_chars (to, inst.instruction, inst.size);
b99bd4ef 22449
e2b0ab59
AV		 22450 int r;
22451 for (r = 0; r < ARM_IT_MAX_RELOCS; r++)
22452 {
22453 if (inst.relocs[r].type != BFD_RELOC_UNUSED)
22454 fix_new_arm (frag_now, to - frag_now->fr_literal,
22455 inst.size, & inst.relocs[r].exp, inst.relocs[r].pc_rel,
22456 inst.relocs[r].type);
22457 }
b99bd4ef 22458
c19d1205 22459 dwarf2_emit_insn (inst.size);
c19d1205 22460}
b99bd4ef 22461
e07e6e58
NC		 22462static char *
22463output_it_inst (int cond, int mask, char * to)
22464{
22465 unsigned long instruction = 0xbf00;
22466
22467 mask &= 0xf;
22468 instruction |= mask;
22469 instruction |= cond << 4;
22470
22471 if (to == NULL)
22472 {
22473 to = frag_more (2);
22474#ifdef OBJ_ELF
22475 dwarf2_emit_insn (2);
22476#endif
22477 }
22478
22479 md_number_to_chars (to, instruction, 2);
22480
22481 return to;
22482}
22483
c19d1205
ZW		 22484/* Tag values used in struct asm_opcode's tag field. */
22485enum opcode_tag
22486{
22487 OT_unconditional, /* Instruction cannot be conditionalized.
22488 The ARM condition field is still 0xE. */
22489 OT_unconditionalF, /* Instruction cannot be conditionalized
22490 and carries 0xF in its ARM condition field. */
22491 OT_csuffix, /* Instruction takes a conditional suffix. */
5ee91343
AV		 22492 OT_csuffixF, /* Some forms of the instruction take a scalar
22493 conditional suffix, others place 0xF where the
22494 condition field would be, others take a vector
22495 conditional suffix. */
c19d1205
ZW		 22496 OT_cinfix3, /* Instruction takes a conditional infix,
22497 beginning at character index 3. (In
22498 unified mode, it becomes a suffix.) */
088fa78e
KH		 22499 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
22500 tsts, cmps, cmns, and teqs. */
e3cb604e
PB		 22501 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
22502 character index 3, even in unified mode. Used for
22503 legacy instructions where suffix and infix forms
22504 may be ambiguous. */
c19d1205 22505 OT_csuf_or_in3, /* Instruction takes either a conditional
e3cb604e 22506 suffix or an infix at character index 3. */
c19d1205
ZW		 22507 OT_odd_infix_unc, /* This is the unconditional variant of an
22508 instruction that takes a conditional infix
22509 at an unusual position. In unified mode,
22510 this variant will accept a suffix. */
22511 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
22512 are the conditional variants of instructions that
22513 take conditional infixes in unusual positions.
22514 The infix appears at character index
22515 (tag - OT_odd_infix_0). These are not accepted
22516 in unified mode. */
22517};
b99bd4ef 22518
c19d1205
ZW		 22519/* Subroutine of md_assemble, responsible for looking up the primary
22520 opcode from the mnemonic the user wrote. STR points to the
22521 beginning of the mnemonic.
22522
22523 This is not simply a hash table lookup, because of conditional
22524 variants. Most instructions have conditional variants, which are
22525 expressed with a _conditional affix_ to the mnemonic. If we were
22526 to encode each conditional variant as a literal string in the opcode
22527 table, it would have approximately 20,000 entries.
22528
22529 Most mnemonics take this affix as a suffix, and in unified syntax,
22530 'most' is upgraded to 'all'. However, in the divided syntax, some
22531 instructions take the affix as an infix, notably the s-variants of
22532 the arithmetic instructions. Of those instructions, all but six
22533 have the infix appear after the third character of the mnemonic.
22534
22535 Accordingly, the algorithm for looking up primary opcodes given
22536 an identifier is:
22537
22538 1. Look up the identifier in the opcode table.
22539 If we find a match, go to step U.
22540
22541 2. Look up the last two characters of the identifier in the
22542 conditions table. If we find a match, look up the first N-2
22543 characters of the identifier in the opcode table. If we
22544 find a match, go to step CE.
22545
22546 3. Look up the fourth and fifth characters of the identifier in
22547 the conditions table. If we find a match, extract those
22548 characters from the identifier, and look up the remaining
22549 characters in the opcode table. If we find a match, go
22550 to step CM.
22551
22552 4. Fail.
22553
22554 U. Examine the tag field of the opcode structure, in case this is
22555 one of the six instructions with its conditional infix in an
22556 unusual place. If it is, the tag tells us where to find the
22557 infix; look it up in the conditions table and set inst.cond
22558 accordingly. Otherwise, this is an unconditional instruction.
22559 Again set inst.cond accordingly. Return the opcode structure.
22560
22561 CE. Examine the tag field to make sure this is an instruction that
22562 should receive a conditional suffix. If it is not, fail.
22563 Otherwise, set inst.cond from the suffix we already looked up,
22564 and return the opcode structure.
22565
22566 CM. Examine the tag field to make sure this is an instruction that
22567 should receive a conditional infix after the third character.
22568 If it is not, fail. Otherwise, undo the edits to the current
22569 line of input and proceed as for case CE. */
22570
22571static const struct asm_opcode *
22572opcode_lookup (char **str)
22573{
22574 char *end, *base;
22575 char *affix;
22576 const struct asm_opcode *opcode;
22577 const struct asm_cond *cond;
e3cb604e 22578 char save[2];
c19d1205
ZW		 22579
22580 /* Scan up to the end of the mnemonic, which must end in white space,
721a8186 22581 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
c19d1205 22582 for (base = end = *str; *end != '\0'; end++)
721a8186 22583 if (*end == ' ' || *end == '.')
c19d1205 22584 break;
b99bd4ef 22585
c19d1205 22586 if (end == base)
c921be7d 22587 return NULL;
b99bd4ef 22588
5287ad62 22589 /* Handle a possible width suffix and/or Neon type suffix. */
c19d1205 22590 if (end[0] == '.')
b99bd4ef 22591 {
5287ad62 22592 int offset = 2;
5f4273c7 22593
267d2029 22594 /* The .w and .n suffixes are only valid if the unified syntax is in
477330fc 22595 use. */
267d2029 22596 if (unified_syntax && end[1] == 'w')
c19d1205 22597 inst.size_req = 4;
267d2029 22598 else if (unified_syntax && end[1] == 'n')
c19d1205
ZW		 22599 inst.size_req = 2;
22600 else
477330fc 22601 offset = 0;
5287ad62
JB		 22602
22603 inst.vectype.elems = 0;
22604
22605 *str = end + offset;
b99bd4ef 22606
5f4273c7 22607 if (end[offset] == '.')
5287ad62 22608 {
267d2029 22609 /* See if we have a Neon type suffix (possible in either unified or
477330fc
RM		 22610 non-unified ARM syntax mode). */
22611 if (parse_neon_type (&inst.vectype, str) == FAIL)
c921be7d 22612 return NULL;
477330fc 22613 }
5287ad62 22614 else if (end[offset] != '\0' && end[offset] != ' ')
477330fc 22615 return NULL;
b99bd4ef 22616 }
c19d1205
ZW		 22617 else
22618 *str = end;
b99bd4ef 22619
c19d1205 22620 /* Look for unaffixed or special-case affixed mnemonic. */
21d799b5 22621 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
477330fc 22622 end - base);
c19d1205 22623 if (opcode)
b99bd4ef 22624 {
c19d1205
ZW		 22625 /* step U */
22626 if (opcode->tag < OT_odd_infix_0)
b99bd4ef 22627 {
c19d1205
ZW		 22628 inst.cond = COND_ALWAYS;
22629 return opcode;
b99bd4ef 22630 }
b99bd4ef 22631
278df34e 22632 if (warn_on_deprecated && unified_syntax)
5c3696f8 22633 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
c19d1205 22634 affix = base + (opcode->tag - OT_odd_infix_0);
21d799b5 22635 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
9c2799c2 22636 gas_assert (cond);
b99bd4ef 22637
c19d1205
ZW		 22638 inst.cond = cond->value;
22639 return opcode;
22640 }
5ee91343
AV		 22641 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
22642 {
22643 /* Cannot have a conditional suffix on a mnemonic of less than a character.
22644 */
22645 if (end - base < 2)
22646 return NULL;
22647 affix = end - 1;
22648 cond = (const struct asm_cond *) hash_find_n (arm_vcond_hsh, affix, 1);
22649 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
22650 affix - base);
22651 /* If this opcode can not be vector predicated then don't accept it with a
22652 vector predication code. */
22653 if (opcode && !opcode->mayBeVecPred)
22654 opcode = NULL;
22655 }
22656 if (!opcode || !cond)
22657 {
22658 /* Cannot have a conditional suffix on a mnemonic of less than two
22659 characters. */
22660 if (end - base < 3)
22661 return NULL;
b99bd4ef 22662
5ee91343
AV		 22663 /* Look for suffixed mnemonic. */
22664 affix = end - 2;
22665 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
22666 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
22667 affix - base);
22668 }
b99bd4ef 22669
c19d1205
ZW		 22670 if (opcode && cond)
22671 {
22672 /* step CE */
22673 switch (opcode->tag)
22674 {
e3cb604e
PB		 22675 case OT_cinfix3_legacy:
22676 /* Ignore conditional suffixes matched on infix only mnemonics. */
22677 break;
22678
c19d1205 22679 case OT_cinfix3:
088fa78e 22680 case OT_cinfix3_deprecated:
c19d1205
ZW		 22681 case OT_odd_infix_unc:
22682 if (!unified_syntax)
0198d5e6 22683 return NULL;
1a0670f3 22684 /* Fall through. */
c19d1205
ZW		 22685
22686 case OT_csuffix:
477330fc 22687 case OT_csuffixF:
c19d1205
ZW		 22688 case OT_csuf_or_in3:
22689 inst.cond = cond->value;
22690 return opcode;
22691
22692 case OT_unconditional:
22693 case OT_unconditionalF:
dfa9f0d5 22694 if (thumb_mode)
c921be7d 22695 inst.cond = cond->value;
dfa9f0d5
PB		 22696 else
22697 {
c921be7d 22698 /* Delayed diagnostic. */
dfa9f0d5
PB		 22699 inst.error = BAD_COND;
22700 inst.cond = COND_ALWAYS;
22701 }
c19d1205 22702 return opcode;
b99bd4ef 22703
c19d1205 22704 default:
c921be7d 22705 return NULL;
c19d1205
ZW		 22706 }
22707 }
b99bd4ef 22708
c19d1205
ZW		 22709 /* Cannot have a usual-position infix on a mnemonic of less than
22710 six characters (five would be a suffix). */
22711 if (end - base < 6)
c921be7d 22712 return NULL;
b99bd4ef 22713
c19d1205
ZW		 22714 /* Look for infixed mnemonic in the usual position. */
22715 affix = base + 3;
21d799b5 22716 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
e3cb604e 22717 if (!cond)
c921be7d 22718 return NULL;
e3cb604e
PB		 22719
22720 memcpy (save, affix, 2);
22721 memmove (affix, affix + 2, (end - affix) - 2);
21d799b5 22722 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
477330fc 22723 (end - base) - 2);
e3cb604e
PB		 22724 memmove (affix + 2, affix, (end - affix) - 2);
22725 memcpy (affix, save, 2);
22726
088fa78e
KH		 22727 if (opcode
22728 && (opcode->tag == OT_cinfix3
22729 || opcode->tag == OT_cinfix3_deprecated
22730 || opcode->tag == OT_csuf_or_in3
22731 || opcode->tag == OT_cinfix3_legacy))
b99bd4ef 22732 {
c921be7d 22733 /* Step CM. */
278df34e 22734 if (warn_on_deprecated && unified_syntax
088fa78e
KH		 22735 && (opcode->tag == OT_cinfix3
22736 || opcode->tag == OT_cinfix3_deprecated))
5c3696f8 22737 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
c19d1205
ZW		 22738
22739 inst.cond = cond->value;
22740 return opcode;
b99bd4ef
NC		 22741 }
22742
c921be7d 22743 return NULL;
b99bd4ef
NC		 22744}
22745
e07e6e58
NC		 22746/* This function generates an initial IT instruction, leaving its block
22747 virtually open for the new instructions. Eventually,
5ee91343 22748 the mask will be updated by now_pred_add_mask () each time
e07e6e58
NC		 22749 a new instruction needs to be included in the IT block.
22750 Finally, the block is closed with close_automatic_it_block ().
22751 The block closure can be requested either from md_assemble (),
22752 a tencode (), or due to a label hook. */
22753
22754static void
22755new_automatic_it_block (int cond)
22756{
5ee91343
AV		 22757 now_pred.state = AUTOMATIC_PRED_BLOCK;
22758 now_pred.mask = 0x18;
22759 now_pred.cc = cond;
22760 now_pred.block_length = 1;
cd000bff 22761 mapping_state (MAP_THUMB);
5ee91343
AV		 22762 now_pred.insn = output_it_inst (cond, now_pred.mask, NULL);
22763 now_pred.warn_deprecated = FALSE;
22764 now_pred.insn_cond = TRUE;
e07e6e58
NC		 22765}
22766
22767/* Close an automatic IT block.
22768 See comments in new_automatic_it_block (). */
22769
22770static void
22771close_automatic_it_block (void)
22772{
5ee91343
AV		 22773 now_pred.mask = 0x10;
22774 now_pred.block_length = 0;
e07e6e58
NC		 22775}
22776
22777/* Update the mask of the current automatically-generated IT
22778 instruction. See comments in new_automatic_it_block (). */
22779
22780static void
5ee91343 22781now_pred_add_mask (int cond)
e07e6e58
NC		 22782{
22783#define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
22784#define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
477330fc 22785 | ((bitvalue) << (nbit)))
e07e6e58 22786 const int resulting_bit = (cond & 1);
c921be7d 22787
5ee91343
AV		 22788 now_pred.mask &= 0xf;
22789 now_pred.mask = SET_BIT_VALUE (now_pred.mask,
477330fc 22790 resulting_bit,
5ee91343
AV		 22791 (5 - now_pred.block_length));
22792 now_pred.mask = SET_BIT_VALUE (now_pred.mask,
477330fc 22793 1,
5ee91343
AV		 22794 ((5 - now_pred.block_length) - 1));
22795 output_it_inst (now_pred.cc, now_pred.mask, now_pred.insn);
e07e6e58
NC		 22796
22797#undef CLEAR_BIT
22798#undef SET_BIT_VALUE
e07e6e58
NC		 22799}
22800
22801/* The IT blocks handling machinery is accessed through the these functions:
22802 it_fsm_pre_encode () from md_assemble ()
5ee91343
AV		 22803 set_pred_insn_type () optional, from the tencode functions
22804 set_pred_insn_type_last () ditto
22805 in_pred_block () ditto
e07e6e58 22806 it_fsm_post_encode () from md_assemble ()
33eaf5de 22807 force_automatic_it_block_close () from label handling functions
e07e6e58
NC		 22808
22809 Rationale:
22810 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
477330fc
RM		 22811 initializing the IT insn type with a generic initial value depending
22812 on the inst.condition.
e07e6e58 22813 2) During the tencode function, two things may happen:
477330fc 22814 a) The tencode function overrides the IT insn type by
5ee91343
AV		 22815 calling either set_pred_insn_type (type) or
22816 set_pred_insn_type_last ().
477330fc 22817 b) The tencode function queries the IT block state by
5ee91343 22818 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
477330fc 22819
5ee91343
AV		 22820 Both set_pred_insn_type and in_pred_block run the internal FSM state
22821 handling function (handle_pred_state), because: a) setting the IT insn
477330fc
RM		 22822 type may incur in an invalid state (exiting the function),
22823 and b) querying the state requires the FSM to be updated.
22824 Specifically we want to avoid creating an IT block for conditional
22825 branches, so it_fsm_pre_encode is actually a guess and we can't
22826 determine whether an IT block is required until the tencode () routine
22827 has decided what type of instruction this actually it.
5ee91343
AV		 22828 Because of this, if set_pred_insn_type and in_pred_block have to be
22829 used, set_pred_insn_type has to be called first.
477330fc 22830
5ee91343
AV		 22831 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
22832 that determines the insn IT type depending on the inst.cond code.
477330fc
RM		 22833 When a tencode () routine encodes an instruction that can be
22834 either outside an IT block, or, in the case of being inside, has to be
5ee91343 22835 the last one, set_pred_insn_type_last () will determine the proper
477330fc 22836 IT instruction type based on the inst.cond code. Otherwise,
5ee91343 22837 set_pred_insn_type can be called for overriding that logic or
477330fc
RM		 22838 for covering other cases.
22839
5ee91343
AV		 22840 Calling handle_pred_state () may not transition the IT block state to
22841 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
477330fc 22842 still queried. Instead, if the FSM determines that the state should
5ee91343 22843 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
477330fc
RM		 22844 after the tencode () function: that's what it_fsm_post_encode () does.
22845
5ee91343 22846 Since in_pred_block () calls the state handling function to get an
477330fc
RM		 22847 updated state, an error may occur (due to invalid insns combination).
22848 In that case, inst.error is set.
22849 Therefore, inst.error has to be checked after the execution of
22850 the tencode () routine.
e07e6e58
NC		 22851
22852 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
477330fc 22853 any pending state change (if any) that didn't take place in
5ee91343 22854 handle_pred_state () as explained above. */
e07e6e58
NC		 22855
22856static void
22857it_fsm_pre_encode (void)
22858{
22859 if (inst.cond != COND_ALWAYS)
5ee91343 22860 inst.pred_insn_type = INSIDE_IT_INSN;
e07e6e58 22861 else
5ee91343 22862 inst.pred_insn_type = OUTSIDE_PRED_INSN;
e07e6e58 22863
5ee91343 22864 now_pred.state_handled = 0;
e07e6e58
NC		 22865}
22866
22867/* IT state FSM handling function. */
5ee91343
AV		 22868/* MVE instructions and non-MVE instructions are handled differently because of
22869 the introduction of VPT blocks.
22870 Specifications say that any non-MVE instruction inside a VPT block is
22871 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
22872 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
35c228db 22873 few exceptions we have MVE_UNPREDICABLE_INSN.
5ee91343
AV		 22874 The error messages provided depending on the different combinations possible
22875 are described in the cases below:
22876 For 'most' MVE instructions:
22877 1) In an IT block, with an IT code: syntax error
22878 2) In an IT block, with a VPT code: error: must be in a VPT block
22879 3) In an IT block, with no code: warning: UNPREDICTABLE
22880 4) In a VPT block, with an IT code: syntax error
22881 5) In a VPT block, with a VPT code: OK!
22882 6) In a VPT block, with no code: error: missing code
22883 7) Outside a pred block, with an IT code: error: syntax error
22884 8) Outside a pred block, with a VPT code: error: should be in a VPT block
22885 9) Outside a pred block, with no code: OK!
22886 For non-MVE instructions:
22887 10) In an IT block, with an IT code: OK!
22888 11) In an IT block, with a VPT code: syntax error
22889 12) In an IT block, with no code: error: missing code
22890 13) In a VPT block, with an IT code: error: should be in an IT block
22891 14) In a VPT block, with a VPT code: syntax error
22892 15) In a VPT block, with no code: UNPREDICTABLE
22893 16) Outside a pred block, with an IT code: error: should be in an IT block
22894 17) Outside a pred block, with a VPT code: syntax error
22895 18) Outside a pred block, with no code: OK!
22896 */
22897
e07e6e58
NC		 22898
22899static int
5ee91343 22900handle_pred_state (void)
e07e6e58 22901{
5ee91343
AV		 22902 now_pred.state_handled = 1;
22903 now_pred.insn_cond = FALSE;
e07e6e58 22904
5ee91343 22905 switch (now_pred.state)
e07e6e58 22906 {
5ee91343
AV		 22907 case OUTSIDE_PRED_BLOCK:
22908 switch (inst.pred_insn_type)
e07e6e58 22909 {
35c228db 22910 case MVE_UNPREDICABLE_INSN:
5ee91343
AV		 22911 case MVE_OUTSIDE_PRED_INSN:
22912 if (inst.cond < COND_ALWAYS)
22913 {
22914 /* Case 7: Outside a pred block, with an IT code: error: syntax
22915 error. */
22916 inst.error = BAD_SYNTAX;
22917 return FAIL;
22918 }
22919 /* Case 9: Outside a pred block, with no code: OK! */
22920 break;
22921 case OUTSIDE_PRED_INSN:
22922 if (inst.cond > COND_ALWAYS)
22923 {
22924 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22925 */
22926 inst.error = BAD_SYNTAX;
22927 return FAIL;
22928 }
22929 /* Case 18: Outside a pred block, with no code: OK! */
e07e6e58
NC		 22930 break;
22931
5ee91343
AV		 22932 case INSIDE_VPT_INSN:
22933 /* Case 8: Outside a pred block, with a VPT code: error: should be in
22934 a VPT block. */
22935 inst.error = BAD_OUT_VPT;
22936 return FAIL;
22937
e07e6e58
NC		 22938 case INSIDE_IT_INSN:
22939 case INSIDE_IT_LAST_INSN:
5ee91343 22940 if (inst.cond < COND_ALWAYS)
e07e6e58 22941 {
5ee91343
AV		 22942 /* Case 16: Outside a pred block, with an IT code: error: should
22943 be in an IT block. */
22944 if (thumb_mode == 0)
e07e6e58 22945 {
5ee91343
AV		 22946 if (unified_syntax
22947 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
22948 as_tsktsk (_("Warning: conditional outside an IT block"\
22949 " for Thumb."));
e07e6e58
NC		 22950 }
22951 else
22952 {
5ee91343
AV		 22953 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
22954 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
22955 {
22956 /* Automatically generate the IT instruction. */
22957 new_automatic_it_block (inst.cond);
22958 if (inst.pred_insn_type == INSIDE_IT_LAST_INSN)
22959 close_automatic_it_block ();
22960 }
22961 else
22962 {
22963 inst.error = BAD_OUT_IT;
22964 return FAIL;
22965 }
e07e6e58 22966 }
5ee91343 22967 break;
e07e6e58 22968 }
5ee91343
AV		 22969 else if (inst.cond > COND_ALWAYS)
22970 {
22971 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22972 */
22973 inst.error = BAD_SYNTAX;
22974 return FAIL;
22975 }
22976 else
22977 gas_assert (0);
e07e6e58
NC		 22978 case IF_INSIDE_IT_LAST_INSN:
22979 case NEUTRAL_IT_INSN:
22980 break;
22981
5ee91343
AV		 22982 case VPT_INSN:
22983 if (inst.cond != COND_ALWAYS)
22984 first_error (BAD_SYNTAX);
22985 now_pred.state = MANUAL_PRED_BLOCK;
22986 now_pred.block_length = 0;
22987 now_pred.type = VECTOR_PRED;
22988 now_pred.cc = 0;
22989 break;
e07e6e58 22990 case IT_INSN:
5ee91343
AV		 22991 now_pred.state = MANUAL_PRED_BLOCK;
22992 now_pred.block_length = 0;
22993 now_pred.type = SCALAR_PRED;
e07e6e58
NC		 22994 break;
22995 }
22996 break;
22997
5ee91343 22998 case AUTOMATIC_PRED_BLOCK:
e07e6e58
NC		 22999 /* Three things may happen now:
23000 a) We should increment current it block size;
23001 b) We should close current it block (closing insn or 4 insns);
23002 c) We should close current it block and start a new one (due
23003 to incompatible conditions or
23004 4 insns-length block reached). */
23005
5ee91343 23006 switch (inst.pred_insn_type)
e07e6e58 23007 {
5ee91343
AV		 23008 case INSIDE_VPT_INSN:
23009 case VPT_INSN:
35c228db 23010 case MVE_UNPREDICABLE_INSN:
5ee91343
AV		 23011 case MVE_OUTSIDE_PRED_INSN:
23012 gas_assert (0);
23013 case OUTSIDE_PRED_INSN:
2b0f3761 23014 /* The closure of the block shall happen immediately,
5ee91343 23015 so any in_pred_block () call reports the block as closed. */
e07e6e58
NC		 23016 force_automatic_it_block_close ();
23017 break;
23018
23019 case INSIDE_IT_INSN:
23020 case INSIDE_IT_LAST_INSN:
23021 case IF_INSIDE_IT_LAST_INSN:
5ee91343 23022 now_pred.block_length++;
e07e6e58 23023
5ee91343
AV		 23024 if (now_pred.block_length > 4
23025 || !now_pred_compatible (inst.cond))
e07e6e58
NC		 23026 {
23027 force_automatic_it_block_close ();
5ee91343 23028 if (inst.pred_insn_type != IF_INSIDE_IT_LAST_INSN)
e07e6e58
NC		 23029 new_automatic_it_block (inst.cond);
23030 }
23031 else
23032 {
5ee91343
AV		 23033 now_pred.insn_cond = TRUE;
23034 now_pred_add_mask (inst.cond);
e07e6e58
NC		 23035 }
23036
5ee91343
AV		 23037 if (now_pred.state == AUTOMATIC_PRED_BLOCK
23038 && (inst.pred_insn_type == INSIDE_IT_LAST_INSN
23039 || inst.pred_insn_type == IF_INSIDE_IT_LAST_INSN))
e07e6e58
NC		 23040 close_automatic_it_block ();
23041 break;
23042
4934a27c 23043 /* Fallthrough. */
e07e6e58 23044 case NEUTRAL_IT_INSN:
5ee91343
AV		 23045 now_pred.block_length++;
23046 now_pred.insn_cond = TRUE;
e07e6e58 23047
5ee91343 23048 if (now_pred.block_length > 4)
e07e6e58
NC		 23049 force_automatic_it_block_close ();
23050 else
5ee91343 23051 now_pred_add_mask (now_pred.cc & 1);
e07e6e58
NC		 23052 break;
23053
23054 case IT_INSN:
23055 close_automatic_it_block ();
5ee91343 23056 now_pred.state = MANUAL_PRED_BLOCK;
e07e6e58
NC		 23057 break;
23058 }
23059 break;
23060
5ee91343 23061 case MANUAL_PRED_BLOCK:
e07e6e58 23062 {
5ee91343
AV		 23063 int cond, is_last;
23064 if (now_pred.type == SCALAR_PRED)
e07e6e58 23065 {
5ee91343
AV		 23066 /* Check conditional suffixes. */
23067 cond = now_pred.cc ^ ((now_pred.mask >> 4) & 1) ^ 1;
23068 now_pred.mask <<= 1;
23069 now_pred.mask &= 0x1f;
23070 is_last = (now_pred.mask == 0x10);
23071 }
23072 else
23073 {
23074 now_pred.cc ^= (now_pred.mask >> 4);
23075 cond = now_pred.cc + 0xf;
23076 now_pred.mask <<= 1;
23077 now_pred.mask &= 0x1f;
23078 is_last = now_pred.mask == 0x10;
23079 }
23080 now_pred.insn_cond = TRUE;
e07e6e58 23081
5ee91343
AV		 23082 switch (inst.pred_insn_type)
23083 {
23084 case OUTSIDE_PRED_INSN:
23085 if (now_pred.type == SCALAR_PRED)
23086 {
23087 if (inst.cond == COND_ALWAYS)
23088 {
23089 /* Case 12: In an IT block, with no code: error: missing
23090 code. */
23091 inst.error = BAD_NOT_IT;
23092 return FAIL;
23093 }
23094 else if (inst.cond > COND_ALWAYS)
23095 {
23096 /* Case 11: In an IT block, with a VPT code: syntax error.
23097 */
23098 inst.error = BAD_SYNTAX;
23099 return FAIL;
23100 }
23101 else if (thumb_mode)
23102 {
23103 /* This is for some special cases where a non-MVE
23104 instruction is not allowed in an IT block, such as cbz,
23105 but are put into one with a condition code.
23106 You could argue this should be a syntax error, but we
23107 gave the 'not allowed in IT block' diagnostic in the
23108 past so we will keep doing so. */
23109 inst.error = BAD_NOT_IT;
23110 return FAIL;
23111 }
23112 break;
23113 }
23114 else
23115 {
23116 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
23117 as_tsktsk (MVE_NOT_VPT);
23118 return SUCCESS;
23119 }
23120 case MVE_OUTSIDE_PRED_INSN:
23121 if (now_pred.type == SCALAR_PRED)
23122 {
23123 if (inst.cond == COND_ALWAYS)
23124 {
23125 /* Case 3: In an IT block, with no code: warning:
23126 UNPREDICTABLE. */
23127 as_tsktsk (MVE_NOT_IT);
23128 return SUCCESS;
23129 }
23130 else if (inst.cond < COND_ALWAYS)
23131 {
23132 /* Case 1: In an IT block, with an IT code: syntax error.
23133 */
23134 inst.error = BAD_SYNTAX;
23135 return FAIL;
23136 }
23137 else
23138 gas_assert (0);
23139 }
23140 else
23141 {
23142 if (inst.cond < COND_ALWAYS)
23143 {
23144 /* Case 4: In a VPT block, with an IT code: syntax error.
23145 */
23146 inst.error = BAD_SYNTAX;
23147 return FAIL;
23148 }
23149 else if (inst.cond == COND_ALWAYS)
23150 {
23151 /* Case 6: In a VPT block, with no code: error: missing
23152 code. */
23153 inst.error = BAD_NOT_VPT;
23154 return FAIL;
23155 }
23156 else
23157 {
23158 gas_assert (0);
23159 }
23160 }
35c228db
AV		 23161 case MVE_UNPREDICABLE_INSN:
23162 as_tsktsk (now_pred.type == SCALAR_PRED ? MVE_NOT_IT : MVE_NOT_VPT);
23163 return SUCCESS;
e07e6e58 23164 case INSIDE_IT_INSN:
5ee91343 23165 if (inst.cond > COND_ALWAYS)
e07e6e58 23166 {
5ee91343
AV		 23167 /* Case 11: In an IT block, with a VPT code: syntax error. */
23168 /* Case 14: In a VPT block, with a VPT code: syntax error. */
23169 inst.error = BAD_SYNTAX;
23170 return FAIL;
23171 }
23172 else if (now_pred.type == SCALAR_PRED)
23173 {
23174 /* Case 10: In an IT block, with an IT code: OK! */
23175 if (cond != inst.cond)
23176 {
23177 inst.error = now_pred.type == SCALAR_PRED ? BAD_IT_COND :
23178 BAD_VPT_COND;
23179 return FAIL;
23180 }
23181 }
23182 else
23183 {
23184 /* Case 13: In a VPT block, with an IT code: error: should be
23185 in an IT block. */
23186 inst.error = BAD_OUT_IT;
e07e6e58
NC		 23187 return FAIL;
23188 }
23189 break;
23190
5ee91343
AV		 23191 case INSIDE_VPT_INSN:
23192 if (now_pred.type == SCALAR_PRED)
23193 {
23194 /* Case 2: In an IT block, with a VPT code: error: must be in a
23195 VPT block. */
23196 inst.error = BAD_OUT_VPT;
23197 return FAIL;
23198 }
23199 /* Case 5: In a VPT block, with a VPT code: OK! */
23200 else if (cond != inst.cond)
23201 {
23202 inst.error = BAD_VPT_COND;
23203 return FAIL;
23204 }
23205 break;
e07e6e58
NC		 23206 case INSIDE_IT_LAST_INSN:
23207 case IF_INSIDE_IT_LAST_INSN:
5ee91343
AV		 23208 if (now_pred.type == VECTOR_PRED || inst.cond > COND_ALWAYS)
23209 {
23210 /* Case 4: In a VPT block, with an IT code: syntax error. */
23211 /* Case 11: In an IT block, with a VPT code: syntax error. */
23212 inst.error = BAD_SYNTAX;
23213 return FAIL;
23214 }
23215 else if (cond != inst.cond)
e07e6e58
NC		 23216 {
23217 inst.error = BAD_IT_COND;
23218 return FAIL;
23219 }
23220 if (!is_last)
23221 {
23222 inst.error = BAD_BRANCH;
23223 return FAIL;
23224 }
23225 break;
23226
23227 case NEUTRAL_IT_INSN:
5ee91343
AV		 23228 /* The BKPT instruction is unconditional even in a IT or VPT
23229 block. */
e07e6e58
NC		 23230 break;
23231
23232 case IT_INSN:
5ee91343
AV		 23233 if (now_pred.type == SCALAR_PRED)
23234 {
23235 inst.error = BAD_IT_IT;
23236 return FAIL;
23237 }
23238 /* fall through. */
23239 case VPT_INSN:
23240 if (inst.cond == COND_ALWAYS)
23241 {
23242 /* Executing a VPT/VPST instruction inside an IT block or a
23243 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
23244 */
23245 if (now_pred.type == SCALAR_PRED)
23246 as_tsktsk (MVE_NOT_IT);
23247 else
23248 as_tsktsk (MVE_NOT_VPT);
23249 return SUCCESS;
23250 }
23251 else
23252 {
23253 /* VPT/VPST do not accept condition codes. */
23254 inst.error = BAD_SYNTAX;
23255 return FAIL;
23256 }
e07e6e58 23257 }
5ee91343 23258 }
e07e6e58
NC		 23259 break;
23260 }
23261
23262 return SUCCESS;
23263}
23264
5a01bb1d
MGD		 23265struct depr_insn_mask
23266{
23267 unsigned long pattern;
23268 unsigned long mask;
23269 const char* description;
23270};
23271
23272/* List of 16-bit instruction patterns deprecated in an IT block in
23273 ARMv8. */
23274static const struct depr_insn_mask depr_it_insns[] = {
23275 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
23276 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
23277 { 0xa000, 0xb800, N_("ADR") },
23278 { 0x4800, 0xf800, N_("Literal loads") },
23279 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
23280 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
c8de034b
JW		 23281 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
23282 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
23283 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
5a01bb1d
MGD		 23284 { 0, 0, NULL }
23285};
23286
e07e6e58
NC		 23287static void
23288it_fsm_post_encode (void)
23289{
23290 int is_last;
23291
5ee91343
AV		 23292 if (!now_pred.state_handled)
23293 handle_pred_state ();
e07e6e58 23294
5ee91343 23295 if (now_pred.insn_cond
24f19ccb 23296 && warn_on_restrict_it
5ee91343 23297 && !now_pred.warn_deprecated
5a01bb1d 23298 && warn_on_deprecated
164446e0
AF		 23299 && (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)
23300 || ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8r))
df9909b8 23301 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m))
5a01bb1d
MGD		 23302 {
23303 if (inst.instruction >= 0x10000)
23304 {
5c3696f8 23305 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
df9909b8 23306 "performance deprecated in ARMv8-A and ARMv8-R"));
5ee91343 23307 now_pred.warn_deprecated = TRUE;
5a01bb1d
MGD		 23308 }
23309 else
23310 {
23311 const struct depr_insn_mask *p = depr_it_insns;
23312
23313 while (p->mask != 0)
23314 {
23315 if ((inst.instruction & p->mask) == p->pattern)
23316 {
df9909b8
TP		 23317 as_tsktsk (_("IT blocks containing 16-bit Thumb "
23318 "instructions of the following class are "
23319 "performance deprecated in ARMv8-A and "
23320 "ARMv8-R: %s"), p->description);
5ee91343 23321 now_pred.warn_deprecated = TRUE;
5a01bb1d
MGD		 23322 break;
23323 }
23324
23325 ++p;
23326 }
23327 }
23328
5ee91343 23329 if (now_pred.block_length > 1)
5a01bb1d 23330 {
5c3696f8 23331 as_tsktsk (_("IT blocks containing more than one conditional "
df9909b8
TP		 23332 "instruction are performance deprecated in ARMv8-A and "
23333 "ARMv8-R"));
5ee91343 23334 now_pred.warn_deprecated = TRUE;
5a01bb1d
MGD		 23335 }
23336 }
23337
5ee91343
AV		 23338 is_last = (now_pred.mask == 0x10);
23339 if (is_last)
23340 {
23341 now_pred.state = OUTSIDE_PRED_BLOCK;
23342 now_pred.mask = 0;
23343 }
e07e6e58
NC		 23344}
23345
23346static void
23347force_automatic_it_block_close (void)
23348{
5ee91343 23349 if (now_pred.state == AUTOMATIC_PRED_BLOCK)
e07e6e58
NC		 23350 {
23351 close_automatic_it_block ();
5ee91343
AV		 23352 now_pred.state = OUTSIDE_PRED_BLOCK;
23353 now_pred.mask = 0;
e07e6e58
NC		 23354 }
23355}
23356
23357static int
5ee91343 23358in_pred_block (void)
e07e6e58 23359{
5ee91343
AV		 23360 if (!now_pred.state_handled)
23361 handle_pred_state ();
e07e6e58 23362
5ee91343 23363 return now_pred.state != OUTSIDE_PRED_BLOCK;
e07e6e58
NC		 23364}
23365
ff8646ee
TP		 23366/* Whether OPCODE only has T32 encoding. Since this function is only used by
23367 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
23368 here, hence the "known" in the function name. */
fc289b0a
TP		 23369
23370static bfd_boolean
ff8646ee 23371known_t32_only_insn (const struct asm_opcode *opcode)
fc289b0a
TP		 23372{
23373 /* Original Thumb-1 wide instruction. */
23374 if (opcode->tencode == do_t_blx
23375 || opcode->tencode == do_t_branch23
23376 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
23377 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))
23378 return TRUE;
23379
16a1fa25
TP		 23380 /* Wide-only instruction added to ARMv8-M Baseline. */
23381 if (ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v8m_m_only)
ff8646ee
TP		 23382 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_atomics)
23383 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v6t2_v8m)
23384 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_div))
23385 return TRUE;
23386
23387 return FALSE;
23388}
23389
23390/* Whether wide instruction variant can be used if available for a valid OPCODE
23391 in ARCH. */
23392
23393static bfd_boolean
23394t32_insn_ok (arm_feature_set arch, const struct asm_opcode *opcode)
23395{
23396 if (known_t32_only_insn (opcode))
23397 return TRUE;
23398
23399 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
23400 of variant T3 of B.W is checked in do_t_branch. */
23401 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)
23402 && opcode->tencode == do_t_branch)
23403 return TRUE;
23404
bada4342
JW		 23405 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
23406 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)
23407 && opcode->tencode == do_t_mov_cmp
23408 /* Make sure CMP instruction is not affected. */
23409 && opcode->aencode == do_mov)
23410 return TRUE;
23411
ff8646ee
TP		 23412 /* Wide instruction variants of all instructions with narrow *and* wide
23413 variants become available with ARMv6t2. Other opcodes are either
23414 narrow-only or wide-only and are thus available if OPCODE is valid. */
23415 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v6t2))
23416 return TRUE;
23417
23418 /* OPCODE with narrow only instruction variant or wide variant not
23419 available. */
fc289b0a
TP		 23420 return FALSE;
23421}
23422
c19d1205
ZW		 23423void
23424md_assemble (char *str)
b99bd4ef 23425{
c19d1205
ZW		 23426 char *p = str;
23427 const struct asm_opcode * opcode;
b99bd4ef 23428
c19d1205
ZW		 23429 /* Align the previous label if needed. */
23430 if (last_label_seen != NULL)
b99bd4ef 23431 {
c19d1205
ZW		 23432 symbol_set_frag (last_label_seen, frag_now);
23433 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
23434 S_SET_SEGMENT (last_label_seen, now_seg);
b99bd4ef
NC		 23435 }
23436
c19d1205 23437 memset (&inst, '\0', sizeof (inst));
e2b0ab59
AV		 23438 int r;
23439 for (r = 0; r < ARM_IT_MAX_RELOCS; r++)
23440 inst.relocs[r].type = BFD_RELOC_UNUSED;
b99bd4ef 23441
c19d1205
ZW		 23442 opcode = opcode_lookup (&p);
23443 if (!opcode)
b99bd4ef 23444 {
c19d1205 23445 /* It wasn't an instruction, but it might be a register alias of
dcbf9037 23446 the form alias .req reg, or a Neon .dn/.qn directive. */
c921be7d 23447 if (! create_register_alias (str, p)
477330fc 23448 && ! create_neon_reg_alias (str, p))
c19d1205 23449 as_bad (_("bad instruction `%s'"), str);
b99bd4ef 23450
b99bd4ef
NC		 23451 return;
23452 }
23453
278df34e 23454 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
5c3696f8 23455 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
088fa78e 23456
037e8744
JB		 23457 /* The value which unconditional instructions should have in place of the
23458 condition field. */
23459 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
23460
c19d1205 23461 if (thumb_mode)
b99bd4ef 23462 {
e74cfd16 23463 arm_feature_set variant;
8f06b2d8
PB		 23464
23465 variant = cpu_variant;
23466 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
e74cfd16
PB		 23467 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
23468 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
c19d1205 23469 /* Check that this instruction is supported for this CPU. */
62b3e311
PB		 23470 if (!opcode->tvariant
23471 || (thumb_mode == 1
23472 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
b99bd4ef 23473 {
173205ca
TP		 23474 if (opcode->tencode == do_t_swi)
23475 as_bad (_("SVC is not permitted on this architecture"));
23476 else
23477 as_bad (_("selected processor does not support `%s' in Thumb mode"), str);
b99bd4ef
NC		 23478 return;
23479 }
c19d1205
ZW		 23480 if (inst.cond != COND_ALWAYS && !unified_syntax
23481 && opcode->tencode != do_t_branch)
b99bd4ef 23482 {
c19d1205 23483 as_bad (_("Thumb does not support conditional execution"));
b99bd4ef
NC		 23484 return;
23485 }
23486
fc289b0a
TP		 23487 /* Two things are addressed here:
23488 1) Implicit require narrow instructions on Thumb-1.
23489 This avoids relaxation accidentally introducing Thumb-2
23490 instructions.
23491 2) Reject wide instructions in non Thumb-2 cores.
23492
23493 Only instructions with narrow and wide variants need to be handled
23494 but selecting all non wide-only instructions is easier. */
23495 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)
ff8646ee 23496 && !t32_insn_ok (variant, opcode))
076d447c 23497 {
fc289b0a
TP		 23498 if (inst.size_req == 0)
23499 inst.size_req = 2;
23500 else if (inst.size_req == 4)
752d5da4 23501 {
ff8646ee
TP		 23502 if (ARM_CPU_HAS_FEATURE (variant, arm_ext_v8m))
23503 as_bad (_("selected processor does not support 32bit wide "
23504 "variant of instruction `%s'"), str);
23505 else
23506 as_bad (_("selected processor does not support `%s' in "
23507 "Thumb-2 mode"), str);
fc289b0a 23508 return;
752d5da4 23509 }
076d447c
PB		 23510 }
23511
c19d1205
ZW		 23512 inst.instruction = opcode->tvalue;
23513
5be8be5d 23514 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
477330fc 23515 {
5ee91343 23516 /* Prepare the pred_insn_type for those encodings that don't set
477330fc
RM		 23517 it. */
23518 it_fsm_pre_encode ();
c19d1205 23519
477330fc 23520 opcode->tencode ();
e07e6e58 23521
477330fc
RM		 23522 it_fsm_post_encode ();
23523 }
e27ec89e 23524
0110f2b8 23525 if (!(inst.error || inst.relax))
b99bd4ef 23526 {
9c2799c2 23527 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
c19d1205
ZW		 23528 inst.size = (inst.instruction > 0xffff ? 4 : 2);
23529 if (inst.size_req && inst.size_req != inst.size)
b99bd4ef 23530 {
c19d1205 23531 as_bad (_("cannot honor width suffix -- `%s'"), str);
b99bd4ef
NC		 23532 return;
23533 }
23534 }
076d447c
PB		 23535
23536 /* Something has gone badly wrong if we try to relax a fixed size
477330fc 23537 instruction. */
9c2799c2 23538 gas_assert (inst.size_req == 0 || !inst.relax);
076d447c 23539
e74cfd16
PB		 23540 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
23541 *opcode->tvariant);
ee065d83 23542 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
fc289b0a
TP		 23543 set those bits when Thumb-2 32-bit instructions are seen. The impact
23544 of relaxable instructions will be considered later after we finish all
23545 relaxation. */
ff8646ee
TP		 23546 if (ARM_FEATURE_CORE_EQUAL (cpu_variant, arm_arch_any))
23547 variant = arm_arch_none;
23548 else
23549 variant = cpu_variant;
23550 if (inst.size == 4 && !t32_insn_ok (variant, opcode))
e74cfd16
PB		 23551 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
23552 arm_ext_v6t2);
cd000bff 23553
88714cb8
DG		 23554 check_neon_suffixes;
23555
cd000bff 23556 if (!inst.error)
c877a2f2
NC		 23557 {
23558 mapping_state (MAP_THUMB);
23559 }
c19d1205 23560 }
3e9e4fcf 23561 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
c19d1205 23562 {
845b51d6
PB		 23563 bfd_boolean is_bx;
23564
23565 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
23566 is_bx = (opcode->aencode == do_bx);
23567
c19d1205 23568 /* Check that this instruction is supported for this CPU. */
845b51d6
PB		 23569 if (!(is_bx && fix_v4bx)
23570 && !(opcode->avariant &&
23571 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
b99bd4ef 23572 {
84b52b66 23573 as_bad (_("selected processor does not support `%s' in ARM mode"), str);
c19d1205 23574 return;
b99bd4ef 23575 }
c19d1205 23576 if (inst.size_req)
b99bd4ef 23577 {
c19d1205
ZW		 23578 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
23579 return;
b99bd4ef
NC		 23580 }
23581
c19d1205
ZW		 23582 inst.instruction = opcode->avalue;
23583 if (opcode->tag == OT_unconditionalF)
eff0bc54 23584 inst.instruction |= 0xFU << 28;
c19d1205
ZW		 23585 else
23586 inst.instruction |= inst.cond << 28;
23587 inst.size = INSN_SIZE;
5be8be5d 23588 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
477330fc
RM		 23589 {
23590 it_fsm_pre_encode ();
23591 opcode->aencode ();
23592 it_fsm_post_encode ();
23593 }
ee065d83 23594 /* Arm mode bx is marked as both v4T and v5 because it's still required
477330fc 23595 on a hypothetical non-thumb v5 core. */
845b51d6 23596 if (is_bx)
e74cfd16 23597 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
ee065d83 23598 else
e74cfd16
PB		 23599 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
23600 *opcode->avariant);
88714cb8
DG		 23601
23602 check_neon_suffixes;
23603
cd000bff 23604 if (!inst.error)
c877a2f2
NC		 23605 {
23606 mapping_state (MAP_ARM);
23607 }
b99bd4ef 23608 }
3e9e4fcf
JB		 23609 else
23610 {
23611 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
23612 "-- `%s'"), str);
23613 return;
23614 }
c19d1205
ZW		 23615 output_inst (str);
23616}
b99bd4ef 23617
e07e6e58 23618static void
5ee91343 23619check_pred_blocks_finished (void)
e07e6e58
NC		 23620{
23621#ifdef OBJ_ELF
23622 asection *sect;
23623
23624 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
5ee91343
AV		 23625 if (seg_info (sect)->tc_segment_info_data.current_pred.state
23626 == MANUAL_PRED_BLOCK)
e07e6e58 23627 {
5ee91343
AV		 23628 if (now_pred.type == SCALAR_PRED)
23629 as_warn (_("section '%s' finished with an open IT block."),
23630 sect->name);
23631 else
23632 as_warn (_("section '%s' finished with an open VPT/VPST block."),
23633 sect->name);
e07e6e58
NC		 23634 }
23635#else
5ee91343
AV		 23636 if (now_pred.state == MANUAL_PRED_BLOCK)
23637 {
23638 if (now_pred.type == SCALAR_PRED)
23639 as_warn (_("file finished with an open IT block."));
23640 else
23641 as_warn (_("file finished with an open VPT/VPST block."));
23642 }
e07e6e58
NC		 23643#endif
23644}
23645
c19d1205
ZW		 23646/* Various frobbings of labels and their addresses. */
23647
23648void
23649arm_start_line_hook (void)
23650{
23651 last_label_seen = NULL;
b99bd4ef
NC		 23652}
23653
c19d1205
ZW		 23654void
23655arm_frob_label (symbolS * sym)
b99bd4ef 23656{
c19d1205 23657 last_label_seen = sym;
b99bd4ef 23658
c19d1205 23659 ARM_SET_THUMB (sym, thumb_mode);
b99bd4ef 23660
c19d1205
ZW		 23661#if defined OBJ_COFF || defined OBJ_ELF
23662 ARM_SET_INTERWORK (sym, support_interwork);
23663#endif
b99bd4ef 23664
e07e6e58
NC		 23665 force_automatic_it_block_close ();
23666
5f4273c7 23667 /* Note - do not allow local symbols (.Lxxx) to be labelled
c19d1205
ZW		 23668 as Thumb functions. This is because these labels, whilst
23669 they exist inside Thumb code, are not the entry points for
23670 possible ARM->Thumb calls. Also, these labels can be used
23671 as part of a computed goto or switch statement. eg gcc
23672 can generate code that looks like this:
b99bd4ef 23673
c19d1205
ZW		 23674 ldr r2, [pc, .Laaa]
23675 lsl r3, r3, #2
23676 ldr r2, [r3, r2]
23677 mov pc, r2
b99bd4ef 23678
c19d1205
ZW		 23679 .Lbbb: .word .Lxxx
23680 .Lccc: .word .Lyyy
23681 ..etc...
23682 .Laaa: .word Lbbb
b99bd4ef 23683
c19d1205
ZW		 23684 The first instruction loads the address of the jump table.
23685 The second instruction converts a table index into a byte offset.
23686 The third instruction gets the jump address out of the table.
23687 The fourth instruction performs the jump.
b99bd4ef 23688
c19d1205
ZW		 23689 If the address stored at .Laaa is that of a symbol which has the
23690 Thumb_Func bit set, then the linker will arrange for this address
23691 to have the bottom bit set, which in turn would mean that the
23692 address computation performed by the third instruction would end
23693 up with the bottom bit set. Since the ARM is capable of unaligned
23694 word loads, the instruction would then load the incorrect address
23695 out of the jump table, and chaos would ensue. */
23696 if (label_is_thumb_function_name
23697 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
fd361982 23698 && (bfd_section_flags (now_seg) & SEC_CODE) != 0)
b99bd4ef 23699 {
c19d1205
ZW		 23700 /* When the address of a Thumb function is taken the bottom
23701 bit of that address should be set. This will allow
23702 interworking between Arm and Thumb functions to work
23703 correctly. */
b99bd4ef 23704
c19d1205 23705 THUMB_SET_FUNC (sym, 1);
b99bd4ef 23706
c19d1205 23707 label_is_thumb_function_name = FALSE;
b99bd4ef 23708 }
07a53e5c 23709
07a53e5c 23710 dwarf2_emit_label (sym);
b99bd4ef
NC		 23711}
23712
c921be7d 23713bfd_boolean
c19d1205 23714arm_data_in_code (void)
b99bd4ef 23715{
c19d1205 23716 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
b99bd4ef 23717 {
c19d1205
ZW		 23718 *input_line_pointer = '/';
23719 input_line_pointer += 5;
23720 *input_line_pointer = 0;
c921be7d 23721 return TRUE;
b99bd4ef
NC		 23722 }
23723
c921be7d 23724 return FALSE;
b99bd4ef
NC		 23725}
23726
c19d1205
ZW		 23727char *
23728arm_canonicalize_symbol_name (char * name)
b99bd4ef 23729{
c19d1205 23730 int len;
b99bd4ef 23731
c19d1205
ZW		 23732 if (thumb_mode && (len = strlen (name)) > 5
23733 && streq (name + len - 5, "/data"))
23734 *(name + len - 5) = 0;
b99bd4ef 23735
c19d1205 23736 return name;
b99bd4ef 23737}
c19d1205
ZW		 23738\f
23739/* Table of all register names defined by default. The user can
23740 define additional names with .req. Note that all register names
23741 should appear in both upper and lowercase variants. Some registers
23742 also have mixed-case names. */
b99bd4ef 23743
dcbf9037 23744#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
c19d1205 23745#define REGNUM(p,n,t) REGDEF(p##n, n, t)
5287ad62 23746#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
c19d1205
ZW		 23747#define REGSET(p,t) \
23748 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
23749 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
23750 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
23751 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
5287ad62
JB		 23752#define REGSETH(p,t) \
23753 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
23754 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
23755 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
23756 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
23757#define REGSET2(p,t) \
23758 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
23759 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
23760 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
23761 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
90ec0d68
MGD		 23762#define SPLRBANK(base,bank,t) \
23763 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
23764 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
23765 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
23766 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
23767 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
23768 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
7ed4c4c5 23769
c19d1205 23770static const struct reg_entry reg_names[] =
7ed4c4c5 23771{
c19d1205
ZW		 23772 /* ARM integer registers. */
23773 REGSET(r, RN), REGSET(R, RN),
7ed4c4c5 23774
c19d1205
ZW		 23775 /* ATPCS synonyms. */
23776 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
23777 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
23778 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
7ed4c4c5 23779
c19d1205
ZW		 23780 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
23781 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
23782 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
7ed4c4c5 23783
c19d1205
ZW		 23784 /* Well-known aliases. */
23785 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
23786 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
23787
23788 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
23789 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
23790
1b883319
AV		 23791 /* Defining the new Zero register from ARMv8.1-M. */
23792 REGDEF(zr,15,ZR),
23793 REGDEF(ZR,15,ZR),
23794
c19d1205
ZW		 23795 /* Coprocessor numbers. */
23796 REGSET(p, CP), REGSET(P, CP),
23797
23798 /* Coprocessor register numbers. The "cr" variants are for backward
23799 compatibility. */
23800 REGSET(c, CN), REGSET(C, CN),
23801 REGSET(cr, CN), REGSET(CR, CN),
23802
90ec0d68
MGD		 23803 /* ARM banked registers. */
23804 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
23805 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
23806 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
23807 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
23808 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
23809 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
23810 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
23811
23812 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
23813 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
23814 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
23815 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
23816 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
1472d06f 23817 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB),
90ec0d68
MGD		 23818 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
23819 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
23820
23821 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
23822 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
23823 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
23824 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
23825 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
23826 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
23827 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
fa94de6b 23828 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
90ec0d68
MGD		 23829 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
23830
c19d1205
ZW		 23831 /* FPA registers. */
23832 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
23833 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
23834
23835 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
23836 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
23837
23838 /* VFP SP registers. */
5287ad62
JB		 23839 REGSET(s,VFS), REGSET(S,VFS),
23840 REGSETH(s,VFS), REGSETH(S,VFS),
c19d1205
ZW		 23841
23842 /* VFP DP Registers. */
5287ad62
JB		 23843 REGSET(d,VFD), REGSET(D,VFD),
23844 /* Extra Neon DP registers. */
23845 REGSETH(d,VFD), REGSETH(D,VFD),
23846
23847 /* Neon QP registers. */
23848 REGSET2(q,NQ), REGSET2(Q,NQ),
c19d1205
ZW		 23849
23850 /* VFP control registers. */
23851 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
23852 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
cd2cf30b
PB		 23853 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
23854 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
23855 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
23856 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
40c7d507 23857 REGDEF(mvfr2,5,VFC), REGDEF(MVFR2,5,VFC),
ba6cd17f
SD		 23858 REGDEF(fpscr_nzcvqc,2,VFC), REGDEF(FPSCR_nzcvqc,2,VFC),
23859 REGDEF(vpr,12,VFC), REGDEF(VPR,12,VFC),
23860 REGDEF(fpcxt_ns,14,VFC), REGDEF(FPCXT_NS,14,VFC),
23861 REGDEF(fpcxt_s,15,VFC), REGDEF(FPCXT_S,15,VFC),
c19d1205
ZW		 23862
23863 /* Maverick DSP coprocessor registers. */
23864 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
23865 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
23866
23867 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
23868 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
23869 REGDEF(dspsc,0,DSPSC),
23870
23871 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
23872 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
23873 REGDEF(DSPSC,0,DSPSC),
23874
23875 /* iWMMXt data registers - p0, c0-15. */
23876 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
23877
23878 /* iWMMXt control registers - p1, c0-3. */
23879 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
23880 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
23881 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
23882 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
23883
23884 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
23885 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
23886 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
23887 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
23888 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
23889
23890 /* XScale accumulator registers. */
23891 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
23892};
23893#undef REGDEF
23894#undef REGNUM
23895#undef REGSET
7ed4c4c5 23896
c19d1205
ZW		 23897/* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
23898 within psr_required_here. */
23899static const struct asm_psr psrs[] =
23900{
23901 /* Backward compatibility notation. Note that "all" is no longer
23902 truly all possible PSR bits. */
23903 {"all", PSR_c | PSR_f},
23904 {"flg", PSR_f},
23905 {"ctl", PSR_c},
23906
23907 /* Individual flags. */
23908 {"f", PSR_f},
23909 {"c", PSR_c},
23910 {"x", PSR_x},
23911 {"s", PSR_s},
59b42a0d 23912
c19d1205
ZW		 23913 /* Combinations of flags. */
23914 {"fs", PSR_f | PSR_s},
23915 {"fx", PSR_f | PSR_x},
23916 {"fc", PSR_f | PSR_c},
23917 {"sf", PSR_s | PSR_f},
23918 {"sx", PSR_s | PSR_x},
23919 {"sc", PSR_s | PSR_c},
23920 {"xf", PSR_x | PSR_f},
23921 {"xs", PSR_x | PSR_s},
23922 {"xc", PSR_x | PSR_c},
23923 {"cf", PSR_c | PSR_f},
23924 {"cs", PSR_c | PSR_s},
23925 {"cx", PSR_c | PSR_x},
23926 {"fsx", PSR_f | PSR_s | PSR_x},
23927 {"fsc", PSR_f | PSR_s | PSR_c},
23928 {"fxs", PSR_f | PSR_x | PSR_s},
23929 {"fxc", PSR_f | PSR_x | PSR_c},
23930 {"fcs", PSR_f | PSR_c | PSR_s},
23931 {"fcx", PSR_f | PSR_c | PSR_x},
23932 {"sfx", PSR_s | PSR_f | PSR_x},
23933 {"sfc", PSR_s | PSR_f | PSR_c},
23934 {"sxf", PSR_s | PSR_x | PSR_f},
23935 {"sxc", PSR_s | PSR_x | PSR_c},
23936 {"scf", PSR_s | PSR_c | PSR_f},
23937 {"scx", PSR_s | PSR_c | PSR_x},
23938 {"xfs", PSR_x | PSR_f | PSR_s},
23939 {"xfc", PSR_x | PSR_f | PSR_c},
23940 {"xsf", PSR_x | PSR_s | PSR_f},
23941 {"xsc", PSR_x | PSR_s | PSR_c},
23942 {"xcf", PSR_x | PSR_c | PSR_f},
23943 {"xcs", PSR_x | PSR_c | PSR_s},
23944 {"cfs", PSR_c | PSR_f | PSR_s},
23945 {"cfx", PSR_c | PSR_f | PSR_x},
23946 {"csf", PSR_c | PSR_s | PSR_f},
23947 {"csx", PSR_c | PSR_s | PSR_x},
23948 {"cxf", PSR_c | PSR_x | PSR_f},
23949 {"cxs", PSR_c | PSR_x | PSR_s},
23950 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
23951 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
23952 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
23953 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
23954 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
23955 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
23956 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
23957 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
23958 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
23959 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
23960 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
23961 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
23962 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
23963 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
23964 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
23965 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
23966 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
23967 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
23968 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
23969 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
23970 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
23971 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
23972 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
23973 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
23974};
23975
62b3e311
PB		 23976/* Table of V7M psr names. */
23977static const struct asm_psr v7m_psrs[] =
23978{
1a336194
TP		 23979 {"apsr", 0x0 }, {"APSR", 0x0 },
23980 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
23981 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
23982 {"psr", 0x3 }, {"PSR", 0x3 },
23983 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
23984 {"ipsr", 0x5 }, {"IPSR", 0x5 },
23985 {"epsr", 0x6 }, {"EPSR", 0x6 },
23986 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
23987 {"msp", 0x8 }, {"MSP", 0x8 },
23988 {"psp", 0x9 }, {"PSP", 0x9 },
23989 {"msplim", 0xa }, {"MSPLIM", 0xa },
23990 {"psplim", 0xb }, {"PSPLIM", 0xb },
23991 {"primask", 0x10}, {"PRIMASK", 0x10},
23992 {"basepri", 0x11}, {"BASEPRI", 0x11},
23993 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
1a336194
TP		 23994 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
23995 {"control", 0x14}, {"CONTROL", 0x14},
23996 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
23997 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
23998 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
23999 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
24000 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
24001 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
24002 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
24003 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
24004 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
62b3e311
PB		 24005};
24006
c19d1205
ZW		 24007/* Table of all shift-in-operand names. */
24008static const struct asm_shift_name shift_names [] =
b99bd4ef 24009{
c19d1205
ZW		 24010 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
24011 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
24012 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
24013 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
24014 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
f5f10c66
AV		 24015 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX },
24016 { "uxtw", SHIFT_UXTW}, { "UXTW", SHIFT_UXTW}
c19d1205 24017};
b99bd4ef 24018
c19d1205
ZW		 24019/* Table of all explicit relocation names. */
24020#ifdef OBJ_ELF
24021static struct reloc_entry reloc_names[] =
24022{
24023 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
24024 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
24025 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
24026 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
24027 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
24028 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
24029 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
24030 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
24031 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
24032 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
b43420e6 24033 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
0855e32b
NS		 24034 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
24035 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
477330fc 24036 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
0855e32b 24037 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
477330fc 24038 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
0855e32b 24039 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
188fd7ae
CL		 24040 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ},
24041 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC },
24042 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC },
24043 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC },
24044 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC },
24045 { "funcdesc", BFD_RELOC_ARM_FUNCDESC },
5c5a4843
CL		 24046 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC },
24047 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC }, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC },
24048 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC }, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC },
24049 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC }, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC },
c19d1205
ZW		 24050};
24051#endif
b99bd4ef 24052
5ee91343 24053/* Table of all conditional affixes. */
c19d1205
ZW		 24054static const struct asm_cond conds[] =
24055{
24056 {"eq", 0x0},
24057 {"ne", 0x1},
24058 {"cs", 0x2}, {"hs", 0x2},
24059 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
24060 {"mi", 0x4},
24061 {"pl", 0x5},
24062 {"vs", 0x6},
24063 {"vc", 0x7},
24064 {"hi", 0x8},
24065 {"ls", 0x9},
24066 {"ge", 0xa},
24067 {"lt", 0xb},
24068 {"gt", 0xc},
24069 {"le", 0xd},
24070 {"al", 0xe}
24071};
5ee91343
AV		 24072static const struct asm_cond vconds[] =
24073{
24074 {"t", 0xf},
24075 {"e", 0x10}
24076};
bfae80f2 24077
e797f7e0 24078#define UL_BARRIER(L,U,CODE,FEAT) \
823d2571
TG		 24079 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
24080 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
e797f7e0 24081
62b3e311
PB		 24082static struct asm_barrier_opt barrier_opt_names[] =
24083{
e797f7e0
MGD		 24084 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER),
24085 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER),
24086 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8),
24087 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER),
24088 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER),
24089 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER),
24090 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER),
24091 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8),
24092 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER),
24093 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER),
24094 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER),
24095 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER),
24096 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8),
24097 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER),
24098 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER),
24099 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8)
62b3e311
PB		 24100};
24101
e797f7e0
MGD		 24102#undef UL_BARRIER
24103
c19d1205
ZW		 24104/* Table of ARM-format instructions. */
24105
24106/* Macros for gluing together operand strings. N.B. In all cases
24107 other than OPS0, the trailing OP_stop comes from default
24108 zero-initialization of the unspecified elements of the array. */
24109#define OPS0() { OP_stop, }
24110#define OPS1(a) { OP_##a, }
24111#define OPS2(a,b) { OP_##a,OP_##b, }
24112#define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
24113#define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
24114#define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
24115#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
24116
5be8be5d
DG		 24117/* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
24118 This is useful when mixing operands for ARM and THUMB, i.e. using the
24119 MIX_ARM_THUMB_OPERANDS macro.
24120 In order to use these macros, prefix the number of operands with _
24121 e.g. _3. */
24122#define OPS_1(a) { a, }
24123#define OPS_2(a,b) { a,b, }
24124#define OPS_3(a,b,c) { a,b,c, }
24125#define OPS_4(a,b,c,d) { a,b,c,d, }
24126#define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
24127#define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
24128
c19d1205
ZW		 24129/* These macros abstract out the exact format of the mnemonic table and
24130 save some repeated characters. */
24131
24132/* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
24133#define TxCE(mnem, op, top, nops, ops, ae, te) \
21d799b5 24134 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
5ee91343 24135 THUMB_VARIANT, do_##ae, do_##te, 0 }
c19d1205
ZW		 24136
24137/* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
24138 a T_MNEM_xyz enumerator. */
24139#define TCE(mnem, aop, top, nops, ops, ae, te) \
e07e6e58 24140 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
c19d1205 24141#define tCE(mnem, aop, top, nops, ops, ae, te) \
21d799b5 24142 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
c19d1205
ZW		 24143
24144/* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
24145 infix after the third character. */
24146#define TxC3(mnem, op, top, nops, ops, ae, te) \
21d799b5 24147 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
5ee91343 24148 THUMB_VARIANT, do_##ae, do_##te, 0 }
088fa78e 24149#define TxC3w(mnem, op, top, nops, ops, ae, te) \
21d799b5 24150 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
5ee91343 24151 THUMB_VARIANT, do_##ae, do_##te, 0 }
c19d1205 24152#define TC3(mnem, aop, top, nops, ops, ae, te) \
e07e6e58 24153 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
088fa78e 24154#define TC3w(mnem, aop, top, nops, ops, ae, te) \
e07e6e58 24155 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
c19d1205 24156#define tC3(mnem, aop, top, nops, ops, ae, te) \
21d799b5 24157 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
088fa78e 24158#define tC3w(mnem, aop, top, nops, ops, ae, te) \
21d799b5 24159 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
c19d1205 24160
c19d1205 24161/* Mnemonic that cannot be conditionalized. The ARM condition-code
dfa9f0d5
PB		 24162 field is still 0xE. Many of the Thumb variants can be executed
24163 conditionally, so this is checked separately. */
c19d1205 24164#define TUE(mnem, op, top, nops, ops, ae, te) \
21d799b5 24165 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
5ee91343 24166 THUMB_VARIANT, do_##ae, do_##te, 0 }
c19d1205 24167
dd5181d5
KT		 24168/* Same as TUE but the encoding function for ARM and Thumb modes is the same.
24169 Used by mnemonics that have very minimal differences in the encoding for
24170 ARM and Thumb variants and can be handled in a common function. */
24171#define TUEc(mnem, op, top, nops, ops, en) \
24172 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
5ee91343 24173 THUMB_VARIANT, do_##en, do_##en, 0 }
dd5181d5 24174
c19d1205
ZW		 24175/* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
24176 condition code field. */
24177#define TUF(mnem, op, top, nops, ops, ae, te) \
21d799b5 24178 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
5ee91343 24179 THUMB_VARIANT, do_##ae, do_##te, 0 }
c19d1205
ZW		 24180
24181/* ARM-only variants of all the above. */
6a86118a 24182#define CE(mnem, op, nops, ops, ae) \
5ee91343 24183 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
6a86118a
NC		 24184
24185#define C3(mnem, op, nops, ops, ae) \
5ee91343 24186 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
6a86118a 24187
cf3cf39d
TP		 24188/* Thumb-only variants of TCE and TUE. */
24189#define ToC(mnem, top, nops, ops, te) \
24190 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
5ee91343 24191 do_##te, 0 }
cf3cf39d
TP		 24192
24193#define ToU(mnem, top, nops, ops, te) \
24194 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
5ee91343 24195 NULL, do_##te, 0 }
cf3cf39d 24196
4389b29a
AV		 24197/* T_MNEM_xyz enumerator variants of ToC. */
24198#define toC(mnem, top, nops, ops, te) \
24199 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
5ee91343 24200 do_##te, 0 }
4389b29a 24201
f6b2b12d
AV		 24202/* T_MNEM_xyz enumerator variants of ToU. */
24203#define toU(mnem, top, nops, ops, te) \
24204 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
5ee91343 24205 NULL, do_##te, 0 }
f6b2b12d 24206
e3cb604e
PB		 24207/* Legacy mnemonics that always have conditional infix after the third
24208 character. */
24209#define CL(mnem, op, nops, ops, ae) \
21d799b5 24210 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
5ee91343 24211 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
e3cb604e 24212
8f06b2d8
PB		 24213/* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
24214#define cCE(mnem, op, nops, ops, ae) \
5ee91343 24215 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
8f06b2d8 24216
57785aa2
AV		 24217/* mov instructions that are shared between coprocessor and MVE. */
24218#define mcCE(mnem, op, nops, ops, ae) \
24219 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
24220
e3cb604e
PB		 24221/* Legacy coprocessor instructions where conditional infix and conditional
24222 suffix are ambiguous. For consistency this includes all FPA instructions,
24223 not just the potentially ambiguous ones. */
24224#define cCL(mnem, op, nops, ops, ae) \
21d799b5 24225 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
5ee91343 24226 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
e3cb604e
PB		 24227
24228/* Coprocessor, takes either a suffix or a position-3 infix
24229 (for an FPA corner case). */
24230#define C3E(mnem, op, nops, ops, ae) \
21d799b5 24231 { mnem, OPS##nops ops, OT_csuf_or_in3, \
5ee91343 24232 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
8f06b2d8 24233
6a86118a 24234#define xCM_(m1, m2, m3, op, nops, ops, ae) \
21d799b5
NC		 24235 { m1 #m2 m3, OPS##nops ops, \
24236 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
5ee91343 24237 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
6a86118a
NC		 24238
24239#define CM(m1, m2, op, nops, ops, ae) \
e07e6e58
NC		 24240 xCM_ (m1, , m2, op, nops, ops, ae), \
24241 xCM_ (m1, eq, m2, op, nops, ops, ae), \
24242 xCM_ (m1, ne, m2, op, nops, ops, ae), \
24243 xCM_ (m1, cs, m2, op, nops, ops, ae), \
24244 xCM_ (m1, hs, m2, op, nops, ops, ae), \
24245 xCM_ (m1, cc, m2, op, nops, ops, ae), \
24246 xCM_ (m1, ul, m2, op, nops, ops, ae), \
24247 xCM_ (m1, lo, m2, op, nops, ops, ae), \
24248 xCM_ (m1, mi, m2, op, nops, ops, ae), \
24249 xCM_ (m1, pl, m2, op, nops, ops, ae), \
24250 xCM_ (m1, vs, m2, op, nops, ops, ae), \
24251 xCM_ (m1, vc, m2, op, nops, ops, ae), \
24252 xCM_ (m1, hi, m2, op, nops, ops, ae), \
24253 xCM_ (m1, ls, m2, op, nops, ops, ae), \
24254 xCM_ (m1, ge, m2, op, nops, ops, ae), \
24255 xCM_ (m1, lt, m2, op, nops, ops, ae), \
24256 xCM_ (m1, gt, m2, op, nops, ops, ae), \
24257 xCM_ (m1, le, m2, op, nops, ops, ae), \
24258 xCM_ (m1, al, m2, op, nops, ops, ae)
6a86118a
NC		 24259
24260#define UE(mnem, op, nops, ops, ae) \
5ee91343 24261 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
6a86118a
NC		 24262
24263#define UF(mnem, op, nops, ops, ae) \
5ee91343 24264 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
6a86118a 24265
5287ad62
JB		 24266/* Neon data-processing. ARM versions are unconditional with cond=0xf.
24267 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
24268 use the same encoding function for each. */
24269#define NUF(mnem, op, nops, ops, enc) \
24270 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
5ee91343 24271 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
5287ad62
JB		 24272
24273/* Neon data processing, version which indirects through neon_enc_tab for
24274 the various overloaded versions of opcodes. */
24275#define nUF(mnem, op, nops, ops, enc) \
21d799b5 24276 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
5ee91343 24277 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
5287ad62
JB		 24278
24279/* Neon insn with conditional suffix for the ARM version, non-overloaded
24280 version. */
5ee91343 24281#define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
037e8744 24282 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
5ee91343 24283 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
5287ad62 24284
037e8744 24285#define NCE(mnem, op, nops, ops, enc) \
5ee91343 24286 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
037e8744
JB		 24287
24288#define NCEF(mnem, op, nops, ops, enc) \
5ee91343 24289 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
037e8744 24290
5287ad62 24291/* Neon insn with conditional suffix for the ARM version, overloaded types. */
5ee91343 24292#define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
21d799b5 24293 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
5ee91343 24294 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
5287ad62 24295
037e8744 24296#define nCE(mnem, op, nops, ops, enc) \
5ee91343 24297 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
037e8744
JB		 24298
24299#define nCEF(mnem, op, nops, ops, enc) \
5ee91343
AV		 24300 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
24301
24302/* */
24303#define mCEF(mnem, op, nops, ops, enc) \
a302e574 24304 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
5ee91343
AV		 24305 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24306
24307
24308/* nCEF but for MVE predicated instructions. */
24309#define mnCEF(mnem, op, nops, ops, enc) \
24310 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
24311
24312/* nCE but for MVE predicated instructions. */
24313#define mnCE(mnem, op, nops, ops, enc) \
24314 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
037e8744 24315
5ee91343
AV		 24316/* NUF but for potentially MVE predicated instructions. */
24317#define MNUF(mnem, op, nops, ops, enc) \
24318 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
24319 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24320
24321/* nUF but for potentially MVE predicated instructions. */
24322#define mnUF(mnem, op, nops, ops, enc) \
24323 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
24324 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24325
24326/* ToC but for potentially MVE predicated instructions. */
24327#define mToC(mnem, top, nops, ops, te) \
24328 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
24329 do_##te, 1 }
24330
24331/* NCE but for MVE predicated instructions. */
24332#define MNCE(mnem, op, nops, ops, enc) \
24333 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
24334
24335/* NCEF but for MVE predicated instructions. */
24336#define MNCEF(mnem, op, nops, ops, enc) \
24337 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
c19d1205
ZW		 24338#define do_0 0
24339
c19d1205 24340static const struct asm_opcode insns[] =
bfae80f2 24341{
74db7efb
NC		 24342#define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
24343#define THUMB_VARIANT & arm_ext_v4t
21d799b5
NC		 24344 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
24345 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
24346 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
24347 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
24348 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
24349 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
24350 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
24351 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
24352 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
24353 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
24354 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
24355 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
24356 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
24357 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
24358 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
24359 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
c19d1205
ZW		 24360
24361 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
24362 for setting PSR flag bits. They are obsolete in V6 and do not
24363 have Thumb equivalents. */
21d799b5
NC		 24364 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
24365 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
24366 CL("tstp", 110f000, 2, (RR, SH), cmp),
24367 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
24368 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
24369 CL("cmpp", 150f000, 2, (RR, SH), cmp),
24370 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
24371 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
24372 CL("cmnp", 170f000, 2, (RR, SH), cmp),
24373
24374 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
72d98d16 24375 tC3("movs", 1b00000, _movs, 2, (RR, SHG), mov, t_mov_cmp),
21d799b5
NC		 24376 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
24377 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
24378
24379 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
5be8be5d
DG		 24380 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
24381 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
24382 OP_RRnpc),
24383 OP_ADDRGLDR),ldst, t_ldst),
24384 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
21d799b5
NC		 24385
24386 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
24387 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
24388 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
24389 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
24390 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
24391 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
24392
21d799b5
NC		 24393 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
24394 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
bfae80f2 24395
c19d1205 24396 /* Pseudo ops. */
21d799b5 24397 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
2fc8bdac 24398 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
21d799b5 24399 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
74db7efb 24400 tCE("udf", 7f000f0, _udf, 1, (oIffffb), bkpt, t_udf),
c19d1205
ZW		 24401
24402 /* Thumb-compatibility pseudo ops. */
21d799b5
NC		 24403 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
24404 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
24405 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
24406 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
24407 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
24408 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
24409 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
24410 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
24411 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
24412 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
24413 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
24414 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
c19d1205 24415
16a4cf17 24416 /* These may simplify to neg. */
21d799b5
NC		 24417 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
24418 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
16a4cf17 24419
173205ca
TP		 24420#undef THUMB_VARIANT
24421#define THUMB_VARIANT & arm_ext_os
24422
24423 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
24424 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
24425
c921be7d
NC		 24426#undef THUMB_VARIANT
24427#define THUMB_VARIANT & arm_ext_v6
24428
21d799b5 24429 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
c19d1205
ZW		 24430
24431 /* V1 instructions with no Thumb analogue prior to V6T2. */
c921be7d
NC		 24432#undef THUMB_VARIANT
24433#define THUMB_VARIANT & arm_ext_v6t2
24434
21d799b5
NC		 24435 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
24436 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
24437 CL("teqp", 130f000, 2, (RR, SH), cmp),
c19d1205 24438
5be8be5d
DG		 24439 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
24440 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
24441 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
24442 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
c19d1205 24443
21d799b5
NC		 24444 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
24445 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
c19d1205 24446
21d799b5
NC		 24447 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
24448 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
c19d1205
ZW		 24449
24450 /* V1 instructions with no Thumb analogue at all. */
21d799b5 24451 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
c19d1205
ZW		 24452 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
24453
24454 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
24455 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
24456 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
24457 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
24458 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
24459 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
24460 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
24461 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
24462
c921be7d
NC		 24463#undef ARM_VARIANT
24464#define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
24465#undef THUMB_VARIANT
24466#define THUMB_VARIANT & arm_ext_v4t
24467
21d799b5
NC		 24468 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
24469 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
c19d1205 24470
c921be7d
NC		 24471#undef THUMB_VARIANT
24472#define THUMB_VARIANT & arm_ext_v6t2
24473
21d799b5 24474 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
c19d1205
ZW		 24475 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
24476
24477 /* Generic coprocessor instructions. */
21d799b5
NC		 24478 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
24479 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
24480 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
24481 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
24482 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
24483 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
db472d6f 24484 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
c19d1205 24485
c921be7d
NC		 24486#undef ARM_VARIANT
24487#define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
24488
21d799b5 24489 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
c19d1205
ZW		 24490 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
24491
c921be7d
NC		 24492#undef ARM_VARIANT
24493#define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
24494#undef THUMB_VARIANT
24495#define THUMB_VARIANT & arm_ext_msr
24496
d2cd1205
JB		 24497 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
24498 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
c19d1205 24499
c921be7d
NC		 24500#undef ARM_VARIANT
24501#define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
24502#undef THUMB_VARIANT
24503#define THUMB_VARIANT & arm_ext_v6t2
24504
21d799b5
NC		 24505 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
24506 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
24507 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
24508 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
24509 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
24510 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
24511 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
24512 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
c19d1205 24513
c921be7d
NC		 24514#undef ARM_VARIANT
24515#define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
24516#undef THUMB_VARIANT
24517#define THUMB_VARIANT & arm_ext_v4t
24518
5be8be5d
DG		 24519 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
24520 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
24521 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
24522 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
56c0a61f
RE		 24523 tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
24524 tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
c19d1205 24525
c921be7d
NC		 24526#undef ARM_VARIANT
24527#define ARM_VARIANT & arm_ext_v4t_5
24528
c19d1205
ZW		 24529 /* ARM Architecture 4T. */
24530 /* Note: bx (and blx) are required on V5, even if the processor does
24531 not support Thumb. */
21d799b5 24532 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
c19d1205 24533
c921be7d
NC		 24534#undef ARM_VARIANT
24535#define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
24536#undef THUMB_VARIANT
24537#define THUMB_VARIANT & arm_ext_v5t
24538
c19d1205
ZW		 24539 /* Note: blx has 2 variants; the .value coded here is for
24540 BLX(2). Only this variant has conditional execution. */
21d799b5
NC		 24541 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
24542 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
c19d1205 24543
c921be7d
NC		 24544#undef THUMB_VARIANT
24545#define THUMB_VARIANT & arm_ext_v6t2
24546
21d799b5
NC		 24547 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
24548 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
24549 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
24550 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
24551 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
24552 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
24553 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
24554 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
c19d1205 24555
c921be7d 24556#undef ARM_VARIANT
74db7efb
NC		 24557#define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
24558#undef THUMB_VARIANT
24559#define THUMB_VARIANT & arm_ext_v5exp
c921be7d 24560
21d799b5
NC		 24561 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
24562 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
24563 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
24564 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
c19d1205 24565
21d799b5
NC		 24566 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
24567 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
c19d1205 24568
21d799b5
NC		 24569 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
24570 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
24571 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
24572 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
c19d1205 24573
21d799b5
NC		 24574 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
24575 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
24576 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
24577 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
c19d1205 24578
21d799b5
NC		 24579 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
24580 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
c19d1205 24581
03ee1b7f
NC		 24582 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
24583 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
24584 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
24585 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
c19d1205 24586
c921be7d 24587#undef ARM_VARIANT
74db7efb
NC		 24588#define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
24589#undef THUMB_VARIANT
24590#define THUMB_VARIANT & arm_ext_v6t2
c921be7d 24591
21d799b5 24592 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
5be8be5d
DG		 24593 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
24594 ldrd, t_ldstd),
24595 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
24596 ADDRGLDRS), ldrd, t_ldstd),
c19d1205 24597
21d799b5
NC		 24598 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
24599 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
c19d1205 24600
c921be7d
NC		 24601#undef ARM_VARIANT
24602#define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
24603
21d799b5 24604 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
c19d1205 24605
c921be7d
NC		 24606#undef ARM_VARIANT
24607#define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
24608#undef THUMB_VARIANT
24609#define THUMB_VARIANT & arm_ext_v6
24610
21d799b5
NC		 24611 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
24612 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
24613 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
24614 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
24615 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
24616 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
24617 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
24618 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
24619 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
24620 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
c19d1205 24621
c921be7d 24622#undef THUMB_VARIANT
ff8646ee 24623#define THUMB_VARIANT & arm_ext_v6t2_v8m
c921be7d 24624
5be8be5d
DG		 24625 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
24626 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
24627 strex, t_strex),
ff8646ee
TP		 24628#undef THUMB_VARIANT
24629#define THUMB_VARIANT & arm_ext_v6t2
24630
21d799b5
NC		 24631 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
24632 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
62b3e311 24633
21d799b5
NC		 24634 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
24635 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
62b3e311 24636
9e3c6df6 24637/* ARM V6 not included in V7M. */
c921be7d
NC		 24638#undef THUMB_VARIANT
24639#define THUMB_VARIANT & arm_ext_v6_notm
9e3c6df6 24640 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
d709e4e6 24641 TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe),
9e3c6df6
PB		 24642 UF(rfeib, 9900a00, 1, (RRw), rfe),
24643 UF(rfeda, 8100a00, 1, (RRw), rfe),
24644 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
24645 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
d709e4e6
RE		 24646 UF(rfefa, 8100a00, 1, (RRw), rfe),
24647 TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe),
24648 UF(rfeed, 9900a00, 1, (RRw), rfe),
9e3c6df6 24649 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
d709e4e6
RE		 24650 TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
24651 TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
9e3c6df6 24652 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
d709e4e6 24653 UF(srsfa, 9c00500, 2, (oRRw, I31w), srs),
9e3c6df6 24654 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
d709e4e6 24655 UF(srsed, 8400500, 2, (oRRw, I31w), srs),
9e3c6df6 24656 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
d709e4e6 24657 TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
941c9cad 24658 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
c921be7d 24659
9e3c6df6
PB		 24660/* ARM V6 not included in V7M (eg. integer SIMD). */
24661#undef THUMB_VARIANT
24662#define THUMB_VARIANT & arm_ext_v6_dsp
21d799b5
NC		 24663 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
24664 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
24665 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24666 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24667 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 24668 /* Old name for QASX. */
74db7efb 24669 TCE("qaddsubx",6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5 24670 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 24671 /* Old name for QSAX. */
74db7efb 24672 TCE("qsubaddx",6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC		 24673 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24674 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24675 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24676 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24677 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 24678 /* Old name for SASX. */
74db7efb 24679 TCE("saddsubx",6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC		 24680 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24681 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
74db7efb 24682 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 24683 /* Old name for SHASX. */
21d799b5 24684 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
74db7efb 24685 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 24686 /* Old name for SHSAX. */
21d799b5
NC		 24687 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24688 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24689 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24690 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 24691 /* Old name for SSAX. */
74db7efb 24692 TCE("ssubaddx",6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC		 24693 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24694 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24695 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24696 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24697 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 24698 /* Old name for UASX. */
74db7efb 24699 TCE("uaddsubx",6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC		 24700 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24701 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
74db7efb 24702 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 24703 /* Old name for UHASX. */
21d799b5
NC		 24704 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24705 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 24706 /* Old name for UHSAX. */
21d799b5
NC		 24707 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24708 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24709 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24710 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24711 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
74db7efb 24712 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 24713 /* Old name for UQASX. */
21d799b5
NC		 24714 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24715 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 24716 /* Old name for UQSAX. */
21d799b5
NC		 24717 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24718 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24719 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24720 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24721 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 24722 /* Old name for USAX. */
74db7efb 24723 TCE("usubaddx",6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5 24724 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC		 24725 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
24726 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
24727 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
24728 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
24729 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
24730 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
24731 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
24732 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
24733 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
24734 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
24735 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
24736 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
24737 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
24738 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
24739 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
24740 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
24741 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
24742 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
24743 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
24744 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
24745 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
24746 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
24747 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
24748 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
24749 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
24750 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
24751 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
21d799b5
NC		 24752 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
24753 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
24754 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
24755 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
24756 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
c19d1205 24757
c921be7d 24758#undef ARM_VARIANT
55e8aae7 24759#define ARM_VARIANT & arm_ext_v6k_v6t2
c921be7d 24760#undef THUMB_VARIANT
55e8aae7 24761#define THUMB_VARIANT & arm_ext_v6k_v6t2
c921be7d 24762
21d799b5
NC		 24763 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
24764 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
24765 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
24766 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
c19d1205 24767
c921be7d
NC		 24768#undef THUMB_VARIANT
24769#define THUMB_VARIANT & arm_ext_v6_notm
5be8be5d
DG		 24770 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
24771 ldrexd, t_ldrexd),
24772 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
24773 RRnpcb), strexd, t_strexd),
ebdca51a 24774
c921be7d 24775#undef THUMB_VARIANT
ff8646ee 24776#define THUMB_VARIANT & arm_ext_v6t2_v8m
5be8be5d
DG		 24777 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
24778 rd_rn, rd_rn),
24779 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
24780 rd_rn, rd_rn),
24781 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
877807f8 24782 strex, t_strexbh),
5be8be5d 24783 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
877807f8 24784 strex, t_strexbh),
21d799b5 24785 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
c19d1205 24786
c921be7d 24787#undef ARM_VARIANT
f4c65163 24788#define ARM_VARIANT & arm_ext_sec
74db7efb 24789#undef THUMB_VARIANT
f4c65163 24790#define THUMB_VARIANT & arm_ext_sec
c921be7d 24791
21d799b5 24792 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
c19d1205 24793
90ec0d68
MGD		 24794#undef ARM_VARIANT
24795#define ARM_VARIANT & arm_ext_virt
24796#undef THUMB_VARIANT
24797#define THUMB_VARIANT & arm_ext_virt
24798
24799 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
24800 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
24801
ddfded2f
MW		 24802#undef ARM_VARIANT
24803#define ARM_VARIANT & arm_ext_pan
24804#undef THUMB_VARIANT
24805#define THUMB_VARIANT & arm_ext_pan
24806
24807 TUF("setpan", 1100000, b610, 1, (I7), setpan, t_setpan),
24808
c921be7d 24809#undef ARM_VARIANT
74db7efb 24810#define ARM_VARIANT & arm_ext_v6t2
f4c65163
MGD		 24811#undef THUMB_VARIANT
24812#define THUMB_VARIANT & arm_ext_v6t2
c921be7d 24813
21d799b5
NC		 24814 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
24815 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
24816 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
24817 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
c19d1205 24818
21d799b5 24819 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
21d799b5 24820 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
c19d1205 24821
5be8be5d
DG		 24822 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
24823 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
24824 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
24825 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
c19d1205 24826
91d8b670
JG		 24827#undef ARM_VARIANT
24828#define ARM_VARIANT & arm_ext_v3
24829#undef THUMB_VARIANT
24830#define THUMB_VARIANT & arm_ext_v6t2
24831
24832 TUE("csdb", 320f014, f3af8014, 0, (), noargs, t_csdb),
c597cc3d
SD		 24833 TUF("ssbb", 57ff040, f3bf8f40, 0, (), noargs, t_csdb),
24834 TUF("pssbb", 57ff044, f3bf8f44, 0, (), noargs, t_csdb),
91d8b670
JG		 24835
24836#undef ARM_VARIANT
24837#define ARM_VARIANT & arm_ext_v6t2
ff8646ee
TP		 24838#undef THUMB_VARIANT
24839#define THUMB_VARIANT & arm_ext_v6t2_v8m
24840 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
24841 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
24842
bf3eeda7 24843 /* Thumb-only instructions. */
74db7efb 24844#undef ARM_VARIANT
bf3eeda7
NS		 24845#define ARM_VARIANT NULL
24846 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
24847 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
c921be7d
NC		 24848
24849 /* ARM does not really have an IT instruction, so always allow it.
24850 The opcode is copied from Thumb in order to allow warnings in
24851 -mimplicit-it=[never | arm] modes. */
24852#undef ARM_VARIANT
24853#define ARM_VARIANT & arm_ext_v1
ff8646ee
TP		 24854#undef THUMB_VARIANT
24855#define THUMB_VARIANT & arm_ext_v6t2
c921be7d 24856
21d799b5
NC		 24857 TUE("it", bf08, bf08, 1, (COND), it, t_it),
24858 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
24859 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
24860 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
24861 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
24862 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
24863 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
24864 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
24865 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
24866 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
24867 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
24868 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
24869 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
24870 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
24871 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
1c444d06 24872 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
21d799b5
NC		 24873 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
24874 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
c19d1205 24875
92e90b6e 24876 /* Thumb2 only instructions. */
c921be7d
NC		 24877#undef ARM_VARIANT
24878#define ARM_VARIANT NULL
92e90b6e 24879
21d799b5
NC		 24880 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
24881 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
24882 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
24883 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
24884 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
24885 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
92e90b6e 24886
eea54501
MGD		 24887 /* Hardware division instructions. */
24888#undef ARM_VARIANT
24889#define ARM_VARIANT & arm_ext_adiv
c921be7d
NC		 24890#undef THUMB_VARIANT
24891#define THUMB_VARIANT & arm_ext_div
24892
eea54501
MGD		 24893 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
24894 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
62b3e311 24895
7e806470 24896 /* ARM V6M/V7 instructions. */
c921be7d
NC		 24897#undef ARM_VARIANT
24898#define ARM_VARIANT & arm_ext_barrier
24899#undef THUMB_VARIANT
24900#define THUMB_VARIANT & arm_ext_barrier
24901
ccb84d65
JB		 24902 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier),
24903 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier),
24904 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier),
7e806470 24905
62b3e311 24906 /* ARM V7 instructions. */
c921be7d
NC		 24907#undef ARM_VARIANT
24908#define ARM_VARIANT & arm_ext_v7
24909#undef THUMB_VARIANT
24910#define THUMB_VARIANT & arm_ext_v7
24911
21d799b5
NC		 24912 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
24913 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
62b3e311 24914
74db7efb 24915#undef ARM_VARIANT
60e5ef9f 24916#define ARM_VARIANT & arm_ext_mp
74db7efb 24917#undef THUMB_VARIANT
60e5ef9f
MGD		 24918#define THUMB_VARIANT & arm_ext_mp
24919
24920 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
24921
53c4b28b
MGD		 24922 /* AArchv8 instructions. */
24923#undef ARM_VARIANT
24924#define ARM_VARIANT & arm_ext_v8
4ed7ed8d
TP		 24925
24926/* Instructions shared between armv8-a and armv8-m. */
53c4b28b 24927#undef THUMB_VARIANT
4ed7ed8d 24928#define THUMB_VARIANT & arm_ext_atomics
53c4b28b 24929
4ed7ed8d
TP		 24930 TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
24931 TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
24932 TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
24933 TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
24934 TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
24935 TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
4b8c8c02 24936 TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
4b8c8c02
RE		 24937 TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
24938 TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
24939 TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
24940 stlex, t_stlex),
4b8c8c02
RE		 24941 TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
24942 stlex, t_stlex),
24943 TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
24944 stlex, t_stlex),
4ed7ed8d
TP		 24945#undef THUMB_VARIANT
24946#define THUMB_VARIANT & arm_ext_v8
53c4b28b 24947
4ed7ed8d 24948 tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
4ed7ed8d
TP		 24949 TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
24950 ldrexd, t_ldrexd),
24951 TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
24952 strexd, t_strexd),
f7dd2fb2
TC		 24953
24954/* Defined in V8 but is in undefined encoding space for earlier
24955 architectures. However earlier architectures are required to treat
24956 this instuction as a semihosting trap as well. Hence while not explicitly
24957 defined as such, it is in fact correct to define the instruction for all
24958 architectures. */
24959#undef THUMB_VARIANT
24960#define THUMB_VARIANT & arm_ext_v1
24961#undef ARM_VARIANT
24962#define ARM_VARIANT & arm_ext_v1
24963 TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
24964
8884b720 24965 /* ARMv8 T32 only. */
74db7efb 24966#undef ARM_VARIANT
b79f7053
MGD		 24967#define ARM_VARIANT NULL
24968 TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
24969 TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
24970 TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
24971
33399f07
MGD		 24972 /* FP for ARMv8. */
24973#undef ARM_VARIANT
a715796b 24974#define ARM_VARIANT & fpu_vfp_ext_armv8xd
33399f07 24975#undef THUMB_VARIANT
a715796b 24976#define THUMB_VARIANT & fpu_vfp_ext_armv8xd
33399f07
MGD		 24977
24978 nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel),
24979 nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
24980 nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
24981 nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
30bdf752 24982 nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
a710b305
AV		 24983 mnCE(vrintz, _vrintr, 2, (RNSDQMQ, oRNSDQMQ), vrintz),
24984 mnCE(vrintx, _vrintr, 2, (RNSDQMQ, oRNSDQMQ), vrintx),
24985 mnUF(vrinta, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrinta),
24986 mnUF(vrintn, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintn),
24987 mnUF(vrintp, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintp),
24988 mnUF(vrintm, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintm),
33399f07 24989
91ff7894
MGD		 24990 /* Crypto v1 extensions. */
24991#undef ARM_VARIANT
24992#define ARM_VARIANT & fpu_crypto_ext_armv8
24993#undef THUMB_VARIANT
24994#define THUMB_VARIANT & fpu_crypto_ext_armv8
24995
24996 nUF(aese, _aes, 2, (RNQ, RNQ), aese),
24997 nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
24998 nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
24999 nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
48adcd8e
MGD		 25000 nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
25001 nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
25002 nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
25003 nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
25004 nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
25005 nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
25006 nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
3c9017d2
MGD		 25007 nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h),
25008 nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1),
25009 nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0),
91ff7894 25010
dd5181d5 25011#undef ARM_VARIANT
8b301fbb 25012#define ARM_VARIANT & arm_ext_crc
dd5181d5 25013#undef THUMB_VARIANT
8b301fbb 25014#define THUMB_VARIANT & arm_ext_crc
dd5181d5
KT		 25015 TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b),
25016 TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h),
25017 TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w),
25018 TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb),
25019 TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch),
25020 TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw),
25021
105bde57
MW		 25022 /* ARMv8.2 RAS extension. */
25023#undef ARM_VARIANT
4d1464f2 25024#define ARM_VARIANT & arm_ext_ras
105bde57 25025#undef THUMB_VARIANT
4d1464f2 25026#define THUMB_VARIANT & arm_ext_ras
105bde57
MW		 25027 TUE ("esb", 320f010, f3af8010, 0, (), noargs, noargs),
25028
49e8a725
SN		 25029#undef ARM_VARIANT
25030#define ARM_VARIANT & arm_ext_v8_3
25031#undef THUMB_VARIANT
25032#define THUMB_VARIANT & arm_ext_v8_3
25033 NCE (vjcvt, eb90bc0, 2, (RVS, RVD), vjcvt),
25034
c604a79a
JW		 25035#undef ARM_VARIANT
25036#define ARM_VARIANT & fpu_neon_ext_dotprod
25037#undef THUMB_VARIANT
25038#define THUMB_VARIANT & fpu_neon_ext_dotprod
25039 NUF (vsdot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_s),
25040 NUF (vudot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_u),
25041
c921be7d
NC		 25042#undef ARM_VARIANT
25043#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
53c4b28b
MGD		 25044#undef THUMB_VARIANT
25045#define THUMB_VARIANT NULL
c921be7d 25046
21d799b5
NC		 25047 cCE("wfs", e200110, 1, (RR), rd),
25048 cCE("rfs", e300110, 1, (RR), rd),
25049 cCE("wfc", e400110, 1, (RR), rd),
25050 cCE("rfc", e500110, 1, (RR), rd),
25051
25052 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
25053 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
25054 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
25055 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
25056
25057 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
25058 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
25059 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
25060 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
25061
25062 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
25063 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
25064 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
25065 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
25066 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
25067 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
25068 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
25069 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
25070 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
25071 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
25072 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
25073 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
25074
25075 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
25076 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
25077 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
25078 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
25079 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
25080 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
25081 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
25082 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
25083 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
25084 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
25085 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
25086 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
25087
25088 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
25089 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
25090 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
25091 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
25092 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
25093 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
25094 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
25095 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
25096 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
25097 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
25098 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
25099 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
25100
25101 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
25102 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
25103 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
25104 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
25105 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
25106 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
25107 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
25108 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
25109 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
25110 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
25111 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
25112 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
25113
25114 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
25115 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
25116 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
25117 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
25118 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
25119 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
25120 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
25121 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
25122 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
25123 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
25124 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
25125 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
25126
25127 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
25128 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
25129 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
25130 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
25131 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
25132 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
25133 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
25134 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
25135 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
25136 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
25137 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
25138 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
25139
25140 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
25141 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
25142 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
25143 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
25144 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
25145 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
25146 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
25147 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
25148 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
25149 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
25150 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
25151 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
25152
25153 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
25154 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
25155 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
25156 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
25157 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
25158 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
25159 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
25160 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
25161 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
25162 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
25163 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
25164 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
25165
25166 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
25167 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
25168 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
25169 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
25170 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
25171 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
25172 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
25173 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
25174 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
25175 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
25176 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
25177 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
25178
25179 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
25180 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
25181 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
25182 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
25183 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
25184 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
25185 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
25186 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
25187 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
25188 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
25189 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
25190 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
25191
25192 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
25193 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
25194 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
25195 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
25196 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
25197 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
25198 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
25199 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
25200 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
25201 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
25202 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
25203 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
25204
25205 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
25206 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
25207 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
25208 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
25209 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
25210 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
25211 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
25212 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
25213 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
25214 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
25215 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
25216 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
25217
25218 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
25219 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
25220 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
25221 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
25222 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
25223 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
25224 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
25225 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
25226 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
25227 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
25228 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
25229 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
25230
25231 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
25232 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
25233 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
25234 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
25235 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
25236 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
25237 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
25238 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
25239 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
25240 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
25241 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
25242 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
25243
25244 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
25245 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
25246 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
25247 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
25248 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
25249 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
25250 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
25251 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
25252 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
25253 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
25254 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
25255 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
25256
25257 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
25258 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
25259 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
25260 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
25261 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
25262 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
25263 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
25264 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
25265 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
25266 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
25267 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
25268 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
25269
25270 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
25271 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
25272 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
25273 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
25274 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
25275 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25276 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25277 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25278 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
25279 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
25280 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
25281 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
25282
25283 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
25284 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
25285 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
25286 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
25287 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
25288 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25289 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25290 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25291 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
25292 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
25293 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
25294 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
25295
25296 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
25297 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
25298 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
25299 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
25300 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
25301 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25302 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25303 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25304 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
25305 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
25306 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
25307 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
25308
25309 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
25310 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
25311 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
25312 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
25313 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
25314 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25315 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25316 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25317 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
25318 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
25319 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
25320 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
25321
25322 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
25323 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
25324 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
25325 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
25326 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
25327 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25328 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25329 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25330 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
25331 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
25332 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
25333 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
25334
25335 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
25336 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
25337 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
25338 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
25339 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
25340 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25341 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25342 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25343 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
25344 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
25345 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
25346 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
25347
25348 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
25349 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
25350 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
25351 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
25352 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
25353 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25354 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25355 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25356 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
25357 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
25358 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
25359 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
25360
25361 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
25362 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
25363 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
25364 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
25365 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
25366 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25367 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25368 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25369 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
25370 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
25371 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
25372 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
25373
25374 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
25375 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
25376 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
25377 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
25378 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
25379 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25380 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25381 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25382 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
25383 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
25384 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
25385 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
25386
25387 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
25388 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
25389 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
25390 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
25391 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
25392 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25393 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25394 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25395 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
25396 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
25397 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
25398 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
25399
25400 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
25401 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
25402 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
25403 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
25404 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
25405 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25406 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25407 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25408 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
25409 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
25410 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
25411 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
25412
25413 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
25414 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
25415 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
25416 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
25417 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
25418 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25419 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25420 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25421 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
25422 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
25423 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
25424 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
25425
25426 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
25427 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
25428 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
25429 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
25430 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
25431 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25432 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25433 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25434 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
25435 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
25436 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
25437 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
25438
25439 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
25440 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
25441 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
25442 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
25443
25444 cCL("flts", e000110, 2, (RF, RR), rn_rd),
25445 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
25446 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
25447 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
25448 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
25449 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
25450 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
25451 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
25452 cCL("flte", e080110, 2, (RF, RR), rn_rd),
25453 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
25454 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
25455 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
b99bd4ef 25456
c19d1205
ZW		 25457 /* The implementation of the FIX instruction is broken on some
25458 assemblers, in that it accepts a precision specifier as well as a
25459 rounding specifier, despite the fact that this is meaningless.
25460 To be more compatible, we accept it as well, though of course it
25461 does not set any bits. */
21d799b5
NC		 25462 cCE("fix", e100110, 2, (RR, RF), rd_rm),
25463 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
25464 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
25465 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
25466 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
25467 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
25468 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
25469 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
25470 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
25471 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
25472 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
25473 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
25474 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
bfae80f2 25475
c19d1205 25476 /* Instructions that were new with the real FPA, call them V2. */
c921be7d
NC		 25477#undef ARM_VARIANT
25478#define ARM_VARIANT & fpu_fpa_ext_v2
25479
21d799b5
NC		 25480 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
25481 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
25482 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
25483 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
25484 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
25485 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
c19d1205 25486
c921be7d
NC		 25487#undef ARM_VARIANT
25488#define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
ba6cd17f
SD		 25489#undef THUMB_VARIANT
25490#define THUMB_VARIANT & arm_ext_v6t2
25491 mcCE(vmrs, ef00a10, 2, (APSR_RR, RVC), vmrs),
25492 mcCE(vmsr, ee00a10, 2, (RVC, RR), vmsr),
ef8f595f
MI		 25493 mcCE(fldd, d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
25494 mcCE(fstd, d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
25495 mcCE(flds, d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
25496 mcCE(fsts, d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
90e9955a
SP		 25497
25498 /* Memory operations. */
25499 mcCE(fldmias, c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
25500 mcCE(fldmdbs, d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
25501 mcCE(fstmias, c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
25502 mcCE(fstmdbs, d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
ba6cd17f 25503#undef THUMB_VARIANT
c921be7d 25504
c19d1205 25505 /* Moves and type conversions. */
21d799b5
NC		 25506 cCE("fmstat", ef1fa10, 0, (), noargs),
25507 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
25508 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
25509 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
25510 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
25511 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
25512 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
25513 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
25514 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
c19d1205
ZW		 25515
25516 /* Memory operations. */
55881a11 25517 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
55881a11
MGD		 25518 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
25519 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
25520 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
25521 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
25522 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
55881a11 25523 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
55881a11
MGD		 25524 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
25525 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
25526 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
25527 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
25528 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
bfae80f2 25529
c19d1205 25530 /* Monadic operations. */
21d799b5
NC		 25531 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
25532 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
25533 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
c19d1205
ZW		 25534
25535 /* Dyadic operations. */
21d799b5
NC		 25536 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
25537 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
25538 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
25539 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
25540 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
25541 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
25542 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
25543 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
25544 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
b99bd4ef 25545
c19d1205 25546 /* Comparisons. */
21d799b5
NC		 25547 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
25548 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
25549 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
25550 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
b99bd4ef 25551
62f3b8c8
PB		 25552 /* Double precision load/store are still present on single precision
25553 implementations. */
55881a11
MGD		 25554 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
25555 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
25556 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
25557 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
25558 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
25559 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
25560 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
25561 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
62f3b8c8 25562
c921be7d
NC		 25563#undef ARM_VARIANT
25564#define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
25565
c19d1205 25566 /* Moves and type conversions. */
21d799b5
NC		 25567 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
25568 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
25569 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
25570 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
25571 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
25572 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
25573 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
25574 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
25575 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
25576 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
25577 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
25578 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
c19d1205 25579
c19d1205 25580 /* Monadic operations. */
21d799b5
NC		 25581 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
25582 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
25583 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
c19d1205
ZW		 25584
25585 /* Dyadic operations. */
21d799b5
NC		 25586 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
25587 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
25588 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
25589 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
25590 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
25591 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
25592 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
25593 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
25594 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
b99bd4ef 25595
c19d1205 25596 /* Comparisons. */
21d799b5
NC		 25597 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
25598 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
25599 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
25600 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
c19d1205 25601
037e8744
JB		 25602/* Instructions which may belong to either the Neon or VFP instruction sets.
25603 Individual encoder functions perform additional architecture checks. */
c921be7d
NC		 25604#undef ARM_VARIANT
25605#define ARM_VARIANT & fpu_vfp_ext_v1xd
ef8f595f
MI		 25606#undef THUMB_VARIANT
25607#define THUMB_VARIANT & arm_ext_v6t2
25608
25609 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
25610 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
25611 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
25612 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
25613 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
25614 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
25615
25616 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
25617 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
25618
c921be7d
NC		 25619#undef THUMB_VARIANT
25620#define THUMB_VARIANT & fpu_vfp_ext_v1xd
25621
037e8744
JB		 25622 /* These mnemonics are unique to VFP. */
25623 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
25624 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
21d799b5
NC		 25625 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
25626 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
25627 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
037e8744
JB		 25628 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
25629
25630 /* Mnemonics shared by Neon and VFP. */
21d799b5 25631 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
037e8744 25632
dd9634d9 25633 mnCEF(vcvt, _vcvt, 3, (RNSDQMQ, RNSDQMQ, oI32z), neon_cvt),
e3e535bc 25634 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
dd9634d9
AV		 25635 MNCEF(vcvtb, eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtb),
25636 MNCEF(vcvtt, eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtt),
f31fef98 25637
037e8744
JB		 25638
25639 /* NOTE: All VMOV encoding is special-cased! */
037e8744
JB		 25640 NCE(vmovq, 0, 1, (VMOV), neon_mov),
25641
32c36c3c
AV		 25642#undef THUMB_VARIANT
25643/* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
25644 by different feature bits. Since we are setting the Thumb guard, we can
25645 require Thumb-1 which makes it a nop guard and set the right feature bit in
25646 do_vldr_vstr (). */
25647#define THUMB_VARIANT & arm_ext_v4t
25648 NCE(vldr, d100b00, 2, (VLDR, ADDRGLDC), vldr_vstr),
25649 NCE(vstr, d000b00, 2, (VLDR, ADDRGLDC), vldr_vstr),
25650
9db2f6b4
RL		 25651#undef ARM_VARIANT
25652#define ARM_VARIANT & arm_ext_fp16
25653#undef THUMB_VARIANT
25654#define THUMB_VARIANT & arm_ext_fp16
25655 /* New instructions added from v8.2, allowing the extraction and insertion of
25656 the upper 16 bits of a 32-bit vector register. */
25657 NCE (vmovx, eb00a40, 2, (RVS, RVS), neon_movhf),
25658 NCE (vins, eb00ac0, 2, (RVS, RVS), neon_movhf),
25659
dec41383 25660 /* New backported fma/fms instructions optional in v8.2. */
aab2c27d
MM		 25661 NUF (vfmsl, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmsl),
25662 NUF (vfmal, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmal),
dec41383 25663
c921be7d
NC		 25664#undef THUMB_VARIANT
25665#define THUMB_VARIANT & fpu_neon_ext_v1
25666#undef ARM_VARIANT
25667#define ARM_VARIANT & fpu_neon_ext_v1
25668
5287ad62
JB		 25669 /* Data processing with three registers of the same length. */
25670 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
25671 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
25672 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
5287ad62 25673 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
5287ad62 25674 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
5287ad62
JB		 25675 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
25676 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
5287ad62 25677 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
5287ad62 25678 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
627907b7 25679 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
627907b7 25680 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
5287ad62 25681 /* If not immediate, fall back to neon_dyadic_i64_su.
5150f0d8
AV		 25682 shl should accept I8 I16 I32 I64,
25683 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
25684 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl),
25685 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl),
5287ad62 25686 /* Logic ops, types optional & ignored. */
4316f0d2 25687 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
4316f0d2 25688 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
4316f0d2 25689 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
4316f0d2 25690 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
4316f0d2 25691 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
5287ad62
JB		 25692 /* Bitfield ops, untyped. */
25693 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
25694 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
25695 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
25696 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
25697 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
25698 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
cc933301 25699 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
21d799b5 25700 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
21d799b5 25701 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
21d799b5 25702 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
5287ad62
JB		 25703 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
25704 back to neon_dyadic_if_su. */
21d799b5
NC		 25705 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
25706 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
25707 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
25708 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
25709 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
25710 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
25711 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
25712 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
428e3f1f 25713 /* Comparison. Type I8 I16 I32 F32. */
21d799b5
NC		 25714 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
25715 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
5287ad62 25716 /* As above, D registers only. */
21d799b5
NC		 25717 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
25718 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
5287ad62 25719 /* Int and float variants, signedness unimportant. */
21d799b5
NC		 25720 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
25721 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
25722 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
5287ad62 25723 /* Add/sub take types I8 I16 I32 I64 F32. */
21d799b5
NC		 25724 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
25725 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
5287ad62
JB		 25726 /* vtst takes sizes 8, 16, 32. */
25727 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
25728 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
25729 /* VMUL takes I8 I16 I32 F32 P8. */
21d799b5 25730 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
5287ad62 25731 /* VQD{R}MULH takes S16 S32. */
21d799b5 25732 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
21d799b5 25733 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
5287ad62
JB		 25734 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
25735 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
25736 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
25737 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
92559b5b
PB		 25738 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
25739 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
25740 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
25741 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
5287ad62
JB		 25742 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
25743 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
25744 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
25745 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
d6b4b13e 25746 /* ARM v8.1 extension. */
643afb90
MW		 25747 nUF (vqrdmlahq, _vqrdmlah, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah),
25748 nUF (vqrdmlsh, _vqrdmlsh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah),
25749 nUF (vqrdmlshq, _vqrdmlsh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah),
5287ad62
JB		 25750
25751 /* Two address, int/float. Types S8 S16 S32 F32. */
5287ad62 25752 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
5287ad62
JB		 25753 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
25754
25755 /* Data processing with two registers and a shift amount. */
25756 /* Right shifts, and variants with rounding.
25757 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
5287ad62 25758 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
5287ad62
JB		 25759 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
25760 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
25761 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
25762 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
25763 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
25764 /* Shift and insert. Sizes accepted 8 16 32 64. */
5287ad62 25765 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
5287ad62
JB		 25766 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
25767 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
5287ad62
JB		 25768 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
25769 /* Right shift immediate, saturating & narrowing, with rounding variants.
25770 Types accepted S16 S32 S64 U16 U32 U64. */
25771 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
25772 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
25773 /* As above, unsigned. Types accepted S16 S32 S64. */
25774 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
25775 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
25776 /* Right shift narrowing. Types accepted I16 I32 I64. */
25777 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
25778 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
25779 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
21d799b5 25780 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
5287ad62 25781 /* CVT with optional immediate for fixed-point variant. */
21d799b5 25782 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
b7fc2769 25783
4316f0d2 25784 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
5287ad62
JB		 25785
25786 /* Data processing, three registers of different lengths. */
25787 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
25788 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
5287ad62
JB		 25789 /* If not scalar, fall back to neon_dyadic_long.
25790 Vector types as above, scalar types S16 S32 U16 U32. */
21d799b5
NC		 25791 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
25792 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
5287ad62
JB		 25793 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
25794 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
25795 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
25796 /* Dyadic, narrowing insns. Types I16 I32 I64. */
25797 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
25798 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
25799 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
25800 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
25801 /* Saturating doubling multiplies. Types S16 S32. */
21d799b5
NC		 25802 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
25803 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
25804 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
5287ad62
JB		 25805 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
25806 S16 S32 U16 U32. */
21d799b5 25807 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
5287ad62
JB		 25808
25809 /* Extract. Size 8. */
3b8d421e
PB		 25810 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
25811 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
5287ad62
JB		 25812
25813 /* Two registers, miscellaneous. */
25814 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
5287ad62 25815 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
5287ad62 25816 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
5287ad62
JB		 25817 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
25818 /* Vector replicate. Sizes 8 16 32. */
21d799b5 25819 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
5287ad62
JB		 25820 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
25821 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
25822 /* VMOVN. Types I16 I32 I64. */
21d799b5 25823 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
5287ad62 25824 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
21d799b5 25825 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
5287ad62 25826 /* VQMOVUN. Types S16 S32 S64. */
21d799b5 25827 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
5287ad62
JB		 25828 /* VZIP / VUZP. Sizes 8 16 32. */
25829 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
25830 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
25831 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
25832 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
25833 /* VQABS / VQNEG. Types S8 S16 S32. */
5287ad62 25834 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
5287ad62
JB		 25835 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
25836 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
25837 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
25838 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
25839 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
25840 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
cc933301 25841 /* Reciprocal estimates. Types U32 F16 F32. */
5287ad62
JB		 25842 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
25843 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
25844 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
25845 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
25846 /* VCLS. Types S8 S16 S32. */
5287ad62
JB		 25847 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
25848 /* VCLZ. Types I8 I16 I32. */
5287ad62
JB		 25849 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
25850 /* VCNT. Size 8. */
25851 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
25852 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
25853 /* Two address, untyped. */
25854 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
25855 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
25856 /* VTRN. Sizes 8 16 32. */
21d799b5
NC		 25857 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
25858 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
5287ad62
JB		 25859
25860 /* Table lookup. Size 8. */
25861 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
25862 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
25863
c921be7d
NC		 25864#undef THUMB_VARIANT
25865#define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
25866#undef ARM_VARIANT
25867#define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
25868
5287ad62 25869 /* Neon element/structure load/store. */
21d799b5
NC		 25870 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
25871 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
25872 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
25873 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
25874 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
25875 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
25876 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
25877 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
5287ad62 25878
c921be7d 25879#undef THUMB_VARIANT
74db7efb
NC		 25880#define THUMB_VARIANT & fpu_vfp_ext_v3xd
25881#undef ARM_VARIANT
25882#define ARM_VARIANT & fpu_vfp_ext_v3xd
62f3b8c8
PB		 25883 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
25884 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
25885 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
25886 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
25887 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
25888 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
25889 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
25890 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
25891 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
25892
74db7efb 25893#undef THUMB_VARIANT
c921be7d
NC		 25894#define THUMB_VARIANT & fpu_vfp_ext_v3
25895#undef ARM_VARIANT
25896#define ARM_VARIANT & fpu_vfp_ext_v3
25897
21d799b5 25898 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
21d799b5 25899 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 25900 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21d799b5 25901 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 25902 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21d799b5 25903 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 25904 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21d799b5 25905 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 25906 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
c19d1205 25907
74db7efb
NC		 25908#undef ARM_VARIANT
25909#define ARM_VARIANT & fpu_vfp_ext_fma
25910#undef THUMB_VARIANT
25911#define THUMB_VARIANT & fpu_vfp_ext_fma
aab2c27d 25912 /* Mnemonics shared by Neon, VFP, MVE and BF16. These are included in the
62f3b8c8
PB		 25913 VFP FMA variant; NEON and VFP FMA always includes the NEON
25914 FMA instructions. */
d58196e0 25915 mnCEF(vfma, _vfma, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_fmac),
aab2c27d 25916 TUF ("vfmat", c300850, fc300850, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), mve_vfma, mve_vfma),
d58196e0
AV		 25917 mnCEF(vfms, _vfms, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), neon_fmac),
25918
62f3b8c8
PB		 25919 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
25920 the v form should always be used. */
25921 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
25922 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
25923 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
25924 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
25925 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
25926 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
25927
5287ad62 25928#undef THUMB_VARIANT
c921be7d
NC		 25929#undef ARM_VARIANT
25930#define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
25931
21d799b5
NC		 25932 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
25933 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
25934 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
25935 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
25936 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
25937 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
25938 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
25939 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
c19d1205 25940
c921be7d
NC		 25941#undef ARM_VARIANT
25942#define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
25943
21d799b5
NC		 25944 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
25945 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
25946 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
25947 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
25948 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
25949 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
25950 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
25951 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
25952 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
74db7efb
NC		 25953 cCE("textrmub",e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
25954 cCE("textrmuh",e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
25955 cCE("textrmuw",e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
25956 cCE("textrmsb",e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
25957 cCE("textrmsh",e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
25958 cCE("textrmsw",e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
21d799b5
NC		 25959 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
25960 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
25961 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
25962 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
25963 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
25964 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
25965 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
25966 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
25967 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
25968 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
25969 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
74db7efb
NC		 25970 cCE("tmovmskb",e100030, 2, (RR, RIWR), rd_rn),
25971 cCE("tmovmskh",e500030, 2, (RR, RIWR), rd_rn),
25972 cCE("tmovmskw",e900030, 2, (RR, RIWR), rd_rn),
21d799b5
NC		 25973 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
25974 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
25975 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
25976 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
25977 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
25978 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
25979 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
25980 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
25981 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25982 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25983 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25984 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25985 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25986 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25987 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25988 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25989 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25990 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
74db7efb
NC		 25991 cCE("walignr0",e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25992 cCE("walignr1",e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25993 cCE("walignr2",ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25994 cCE("walignr3",eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21d799b5
NC		 25995 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25996 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25997 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25998 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25999 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26000 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26001 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26002 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26003 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
74db7efb
NC		 26004 cCE("wcmpgtub",e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26005 cCE("wcmpgtuh",e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26006 cCE("wcmpgtuw",e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26007 cCE("wcmpgtsb",e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26008 cCE("wcmpgtsh",e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26009 cCE("wcmpgtsw",eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21d799b5
NC		 26010 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
26011 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
26012 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
26013 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
26014 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26015 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26016 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26017 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26018 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26019 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26020 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26021 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26022 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26023 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26024 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26025 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26026 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26027 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26028 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26029 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26030 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26031 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26032 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
26033 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26034 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26035 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26036 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26037 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
74db7efb
NC		 26038 cCE("wpackhss",e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26039 cCE("wpackhus",e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26040 cCE("wpackwss",eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26041 cCE("wpackwus",e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26042 cCE("wpackdss",ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26043 cCE("wpackdus",ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21d799b5
NC		 26044 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26045 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
26046 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26047 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
26048 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26049 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
26050 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26051 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26052 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26053 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26054 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
26055 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26056 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
26057 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26058 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
26059 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26060 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
26061 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26062 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
26063 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26064 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
26065 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26066 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
26067 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26068 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
26069 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26070 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
26071 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26072 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
26073 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
26074 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
26075 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
26076 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
26077 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26078 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26079 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26080 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26081 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26082 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26083 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26084 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26085 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26086 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
26087 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
26088 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
26089 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
26090 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
26091 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
26092 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26093 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26094 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26095 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
26096 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
26097 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
26098 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
26099 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
26100 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
26101 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26102 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26103 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26104 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26105 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
c19d1205 26106
c921be7d
NC		 26107#undef ARM_VARIANT
26108#define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
26109
21d799b5
NC		 26110 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
26111 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
26112 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
26113 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
26114 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
26115 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
26116 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26117 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26118 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26119 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26120 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26121 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26122 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26123 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26124 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26125 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26126 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26127 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26128 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26129 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26130 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
26131 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26132 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26133 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26134 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26135 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26136 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26137 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26138 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26139 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26140 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26141 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26142 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26143 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26144 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26145 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26146 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26147 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26148 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26149 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26150 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26151 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26152 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26153 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26154 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26155 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26156 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26157 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26158 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26159 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26160 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26161 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26162 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26163 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26164 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26165 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
26166 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
2d447fca 26167
c921be7d
NC		 26168#undef ARM_VARIANT
26169#define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
26170
21d799b5
NC		 26171 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
26172 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
26173 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
26174 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
26175 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
26176 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
26177 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
26178 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
26179 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
26180 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
26181 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
26182 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
26183 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
26184 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
74db7efb
NC		 26185 cCE("cfmv64lr",e000510, 2, (RMDX, RR), rn_rd),
26186 cCE("cfmvr64l",e100510, 2, (RR, RMDX), rd_rn),
26187 cCE("cfmv64hr",e000530, 2, (RMDX, RR), rn_rd),
26188 cCE("cfmvr64h",e100530, 2, (RR, RMDX), rd_rn),
26189 cCE("cfmval32",e200440, 2, (RMAX, RMFX), rd_rn),
26190 cCE("cfmv32al",e100440, 2, (RMFX, RMAX), rd_rn),
26191 cCE("cfmvam32",e200460, 2, (RMAX, RMFX), rd_rn),
26192 cCE("cfmv32am",e100460, 2, (RMFX, RMAX), rd_rn),
26193 cCE("cfmvah32",e200480, 2, (RMAX, RMFX), rd_rn),
26194 cCE("cfmv32ah",e100480, 2, (RMFX, RMAX), rd_rn),
21d799b5
NC		 26195 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
26196 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
26197 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
26198 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
74db7efb
NC		 26199 cCE("cfmvsc32",e2004e0, 2, (RMDS, RMDX), mav_dspsc),
26200 cCE("cfmv32sc",e1004e0, 2, (RMDX, RMDS), rd),
21d799b5
NC		 26201 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
26202 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
26203 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
26204 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
74db7efb
NC		 26205 cCE("cfcvt32s",e000480, 2, (RMF, RMFX), rd_rn),
26206 cCE("cfcvt32d",e0004a0, 2, (RMD, RMFX), rd_rn),
26207 cCE("cfcvt64s",e0004c0, 2, (RMF, RMDX), rd_rn),
26208 cCE("cfcvt64d",e0004e0, 2, (RMD, RMDX), rd_rn),
26209 cCE("cfcvts32",e100580, 2, (RMFX, RMF), rd_rn),
26210 cCE("cfcvtd32",e1005a0, 2, (RMFX, RMD), rd_rn),
21d799b5
NC		 26211 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
26212 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
74db7efb
NC		 26213 cCE("cfrshl32",e000550, 3, (RMFX, RMFX, RR), mav_triple),
26214 cCE("cfrshl64",e000570, 3, (RMDX, RMDX, RR), mav_triple),
21d799b5
NC		 26215 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
26216 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
26217 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
26218 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
26219 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
26220 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
26221 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
26222 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
26223 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
26224 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
26225 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
26226 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
26227 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
26228 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
26229 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
26230 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
26231 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
26232 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
26233 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
26234 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
26235 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
26236 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
26237 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
26238 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
26239 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
26240 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
26241 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
26242 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
74db7efb
NC		 26243 cCE("cfmadd32",e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
26244 cCE("cfmsub32",e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
21d799b5
NC		 26245 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
26246 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
4ed7ed8d 26247
7fadb25d
SD		 26248 /* ARMv8.5-A instructions. */
26249#undef ARM_VARIANT
26250#define ARM_VARIANT & arm_ext_sb
26251#undef THUMB_VARIANT
26252#define THUMB_VARIANT & arm_ext_sb
26253 TUF("sb", 57ff070, f3bf8f70, 0, (), noargs, noargs),
26254
dad0c3bf
SD		 26255#undef ARM_VARIANT
26256#define ARM_VARIANT & arm_ext_predres
26257#undef THUMB_VARIANT
26258#define THUMB_VARIANT & arm_ext_predres
26259 CE("cfprctx", e070f93, 1, (RRnpc), rd),
26260 CE("dvprctx", e070fb3, 1, (RRnpc), rd),
26261 CE("cpprctx", e070ff3, 1, (RRnpc), rd),
26262
16a1fa25 26263 /* ARMv8-M instructions. */
4ed7ed8d
TP		 26264#undef ARM_VARIANT
26265#define ARM_VARIANT NULL
26266#undef THUMB_VARIANT
26267#define THUMB_VARIANT & arm_ext_v8m
cf3cf39d
TP		 26268 ToU("sg", e97fe97f, 0, (), noargs),
26269 ToC("blxns", 4784, 1, (RRnpc), t_blx),
26270 ToC("bxns", 4704, 1, (RRnpc), t_bx),
26271 ToC("tt", e840f000, 2, (RRnpc, RRnpc), tt),
26272 ToC("ttt", e840f040, 2, (RRnpc, RRnpc), tt),
26273 ToC("tta", e840f080, 2, (RRnpc, RRnpc), tt),
26274 ToC("ttat", e840f0c0, 2, (RRnpc, RRnpc), tt),
16a1fa25
TP		 26275
26276 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
26277 instructions behave as nop if no VFP is present. */
26278#undef THUMB_VARIANT
26279#define THUMB_VARIANT & arm_ext_v8m_main
cf3cf39d
TP		 26280 ToC("vlldm", ec300a00, 1, (RRnpc), rn),
26281 ToC("vlstm", ec200a00, 1, (RRnpc), rn),
4389b29a
AV		 26282
26283 /* Armv8.1-M Mainline instructions. */
26284#undef THUMB_VARIANT
26285#define THUMB_VARIANT & arm_ext_v8_1m_main
e39c1607
SD		 26286 toU("cinc", _cinc, 3, (RRnpcsp, RR_ZR, COND), t_cond),
26287 toU("cinv", _cinv, 3, (RRnpcsp, RR_ZR, COND), t_cond),
26288 toU("cneg", _cneg, 3, (RRnpcsp, RR_ZR, COND), t_cond),
26289 toU("csel", _csel, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond),
26290 toU("csetm", _csetm, 2, (RRnpcsp, COND), t_cond),
26291 toU("cset", _cset, 2, (RRnpcsp, COND), t_cond),
26292 toU("csinc", _csinc, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond),
26293 toU("csinv", _csinv, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond),
26294 toU("csneg", _csneg, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond),
26295
4389b29a 26296 toC("bf", _bf, 2, (EXPs, EXPs), t_branch_future),
f6b2b12d 26297 toU("bfcsel", _bfcsel, 4, (EXPs, EXPs, EXPs, COND), t_branch_future),
f1c7f421 26298 toC("bfx", _bfx, 2, (EXPs, RRnpcsp), t_branch_future),
65d1bc05 26299 toC("bfl", _bfl, 2, (EXPs, EXPs), t_branch_future),
f1c7f421 26300 toC("bflx", _bflx, 2, (EXPs, RRnpcsp), t_branch_future),
60f993ce
AV		 26301
26302 toU("dls", _dls, 2, (LR, RRnpcsp), t_loloop),
26303 toU("wls", _wls, 3, (LR, RRnpcsp, EXP), t_loloop),
26304 toU("le", _le, 2, (oLR, EXP), t_loloop),
4b5a202f 26305
efd6b359 26306 ToC("clrm", e89f0000, 1, (CLRMLST), t_clrm),
5ee91343
AV		 26307 ToC("vscclrm", ec9f0a00, 1, (VRSDVLST), t_vscclrm),
26308
26309#undef THUMB_VARIANT
26310#define THUMB_VARIANT & mve_ext
23d00a41
SD		 26311 ToC("lsll", ea50010d, 3, (RRe, RRo, RRnpcsp_I32), mve_scalar_shift),
26312 ToC("lsrl", ea50011f, 3, (RRe, RRo, I32), mve_scalar_shift),
26313 ToC("asrl", ea50012d, 3, (RRe, RRo, RRnpcsp_I32), mve_scalar_shift),
08132bdd
SP		 26314 ToC("uqrshll", ea51010d, 4, (RRe, RRo, I48_I64, RRnpcsp), mve_scalar_shift1),
26315 ToC("sqrshrl", ea51012d, 4, (RRe, RRo, I48_I64, RRnpcsp), mve_scalar_shift1),
23d00a41
SD		 26316 ToC("uqshll", ea51010f, 3, (RRe, RRo, I32), mve_scalar_shift),
26317 ToC("urshrl", ea51011f, 3, (RRe, RRo, I32), mve_scalar_shift),
26318 ToC("srshrl", ea51012f, 3, (RRe, RRo, I32), mve_scalar_shift),
26319 ToC("sqshll", ea51013f, 3, (RRe, RRo, I32), mve_scalar_shift),
26320 ToC("uqrshl", ea500f0d, 2, (RRnpcsp, RRnpcsp), mve_scalar_shift),
26321 ToC("sqrshr", ea500f2d, 2, (RRnpcsp, RRnpcsp), mve_scalar_shift),
26322 ToC("uqshl", ea500f0f, 2, (RRnpcsp, I32), mve_scalar_shift),
26323 ToC("urshr", ea500f1f, 2, (RRnpcsp, I32), mve_scalar_shift),
26324 ToC("srshr", ea500f2f, 2, (RRnpcsp, I32), mve_scalar_shift),
26325 ToC("sqshl", ea500f3f, 2, (RRnpcsp, I32), mve_scalar_shift),
1b883319
AV		 26326
26327 ToC("vpt", ee410f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26328 ToC("vptt", ee018f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26329 ToC("vpte", ee418f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26330 ToC("vpttt", ee014f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26331 ToC("vptte", ee01cf00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26332 ToC("vptet", ee41cf00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26333 ToC("vptee", ee414f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26334 ToC("vptttt", ee012f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26335 ToC("vpttte", ee016f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26336 ToC("vpttet", ee01ef00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26337 ToC("vpttee", ee01af00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26338 ToC("vptett", ee41af00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26339 ToC("vptete", ee41ef00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26340 ToC("vpteet", ee416f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26341 ToC("vpteee", ee412f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26342
5ee91343
AV		 26343 ToC("vpst", fe710f4d, 0, (), mve_vpt),
26344 ToC("vpstt", fe318f4d, 0, (), mve_vpt),
26345 ToC("vpste", fe718f4d, 0, (), mve_vpt),
26346 ToC("vpsttt", fe314f4d, 0, (), mve_vpt),
26347 ToC("vpstte", fe31cf4d, 0, (), mve_vpt),
26348 ToC("vpstet", fe71cf4d, 0, (), mve_vpt),
26349 ToC("vpstee", fe714f4d, 0, (), mve_vpt),
26350 ToC("vpstttt", fe312f4d, 0, (), mve_vpt),
26351 ToC("vpsttte", fe316f4d, 0, (), mve_vpt),
26352 ToC("vpsttet", fe31ef4d, 0, (), mve_vpt),
26353 ToC("vpsttee", fe31af4d, 0, (), mve_vpt),
26354 ToC("vpstett", fe71af4d, 0, (), mve_vpt),
26355 ToC("vpstete", fe71ef4d, 0, (), mve_vpt),
26356 ToC("vpsteet", fe716f4d, 0, (), mve_vpt),
26357 ToC("vpsteee", fe712f4d, 0, (), mve_vpt),
26358
a302e574 26359 /* MVE and MVE FP only. */
7df54120 26360 mToC("vhcadd", ee000f00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vhcadd),
efd0b310 26361 mCEF(vctp, _vctp, 1, (RRnpc), mve_vctp),
c2dafc2a
AV		 26362 mCEF(vadc, _vadc, 3, (RMQ, RMQ, RMQ), mve_vadc),
26363 mCEF(vadci, _vadci, 3, (RMQ, RMQ, RMQ), mve_vadc),
26364 mToC("vsbc", fe300f00, 3, (RMQ, RMQ, RMQ), mve_vsbc),
26365 mToC("vsbci", fe301f00, 3, (RMQ, RMQ, RMQ), mve_vsbc),
886e1c73 26366 mCEF(vmullb, _vmullb, 3, (RMQ, RMQ, RMQ), mve_vmull),
a302e574
AV		 26367 mCEF(vabav, _vabav, 3, (RRnpcsp, RMQ, RMQ), mve_vabav),
26368 mCEF(vmladav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav),
26369 mCEF(vmladava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav),
26370 mCEF(vmladavx, _vmladavx, 3, (RRe, RMQ, RMQ), mve_vmladav),
26371 mCEF(vmladavax, _vmladavax, 3, (RRe, RMQ, RMQ), mve_vmladav),
26372 mCEF(vmlav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav),
26373 mCEF(vmlava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav),
26374 mCEF(vmlsdav, _vmlsdav, 3, (RRe, RMQ, RMQ), mve_vmladav),
26375 mCEF(vmlsdava, _vmlsdava, 3, (RRe, RMQ, RMQ), mve_vmladav),
26376 mCEF(vmlsdavx, _vmlsdavx, 3, (RRe, RMQ, RMQ), mve_vmladav),
26377 mCEF(vmlsdavax, _vmlsdavax, 3, (RRe, RMQ, RMQ), mve_vmladav),
26378
35c228db
AV		 26379 mCEF(vst20, _vst20, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
26380 mCEF(vst21, _vst21, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
26381 mCEF(vst40, _vst40, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
26382 mCEF(vst41, _vst41, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
26383 mCEF(vst42, _vst42, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
26384 mCEF(vst43, _vst43, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
26385 mCEF(vld20, _vld20, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
26386 mCEF(vld21, _vld21, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
26387 mCEF(vld40, _vld40, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
26388 mCEF(vld41, _vld41, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
26389 mCEF(vld42, _vld42, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
26390 mCEF(vld43, _vld43, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
f5f10c66
AV		 26391 mCEF(vstrb, _vstrb, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
26392 mCEF(vstrh, _vstrh, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
26393 mCEF(vstrw, _vstrw, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
26394 mCEF(vstrd, _vstrd, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
26395 mCEF(vldrb, _vldrb, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
26396 mCEF(vldrh, _vldrh, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
26397 mCEF(vldrw, _vldrw, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
26398 mCEF(vldrd, _vldrd, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
35c228db 26399
57785aa2
AV		 26400 mCEF(vmovnt, _vmovnt, 2, (RMQ, RMQ), mve_movn),
26401 mCEF(vmovnb, _vmovnb, 2, (RMQ, RMQ), mve_movn),
c2dafc2a 26402 mCEF(vbrsr, _vbrsr, 3, (RMQ, RMQ, RR), mve_vbrsr),
26c1e780
AV		 26403 mCEF(vaddlv, _vaddlv, 3, (RRe, RRo, RMQ), mve_vaddlv),
26404 mCEF(vaddlva, _vaddlva, 3, (RRe, RRo, RMQ), mve_vaddlv),
26405 mCEF(vaddv, _vaddv, 2, (RRe, RMQ), mve_vaddv),
26406 mCEF(vaddva, _vaddva, 2, (RRe, RMQ), mve_vaddv),
b409bdb6
AV		 26407 mCEF(vddup, _vddup, 3, (RMQ, RRe, EXPi), mve_viddup),
26408 mCEF(vdwdup, _vdwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup),
26409 mCEF(vidup, _vidup, 3, (RMQ, RRe, EXPi), mve_viddup),
26410 mCEF(viwdup, _viwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup),
935295b5
AV		 26411 mToC("vmaxa", ee330e81, 2, (RMQ, RMQ), mve_vmaxa_vmina),
26412 mToC("vmina", ee331e81, 2, (RMQ, RMQ), mve_vmaxa_vmina),
13ccd4c0
AV		 26413 mCEF(vmaxv, _vmaxv, 2, (RR, RMQ), mve_vmaxv),
26414 mCEF(vmaxav, _vmaxav, 2, (RR, RMQ), mve_vmaxv),
26415 mCEF(vminv, _vminv, 2, (RR, RMQ), mve_vmaxv),
26416 mCEF(vminav, _vminav, 2, (RR, RMQ), mve_vmaxv),
57785aa2 26417
93925576
AV		 26418 mCEF(vmlaldav, _vmlaldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
26419 mCEF(vmlaldava, _vmlaldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
26420 mCEF(vmlaldavx, _vmlaldavx, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
26421 mCEF(vmlaldavax, _vmlaldavax, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
26422 mCEF(vmlalv, _vmlaldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
26423 mCEF(vmlalva, _vmlaldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
26424 mCEF(vmlsldav, _vmlsldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
26425 mCEF(vmlsldava, _vmlsldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
26426 mCEF(vmlsldavx, _vmlsldavx, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
26427 mCEF(vmlsldavax, _vmlsldavax, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
26428 mToC("vrmlaldavh", ee800f00, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
26429 mToC("vrmlaldavha",ee800f20, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
26430 mCEF(vrmlaldavhx, _vrmlaldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
26431 mCEF(vrmlaldavhax, _vrmlaldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
26432 mToC("vrmlalvh", ee800f00, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
26433 mToC("vrmlalvha", ee800f20, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
26434 mCEF(vrmlsldavh, _vrmlsldavh, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
26435 mCEF(vrmlsldavha, _vrmlsldavha, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
26436 mCEF(vrmlsldavhx, _vrmlsldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
26437 mCEF(vrmlsldavhax, _vrmlsldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
26438
2d78f95b
AV		 26439 mToC("vmlas", ee011e40, 3, (RMQ, RMQ, RR), mve_vmlas),
26440 mToC("vmulh", ee010e01, 3, (RMQ, RMQ, RMQ), mve_vmulh),
26441 mToC("vrmulh", ee011e01, 3, (RMQ, RMQ, RMQ), mve_vmulh),
3063888e
AV		 26442 mToC("vpnot", fe310f4d, 0, (), mve_vpnot),
26443 mToC("vpsel", fe310f01, 3, (RMQ, RMQ, RMQ), mve_vpsel),
2d78f95b 26444
8b8b22a4
AV		 26445 mToC("vqdmladh", ee000e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
26446 mToC("vqdmladhx", ee001e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
26447 mToC("vqrdmladh", ee000e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
26448 mToC("vqrdmladhx",ee001e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
26449 mToC("vqdmlsdh", fe000e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
26450 mToC("vqdmlsdhx", fe001e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
26451 mToC("vqrdmlsdh", fe000e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
26452 mToC("vqrdmlsdhx",fe001e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
42b16635
AV		 26453 mToC("vqdmlah", ee000e60, 3, (RMQ, RMQ, RR), mve_vqdmlah),
26454 mToC("vqdmlash", ee001e60, 3, (RMQ, RMQ, RR), mve_vqdmlah),
26455 mToC("vqrdmlash", ee001e40, 3, (RMQ, RMQ, RR), mve_vqdmlah),
35d1cfc2
AV		 26456 mToC("vqdmullt", ee301f00, 3, (RMQ, RMQ, RMQRR), mve_vqdmull),
26457 mToC("vqdmullb", ee300f00, 3, (RMQ, RMQ, RMQRR), mve_vqdmull),
1be7aba3
AV		 26458 mCEF(vqmovnt, _vqmovnt, 2, (RMQ, RMQ), mve_vqmovn),
26459 mCEF(vqmovnb, _vqmovnb, 2, (RMQ, RMQ), mve_vqmovn),
26460 mCEF(vqmovunt, _vqmovunt, 2, (RMQ, RMQ), mve_vqmovn),
26461 mCEF(vqmovunb, _vqmovunb, 2, (RMQ, RMQ), mve_vqmovn),
8b8b22a4 26462
4aa88b50
AV		 26463 mCEF(vshrnt, _vshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
26464 mCEF(vshrnb, _vshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
26465 mCEF(vrshrnt, _vrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
26466 mCEF(vrshrnb, _vrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
26467 mCEF(vqshrnt, _vqrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
26468 mCEF(vqshrnb, _vqrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
26469 mCEF(vqshrunt, _vqrshrunt, 3, (RMQ, RMQ, I32z), mve_vshrn),
26470 mCEF(vqshrunb, _vqrshrunb, 3, (RMQ, RMQ, I32z), mve_vshrn),
26471 mCEF(vqrshrnt, _vqrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
26472 mCEF(vqrshrnb, _vqrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
26473 mCEF(vqrshrunt, _vqrshrunt, 3, (RMQ, RMQ, I32z), mve_vshrn),
26474 mCEF(vqrshrunb, _vqrshrunb, 3, (RMQ, RMQ, I32z), mve_vshrn),
26475
acca5630
AV		 26476 mToC("vshlc", eea00fc0, 3, (RMQ, RR, I32z), mve_vshlc),
26477 mToC("vshllt", ee201e00, 3, (RMQ, RMQ, I32), mve_vshll),
26478 mToC("vshllb", ee200e00, 3, (RMQ, RMQ, I32), mve_vshll),
26479
1f6234a3
AV		 26480 toU("dlstp", _dlstp, 2, (LR, RR), t_loloop),
26481 toU("wlstp", _wlstp, 3, (LR, RR, EXP), t_loloop),
26482 toU("letp", _letp, 2, (LR, EXP), t_loloop),
26483 toU("lctp", _lctp, 0, (), t_loloop),
26484
5d281bf0
AV		 26485#undef THUMB_VARIANT
26486#define THUMB_VARIANT & mve_fp_ext
26487 mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul),
f30ee27c 26488 mToC("vfmas", ee311e40, 3, (RMQ, RMQ, RR), mve_vfmas),
935295b5
AV		 26489 mToC("vmaxnma", ee3f0e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma),
26490 mToC("vminnma", ee3f1e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma),
8cd78170
AV		 26491 mToC("vmaxnmv", eeee0f00, 2, (RR, RMQ), mve_vmaxnmv),
26492 mToC("vmaxnmav",eeec0f00, 2, (RR, RMQ), mve_vmaxnmv),
26493 mToC("vminnmv", eeee0f80, 2, (RR, RMQ), mve_vmaxnmv),
26494 mToC("vminnmav",eeec0f80, 2, (RR, RMQ), mve_vmaxnmv),
5d281bf0 26495
5ee91343 26496#undef ARM_VARIANT
57785aa2 26497#define ARM_VARIANT & fpu_vfp_ext_v1
5ee91343
AV		 26498#undef THUMB_VARIANT
26499#define THUMB_VARIANT & arm_ext_v6t2
a8465a06
AV		 26500 mnCEF(vmla, _vmla, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mac_maybe_scalar),
26501 mnCEF(vmul, _vmul, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mul),
5ee91343 26502
57785aa2
AV		 26503 mcCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
26504
26505#undef ARM_VARIANT
26506#define ARM_VARIANT & fpu_vfp_ext_v1xd
26507
26508 MNCE(vmov, 0, 1, (VMOV), neon_mov),
26509 mcCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
26510 mcCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
26511 mcCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
26512
886e1c73
AV		 26513 mCEF(vmullt, _vmullt, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ), mve_vmull),
26514 mnCEF(vadd, _vadd, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i),
26515 mnCEF(vsub, _vsub, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i),
5ee91343 26516
485dee97
AV		 26517 MNCEF(vabs, 1b10300, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg),
26518 MNCEF(vneg, 1b10380, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg),
26519
57785aa2
AV		 26520 mCEF(vmovlt, _vmovlt, 1, (VMOV), mve_movl),
26521 mCEF(vmovlb, _vmovlb, 1, (VMOV), mve_movl),
26522
1b883319
AV		 26523 mnCE(vcmp, _vcmp, 3, (RVSD_COND, RSVDMQ_FI0, oRMQRZ), vfp_nsyn_cmp),
26524 mnCE(vcmpe, _vcmpe, 3, (RVSD_COND, RSVDMQ_FI0, oRMQRZ), vfp_nsyn_cmp),
26525
57785aa2
AV		 26526#undef ARM_VARIANT
26527#define ARM_VARIANT & fpu_vfp_ext_v2
26528
26529 mcCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
26530 mcCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
26531 mcCE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
26532 mcCE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
26533
dd9634d9
AV		 26534#undef ARM_VARIANT
26535#define ARM_VARIANT & fpu_vfp_ext_armv8xd
26536 mnUF(vcvta, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvta),
26537 mnUF(vcvtp, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtp),
26538 mnUF(vcvtn, _vcvta, 3, (RNSDQMQ, oRNSDQMQ, oI32z), neon_cvtn),
26539 mnUF(vcvtm, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtm),
935295b5
AV		 26540 mnUF(vmaxnm, _vmaxnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm),
26541 mnUF(vminnm, _vminnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm),
dd9634d9
AV		 26542
26543#undef ARM_VARIANT
5ee91343 26544#define ARM_VARIANT & fpu_neon_ext_v1
f601a00c 26545 mnUF(vabd, _vabd, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
5ee91343 26546 mnUF(vabdl, _vabdl, 3, (RNQMQ, RNDMQ, RNDMQ), neon_dyadic_long),
66d1f7cc
AV		 26547 mnUF(vaddl, _vaddl, 3, (RNSDQMQ, oRNSDMQ, RNSDMQR), neon_dyadic_long),
26548 mnUF(vsubl, _vsubl, 3, (RNSDQMQ, oRNSDMQ, RNSDMQR), neon_dyadic_long),
f601a00c
AV		 26549 mnUF(vand, _vand, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
26550 mnUF(vbic, _vbic, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
26551 mnUF(vorr, _vorr, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
26552 mnUF(vorn, _vorn, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
26553 mnUF(veor, _veor, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_logic),
f30ee27c
AV		 26554 MNUF(vcls, 1b00400, 2, (RNDQMQ, RNDQMQ), neon_cls),
26555 MNUF(vclz, 1b00480, 2, (RNDQMQ, RNDQMQ), neon_clz),
b409bdb6 26556 mnCE(vdup, _vdup, 2, (RNDQMQ, RR_RNSC), neon_dup),
7df54120
AV		 26557 MNUF(vhadd, 00000000, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su),
26558 MNUF(vrhadd, 00000100, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_i_su),
26559 MNUF(vhsub, 00000200, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su),
935295b5
AV		 26560 mnUF(vmin, _vmin, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
26561 mnUF(vmax, _vmax, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
a8465a06
AV		 26562 MNUF(vqadd, 0000010, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i64_su),
26563 MNUF(vqsub, 0000210, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i64_su),
1a186d29
AV		 26564 mnUF(vmvn, _vmvn, 2, (RNDQMQ, RNDQMQ_Ibig), neon_mvn),
26565 MNUF(vqabs, 1b00700, 2, (RNDQMQ, RNDQMQ), neon_sat_abs_neg),
26566 MNUF(vqneg, 1b00780, 2, (RNDQMQ, RNDQMQ), neon_sat_abs_neg),
42b16635
AV		 26567 mnUF(vqrdmlah, _vqrdmlah,3, (RNDQMQ, oRNDQMQ, RNDQ_RNSC_RR), neon_qrdmlah),
26568 mnUF(vqdmulh, _vqdmulh, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_RNSC_RR), neon_qdmulh),
26569 mnUF(vqrdmulh, _vqrdmulh,3, (RNDQMQ, oRNDQMQ, RNDQMQ_RNSC_RR), neon_qdmulh),
1be7aba3
AV		 26570 MNUF(vqrshl, 0000510, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_rshl),
26571 MNUF(vrshl, 0000500, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_rshl),
4401c241
AV		 26572 MNUF(vshr, 0800010, 3, (RNDQMQ, oRNDQMQ, I64z), neon_rshift_round_imm),
26573 MNUF(vrshr, 0800210, 3, (RNDQMQ, oRNDQMQ, I64z), neon_rshift_round_imm),
26574 MNUF(vsli, 1800510, 3, (RNDQMQ, oRNDQMQ, I63), neon_sli),
26575 MNUF(vsri, 1800410, 3, (RNDQMQ, oRNDQMQ, I64z), neon_sri),
26576 MNUF(vrev64, 1b00000, 2, (RNDQMQ, RNDQMQ), neon_rev),
26577 MNUF(vrev32, 1b00080, 2, (RNDQMQ, RNDQMQ), neon_rev),
26578 MNUF(vrev16, 1b00100, 2, (RNDQMQ, RNDQMQ), neon_rev),
5150f0d8
AV		 26579 mnUF(vshl, _vshl, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_I63b_RR), neon_shl),
26580 mnUF(vqshl, _vqshl, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_I63b_RR), neon_qshl),
26581 MNUF(vqshlu, 1800610, 3, (RNDQMQ, oRNDQMQ, I63), neon_qshlu_imm),
5d281bf0
AV		 26582
26583#undef ARM_VARIANT
26584#define ARM_VARIANT & arm_ext_v8_3
26585#undef THUMB_VARIANT
26586#define THUMB_VARIANT & arm_ext_v6t2_v8m
26587 MNUF (vcadd, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ, EXPi), vcadd),
26588 MNUF (vcmla, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ_RNSC, EXPi), vcmla),
aab2c27d
MM		 26589
26590#undef ARM_VARIANT
26591#define ARM_VARIANT &arm_ext_bf16
26592#undef THUMB_VARIANT
26593#define THUMB_VARIANT &arm_ext_bf16
26594 TUF ("vdot", c000d00, fc000d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), vdot, vdot),
26595 TUF ("vmmla", c000c40, fc000c40, 3, (RNQ, RNQ, RNQ), vmmla, vmmla),
26596 TUF ("vfmab", c300810, fc300810, 3, (RNDQ, RNDQ, RNDQ_RNSC), bfloat_vfma, bfloat_vfma),
26597
26598#undef ARM_VARIANT
26599#define ARM_VARIANT &arm_ext_i8mm
26600#undef THUMB_VARIANT
26601#define THUMB_VARIANT &arm_ext_i8mm
26602 TUF ("vsmmla", c200c40, fc200c40, 3, (RNQ, RNQ, RNQ), vsmmla, vsmmla),
26603 TUF ("vummla", c200c50, fc200c50, 3, (RNQ, RNQ, RNQ), vummla, vummla),
616ce08e 26604 TUF ("vusmmla", ca00c40, fca00c40, 3, (RNQ, RNQ, RNQ), vsmmla, vsmmla),
aab2c27d
MM		 26605 TUF ("vusdot", c800d00, fc800d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), vusdot, vusdot),
26606 TUF ("vsudot", c800d10, fc800d10, 3, (RNDQ, RNDQ, RNSC), vsudot, vsudot),
4934a27c
MM		 26607
26608#undef ARM_VARIANT
26609#undef THUMB_VARIANT
26610#define THUMB_VARIANT &arm_ext_cde
26611 ToC ("cx1", ee000000, 3, (RCP, APSR_RR, I8191), cx1),
26612 ToC ("cx1a", fe000000, 3, (RCP, APSR_RR, I8191), cx1a),
26613 ToC ("cx1d", ee000040, 4, (RCP, RR, APSR_RR, I8191), cx1d),
26614 ToC ("cx1da", fe000040, 4, (RCP, RR, APSR_RR, I8191), cx1da),
26615
26616 ToC ("cx2", ee400000, 4, (RCP, APSR_RR, APSR_RR, I511), cx2),
26617 ToC ("cx2a", fe400000, 4, (RCP, APSR_RR, APSR_RR, I511), cx2a),
26618 ToC ("cx2d", ee400040, 5, (RCP, RR, APSR_RR, APSR_RR, I511), cx2d),
26619 ToC ("cx2da", fe400040, 5, (RCP, RR, APSR_RR, APSR_RR, I511), cx2da),
26620
26621 ToC ("cx3", ee800000, 5, (RCP, APSR_RR, APSR_RR, APSR_RR, I63), cx3),
26622 ToC ("cx3a", fe800000, 5, (RCP, APSR_RR, APSR_RR, APSR_RR, I63), cx3a),
26623 ToC ("cx3d", ee800040, 6, (RCP, RR, APSR_RR, APSR_RR, APSR_RR, I63), cx3d),
26624 ToC ("cx3da", fe800040, 6, (RCP, RR, APSR_RR, APSR_RR, APSR_RR, I63), cx3da),
5aae9ae9
MM		 26625
26626 mToC ("vcx1", ec200000, 3, (RCP, RNSDMQ, I4095), vcx1),
26627 mToC ("vcx1a", fc200000, 3, (RCP, RNSDMQ, I4095), vcx1),
26628
26629 mToC ("vcx2", ec300000, 4, (RCP, RNSDMQ, RNSDMQ, I127), vcx2),
26630 mToC ("vcx2a", fc300000, 4, (RCP, RNSDMQ, RNSDMQ, I127), vcx2),
26631
26632 mToC ("vcx3", ec800000, 5, (RCP, RNSDMQ, RNSDMQ, RNSDMQ, I15), vcx3),
26633 mToC ("vcx3a", fc800000, 5, (RCP, RNSDMQ, RNSDMQ, RNSDMQ, I15), vcx3),
c19d1205 26634};
5aae9ae9 26635
c19d1205
ZW		 26636#undef ARM_VARIANT
26637#undef THUMB_VARIANT
26638#undef TCE
c19d1205
ZW		 26639#undef TUE
26640#undef TUF
26641#undef TCC
8f06b2d8 26642#undef cCE
e3cb604e
PB		 26643#undef cCL
26644#undef C3E
4389b29a 26645#undef C3
c19d1205
ZW		 26646#undef CE
26647#undef CM
4389b29a 26648#undef CL
c19d1205
ZW		 26649#undef UE
26650#undef UF
26651#undef UT
5287ad62
JB		 26652#undef NUF
26653#undef nUF
26654#undef NCE
26655#undef nCE
c19d1205
ZW		 26656#undef OPS0
26657#undef OPS1
26658#undef OPS2
26659#undef OPS3
26660#undef OPS4
26661#undef OPS5
26662#undef OPS6
26663#undef do_0
4389b29a
AV		 26664#undef ToC
26665#undef toC
26666#undef ToU
f6b2b12d 26667#undef toU
c19d1205
ZW		 26668\f
26669/* MD interface: bits in the object file. */
bfae80f2 26670
c19d1205
ZW		 26671/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
26672 for use in the a.out file, and stores them in the array pointed to by buf.
26673 This knows about the endian-ness of the target machine and does
26674 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
26675 2 (short) and 4 (long) Floating numbers are put out as a series of
26676 LITTLENUMS (shorts, here at least). */
b99bd4ef 26677
c19d1205
ZW		 26678void
26679md_number_to_chars (char * buf, valueT val, int n)
26680{
26681 if (target_big_endian)
26682 number_to_chars_bigendian (buf, val, n);
26683 else
26684 number_to_chars_littleendian (buf, val, n);
bfae80f2
RE		 26685}
26686
c19d1205
ZW		 26687static valueT
26688md_chars_to_number (char * buf, int n)
bfae80f2 26689{
c19d1205
ZW		 26690 valueT result = 0;
26691 unsigned char * where = (unsigned char *) buf;
bfae80f2 26692
c19d1205 26693 if (target_big_endian)
b99bd4ef 26694 {
c19d1205
ZW		 26695 while (n--)
26696 {
26697 result <<= 8;
26698 result |= (*where++ & 255);
26699 }
b99bd4ef 26700 }
c19d1205 26701 else
b99bd4ef 26702 {
c19d1205
ZW		 26703 while (n--)
26704 {
26705 result <<= 8;
26706 result |= (where[n] & 255);
26707 }
bfae80f2 26708 }
b99bd4ef 26709
c19d1205 26710 return result;
bfae80f2 26711}
b99bd4ef 26712
c19d1205 26713/* MD interface: Sections. */
b99bd4ef 26714
fa94de6b
RM		 26715/* Calculate the maximum variable size (i.e., excluding fr_fix)
26716 that an rs_machine_dependent frag may reach. */
26717
26718unsigned int
26719arm_frag_max_var (fragS *fragp)
26720{
26721 /* We only use rs_machine_dependent for variable-size Thumb instructions,
26722 which are either THUMB_SIZE (2) or INSN_SIZE (4).
26723
26724 Note that we generate relaxable instructions even for cases that don't
26725 really need it, like an immediate that's a trivial constant. So we're
26726 overestimating the instruction size for some of those cases. Rather
26727 than putting more intelligence here, it would probably be better to
26728 avoid generating a relaxation frag in the first place when it can be
26729 determined up front that a short instruction will suffice. */
26730
26731 gas_assert (fragp->fr_type == rs_machine_dependent);
26732 return INSN_SIZE;
26733}
26734
0110f2b8
PB		 26735/* Estimate the size of a frag before relaxing. Assume everything fits in
26736 2 bytes. */
26737
c19d1205 26738int
0110f2b8 26739md_estimate_size_before_relax (fragS * fragp,
c19d1205
ZW		 26740 segT segtype ATTRIBUTE_UNUSED)
26741{
0110f2b8
PB		 26742 fragp->fr_var = 2;
26743 return 2;
26744}
26745
26746/* Convert a machine dependent frag. */
26747
26748void
26749md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
26750{
26751 unsigned long insn;
26752 unsigned long old_op;
26753 char *buf;
26754 expressionS exp;
26755 fixS *fixp;
26756 int reloc_type;
26757 int pc_rel;
26758 int opcode;
26759
26760 buf = fragp->fr_literal + fragp->fr_fix;
26761
26762 old_op = bfd_get_16(abfd, buf);
5f4273c7
NC		 26763 if (fragp->fr_symbol)
26764 {
0110f2b8
PB		 26765 exp.X_op = O_symbol;
26766 exp.X_add_symbol = fragp->fr_symbol;
5f4273c7
NC		 26767 }
26768 else
26769 {
0110f2b8 26770 exp.X_op = O_constant;
5f4273c7 26771 }
0110f2b8
PB		 26772 exp.X_add_number = fragp->fr_offset;
26773 opcode = fragp->fr_subtype;
26774 switch (opcode)
26775 {
26776 case T_MNEM_ldr_pc:
26777 case T_MNEM_ldr_pc2:
26778 case T_MNEM_ldr_sp:
26779 case T_MNEM_str_sp:
26780 case T_MNEM_ldr:
26781 case T_MNEM_ldrb:
26782 case T_MNEM_ldrh:
26783 case T_MNEM_str:
26784 case T_MNEM_strb:
26785 case T_MNEM_strh:
26786 if (fragp->fr_var == 4)
26787 {
5f4273c7 26788 insn = THUMB_OP32 (opcode);
0110f2b8
PB		 26789 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
26790 {
26791 insn |= (old_op & 0x700) << 4;
26792 }
26793 else
26794 {
26795 insn |= (old_op & 7) << 12;
26796 insn |= (old_op & 0x38) << 13;
26797 }
26798 insn |= 0x00000c00;
26799 put_thumb32_insn (buf, insn);
26800 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
26801 }
26802 else
26803 {
26804 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
26805 }
26806 pc_rel = (opcode == T_MNEM_ldr_pc2);
26807 break;
26808 case T_MNEM_adr:
26809 if (fragp->fr_var == 4)
26810 {
26811 insn = THUMB_OP32 (opcode);
26812 insn |= (old_op & 0xf0) << 4;
26813 put_thumb32_insn (buf, insn);
26814 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
26815 }
26816 else
26817 {
26818 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
26819 exp.X_add_number -= 4;
26820 }
26821 pc_rel = 1;
26822 break;
26823 case T_MNEM_mov:
26824 case T_MNEM_movs:
26825 case T_MNEM_cmp:
26826 case T_MNEM_cmn:
26827 if (fragp->fr_var == 4)
26828 {
26829 int r0off = (opcode == T_MNEM_mov
26830 || opcode == T_MNEM_movs) ? 0 : 8;
26831 insn = THUMB_OP32 (opcode);
26832 insn = (insn & 0xe1ffffff) | 0x10000000;
26833 insn |= (old_op & 0x700) << r0off;
26834 put_thumb32_insn (buf, insn);
26835 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
26836 }
26837 else
26838 {
26839 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
26840 }
26841 pc_rel = 0;
26842 break;
26843 case T_MNEM_b:
26844 if (fragp->fr_var == 4)
26845 {
26846 insn = THUMB_OP32(opcode);
26847 put_thumb32_insn (buf, insn);
26848 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
26849 }
26850 else
26851 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
26852 pc_rel = 1;
26853 break;
26854 case T_MNEM_bcond:
26855 if (fragp->fr_var == 4)
26856 {
26857 insn = THUMB_OP32(opcode);
26858 insn |= (old_op & 0xf00) << 14;
26859 put_thumb32_insn (buf, insn);
26860 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
26861 }
26862 else
26863 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
26864 pc_rel = 1;
26865 break;
26866 case T_MNEM_add_sp:
26867 case T_MNEM_add_pc:
26868 case T_MNEM_inc_sp:
26869 case T_MNEM_dec_sp:
26870 if (fragp->fr_var == 4)
26871 {
26872 /* ??? Choose between add and addw. */
26873 insn = THUMB_OP32 (opcode);
26874 insn |= (old_op & 0xf0) << 4;
26875 put_thumb32_insn (buf, insn);
16805f35
PB		 26876 if (opcode == T_MNEM_add_pc)
26877 reloc_type = BFD_RELOC_ARM_T32_IMM12;
26878 else
26879 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
0110f2b8
PB		 26880 }
26881 else
26882 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
26883 pc_rel = 0;
26884 break;
26885
26886 case T_MNEM_addi:
26887 case T_MNEM_addis:
26888 case T_MNEM_subi:
26889 case T_MNEM_subis:
26890 if (fragp->fr_var == 4)
26891 {
26892 insn = THUMB_OP32 (opcode);
26893 insn |= (old_op & 0xf0) << 4;
26894 insn |= (old_op & 0xf) << 16;
26895 put_thumb32_insn (buf, insn);
16805f35
PB		 26896 if (insn & (1 << 20))
26897 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
26898 else
26899 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
0110f2b8
PB		 26900 }
26901 else
26902 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
26903 pc_rel = 0;
26904 break;
26905 default:
5f4273c7 26906 abort ();
0110f2b8
PB		 26907 }
26908 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
21d799b5 26909 (enum bfd_reloc_code_real) reloc_type);
0110f2b8
PB		 26910 fixp->fx_file = fragp->fr_file;
26911 fixp->fx_line = fragp->fr_line;
26912 fragp->fr_fix += fragp->fr_var;
3cfdb781
TG		 26913
26914 /* Set whether we use thumb-2 ISA based on final relaxation results. */
26915 if (thumb_mode && fragp->fr_var == 4 && no_cpu_selected ()
26916 && !ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2))
26917 ARM_MERGE_FEATURE_SETS (arm_arch_used, thumb_arch_used, arm_ext_v6t2);
0110f2b8
PB		 26918}
26919
26920/* Return the size of a relaxable immediate operand instruction.
26921 SHIFT and SIZE specify the form of the allowable immediate. */
26922static int
26923relax_immediate (fragS *fragp, int size, int shift)
26924{
26925 offsetT offset;
26926 offsetT mask;
26927 offsetT low;
26928
26929 /* ??? Should be able to do better than this. */
26930 if (fragp->fr_symbol)
26931 return 4;
26932
26933 low = (1 << shift) - 1;
26934 mask = (1 << (shift + size)) - (1 << shift);
26935 offset = fragp->fr_offset;
26936 /* Force misaligned offsets to 32-bit variant. */
26937 if (offset & low)
5e77afaa 26938 return 4;
0110f2b8
PB		 26939 if (offset & ~mask)
26940 return 4;
26941 return 2;
26942}
26943
5e77afaa
PB		 26944/* Get the address of a symbol during relaxation. */
26945static addressT
5f4273c7 26946relaxed_symbol_addr (fragS *fragp, long stretch)
5e77afaa
PB		 26947{
26948 fragS *sym_frag;
26949 addressT addr;
26950 symbolS *sym;
26951
26952 sym = fragp->fr_symbol;
26953 sym_frag = symbol_get_frag (sym);
26954 know (S_GET_SEGMENT (sym) != absolute_section
26955 || sym_frag == &zero_address_frag);
26956 addr = S_GET_VALUE (sym) + fragp->fr_offset;
26957
26958 /* If frag has yet to be reached on this pass, assume it will
26959 move by STRETCH just as we did. If this is not so, it will
26960 be because some frag between grows, and that will force
26961 another pass. */
26962
26963 if (stretch != 0
26964 && sym_frag->relax_marker != fragp->relax_marker)
4396b686
PB		 26965 {
26966 fragS *f;
26967
26968 /* Adjust stretch for any alignment frag. Note that if have
26969 been expanding the earlier code, the symbol may be
26970 defined in what appears to be an earlier frag. FIXME:
26971 This doesn't handle the fr_subtype field, which specifies
26972 a maximum number of bytes to skip when doing an
26973 alignment. */
26974 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
26975 {
26976 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
26977 {
26978 if (stretch < 0)
26979 stretch = - ((- stretch)
26980 & ~ ((1 << (int) f->fr_offset) - 1));
26981 else
26982 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
26983 if (stretch == 0)
26984 break;
26985 }
26986 }
26987 if (f != NULL)
26988 addr += stretch;
26989 }
5e77afaa
PB		 26990
26991 return addr;
26992}
26993
0110f2b8
PB		 26994/* Return the size of a relaxable adr pseudo-instruction or PC-relative
26995 load. */
26996static int
5e77afaa 26997relax_adr (fragS *fragp, asection *sec, long stretch)
0110f2b8
PB		 26998{
26999 addressT addr;
27000 offsetT val;
27001
27002 /* Assume worst case for symbols not known to be in the same section. */
974da60d
NC		 27003 if (fragp->fr_symbol == NULL
27004 || !S_IS_DEFINED (fragp->fr_symbol)
77db8e2e
NC		 27005 || sec != S_GET_SEGMENT (fragp->fr_symbol)
27006 || S_IS_WEAK (fragp->fr_symbol))
0110f2b8
PB		 27007 return 4;
27008
5f4273c7 27009 val = relaxed_symbol_addr (fragp, stretch);
0110f2b8
PB		 27010 addr = fragp->fr_address + fragp->fr_fix;
27011 addr = (addr + 4) & ~3;
5e77afaa 27012 /* Force misaligned targets to 32-bit variant. */
0110f2b8 27013 if (val & 3)
5e77afaa 27014 return 4;
0110f2b8
PB		 27015 val -= addr;
27016 if (val < 0 || val > 1020)
27017 return 4;
27018 return 2;
27019}
27020
27021/* Return the size of a relaxable add/sub immediate instruction. */
27022static int
27023relax_addsub (fragS *fragp, asection *sec)
27024{
27025 char *buf;
27026 int op;
27027
27028 buf = fragp->fr_literal + fragp->fr_fix;
27029 op = bfd_get_16(sec->owner, buf);
27030 if ((op & 0xf) == ((op >> 4) & 0xf))
27031 return relax_immediate (fragp, 8, 0);
27032 else
27033 return relax_immediate (fragp, 3, 0);
27034}
27035
e83a675f
RE		 27036/* Return TRUE iff the definition of symbol S could be pre-empted
27037 (overridden) at link or load time. */
27038static bfd_boolean
27039symbol_preemptible (symbolS *s)
27040{
27041 /* Weak symbols can always be pre-empted. */
27042 if (S_IS_WEAK (s))
27043 return TRUE;
27044
27045 /* Non-global symbols cannot be pre-empted. */
27046 if (! S_IS_EXTERNAL (s))
27047 return FALSE;
27048
27049#ifdef OBJ_ELF
27050 /* In ELF, a global symbol can be marked protected, or private. In that
27051 case it can't be pre-empted (other definitions in the same link unit
27052 would violate the ODR). */
27053 if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT)
27054 return FALSE;
27055#endif
27056
27057 /* Other global symbols might be pre-empted. */
27058 return TRUE;
27059}
0110f2b8
PB		 27060
27061/* Return the size of a relaxable branch instruction. BITS is the
27062 size of the offset field in the narrow instruction. */
27063
27064static int
5e77afaa 27065relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
0110f2b8
PB		 27066{
27067 addressT addr;
27068 offsetT val;
27069 offsetT limit;
27070
27071 /* Assume worst case for symbols not known to be in the same section. */
5f4273c7 27072 if (!S_IS_DEFINED (fragp->fr_symbol)
77db8e2e
NC		 27073 || sec != S_GET_SEGMENT (fragp->fr_symbol)
27074 || S_IS_WEAK (fragp->fr_symbol))
0110f2b8
PB		 27075 return 4;
27076
267bf995 27077#ifdef OBJ_ELF
e83a675f 27078 /* A branch to a function in ARM state will require interworking. */
267bf995
RR		 27079 if (S_IS_DEFINED (fragp->fr_symbol)
27080 && ARM_IS_FUNC (fragp->fr_symbol))
27081 return 4;
e83a675f 27082#endif
0d9b4b55 27083
e83a675f 27084 if (symbol_preemptible (fragp->fr_symbol))
0d9b4b55 27085 return 4;
267bf995 27086
5f4273c7 27087 val = relaxed_symbol_addr (fragp, stretch);
0110f2b8
PB		 27088 addr = fragp->fr_address + fragp->fr_fix + 4;
27089 val -= addr;
27090
27091 /* Offset is a signed value *2 */
27092 limit = 1 << bits;
27093 if (val >= limit || val < -limit)
27094 return 4;
27095 return 2;
27096}
27097
27098
27099/* Relax a machine dependent frag. This returns the amount by which
27100 the current size of the frag should change. */
27101
27102int
5e77afaa 27103arm_relax_frag (asection *sec, fragS *fragp, long stretch)
0110f2b8
PB		 27104{
27105 int oldsize;
27106 int newsize;
27107
27108 oldsize = fragp->fr_var;
27109 switch (fragp->fr_subtype)
27110 {
27111 case T_MNEM_ldr_pc2:
5f4273c7 27112 newsize = relax_adr (fragp, sec, stretch);
0110f2b8
PB		 27113 break;
27114 case T_MNEM_ldr_pc:
27115 case T_MNEM_ldr_sp:
27116 case T_MNEM_str_sp:
5f4273c7 27117 newsize = relax_immediate (fragp, 8, 2);
0110f2b8
PB		 27118 break;
27119 case T_MNEM_ldr:
27120 case T_MNEM_str:
5f4273c7 27121 newsize = relax_immediate (fragp, 5, 2);
0110f2b8
PB		 27122 break;
27123 case T_MNEM_ldrh:
27124 case T_MNEM_strh:
5f4273c7 27125 newsize = relax_immediate (fragp, 5, 1);
0110f2b8
PB		 27126 break;
27127 case T_MNEM_ldrb:
27128 case T_MNEM_strb:
5f4273c7 27129 newsize = relax_immediate (fragp, 5, 0);
0110f2b8
PB		 27130 break;
27131 case T_MNEM_adr:
5f4273c7 27132 newsize = relax_adr (fragp, sec, stretch);
0110f2b8
PB		 27133 break;
27134 case T_MNEM_mov:
27135 case T_MNEM_movs:
27136 case T_MNEM_cmp:
27137 case T_MNEM_cmn:
5f4273c7 27138 newsize = relax_immediate (fragp, 8, 0);
0110f2b8
PB		 27139 break;
27140 case T_MNEM_b:
5f4273c7 27141 newsize = relax_branch (fragp, sec, 11, stretch);
0110f2b8
PB		 27142 break;
27143 case T_MNEM_bcond:
5f4273c7 27144 newsize = relax_branch (fragp, sec, 8, stretch);
0110f2b8
PB		 27145 break;
27146 case T_MNEM_add_sp:
27147 case T_MNEM_add_pc:
27148 newsize = relax_immediate (fragp, 8, 2);
27149 break;
27150 case T_MNEM_inc_sp:
27151 case T_MNEM_dec_sp:
27152 newsize = relax_immediate (fragp, 7, 2);
27153 break;
27154 case T_MNEM_addi:
27155 case T_MNEM_addis:
27156 case T_MNEM_subi:
27157 case T_MNEM_subis:
27158 newsize = relax_addsub (fragp, sec);
27159 break;
27160 default:
5f4273c7 27161 abort ();
0110f2b8 27162 }
5e77afaa
PB		 27163
27164 fragp->fr_var = newsize;
27165 /* Freeze wide instructions that are at or before the same location as
27166 in the previous pass. This avoids infinite loops.
5f4273c7
NC		 27167 Don't freeze them unconditionally because targets may be artificially
27168 misaligned by the expansion of preceding frags. */
5e77afaa 27169 if (stretch <= 0 && newsize > 2)
0110f2b8 27170 {
0110f2b8 27171 md_convert_frag (sec->owner, sec, fragp);
5f4273c7 27172 frag_wane (fragp);
0110f2b8 27173 }
5e77afaa 27174
0110f2b8 27175 return newsize - oldsize;
c19d1205 27176}
b99bd4ef 27177
c19d1205 27178/* Round up a section size to the appropriate boundary. */
b99bd4ef 27179
c19d1205
ZW		 27180valueT
27181md_section_align (segT segment ATTRIBUTE_UNUSED,
27182 valueT size)
27183{
6844c0cc 27184 return size;
bfae80f2 27185}
b99bd4ef 27186
c19d1205
ZW		 27187/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
27188 of an rs_align_code fragment. */
27189
27190void
27191arm_handle_align (fragS * fragP)
bfae80f2 27192{
d9235011 27193 static unsigned char const arm_noop[2][2][4] =
e7495e45
NS		 27194 {
27195 { /* ARMv1 */
27196 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
27197 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
27198 },
27199 { /* ARMv6k */
27200 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
27201 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
27202 },
27203 };
d9235011 27204 static unsigned char const thumb_noop[2][2][2] =
e7495e45
NS		 27205 {
27206 { /* Thumb-1 */
27207 {0xc0, 0x46}, /* LE */
27208 {0x46, 0xc0}, /* BE */
27209 },
27210 { /* Thumb-2 */
27211 {0x00, 0xbf}, /* LE */
27212 {0xbf, 0x00} /* BE */
27213 }
27214 };
d9235011 27215 static unsigned char const wide_thumb_noop[2][4] =
e7495e45
NS		 27216 { /* Wide Thumb-2 */
27217 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
27218 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
27219 };
c921be7d 27220
e7495e45 27221 unsigned bytes, fix, noop_size;
c19d1205 27222 char * p;
d9235011
TS		 27223 const unsigned char * noop;
27224 const unsigned char *narrow_noop = NULL;
cd000bff
DJ		 27225#ifdef OBJ_ELF
27226 enum mstate state;
27227#endif
bfae80f2 27228
c19d1205 27229 if (fragP->fr_type != rs_align_code)
bfae80f2
RE		 27230 return;
27231
c19d1205
ZW		 27232 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
27233 p = fragP->fr_literal + fragP->fr_fix;
27234 fix = 0;
bfae80f2 27235
c19d1205
ZW		 27236 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
27237 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
bfae80f2 27238
cd000bff 27239 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
8dc2430f 27240
cd000bff 27241 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
a737bd4d 27242 {
7f78eb34
JW		 27243 if (ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
27244 ? selected_cpu : arm_arch_none, arm_ext_v6t2))
e7495e45
NS		 27245 {
27246 narrow_noop = thumb_noop[1][target_big_endian];
27247 noop = wide_thumb_noop[target_big_endian];
27248 }
c19d1205 27249 else
e7495e45
NS		 27250 noop = thumb_noop[0][target_big_endian];
27251 noop_size = 2;
cd000bff
DJ		 27252#ifdef OBJ_ELF
27253 state = MAP_THUMB;
27254#endif
7ed4c4c5
NC		 27255 }
27256 else
27257 {
7f78eb34
JW		 27258 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
27259 ? selected_cpu : arm_arch_none,
27260 arm_ext_v6k) != 0]
e7495e45
NS		 27261 [target_big_endian];
27262 noop_size = 4;
cd000bff
DJ		 27263#ifdef OBJ_ELF
27264 state = MAP_ARM;
27265#endif
7ed4c4c5 27266 }
c921be7d 27267
e7495e45 27268 fragP->fr_var = noop_size;
c921be7d 27269
c19d1205 27270 if (bytes & (noop_size - 1))
7ed4c4c5 27271 {
c19d1205 27272 fix = bytes & (noop_size - 1);
cd000bff
DJ		 27273#ifdef OBJ_ELF
27274 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
27275#endif
c19d1205
ZW		 27276 memset (p, 0, fix);
27277 p += fix;
27278 bytes -= fix;
a737bd4d 27279 }
a737bd4d 27280
e7495e45
NS		 27281 if (narrow_noop)
27282 {
27283 if (bytes & noop_size)
27284 {
27285 /* Insert a narrow noop. */
27286 memcpy (p, narrow_noop, noop_size);
27287 p += noop_size;
27288 bytes -= noop_size;
27289 fix += noop_size;
27290 }
27291
27292 /* Use wide noops for the remainder */
27293 noop_size = 4;
27294 }
27295
c19d1205 27296 while (bytes >= noop_size)
a737bd4d 27297 {
c19d1205
ZW		 27298 memcpy (p, noop, noop_size);
27299 p += noop_size;
27300 bytes -= noop_size;
27301 fix += noop_size;
a737bd4d
NC		 27302 }
27303
c19d1205 27304 fragP->fr_fix += fix;
a737bd4d
NC		 27305}
27306
c19d1205
ZW		 27307/* Called from md_do_align. Used to create an alignment
27308 frag in a code section. */
27309
27310void
27311arm_frag_align_code (int n, int max)
bfae80f2 27312{
c19d1205 27313 char * p;
7ed4c4c5 27314
c19d1205 27315 /* We assume that there will never be a requirement
6ec8e702 27316 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
c19d1205 27317 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
6ec8e702
NC		 27318 {
27319 char err_msg[128];
27320
fa94de6b 27321 sprintf (err_msg,
477330fc
RM		 27322 _("alignments greater than %d bytes not supported in .text sections."),
27323 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
20203fb9 27324 as_fatal ("%s", err_msg);
6ec8e702 27325 }
bfae80f2 27326
c19d1205
ZW		 27327 p = frag_var (rs_align_code,
27328 MAX_MEM_FOR_RS_ALIGN_CODE,
27329 1,
27330 (relax_substateT) max,
27331 (symbolS *) NULL,
27332 (offsetT) n,
27333 (char *) NULL);
27334 *p = 0;
27335}
bfae80f2 27336
8dc2430f
NC		 27337/* Perform target specific initialisation of a frag.
27338 Note - despite the name this initialisation is not done when the frag
27339 is created, but only when its type is assigned. A frag can be created
27340 and used a long time before its type is set, so beware of assuming that
33eaf5de 27341 this initialisation is performed first. */
bfae80f2 27342
cd000bff
DJ		 27343#ifndef OBJ_ELF
27344void
27345arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
27346{
27347 /* Record whether this frag is in an ARM or a THUMB area. */
2e98972e 27348 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
cd000bff
DJ		 27349}
27350
27351#else /* OBJ_ELF is defined. */
c19d1205 27352void
cd000bff 27353arm_init_frag (fragS * fragP, int max_chars)
c19d1205 27354{
e8d84ca1 27355 bfd_boolean frag_thumb_mode;
b968d18a 27356
8dc2430f
NC		 27357 /* If the current ARM vs THUMB mode has not already
27358 been recorded into this frag then do so now. */
cd000bff 27359 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
b968d18a
JW		 27360 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
27361
e8d84ca1
NC		 27362 /* PR 21809: Do not set a mapping state for debug sections
27363 - it just confuses other tools. */
fd361982 27364 if (bfd_section_flags (now_seg) & SEC_DEBUGGING)
e8d84ca1
NC		 27365 return;
27366
b968d18a 27367 frag_thumb_mode = fragP->tc_frag_data.thumb_mode ^ MODE_RECORDED;
cd000bff 27368
f9c1b181
RL		 27369 /* Record a mapping symbol for alignment frags. We will delete this
27370 later if the alignment ends up empty. */
27371 switch (fragP->fr_type)
27372 {
27373 case rs_align:
27374 case rs_align_test:
27375 case rs_fill:
27376 mapping_state_2 (MAP_DATA, max_chars);
27377 break;
27378 case rs_align_code:
b968d18a 27379 mapping_state_2 (frag_thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
f9c1b181
RL		 27380 break;
27381 default:
27382 break;
cd000bff 27383 }
bfae80f2
RE		 27384}
27385
c19d1205
ZW		 27386/* When we change sections we need to issue a new mapping symbol. */
27387
27388void
27389arm_elf_change_section (void)
bfae80f2 27390{
c19d1205
ZW		 27391 /* Link an unlinked unwind index table section to the .text section. */
27392 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
27393 && elf_linked_to_section (now_seg) == NULL)
27394 elf_linked_to_section (now_seg) = text_section;
bfae80f2
RE		 27395}
27396
c19d1205
ZW		 27397int
27398arm_elf_section_type (const char * str, size_t len)
e45d0630 27399{
c19d1205
ZW		 27400 if (len == 5 && strncmp (str, "exidx", 5) == 0)
27401 return SHT_ARM_EXIDX;
e45d0630 27402
c19d1205
ZW		 27403 return -1;
27404}
27405\f
27406/* Code to deal with unwinding tables. */
e45d0630 27407
c19d1205 27408static void add_unwind_adjustsp (offsetT);
e45d0630 27409
5f4273c7 27410/* Generate any deferred unwind frame offset. */
e45d0630 27411
bfae80f2 27412static void
c19d1205 27413flush_pending_unwind (void)
bfae80f2 27414{
c19d1205 27415 offsetT offset;
bfae80f2 27416
c19d1205
ZW		 27417 offset = unwind.pending_offset;
27418 unwind.pending_offset = 0;
27419 if (offset != 0)
27420 add_unwind_adjustsp (offset);
bfae80f2
RE		 27421}
27422
c19d1205
ZW		 27423/* Add an opcode to this list for this function. Two-byte opcodes should
27424 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
27425 order. */
27426
bfae80f2 27427static void
c19d1205 27428add_unwind_opcode (valueT op, int length)
bfae80f2 27429{
c19d1205
ZW		 27430 /* Add any deferred stack adjustment. */
27431 if (unwind.pending_offset)
27432 flush_pending_unwind ();
bfae80f2 27433
c19d1205 27434 unwind.sp_restored = 0;
bfae80f2 27435
c19d1205 27436 if (unwind.opcode_count + length > unwind.opcode_alloc)
bfae80f2 27437 {
c19d1205
ZW		 27438 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
27439 if (unwind.opcodes)
325801bd
TS		 27440 unwind.opcodes = XRESIZEVEC (unsigned char, unwind.opcodes,
27441 unwind.opcode_alloc);
c19d1205 27442 else
325801bd 27443 unwind.opcodes = XNEWVEC (unsigned char, unwind.opcode_alloc);
bfae80f2 27444 }
c19d1205 27445 while (length > 0)
bfae80f2 27446 {
c19d1205
ZW		 27447 length--;
27448 unwind.opcodes[unwind.opcode_count] = op & 0xff;
27449 op >>= 8;
27450 unwind.opcode_count++;
bfae80f2 27451 }
bfae80f2
RE		 27452}
27453
c19d1205
ZW		 27454/* Add unwind opcodes to adjust the stack pointer. */
27455
bfae80f2 27456static void
c19d1205 27457add_unwind_adjustsp (offsetT offset)
bfae80f2 27458{
c19d1205 27459 valueT op;
bfae80f2 27460
c19d1205 27461 if (offset > 0x200)
bfae80f2 27462 {
c19d1205
ZW		 27463 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
27464 char bytes[5];
27465 int n;
27466 valueT o;
bfae80f2 27467
c19d1205
ZW		 27468 /* Long form: 0xb2, uleb128. */
27469 /* This might not fit in a word so add the individual bytes,
27470 remembering the list is built in reverse order. */
27471 o = (valueT) ((offset - 0x204) >> 2);
27472 if (o == 0)
27473 add_unwind_opcode (0, 1);
bfae80f2 27474
c19d1205
ZW		 27475 /* Calculate the uleb128 encoding of the offset. */
27476 n = 0;
27477 while (o)
27478 {
27479 bytes[n] = o & 0x7f;
27480 o >>= 7;
27481 if (o)
27482 bytes[n] |= 0x80;
27483 n++;
27484 }
27485 /* Add the insn. */
27486 for (; n; n--)
27487 add_unwind_opcode (bytes[n - 1], 1);
27488 add_unwind_opcode (0xb2, 1);
27489 }
27490 else if (offset > 0x100)
bfae80f2 27491 {
c19d1205
ZW		 27492 /* Two short opcodes. */
27493 add_unwind_opcode (0x3f, 1);
27494 op = (offset - 0x104) >> 2;
27495 add_unwind_opcode (op, 1);
bfae80f2 27496 }
c19d1205
ZW		 27497 else if (offset > 0)
27498 {
27499 /* Short opcode. */
27500 op = (offset - 4) >> 2;
27501 add_unwind_opcode (op, 1);
27502 }
27503 else if (offset < 0)
bfae80f2 27504 {
c19d1205
ZW		 27505 offset = -offset;
27506 while (offset > 0x100)
bfae80f2 27507 {
c19d1205
ZW		 27508 add_unwind_opcode (0x7f, 1);
27509 offset -= 0x100;
bfae80f2 27510 }
c19d1205
ZW		 27511 op = ((offset - 4) >> 2) | 0x40;
27512 add_unwind_opcode (op, 1);
bfae80f2 27513 }
bfae80f2
RE		 27514}
27515
c19d1205 27516/* Finish the list of unwind opcodes for this function. */
0198d5e6 27517
c19d1205
ZW		 27518static void
27519finish_unwind_opcodes (void)
bfae80f2 27520{
c19d1205 27521 valueT op;
bfae80f2 27522
c19d1205 27523 if (unwind.fp_used)
bfae80f2 27524 {
708587a4 27525 /* Adjust sp as necessary. */
c19d1205
ZW		 27526 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
27527 flush_pending_unwind ();
bfae80f2 27528
c19d1205
ZW		 27529 /* After restoring sp from the frame pointer. */
27530 op = 0x90 | unwind.fp_reg;
27531 add_unwind_opcode (op, 1);
27532 }
27533 else
27534 flush_pending_unwind ();
bfae80f2
RE		 27535}
27536
bfae80f2 27537
c19d1205
ZW		 27538/* Start an exception table entry. If idx is nonzero this is an index table
27539 entry. */
bfae80f2
RE		 27540
27541static void
c19d1205 27542start_unwind_section (const segT text_seg, int idx)
bfae80f2 27543{
c19d1205
ZW		 27544 const char * text_name;
27545 const char * prefix;
27546 const char * prefix_once;
a8c4d40b 27547 struct elf_section_match match;
c19d1205 27548 char * sec_name;
c19d1205
ZW		 27549 int type;
27550 int flags;
27551 int linkonce;
bfae80f2 27552
c19d1205 27553 if (idx)
bfae80f2 27554 {
c19d1205
ZW		 27555 prefix = ELF_STRING_ARM_unwind;
27556 prefix_once = ELF_STRING_ARM_unwind_once;
27557 type = SHT_ARM_EXIDX;
bfae80f2 27558 }
c19d1205 27559 else
bfae80f2 27560 {
c19d1205
ZW		 27561 prefix = ELF_STRING_ARM_unwind_info;
27562 prefix_once = ELF_STRING_ARM_unwind_info_once;
27563 type = SHT_PROGBITS;
bfae80f2
RE		 27564 }
27565
c19d1205
ZW		 27566 text_name = segment_name (text_seg);
27567 if (streq (text_name, ".text"))
27568 text_name = "";
27569
27570 if (strncmp (text_name, ".gnu.linkonce.t.",
27571 strlen (".gnu.linkonce.t.")) == 0)
bfae80f2 27572 {
c19d1205
ZW		 27573 prefix = prefix_once;
27574 text_name += strlen (".gnu.linkonce.t.");
bfae80f2
RE		 27575 }
27576
29a2809e 27577 sec_name = concat (prefix, text_name, (char *) NULL);
bfae80f2 27578
c19d1205
ZW		 27579 flags = SHF_ALLOC;
27580 linkonce = 0;
a8c4d40b 27581 memset (&match, 0, sizeof (match));
bfae80f2 27582
c19d1205
ZW		 27583 /* Handle COMDAT group. */
27584 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
bfae80f2 27585 {
a8c4d40b
L		 27586 match.group_name = elf_group_name (text_seg);
27587 if (match.group_name == NULL)
c19d1205 27588 {
bd3ba5d1 27589 as_bad (_("Group section `%s' has no group signature"),
c19d1205
ZW		 27590 segment_name (text_seg));
27591 ignore_rest_of_line ();
27592 return;
27593 }
27594 flags |= SHF_GROUP;
27595 linkonce = 1;
bfae80f2
RE		 27596 }
27597
a8c4d40b 27598 obj_elf_change_section (sec_name, type, flags, 0, &match,
a91e1603 27599 linkonce, 0);
bfae80f2 27600
5f4273c7 27601 /* Set the section link for index tables. */
c19d1205
ZW		 27602 if (idx)
27603 elf_linked_to_section (now_seg) = text_seg;
bfae80f2
RE		 27604}
27605
bfae80f2 27606
c19d1205
ZW		 27607/* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
27608 personality routine data. Returns zero, or the index table value for
cad0da33 27609 an inline entry. */
c19d1205
ZW		 27610
27611static valueT
27612create_unwind_entry (int have_data)
bfae80f2 27613{
c19d1205
ZW		 27614 int size;
27615 addressT where;
27616 char *ptr;
27617 /* The current word of data. */
27618 valueT data;
27619 /* The number of bytes left in this word. */
27620 int n;
bfae80f2 27621
c19d1205 27622 finish_unwind_opcodes ();
bfae80f2 27623
c19d1205
ZW		 27624 /* Remember the current text section. */
27625 unwind.saved_seg = now_seg;
27626 unwind.saved_subseg = now_subseg;
bfae80f2 27627
c19d1205 27628 start_unwind_section (now_seg, 0);
bfae80f2 27629
c19d1205 27630 if (unwind.personality_routine == NULL)
bfae80f2 27631 {
c19d1205
ZW		 27632 if (unwind.personality_index == -2)
27633 {
27634 if (have_data)
5f4273c7 27635 as_bad (_("handlerdata in cantunwind frame"));
c19d1205
ZW		 27636 return 1; /* EXIDX_CANTUNWIND. */
27637 }
bfae80f2 27638
c19d1205
ZW		 27639 /* Use a default personality routine if none is specified. */
27640 if (unwind.personality_index == -1)
27641 {
27642 if (unwind.opcode_count > 3)
27643 unwind.personality_index = 1;
27644 else
27645 unwind.personality_index = 0;
27646 }
bfae80f2 27647
c19d1205
ZW		 27648 /* Space for the personality routine entry. */
27649 if (unwind.personality_index == 0)
27650 {
27651 if (unwind.opcode_count > 3)
27652 as_bad (_("too many unwind opcodes for personality routine 0"));
bfae80f2 27653
c19d1205
ZW		 27654 if (!have_data)
27655 {
27656 /* All the data is inline in the index table. */
27657 data = 0x80;
27658 n = 3;
27659 while (unwind.opcode_count > 0)
27660 {
27661 unwind.opcode_count--;
27662 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
27663 n--;
27664 }
bfae80f2 27665
c19d1205
ZW		 27666 /* Pad with "finish" opcodes. */
27667 while (n--)
27668 data = (data << 8) | 0xb0;
bfae80f2 27669
c19d1205
ZW		 27670 return data;
27671 }
27672 size = 0;
27673 }
27674 else
27675 /* We get two opcodes "free" in the first word. */
27676 size = unwind.opcode_count - 2;
27677 }
27678 else
5011093d 27679 {
cad0da33
NC		 27680 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
27681 if (unwind.personality_index != -1)
27682 {
27683 as_bad (_("attempt to recreate an unwind entry"));
27684 return 1;
27685 }
5011093d
NC		 27686
27687 /* An extra byte is required for the opcode count. */
27688 size = unwind.opcode_count + 1;
27689 }
bfae80f2 27690
c19d1205
ZW		 27691 size = (size + 3) >> 2;
27692 if (size > 0xff)
27693 as_bad (_("too many unwind opcodes"));
bfae80f2 27694
c19d1205
ZW		 27695 frag_align (2, 0, 0);
27696 record_alignment (now_seg, 2);
27697 unwind.table_entry = expr_build_dot ();
27698
27699 /* Allocate the table entry. */
27700 ptr = frag_more ((size << 2) + 4);
74929e7b
NC		 27701 /* PR 13449: Zero the table entries in case some of them are not used. */
27702 memset (ptr, 0, (size << 2) + 4);
c19d1205 27703 where = frag_now_fix () - ((size << 2) + 4);
bfae80f2 27704
c19d1205 27705 switch (unwind.personality_index)
bfae80f2 27706 {
c19d1205
ZW		 27707 case -1:
27708 /* ??? Should this be a PLT generating relocation? */
27709 /* Custom personality routine. */
27710 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
27711 BFD_RELOC_ARM_PREL31);
bfae80f2 27712
c19d1205
ZW		 27713 where += 4;
27714 ptr += 4;
bfae80f2 27715
c19d1205 27716 /* Set the first byte to the number of additional words. */
5011093d 27717 data = size > 0 ? size - 1 : 0;
c19d1205
ZW		 27718 n = 3;
27719 break;
bfae80f2 27720
c19d1205
ZW		 27721 /* ABI defined personality routines. */
27722 case 0:
27723 /* Three opcodes bytes are packed into the first word. */
27724 data = 0x80;
27725 n = 3;
27726 break;
bfae80f2 27727
c19d1205
ZW		 27728 case 1:
27729 case 2:
27730 /* The size and first two opcode bytes go in the first word. */
27731 data = ((0x80 + unwind.personality_index) << 8) | size;
27732 n = 2;
27733 break;
bfae80f2 27734
c19d1205
ZW		 27735 default:
27736 /* Should never happen. */
27737 abort ();
27738 }
bfae80f2 27739
c19d1205
ZW		 27740 /* Pack the opcodes into words (MSB first), reversing the list at the same
27741 time. */
27742 while (unwind.opcode_count > 0)
27743 {
27744 if (n == 0)
27745 {
27746 md_number_to_chars (ptr, data, 4);
27747 ptr += 4;
27748 n = 4;
27749 data = 0;
27750 }
27751 unwind.opcode_count--;
27752 n--;
27753 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
27754 }
27755
27756 /* Finish off the last word. */
27757 if (n < 4)
27758 {
27759 /* Pad with "finish" opcodes. */
27760 while (n--)
27761 data = (data << 8) | 0xb0;
27762
27763 md_number_to_chars (ptr, data, 4);
27764 }
27765
27766 if (!have_data)
27767 {
27768 /* Add an empty descriptor if there is no user-specified data. */
27769 ptr = frag_more (4);
27770 md_number_to_chars (ptr, 0, 4);
27771 }
27772
27773 return 0;
bfae80f2
RE		 27774}
27775
f0927246
NC		 27776
27777/* Initialize the DWARF-2 unwind information for this procedure. */
27778
27779void
27780tc_arm_frame_initial_instructions (void)
27781{
27782 cfi_add_CFA_def_cfa (REG_SP, 0);
27783}
27784#endif /* OBJ_ELF */
27785
c19d1205
ZW		 27786/* Convert REGNAME to a DWARF-2 register number. */
27787
27788int
1df69f4f 27789tc_arm_regname_to_dw2regnum (char *regname)
bfae80f2 27790{
1df69f4f 27791 int reg = arm_reg_parse (&regname, REG_TYPE_RN);
1f5afe1c
NC		 27792 if (reg != FAIL)
27793 return reg;
c19d1205 27794
1f5afe1c
NC		 27795 /* PR 16694: Allow VFP registers as well. */
27796 reg = arm_reg_parse (&regname, REG_TYPE_VFS);
27797 if (reg != FAIL)
27798 return 64 + reg;
c19d1205 27799
1f5afe1c
NC		 27800 reg = arm_reg_parse (&regname, REG_TYPE_VFD);
27801 if (reg != FAIL)
27802 return reg + 256;
27803
0198d5e6 27804 return FAIL;
bfae80f2
RE		 27805}
27806
f0927246 27807#ifdef TE_PE
c19d1205 27808void
f0927246 27809tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
bfae80f2 27810{
91d6fa6a 27811 expressionS exp;
bfae80f2 27812
91d6fa6a
NC		 27813 exp.X_op = O_secrel;
27814 exp.X_add_symbol = symbol;
27815 exp.X_add_number = 0;
27816 emit_expr (&exp, size);
f0927246
NC		 27817}
27818#endif
bfae80f2 27819
c19d1205 27820/* MD interface: Symbol and relocation handling. */
bfae80f2 27821
2fc8bdac
ZW		 27822/* Return the address within the segment that a PC-relative fixup is
27823 relative to. For ARM, PC-relative fixups applied to instructions
27824 are generally relative to the location of the fixup plus 8 bytes.
27825 Thumb branches are offset by 4, and Thumb loads relative to PC
27826 require special handling. */
bfae80f2 27827
c19d1205 27828long
2fc8bdac 27829md_pcrel_from_section (fixS * fixP, segT seg)
bfae80f2 27830{
2fc8bdac
ZW		 27831 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
27832
27833 /* If this is pc-relative and we are going to emit a relocation
27834 then we just want to put out any pipeline compensation that the linker
53baae48
NC		 27835 will need. Otherwise we want to use the calculated base.
27836 For WinCE we skip the bias for externals as well, since this
27837 is how the MS ARM-CE assembler behaves and we want to be compatible. */
5f4273c7 27838 if (fixP->fx_pcrel
2fc8bdac 27839 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
53baae48
NC		 27840 || (arm_force_relocation (fixP)
27841#ifdef TE_WINCE
27842 && !S_IS_EXTERNAL (fixP->fx_addsy)
27843#endif
27844 )))
2fc8bdac 27845 base = 0;
bfae80f2 27846
267bf995 27847
c19d1205 27848 switch (fixP->fx_r_type)
bfae80f2 27849 {
2fc8bdac
ZW		 27850 /* PC relative addressing on the Thumb is slightly odd as the
27851 bottom two bits of the PC are forced to zero for the
27852 calculation. This happens *after* application of the
27853 pipeline offset. However, Thumb adrl already adjusts for
27854 this, so we need not do it again. */
c19d1205 27855 case BFD_RELOC_ARM_THUMB_ADD:
2fc8bdac 27856 return base & ~3;
c19d1205
ZW		 27857
27858 case BFD_RELOC_ARM_THUMB_OFFSET:
27859 case BFD_RELOC_ARM_T32_OFFSET_IMM:
e9f89963 27860 case BFD_RELOC_ARM_T32_ADD_PC12:
8f06b2d8 27861 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
2fc8bdac 27862 return (base + 4) & ~3;
c19d1205 27863
2fc8bdac 27864 /* Thumb branches are simply offset by +4. */
e12437dc 27865 case BFD_RELOC_THUMB_PCREL_BRANCH5:
2fc8bdac
ZW		 27866 case BFD_RELOC_THUMB_PCREL_BRANCH7:
27867 case BFD_RELOC_THUMB_PCREL_BRANCH9:
27868 case BFD_RELOC_THUMB_PCREL_BRANCH12:
27869 case BFD_RELOC_THUMB_PCREL_BRANCH20:
2fc8bdac 27870 case BFD_RELOC_THUMB_PCREL_BRANCH25:
f6b2b12d 27871 case BFD_RELOC_THUMB_PCREL_BFCSEL:
e5d6e09e 27872 case BFD_RELOC_ARM_THUMB_BF17:
1caf72a5 27873 case BFD_RELOC_ARM_THUMB_BF19:
1889da70 27874 case BFD_RELOC_ARM_THUMB_BF13:
60f993ce 27875 case BFD_RELOC_ARM_THUMB_LOOP12:
2fc8bdac 27876 return base + 4;
bfae80f2 27877
267bf995 27878 case BFD_RELOC_THUMB_PCREL_BRANCH23:
486499d0
CL		 27879 if (fixP->fx_addsy
27880 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 27881 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995 27882 && ARM_IS_FUNC (fixP->fx_addsy)
477330fc
RM		 27883 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
27884 base = fixP->fx_where + fixP->fx_frag->fr_address;
267bf995
RR		 27885 return base + 4;
27886
00adf2d4
JB		 27887 /* BLX is like branches above, but forces the low two bits of PC to
27888 zero. */
486499d0
CL		 27889 case BFD_RELOC_THUMB_PCREL_BLX:
27890 if (fixP->fx_addsy
27891 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 27892 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
477330fc
RM		 27893 && THUMB_IS_FUNC (fixP->fx_addsy)
27894 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
27895 base = fixP->fx_where + fixP->fx_frag->fr_address;
00adf2d4
JB		 27896 return (base + 4) & ~3;
27897
2fc8bdac
ZW		 27898 /* ARM mode branches are offset by +8. However, the Windows CE
27899 loader expects the relocation not to take this into account. */
267bf995 27900 case BFD_RELOC_ARM_PCREL_BLX:
486499d0
CL		 27901 if (fixP->fx_addsy
27902 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 27903 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
477330fc
RM		 27904 && ARM_IS_FUNC (fixP->fx_addsy)
27905 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
27906 base = fixP->fx_where + fixP->fx_frag->fr_address;
486499d0 27907 return base + 8;
267bf995 27908
486499d0
CL		 27909 case BFD_RELOC_ARM_PCREL_CALL:
27910 if (fixP->fx_addsy
27911 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 27912 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
477330fc
RM		 27913 && THUMB_IS_FUNC (fixP->fx_addsy)
27914 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
27915 base = fixP->fx_where + fixP->fx_frag->fr_address;
486499d0 27916 return base + 8;
267bf995 27917
2fc8bdac 27918 case BFD_RELOC_ARM_PCREL_BRANCH:
39b41c9c 27919 case BFD_RELOC_ARM_PCREL_JUMP:
2fc8bdac 27920 case BFD_RELOC_ARM_PLT32:
c19d1205 27921#ifdef TE_WINCE
5f4273c7 27922 /* When handling fixups immediately, because we have already
477330fc 27923 discovered the value of a symbol, or the address of the frag involved
53baae48 27924 we must account for the offset by +8, as the OS loader will never see the reloc.
477330fc
RM		 27925 see fixup_segment() in write.c
27926 The S_IS_EXTERNAL test handles the case of global symbols.
27927 Those need the calculated base, not just the pipe compensation the linker will need. */
53baae48
NC		 27928 if (fixP->fx_pcrel
27929 && fixP->fx_addsy != NULL
27930 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27931 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
27932 return base + 8;
2fc8bdac 27933 return base;
c19d1205 27934#else
2fc8bdac 27935 return base + 8;
c19d1205 27936#endif
2fc8bdac 27937
267bf995 27938
2fc8bdac
ZW		 27939 /* ARM mode loads relative to PC are also offset by +8. Unlike
27940 branches, the Windows CE loader *does* expect the relocation
27941 to take this into account. */
27942 case BFD_RELOC_ARM_OFFSET_IMM:
27943 case BFD_RELOC_ARM_OFFSET_IMM8:
27944 case BFD_RELOC_ARM_HWLITERAL:
27945 case BFD_RELOC_ARM_LITERAL:
27946 case BFD_RELOC_ARM_CP_OFF_IMM:
27947 return base + 8;
27948
27949
27950 /* Other PC-relative relocations are un-offset. */
27951 default:
27952 return base;
27953 }
bfae80f2
RE		 27954}
27955
8b2d793c
NC		 27956static bfd_boolean flag_warn_syms = TRUE;
27957
ae8714c2
NC		 27958bfd_boolean
27959arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char * name)
bfae80f2 27960{
8b2d793c
NC		 27961 /* PR 18347 - Warn if the user attempts to create a symbol with the same
27962 name as an ARM instruction. Whilst strictly speaking it is allowed, it
27963 does mean that the resulting code might be very confusing to the reader.
27964 Also this warning can be triggered if the user omits an operand before
27965 an immediate address, eg:
27966
27967 LDR =foo
27968
27969 GAS treats this as an assignment of the value of the symbol foo to a
27970 symbol LDR, and so (without this code) it will not issue any kind of
27971 warning or error message.
27972
27973 Note - ARM instructions are case-insensitive but the strings in the hash
27974 table are all stored in lower case, so we must first ensure that name is
ae8714c2
NC		 27975 lower case too. */
27976 if (flag_warn_syms && arm_ops_hsh)
8b2d793c
NC		 27977 {
27978 char * nbuf = strdup (name);
27979 char * p;
27980
27981 for (p = nbuf; *p; p++)
27982 *p = TOLOWER (*p);
27983 if (hash_find (arm_ops_hsh, nbuf) != NULL)
27984 {
27985 static struct hash_control * already_warned = NULL;
27986
27987 if (already_warned == NULL)
27988 already_warned = hash_new ();
27989 /* Only warn about the symbol once. To keep the code
27990 simple we let hash_insert do the lookup for us. */
3076e594 27991 if (hash_insert (already_warned, nbuf, NULL) == NULL)
ae8714c2 27992 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name);
8b2d793c
NC		 27993 }
27994 else
27995 free (nbuf);
27996 }
3739860c 27997
ae8714c2
NC		 27998 return FALSE;
27999}
28000
28001/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
28002 Otherwise we have no need to default values of symbols. */
28003
28004symbolS *
28005md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
28006{
28007#ifdef OBJ_ELF
28008 if (name[0] == '_' && name[1] == 'G'
28009 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
28010 {
28011 if (!GOT_symbol)
28012 {
28013 if (symbol_find (name))
28014 as_bad (_("GOT already in the symbol table"));
28015
28016 GOT_symbol = symbol_new (name, undefined_section,
28017 (valueT) 0, & zero_address_frag);
28018 }
28019
28020 return GOT_symbol;
28021 }
28022#endif
28023
c921be7d 28024 return NULL;
bfae80f2
RE		 28025}
28026
55cf6793 28027/* Subroutine of md_apply_fix. Check to see if an immediate can be
c19d1205
ZW		 28028 computed as two separate immediate values, added together. We
28029 already know that this value cannot be computed by just one ARM
28030 instruction. */
28031
28032static unsigned int
28033validate_immediate_twopart (unsigned int val,
28034 unsigned int * highpart)
bfae80f2 28035{
c19d1205
ZW		 28036 unsigned int a;
28037 unsigned int i;
bfae80f2 28038
c19d1205
ZW		 28039 for (i = 0; i < 32; i += 2)
28040 if (((a = rotate_left (val, i)) & 0xff) != 0)
28041 {
28042 if (a & 0xff00)
28043 {
28044 if (a & ~ 0xffff)
28045 continue;
28046 * highpart = (a >> 8) | ((i + 24) << 7);
28047 }
28048 else if (a & 0xff0000)
28049 {
28050 if (a & 0xff000000)
28051 continue;
28052 * highpart = (a >> 16) | ((i + 16) << 7);
28053 }
28054 else
28055 {
9c2799c2 28056 gas_assert (a & 0xff000000);
c19d1205
ZW		 28057 * highpart = (a >> 24) | ((i + 8) << 7);
28058 }
bfae80f2 28059
c19d1205
ZW		 28060 return (a & 0xff) | (i << 7);
28061 }
bfae80f2 28062
c19d1205 28063 return FAIL;
bfae80f2
RE		 28064}
28065
c19d1205
ZW		 28066static int
28067validate_offset_imm (unsigned int val, int hwse)
28068{
28069 if ((hwse && val > 255) || val > 4095)
28070 return FAIL;
28071 return val;
28072}
bfae80f2 28073
55cf6793 28074/* Subroutine of md_apply_fix. Do those data_ops which can take a
c19d1205
ZW		 28075 negative immediate constant by altering the instruction. A bit of
28076 a hack really.
28077 MOV <-> MVN
28078 AND <-> BIC
28079 ADC <-> SBC
28080 by inverting the second operand, and
28081 ADD <-> SUB
28082 CMP <-> CMN
28083 by negating the second operand. */
bfae80f2 28084
c19d1205
ZW		 28085static int
28086negate_data_op (unsigned long * instruction,
28087 unsigned long value)
bfae80f2 28088{
c19d1205
ZW		 28089 int op, new_inst;
28090 unsigned long negated, inverted;
bfae80f2 28091
c19d1205
ZW		 28092 negated = encode_arm_immediate (-value);
28093 inverted = encode_arm_immediate (~value);
bfae80f2 28094
c19d1205
ZW		 28095 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
28096 switch (op)
bfae80f2 28097 {
c19d1205
ZW		 28098 /* First negates. */
28099 case OPCODE_SUB: /* ADD <-> SUB */
28100 new_inst = OPCODE_ADD;
28101 value = negated;
28102 break;
bfae80f2 28103
c19d1205
ZW		 28104 case OPCODE_ADD:
28105 new_inst = OPCODE_SUB;
28106 value = negated;
28107 break;
bfae80f2 28108
c19d1205
ZW		 28109 case OPCODE_CMP: /* CMP <-> CMN */
28110 new_inst = OPCODE_CMN;
28111 value = negated;
28112 break;
bfae80f2 28113
c19d1205
ZW		 28114 case OPCODE_CMN:
28115 new_inst = OPCODE_CMP;
28116 value = negated;
28117 break;
bfae80f2 28118
c19d1205
ZW		 28119 /* Now Inverted ops. */
28120 case OPCODE_MOV: /* MOV <-> MVN */
28121 new_inst = OPCODE_MVN;
28122 value = inverted;
28123 break;
bfae80f2 28124
c19d1205
ZW		 28125 case OPCODE_MVN:
28126 new_inst = OPCODE_MOV;
28127 value = inverted;
28128 break;
bfae80f2 28129
c19d1205
ZW		 28130 case OPCODE_AND: /* AND <-> BIC */
28131 new_inst = OPCODE_BIC;
28132 value = inverted;
28133 break;
bfae80f2 28134
c19d1205
ZW		 28135 case OPCODE_BIC:
28136 new_inst = OPCODE_AND;
28137 value = inverted;
28138 break;
bfae80f2 28139
c19d1205
ZW		 28140 case OPCODE_ADC: /* ADC <-> SBC */
28141 new_inst = OPCODE_SBC;
28142 value = inverted;
28143 break;
bfae80f2 28144
c19d1205
ZW		 28145 case OPCODE_SBC:
28146 new_inst = OPCODE_ADC;
28147 value = inverted;
28148 break;
bfae80f2 28149
c19d1205
ZW		 28150 /* We cannot do anything. */
28151 default:
28152 return FAIL;
b99bd4ef
NC		 28153 }
28154
c19d1205
ZW		 28155 if (value == (unsigned) FAIL)
28156 return FAIL;
28157
28158 *instruction &= OPCODE_MASK;
28159 *instruction |= new_inst << DATA_OP_SHIFT;
28160 return value;
b99bd4ef
NC		 28161}
28162
ef8d22e6
PB		 28163/* Like negate_data_op, but for Thumb-2. */
28164
28165static unsigned int
16dd5e42 28166thumb32_negate_data_op (offsetT *instruction, unsigned int value)
ef8d22e6
PB		 28167{
28168 int op, new_inst;
28169 int rd;
16dd5e42 28170 unsigned int negated, inverted;
ef8d22e6
PB		 28171
28172 negated = encode_thumb32_immediate (-value);
28173 inverted = encode_thumb32_immediate (~value);
28174
28175 rd = (*instruction >> 8) & 0xf;
28176 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
28177 switch (op)
28178 {
28179 /* ADD <-> SUB. Includes CMP <-> CMN. */
28180 case T2_OPCODE_SUB:
28181 new_inst = T2_OPCODE_ADD;
28182 value = negated;
28183 break;
28184
28185 case T2_OPCODE_ADD:
28186 new_inst = T2_OPCODE_SUB;
28187 value = negated;
28188 break;
28189
28190 /* ORR <-> ORN. Includes MOV <-> MVN. */
28191 case T2_OPCODE_ORR:
28192 new_inst = T2_OPCODE_ORN;
28193 value = inverted;
28194 break;
28195
28196 case T2_OPCODE_ORN:
28197 new_inst = T2_OPCODE_ORR;
28198 value = inverted;
28199 break;
28200
28201 /* AND <-> BIC. TST has no inverted equivalent. */
28202 case T2_OPCODE_AND:
28203 new_inst = T2_OPCODE_BIC;
28204 if (rd == 15)
28205 value = FAIL;
28206 else
28207 value = inverted;
28208 break;
28209
28210 case T2_OPCODE_BIC:
28211 new_inst = T2_OPCODE_AND;
28212 value = inverted;
28213 break;
28214
28215 /* ADC <-> SBC */
28216 case T2_OPCODE_ADC:
28217 new_inst = T2_OPCODE_SBC;
28218 value = inverted;
28219 break;
28220
28221 case T2_OPCODE_SBC:
28222 new_inst = T2_OPCODE_ADC;
28223 value = inverted;
28224 break;
28225
28226 /* We cannot do anything. */
28227 default:
28228 return FAIL;
28229 }
28230
16dd5e42 28231 if (value == (unsigned int)FAIL)
ef8d22e6
PB		 28232 return FAIL;
28233
28234 *instruction &= T2_OPCODE_MASK;
28235 *instruction |= new_inst << T2_DATA_OP_SHIFT;
28236 return value;
28237}
28238
8f06b2d8 28239/* Read a 32-bit thumb instruction from buf. */
0198d5e6 28240
8f06b2d8
PB		 28241static unsigned long
28242get_thumb32_insn (char * buf)
28243{
28244 unsigned long insn;
28245 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
28246 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
28247
28248 return insn;
28249}
28250
a8bc6c78
PB		 28251/* We usually want to set the low bit on the address of thumb function
28252 symbols. In particular .word foo - . should have the low bit set.
28253 Generic code tries to fold the difference of two symbols to
28254 a constant. Prevent this and force a relocation when the first symbols
28255 is a thumb function. */
c921be7d
NC		 28256
28257bfd_boolean
a8bc6c78
PB		 28258arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
28259{
28260 if (op == O_subtract
28261 && l->X_op == O_symbol
28262 && r->X_op == O_symbol
28263 && THUMB_IS_FUNC (l->X_add_symbol))
28264 {
28265 l->X_op = O_subtract;
28266 l->X_op_symbol = r->X_add_symbol;
28267 l->X_add_number -= r->X_add_number;
c921be7d 28268 return TRUE;
a8bc6c78 28269 }
c921be7d 28270
a8bc6c78 28271 /* Process as normal. */
c921be7d 28272 return FALSE;
a8bc6c78
PB		 28273}
28274
4a42ebbc
RR		 28275/* Encode Thumb2 unconditional branches and calls. The encoding
28276 for the 2 are identical for the immediate values. */
28277
28278static void
28279encode_thumb2_b_bl_offset (char * buf, offsetT value)
28280{
28281#define T2I1I2MASK ((1 << 13) | (1 << 11))
28282 offsetT newval;
28283 offsetT newval2;
28284 addressT S, I1, I2, lo, hi;
28285
28286 S = (value >> 24) & 0x01;
28287 I1 = (value >> 23) & 0x01;
28288 I2 = (value >> 22) & 0x01;
28289 hi = (value >> 12) & 0x3ff;
fa94de6b 28290 lo = (value >> 1) & 0x7ff;
4a42ebbc
RR		 28291 newval = md_chars_to_number (buf, THUMB_SIZE);
28292 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
28293 newval |= (S << 10) | hi;
28294 newval2 &= ~T2I1I2MASK;
28295 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
28296 md_number_to_chars (buf, newval, THUMB_SIZE);
28297 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
28298}
28299
c19d1205 28300void
55cf6793 28301md_apply_fix (fixS * fixP,
c19d1205
ZW		 28302 valueT * valP,
28303 segT seg)
28304{
28305 offsetT value = * valP;
28306 offsetT newval;
28307 unsigned int newimm;
28308 unsigned long temp;
28309 int sign;
28310 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
b99bd4ef 28311
9c2799c2 28312 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
b99bd4ef 28313
c19d1205 28314 /* Note whether this will delete the relocation. */
4962c51a 28315
c19d1205
ZW		 28316 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
28317 fixP->fx_done = 1;
b99bd4ef 28318
adbaf948 28319 /* On a 64-bit host, silently truncate 'value' to 32 bits for
5f4273c7 28320 consistency with the behaviour on 32-bit hosts. Remember value
adbaf948
ZW		 28321 for emit_reloc. */
28322 value &= 0xffffffff;
28323 value ^= 0x80000000;
5f4273c7 28324 value -= 0x80000000;
adbaf948
ZW		 28325
28326 *valP = value;
c19d1205 28327 fixP->fx_addnumber = value;
b99bd4ef 28328
adbaf948
ZW		 28329 /* Same treatment for fixP->fx_offset. */
28330 fixP->fx_offset &= 0xffffffff;
28331 fixP->fx_offset ^= 0x80000000;
28332 fixP->fx_offset -= 0x80000000;
28333
c19d1205 28334 switch (fixP->fx_r_type)
b99bd4ef 28335 {
c19d1205
ZW		 28336 case BFD_RELOC_NONE:
28337 /* This will need to go in the object file. */
28338 fixP->fx_done = 0;
28339 break;
b99bd4ef 28340
c19d1205
ZW		 28341 case BFD_RELOC_ARM_IMMEDIATE:
28342 /* We claim that this fixup has been processed here,
28343 even if in fact we generate an error because we do
28344 not have a reloc for it, so tc_gen_reloc will reject it. */
28345 fixP->fx_done = 1;
b99bd4ef 28346
77db8e2e 28347 if (fixP->fx_addsy)
b99bd4ef 28348 {
77db8e2e 28349 const char *msg = 0;
b99bd4ef 28350
77db8e2e
NC		 28351 if (! S_IS_DEFINED (fixP->fx_addsy))
28352 msg = _("undefined symbol %s used as an immediate value");
28353 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
28354 msg = _("symbol %s is in a different section");
28355 else if (S_IS_WEAK (fixP->fx_addsy))
28356 msg = _("symbol %s is weak and may be overridden later");
28357
28358 if (msg)
28359 {
28360 as_bad_where (fixP->fx_file, fixP->fx_line,
28361 msg, S_GET_NAME (fixP->fx_addsy));
28362 break;
28363 }
42e5fcbf
AS		 28364 }
28365
c19d1205
ZW		 28366 temp = md_chars_to_number (buf, INSN_SIZE);
28367
5e73442d
SL		 28368 /* If the offset is negative, we should use encoding A2 for ADR. */
28369 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
28370 newimm = negate_data_op (&temp, value);
28371 else
28372 {
28373 newimm = encode_arm_immediate (value);
28374
28375 /* If the instruction will fail, see if we can fix things up by
28376 changing the opcode. */
28377 if (newimm == (unsigned int) FAIL)
28378 newimm = negate_data_op (&temp, value);
bada4342
JW		 28379 /* MOV accepts both ARM modified immediate (A1 encoding) and
28380 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
28381 When disassembling, MOV is preferred when there is no encoding
28382 overlap. */
28383 if (newimm == (unsigned int) FAIL
28384 && ((temp >> DATA_OP_SHIFT) & 0xf) == OPCODE_MOV
28385 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
28386 && !((temp >> SBIT_SHIFT) & 0x1)
28387 && value >= 0 && value <= 0xffff)
28388 {
28389 /* Clear bits[23:20] to change encoding from A1 to A2. */
28390 temp &= 0xff0fffff;
28391 /* Encoding high 4bits imm. Code below will encode the remaining
28392 low 12bits. */
28393 temp |= (value & 0x0000f000) << 4;
28394 newimm = value & 0x00000fff;
28395 }
5e73442d
SL		 28396 }
28397
28398 if (newimm == (unsigned int) FAIL)
b99bd4ef 28399 {
c19d1205
ZW		 28400 as_bad_where (fixP->fx_file, fixP->fx_line,
28401 _("invalid constant (%lx) after fixup"),
28402 (unsigned long) value);
28403 break;
b99bd4ef 28404 }
b99bd4ef 28405
c19d1205
ZW		 28406 newimm |= (temp & 0xfffff000);
28407 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
28408 break;
b99bd4ef 28409
c19d1205
ZW		 28410 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
28411 {
28412 unsigned int highpart = 0;
28413 unsigned int newinsn = 0xe1a00000; /* nop. */
b99bd4ef 28414
77db8e2e 28415 if (fixP->fx_addsy)
42e5fcbf 28416 {
77db8e2e 28417 const char *msg = 0;
42e5fcbf 28418
77db8e2e
NC		 28419 if (! S_IS_DEFINED (fixP->fx_addsy))
28420 msg = _("undefined symbol %s used as an immediate value");
28421 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
28422 msg = _("symbol %s is in a different section");
28423 else if (S_IS_WEAK (fixP->fx_addsy))
28424 msg = _("symbol %s is weak and may be overridden later");
42e5fcbf 28425
77db8e2e
NC		 28426 if (msg)
28427 {
28428 as_bad_where (fixP->fx_file, fixP->fx_line,
28429 msg, S_GET_NAME (fixP->fx_addsy));
28430 break;
28431 }
28432 }
fa94de6b 28433
c19d1205
ZW		 28434 newimm = encode_arm_immediate (value);
28435 temp = md_chars_to_number (buf, INSN_SIZE);
b99bd4ef 28436
c19d1205
ZW		 28437 /* If the instruction will fail, see if we can fix things up by
28438 changing the opcode. */
28439 if (newimm == (unsigned int) FAIL
28440 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
28441 {
28442 /* No ? OK - try using two ADD instructions to generate
28443 the value. */
28444 newimm = validate_immediate_twopart (value, & highpart);
b99bd4ef 28445
c19d1205
ZW		 28446 /* Yes - then make sure that the second instruction is
28447 also an add. */
28448 if (newimm != (unsigned int) FAIL)
28449 newinsn = temp;
28450 /* Still No ? Try using a negated value. */
28451 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
28452 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
28453 /* Otherwise - give up. */
28454 else
28455 {
28456 as_bad_where (fixP->fx_file, fixP->fx_line,
28457 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
28458 (long) value);
28459 break;
28460 }
b99bd4ef 28461
c19d1205
ZW		 28462 /* Replace the first operand in the 2nd instruction (which
28463 is the PC) with the destination register. We have
28464 already added in the PC in the first instruction and we
28465 do not want to do it again. */
28466 newinsn &= ~ 0xf0000;
28467 newinsn |= ((newinsn & 0x0f000) << 4);
28468 }
b99bd4ef 28469
c19d1205
ZW		 28470 newimm |= (temp & 0xfffff000);
28471 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
b99bd4ef 28472
c19d1205
ZW		 28473 highpart |= (newinsn & 0xfffff000);
28474 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
28475 }
28476 break;
b99bd4ef 28477
c19d1205 28478 case BFD_RELOC_ARM_OFFSET_IMM:
00a97672
RS		 28479 if (!fixP->fx_done && seg->use_rela_p)
28480 value = 0;
1a0670f3 28481 /* Fall through. */
00a97672 28482
c19d1205 28483 case BFD_RELOC_ARM_LITERAL:
26d97720 28484 sign = value > 0;
b99bd4ef 28485
c19d1205
ZW		 28486 if (value < 0)
28487 value = - value;
b99bd4ef 28488
c19d1205 28489 if (validate_offset_imm (value, 0) == FAIL)
f03698e6 28490 {
c19d1205
ZW		 28491 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
28492 as_bad_where (fixP->fx_file, fixP->fx_line,
28493 _("invalid literal constant: pool needs to be closer"));
28494 else
28495 as_bad_where (fixP->fx_file, fixP->fx_line,
28496 _("bad immediate value for offset (%ld)"),
28497 (long) value);
28498 break;
f03698e6
RE		 28499 }
28500
c19d1205 28501 newval = md_chars_to_number (buf, INSN_SIZE);
26d97720
NS		 28502 if (value == 0)
28503 newval &= 0xfffff000;
28504 else
28505 {
28506 newval &= 0xff7ff000;
28507 newval |= value | (sign ? INDEX_UP : 0);
28508 }
c19d1205
ZW		 28509 md_number_to_chars (buf, newval, INSN_SIZE);
28510 break;
b99bd4ef 28511
c19d1205
ZW		 28512 case BFD_RELOC_ARM_OFFSET_IMM8:
28513 case BFD_RELOC_ARM_HWLITERAL:
26d97720 28514 sign = value > 0;
b99bd4ef 28515
c19d1205
ZW		 28516 if (value < 0)
28517 value = - value;
b99bd4ef 28518
c19d1205 28519 if (validate_offset_imm (value, 1) == FAIL)
b99bd4ef 28520 {
c19d1205
ZW		 28521 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
28522 as_bad_where (fixP->fx_file, fixP->fx_line,
28523 _("invalid literal constant: pool needs to be closer"));
28524 else
427d0db6
RM		 28525 as_bad_where (fixP->fx_file, fixP->fx_line,
28526 _("bad immediate value for 8-bit offset (%ld)"),
28527 (long) value);
c19d1205 28528 break;
b99bd4ef
NC		 28529 }
28530
c19d1205 28531 newval = md_chars_to_number (buf, INSN_SIZE);
26d97720
NS		 28532 if (value == 0)
28533 newval &= 0xfffff0f0;
28534 else
28535 {
28536 newval &= 0xff7ff0f0;
28537 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
28538 }
c19d1205
ZW		 28539 md_number_to_chars (buf, newval, INSN_SIZE);
28540 break;
b99bd4ef 28541
c19d1205
ZW		 28542 case BFD_RELOC_ARM_T32_OFFSET_U8:
28543 if (value < 0 || value > 1020 || value % 4 != 0)
28544 as_bad_where (fixP->fx_file, fixP->fx_line,
28545 _("bad immediate value for offset (%ld)"), (long) value);
28546 value /= 4;
b99bd4ef 28547
c19d1205 28548 newval = md_chars_to_number (buf+2, THUMB_SIZE);
c19d1205
ZW		 28549 newval |= value;
28550 md_number_to_chars (buf+2, newval, THUMB_SIZE);
28551 break;
b99bd4ef 28552
c19d1205
ZW		 28553 case BFD_RELOC_ARM_T32_OFFSET_IMM:
28554 /* This is a complicated relocation used for all varieties of Thumb32
28555 load/store instruction with immediate offset:
28556
28557 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
477330fc 28558 *4, optional writeback(W)
c19d1205
ZW		 28559 (doubleword load/store)
28560
28561 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
28562 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
28563 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
28564 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
28565 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
28566
28567 Uppercase letters indicate bits that are already encoded at
28568 this point. Lowercase letters are our problem. For the
28569 second block of instructions, the secondary opcode nybble
28570 (bits 8..11) is present, and bit 23 is zero, even if this is
28571 a PC-relative operation. */
28572 newval = md_chars_to_number (buf, THUMB_SIZE);
28573 newval <<= 16;
28574 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
b99bd4ef 28575
c19d1205 28576 if ((newval & 0xf0000000) == 0xe0000000)
b99bd4ef 28577 {
c19d1205
ZW		 28578 /* Doubleword load/store: 8-bit offset, scaled by 4. */
28579 if (value >= 0)
28580 newval |= (1 << 23);
28581 else
28582 value = -value;
28583 if (value % 4 != 0)
28584 {
28585 as_bad_where (fixP->fx_file, fixP->fx_line,
28586 _("offset not a multiple of 4"));
28587 break;
28588 }
28589 value /= 4;
216d22bc 28590 if (value > 0xff)
c19d1205
ZW		 28591 {
28592 as_bad_where (fixP->fx_file, fixP->fx_line,
28593 _("offset out of range"));
28594 break;
28595 }
28596 newval &= ~0xff;
b99bd4ef 28597 }
c19d1205 28598 else if ((newval & 0x000f0000) == 0x000f0000)
b99bd4ef 28599 {
c19d1205
ZW		 28600 /* PC-relative, 12-bit offset. */
28601 if (value >= 0)
28602 newval |= (1 << 23);
28603 else
28604 value = -value;
216d22bc 28605 if (value > 0xfff)
c19d1205
ZW		 28606 {
28607 as_bad_where (fixP->fx_file, fixP->fx_line,
28608 _("offset out of range"));
28609 break;
28610 }
28611 newval &= ~0xfff;
b99bd4ef 28612 }
c19d1205 28613 else if ((newval & 0x00000100) == 0x00000100)
b99bd4ef 28614 {
c19d1205
ZW		 28615 /* Writeback: 8-bit, +/- offset. */
28616 if (value >= 0)
28617 newval |= (1 << 9);
28618 else
28619 value = -value;
216d22bc 28620 if (value > 0xff)
c19d1205
ZW		 28621 {
28622 as_bad_where (fixP->fx_file, fixP->fx_line,
28623 _("offset out of range"));
28624 break;
28625 }
28626 newval &= ~0xff;
b99bd4ef 28627 }
c19d1205 28628 else if ((newval & 0x00000f00) == 0x00000e00)
b99bd4ef 28629 {
c19d1205 28630 /* T-instruction: positive 8-bit offset. */
216d22bc 28631 if (value < 0 || value > 0xff)
b99bd4ef 28632 {
c19d1205
ZW		 28633 as_bad_where (fixP->fx_file, fixP->fx_line,
28634 _("offset out of range"));
28635 break;
b99bd4ef 28636 }
c19d1205
ZW		 28637 newval &= ~0xff;
28638 newval |= value;
b99bd4ef
NC		 28639 }
28640 else
b99bd4ef 28641 {
c19d1205
ZW		 28642 /* Positive 12-bit or negative 8-bit offset. */
28643 int limit;
28644 if (value >= 0)
b99bd4ef 28645 {
c19d1205
ZW		 28646 newval |= (1 << 23);
28647 limit = 0xfff;
28648 }
28649 else
28650 {
28651 value = -value;
28652 limit = 0xff;
28653 }
28654 if (value > limit)
28655 {
28656 as_bad_where (fixP->fx_file, fixP->fx_line,
28657 _("offset out of range"));
28658 break;
b99bd4ef 28659 }
c19d1205 28660 newval &= ~limit;
b99bd4ef 28661 }
b99bd4ef 28662
c19d1205
ZW		 28663 newval |= value;
28664 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
28665 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
28666 break;
404ff6b5 28667
c19d1205
ZW		 28668 case BFD_RELOC_ARM_SHIFT_IMM:
28669 newval = md_chars_to_number (buf, INSN_SIZE);
28670 if (((unsigned long) value) > 32
28671 || (value == 32
28672 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
28673 {
28674 as_bad_where (fixP->fx_file, fixP->fx_line,
28675 _("shift expression is too large"));
28676 break;
28677 }
404ff6b5 28678
c19d1205
ZW		 28679 if (value == 0)
28680 /* Shifts of zero must be done as lsl. */
28681 newval &= ~0x60;
28682 else if (value == 32)
28683 value = 0;
28684 newval &= 0xfffff07f;
28685 newval |= (value & 0x1f) << 7;
28686 md_number_to_chars (buf, newval, INSN_SIZE);
28687 break;
404ff6b5 28688
c19d1205 28689 case BFD_RELOC_ARM_T32_IMMEDIATE:
16805f35 28690 case BFD_RELOC_ARM_T32_ADD_IMM:
92e90b6e 28691 case BFD_RELOC_ARM_T32_IMM12:
e9f89963 28692 case BFD_RELOC_ARM_T32_ADD_PC12:
c19d1205
ZW		 28693 /* We claim that this fixup has been processed here,
28694 even if in fact we generate an error because we do
28695 not have a reloc for it, so tc_gen_reloc will reject it. */
28696 fixP->fx_done = 1;
404ff6b5 28697
c19d1205
ZW		 28698 if (fixP->fx_addsy
28699 && ! S_IS_DEFINED (fixP->fx_addsy))
28700 {
28701 as_bad_where (fixP->fx_file, fixP->fx_line,
28702 _("undefined symbol %s used as an immediate value"),
28703 S_GET_NAME (fixP->fx_addsy));
28704 break;
28705 }
404ff6b5 28706
c19d1205
ZW		 28707 newval = md_chars_to_number (buf, THUMB_SIZE);
28708 newval <<= 16;
28709 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
404ff6b5 28710
16805f35 28711 newimm = FAIL;
bada4342
JW		 28712 if ((fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
28713 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
28714 Thumb2 modified immediate encoding (T2). */
28715 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
16805f35 28716 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
ef8d22e6
PB		 28717 {
28718 newimm = encode_thumb32_immediate (value);
28719 if (newimm == (unsigned int) FAIL)
28720 newimm = thumb32_negate_data_op (&newval, value);
28721 }
bada4342 28722 if (newimm == (unsigned int) FAIL)
92e90b6e 28723 {
bada4342 28724 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE)
e9f89963 28725 {
bada4342
JW		 28726 /* Turn add/sum into addw/subw. */
28727 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
28728 newval = (newval & 0xfeffffff) | 0x02000000;
28729 /* No flat 12-bit imm encoding for addsw/subsw. */
28730 if ((newval & 0x00100000) == 0)
40f246e3 28731 {
bada4342
JW		 28732 /* 12 bit immediate for addw/subw. */
28733 if (value < 0)
28734 {
28735 value = -value;
28736 newval ^= 0x00a00000;
28737 }
28738 if (value > 0xfff)
28739 newimm = (unsigned int) FAIL;
28740 else
28741 newimm = value;
28742 }
28743 }
28744 else
28745 {
28746 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
28747 UINT16 (T3 encoding), MOVW only accepts UINT16. When
28748 disassembling, MOV is preferred when there is no encoding
db7bf105 28749 overlap. */
bada4342 28750 if (((newval >> T2_DATA_OP_SHIFT) & 0xf) == T2_OPCODE_ORR
db7bf105
NC		 28751 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
28752 but with the Rn field [19:16] set to 1111. */
28753 && (((newval >> 16) & 0xf) == 0xf)
bada4342
JW		 28754 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m)
28755 && !((newval >> T2_SBIT_SHIFT) & 0x1)
db7bf105 28756 && value >= 0 && value <= 0xffff)
bada4342
JW		 28757 {
28758 /* Toggle bit[25] to change encoding from T2 to T3. */
28759 newval ^= 1 << 25;
28760 /* Clear bits[19:16]. */
28761 newval &= 0xfff0ffff;
28762 /* Encoding high 4bits imm. Code below will encode the
28763 remaining low 12bits. */
28764 newval |= (value & 0x0000f000) << 4;
28765 newimm = value & 0x00000fff;
40f246e3 28766 }
e9f89963 28767 }
92e90b6e 28768 }
cc8a6dd0 28769
c19d1205 28770 if (newimm == (unsigned int)FAIL)
3631a3c8 28771 {
c19d1205
ZW		 28772 as_bad_where (fixP->fx_file, fixP->fx_line,
28773 _("invalid constant (%lx) after fixup"),
28774 (unsigned long) value);
28775 break;
3631a3c8
NC		 28776 }
28777
c19d1205
ZW		 28778 newval |= (newimm & 0x800) << 15;
28779 newval |= (newimm & 0x700) << 4;
28780 newval |= (newimm & 0x0ff);
cc8a6dd0 28781
c19d1205
ZW		 28782 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
28783 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
28784 break;
a737bd4d 28785
3eb17e6b 28786 case BFD_RELOC_ARM_SMC:
ba85f98c 28787 if (((unsigned long) value) > 0xf)
c19d1205 28788 as_bad_where (fixP->fx_file, fixP->fx_line,
3eb17e6b 28789 _("invalid smc expression"));
ba85f98c 28790
2fc8bdac 28791 newval = md_chars_to_number (buf, INSN_SIZE);
ba85f98c 28792 newval |= (value & 0xf);
c19d1205
ZW		 28793 md_number_to_chars (buf, newval, INSN_SIZE);
28794 break;
a737bd4d 28795
90ec0d68
MGD		 28796 case BFD_RELOC_ARM_HVC:
28797 if (((unsigned long) value) > 0xffff)
28798 as_bad_where (fixP->fx_file, fixP->fx_line,
28799 _("invalid hvc expression"));
28800 newval = md_chars_to_number (buf, INSN_SIZE);
28801 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
28802 md_number_to_chars (buf, newval, INSN_SIZE);
28803 break;
28804
c19d1205 28805 case BFD_RELOC_ARM_SWI:
adbaf948 28806 if (fixP->tc_fix_data != 0)
c19d1205
ZW		 28807 {
28808 if (((unsigned long) value) > 0xff)
28809 as_bad_where (fixP->fx_file, fixP->fx_line,
28810 _("invalid swi expression"));
2fc8bdac 28811 newval = md_chars_to_number (buf, THUMB_SIZE);
c19d1205
ZW		 28812 newval |= value;
28813 md_number_to_chars (buf, newval, THUMB_SIZE);
28814 }
28815 else
28816 {
28817 if (((unsigned long) value) > 0x00ffffff)
28818 as_bad_where (fixP->fx_file, fixP->fx_line,
28819 _("invalid swi expression"));
2fc8bdac 28820 newval = md_chars_to_number (buf, INSN_SIZE);
c19d1205
ZW		 28821 newval |= value;
28822 md_number_to_chars (buf, newval, INSN_SIZE);
28823 }
28824 break;
a737bd4d 28825
c19d1205
ZW		 28826 case BFD_RELOC_ARM_MULTI:
28827 if (((unsigned long) value) > 0xffff)
28828 as_bad_where (fixP->fx_file, fixP->fx_line,
28829 _("invalid expression in load/store multiple"));
28830 newval = value | md_chars_to_number (buf, INSN_SIZE);
28831 md_number_to_chars (buf, newval, INSN_SIZE);
28832 break;
a737bd4d 28833
c19d1205 28834#ifdef OBJ_ELF
39b41c9c 28835 case BFD_RELOC_ARM_PCREL_CALL:
267bf995
RR		 28836
28837 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
28838 && fixP->fx_addsy
34e77a92 28839 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 28840 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28841 && THUMB_IS_FUNC (fixP->fx_addsy))
28842 /* Flip the bl to blx. This is a simple flip
28843 bit here because we generate PCREL_CALL for
28844 unconditional bls. */
28845 {
28846 newval = md_chars_to_number (buf, INSN_SIZE);
28847 newval = newval | 0x10000000;
28848 md_number_to_chars (buf, newval, INSN_SIZE);
28849 temp = 1;
28850 fixP->fx_done = 1;
28851 }
39b41c9c
PB		 28852 else
28853 temp = 3;
28854 goto arm_branch_common;
28855
28856 case BFD_RELOC_ARM_PCREL_JUMP:
267bf995
RR		 28857 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
28858 && fixP->fx_addsy
34e77a92 28859 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 28860 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28861 && THUMB_IS_FUNC (fixP->fx_addsy))
28862 {
28863 /* This would map to a bl<cond>, b<cond>,
28864 b<always> to a Thumb function. We
28865 need to force a relocation for this particular
28866 case. */
28867 newval = md_chars_to_number (buf, INSN_SIZE);
28868 fixP->fx_done = 0;
28869 }
1a0670f3 28870 /* Fall through. */
267bf995 28871
2fc8bdac 28872 case BFD_RELOC_ARM_PLT32:
c19d1205 28873#endif
39b41c9c
PB		 28874 case BFD_RELOC_ARM_PCREL_BRANCH:
28875 temp = 3;
28876 goto arm_branch_common;
a737bd4d 28877
39b41c9c 28878 case BFD_RELOC_ARM_PCREL_BLX:
267bf995 28879
39b41c9c 28880 temp = 1;
267bf995
RR		 28881 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
28882 && fixP->fx_addsy
34e77a92 28883 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 28884 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28885 && ARM_IS_FUNC (fixP->fx_addsy))
28886 {
28887 /* Flip the blx to a bl and warn. */
28888 const char *name = S_GET_NAME (fixP->fx_addsy);
28889 newval = 0xeb000000;
28890 as_warn_where (fixP->fx_file, fixP->fx_line,
28891 _("blx to '%s' an ARM ISA state function changed to bl"),
28892 name);
28893 md_number_to_chars (buf, newval, INSN_SIZE);
28894 temp = 3;
28895 fixP->fx_done = 1;
28896 }
28897
28898#ifdef OBJ_ELF
28899 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
477330fc 28900 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
267bf995
RR		 28901#endif
28902
39b41c9c 28903 arm_branch_common:
c19d1205 28904 /* We are going to store value (shifted right by two) in the
39b41c9c
PB		 28905 instruction, in a 24 bit, signed field. Bits 26 through 32 either
28906 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
de194d85 28907 also be clear. */
39b41c9c 28908 if (value & temp)
c19d1205 28909 as_bad_where (fixP->fx_file, fixP->fx_line,
2fc8bdac
ZW		 28910 _("misaligned branch destination"));
28911 if ((value & (offsetT)0xfe000000) != (offsetT)0
28912 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
08f10d51 28913 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
a737bd4d 28914
2fc8bdac 28915 if (fixP->fx_done || !seg->use_rela_p)
c19d1205 28916 {
2fc8bdac
ZW		 28917 newval = md_chars_to_number (buf, INSN_SIZE);
28918 newval |= (value >> 2) & 0x00ffffff;
7ae2971b
PB		 28919 /* Set the H bit on BLX instructions. */
28920 if (temp == 1)
28921 {
28922 if (value & 2)
28923 newval |= 0x01000000;
28924 else
28925 newval &= ~0x01000000;
28926 }
2fc8bdac 28927 md_number_to_chars (buf, newval, INSN_SIZE);
c19d1205 28928 }
c19d1205 28929 break;
a737bd4d 28930
25fe350b
MS		 28931 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
28932 /* CBZ can only branch forward. */
a737bd4d 28933
738755b0 28934 /* Attempts to use CBZ to branch to the next instruction
477330fc
RM		 28935 (which, strictly speaking, are prohibited) will be turned into
28936 no-ops.
738755b0
MS		 28937
28938 FIXME: It may be better to remove the instruction completely and
28939 perform relaxation. */
28940 if (value == -2)
2fc8bdac
ZW		 28941 {
28942 newval = md_chars_to_number (buf, THUMB_SIZE);
738755b0 28943 newval = 0xbf00; /* NOP encoding T1 */
2fc8bdac
ZW		 28944 md_number_to_chars (buf, newval, THUMB_SIZE);
28945 }
738755b0
MS		 28946 else
28947 {
28948 if (value & ~0x7e)
08f10d51 28949 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
738755b0 28950
477330fc 28951 if (fixP->fx_done || !seg->use_rela_p)
738755b0
MS		 28952 {
28953 newval = md_chars_to_number (buf, THUMB_SIZE);
28954 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
28955 md_number_to_chars (buf, newval, THUMB_SIZE);
28956 }
28957 }
c19d1205 28958 break;
a737bd4d 28959
c19d1205 28960 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
e8f8842d 28961 if (out_of_range_p (value, 8))
08f10d51 28962 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
a737bd4d 28963
2fc8bdac
ZW		 28964 if (fixP->fx_done || !seg->use_rela_p)
28965 {
28966 newval = md_chars_to_number (buf, THUMB_SIZE);
28967 newval |= (value & 0x1ff) >> 1;
28968 md_number_to_chars (buf, newval, THUMB_SIZE);
28969 }
c19d1205 28970 break;
a737bd4d 28971
c19d1205 28972 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
e8f8842d 28973 if (out_of_range_p (value, 11))
08f10d51 28974 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
a737bd4d 28975
2fc8bdac
ZW		 28976 if (fixP->fx_done || !seg->use_rela_p)
28977 {
28978 newval = md_chars_to_number (buf, THUMB_SIZE);
28979 newval |= (value & 0xfff) >> 1;
28980 md_number_to_chars (buf, newval, THUMB_SIZE);
28981 }
c19d1205 28982 break;
a737bd4d 28983
e8f8842d 28984 /* This relocation is misnamed, it should be BRANCH21. */
c19d1205 28985 case BFD_RELOC_THUMB_PCREL_BRANCH20:
267bf995
RR		 28986 if (fixP->fx_addsy
28987 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 28988 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 28989 && ARM_IS_FUNC (fixP->fx_addsy)
28990 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
28991 {
28992 /* Force a relocation for a branch 20 bits wide. */
28993 fixP->fx_done = 0;
28994 }
e8f8842d 28995 if (out_of_range_p (value, 20))
2fc8bdac
ZW		 28996 as_bad_where (fixP->fx_file, fixP->fx_line,
28997 _("conditional branch out of range"));
404ff6b5 28998
2fc8bdac
ZW		 28999 if (fixP->fx_done || !seg->use_rela_p)
29000 {
29001 offsetT newval2;
29002 addressT S, J1, J2, lo, hi;
404ff6b5 29003
2fc8bdac
ZW		 29004 S = (value & 0x00100000) >> 20;
29005 J2 = (value & 0x00080000) >> 19;
29006 J1 = (value & 0x00040000) >> 18;
29007 hi = (value & 0x0003f000) >> 12;
29008 lo = (value & 0x00000ffe) >> 1;
6c43fab6 29009
2fc8bdac
ZW		 29010 newval = md_chars_to_number (buf, THUMB_SIZE);
29011 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
29012 newval |= (S << 10) | hi;
29013 newval2 |= (J1 << 13) | (J2 << 11) | lo;
29014 md_number_to_chars (buf, newval, THUMB_SIZE);
29015 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
29016 }
c19d1205 29017 break;
6c43fab6 29018
c19d1205 29019 case BFD_RELOC_THUMB_PCREL_BLX:
267bf995
RR		 29020 /* If there is a blx from a thumb state function to
29021 another thumb function flip this to a bl and warn
29022 about it. */
29023
29024 if (fixP->fx_addsy
34e77a92 29025 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 29026 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
29027 && THUMB_IS_FUNC (fixP->fx_addsy))
29028 {
29029 const char *name = S_GET_NAME (fixP->fx_addsy);
29030 as_warn_where (fixP->fx_file, fixP->fx_line,
29031 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
29032 name);
29033 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
29034 newval = newval | 0x1000;
29035 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
29036 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
29037 fixP->fx_done = 1;
29038 }
29039
29040
29041 goto thumb_bl_common;
29042
c19d1205 29043 case BFD_RELOC_THUMB_PCREL_BRANCH23:
267bf995
RR		 29044 /* A bl from Thumb state ISA to an internal ARM state function
29045 is converted to a blx. */
29046 if (fixP->fx_addsy
29047 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 29048 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 29049 && ARM_IS_FUNC (fixP->fx_addsy)
29050 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
29051 {
29052 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
29053 newval = newval & ~0x1000;
29054 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
29055 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
29056 fixP->fx_done = 1;
29057 }
29058
29059 thumb_bl_common:
29060
2fc8bdac
ZW		 29061 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
29062 /* For a BLX instruction, make sure that the relocation is rounded up
29063 to a word boundary. This follows the semantics of the instruction
29064 which specifies that bit 1 of the target address will come from bit
29065 1 of the base address. */
d406f3e4
JB		 29066 value = (value + 3) & ~ 3;
29067
29068#ifdef OBJ_ELF
29069 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
29070 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
29071 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
29072#endif
404ff6b5 29073
e8f8842d 29074 if (out_of_range_p (value, 22))
2b2f5df9 29075 {
fc289b0a 29076 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)))
2b2f5df9 29077 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
e8f8842d 29078 else if (out_of_range_p (value, 24))
2b2f5df9
NC		 29079 as_bad_where (fixP->fx_file, fixP->fx_line,
29080 _("Thumb2 branch out of range"));
29081 }
4a42ebbc
RR		 29082
29083 if (fixP->fx_done || !seg->use_rela_p)
29084 encode_thumb2_b_bl_offset (buf, value);
29085
c19d1205 29086 break;
404ff6b5 29087
c19d1205 29088 case BFD_RELOC_THUMB_PCREL_BRANCH25:
e8f8842d 29089 if (out_of_range_p (value, 24))
08f10d51 29090 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
6c43fab6 29091
2fc8bdac 29092 if (fixP->fx_done || !seg->use_rela_p)
4a42ebbc 29093 encode_thumb2_b_bl_offset (buf, value);
6c43fab6 29094
2fc8bdac 29095 break;
a737bd4d 29096
2fc8bdac
ZW		 29097 case BFD_RELOC_8:
29098 if (fixP->fx_done || !seg->use_rela_p)
4b1a927e 29099 *buf = value;
c19d1205 29100 break;
a737bd4d 29101
c19d1205 29102 case BFD_RELOC_16:
2fc8bdac 29103 if (fixP->fx_done || !seg->use_rela_p)
c19d1205 29104 md_number_to_chars (buf, value, 2);
c19d1205 29105 break;
a737bd4d 29106
c19d1205 29107#ifdef OBJ_ELF
0855e32b
NS		 29108 case BFD_RELOC_ARM_TLS_CALL:
29109 case BFD_RELOC_ARM_THM_TLS_CALL:
29110 case BFD_RELOC_ARM_TLS_DESCSEQ:
29111 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
0855e32b 29112 case BFD_RELOC_ARM_TLS_GOTDESC:
c19d1205
ZW		 29113 case BFD_RELOC_ARM_TLS_GD32:
29114 case BFD_RELOC_ARM_TLS_LE32:
29115 case BFD_RELOC_ARM_TLS_IE32:
29116 case BFD_RELOC_ARM_TLS_LDM32:
29117 case BFD_RELOC_ARM_TLS_LDO32:
29118 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4b1a927e 29119 break;
6c43fab6 29120
5c5a4843
CL		 29121 /* Same handling as above, but with the arm_fdpic guard. */
29122 case BFD_RELOC_ARM_TLS_GD32_FDPIC:
29123 case BFD_RELOC_ARM_TLS_IE32_FDPIC:
29124 case BFD_RELOC_ARM_TLS_LDM32_FDPIC:
29125 if (arm_fdpic)
29126 {
29127 S_SET_THREAD_LOCAL (fixP->fx_addsy);
29128 }
29129 else
29130 {
29131 as_bad_where (fixP->fx_file, fixP->fx_line,
29132 _("Relocation supported only in FDPIC mode"));
29133 }
29134 break;
29135
c19d1205
ZW		 29136 case BFD_RELOC_ARM_GOT32:
29137 case BFD_RELOC_ARM_GOTOFF:
c19d1205 29138 break;
b43420e6
NC		 29139
29140 case BFD_RELOC_ARM_GOT_PREL:
29141 if (fixP->fx_done || !seg->use_rela_p)
477330fc 29142 md_number_to_chars (buf, value, 4);
b43420e6
NC		 29143 break;
29144
9a6f4e97
NS		 29145 case BFD_RELOC_ARM_TARGET2:
29146 /* TARGET2 is not partial-inplace, so we need to write the
477330fc
RM		 29147 addend here for REL targets, because it won't be written out
29148 during reloc processing later. */
9a6f4e97
NS		 29149 if (fixP->fx_done || !seg->use_rela_p)
29150 md_number_to_chars (buf, fixP->fx_offset, 4);
29151 break;
188fd7ae
CL		 29152
29153 /* Relocations for FDPIC. */
29154 case BFD_RELOC_ARM_GOTFUNCDESC:
29155 case BFD_RELOC_ARM_GOTOFFFUNCDESC:
29156 case BFD_RELOC_ARM_FUNCDESC:
29157 if (arm_fdpic)
29158 {
29159 if (fixP->fx_done || !seg->use_rela_p)
29160 md_number_to_chars (buf, 0, 4);
29161 }
29162 else
29163 {
29164 as_bad_where (fixP->fx_file, fixP->fx_line,
29165 _("Relocation supported only in FDPIC mode"));
29166 }
29167 break;
c19d1205 29168#endif
6c43fab6 29169
c19d1205
ZW		 29170 case BFD_RELOC_RVA:
29171 case BFD_RELOC_32:
29172 case BFD_RELOC_ARM_TARGET1:
29173 case BFD_RELOC_ARM_ROSEGREL32:
29174 case BFD_RELOC_ARM_SBREL32:
29175 case BFD_RELOC_32_PCREL:
f0927246
NC		 29176#ifdef TE_PE
29177 case BFD_RELOC_32_SECREL:
29178#endif
2fc8bdac 29179 if (fixP->fx_done || !seg->use_rela_p)
53baae48
NC		 29180#ifdef TE_WINCE
29181 /* For WinCE we only do this for pcrel fixups. */
29182 if (fixP->fx_done || fixP->fx_pcrel)
29183#endif
29184 md_number_to_chars (buf, value, 4);
c19d1205 29185 break;
6c43fab6 29186
c19d1205
ZW		 29187#ifdef OBJ_ELF
29188 case BFD_RELOC_ARM_PREL31:
2fc8bdac 29189 if (fixP->fx_done || !seg->use_rela_p)
c19d1205
ZW		 29190 {
29191 newval = md_chars_to_number (buf, 4) & 0x80000000;
29192 if ((value ^ (value >> 1)) & 0x40000000)
29193 {
29194 as_bad_where (fixP->fx_file, fixP->fx_line,
29195 _("rel31 relocation overflow"));
29196 }
29197 newval |= value & 0x7fffffff;
29198 md_number_to_chars (buf, newval, 4);
29199 }
29200 break;
c19d1205 29201#endif
a737bd4d 29202
c19d1205 29203 case BFD_RELOC_ARM_CP_OFF_IMM:
8f06b2d8 29204 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
32c36c3c 29205 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM:
9db2f6b4
RL		 29206 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM)
29207 newval = md_chars_to_number (buf, INSN_SIZE);
29208 else
29209 newval = get_thumb32_insn (buf);
29210 if ((newval & 0x0f200f00) == 0x0d000900)
29211 {
29212 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
29213 has permitted values that are multiples of 2, in the range 0
29214 to 510. */
29215 if (value < -510 || value > 510 || (value & 1))
29216 as_bad_where (fixP->fx_file, fixP->fx_line,
29217 _("co-processor offset out of range"));
29218 }
32c36c3c
AV		 29219 else if ((newval & 0xfe001f80) == 0xec000f80)
29220 {
29221 if (value < -511 || value > 512 || (value & 3))
29222 as_bad_where (fixP->fx_file, fixP->fx_line,
29223 _("co-processor offset out of range"));
29224 }
9db2f6b4 29225 else if (value < -1023 || value > 1023 || (value & 3))
c19d1205
ZW		 29226 as_bad_where (fixP->fx_file, fixP->fx_line,
29227 _("co-processor offset out of range"));
29228 cp_off_common:
26d97720 29229 sign = value > 0;
c19d1205
ZW		 29230 if (value < 0)
29231 value = -value;
8f06b2d8
PB		 29232 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
29233 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
29234 newval = md_chars_to_number (buf, INSN_SIZE);
29235 else
29236 newval = get_thumb32_insn (buf);
26d97720 29237 if (value == 0)
32c36c3c
AV		 29238 {
29239 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM)
29240 newval &= 0xffffff80;
29241 else
29242 newval &= 0xffffff00;
29243 }
26d97720
NS		 29244 else
29245 {
32c36c3c
AV		 29246 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM)
29247 newval &= 0xff7fff80;
29248 else
29249 newval &= 0xff7fff00;
9db2f6b4
RL		 29250 if ((newval & 0x0f200f00) == 0x0d000900)
29251 {
29252 /* This is a fp16 vstr/vldr.
29253
29254 It requires the immediate offset in the instruction is shifted
29255 left by 1 to be a half-word offset.
29256
29257 Here, left shift by 1 first, and later right shift by 2
29258 should get the right offset. */
29259 value <<= 1;
29260 }
26d97720
NS		 29261 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
29262 }
8f06b2d8
PB		 29263 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
29264 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
29265 md_number_to_chars (buf, newval, INSN_SIZE);
29266 else
29267 put_thumb32_insn (buf, newval);
c19d1205 29268 break;
a737bd4d 29269
c19d1205 29270 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
8f06b2d8 29271 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
c19d1205
ZW		 29272 if (value < -255 || value > 255)
29273 as_bad_where (fixP->fx_file, fixP->fx_line,
29274 _("co-processor offset out of range"));
df7849c5 29275 value *= 4;
c19d1205 29276 goto cp_off_common;
6c43fab6 29277
c19d1205
ZW		 29278 case BFD_RELOC_ARM_THUMB_OFFSET:
29279 newval = md_chars_to_number (buf, THUMB_SIZE);
29280 /* Exactly what ranges, and where the offset is inserted depends
29281 on the type of instruction, we can establish this from the
29282 top 4 bits. */
29283 switch (newval >> 12)
29284 {
29285 case 4: /* PC load. */
29286 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
29287 forced to zero for these loads; md_pcrel_from has already
29288 compensated for this. */
29289 if (value & 3)
29290 as_bad_where (fixP->fx_file, fixP->fx_line,
29291 _("invalid offset, target not word aligned (0x%08lX)"),
0359e808
NC		 29292 (((unsigned long) fixP->fx_frag->fr_address
29293 + (unsigned long) fixP->fx_where) & ~3)
29294 + (unsigned long) value);
749479c8
AO		 29295 else if (get_recorded_alignment (seg) < 2)
29296 as_warn_where (fixP->fx_file, fixP->fx_line,
29297 _("section does not have enough alignment to ensure safe PC-relative loads"));
a737bd4d 29298
c19d1205
ZW		 29299 if (value & ~0x3fc)
29300 as_bad_where (fixP->fx_file, fixP->fx_line,
29301 _("invalid offset, value too big (0x%08lX)"),
29302 (long) value);
a737bd4d 29303
c19d1205
ZW		 29304 newval |= value >> 2;
29305 break;
a737bd4d 29306
c19d1205
ZW		 29307 case 9: /* SP load/store. */
29308 if (value & ~0x3fc)
29309 as_bad_where (fixP->fx_file, fixP->fx_line,
29310 _("invalid offset, value too big (0x%08lX)"),
29311 (long) value);
29312 newval |= value >> 2;
29313 break;
6c43fab6 29314
c19d1205
ZW		 29315 case 6: /* Word load/store. */
29316 if (value & ~0x7c)
29317 as_bad_where (fixP->fx_file, fixP->fx_line,
29318 _("invalid offset, value too big (0x%08lX)"),
29319 (long) value);
29320 newval |= value << 4; /* 6 - 2. */
29321 break;
a737bd4d 29322
c19d1205
ZW		 29323 case 7: /* Byte load/store. */
29324 if (value & ~0x1f)
29325 as_bad_where (fixP->fx_file, fixP->fx_line,
29326 _("invalid offset, value too big (0x%08lX)"),
29327 (long) value);
29328 newval |= value << 6;
29329 break;
a737bd4d 29330
c19d1205
ZW		 29331 case 8: /* Halfword load/store. */
29332 if (value & ~0x3e)
29333 as_bad_where (fixP->fx_file, fixP->fx_line,
29334 _("invalid offset, value too big (0x%08lX)"),
29335 (long) value);
29336 newval |= value << 5; /* 6 - 1. */
29337 break;
a737bd4d 29338
c19d1205
ZW		 29339 default:
29340 as_bad_where (fixP->fx_file, fixP->fx_line,
29341 "Unable to process relocation for thumb opcode: %lx",
29342 (unsigned long) newval);
29343 break;
29344 }
29345 md_number_to_chars (buf, newval, THUMB_SIZE);
29346 break;
a737bd4d 29347
c19d1205
ZW		 29348 case BFD_RELOC_ARM_THUMB_ADD:
29349 /* This is a complicated relocation, since we use it for all of
29350 the following immediate relocations:
a737bd4d 29351
c19d1205
ZW		 29352 3bit ADD/SUB
29353 8bit ADD/SUB
29354 9bit ADD/SUB SP word-aligned
29355 10bit ADD PC/SP word-aligned
a737bd4d 29356
c19d1205
ZW		 29357 The type of instruction being processed is encoded in the
29358 instruction field:
a737bd4d 29359
c19d1205
ZW		 29360 0x8000 SUB
29361 0x00F0 Rd
29362 0x000F Rs
29363 */
29364 newval = md_chars_to_number (buf, THUMB_SIZE);
29365 {
29366 int rd = (newval >> 4) & 0xf;
29367 int rs = newval & 0xf;
29368 int subtract = !!(newval & 0x8000);
a737bd4d 29369
c19d1205
ZW		 29370 /* Check for HI regs, only very restricted cases allowed:
29371 Adjusting SP, and using PC or SP to get an address. */
29372 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
29373 || (rs > 7 && rs != REG_SP && rs != REG_PC))
29374 as_bad_where (fixP->fx_file, fixP->fx_line,
29375 _("invalid Hi register with immediate"));
a737bd4d 29376
c19d1205
ZW		 29377 /* If value is negative, choose the opposite instruction. */
29378 if (value < 0)
29379 {
29380 value = -value;
29381 subtract = !subtract;
29382 if (value < 0)
29383 as_bad_where (fixP->fx_file, fixP->fx_line,
29384 _("immediate value out of range"));
29385 }
a737bd4d 29386
c19d1205
ZW		 29387 if (rd == REG_SP)
29388 {
75c11999 29389 if (value & ~0x1fc)
c19d1205
ZW		 29390 as_bad_where (fixP->fx_file, fixP->fx_line,
29391 _("invalid immediate for stack address calculation"));
29392 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
29393 newval |= value >> 2;
29394 }
29395 else if (rs == REG_PC || rs == REG_SP)
29396 {
c12d2c9d
NC		 29397 /* PR gas/18541. If the addition is for a defined symbol
29398 within range of an ADR instruction then accept it. */
29399 if (subtract
29400 && value == 4
29401 && fixP->fx_addsy != NULL)
29402 {
29403 subtract = 0;
29404
29405 if (! S_IS_DEFINED (fixP->fx_addsy)
29406 || S_GET_SEGMENT (fixP->fx_addsy) != seg
29407 || S_IS_WEAK (fixP->fx_addsy))
29408 {
29409 as_bad_where (fixP->fx_file, fixP->fx_line,
29410 _("address calculation needs a strongly defined nearby symbol"));
29411 }
29412 else
29413 {
29414 offsetT v = fixP->fx_where + fixP->fx_frag->fr_address;
29415
29416 /* Round up to the next 4-byte boundary. */
29417 if (v & 3)
29418 v = (v + 3) & ~ 3;
29419 else
29420 v += 4;
29421 v = S_GET_VALUE (fixP->fx_addsy) - v;
29422
29423 if (v & ~0x3fc)
29424 {
29425 as_bad_where (fixP->fx_file, fixP->fx_line,
29426 _("symbol too far away"));
29427 }
29428 else
29429 {
29430 fixP->fx_done = 1;
29431 value = v;
29432 }
29433 }
29434 }
29435
c19d1205
ZW		 29436 if (subtract || value & ~0x3fc)
29437 as_bad_where (fixP->fx_file, fixP->fx_line,
29438 _("invalid immediate for address calculation (value = 0x%08lX)"),
5fc177c8 29439 (unsigned long) (subtract ? - value : value));
c19d1205
ZW		 29440 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
29441 newval |= rd << 8;
29442 newval |= value >> 2;
29443 }
29444 else if (rs == rd)
29445 {
29446 if (value & ~0xff)
29447 as_bad_where (fixP->fx_file, fixP->fx_line,
29448 _("immediate value out of range"));
29449 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
29450 newval |= (rd << 8) | value;
29451 }
29452 else
29453 {
29454 if (value & ~0x7)
29455 as_bad_where (fixP->fx_file, fixP->fx_line,
29456 _("immediate value out of range"));
29457 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
29458 newval |= rd | (rs << 3) | (value << 6);
29459 }
29460 }
29461 md_number_to_chars (buf, newval, THUMB_SIZE);
29462 break;
a737bd4d 29463
c19d1205
ZW		 29464 case BFD_RELOC_ARM_THUMB_IMM:
29465 newval = md_chars_to_number (buf, THUMB_SIZE);
29466 if (value < 0 || value > 255)
29467 as_bad_where (fixP->fx_file, fixP->fx_line,
4e6e072b 29468 _("invalid immediate: %ld is out of range"),
c19d1205
ZW		 29469 (long) value);
29470 newval |= value;
29471 md_number_to_chars (buf, newval, THUMB_SIZE);
29472 break;
a737bd4d 29473
c19d1205
ZW		 29474 case BFD_RELOC_ARM_THUMB_SHIFT:
29475 /* 5bit shift value (0..32). LSL cannot take 32. */
29476 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
29477 temp = newval & 0xf800;
29478 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
29479 as_bad_where (fixP->fx_file, fixP->fx_line,
29480 _("invalid shift value: %ld"), (long) value);
29481 /* Shifts of zero must be encoded as LSL. */
29482 if (value == 0)
29483 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
29484 /* Shifts of 32 are encoded as zero. */
29485 else if (value == 32)
29486 value = 0;
29487 newval |= value << 6;
29488 md_number_to_chars (buf, newval, THUMB_SIZE);
29489 break;
a737bd4d 29490
c19d1205
ZW		 29491 case BFD_RELOC_VTABLE_INHERIT:
29492 case BFD_RELOC_VTABLE_ENTRY:
29493 fixP->fx_done = 0;
29494 return;
6c43fab6 29495
b6895b4f
PB		 29496 case BFD_RELOC_ARM_MOVW:
29497 case BFD_RELOC_ARM_MOVT:
29498 case BFD_RELOC_ARM_THUMB_MOVW:
29499 case BFD_RELOC_ARM_THUMB_MOVT:
29500 if (fixP->fx_done || !seg->use_rela_p)
29501 {
29502 /* REL format relocations are limited to a 16-bit addend. */
29503 if (!fixP->fx_done)
29504 {
39623e12 29505 if (value < -0x8000 || value > 0x7fff)
b6895b4f 29506 as_bad_where (fixP->fx_file, fixP->fx_line,
ff5075ca 29507 _("offset out of range"));
b6895b4f
PB		 29508 }
29509 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
29510 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
29511 {
29512 value >>= 16;
29513 }
29514
29515 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
29516 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
29517 {
29518 newval = get_thumb32_insn (buf);
29519 newval &= 0xfbf08f00;
29520 newval |= (value & 0xf000) << 4;
29521 newval |= (value & 0x0800) << 15;
29522 newval |= (value & 0x0700) << 4;
29523 newval |= (value & 0x00ff);
29524 put_thumb32_insn (buf, newval);
29525 }
29526 else
29527 {
29528 newval = md_chars_to_number (buf, 4);
29529 newval &= 0xfff0f000;
29530 newval |= value & 0x0fff;
29531 newval |= (value & 0xf000) << 4;
29532 md_number_to_chars (buf, newval, 4);
29533 }
29534 }
29535 return;
29536
72d98d16
MG		 29537 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC:
29538 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC:
29539 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC:
29540 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC:
29541 gas_assert (!fixP->fx_done);
29542 {
29543 bfd_vma insn;
29544 bfd_boolean is_mov;
29545 bfd_vma encoded_addend = value;
29546
29547 /* Check that addend can be encoded in instruction. */
29548 if (!seg->use_rela_p && (value < 0 || value > 255))
29549 as_bad_where (fixP->fx_file, fixP->fx_line,
29550 _("the offset 0x%08lX is not representable"),
29551 (unsigned long) encoded_addend);
29552
29553 /* Extract the instruction. */
29554 insn = md_chars_to_number (buf, THUMB_SIZE);
29555 is_mov = (insn & 0xf800) == 0x2000;
29556
29557 /* Encode insn. */
29558 if (is_mov)
29559 {
29560 if (!seg->use_rela_p)
29561 insn |= encoded_addend;
29562 }
29563 else
29564 {
29565 int rd, rs;
29566
29567 /* Extract the instruction. */
29568 /* Encoding is the following
29569 0x8000 SUB
29570 0x00F0 Rd
29571 0x000F Rs
29572 */
29573 /* The following conditions must be true :
29574 - ADD
29575 - Rd == Rs
29576 - Rd <= 7
29577 */
29578 rd = (insn >> 4) & 0xf;
29579 rs = insn & 0xf;
29580 if ((insn & 0x8000) || (rd != rs) || rd > 7)
29581 as_bad_where (fixP->fx_file, fixP->fx_line,
29582 _("Unable to process relocation for thumb opcode: %lx"),
29583 (unsigned long) insn);
29584
29585 /* Encode as ADD immediate8 thumb 1 code. */
29586 insn = 0x3000 | (rd << 8);
29587
29588 /* Place the encoded addend into the first 8 bits of the
29589 instruction. */
29590 if (!seg->use_rela_p)
29591 insn |= encoded_addend;
29592 }
29593
29594 /* Update the instruction. */
29595 md_number_to_chars (buf, insn, THUMB_SIZE);
29596 }
29597 break;
29598
4962c51a
MS		 29599 case BFD_RELOC_ARM_ALU_PC_G0_NC:
29600 case BFD_RELOC_ARM_ALU_PC_G0:
29601 case BFD_RELOC_ARM_ALU_PC_G1_NC:
29602 case BFD_RELOC_ARM_ALU_PC_G1:
29603 case BFD_RELOC_ARM_ALU_PC_G2:
29604 case BFD_RELOC_ARM_ALU_SB_G0_NC:
29605 case BFD_RELOC_ARM_ALU_SB_G0:
29606 case BFD_RELOC_ARM_ALU_SB_G1_NC:
29607 case BFD_RELOC_ARM_ALU_SB_G1:
29608 case BFD_RELOC_ARM_ALU_SB_G2:
9c2799c2 29609 gas_assert (!fixP->fx_done);
4962c51a
MS		 29610 if (!seg->use_rela_p)
29611 {
477330fc
RM		 29612 bfd_vma insn;
29613 bfd_vma encoded_addend;
3ca4a8ec 29614 bfd_vma addend_abs = llabs (value);
477330fc
RM		 29615
29616 /* Check that the absolute value of the addend can be
29617 expressed as an 8-bit constant plus a rotation. */
29618 encoded_addend = encode_arm_immediate (addend_abs);
29619 if (encoded_addend == (unsigned int) FAIL)
4962c51a 29620 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 29621 _("the offset 0x%08lX is not representable"),
29622 (unsigned long) addend_abs);
29623
29624 /* Extract the instruction. */
29625 insn = md_chars_to_number (buf, INSN_SIZE);
29626
29627 /* If the addend is positive, use an ADD instruction.
29628 Otherwise use a SUB. Take care not to destroy the S bit. */
29629 insn &= 0xff1fffff;
29630 if (value < 0)
29631 insn |= 1 << 22;
29632 else
29633 insn |= 1 << 23;
29634
29635 /* Place the encoded addend into the first 12 bits of the
29636 instruction. */
29637 insn &= 0xfffff000;
29638 insn |= encoded_addend;
29639
29640 /* Update the instruction. */
29641 md_number_to_chars (buf, insn, INSN_SIZE);
4962c51a
MS		 29642 }
29643 break;
29644
29645 case BFD_RELOC_ARM_LDR_PC_G0:
29646 case BFD_RELOC_ARM_LDR_PC_G1:
29647 case BFD_RELOC_ARM_LDR_PC_G2:
29648 case BFD_RELOC_ARM_LDR_SB_G0:
29649 case BFD_RELOC_ARM_LDR_SB_G1:
29650 case BFD_RELOC_ARM_LDR_SB_G2:
9c2799c2 29651 gas_assert (!fixP->fx_done);
4962c51a 29652 if (!seg->use_rela_p)
477330fc
RM		 29653 {
29654 bfd_vma insn;
3ca4a8ec 29655 bfd_vma addend_abs = llabs (value);
4962c51a 29656
477330fc
RM		 29657 /* Check that the absolute value of the addend can be
29658 encoded in 12 bits. */
29659 if (addend_abs >= 0x1000)
4962c51a 29660 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 29661 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
29662 (unsigned long) addend_abs);
29663
29664 /* Extract the instruction. */
29665 insn = md_chars_to_number (buf, INSN_SIZE);
29666
29667 /* If the addend is negative, clear bit 23 of the instruction.
29668 Otherwise set it. */
29669 if (value < 0)
29670 insn &= ~(1 << 23);
29671 else
29672 insn |= 1 << 23;
29673
29674 /* Place the absolute value of the addend into the first 12 bits
29675 of the instruction. */
29676 insn &= 0xfffff000;
29677 insn |= addend_abs;
29678
29679 /* Update the instruction. */
29680 md_number_to_chars (buf, insn, INSN_SIZE);
29681 }
4962c51a
MS		 29682 break;
29683
29684 case BFD_RELOC_ARM_LDRS_PC_G0:
29685 case BFD_RELOC_ARM_LDRS_PC_G1:
29686 case BFD_RELOC_ARM_LDRS_PC_G2:
29687 case BFD_RELOC_ARM_LDRS_SB_G0:
29688 case BFD_RELOC_ARM_LDRS_SB_G1:
29689 case BFD_RELOC_ARM_LDRS_SB_G2:
9c2799c2 29690 gas_assert (!fixP->fx_done);
4962c51a 29691 if (!seg->use_rela_p)
477330fc
RM		 29692 {
29693 bfd_vma insn;
3ca4a8ec 29694 bfd_vma addend_abs = llabs (value);
4962c51a 29695
477330fc
RM		 29696 /* Check that the absolute value of the addend can be
29697 encoded in 8 bits. */
29698 if (addend_abs >= 0x100)
4962c51a 29699 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 29700 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
29701 (unsigned long) addend_abs);
29702
29703 /* Extract the instruction. */
29704 insn = md_chars_to_number (buf, INSN_SIZE);
29705
29706 /* If the addend is negative, clear bit 23 of the instruction.
29707 Otherwise set it. */
29708 if (value < 0)
29709 insn &= ~(1 << 23);
29710 else
29711 insn |= 1 << 23;
29712
29713 /* Place the first four bits of the absolute value of the addend
29714 into the first 4 bits of the instruction, and the remaining
29715 four into bits 8 .. 11. */
29716 insn &= 0xfffff0f0;
29717 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
29718
29719 /* Update the instruction. */
29720 md_number_to_chars (buf, insn, INSN_SIZE);
29721 }
4962c51a
MS		 29722 break;
29723
29724 case BFD_RELOC_ARM_LDC_PC_G0:
29725 case BFD_RELOC_ARM_LDC_PC_G1:
29726 case BFD_RELOC_ARM_LDC_PC_G2:
29727 case BFD_RELOC_ARM_LDC_SB_G0:
29728 case BFD_RELOC_ARM_LDC_SB_G1:
29729 case BFD_RELOC_ARM_LDC_SB_G2:
9c2799c2 29730 gas_assert (!fixP->fx_done);
4962c51a 29731 if (!seg->use_rela_p)
477330fc
RM		 29732 {
29733 bfd_vma insn;
3ca4a8ec 29734 bfd_vma addend_abs = llabs (value);
4962c51a 29735
477330fc
RM		 29736 /* Check that the absolute value of the addend is a multiple of
29737 four and, when divided by four, fits in 8 bits. */
29738 if (addend_abs & 0x3)
4962c51a 29739 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 29740 _("bad offset 0x%08lX (must be word-aligned)"),
29741 (unsigned long) addend_abs);
4962c51a 29742
477330fc 29743 if ((addend_abs >> 2) > 0xff)
4962c51a 29744 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 29745 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
29746 (unsigned long) addend_abs);
29747
29748 /* Extract the instruction. */
29749 insn = md_chars_to_number (buf, INSN_SIZE);
29750
29751 /* If the addend is negative, clear bit 23 of the instruction.
29752 Otherwise set it. */
29753 if (value < 0)
29754 insn &= ~(1 << 23);
29755 else
29756 insn |= 1 << 23;
29757
29758 /* Place the addend (divided by four) into the first eight
29759 bits of the instruction. */
29760 insn &= 0xfffffff0;
29761 insn |= addend_abs >> 2;
29762
29763 /* Update the instruction. */
29764 md_number_to_chars (buf, insn, INSN_SIZE);
29765 }
4962c51a
MS		 29766 break;
29767
e12437dc
AV		 29768 case BFD_RELOC_THUMB_PCREL_BRANCH5:
29769 if (fixP->fx_addsy
29770 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
29771 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
29772 && ARM_IS_FUNC (fixP->fx_addsy)
29773 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
29774 {
29775 /* Force a relocation for a branch 5 bits wide. */
29776 fixP->fx_done = 0;
29777 }
29778 if (v8_1_branch_value_check (value, 5, FALSE) == FAIL)
29779 as_bad_where (fixP->fx_file, fixP->fx_line,
29780 BAD_BRANCH_OFF);
29781
29782 if (fixP->fx_done || !seg->use_rela_p)
29783 {
29784 addressT boff = value >> 1;
29785
29786 newval = md_chars_to_number (buf, THUMB_SIZE);
29787 newval |= (boff << 7);
29788 md_number_to_chars (buf, newval, THUMB_SIZE);
29789 }
29790 break;
29791
f6b2b12d
AV		 29792 case BFD_RELOC_THUMB_PCREL_BFCSEL:
29793 if (fixP->fx_addsy
29794 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
29795 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
29796 && ARM_IS_FUNC (fixP->fx_addsy)
29797 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
29798 {
29799 fixP->fx_done = 0;
29800 }
29801 if ((value & ~0x7f) && ((value & ~0x3f) != ~0x3f))
29802 as_bad_where (fixP->fx_file, fixP->fx_line,
29803 _("branch out of range"));
29804
29805 if (fixP->fx_done || !seg->use_rela_p)
29806 {
29807 newval = md_chars_to_number (buf, THUMB_SIZE);
29808
29809 addressT boff = ((newval & 0x0780) >> 7) << 1;
29810 addressT diff = value - boff;
29811
29812 if (diff == 4)
29813 {
29814 newval |= 1 << 1; /* T bit. */
29815 }
29816 else if (diff != 2)
29817 {
29818 as_bad_where (fixP->fx_file, fixP->fx_line,
29819 _("out of range label-relative fixup value"));
29820 }
29821 md_number_to_chars (buf, newval, THUMB_SIZE);
29822 }
29823 break;
29824
e5d6e09e
AV		 29825 case BFD_RELOC_ARM_THUMB_BF17:
29826 if (fixP->fx_addsy
29827 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
29828 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
29829 && ARM_IS_FUNC (fixP->fx_addsy)
29830 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
29831 {
29832 /* Force a relocation for a branch 17 bits wide. */
29833 fixP->fx_done = 0;
29834 }
29835
29836 if (v8_1_branch_value_check (value, 17, TRUE) == FAIL)
29837 as_bad_where (fixP->fx_file, fixP->fx_line,
29838 BAD_BRANCH_OFF);
29839
29840 if (fixP->fx_done || !seg->use_rela_p)
29841 {
29842 offsetT newval2;
29843 addressT immA, immB, immC;
29844
29845 immA = (value & 0x0001f000) >> 12;
29846 immB = (value & 0x00000ffc) >> 2;
29847 immC = (value & 0x00000002) >> 1;
29848
29849 newval = md_chars_to_number (buf, THUMB_SIZE);
29850 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
29851 newval |= immA;
29852 newval2 |= (immC << 11) | (immB << 1);
29853 md_number_to_chars (buf, newval, THUMB_SIZE);
29854 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
29855 }
29856 break;
29857
1caf72a5
AV		 29858 case BFD_RELOC_ARM_THUMB_BF19:
29859 if (fixP->fx_addsy
29860 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
29861 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
29862 && ARM_IS_FUNC (fixP->fx_addsy)
29863 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
29864 {
29865 /* Force a relocation for a branch 19 bits wide. */
29866 fixP->fx_done = 0;
29867 }
29868
29869 if (v8_1_branch_value_check (value, 19, TRUE) == FAIL)
29870 as_bad_where (fixP->fx_file, fixP->fx_line,
29871 BAD_BRANCH_OFF);
29872
29873 if (fixP->fx_done || !seg->use_rela_p)
29874 {
29875 offsetT newval2;
29876 addressT immA, immB, immC;
29877
29878 immA = (value & 0x0007f000) >> 12;
29879 immB = (value & 0x00000ffc) >> 2;
29880 immC = (value & 0x00000002) >> 1;
29881
29882 newval = md_chars_to_number (buf, THUMB_SIZE);
29883 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
29884 newval |= immA;
29885 newval2 |= (immC << 11) | (immB << 1);
29886 md_number_to_chars (buf, newval, THUMB_SIZE);
29887 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
29888 }
29889 break;
29890
1889da70
AV		 29891 case BFD_RELOC_ARM_THUMB_BF13:
29892 if (fixP->fx_addsy
29893 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
29894 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
29895 && ARM_IS_FUNC (fixP->fx_addsy)
29896 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
29897 {
29898 /* Force a relocation for a branch 13 bits wide. */
29899 fixP->fx_done = 0;
29900 }
29901
29902 if (v8_1_branch_value_check (value, 13, TRUE) == FAIL)
29903 as_bad_where (fixP->fx_file, fixP->fx_line,
29904 BAD_BRANCH_OFF);
29905
29906 if (fixP->fx_done || !seg->use_rela_p)
29907 {
29908 offsetT newval2;
29909 addressT immA, immB, immC;
29910
29911 immA = (value & 0x00001000) >> 12;
29912 immB = (value & 0x00000ffc) >> 2;
29913 immC = (value & 0x00000002) >> 1;
29914
29915 newval = md_chars_to_number (buf, THUMB_SIZE);
29916 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
29917 newval |= immA;
29918 newval2 |= (immC << 11) | (immB << 1);
29919 md_number_to_chars (buf, newval, THUMB_SIZE);
29920 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
29921 }
29922 break;
29923
60f993ce
AV		 29924 case BFD_RELOC_ARM_THUMB_LOOP12:
29925 if (fixP->fx_addsy
29926 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
29927 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
29928 && ARM_IS_FUNC (fixP->fx_addsy)
29929 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
29930 {
29931 /* Force a relocation for a branch 12 bits wide. */
29932 fixP->fx_done = 0;
29933 }
29934
29935 bfd_vma insn = get_thumb32_insn (buf);
1f6234a3 29936 /* le lr, <label>, le <label> or letp lr, <label> */
60f993ce 29937 if (((insn & 0xffffffff) == 0xf00fc001)
1f6234a3
AV		 29938 || ((insn & 0xffffffff) == 0xf02fc001)
29939 || ((insn & 0xffffffff) == 0xf01fc001))
60f993ce
AV		 29940 value = -value;
29941
29942 if (v8_1_branch_value_check (value, 12, FALSE) == FAIL)
29943 as_bad_where (fixP->fx_file, fixP->fx_line,
29944 BAD_BRANCH_OFF);
29945 if (fixP->fx_done || !seg->use_rela_p)
29946 {
29947 addressT imml, immh;
29948
29949 immh = (value & 0x00000ffc) >> 2;
29950 imml = (value & 0x00000002) >> 1;
29951
29952 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
29953 newval |= (imml << 11) | (immh << 1);
29954 md_number_to_chars (buf + THUMB_SIZE, newval, THUMB_SIZE);
29955 }
29956 break;
29957
845b51d6
PB		 29958 case BFD_RELOC_ARM_V4BX:
29959 /* This will need to go in the object file. */
29960 fixP->fx_done = 0;
29961 break;
29962
c19d1205
ZW		 29963 case BFD_RELOC_UNUSED:
29964 default:
29965 as_bad_where (fixP->fx_file, fixP->fx_line,
29966 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
29967 }
6c43fab6
RE		 29968}
29969
c19d1205
ZW		 29970/* Translate internal representation of relocation info to BFD target
29971 format. */
a737bd4d 29972
c19d1205 29973arelent *
00a97672 29974tc_gen_reloc (asection *section, fixS *fixp)
a737bd4d 29975{
c19d1205
ZW		 29976 arelent * reloc;
29977 bfd_reloc_code_real_type code;
a737bd4d 29978
325801bd 29979 reloc = XNEW (arelent);
a737bd4d 29980
325801bd 29981 reloc->sym_ptr_ptr = XNEW (asymbol *);
c19d1205
ZW		 29982 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
29983 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
a737bd4d 29984
2fc8bdac 29985 if (fixp->fx_pcrel)
00a97672
RS		 29986 {
29987 if (section->use_rela_p)
29988 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
29989 else
29990 fixp->fx_offset = reloc->address;
29991 }
c19d1205 29992 reloc->addend = fixp->fx_offset;
a737bd4d 29993
c19d1205 29994 switch (fixp->fx_r_type)
a737bd4d 29995 {
c19d1205
ZW		 29996 case BFD_RELOC_8:
29997 if (fixp->fx_pcrel)
29998 {
29999 code = BFD_RELOC_8_PCREL;
30000 break;
30001 }
1a0670f3 30002 /* Fall through. */
a737bd4d 30003
c19d1205
ZW		 30004 case BFD_RELOC_16:
30005 if (fixp->fx_pcrel)
30006 {
30007 code = BFD_RELOC_16_PCREL;
30008 break;
30009 }
1a0670f3 30010 /* Fall through. */
6c43fab6 30011
c19d1205
ZW		 30012 case BFD_RELOC_32:
30013 if (fixp->fx_pcrel)
30014 {
30015 code = BFD_RELOC_32_PCREL;
30016 break;
30017 }
1a0670f3 30018 /* Fall through. */
a737bd4d 30019
b6895b4f
PB		 30020 case BFD_RELOC_ARM_MOVW:
30021 if (fixp->fx_pcrel)
30022 {
30023 code = BFD_RELOC_ARM_MOVW_PCREL;
30024 break;
30025 }
1a0670f3 30026 /* Fall through. */
b6895b4f
PB		 30027
30028 case BFD_RELOC_ARM_MOVT:
30029 if (fixp->fx_pcrel)
30030 {
30031 code = BFD_RELOC_ARM_MOVT_PCREL;
30032 break;
30033 }
1a0670f3 30034 /* Fall through. */
b6895b4f
PB		 30035
30036 case BFD_RELOC_ARM_THUMB_MOVW:
30037 if (fixp->fx_pcrel)
30038 {
30039 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
30040 break;
30041 }
1a0670f3 30042 /* Fall through. */
b6895b4f
PB		 30043
30044 case BFD_RELOC_ARM_THUMB_MOVT:
30045 if (fixp->fx_pcrel)
30046 {
30047 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
30048 break;
30049 }
1a0670f3 30050 /* Fall through. */
b6895b4f 30051
c19d1205
ZW		 30052 case BFD_RELOC_NONE:
30053 case BFD_RELOC_ARM_PCREL_BRANCH:
30054 case BFD_RELOC_ARM_PCREL_BLX:
30055 case BFD_RELOC_RVA:
30056 case BFD_RELOC_THUMB_PCREL_BRANCH7:
30057 case BFD_RELOC_THUMB_PCREL_BRANCH9:
30058 case BFD_RELOC_THUMB_PCREL_BRANCH12:
30059 case BFD_RELOC_THUMB_PCREL_BRANCH20:
30060 case BFD_RELOC_THUMB_PCREL_BRANCH23:
30061 case BFD_RELOC_THUMB_PCREL_BRANCH25:
c19d1205
ZW		 30062 case BFD_RELOC_VTABLE_ENTRY:
30063 case BFD_RELOC_VTABLE_INHERIT:
f0927246
NC		 30064#ifdef TE_PE
30065 case BFD_RELOC_32_SECREL:
30066#endif
c19d1205
ZW		 30067 code = fixp->fx_r_type;
30068 break;
a737bd4d 30069
00adf2d4
JB		 30070 case BFD_RELOC_THUMB_PCREL_BLX:
30071#ifdef OBJ_ELF
30072 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
30073 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
30074 else
30075#endif
30076 code = BFD_RELOC_THUMB_PCREL_BLX;
30077 break;
30078
c19d1205
ZW		 30079 case BFD_RELOC_ARM_LITERAL:
30080 case BFD_RELOC_ARM_HWLITERAL:
30081 /* If this is called then the a literal has
30082 been referenced across a section boundary. */
30083 as_bad_where (fixp->fx_file, fixp->fx_line,
30084 _("literal referenced across section boundary"));
30085 return NULL;
a737bd4d 30086
c19d1205 30087#ifdef OBJ_ELF
0855e32b
NS		 30088 case BFD_RELOC_ARM_TLS_CALL:
30089 case BFD_RELOC_ARM_THM_TLS_CALL:
30090 case BFD_RELOC_ARM_TLS_DESCSEQ:
30091 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
c19d1205
ZW		 30092 case BFD_RELOC_ARM_GOT32:
30093 case BFD_RELOC_ARM_GOTOFF:
b43420e6 30094 case BFD_RELOC_ARM_GOT_PREL:
c19d1205
ZW		 30095 case BFD_RELOC_ARM_PLT32:
30096 case BFD_RELOC_ARM_TARGET1:
30097 case BFD_RELOC_ARM_ROSEGREL32:
30098 case BFD_RELOC_ARM_SBREL32:
30099 case BFD_RELOC_ARM_PREL31:
30100 case BFD_RELOC_ARM_TARGET2:
c19d1205 30101 case BFD_RELOC_ARM_TLS_LDO32:
39b41c9c
PB		 30102 case BFD_RELOC_ARM_PCREL_CALL:
30103 case BFD_RELOC_ARM_PCREL_JUMP:
4962c51a
MS		 30104 case BFD_RELOC_ARM_ALU_PC_G0_NC:
30105 case BFD_RELOC_ARM_ALU_PC_G0:
30106 case BFD_RELOC_ARM_ALU_PC_G1_NC:
30107 case BFD_RELOC_ARM_ALU_PC_G1:
30108 case BFD_RELOC_ARM_ALU_PC_G2:
30109 case BFD_RELOC_ARM_LDR_PC_G0:
30110 case BFD_RELOC_ARM_LDR_PC_G1:
30111 case BFD_RELOC_ARM_LDR_PC_G2:
30112 case BFD_RELOC_ARM_LDRS_PC_G0:
30113 case BFD_RELOC_ARM_LDRS_PC_G1:
30114 case BFD_RELOC_ARM_LDRS_PC_G2:
30115 case BFD_RELOC_ARM_LDC_PC_G0:
30116 case BFD_RELOC_ARM_LDC_PC_G1:
30117 case BFD_RELOC_ARM_LDC_PC_G2:
30118 case BFD_RELOC_ARM_ALU_SB_G0_NC:
30119 case BFD_RELOC_ARM_ALU_SB_G0:
30120 case BFD_RELOC_ARM_ALU_SB_G1_NC:
30121 case BFD_RELOC_ARM_ALU_SB_G1:
30122 case BFD_RELOC_ARM_ALU_SB_G2:
30123 case BFD_RELOC_ARM_LDR_SB_G0:
30124 case BFD_RELOC_ARM_LDR_SB_G1:
30125 case BFD_RELOC_ARM_LDR_SB_G2:
30126 case BFD_RELOC_ARM_LDRS_SB_G0:
30127 case BFD_RELOC_ARM_LDRS_SB_G1:
30128 case BFD_RELOC_ARM_LDRS_SB_G2:
30129 case BFD_RELOC_ARM_LDC_SB_G0:
30130 case BFD_RELOC_ARM_LDC_SB_G1:
30131 case BFD_RELOC_ARM_LDC_SB_G2:
845b51d6 30132 case BFD_RELOC_ARM_V4BX:
72d98d16
MG		 30133 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC:
30134 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC:
30135 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC:
30136 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC:
188fd7ae
CL		 30137 case BFD_RELOC_ARM_GOTFUNCDESC:
30138 case BFD_RELOC_ARM_GOTOFFFUNCDESC:
30139 case BFD_RELOC_ARM_FUNCDESC:
e5d6e09e 30140 case BFD_RELOC_ARM_THUMB_BF17:
1caf72a5 30141 case BFD_RELOC_ARM_THUMB_BF19:
1889da70 30142 case BFD_RELOC_ARM_THUMB_BF13:
c19d1205
ZW		 30143 code = fixp->fx_r_type;
30144 break;
a737bd4d 30145
0855e32b 30146 case BFD_RELOC_ARM_TLS_GOTDESC:
c19d1205 30147 case BFD_RELOC_ARM_TLS_GD32:
5c5a4843 30148 case BFD_RELOC_ARM_TLS_GD32_FDPIC:
75c11999 30149 case BFD_RELOC_ARM_TLS_LE32:
c19d1205 30150 case BFD_RELOC_ARM_TLS_IE32:
5c5a4843 30151 case BFD_RELOC_ARM_TLS_IE32_FDPIC:
c19d1205 30152 case BFD_RELOC_ARM_TLS_LDM32:
5c5a4843 30153 case BFD_RELOC_ARM_TLS_LDM32_FDPIC:
c19d1205
ZW		 30154 /* BFD will include the symbol's address in the addend.
30155 But we don't want that, so subtract it out again here. */
30156 if (!S_IS_COMMON (fixp->fx_addsy))
30157 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
30158 code = fixp->fx_r_type;
30159 break;
30160#endif
a737bd4d 30161
c19d1205
ZW		 30162 case BFD_RELOC_ARM_IMMEDIATE:
30163 as_bad_where (fixp->fx_file, fixp->fx_line,
30164 _("internal relocation (type: IMMEDIATE) not fixed up"));
30165 return NULL;
a737bd4d 30166
c19d1205
ZW		 30167 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
30168 as_bad_where (fixp->fx_file, fixp->fx_line,
30169 _("ADRL used for a symbol not defined in the same file"));
30170 return NULL;
a737bd4d 30171
e12437dc 30172 case BFD_RELOC_THUMB_PCREL_BRANCH5:
f6b2b12d 30173 case BFD_RELOC_THUMB_PCREL_BFCSEL:
60f993ce 30174 case BFD_RELOC_ARM_THUMB_LOOP12:
e12437dc
AV		 30175 as_bad_where (fixp->fx_file, fixp->fx_line,
30176 _("%s used for a symbol not defined in the same file"),
30177 bfd_get_reloc_code_name (fixp->fx_r_type));
30178 return NULL;
30179
c19d1205 30180 case BFD_RELOC_ARM_OFFSET_IMM:
00a97672
RS		 30181 if (section->use_rela_p)
30182 {
30183 code = fixp->fx_r_type;
30184 break;
30185 }
30186
c19d1205
ZW		 30187 if (fixp->fx_addsy != NULL
30188 && !S_IS_DEFINED (fixp->fx_addsy)
30189 && S_IS_LOCAL (fixp->fx_addsy))
a737bd4d 30190 {
c19d1205
ZW		 30191 as_bad_where (fixp->fx_file, fixp->fx_line,
30192 _("undefined local label `%s'"),
30193 S_GET_NAME (fixp->fx_addsy));
30194 return NULL;
a737bd4d
NC		 30195 }
30196
c19d1205
ZW		 30197 as_bad_where (fixp->fx_file, fixp->fx_line,
30198 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
30199 return NULL;
a737bd4d 30200
c19d1205
ZW		 30201 default:
30202 {
e0471c16 30203 const char * type;
6c43fab6 30204
c19d1205
ZW		 30205 switch (fixp->fx_r_type)
30206 {
30207 case BFD_RELOC_NONE: type = "NONE"; break;
30208 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
30209 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
3eb17e6b 30210 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
c19d1205
ZW		 30211 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
30212 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
30213 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
db187cb9 30214 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
8f06b2d8 30215 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
c19d1205
ZW		 30216 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
30217 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
30218 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
30219 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
30220 default: type = _("<unknown>"); break;
30221 }
30222 as_bad_where (fixp->fx_file, fixp->fx_line,
30223 _("cannot represent %s relocation in this object file format"),
30224 type);
30225 return NULL;
30226 }
a737bd4d 30227 }
6c43fab6 30228
c19d1205
ZW		 30229#ifdef OBJ_ELF
30230 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
30231 && GOT_symbol
30232 && fixp->fx_addsy == GOT_symbol)
30233 {
30234 code = BFD_RELOC_ARM_GOTPC;
30235 reloc->addend = fixp->fx_offset = reloc->address;
30236 }
30237#endif
6c43fab6 30238
c19d1205 30239 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
6c43fab6 30240
c19d1205
ZW		 30241 if (reloc->howto == NULL)
30242 {
30243 as_bad_where (fixp->fx_file, fixp->fx_line,
30244 _("cannot represent %s relocation in this object file format"),
30245 bfd_get_reloc_code_name (code));
30246 return NULL;
30247 }
6c43fab6 30248
c19d1205
ZW		 30249 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
30250 vtable entry to be used in the relocation's section offset. */
30251 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
30252 reloc->address = fixp->fx_offset;
6c43fab6 30253
c19d1205 30254 return reloc;
6c43fab6
RE		 30255}
30256
c19d1205 30257/* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6c43fab6 30258
c19d1205
ZW		 30259void
30260cons_fix_new_arm (fragS * frag,
30261 int where,
30262 int size,
62ebcb5c
AM		 30263 expressionS * exp,
30264 bfd_reloc_code_real_type reloc)
6c43fab6 30265{
c19d1205 30266 int pcrel = 0;
6c43fab6 30267
c19d1205
ZW		 30268 /* Pick a reloc.
30269 FIXME: @@ Should look at CPU word size. */
30270 switch (size)
30271 {
30272 case 1:
62ebcb5c 30273 reloc = BFD_RELOC_8;
c19d1205
ZW		 30274 break;
30275 case 2:
62ebcb5c 30276 reloc = BFD_RELOC_16;
c19d1205
ZW		 30277 break;
30278 case 4:
30279 default:
62ebcb5c 30280 reloc = BFD_RELOC_32;
c19d1205
ZW		 30281 break;
30282 case 8:
62ebcb5c 30283 reloc = BFD_RELOC_64;
c19d1205
ZW		 30284 break;
30285 }
6c43fab6 30286
f0927246
NC		 30287#ifdef TE_PE
30288 if (exp->X_op == O_secrel)
30289 {
30290 exp->X_op = O_symbol;
62ebcb5c 30291 reloc = BFD_RELOC_32_SECREL;
f0927246
NC		 30292 }
30293#endif
30294
62ebcb5c 30295 fix_new_exp (frag, where, size, exp, pcrel, reloc);
c19d1205 30296}
6c43fab6 30297
4343666d 30298#if defined (OBJ_COFF)
c19d1205
ZW		 30299void
30300arm_validate_fix (fixS * fixP)
6c43fab6 30301{
c19d1205
ZW		 30302 /* If the destination of the branch is a defined symbol which does not have
30303 the THUMB_FUNC attribute, then we must be calling a function which has
30304 the (interfacearm) attribute. We look for the Thumb entry point to that
30305 function and change the branch to refer to that function instead. */
30306 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
30307 && fixP->fx_addsy != NULL
30308 && S_IS_DEFINED (fixP->fx_addsy)
30309 && ! THUMB_IS_FUNC (fixP->fx_addsy))
6c43fab6 30310 {
c19d1205 30311 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
6c43fab6 30312 }
c19d1205
ZW		 30313}
30314#endif
6c43fab6 30315
267bf995 30316
c19d1205
ZW		 30317int
30318arm_force_relocation (struct fix * fixp)
30319{
30320#if defined (OBJ_COFF) && defined (TE_PE)
30321 if (fixp->fx_r_type == BFD_RELOC_RVA)
30322 return 1;
30323#endif
6c43fab6 30324
267bf995
RR		 30325 /* In case we have a call or a branch to a function in ARM ISA mode from
30326 a thumb function or vice-versa force the relocation. These relocations
30327 are cleared off for some cores that might have blx and simple transformations
30328 are possible. */
30329
30330#ifdef OBJ_ELF
30331 switch (fixp->fx_r_type)
30332 {
30333 case BFD_RELOC_ARM_PCREL_JUMP:
30334 case BFD_RELOC_ARM_PCREL_CALL:
30335 case BFD_RELOC_THUMB_PCREL_BLX:
30336 if (THUMB_IS_FUNC (fixp->fx_addsy))
30337 return 1;
30338 break;
30339
30340 case BFD_RELOC_ARM_PCREL_BLX:
30341 case BFD_RELOC_THUMB_PCREL_BRANCH25:
30342 case BFD_RELOC_THUMB_PCREL_BRANCH20:
30343 case BFD_RELOC_THUMB_PCREL_BRANCH23:
30344 if (ARM_IS_FUNC (fixp->fx_addsy))
30345 return 1;
30346 break;
30347
30348 default:
30349 break;
30350 }
30351#endif
30352
b5884301
PB		 30353 /* Resolve these relocations even if the symbol is extern or weak.
30354 Technically this is probably wrong due to symbol preemption.
30355 In practice these relocations do not have enough range to be useful
30356 at dynamic link time, and some code (e.g. in the Linux kernel)
30357 expects these references to be resolved. */
c19d1205
ZW		 30358 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
30359 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
b5884301 30360 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
0110f2b8 30361 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
b5884301
PB		 30362 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
30363 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
30364 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
16805f35 30365 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
0110f2b8
PB		 30366 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
30367 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
b5884301
PB		 30368 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
30369 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
30370 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
30371 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
c19d1205 30372 return 0;
a737bd4d 30373
4962c51a
MS		 30374 /* Always leave these relocations for the linker. */
30375 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
30376 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
30377 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
30378 return 1;
30379
f0291e4c
PB		 30380 /* Always generate relocations against function symbols. */
30381 if (fixp->fx_r_type == BFD_RELOC_32
30382 && fixp->fx_addsy
30383 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
30384 return 1;
30385
c19d1205 30386 return generic_force_reloc (fixp);
404ff6b5
AH		 30387}
30388
0ffdc86c 30389#if defined (OBJ_ELF) || defined (OBJ_COFF)
e28387c3
PB		 30390/* Relocations against function names must be left unadjusted,
30391 so that the linker can use this information to generate interworking
30392 stubs. The MIPS version of this function
c19d1205
ZW		 30393 also prevents relocations that are mips-16 specific, but I do not
30394 know why it does this.
404ff6b5 30395
c19d1205
ZW		 30396 FIXME:
30397 There is one other problem that ought to be addressed here, but
30398 which currently is not: Taking the address of a label (rather
30399 than a function) and then later jumping to that address. Such
30400 addresses also ought to have their bottom bit set (assuming that
30401 they reside in Thumb code), but at the moment they will not. */
404ff6b5 30402
c19d1205
ZW		 30403bfd_boolean
30404arm_fix_adjustable (fixS * fixP)
404ff6b5 30405{
c19d1205
ZW		 30406 if (fixP->fx_addsy == NULL)
30407 return 1;
404ff6b5 30408
e28387c3
PB		 30409 /* Preserve relocations against symbols with function type. */
30410 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
c921be7d 30411 return FALSE;
e28387c3 30412
c19d1205
ZW		 30413 if (THUMB_IS_FUNC (fixP->fx_addsy)
30414 && fixP->fx_subsy == NULL)
c921be7d 30415 return FALSE;
a737bd4d 30416
c19d1205
ZW		 30417 /* We need the symbol name for the VTABLE entries. */
30418 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
30419 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
c921be7d 30420 return FALSE;
404ff6b5 30421
c19d1205
ZW		 30422 /* Don't allow symbols to be discarded on GOT related relocs. */
30423 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
30424 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
30425 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
30426 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
5c5a4843 30427 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32_FDPIC
c19d1205
ZW		 30428 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
30429 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
5c5a4843 30430 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32_FDPIC
c19d1205 30431 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
5c5a4843 30432 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32_FDPIC
c19d1205 30433 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
0855e32b
NS		 30434 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
30435 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
30436 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
30437 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
30438 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
c19d1205 30439 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
c921be7d 30440 return FALSE;
a737bd4d 30441
4962c51a
MS		 30442 /* Similarly for group relocations. */
30443 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
30444 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
30445 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
c921be7d 30446 return FALSE;
4962c51a 30447
79947c54
CD		 30448 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
30449 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
30450 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
30451 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
30452 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
30453 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
30454 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
30455 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
30456 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
c921be7d 30457 return FALSE;
79947c54 30458
72d98d16
MG		 30459 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
30460 offsets, so keep these symbols. */
30461 if (fixP->fx_r_type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
30462 && fixP->fx_r_type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
30463 return FALSE;
30464
c921be7d 30465 return TRUE;
a737bd4d 30466}
0ffdc86c
NC		 30467#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
30468
30469#ifdef OBJ_ELF
c19d1205
ZW		 30470const char *
30471elf32_arm_target_format (void)
404ff6b5 30472{
c19d1205
ZW		 30473#ifdef TE_SYMBIAN
30474 return (target_big_endian
30475 ? "elf32-bigarm-symbian"
30476 : "elf32-littlearm-symbian");
30477#elif defined (TE_VXWORKS)
30478 return (target_big_endian
30479 ? "elf32-bigarm-vxworks"
30480 : "elf32-littlearm-vxworks");
b38cadfb
NC		 30481#elif defined (TE_NACL)
30482 return (target_big_endian
30483 ? "elf32-bigarm-nacl"
30484 : "elf32-littlearm-nacl");
c19d1205 30485#else
18a20338
CL		 30486 if (arm_fdpic)
30487 {
30488 if (target_big_endian)
30489 return "elf32-bigarm-fdpic";
30490 else
30491 return "elf32-littlearm-fdpic";
30492 }
c19d1205 30493 else
18a20338
CL		 30494 {
30495 if (target_big_endian)
30496 return "elf32-bigarm";
30497 else
30498 return "elf32-littlearm";
30499 }
c19d1205 30500#endif
404ff6b5
AH		 30501}
30502
c19d1205
ZW		 30503void
30504armelf_frob_symbol (symbolS * symp,
30505 int * puntp)
404ff6b5 30506{
c19d1205
ZW		 30507 elf_frob_symbol (symp, puntp);
30508}
30509#endif
404ff6b5 30510
c19d1205 30511/* MD interface: Finalization. */
a737bd4d 30512
c19d1205
ZW		 30513void
30514arm_cleanup (void)
30515{
30516 literal_pool * pool;
a737bd4d 30517
5ee91343
AV		 30518 /* Ensure that all the predication blocks are properly closed. */
30519 check_pred_blocks_finished ();
e07e6e58 30520
c19d1205
ZW		 30521 for (pool = list_of_pools; pool; pool = pool->next)
30522 {
5f4273c7 30523 /* Put it at the end of the relevant section. */
c19d1205
ZW		 30524 subseg_set (pool->section, pool->sub_section);
30525#ifdef OBJ_ELF
30526 arm_elf_change_section ();
30527#endif
30528 s_ltorg (0);
30529 }
404ff6b5
AH		 30530}
30531
cd000bff
DJ		 30532#ifdef OBJ_ELF
30533/* Remove any excess mapping symbols generated for alignment frags in
30534 SEC. We may have created a mapping symbol before a zero byte
30535 alignment; remove it if there's a mapping symbol after the
30536 alignment. */
30537static void
30538check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
30539 void *dummy ATTRIBUTE_UNUSED)
30540{
30541 segment_info_type *seginfo = seg_info (sec);
30542 fragS *fragp;
30543
30544 if (seginfo == NULL || seginfo->frchainP == NULL)
30545 return;
30546
30547 for (fragp = seginfo->frchainP->frch_root;
30548 fragp != NULL;
30549 fragp = fragp->fr_next)
30550 {
30551 symbolS *sym = fragp->tc_frag_data.last_map;
30552 fragS *next = fragp->fr_next;
30553
30554 /* Variable-sized frags have been converted to fixed size by
30555 this point. But if this was variable-sized to start with,
30556 there will be a fixed-size frag after it. So don't handle
30557 next == NULL. */
30558 if (sym == NULL || next == NULL)
30559 continue;
30560
30561 if (S_GET_VALUE (sym) < next->fr_address)
30562 /* Not at the end of this frag. */
30563 continue;
30564 know (S_GET_VALUE (sym) == next->fr_address);
30565
30566 do
30567 {
30568 if (next->tc_frag_data.first_map != NULL)
30569 {
30570 /* Next frag starts with a mapping symbol. Discard this
30571 one. */
30572 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
30573 break;
30574 }
30575
30576 if (next->fr_next == NULL)
30577 {
30578 /* This mapping symbol is at the end of the section. Discard
30579 it. */
30580 know (next->fr_fix == 0 && next->fr_var == 0);
30581 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
30582 break;
30583 }
30584
30585 /* As long as we have empty frags without any mapping symbols,
30586 keep looking. */
30587 /* If the next frag is non-empty and does not start with a
30588 mapping symbol, then this mapping symbol is required. */
30589 if (next->fr_address != next->fr_next->fr_address)
30590 break;
30591
30592 next = next->fr_next;
30593 }
30594 while (next != NULL);
30595 }
30596}
30597#endif
30598
c19d1205
ZW		 30599/* Adjust the symbol table. This marks Thumb symbols as distinct from
30600 ARM ones. */
404ff6b5 30601
c19d1205
ZW		 30602void
30603arm_adjust_symtab (void)
404ff6b5 30604{
c19d1205
ZW		 30605#ifdef OBJ_COFF
30606 symbolS * sym;
404ff6b5 30607
c19d1205
ZW		 30608 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
30609 {
30610 if (ARM_IS_THUMB (sym))
30611 {
30612 if (THUMB_IS_FUNC (sym))
30613 {
30614 /* Mark the symbol as a Thumb function. */
30615 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
30616 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
30617 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
404ff6b5 30618
c19d1205
ZW		 30619 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
30620 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
30621 else
30622 as_bad (_("%s: unexpected function type: %d"),
30623 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
30624 }
30625 else switch (S_GET_STORAGE_CLASS (sym))
30626 {
30627 case C_EXT:
30628 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
30629 break;
30630 case C_STAT:
30631 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
30632 break;
30633 case C_LABEL:
30634 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
30635 break;
30636 default:
30637 /* Do nothing. */
30638 break;
30639 }
30640 }
a737bd4d 30641
c19d1205
ZW		 30642 if (ARM_IS_INTERWORK (sym))
30643 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
404ff6b5 30644 }
c19d1205
ZW		 30645#endif
30646#ifdef OBJ_ELF
30647 symbolS * sym;
30648 char bind;
404ff6b5 30649
c19d1205 30650 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
404ff6b5 30651 {
c19d1205
ZW		 30652 if (ARM_IS_THUMB (sym))
30653 {
30654 elf_symbol_type * elf_sym;
404ff6b5 30655
c19d1205
ZW		 30656 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
30657 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
404ff6b5 30658
b0796911
PB		 30659 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
30660 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
c19d1205
ZW		 30661 {
30662 /* If it's a .thumb_func, declare it as so,
30663 otherwise tag label as .code 16. */
30664 if (THUMB_IS_FUNC (sym))
39d911fc
TP		 30665 ARM_SET_SYM_BRANCH_TYPE (elf_sym->internal_elf_sym.st_target_internal,
30666 ST_BRANCH_TO_THUMB);
3ba67470 30667 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
c19d1205
ZW		 30668 elf_sym->internal_elf_sym.st_info =
30669 ELF_ST_INFO (bind, STT_ARM_16BIT);
30670 }
30671 }
30672 }
cd000bff
DJ		 30673
30674 /* Remove any overlapping mapping symbols generated by alignment frags. */
30675 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
709001e9
MM		 30676 /* Now do generic ELF adjustments. */
30677 elf_adjust_symtab ();
c19d1205 30678#endif
404ff6b5
AH		 30679}
30680
c19d1205 30681/* MD interface: Initialization. */
404ff6b5 30682
a737bd4d 30683static void
c19d1205 30684set_constant_flonums (void)
a737bd4d 30685{
c19d1205 30686 int i;
404ff6b5 30687
c19d1205
ZW		 30688 for (i = 0; i < NUM_FLOAT_VALS; i++)
30689 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
30690 abort ();
a737bd4d 30691}
404ff6b5 30692
3e9e4fcf
JB		 30693/* Auto-select Thumb mode if it's the only available instruction set for the
30694 given architecture. */
30695
30696static void
30697autoselect_thumb_from_cpu_variant (void)
30698{
30699 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
30700 opcode_select (16);
30701}
30702
c19d1205
ZW		 30703void
30704md_begin (void)
a737bd4d 30705{
c19d1205
ZW		 30706 unsigned mach;
30707 unsigned int i;
404ff6b5 30708
c19d1205
ZW		 30709 if ( (arm_ops_hsh = hash_new ()) == NULL
30710 || (arm_cond_hsh = hash_new ()) == NULL
5ee91343 30711 || (arm_vcond_hsh = hash_new ()) == NULL
c19d1205
ZW		 30712 || (arm_shift_hsh = hash_new ()) == NULL
30713 || (arm_psr_hsh = hash_new ()) == NULL
62b3e311 30714 || (arm_v7m_psr_hsh = hash_new ()) == NULL
c19d1205 30715 || (arm_reg_hsh = hash_new ()) == NULL
62b3e311
PB		 30716 || (arm_reloc_hsh = hash_new ()) == NULL
30717 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
c19d1205
ZW		 30718 as_fatal (_("virtual memory exhausted"));
30719
30720 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
d3ce72d0 30721 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
c19d1205 30722 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
d3ce72d0 30723 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
5ee91343
AV		 30724 for (i = 0; i < sizeof (vconds) / sizeof (struct asm_cond); i++)
30725 hash_insert (arm_vcond_hsh, vconds[i].template_name, (void *) (vconds + i));
c19d1205 30726 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
5a49b8ac 30727 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
c19d1205 30728 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
d3ce72d0 30729 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
62b3e311 30730 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
d3ce72d0 30731 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
477330fc 30732 (void *) (v7m_psrs + i));
c19d1205 30733 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
5a49b8ac 30734 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
62b3e311
PB		 30735 for (i = 0;
30736 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
30737 i++)
d3ce72d0 30738 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
5a49b8ac 30739 (void *) (barrier_opt_names + i));
c19d1205 30740#ifdef OBJ_ELF
3da1d841
NC		 30741 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
30742 {
30743 struct reloc_entry * entry = reloc_names + i;
30744
30745 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
30746 /* This makes encode_branch() use the EABI versions of this relocation. */
30747 entry->reloc = BFD_RELOC_UNUSED;
30748
30749 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
30750 }
c19d1205
ZW		 30751#endif
30752
30753 set_constant_flonums ();
404ff6b5 30754
c19d1205
ZW		 30755 /* Set the cpu variant based on the command-line options. We prefer
30756 -mcpu= over -march= if both are set (as for GCC); and we prefer
30757 -mfpu= over any other way of setting the floating point unit.
30758 Use of legacy options with new options are faulted. */
e74cfd16 30759 if (legacy_cpu)
404ff6b5 30760 {
e74cfd16 30761 if (mcpu_cpu_opt || march_cpu_opt)
c19d1205
ZW		 30762 as_bad (_("use of old and new-style options to set CPU type"));
30763
4d354d8b 30764 selected_arch = *legacy_cpu;
404ff6b5 30765 }
4d354d8b
TP		 30766 else if (mcpu_cpu_opt)
30767 {
30768 selected_arch = *mcpu_cpu_opt;
30769 selected_ext = *mcpu_ext_opt;
30770 }
30771 else if (march_cpu_opt)
c168ce07 30772 {
4d354d8b
TP		 30773 selected_arch = *march_cpu_opt;
30774 selected_ext = *march_ext_opt;
c168ce07 30775 }
4d354d8b 30776 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
404ff6b5 30777
e74cfd16 30778 if (legacy_fpu)
c19d1205 30779 {
e74cfd16 30780 if (mfpu_opt)
c19d1205 30781 as_bad (_("use of old and new-style options to set FPU type"));
03b1477f 30782
4d354d8b 30783 selected_fpu = *legacy_fpu;
03b1477f 30784 }
4d354d8b
TP		 30785 else if (mfpu_opt)
30786 selected_fpu = *mfpu_opt;
30787 else
03b1477f 30788 {
45eb4c1b
NS		 30789#if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
30790 || defined (TE_NetBSD) || defined (TE_VXWORKS))
39c2da32
RE		 30791 /* Some environments specify a default FPU. If they don't, infer it
30792 from the processor. */
e74cfd16 30793 if (mcpu_fpu_opt)
4d354d8b 30794 selected_fpu = *mcpu_fpu_opt;
e7da50fa 30795 else if (march_fpu_opt)
4d354d8b 30796 selected_fpu = *march_fpu_opt;
39c2da32 30797#else
4d354d8b 30798 selected_fpu = fpu_default;
39c2da32 30799#endif
03b1477f
RE		 30800 }
30801
4d354d8b 30802 if (ARM_FEATURE_ZERO (selected_fpu))
03b1477f 30803 {
4d354d8b
TP		 30804 if (!no_cpu_selected ())
30805 selected_fpu = fpu_default;
03b1477f 30806 else
4d354d8b 30807 selected_fpu = fpu_arch_fpa;
03b1477f
RE		 30808 }
30809
ee065d83 30810#ifdef CPU_DEFAULT
4d354d8b 30811 if (ARM_FEATURE_ZERO (selected_arch))
ee065d83 30812 {
4d354d8b
TP		 30813 selected_arch = cpu_default;
30814 selected_cpu = selected_arch;
ee065d83 30815 }
4d354d8b 30816 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
e74cfd16 30817#else
4d354d8b
TP		 30818 /* Autodection of feature mode: allow all features in cpu_variant but leave
30819 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
30820 after all instruction have been processed and we can decide what CPU
30821 should be selected. */
30822 if (ARM_FEATURE_ZERO (selected_arch))
30823 ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu);
ee065d83 30824 else
4d354d8b 30825 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
ee065d83 30826#endif
03b1477f 30827
3e9e4fcf
JB		 30828 autoselect_thumb_from_cpu_variant ();
30829
e74cfd16 30830 arm_arch_used = thumb_arch_used = arm_arch_none;
ee065d83 30831
f17c130b 30832#if defined OBJ_COFF || defined OBJ_ELF
b99bd4ef 30833 {
7cc69913
NC		 30834 unsigned int flags = 0;
30835
30836#if defined OBJ_ELF
30837 flags = meabi_flags;
d507cf36
PB		 30838
30839 switch (meabi_flags)
33a392fb 30840 {
d507cf36 30841 case EF_ARM_EABI_UNKNOWN:
7cc69913 30842#endif
d507cf36
PB		 30843 /* Set the flags in the private structure. */
30844 if (uses_apcs_26) flags |= F_APCS26;
30845 if (support_interwork) flags |= F_INTERWORK;
30846 if (uses_apcs_float) flags |= F_APCS_FLOAT;
c19d1205 30847 if (pic_code) flags |= F_PIC;
e74cfd16 30848 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
7cc69913
NC		 30849 flags |= F_SOFT_FLOAT;
30850
d507cf36
PB		 30851 switch (mfloat_abi_opt)
30852 {
30853 case ARM_FLOAT_ABI_SOFT:
30854 case ARM_FLOAT_ABI_SOFTFP:
30855 flags |= F_SOFT_FLOAT;
30856 break;
33a392fb 30857
d507cf36
PB		 30858 case ARM_FLOAT_ABI_HARD:
30859 if (flags & F_SOFT_FLOAT)
30860 as_bad (_("hard-float conflicts with specified fpu"));
30861 break;
30862 }
03b1477f 30863
e74cfd16
PB		 30864 /* Using pure-endian doubles (even if soft-float). */
30865 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
7cc69913 30866 flags |= F_VFP_FLOAT;
f17c130b 30867
fde78edd 30868#if defined OBJ_ELF
e74cfd16 30869 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
d507cf36 30870 flags |= EF_ARM_MAVERICK_FLOAT;
d507cf36
PB		 30871 break;
30872
8cb51566 30873 case EF_ARM_EABI_VER4:
3a4a14e9 30874 case EF_ARM_EABI_VER5:
c19d1205 30875 /* No additional flags to set. */
d507cf36
PB		 30876 break;
30877
30878 default:
30879 abort ();
30880 }
7cc69913 30881#endif
b99bd4ef
NC		 30882 bfd_set_private_flags (stdoutput, flags);
30883
30884 /* We have run out flags in the COFF header to encode the
30885 status of ATPCS support, so instead we create a dummy,
c19d1205 30886 empty, debug section called .arm.atpcs. */
b99bd4ef
NC		 30887 if (atpcs)
30888 {
30889 asection * sec;
30890
30891 sec = bfd_make_section (stdoutput, ".arm.atpcs");
30892
30893 if (sec != NULL)
30894 {
fd361982
AM		 30895 bfd_set_section_flags (sec, SEC_READONLY | SEC_DEBUGGING);
30896 bfd_set_section_size (sec, 0);
b99bd4ef
NC		 30897 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
30898 }
30899 }
7cc69913 30900 }
f17c130b 30901#endif
b99bd4ef
NC		 30902
30903 /* Record the CPU type as well. */
2d447fca
JM		 30904 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
30905 mach = bfd_mach_arm_iWMMXt2;
30906 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
e16bb312 30907 mach = bfd_mach_arm_iWMMXt;
e74cfd16 30908 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
b99bd4ef 30909 mach = bfd_mach_arm_XScale;
e74cfd16 30910 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
fde78edd 30911 mach = bfd_mach_arm_ep9312;
e74cfd16 30912 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
b99bd4ef 30913 mach = bfd_mach_arm_5TE;
e74cfd16 30914 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
b99bd4ef 30915 {
e74cfd16 30916 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
b99bd4ef
NC		 30917 mach = bfd_mach_arm_5T;
30918 else
30919 mach = bfd_mach_arm_5;
30920 }
e74cfd16 30921 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
b99bd4ef 30922 {
e74cfd16 30923 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
b99bd4ef
NC		 30924 mach = bfd_mach_arm_4T;
30925 else
30926 mach = bfd_mach_arm_4;
30927 }
e74cfd16 30928 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
b99bd4ef 30929 mach = bfd_mach_arm_3M;
e74cfd16
PB		 30930 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
30931 mach = bfd_mach_arm_3;
30932 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
30933 mach = bfd_mach_arm_2a;
30934 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
30935 mach = bfd_mach_arm_2;
30936 else
30937 mach = bfd_mach_arm_unknown;
b99bd4ef
NC		 30938
30939 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
30940}
30941
c19d1205 30942/* Command line processing. */
b99bd4ef 30943
c19d1205
ZW		 30944/* md_parse_option
30945 Invocation line includes a switch not recognized by the base assembler.
30946 See if it's a processor-specific option.
b99bd4ef 30947
c19d1205
ZW		 30948 This routine is somewhat complicated by the need for backwards
30949 compatibility (since older releases of gcc can't be changed).
30950 The new options try to make the interface as compatible as
30951 possible with GCC.
b99bd4ef 30952
c19d1205 30953 New options (supported) are:
b99bd4ef 30954
c19d1205
ZW		 30955 -mcpu=<cpu name> Assemble for selected processor
30956 -march=<architecture name> Assemble for selected architecture
30957 -mfpu=<fpu architecture> Assemble for selected FPU.
30958 -EB/-mbig-endian Big-endian
30959 -EL/-mlittle-endian Little-endian
30960 -k Generate PIC code
30961 -mthumb Start in Thumb mode
30962 -mthumb-interwork Code supports ARM/Thumb interworking
b99bd4ef 30963
278df34e 30964 -m[no-]warn-deprecated Warn about deprecated features
8b2d793c 30965 -m[no-]warn-syms Warn when symbols match instructions
267bf995 30966
c19d1205 30967 For now we will also provide support for:
b99bd4ef 30968
c19d1205
ZW		 30969 -mapcs-32 32-bit Program counter
30970 -mapcs-26 26-bit Program counter
30971 -macps-float Floats passed in FP registers
30972 -mapcs-reentrant Reentrant code
30973 -matpcs
30974 (sometime these will probably be replaced with -mapcs=<list of options>
30975 and -matpcs=<list of options>)
b99bd4ef 30976
c19d1205
ZW		 30977 The remaining options are only supported for back-wards compatibility.
30978 Cpu variants, the arm part is optional:
30979 -m[arm]1 Currently not supported.
30980 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
30981 -m[arm]3 Arm 3 processor
30982 -m[arm]6[xx], Arm 6 processors
30983 -m[arm]7[xx][t][[d]m] Arm 7 processors
30984 -m[arm]8[10] Arm 8 processors
30985 -m[arm]9[20][tdmi] Arm 9 processors
30986 -mstrongarm[110[0]] StrongARM processors
30987 -mxscale XScale processors
30988 -m[arm]v[2345[t[e]]] Arm architectures
30989 -mall All (except the ARM1)
30990 FP variants:
30991 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
30992 -mfpe-old (No float load/store multiples)
30993 -mvfpxd VFP Single precision
30994 -mvfp All VFP
30995 -mno-fpu Disable all floating point instructions
b99bd4ef 30996
c19d1205
ZW		 30997 The following CPU names are recognized:
30998 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
30999 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
31000 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
31001 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
31002 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
31003 arm10t arm10e, arm1020t, arm1020e, arm10200e,
31004 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
b99bd4ef 31005
c19d1205 31006 */
b99bd4ef 31007
c19d1205 31008const char * md_shortopts = "m:k";
b99bd4ef 31009
c19d1205
ZW		 31010#ifdef ARM_BI_ENDIAN
31011#define OPTION_EB (OPTION_MD_BASE + 0)
31012#define OPTION_EL (OPTION_MD_BASE + 1)
b99bd4ef 31013#else
c19d1205
ZW		 31014#if TARGET_BYTES_BIG_ENDIAN
31015#define OPTION_EB (OPTION_MD_BASE + 0)
b99bd4ef 31016#else
c19d1205
ZW		 31017#define OPTION_EL (OPTION_MD_BASE + 1)
31018#endif
b99bd4ef 31019#endif
845b51d6 31020#define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
18a20338 31021#define OPTION_FDPIC (OPTION_MD_BASE + 3)
b99bd4ef 31022
c19d1205 31023struct option md_longopts[] =
b99bd4ef 31024{
c19d1205
ZW		 31025#ifdef OPTION_EB
31026 {"EB", no_argument, NULL, OPTION_EB},
31027#endif
31028#ifdef OPTION_EL
31029 {"EL", no_argument, NULL, OPTION_EL},
b99bd4ef 31030#endif
845b51d6 31031 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
18a20338
CL		 31032#ifdef OBJ_ELF
31033 {"fdpic", no_argument, NULL, OPTION_FDPIC},
31034#endif
c19d1205
ZW		 31035 {NULL, no_argument, NULL, 0}
31036};
b99bd4ef 31037
c19d1205 31038size_t md_longopts_size = sizeof (md_longopts);
b99bd4ef 31039
c19d1205 31040struct arm_option_table
b99bd4ef 31041{
0198d5e6
TC		 31042 const char * option; /* Option name to match. */
31043 const char * help; /* Help information. */
31044 int * var; /* Variable to change. */
31045 int value; /* What to change it to. */
31046 const char * deprecated; /* If non-null, print this message. */
c19d1205 31047};
b99bd4ef 31048
c19d1205
ZW		 31049struct arm_option_table arm_opts[] =
31050{
31051 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
31052 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
31053 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
31054 &support_interwork, 1, NULL},
31055 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
31056 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
31057 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
31058 1, NULL},
31059 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
31060 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
31061 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
31062 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
31063 NULL},
b99bd4ef 31064
c19d1205
ZW		 31065 /* These are recognized by the assembler, but have no affect on code. */
31066 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
31067 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
278df34e
NS		 31068
31069 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
31070 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
31071 &warn_on_deprecated, 0, NULL},
24f19ccb
AV		 31072
31073 {"mwarn-restrict-it", N_("warn about performance deprecated IT instructions"
31074 " in ARMv8-A and ARMv8-R"), &warn_on_restrict_it, 1, NULL},
31075 {"mno-warn-restrict-it", NULL, &warn_on_restrict_it, 0, NULL},
31076
8b2d793c
NC		 31077 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms), TRUE, NULL},
31078 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms), FALSE, NULL},
e74cfd16
PB		 31079 {NULL, NULL, NULL, 0, NULL}
31080};
31081
31082struct arm_legacy_option_table
31083{
0198d5e6
TC		 31084 const char * option; /* Option name to match. */
31085 const arm_feature_set ** var; /* Variable to change. */
31086 const arm_feature_set value; /* What to change it to. */
31087 const char * deprecated; /* If non-null, print this message. */
e74cfd16 31088};
b99bd4ef 31089
e74cfd16
PB		 31090const struct arm_legacy_option_table arm_legacy_opts[] =
31091{
c19d1205
ZW		 31092 /* DON'T add any new processors to this list -- we want the whole list
31093 to go away... Add them to the processors table instead. */
e74cfd16
PB		 31094 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
31095 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
31096 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
31097 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
31098 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
31099 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
31100 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
31101 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
31102 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
31103 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
31104 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
31105 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
31106 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
31107 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
31108 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
31109 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
31110 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
31111 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
31112 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
31113 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
31114 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
31115 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
31116 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
31117 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
31118 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
31119 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
31120 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
31121 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
31122 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
31123 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
31124 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
31125 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
31126 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
31127 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
31128 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
31129 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
31130 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
31131 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
31132 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
31133 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
31134 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
31135 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
31136 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
31137 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
31138 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
31139 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
31140 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
31141 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
31142 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
31143 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
31144 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
31145 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
31146 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
31147 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
31148 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
31149 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
31150 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
31151 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
31152 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
31153 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
31154 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
31155 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
31156 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
31157 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
31158 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
31159 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
31160 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
31161 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
31162 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
31163 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
c19d1205 31164 N_("use -mcpu=strongarm110")},
e74cfd16 31165 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
c19d1205 31166 N_("use -mcpu=strongarm1100")},
e74cfd16 31167 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
c19d1205 31168 N_("use -mcpu=strongarm1110")},
e74cfd16
PB		 31169 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
31170 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
31171 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
7ed4c4c5 31172
c19d1205 31173 /* Architecture variants -- don't add any more to this list either. */
e74cfd16
PB		 31174 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
31175 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
31176 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
31177 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
31178 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
31179 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
31180 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
31181 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
31182 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
31183 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
31184 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
31185 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
31186 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
31187 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
31188 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
31189 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
31190 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
31191 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
7ed4c4c5 31192
c19d1205 31193 /* Floating point variants -- don't add any more to this list either. */
0198d5e6
TC		 31194 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
31195 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
31196 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
31197 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
c19d1205 31198 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
7ed4c4c5 31199
e74cfd16 31200 {NULL, NULL, ARM_ARCH_NONE, NULL}
c19d1205 31201};
7ed4c4c5 31202
c19d1205 31203struct arm_cpu_option_table
7ed4c4c5 31204{
0198d5e6
TC		 31205 const char * name;
31206 size_t name_len;
31207 const arm_feature_set value;
31208 const arm_feature_set ext;
c19d1205
ZW		 31209 /* For some CPUs we assume an FPU unless the user explicitly sets
31210 -mfpu=... */
0198d5e6 31211 const arm_feature_set default_fpu;
ee065d83
PB		 31212 /* The canonical name of the CPU, or NULL to use NAME converted to upper
31213 case. */
0198d5e6 31214 const char * canonical_name;
c19d1205 31215};
7ed4c4c5 31216
c19d1205
ZW		 31217/* This list should, at a minimum, contain all the cpu names
31218 recognized by GCC. */
996b5569 31219#define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
0198d5e6 31220
e74cfd16 31221static const struct arm_cpu_option_table arm_cpus[] =
c19d1205 31222{
996b5569
TP		 31223 ARM_CPU_OPT ("all", NULL, ARM_ANY,
31224 ARM_ARCH_NONE,
31225 FPU_ARCH_FPA),
31226 ARM_CPU_OPT ("arm1", NULL, ARM_ARCH_V1,
31227 ARM_ARCH_NONE,
31228 FPU_ARCH_FPA),
31229 ARM_CPU_OPT ("arm2", NULL, ARM_ARCH_V2,
31230 ARM_ARCH_NONE,
31231 FPU_ARCH_FPA),
31232 ARM_CPU_OPT ("arm250", NULL, ARM_ARCH_V2S,
31233 ARM_ARCH_NONE,
31234 FPU_ARCH_FPA),
31235 ARM_CPU_OPT ("arm3", NULL, ARM_ARCH_V2S,
31236 ARM_ARCH_NONE,
31237 FPU_ARCH_FPA),
31238 ARM_CPU_OPT ("arm6", NULL, ARM_ARCH_V3,
31239 ARM_ARCH_NONE,
31240 FPU_ARCH_FPA),
31241 ARM_CPU_OPT ("arm60", NULL, ARM_ARCH_V3,
31242 ARM_ARCH_NONE,
31243 FPU_ARCH_FPA),
31244 ARM_CPU_OPT ("arm600", NULL, ARM_ARCH_V3,
31245 ARM_ARCH_NONE,
31246 FPU_ARCH_FPA),
31247 ARM_CPU_OPT ("arm610", NULL, ARM_ARCH_V3,
31248 ARM_ARCH_NONE,
31249 FPU_ARCH_FPA),
31250 ARM_CPU_OPT ("arm620", NULL, ARM_ARCH_V3,
31251 ARM_ARCH_NONE,
31252 FPU_ARCH_FPA),
31253 ARM_CPU_OPT ("arm7", NULL, ARM_ARCH_V3,
31254 ARM_ARCH_NONE,
31255 FPU_ARCH_FPA),
31256 ARM_CPU_OPT ("arm7m", NULL, ARM_ARCH_V3M,
31257 ARM_ARCH_NONE,
31258 FPU_ARCH_FPA),
31259 ARM_CPU_OPT ("arm7d", NULL, ARM_ARCH_V3,
31260 ARM_ARCH_NONE,
31261 FPU_ARCH_FPA),
31262 ARM_CPU_OPT ("arm7dm", NULL, ARM_ARCH_V3M,
31263 ARM_ARCH_NONE,
31264 FPU_ARCH_FPA),
31265 ARM_CPU_OPT ("arm7di", NULL, ARM_ARCH_V3,
31266 ARM_ARCH_NONE,
31267 FPU_ARCH_FPA),
31268 ARM_CPU_OPT ("arm7dmi", NULL, ARM_ARCH_V3M,
31269 ARM_ARCH_NONE,
31270 FPU_ARCH_FPA),
31271 ARM_CPU_OPT ("arm70", NULL, ARM_ARCH_V3,
31272 ARM_ARCH_NONE,
31273 FPU_ARCH_FPA),
31274 ARM_CPU_OPT ("arm700", NULL, ARM_ARCH_V3,
31275 ARM_ARCH_NONE,
31276 FPU_ARCH_FPA),
31277 ARM_CPU_OPT ("arm700i", NULL, ARM_ARCH_V3,
31278 ARM_ARCH_NONE,
31279 FPU_ARCH_FPA),
31280 ARM_CPU_OPT ("arm710", NULL, ARM_ARCH_V3,
31281 ARM_ARCH_NONE,
31282 FPU_ARCH_FPA),
31283 ARM_CPU_OPT ("arm710t", NULL, ARM_ARCH_V4T,
31284 ARM_ARCH_NONE,
31285 FPU_ARCH_FPA),
31286 ARM_CPU_OPT ("arm720", NULL, ARM_ARCH_V3,
31287 ARM_ARCH_NONE,
31288 FPU_ARCH_FPA),
31289 ARM_CPU_OPT ("arm720t", NULL, ARM_ARCH_V4T,
31290 ARM_ARCH_NONE,
31291 FPU_ARCH_FPA),
31292 ARM_CPU_OPT ("arm740t", NULL, ARM_ARCH_V4T,
31293 ARM_ARCH_NONE,
31294 FPU_ARCH_FPA),
31295 ARM_CPU_OPT ("arm710c", NULL, ARM_ARCH_V3,
31296 ARM_ARCH_NONE,
31297 FPU_ARCH_FPA),
31298 ARM_CPU_OPT ("arm7100", NULL, ARM_ARCH_V3,
31299 ARM_ARCH_NONE,
31300 FPU_ARCH_FPA),
31301 ARM_CPU_OPT ("arm7500", NULL, ARM_ARCH_V3,
31302 ARM_ARCH_NONE,
31303 FPU_ARCH_FPA),
31304 ARM_CPU_OPT ("arm7500fe", NULL, ARM_ARCH_V3,
31305 ARM_ARCH_NONE,
31306 FPU_ARCH_FPA),
31307 ARM_CPU_OPT ("arm7t", NULL, ARM_ARCH_V4T,
31308 ARM_ARCH_NONE,
31309 FPU_ARCH_FPA),
31310 ARM_CPU_OPT ("arm7tdmi", NULL, ARM_ARCH_V4T,
31311 ARM_ARCH_NONE,
31312 FPU_ARCH_FPA),
31313 ARM_CPU_OPT ("arm7tdmi-s", NULL, ARM_ARCH_V4T,
31314 ARM_ARCH_NONE,
31315 FPU_ARCH_FPA),
31316 ARM_CPU_OPT ("arm8", NULL, ARM_ARCH_V4,
31317 ARM_ARCH_NONE,
31318 FPU_ARCH_FPA),
31319 ARM_CPU_OPT ("arm810", NULL, ARM_ARCH_V4,
31320 ARM_ARCH_NONE,
31321 FPU_ARCH_FPA),
31322 ARM_CPU_OPT ("strongarm", NULL, ARM_ARCH_V4,
31323 ARM_ARCH_NONE,
31324 FPU_ARCH_FPA),
31325 ARM_CPU_OPT ("strongarm1", NULL, ARM_ARCH_V4,
31326 ARM_ARCH_NONE,
31327 FPU_ARCH_FPA),
31328 ARM_CPU_OPT ("strongarm110", NULL, ARM_ARCH_V4,
31329 ARM_ARCH_NONE,
31330 FPU_ARCH_FPA),
31331 ARM_CPU_OPT ("strongarm1100", NULL, ARM_ARCH_V4,
31332 ARM_ARCH_NONE,
31333 FPU_ARCH_FPA),
31334 ARM_CPU_OPT ("strongarm1110", NULL, ARM_ARCH_V4,
31335 ARM_ARCH_NONE,
31336 FPU_ARCH_FPA),
31337 ARM_CPU_OPT ("arm9", NULL, ARM_ARCH_V4T,
31338 ARM_ARCH_NONE,
31339 FPU_ARCH_FPA),
31340 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T,
31341 ARM_ARCH_NONE,
31342 FPU_ARCH_FPA),
31343 ARM_CPU_OPT ("arm920t", NULL, ARM_ARCH_V4T,
31344 ARM_ARCH_NONE,
31345 FPU_ARCH_FPA),
31346 ARM_CPU_OPT ("arm922t", NULL, ARM_ARCH_V4T,
31347 ARM_ARCH_NONE,
31348 FPU_ARCH_FPA),
31349 ARM_CPU_OPT ("arm940t", NULL, ARM_ARCH_V4T,
31350 ARM_ARCH_NONE,
31351 FPU_ARCH_FPA),
31352 ARM_CPU_OPT ("arm9tdmi", NULL, ARM_ARCH_V4T,
31353 ARM_ARCH_NONE,
31354 FPU_ARCH_FPA),
31355 ARM_CPU_OPT ("fa526", NULL, ARM_ARCH_V4,
31356 ARM_ARCH_NONE,
31357 FPU_ARCH_FPA),
31358 ARM_CPU_OPT ("fa626", NULL, ARM_ARCH_V4,
31359 ARM_ARCH_NONE,
31360 FPU_ARCH_FPA),
31361
c19d1205
ZW		 31362 /* For V5 or later processors we default to using VFP; but the user
31363 should really set the FPU type explicitly. */
996b5569
TP		 31364 ARM_CPU_OPT ("arm9e-r0", NULL, ARM_ARCH_V5TExP,
31365 ARM_ARCH_NONE,
31366 FPU_ARCH_VFP_V2),
31367 ARM_CPU_OPT ("arm9e", NULL, ARM_ARCH_V5TE,
31368 ARM_ARCH_NONE,
31369 FPU_ARCH_VFP_V2),
31370 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ,
31371 ARM_ARCH_NONE,
31372 FPU_ARCH_VFP_V2),
31373 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ,
31374 ARM_ARCH_NONE,
31375 FPU_ARCH_VFP_V2),
31376 ARM_CPU_OPT ("arm926ej-s", NULL, ARM_ARCH_V5TEJ,
31377 ARM_ARCH_NONE,
31378 FPU_ARCH_VFP_V2),
31379 ARM_CPU_OPT ("arm946e-r0", NULL, ARM_ARCH_V5TExP,
31380 ARM_ARCH_NONE,
31381 FPU_ARCH_VFP_V2),
31382 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE,
31383 ARM_ARCH_NONE,
31384 FPU_ARCH_VFP_V2),
31385 ARM_CPU_OPT ("arm946e-s", NULL, ARM_ARCH_V5TE,
31386 ARM_ARCH_NONE,
31387 FPU_ARCH_VFP_V2),
31388 ARM_CPU_OPT ("arm966e-r0", NULL, ARM_ARCH_V5TExP,
31389 ARM_ARCH_NONE,
31390 FPU_ARCH_VFP_V2),
31391 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE,
31392 ARM_ARCH_NONE,
31393 FPU_ARCH_VFP_V2),
31394 ARM_CPU_OPT ("arm966e-s", NULL, ARM_ARCH_V5TE,
31395 ARM_ARCH_NONE,
31396 FPU_ARCH_VFP_V2),
31397 ARM_CPU_OPT ("arm968e-s", NULL, ARM_ARCH_V5TE,
31398 ARM_ARCH_NONE,
31399 FPU_ARCH_VFP_V2),
31400 ARM_CPU_OPT ("arm10t", NULL, ARM_ARCH_V5T,
31401 ARM_ARCH_NONE,
31402 FPU_ARCH_VFP_V1),
31403 ARM_CPU_OPT ("arm10tdmi", NULL, ARM_ARCH_V5T,
31404 ARM_ARCH_NONE,
31405 FPU_ARCH_VFP_V1),
31406 ARM_CPU_OPT ("arm10e", NULL, ARM_ARCH_V5TE,
31407 ARM_ARCH_NONE,
31408 FPU_ARCH_VFP_V2),
31409 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE,
31410 ARM_ARCH_NONE,
31411 FPU_ARCH_VFP_V2),
31412 ARM_CPU_OPT ("arm1020t", NULL, ARM_ARCH_V5T,
31413 ARM_ARCH_NONE,
31414 FPU_ARCH_VFP_V1),
31415 ARM_CPU_OPT ("arm1020e", NULL, ARM_ARCH_V5TE,
31416 ARM_ARCH_NONE,
31417 FPU_ARCH_VFP_V2),
31418 ARM_CPU_OPT ("arm1022e", NULL, ARM_ARCH_V5TE,
31419 ARM_ARCH_NONE,
31420 FPU_ARCH_VFP_V2),
31421 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ,
31422 ARM_ARCH_NONE,
31423 FPU_ARCH_VFP_V2),
31424 ARM_CPU_OPT ("arm1026ej-s", NULL, ARM_ARCH_V5TEJ,
31425 ARM_ARCH_NONE,
31426 FPU_ARCH_VFP_V2),
31427 ARM_CPU_OPT ("fa606te", NULL, ARM_ARCH_V5TE,
31428 ARM_ARCH_NONE,
31429 FPU_ARCH_VFP_V2),
31430 ARM_CPU_OPT ("fa616te", NULL, ARM_ARCH_V5TE,
31431 ARM_ARCH_NONE,
31432 FPU_ARCH_VFP_V2),
31433 ARM_CPU_OPT ("fa626te", NULL, ARM_ARCH_V5TE,
31434 ARM_ARCH_NONE,
31435 FPU_ARCH_VFP_V2),
31436 ARM_CPU_OPT ("fmp626", NULL, ARM_ARCH_V5TE,
31437 ARM_ARCH_NONE,
31438 FPU_ARCH_VFP_V2),
31439 ARM_CPU_OPT ("fa726te", NULL, ARM_ARCH_V5TE,
31440 ARM_ARCH_NONE,
31441 FPU_ARCH_VFP_V2),
31442 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6,
31443 ARM_ARCH_NONE,
31444 FPU_NONE),
31445 ARM_CPU_OPT ("arm1136j-s", NULL, ARM_ARCH_V6,
31446 ARM_ARCH_NONE,
31447 FPU_NONE),
31448 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6,
31449 ARM_ARCH_NONE,
31450 FPU_ARCH_VFP_V2),
31451 ARM_CPU_OPT ("arm1136jf-s", NULL, ARM_ARCH_V6,
31452 ARM_ARCH_NONE,
31453 FPU_ARCH_VFP_V2),
31454 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K,
31455 ARM_ARCH_NONE,
31456 FPU_ARCH_VFP_V2),
31457 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K,
31458 ARM_ARCH_NONE,
31459 FPU_NONE),
31460 ARM_CPU_OPT ("arm1156t2-s", NULL, ARM_ARCH_V6T2,
31461 ARM_ARCH_NONE,
31462 FPU_NONE),
31463 ARM_CPU_OPT ("arm1156t2f-s", NULL, ARM_ARCH_V6T2,
31464 ARM_ARCH_NONE,
31465 FPU_ARCH_VFP_V2),
31466 ARM_CPU_OPT ("arm1176jz-s", NULL, ARM_ARCH_V6KZ,
31467 ARM_ARCH_NONE,
31468 FPU_NONE),
31469 ARM_CPU_OPT ("arm1176jzf-s", NULL, ARM_ARCH_V6KZ,
31470 ARM_ARCH_NONE,
31471 FPU_ARCH_VFP_V2),
31472 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A,
31473 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
31474 FPU_NONE),
31475 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE,
31476 ARM_ARCH_NONE,
31477 FPU_ARCH_NEON_VFP_V4),
31478 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A,
31479 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
31480 ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
31481 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A,
31482 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
31483 ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
31484 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE,
31485 ARM_ARCH_NONE,
31486 FPU_ARCH_NEON_VFP_V4),
31487 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE,
31488 ARM_ARCH_NONE,
31489 FPU_ARCH_NEON_VFP_V4),
31490 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE,
31491 ARM_ARCH_NONE,
31492 FPU_ARCH_NEON_VFP_V4),
31493 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A,
8b301fbb 31494 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
996b5569
TP		 31495 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
31496 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A,
8b301fbb 31497 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
996b5569
TP		 31498 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
31499 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A,
8b301fbb 31500 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
996b5569 31501 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
15a7695f
JG		 31502 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A,
31503 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0198d5e6 31504 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
996b5569 31505 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A,
8b301fbb 31506 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
996b5569
TP		 31507 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
31508 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A,
8b301fbb 31509 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
996b5569
TP		 31510 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
31511 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A,
8b301fbb 31512 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
996b5569 31513 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
15a7695f
JG		 31514 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A,
31515 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0198d5e6 31516 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
7ebd1359 31517 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A,
31518 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31519 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
0535e5d7
DZ		 31520 ARM_CPU_OPT ("cortex-a76ae", "Cortex-A76AE", ARM_ARCH_V8_2A,
31521 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31522 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
31523 ARM_CPU_OPT ("cortex-a77", "Cortex-A77", ARM_ARCH_V8_2A,
31524 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31525 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
ef8df4ca
KT		 31526 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A,
31527 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31528 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
996b5569
TP		 31529 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R,
31530 ARM_ARCH_NONE,
31531 FPU_NONE),
31532 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R,
31533 ARM_ARCH_NONE,
31534 FPU_ARCH_VFP_V3D16),
31535 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R,
31536 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
31537 FPU_NONE),
31538 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R,
31539 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
31540 FPU_ARCH_VFP_V3D16),
31541 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R,
31542 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
31543 FPU_ARCH_VFP_V3D16),
0cda1e19 31544 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R,
8b301fbb 31545 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
0cda1e19 31546 FPU_ARCH_NEON_VFP_ARMV8),
0535e5d7
DZ		 31547 ARM_CPU_OPT ("cortex-m35p", "Cortex-M35P", ARM_ARCH_V8M_MAIN,
31548 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
31549 FPU_NONE),
996b5569
TP		 31550 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN,
31551 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
31552 FPU_NONE),
31553 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE,
31554 ARM_ARCH_NONE,
31555 FPU_NONE),
31556 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM,
31557 ARM_ARCH_NONE,
31558 FPU_NONE),
31559 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM,
31560 ARM_ARCH_NONE,
31561 FPU_NONE),
31562 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M,
31563 ARM_ARCH_NONE,
31564 FPU_NONE),
31565 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM,
31566 ARM_ARCH_NONE,
31567 FPU_NONE),
31568 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM,
31569 ARM_ARCH_NONE,
31570 FPU_NONE),
31571 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM,
31572 ARM_ARCH_NONE,
31573 FPU_NONE),
31574 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A,
8b301fbb 31575 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
996b5569 31576 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
83f43c83
KT		 31577 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A,
31578 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31579 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
c19d1205 31580 /* ??? XSCALE is really an architecture. */
996b5569
TP		 31581 ARM_CPU_OPT ("xscale", NULL, ARM_ARCH_XSCALE,
31582 ARM_ARCH_NONE,
31583 FPU_ARCH_VFP_V2),
31584
c19d1205 31585 /* ??? iwmmxt is not a processor. */
996b5569
TP		 31586 ARM_CPU_OPT ("iwmmxt", NULL, ARM_ARCH_IWMMXT,
31587 ARM_ARCH_NONE,
31588 FPU_ARCH_VFP_V2),
31589 ARM_CPU_OPT ("iwmmxt2", NULL, ARM_ARCH_IWMMXT2,
31590 ARM_ARCH_NONE,
31591 FPU_ARCH_VFP_V2),
31592 ARM_CPU_OPT ("i80200", NULL, ARM_ARCH_XSCALE,
31593 ARM_ARCH_NONE,
31594 FPU_ARCH_VFP_V2),
31595
0198d5e6 31596 /* Maverick. */
996b5569
TP		 31597 ARM_CPU_OPT ("ep9312", "ARM920T",
31598 ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
31599 ARM_ARCH_NONE, FPU_ARCH_MAVERICK),
31600
da4339ed 31601 /* Marvell processors. */
996b5569
TP		 31602 ARM_CPU_OPT ("marvell-pj4", NULL, ARM_ARCH_V7A,
31603 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
31604 FPU_ARCH_VFP_V3D16),
31605 ARM_CPU_OPT ("marvell-whitney", NULL, ARM_ARCH_V7A,
31606 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
31607 FPU_ARCH_NEON_VFP_V4),
da4339ed 31608
996b5569
TP		 31609 /* APM X-Gene family. */
31610 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A,
31611 ARM_ARCH_NONE,
31612 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
31613 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A,
8b301fbb 31614 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
996b5569
TP		 31615 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
31616
31617 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
c19d1205 31618};
f3bad469 31619#undef ARM_CPU_OPT
7ed4c4c5 31620
34ef62f4
AV		 31621struct arm_ext_table
31622{
31623 const char * name;
31624 size_t name_len;
31625 const arm_feature_set merge;
31626 const arm_feature_set clear;
31627};
31628
c19d1205 31629struct arm_arch_option_table
7ed4c4c5 31630{
34ef62f4
AV		 31631 const char * name;
31632 size_t name_len;
31633 const arm_feature_set value;
31634 const arm_feature_set default_fpu;
31635 const struct arm_ext_table * ext_table;
31636};
31637
31638/* Used to add support for +E and +noE extension. */
31639#define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
31640/* Used to add support for a +E extension. */
31641#define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
31642/* Used to add support for a +noE extension. */
31643#define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
31644
31645#define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
31646 ~0 & ~FPU_ENDIAN_PURE)
31647
31648static const struct arm_ext_table armv5te_ext_table[] =
31649{
31650 ARM_EXT ("fp", FPU_ARCH_VFP_V2, ALL_FP),
31651 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31652};
31653
31654static const struct arm_ext_table armv7_ext_table[] =
31655{
31656 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
31657 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31658};
31659
31660static const struct arm_ext_table armv7ve_ext_table[] =
31661{
31662 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16, ALL_FP),
31663 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16),
31664 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3),
31665 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
31666 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16),
31667 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16), /* Alias for +fp. */
31668 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4),
31669
31670 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4,
31671 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)),
31672
31673 /* Aliases for +simd. */
31674 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4),
31675
31676 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
31677 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
31678 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16),
31679
31680 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31681};
31682
31683static const struct arm_ext_table armv7a_ext_table[] =
31684{
31685 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
31686 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp. */
31687 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3),
31688 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
31689 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16),
31690 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16),
31691 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4),
31692
31693 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1,
31694 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)),
31695
31696 /* Aliases for +simd. */
31697 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
31698 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
31699
31700 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16),
31701 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4),
31702
31703 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP)),
31704 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC)),
31705 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31706};
31707
31708static const struct arm_ext_table armv7r_ext_table[] =
31709{
31710 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD),
31711 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD), /* Alias for +fp.sp. */
31712 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
31713 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp. */
31714 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16),
31715 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
31716 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
31717 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV)),
31718 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31719};
31720
31721static const struct arm_ext_table armv7em_ext_table[] =
31722{
31723 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16, ALL_FP),
31724 /* Alias for +fp, used to be known as fpv4-sp-d16. */
31725 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16),
31726 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16),
31727 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16),
31728 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16),
31729 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31730};
31731
31732static const struct arm_ext_table armv8a_ext_table[] =
31733{
8b301fbb 31734 ARM_ADD ("crc", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC)),
34ef62f4
AV		 31735 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8),
31736 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
31737 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
31738
31739 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31740 should use the +simd option to turn on FP. */
31741 ARM_REMOVE ("fp", ALL_FP),
31742 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
31743 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
31744 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31745};
31746
31747
31748static const struct arm_ext_table armv81a_ext_table[] =
31749{
31750 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1),
31751 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
31752 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
31753
31754 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31755 should use the +simd option to turn on FP. */
31756 ARM_REMOVE ("fp", ALL_FP),
31757 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
31758 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
31759 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31760};
31761
31762static const struct arm_ext_table armv82a_ext_table[] =
31763{
31764 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1),
31765 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16),
31766 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML),
616ce08e
MM		 31767 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16)),
31768 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM)),
34ef62f4
AV		 31769 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
31770 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
31771 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
31772
31773 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31774 should use the +simd option to turn on FP. */
31775 ARM_REMOVE ("fp", ALL_FP),
31776 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
31777 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
31778 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31779};
31780
31781static const struct arm_ext_table armv84a_ext_table[] =
31782{
31783 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
31784 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML),
616ce08e
MM		 31785 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16)),
31786 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM)),
34ef62f4
AV		 31787 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4,
31788 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
31789
31790 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31791 should use the +simd option to turn on FP. */
31792 ARM_REMOVE ("fp", ALL_FP),
31793 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
31794 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
31795 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31796};
31797
31798static const struct arm_ext_table armv85a_ext_table[] =
31799{
31800 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
31801 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML),
616ce08e
MM		 31802 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16)),
31803 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM)),
34ef62f4
AV		 31804 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4,
31805 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
31806
31807 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31808 should use the +simd option to turn on FP. */
31809 ARM_REMOVE ("fp", ALL_FP),
31810 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31811};
31812
aab2c27d
MM		 31813static const struct arm_ext_table armv86a_ext_table[] =
31814{
616ce08e 31815 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM)),
aab2c27d
MM		 31816 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31817};
31818
4934a27c
MM		 31819#define CDE_EXTENSIONS \
31820 ARM_ADD ("cdecp0", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)), \
31821 ARM_ADD ("cdecp1", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)), \
31822 ARM_ADD ("cdecp2", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)), \
31823 ARM_ADD ("cdecp3", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)), \
31824 ARM_ADD ("cdecp4", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)), \
31825 ARM_ADD ("cdecp5", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)), \
31826 ARM_ADD ("cdecp6", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)), \
31827 ARM_ADD ("cdecp7", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7))
31828
34ef62f4
AV		 31829static const struct arm_ext_table armv8m_main_ext_table[] =
31830{
92169145
AV		 31831 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP),
31832 ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP)),
34ef62f4
AV		 31833 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16, ALL_FP),
31834 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16),
4934a27c 31835 CDE_EXTENSIONS,
34ef62f4
AV		 31836 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31837};
31838
92169145 31839
e0991585
AV		 31840static const struct arm_ext_table armv8_1m_main_ext_table[] =
31841{
92169145
AV		 31842 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP),
31843 ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP)),
e0991585
AV		 31844 ARM_EXT ("fp",
31845 ARM_FEATURE (0, ARM_EXT2_FP16_INST,
31846 FPU_VFP_V5_SP_D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA),
31847 ALL_FP),
31848 ARM_ADD ("fp.dp",
31849 ARM_FEATURE (0, ARM_EXT2_FP16_INST,
31850 FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)),
92169145 31851 ARM_EXT ("mve", ARM_FEATURE (ARM_AEXT_V8M_MAIN_DSP, ARM_EXT2_MVE, 0),
2da2eaf4 31852 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
a7ad558c 31853 ARM_ADD ("mve.fp",
92169145
AV		 31854 ARM_FEATURE (ARM_AEXT_V8M_MAIN_DSP,
31855 ARM_EXT2_FP16_INST | ARM_EXT2_MVE | ARM_EXT2_MVE_FP,
2da2eaf4 31856 FPU_VFP_V5_SP_D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)),
4934a27c 31857 CDE_EXTENSIONS,
e0991585
AV		 31858 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31859};
31860
4934a27c
MM		 31861#undef CDE_EXTENSIONS
31862
34ef62f4
AV		 31863static const struct arm_ext_table armv8r_ext_table[] =
31864{
8b301fbb 31865 ARM_ADD ("crc", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC)),
34ef62f4
AV		 31866 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8),
31867 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
31868 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
31869 ARM_REMOVE ("fp", ALL_FP),
31870 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16),
31871 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
c19d1205 31872};
7ed4c4c5 31873
c19d1205
ZW		 31874/* This list should, at a minimum, contain all the architecture names
31875 recognized by GCC. */
34ef62f4
AV		 31876#define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
31877#define ARM_ARCH_OPT2(N, V, DF, ext) \
31878 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
0198d5e6 31879
e74cfd16 31880static const struct arm_arch_option_table arm_archs[] =
c19d1205 31881{
497d849d
TP		 31882 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
31883 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
31884 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
31885 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
31886 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
31887 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
31888 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
31889 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
31890 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
31891 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
31892 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
31893 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
31894 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
31895 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
34ef62f4
AV		 31896 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP, armv5te),
31897 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP, armv5te),
31898 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP, armv5te),
31899 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP, armv5te),
31900 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP, armv5te),
31901 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP, armv5te),
31902 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP, armv5te),
f33026a9
MW		 31903 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
31904 kept to preserve existing behaviour. */
34ef62f4
AV		 31905 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ, FPU_ARCH_VFP, armv5te),
31906 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ, FPU_ARCH_VFP, armv5te),
31907 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP, armv5te),
31908 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP, armv5te),
31909 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP, armv5te),
f33026a9
MW		 31910 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
31911 kept to preserve existing behaviour. */
34ef62f4
AV		 31912 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP, armv5te),
31913 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP, armv5te),
497d849d
TP		 31914 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
31915 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
34ef62f4 31916 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP, armv7),
c450d570
PB		 31917 /* The official spelling of the ARMv7 profile variants is the dashed form.
31918 Accept the non-dashed form for compatibility with old toolchains. */
34ef62f4
AV		 31919 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP, armv7a),
31920 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE, FPU_ARCH_VFP, armv7ve),
31921 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP, armv7r),
497d849d 31922 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
34ef62f4
AV		 31923 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP, armv7a),
31924 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP, armv7r),
497d849d 31925 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
34ef62f4 31926 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP, armv7em),
497d849d 31927 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE, FPU_ARCH_VFP),
34ef62f4
AV		 31928 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN, FPU_ARCH_VFP,
31929 armv8m_main),
e0991585
AV		 31930 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN, FPU_ARCH_VFP,
31931 armv8_1m_main),
34ef62f4
AV		 31932 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP, armv8a),
31933 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A, FPU_ARCH_VFP, armv81a),
31934 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A, FPU_ARCH_VFP, armv82a),
31935 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A, FPU_ARCH_VFP, armv82a),
31936 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R, FPU_ARCH_VFP, armv8r),
31937 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A, FPU_ARCH_VFP, armv84a),
31938 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A, FPU_ARCH_VFP, armv85a),
aab2c27d 31939 ARM_ARCH_OPT2 ("armv8.6-a", ARM_ARCH_V8_6A, FPU_ARCH_VFP, armv86a),
497d849d
TP		 31940 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
31941 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
31942 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2, FPU_ARCH_VFP),
34ef62f4 31943 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
c19d1205 31944};
f3bad469 31945#undef ARM_ARCH_OPT
7ed4c4c5 31946
69133863 31947/* ISA extensions in the co-processor and main instruction set space. */
0198d5e6 31948
69133863 31949struct arm_option_extension_value_table
c19d1205 31950{
0198d5e6
TC		 31951 const char * name;
31952 size_t name_len;
31953 const arm_feature_set merge_value;
31954 const arm_feature_set clear_value;
d942732e
TP		 31955 /* List of architectures for which an extension is available. ARM_ARCH_NONE
31956 indicates that an extension is available for all architectures while
31957 ARM_ANY marks an empty entry. */
0198d5e6 31958 const arm_feature_set allowed_archs[2];
c19d1205 31959};
7ed4c4c5 31960
0198d5e6
TC		 31961/* The following table must be in alphabetical order with a NULL last entry. */
31962
d942732e
TP		 31963#define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
31964#define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
0198d5e6 31965
34ef62f4
AV		 31966/* DEPRECATED: Refrain from using this table to add any new extensions, instead
31967 use the context sensitive approach using arm_ext_table's. */
69133863 31968static const struct arm_option_extension_value_table arm_extensions[] =
c19d1205 31969{
8b301fbb
MI		 31970 ARM_EXT_OPT ("crc", ARM_FEATURE_CORE_HIGH(ARM_EXT2_CRC),
31971 ARM_FEATURE_CORE_HIGH(ARM_EXT2_CRC),
823d2571 31972 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
bca38921 31973 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
823d2571
TG		 31974 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8),
31975 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
c604a79a
JW		 31976 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8,
31977 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
31978 ARM_ARCH_V8_2A),
15afaa63
TP		 31979 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
31980 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
31981 ARM_FEATURE_CORE (ARM_EXT_V7M, ARM_EXT2_V8M)),
823d2571
TG		 31982 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, ARM_FEATURE_COPROC (FPU_VFP_ARMV8),
31983 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
b8ec4e87
JW		 31984 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31985 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31986 ARM_ARCH_V8_2A),
01f48020
TC		 31987 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31988 | ARM_EXT2_FP16_FML),
31989 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31990 | ARM_EXT2_FP16_FML),
31991 ARM_ARCH_V8_2A),
d942732e 31992 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
823d2571 31993 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
d942732e
TP		 31994 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
31995 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)),
3d030cdb
TP		 31996 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
31997 Thumb divide instruction. Due to this having the same name as the
31998 previous entry, this will be ignored when doing command-line parsing and
31999 only considered by build attribute selection code. */
32000 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
32001 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
32002 ARM_FEATURE_CORE_LOW (ARM_EXT_V7)),
823d2571 32003 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
d942732e 32004 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), ARM_ARCH_NONE),
823d2571 32005 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2),
d942732e 32006 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), ARM_ARCH_NONE),
823d2571 32007 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
d942732e
TP		 32008 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), ARM_ARCH_NONE),
32009 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
823d2571 32010 ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
d942732e
TP		 32011 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
32012 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)),
823d2571
TG		 32013 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
32014 ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
32015 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M)),
ddfded2f
MW		 32016 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
32017 ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0),
ced40572 32018 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
dad0c3bf
SD		 32019 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES),
32020 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES),
32021 ARM_ARCH_V8A),
4d1464f2
MW		 32022 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
32023 ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_RAS, 0),
ced40572 32024 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
643afb90
MW		 32025 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1,
32026 ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA),
ced40572 32027 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
7fadb25d
SD		 32028 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB),
32029 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB),
32030 ARM_ARCH_V8A),
d942732e 32031 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
823d2571 32032 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
d942732e
TP		 32033 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
32034 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
643afb90
MW		 32035 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
32036 ARM_FEATURE_COPROC (FPU_NEON_ARMV8),
32037 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
823d2571
TG		 32038 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT | ARM_EXT_ADIV
32039 | ARM_EXT_DIV),
32040 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
32041 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
32042 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
d942732e
TP		 32043 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), ARM_ARCH_NONE),
32044 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, { ARM_ARCH_NONE, ARM_ARCH_NONE } }
69133863 32045};
f3bad469 32046#undef ARM_EXT_OPT
69133863
MGD		 32047
32048/* ISA floating-point and Advanced SIMD extensions. */
32049struct arm_option_fpu_value_table
32050{
0198d5e6
TC		 32051 const char * name;
32052 const arm_feature_set value;
c19d1205 32053};
7ed4c4c5 32054
c19d1205
ZW		 32055/* This list should, at a minimum, contain all the fpu names
32056 recognized by GCC. */
69133863 32057static const struct arm_option_fpu_value_table arm_fpus[] =
c19d1205
ZW		 32058{
32059 {"softfpa", FPU_NONE},
32060 {"fpe", FPU_ARCH_FPE},
32061 {"fpe2", FPU_ARCH_FPE},
32062 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
32063 {"fpa", FPU_ARCH_FPA},
32064 {"fpa10", FPU_ARCH_FPA},
32065 {"fpa11", FPU_ARCH_FPA},
32066 {"arm7500fe", FPU_ARCH_FPA},
32067 {"softvfp", FPU_ARCH_VFP},
32068 {"softvfp+vfp", FPU_ARCH_VFP_V2},
32069 {"vfp", FPU_ARCH_VFP_V2},
32070 {"vfp9", FPU_ARCH_VFP_V2},
d5e0ba9c 32071 {"vfp3", FPU_ARCH_VFP_V3}, /* Undocumented, use vfpv3. */
c19d1205
ZW		 32072 {"vfp10", FPU_ARCH_VFP_V2},
32073 {"vfp10-r0", FPU_ARCH_VFP_V1},
32074 {"vfpxd", FPU_ARCH_VFP_V1xD},
b1cc4aeb
PB		 32075 {"vfpv2", FPU_ARCH_VFP_V2},
32076 {"vfpv3", FPU_ARCH_VFP_V3},
62f3b8c8 32077 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
b1cc4aeb 32078 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
62f3b8c8
PB		 32079 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
32080 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
32081 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
c19d1205
ZW		 32082 {"arm1020t", FPU_ARCH_VFP_V1},
32083 {"arm1020e", FPU_ARCH_VFP_V2},
d5e0ba9c 32084 {"arm1136jfs", FPU_ARCH_VFP_V2}, /* Undocumented, use arm1136jf-s. */
c19d1205
ZW		 32085 {"arm1136jf-s", FPU_ARCH_VFP_V2},
32086 {"maverick", FPU_ARCH_MAVERICK},
d5e0ba9c 32087 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
d3375ddd 32088 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
8e79c3df 32089 {"neon-fp16", FPU_ARCH_NEON_FP16},
62f3b8c8
PB		 32090 {"vfpv4", FPU_ARCH_VFP_V4},
32091 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
ada65aa3 32092 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
a715796b
TG		 32093 {"fpv5-d16", FPU_ARCH_VFP_V5D16},
32094 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16},
62f3b8c8 32095 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
bca38921
MGD		 32096 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
32097 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
32098 {"crypto-neon-fp-armv8",
32099 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
d6b4b13e 32100 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1},
081e4c7d
MW		 32101 {"crypto-neon-fp-armv8.1",
32102 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1},
e74cfd16
PB		 32103 {NULL, ARM_ARCH_NONE}
32104};
32105
32106struct arm_option_value_table
32107{
e0471c16 32108 const char *name;
e74cfd16 32109 long value;
c19d1205 32110};
7ed4c4c5 32111
e74cfd16 32112static const struct arm_option_value_table arm_float_abis[] =
c19d1205
ZW		 32113{
32114 {"hard", ARM_FLOAT_ABI_HARD},
32115 {"softfp", ARM_FLOAT_ABI_SOFTFP},
32116 {"soft", ARM_FLOAT_ABI_SOFT},
e74cfd16 32117 {NULL, 0}
c19d1205 32118};
7ed4c4c5 32119
c19d1205 32120#ifdef OBJ_ELF
3a4a14e9 32121/* We only know how to output GNU and ver 4/5 (AAELF) formats. */
e74cfd16 32122static const struct arm_option_value_table arm_eabis[] =
c19d1205
ZW		 32123{
32124 {"gnu", EF_ARM_EABI_UNKNOWN},
32125 {"4", EF_ARM_EABI_VER4},
3a4a14e9 32126 {"5", EF_ARM_EABI_VER5},
e74cfd16 32127 {NULL, 0}
c19d1205
ZW		 32128};
32129#endif
7ed4c4c5 32130
c19d1205
ZW		 32131struct arm_long_option_table
32132{
0198d5e6 32133 const char * option; /* Substring to match. */
e0471c16 32134 const char * help; /* Help information. */
17b9d67d 32135 int (* func) (const char * subopt); /* Function to decode sub-option. */
e0471c16 32136 const char * deprecated; /* If non-null, print this message. */
c19d1205 32137};
7ed4c4c5 32138
c921be7d 32139static bfd_boolean
c168ce07 32140arm_parse_extension (const char *str, const arm_feature_set *opt_set,
34ef62f4
AV		 32141 arm_feature_set *ext_set,
32142 const struct arm_ext_table *ext_table)
7ed4c4c5 32143{
69133863 32144 /* We insist on extensions being specified in alphabetical order, and with
fa94de6b
RM		 32145 extensions being added before being removed. We achieve this by having
32146 the global ARM_EXTENSIONS table in alphabetical order, and using the
69133863 32147 ADDING_VALUE variable to indicate whether we are adding an extension (1)
fa94de6b 32148 or removing it (0) and only allowing it to change in the order
69133863
MGD		 32149 -1 -> 1 -> 0. */
32150 const struct arm_option_extension_value_table * opt = NULL;
d942732e 32151 const arm_feature_set arm_any = ARM_ANY;
69133863
MGD		 32152 int adding_value = -1;
32153
c19d1205 32154 while (str != NULL && *str != 0)
7ed4c4c5 32155 {
82b8a785 32156 const char *ext;
f3bad469 32157 size_t len;
7ed4c4c5 32158
c19d1205
ZW		 32159 if (*str != '+')
32160 {
32161 as_bad (_("invalid architectural extension"));
c921be7d 32162 return FALSE;
c19d1205 32163 }
7ed4c4c5 32164
c19d1205
ZW		 32165 str++;
32166 ext = strchr (str, '+');
7ed4c4c5 32167
c19d1205 32168 if (ext != NULL)
f3bad469 32169 len = ext - str;
c19d1205 32170 else
f3bad469 32171 len = strlen (str);
7ed4c4c5 32172
f3bad469 32173 if (len >= 2 && strncmp (str, "no", 2) == 0)
69133863
MGD		 32174 {
32175 if (adding_value != 0)
32176 {
32177 adding_value = 0;
32178 opt = arm_extensions;
32179 }
32180
f3bad469 32181 len -= 2;
69133863
MGD		 32182 str += 2;
32183 }
f3bad469 32184 else if (len > 0)
69133863
MGD		 32185 {
32186 if (adding_value == -1)
32187 {
32188 adding_value = 1;
32189 opt = arm_extensions;
32190 }
32191 else if (adding_value != 1)
32192 {
32193 as_bad (_("must specify extensions to add before specifying "
32194 "those to remove"));
32195 return FALSE;
32196 }
32197 }
32198
f3bad469 32199 if (len == 0)
c19d1205
ZW		 32200 {
32201 as_bad (_("missing architectural extension"));
c921be7d 32202 return FALSE;
c19d1205 32203 }
7ed4c4c5 32204
69133863
MGD		 32205 gas_assert (adding_value != -1);
32206 gas_assert (opt != NULL);
32207
34ef62f4
AV		 32208 if (ext_table != NULL)
32209 {
32210 const struct arm_ext_table * ext_opt = ext_table;
32211 bfd_boolean found = FALSE;
32212 for (; ext_opt->name != NULL; ext_opt++)
32213 if (ext_opt->name_len == len
32214 && strncmp (ext_opt->name, str, len) == 0)
32215 {
32216 if (adding_value)
32217 {
32218 if (ARM_FEATURE_ZERO (ext_opt->merge))
32219 /* TODO: Option not supported. When we remove the
32220 legacy table this case should error out. */
32221 continue;
32222
32223 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, ext_opt->merge);
32224 }
32225 else
32226 {
32227 if (ARM_FEATURE_ZERO (ext_opt->clear))
32228 /* TODO: Option not supported. When we remove the
32229 legacy table this case should error out. */
32230 continue;
32231 ARM_CLEAR_FEATURE (*ext_set, *ext_set, ext_opt->clear);
32232 }
32233 found = TRUE;
32234 break;
32235 }
32236 if (found)
32237 {
32238 str = ext;
32239 continue;
32240 }
32241 }
32242
69133863
MGD		 32243 /* Scan over the options table trying to find an exact match. */
32244 for (; opt->name != NULL; opt++)
f3bad469 32245 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
c19d1205 32246 {
d942732e
TP		 32247 int i, nb_allowed_archs =
32248 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]);
69133863 32249 /* Check we can apply the extension to this architecture. */
d942732e
TP		 32250 for (i = 0; i < nb_allowed_archs; i++)
32251 {
32252 /* Empty entry. */
32253 if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_any))
32254 continue;
c168ce07 32255 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *opt_set))
d942732e
TP		 32256 break;
32257 }
32258 if (i == nb_allowed_archs)
69133863
MGD		 32259 {
32260 as_bad (_("extension does not apply to the base architecture"));
32261 return FALSE;
32262 }
32263
32264 /* Add or remove the extension. */
32265 if (adding_value)
4d354d8b 32266 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->merge_value);
69133863 32267 else
4d354d8b 32268 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->clear_value);
69133863 32269
3d030cdb
TP		 32270 /* Allowing Thumb division instructions for ARMv7 in autodetection
32271 rely on this break so that duplicate extensions (extensions
32272 with the same name as a previous extension in the list) are not
32273 considered for command-line parsing. */
c19d1205
ZW		 32274 break;
32275 }
7ed4c4c5 32276
c19d1205
ZW		 32277 if (opt->name == NULL)
32278 {
69133863
MGD		 32279 /* Did we fail to find an extension because it wasn't specified in
32280 alphabetical order, or because it does not exist? */
32281
32282 for (opt = arm_extensions; opt->name != NULL; opt++)
f3bad469 32283 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
69133863
MGD		 32284 break;
32285
32286 if (opt->name == NULL)
32287 as_bad (_("unknown architectural extension `%s'"), str);
32288 else
32289 as_bad (_("architectural extensions must be specified in "
32290 "alphabetical order"));
32291
c921be7d 32292 return FALSE;
c19d1205 32293 }
69133863
MGD		 32294 else
32295 {
32296 /* We should skip the extension we've just matched the next time
32297 round. */
32298 opt++;
32299 }
7ed4c4c5 32300
c19d1205
ZW		 32301 str = ext;
32302 };
7ed4c4c5 32303
c921be7d 32304 return TRUE;
c19d1205 32305}
7ed4c4c5 32306
5312fe52
BW		 32307static bfd_boolean
32308arm_parse_fp16_opt (const char *str)
32309{
32310 if (strcasecmp (str, "ieee") == 0)
32311 fp16_format = ARM_FP16_FORMAT_IEEE;
32312 else if (strcasecmp (str, "alternative") == 0)
32313 fp16_format = ARM_FP16_FORMAT_ALTERNATIVE;
32314 else
32315 {
32316 as_bad (_("unrecognised float16 format \"%s\""), str);
32317 return FALSE;
32318 }
32319
32320 return TRUE;
32321}
32322
c921be7d 32323static bfd_boolean
17b9d67d 32324arm_parse_cpu (const char *str)
7ed4c4c5 32325{
f3bad469 32326 const struct arm_cpu_option_table *opt;
82b8a785 32327 const char *ext = strchr (str, '+');
f3bad469 32328 size_t len;
7ed4c4c5 32329
c19d1205 32330 if (ext != NULL)
f3bad469 32331 len = ext - str;
7ed4c4c5 32332 else
f3bad469 32333 len = strlen (str);
7ed4c4c5 32334
f3bad469 32335 if (len == 0)
7ed4c4c5 32336 {
c19d1205 32337 as_bad (_("missing cpu name `%s'"), str);
c921be7d 32338 return FALSE;
7ed4c4c5
NC		 32339 }
32340
c19d1205 32341 for (opt = arm_cpus; opt->name != NULL; opt++)
f3bad469 32342 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
c19d1205 32343 {
c168ce07 32344 mcpu_cpu_opt = &opt->value;
4d354d8b
TP		 32345 if (mcpu_ext_opt == NULL)
32346 mcpu_ext_opt = XNEW (arm_feature_set);
32347 *mcpu_ext_opt = opt->ext;
e74cfd16 32348 mcpu_fpu_opt = &opt->default_fpu;
ee065d83 32349 if (opt->canonical_name)
ef8e6722
JW		 32350 {
32351 gas_assert (sizeof selected_cpu_name > strlen (opt->canonical_name));
32352 strcpy (selected_cpu_name, opt->canonical_name);
32353 }
ee065d83
PB		 32354 else
32355 {
f3bad469 32356 size_t i;
c921be7d 32357
ef8e6722
JW		 32358 if (len >= sizeof selected_cpu_name)
32359 len = (sizeof selected_cpu_name) - 1;
32360
f3bad469 32361 for (i = 0; i < len; i++)
ee065d83
PB		 32362 selected_cpu_name[i] = TOUPPER (opt->name[i]);
32363 selected_cpu_name[i] = 0;
32364 }
7ed4c4c5 32365
c19d1205 32366 if (ext != NULL)
34ef62f4 32367 return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, NULL);
7ed4c4c5 32368
c921be7d 32369 return TRUE;
c19d1205 32370 }
7ed4c4c5 32371
c19d1205 32372 as_bad (_("unknown cpu `%s'"), str);
c921be7d 32373 return FALSE;
7ed4c4c5
NC		 32374}
32375
c921be7d 32376static bfd_boolean
17b9d67d 32377arm_parse_arch (const char *str)
7ed4c4c5 32378{
e74cfd16 32379 const struct arm_arch_option_table *opt;
82b8a785 32380 const char *ext = strchr (str, '+');
f3bad469 32381 size_t len;
7ed4c4c5 32382
c19d1205 32383 if (ext != NULL)
f3bad469 32384 len = ext - str;
7ed4c4c5 32385 else
f3bad469 32386 len = strlen (str);
7ed4c4c5 32387
f3bad469 32388 if (len == 0)
7ed4c4c5 32389 {
c19d1205 32390 as_bad (_("missing architecture name `%s'"), str);
c921be7d 32391 return FALSE;
7ed4c4c5
NC		 32392 }
32393
c19d1205 32394 for (opt = arm_archs; opt->name != NULL; opt++)
f3bad469 32395 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
c19d1205 32396 {
e74cfd16 32397 march_cpu_opt = &opt->value;
4d354d8b
TP		 32398 if (march_ext_opt == NULL)
32399 march_ext_opt = XNEW (arm_feature_set);
32400 *march_ext_opt = arm_arch_none;
e74cfd16 32401 march_fpu_opt = &opt->default_fpu;
e20f9590 32402 selected_ctx_ext_table = opt->ext_table;
5f4273c7 32403 strcpy (selected_cpu_name, opt->name);
7ed4c4c5 32404
c19d1205 32405 if (ext != NULL)
34ef62f4
AV		 32406 return arm_parse_extension (ext, march_cpu_opt, march_ext_opt,
32407 opt->ext_table);
7ed4c4c5 32408
c921be7d 32409 return TRUE;
c19d1205
ZW		 32410 }
32411
32412 as_bad (_("unknown architecture `%s'\n"), str);
c921be7d 32413 return FALSE;
7ed4c4c5 32414}
eb043451 32415
c921be7d 32416static bfd_boolean
17b9d67d 32417arm_parse_fpu (const char * str)
c19d1205 32418{
69133863 32419 const struct arm_option_fpu_value_table * opt;
b99bd4ef 32420
c19d1205
ZW		 32421 for (opt = arm_fpus; opt->name != NULL; opt++)
32422 if (streq (opt->name, str))
32423 {
e74cfd16 32424 mfpu_opt = &opt->value;
c921be7d 32425 return TRUE;
c19d1205 32426 }
b99bd4ef 32427
c19d1205 32428 as_bad (_("unknown floating point format `%s'\n"), str);
c921be7d 32429 return FALSE;
c19d1205
ZW		 32430}
32431
c921be7d 32432static bfd_boolean
17b9d67d 32433arm_parse_float_abi (const char * str)
b99bd4ef 32434{
e74cfd16 32435 const struct arm_option_value_table * opt;
b99bd4ef 32436
c19d1205
ZW		 32437 for (opt = arm_float_abis; opt->name != NULL; opt++)
32438 if (streq (opt->name, str))
32439 {
32440 mfloat_abi_opt = opt->value;
c921be7d 32441 return TRUE;
c19d1205 32442 }
cc8a6dd0 32443
c19d1205 32444 as_bad (_("unknown floating point abi `%s'\n"), str);
c921be7d 32445 return FALSE;
c19d1205 32446}
b99bd4ef 32447
c19d1205 32448#ifdef OBJ_ELF
c921be7d 32449static bfd_boolean
17b9d67d 32450arm_parse_eabi (const char * str)
c19d1205 32451{
e74cfd16 32452 const struct arm_option_value_table *opt;
cc8a6dd0 32453
c19d1205
ZW		 32454 for (opt = arm_eabis; opt->name != NULL; opt++)
32455 if (streq (opt->name, str))
32456 {
32457 meabi_flags = opt->value;
c921be7d 32458 return TRUE;
c19d1205
ZW		 32459 }
32460 as_bad (_("unknown EABI `%s'\n"), str);
c921be7d 32461 return FALSE;
c19d1205
ZW		 32462}
32463#endif
cc8a6dd0 32464
c921be7d 32465static bfd_boolean
17b9d67d 32466arm_parse_it_mode (const char * str)
e07e6e58 32467{
c921be7d 32468 bfd_boolean ret = TRUE;
e07e6e58
NC		 32469
32470 if (streq ("arm", str))
32471 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
32472 else if (streq ("thumb", str))
32473 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
32474 else if (streq ("always", str))
32475 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
32476 else if (streq ("never", str))
32477 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
32478 else
32479 {
32480 as_bad (_("unknown implicit IT mode `%s', should be "\
477330fc 32481 "arm, thumb, always, or never."), str);
c921be7d 32482 ret = FALSE;
e07e6e58
NC		 32483 }
32484
32485 return ret;
32486}
32487
2e6976a8 32488static bfd_boolean
17b9d67d 32489arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED)
2e6976a8
DG		 32490{
32491 codecomposer_syntax = TRUE;
32492 arm_comment_chars[0] = ';';
32493 arm_line_separator_chars[0] = 0;
32494 return TRUE;
32495}
32496
c19d1205
ZW		 32497struct arm_long_option_table arm_long_opts[] =
32498{
32499 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
32500 arm_parse_cpu, NULL},
32501 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
32502 arm_parse_arch, NULL},
32503 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
32504 arm_parse_fpu, NULL},
32505 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
32506 arm_parse_float_abi, NULL},
32507#ifdef OBJ_ELF
7fac0536 32508 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
c19d1205
ZW		 32509 arm_parse_eabi, NULL},
32510#endif
e07e6e58
NC		 32511 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
32512 arm_parse_it_mode, NULL},
2e6976a8
DG		 32513 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
32514 arm_ccs_mode, NULL},
5312fe52
BW		 32515 {"mfp16-format=",
32516 N_("[ieee|alternative]\n\
32517 set the encoding for half precision floating point "
32518 "numbers to IEEE\n\
32519 or Arm alternative format."),
32520 arm_parse_fp16_opt, NULL },
c19d1205
ZW		 32521 {NULL, NULL, 0, NULL}
32522};
cc8a6dd0 32523
c19d1205 32524int
17b9d67d 32525md_parse_option (int c, const char * arg)
c19d1205
ZW		 32526{
32527 struct arm_option_table *opt;
e74cfd16 32528 const struct arm_legacy_option_table *fopt;
c19d1205 32529 struct arm_long_option_table *lopt;
b99bd4ef 32530
c19d1205 32531 switch (c)
b99bd4ef 32532 {
c19d1205
ZW		 32533#ifdef OPTION_EB
32534 case OPTION_EB:
32535 target_big_endian = 1;
32536 break;
32537#endif
cc8a6dd0 32538
c19d1205
ZW		 32539#ifdef OPTION_EL
32540 case OPTION_EL:
32541 target_big_endian = 0;
32542 break;
32543#endif
b99bd4ef 32544
845b51d6
PB		 32545 case OPTION_FIX_V4BX:
32546 fix_v4bx = TRUE;
32547 break;
32548
18a20338
CL		 32549#ifdef OBJ_ELF
32550 case OPTION_FDPIC:
32551 arm_fdpic = TRUE;
32552 break;
32553#endif /* OBJ_ELF */
32554
c19d1205
ZW		 32555 case 'a':
32556 /* Listing option. Just ignore these, we don't support additional
32557 ones. */
32558 return 0;
b99bd4ef 32559
c19d1205
ZW		 32560 default:
32561 for (opt = arm_opts; opt->option != NULL; opt++)
32562 {
32563 if (c == opt->option[0]
32564 && ((arg == NULL && opt->option[1] == 0)
32565 || streq (arg, opt->option + 1)))
32566 {
c19d1205 32567 /* If the option is deprecated, tell the user. */
278df34e 32568 if (warn_on_deprecated && opt->deprecated != NULL)
c19d1205
ZW		 32569 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
32570 arg ? arg : "", _(opt->deprecated));
b99bd4ef 32571
c19d1205
ZW		 32572 if (opt->var != NULL)
32573 *opt->var = opt->value;
cc8a6dd0 32574
c19d1205
ZW		 32575 return 1;
32576 }
32577 }
b99bd4ef 32578
e74cfd16
PB		 32579 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
32580 {
32581 if (c == fopt->option[0]
32582 && ((arg == NULL && fopt->option[1] == 0)
32583 || streq (arg, fopt->option + 1)))
32584 {
e74cfd16 32585 /* If the option is deprecated, tell the user. */
278df34e 32586 if (warn_on_deprecated && fopt->deprecated != NULL)
e74cfd16
PB		 32587 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
32588 arg ? arg : "", _(fopt->deprecated));
e74cfd16
PB		 32589
32590 if (fopt->var != NULL)
32591 *fopt->var = &fopt->value;
32592
32593 return 1;
32594 }
32595 }
32596
c19d1205
ZW		 32597 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
32598 {
32599 /* These options are expected to have an argument. */
32600 if (c == lopt->option[0]
32601 && arg != NULL
32602 && strncmp (arg, lopt->option + 1,
32603 strlen (lopt->option + 1)) == 0)
32604 {
c19d1205 32605 /* If the option is deprecated, tell the user. */
278df34e 32606 if (warn_on_deprecated && lopt->deprecated != NULL)
c19d1205
ZW		 32607 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
32608 _(lopt->deprecated));
b99bd4ef 32609
c19d1205
ZW		 32610 /* Call the sup-option parser. */
32611 return lopt->func (arg + strlen (lopt->option) - 1);
32612 }
32613 }
a737bd4d 32614
c19d1205
ZW		 32615 return 0;
32616 }
a394c00f 32617
c19d1205
ZW		 32618 return 1;
32619}
a394c00f 32620
c19d1205
ZW		 32621void
32622md_show_usage (FILE * fp)
a394c00f 32623{
c19d1205
ZW		 32624 struct arm_option_table *opt;
32625 struct arm_long_option_table *lopt;
a394c00f 32626
c19d1205 32627 fprintf (fp, _(" ARM-specific assembler options:\n"));
a394c00f 32628
c19d1205
ZW		 32629 for (opt = arm_opts; opt->option != NULL; opt++)
32630 if (opt->help != NULL)
32631 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
a394c00f 32632
c19d1205
ZW		 32633 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
32634 if (lopt->help != NULL)
32635 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
a394c00f 32636
c19d1205
ZW		 32637#ifdef OPTION_EB
32638 fprintf (fp, _("\
32639 -EB assemble code for a big-endian cpu\n"));
a394c00f
NC		 32640#endif
32641
c19d1205
ZW		 32642#ifdef OPTION_EL
32643 fprintf (fp, _("\
32644 -EL assemble code for a little-endian cpu\n"));
a737bd4d 32645#endif
845b51d6
PB		 32646
32647 fprintf (fp, _("\
32648 --fix-v4bx Allow BX in ARMv4 code\n"));
18a20338
CL		 32649
32650#ifdef OBJ_ELF
32651 fprintf (fp, _("\
32652 --fdpic generate an FDPIC object file\n"));
32653#endif /* OBJ_ELF */
c19d1205 32654}
ee065d83 32655
ee065d83 32656#ifdef OBJ_ELF
0198d5e6 32657
62b3e311
PB		 32658typedef struct
32659{
32660 int val;
32661 arm_feature_set flags;
32662} cpu_arch_ver_table;
32663
2c6b98ea
TP		 32664/* Mapping from CPU features to EABI CPU arch values. Table must be sorted
32665 chronologically for architectures, with an exception for ARMv6-M and
32666 ARMv6S-M due to legacy reasons. No new architecture should have a
32667 special case. This allows for build attribute selection results to be
32668 stable when new architectures are added. */
62b3e311
PB		 32669static const cpu_arch_ver_table cpu_arch_ver[] =
32670{
031254f2
AV		 32671 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V1},
32672 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2},
32673 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2S},
32674 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3},
32675 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3M},
32676 {TAG_CPU_ARCH_V4, ARM_ARCH_V4xM},
32677 {TAG_CPU_ARCH_V4, ARM_ARCH_V4},
32678 {TAG_CPU_ARCH_V4T, ARM_ARCH_V4TxM},
32679 {TAG_CPU_ARCH_V4T, ARM_ARCH_V4T},
32680 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5xM},
32681 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5},
32682 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5TxM},
32683 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5T},
32684 {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TExP},
32685 {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TE},
32686 {TAG_CPU_ARCH_V5TEJ, ARM_ARCH_V5TEJ},
32687 {TAG_CPU_ARCH_V6, ARM_ARCH_V6},
32688 {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6Z},
32689 {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6KZ},
32690 {TAG_CPU_ARCH_V6K, ARM_ARCH_V6K},
32691 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6T2},
32692 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KT2},
32693 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6ZT2},
32694 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KZT2},
2c6b98ea
TP		 32695
32696 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
32697 always selected build attributes to match those of ARMv6-M
32698 (resp. ARMv6S-M). However, due to these architectures being a strict
32699 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
32700 would be selected when fully respecting chronology of architectures.
32701 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
32702 move them before ARMv7 architectures. */
031254f2
AV		 32703 {TAG_CPU_ARCH_V6_M, ARM_ARCH_V6M},
32704 {TAG_CPU_ARCH_V6S_M, ARM_ARCH_V6SM},
32705
32706 {TAG_CPU_ARCH_V7, ARM_ARCH_V7},
32707 {TAG_CPU_ARCH_V7, ARM_ARCH_V7A},
32708 {TAG_CPU_ARCH_V7, ARM_ARCH_V7R},
32709 {TAG_CPU_ARCH_V7, ARM_ARCH_V7M},
32710 {TAG_CPU_ARCH_V7, ARM_ARCH_V7VE},
32711 {TAG_CPU_ARCH_V7E_M, ARM_ARCH_V7EM},
32712 {TAG_CPU_ARCH_V8, ARM_ARCH_V8A},
32713 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_1A},
32714 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_2A},
32715 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_3A},
32716 {TAG_CPU_ARCH_V8M_BASE, ARM_ARCH_V8M_BASE},
32717 {TAG_CPU_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN},
32718 {TAG_CPU_ARCH_V8R, ARM_ARCH_V8R},
32719 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_4A},
32720 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_5A},
32721 {TAG_CPU_ARCH_V8_1M_MAIN, ARM_ARCH_V8_1M_MAIN},
aab2c27d
MM		 32722 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_6A},
32723 {-1, ARM_ARCH_NONE}
62b3e311
PB		 32724};
32725
ee3c0378 32726/* Set an attribute if it has not already been set by the user. */
0198d5e6 32727
ee3c0378
AS		 32728static void
32729aeabi_set_attribute_int (int tag, int value)
32730{
32731 if (tag < 1
32732 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
32733 || !attributes_set_explicitly[tag])
32734 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
32735}
32736
32737static void
32738aeabi_set_attribute_string (int tag, const char *value)
32739{
32740 if (tag < 1
32741 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
32742 || !attributes_set_explicitly[tag])
32743 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
32744}
32745
2c6b98ea
TP		 32746/* Return whether features in the *NEEDED feature set are available via
32747 extensions for the architecture whose feature set is *ARCH_FSET. */
0198d5e6 32748
2c6b98ea
TP		 32749static bfd_boolean
32750have_ext_for_needed_feat_p (const arm_feature_set *arch_fset,
32751 const arm_feature_set *needed)
32752{
32753 int i, nb_allowed_archs;
32754 arm_feature_set ext_fset;
32755 const struct arm_option_extension_value_table *opt;
32756
32757 ext_fset = arm_arch_none;
32758 for (opt = arm_extensions; opt->name != NULL; opt++)
32759 {
32760 /* Extension does not provide any feature we need. */
32761 if (!ARM_CPU_HAS_FEATURE (*needed, opt->merge_value))
32762 continue;
32763
32764 nb_allowed_archs =
32765 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]);
32766 for (i = 0; i < nb_allowed_archs; i++)
32767 {
32768 /* Empty entry. */
32769 if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_arch_any))
32770 break;
32771
32772 /* Extension is available, add it. */
32773 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *arch_fset))
32774 ARM_MERGE_FEATURE_SETS (ext_fset, ext_fset, opt->merge_value);
32775 }
32776 }
32777
32778 /* Can we enable all features in *needed? */
32779 return ARM_FSET_CPU_SUBSET (*needed, ext_fset);
32780}
32781
32782/* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
32783 a given architecture feature set *ARCH_EXT_FSET including extension feature
32784 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
32785 - if true, check for an exact match of the architecture modulo extensions;
32786 - otherwise, select build attribute value of the first superset
32787 architecture released so that results remains stable when new architectures
32788 are added.
32789 For -march/-mcpu=all the build attribute value of the most featureful
32790 architecture is returned. Tag_CPU_arch_profile result is returned in
32791 PROFILE. */
0198d5e6 32792
2c6b98ea
TP		 32793static int
32794get_aeabi_cpu_arch_from_fset (const arm_feature_set *arch_ext_fset,
32795 const arm_feature_set *ext_fset,
32796 char *profile, int exact_match)
32797{
32798 arm_feature_set arch_fset;
32799 const cpu_arch_ver_table *p_ver, *p_ver_ret = NULL;
32800
32801 /* Select most featureful architecture with all its extensions if building
32802 for -march=all as the feature sets used to set build attributes. */
32803 if (ARM_FEATURE_EQUAL (*arch_ext_fset, arm_arch_any))
32804 {
32805 /* Force revisiting of decision for each new architecture. */
031254f2 32806 gas_assert (MAX_TAG_CPU_ARCH <= TAG_CPU_ARCH_V8_1M_MAIN);
2c6b98ea
TP		 32807 *profile = 'A';
32808 return TAG_CPU_ARCH_V8;
32809 }
32810
32811 ARM_CLEAR_FEATURE (arch_fset, *arch_ext_fset, *ext_fset);
32812
32813 for (p_ver = cpu_arch_ver; p_ver->val != -1; p_ver++)
32814 {
32815 arm_feature_set known_arch_fset;
32816
32817 ARM_CLEAR_FEATURE (known_arch_fset, p_ver->flags, fpu_any);
32818 if (exact_match)
32819 {
32820 /* Base architecture match user-specified architecture and
32821 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
32822 if (ARM_FEATURE_EQUAL (*arch_ext_fset, known_arch_fset))
32823 {
32824 p_ver_ret = p_ver;
32825 goto found;
32826 }
32827 /* Base architecture match user-specified architecture only
32828 (eg. ARMv6-M in the same case as above). Record it in case we
32829 find a match with above condition. */
32830 else if (p_ver_ret == NULL
32831 && ARM_FEATURE_EQUAL (arch_fset, known_arch_fset))
32832 p_ver_ret = p_ver;
32833 }
32834 else
32835 {
32836
32837 /* Architecture has all features wanted. */
32838 if (ARM_FSET_CPU_SUBSET (arch_fset, known_arch_fset))
32839 {
32840 arm_feature_set added_fset;
32841
32842 /* Compute features added by this architecture over the one
32843 recorded in p_ver_ret. */
32844 if (p_ver_ret != NULL)
32845 ARM_CLEAR_FEATURE (added_fset, known_arch_fset,
32846 p_ver_ret->flags);
32847 /* First architecture that match incl. with extensions, or the
32848 only difference in features over the recorded match is
32849 features that were optional and are now mandatory. */
32850 if (p_ver_ret == NULL
32851 || ARM_FSET_CPU_SUBSET (added_fset, arch_fset))
32852 {
32853 p_ver_ret = p_ver;
32854 goto found;
32855 }
32856 }
32857 else if (p_ver_ret == NULL)
32858 {
32859 arm_feature_set needed_ext_fset;
32860
32861 ARM_CLEAR_FEATURE (needed_ext_fset, arch_fset, known_arch_fset);
32862
32863 /* Architecture has all features needed when using some
32864 extensions. Record it and continue searching in case there
32865 exist an architecture providing all needed features without
32866 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
32867 OS extension). */
32868 if (have_ext_for_needed_feat_p (&known_arch_fset,
32869 &needed_ext_fset))
32870 p_ver_ret = p_ver;
32871 }
32872 }
32873 }
32874
32875 if (p_ver_ret == NULL)
32876 return -1;
32877
dc1e8a47 32878 found:
2c6b98ea 32879 /* Tag_CPU_arch_profile. */
164446e0
AF		 32880 if (!ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8r)
32881 && (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7a)
32882 || ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8)
32883 || (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_atomics)
32884 && !ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8m_m_only))))
2c6b98ea 32885 *profile = 'A';
164446e0
AF		 32886 else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7r)
32887 || ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8r))
2c6b98ea
TP		 32888 *profile = 'R';
32889 else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_m))
32890 *profile = 'M';
32891 else
32892 *profile = '\0';
32893 return p_ver_ret->val;
32894}
32895
ee065d83 32896/* Set the public EABI object attributes. */
0198d5e6 32897
c168ce07 32898static void
ee065d83
PB		 32899aeabi_set_public_attributes (void)
32900{
b90d5ba0 32901 char profile = '\0';
2c6b98ea 32902 int arch = -1;
90ec0d68 32903 int virt_sec = 0;
bca38921 32904 int fp16_optional = 0;
2c6b98ea
TP		 32905 int skip_exact_match = 0;
32906 arm_feature_set flags, flags_arch, flags_ext;
ee065d83 32907
54bab281
TP		 32908 /* Autodetection mode, choose the architecture based the instructions
32909 actually used. */
32910 if (no_cpu_selected ())
32911 {
32912 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
ddd7f988 32913
54bab281
TP		 32914 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
32915 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
ddd7f988 32916
54bab281
TP		 32917 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
32918 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
ddd7f988 32919
54bab281 32920 /* Code run during relaxation relies on selected_cpu being set. */
4d354d8b
TP		 32921 ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any);
32922 flags_ext = arm_arch_none;
32923 ARM_CLEAR_FEATURE (selected_arch, flags_arch, flags_ext);
32924 selected_ext = flags_ext;
54bab281
TP		 32925 selected_cpu = flags;
32926 }
32927 /* Otherwise, choose the architecture based on the capabilities of the
32928 requested cpu. */
32929 else
4d354d8b
TP		 32930 {
32931 ARM_MERGE_FEATURE_SETS (flags_arch, selected_arch, selected_ext);
32932 ARM_CLEAR_FEATURE (flags_arch, flags_arch, fpu_any);
32933 flags_ext = selected_ext;
32934 flags = selected_cpu;
32935 }
32936 ARM_MERGE_FEATURE_SETS (flags, flags, selected_fpu);
7f78eb34 32937
ddd7f988 32938 /* Allow the user to override the reported architecture. */
4d354d8b 32939 if (!ARM_FEATURE_ZERO (selected_object_arch))
7a1d4c38 32940 {
4d354d8b 32941 ARM_CLEAR_FEATURE (flags_arch, selected_object_arch, fpu_any);
2c6b98ea 32942 flags_ext = arm_arch_none;
7a1d4c38 32943 }
2c6b98ea 32944 else
4d354d8b 32945 skip_exact_match = ARM_FEATURE_EQUAL (selected_cpu, arm_arch_any);
2c6b98ea
TP		 32946
32947 /* When this function is run again after relaxation has happened there is no
32948 way to determine whether an architecture or CPU was specified by the user:
32949 - selected_cpu is set above for relaxation to work;
32950 - march_cpu_opt is not set if only -mcpu or .cpu is used;
32951 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
32952 Therefore, if not in -march=all case we first try an exact match and fall
32953 back to autodetection. */
32954 if (!skip_exact_match)
32955 arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 1);
32956 if (arch == -1)
32957 arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 0);
32958 if (arch == -1)
32959 as_bad (_("no architecture contains all the instructions used\n"));
9e3c6df6 32960
ee065d83
PB		 32961 /* Tag_CPU_name. */
32962 if (selected_cpu_name[0])
32963 {
91d6fa6a 32964 char *q;
ee065d83 32965
91d6fa6a
NC		 32966 q = selected_cpu_name;
32967 if (strncmp (q, "armv", 4) == 0)
ee065d83
PB		 32968 {
32969 int i;
5f4273c7 32970
91d6fa6a
NC		 32971 q += 4;
32972 for (i = 0; q[i]; i++)
32973 q[i] = TOUPPER (q[i]);
ee065d83 32974 }
91d6fa6a 32975 aeabi_set_attribute_string (Tag_CPU_name, q);
ee065d83 32976 }
62f3b8c8 32977
ee065d83 32978 /* Tag_CPU_arch. */
ee3c0378 32979 aeabi_set_attribute_int (Tag_CPU_arch, arch);
62f3b8c8 32980
62b3e311 32981 /* Tag_CPU_arch_profile. */
69239280
MGD		 32982 if (profile != '\0')
32983 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
62f3b8c8 32984
15afaa63 32985 /* Tag_DSP_extension. */
4d354d8b 32986 if (ARM_CPU_HAS_FEATURE (selected_ext, arm_ext_dsp))
6c290d53 32987 aeabi_set_attribute_int (Tag_DSP_extension, 1);
15afaa63 32988
2c6b98ea 32989 ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any);
ee065d83 32990 /* Tag_ARM_ISA_use. */
ee3c0378 32991 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
2c6b98ea 32992 || ARM_FEATURE_ZERO (flags_arch))
ee3c0378 32993 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
62f3b8c8 32994
ee065d83 32995 /* Tag_THUMB_ISA_use. */
ee3c0378 32996 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
2c6b98ea 32997 || ARM_FEATURE_ZERO (flags_arch))
4ed7ed8d
TP		 32998 {
32999 int thumb_isa_use;
33000
33001 if (!ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
16a1fa25 33002 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m_m_only))
4ed7ed8d
TP		 33003 thumb_isa_use = 3;
33004 else if (ARM_CPU_HAS_FEATURE (flags, arm_arch_t2))
33005 thumb_isa_use = 2;
33006 else
33007 thumb_isa_use = 1;
33008 aeabi_set_attribute_int (Tag_THUMB_ISA_use, thumb_isa_use);
33009 }
62f3b8c8 33010
ee065d83 33011 /* Tag_VFP_arch. */
a715796b
TG		 33012 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8xd))
33013 aeabi_set_attribute_int (Tag_VFP_arch,
33014 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
33015 ? 7 : 8);
bca38921 33016 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
62f3b8c8
PB		 33017 aeabi_set_attribute_int (Tag_VFP_arch,
33018 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
33019 ? 5 : 6);
33020 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
bca38921
MGD		 33021 {
33022 fp16_optional = 1;
33023 aeabi_set_attribute_int (Tag_VFP_arch, 3);
33024 }
ada65aa3 33025 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
bca38921
MGD		 33026 {
33027 aeabi_set_attribute_int (Tag_VFP_arch, 4);
33028 fp16_optional = 1;
33029 }
ee3c0378
AS		 33030 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
33031 aeabi_set_attribute_int (Tag_VFP_arch, 2);
33032 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
477330fc 33033 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
ee3c0378 33034 aeabi_set_attribute_int (Tag_VFP_arch, 1);
62f3b8c8 33035
4547cb56
NC		 33036 /* Tag_ABI_HardFP_use. */
33037 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
33038 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
33039 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
33040
ee065d83 33041 /* Tag_WMMX_arch. */
ee3c0378
AS		 33042 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
33043 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
33044 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
33045 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
62f3b8c8 33046
ee3c0378 33047 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
9411fd44
MW		 33048 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v8_1))
33049 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 4);
33050 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
bca38921
MGD		 33051 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
33052 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
33053 {
33054 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
33055 {
33056 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
33057 }
33058 else
33059 {
33060 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
33061 fp16_optional = 1;
33062 }
33063 }
fa94de6b 33064
a7ad558c
AV		 33065 if (ARM_CPU_HAS_FEATURE (flags, mve_fp_ext))
33066 aeabi_set_attribute_int (Tag_MVE_arch, 2);
33067 else if (ARM_CPU_HAS_FEATURE (flags, mve_ext))
33068 aeabi_set_attribute_int (Tag_MVE_arch, 1);
33069
ee3c0378 33070 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
bca38921 33071 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
ee3c0378 33072 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
4547cb56 33073
69239280
MGD		 33074 /* Tag_DIV_use.
33075
33076 We set Tag_DIV_use to two when integer divide instructions have been used
33077 in ARM state, or when Thumb integer divide instructions have been used,
33078 but we have no architecture profile set, nor have we any ARM instructions.
33079
4ed7ed8d
TP		 33080 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
33081 by the base architecture.
bca38921 33082
69239280 33083 For new architectures we will have to check these tests. */
031254f2 33084 gas_assert (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
4ed7ed8d
TP		 33085 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
33086 || ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m))
bca38921
MGD		 33087 aeabi_set_attribute_int (Tag_DIV_use, 0);
33088 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
33089 || (profile == '\0'
33090 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
33091 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
eea54501 33092 aeabi_set_attribute_int (Tag_DIV_use, 2);
60e5ef9f
MGD		 33093
33094 /* Tag_MP_extension_use. */
33095 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
33096 aeabi_set_attribute_int (Tag_MPextension_use, 1);
f4c65163
MGD		 33097
33098 /* Tag Virtualization_use. */
33099 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
90ec0d68
MGD		 33100 virt_sec |= 1;
33101 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
33102 virt_sec |= 2;
33103 if (virt_sec != 0)
33104 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
5312fe52
BW		 33105
33106 if (fp16_format != ARM_FP16_FORMAT_DEFAULT)
33107 aeabi_set_attribute_int (Tag_ABI_FP_16bit_format, fp16_format);
ee065d83
PB		 33108}
33109
c168ce07
TP		 33110/* Post relaxation hook. Recompute ARM attributes now that relaxation is
33111 finished and free extension feature bits which will not be used anymore. */
0198d5e6 33112
c168ce07
TP		 33113void
33114arm_md_post_relax (void)
33115{
33116 aeabi_set_public_attributes ();
4d354d8b
TP		 33117 XDELETE (mcpu_ext_opt);
33118 mcpu_ext_opt = NULL;
33119 XDELETE (march_ext_opt);
33120 march_ext_opt = NULL;
c168ce07
TP		 33121}
33122
104d59d1 33123/* Add the default contents for the .ARM.attributes section. */
0198d5e6 33124
ee065d83
PB		 33125void
33126arm_md_end (void)
33127{
ee065d83
PB		 33128 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
33129 return;
33130
33131 aeabi_set_public_attributes ();
ee065d83 33132}
8463be01 33133#endif /* OBJ_ELF */
ee065d83 33134
ee065d83
PB		 33135/* Parse a .cpu directive. */
33136
33137static void
33138s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
33139{
e74cfd16 33140 const struct arm_cpu_option_table *opt;
ee065d83
PB		 33141 char *name;
33142 char saved_char;
33143
33144 name = input_line_pointer;
5f4273c7 33145 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB		 33146 input_line_pointer++;
33147 saved_char = *input_line_pointer;
33148 *input_line_pointer = 0;
33149
33150 /* Skip the first "all" entry. */
33151 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
33152 if (streq (opt->name, name))
33153 {
4d354d8b
TP		 33154 selected_arch = opt->value;
33155 selected_ext = opt->ext;
33156 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
ee065d83 33157 if (opt->canonical_name)
5f4273c7 33158 strcpy (selected_cpu_name, opt->canonical_name);
ee065d83
PB		 33159 else
33160 {
33161 int i;
33162 for (i = 0; opt->name[i]; i++)
33163 selected_cpu_name[i] = TOUPPER (opt->name[i]);
f3bad469 33164
ee065d83
PB		 33165 selected_cpu_name[i] = 0;
33166 }
4d354d8b
TP		 33167 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
33168
ee065d83
PB		 33169 *input_line_pointer = saved_char;
33170 demand_empty_rest_of_line ();
33171 return;
33172 }
33173 as_bad (_("unknown cpu `%s'"), name);
33174 *input_line_pointer = saved_char;
33175 ignore_rest_of_line ();
33176}
33177
ee065d83
PB		 33178/* Parse a .arch directive. */
33179
33180static void
33181s_arm_arch (int ignored ATTRIBUTE_UNUSED)
33182{
e74cfd16 33183 const struct arm_arch_option_table *opt;
ee065d83
PB		 33184 char saved_char;
33185 char *name;
33186
33187 name = input_line_pointer;
5f4273c7 33188 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB		 33189 input_line_pointer++;
33190 saved_char = *input_line_pointer;
33191 *input_line_pointer = 0;
33192
33193 /* Skip the first "all" entry. */
33194 for (opt = arm_archs + 1; opt->name != NULL; opt++)
33195 if (streq (opt->name, name))
33196 {
4d354d8b 33197 selected_arch = opt->value;
0e7aaa72 33198 selected_ctx_ext_table = opt->ext_table;
4d354d8b
TP		 33199 selected_ext = arm_arch_none;
33200 selected_cpu = selected_arch;
5f4273c7 33201 strcpy (selected_cpu_name, opt->name);
4d354d8b 33202 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
ee065d83
PB		 33203 *input_line_pointer = saved_char;
33204 demand_empty_rest_of_line ();
33205 return;
33206 }
33207
33208 as_bad (_("unknown architecture `%s'\n"), name);
33209 *input_line_pointer = saved_char;
33210 ignore_rest_of_line ();
33211}
33212
7a1d4c38
PB		 33213/* Parse a .object_arch directive. */
33214
33215static void
33216s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
33217{
33218 const struct arm_arch_option_table *opt;
33219 char saved_char;
33220 char *name;
33221
33222 name = input_line_pointer;
5f4273c7 33223 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
7a1d4c38
PB		 33224 input_line_pointer++;
33225 saved_char = *input_line_pointer;
33226 *input_line_pointer = 0;
33227
33228 /* Skip the first "all" entry. */
33229 for (opt = arm_archs + 1; opt->name != NULL; opt++)
33230 if (streq (opt->name, name))
33231 {
4d354d8b 33232 selected_object_arch = opt->value;
7a1d4c38
PB		 33233 *input_line_pointer = saved_char;
33234 demand_empty_rest_of_line ();
33235 return;
33236 }
33237
33238 as_bad (_("unknown architecture `%s'\n"), name);
33239 *input_line_pointer = saved_char;
33240 ignore_rest_of_line ();
33241}
33242
69133863
MGD		 33243/* Parse a .arch_extension directive. */
33244
33245static void
33246s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
33247{
33248 const struct arm_option_extension_value_table *opt;
33249 char saved_char;
33250 char *name;
33251 int adding_value = 1;
33252
33253 name = input_line_pointer;
33254 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
33255 input_line_pointer++;
33256 saved_char = *input_line_pointer;
33257 *input_line_pointer = 0;
33258
33259 if (strlen (name) >= 2
33260 && strncmp (name, "no", 2) == 0)
33261 {
33262 adding_value = 0;
33263 name += 2;
33264 }
33265
e20f9590
MI		 33266 /* Check the context specific extension table */
33267 if (selected_ctx_ext_table)
33268 {
33269 const struct arm_ext_table * ext_opt;
33270 for (ext_opt = selected_ctx_ext_table; ext_opt->name != NULL; ext_opt++)
33271 {
33272 if (streq (ext_opt->name, name))
33273 {
33274 if (adding_value)
33275 {
33276 if (ARM_FEATURE_ZERO (ext_opt->merge))
33277 /* TODO: Option not supported. When we remove the
33278 legacy table this case should error out. */
33279 continue;
33280 ARM_MERGE_FEATURE_SETS (selected_ext, selected_ext,
33281 ext_opt->merge);
33282 }
33283 else
33284 ARM_CLEAR_FEATURE (selected_ext, selected_ext, ext_opt->clear);
33285
33286 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
33287 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
33288 *input_line_pointer = saved_char;
33289 demand_empty_rest_of_line ();
33290 return;
33291 }
33292 }
33293 }
33294
69133863
MGD		 33295 for (opt = arm_extensions; opt->name != NULL; opt++)
33296 if (streq (opt->name, name))
33297 {
d942732e
TP		 33298 int i, nb_allowed_archs =
33299 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[i]);
33300 for (i = 0; i < nb_allowed_archs; i++)
33301 {
33302 /* Empty entry. */
4d354d8b 33303 if (ARM_CPU_IS_ANY (opt->allowed_archs[i]))
d942732e 33304 continue;
4d354d8b 33305 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], selected_arch))
d942732e
TP		 33306 break;
33307 }
33308
33309 if (i == nb_allowed_archs)
69133863
MGD		 33310 {
33311 as_bad (_("architectural extension `%s' is not allowed for the "
33312 "current base architecture"), name);
33313 break;
33314 }
33315
33316 if (adding_value)
4d354d8b 33317 ARM_MERGE_FEATURE_SETS (selected_ext, selected_ext,
5a70a223 33318 opt->merge_value);
69133863 33319 else
4d354d8b 33320 ARM_CLEAR_FEATURE (selected_ext, selected_ext, opt->clear_value);
69133863 33321
4d354d8b
TP		 33322 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
33323 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
69133863
MGD		 33324 *input_line_pointer = saved_char;
33325 demand_empty_rest_of_line ();
3d030cdb
TP		 33326 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
33327 on this return so that duplicate extensions (extensions with the
33328 same name as a previous extension in the list) are not considered
33329 for command-line parsing. */
69133863
MGD		 33330 return;
33331 }
33332
33333 if (opt->name == NULL)
e673710a 33334 as_bad (_("unknown architecture extension `%s'\n"), name);
69133863
MGD		 33335
33336 *input_line_pointer = saved_char;
33337 ignore_rest_of_line ();
33338}
33339
ee065d83
PB		 33340/* Parse a .fpu directive. */
33341
33342static void
33343s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
33344{
69133863 33345 const struct arm_option_fpu_value_table *opt;
ee065d83
PB		 33346 char saved_char;
33347 char *name;
33348
33349 name = input_line_pointer;
5f4273c7 33350 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB		 33351 input_line_pointer++;
33352 saved_char = *input_line_pointer;
33353 *input_line_pointer = 0;
5f4273c7 33354
ee065d83
PB		 33355 for (opt = arm_fpus; opt->name != NULL; opt++)
33356 if (streq (opt->name, name))
33357 {
4d354d8b 33358 selected_fpu = opt->value;
f4399880 33359 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, fpu_any);
4d354d8b
TP		 33360#ifndef CPU_DEFAULT
33361 if (no_cpu_selected ())
33362 ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu);
33363 else
33364#endif
33365 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
ee065d83
PB		 33366 *input_line_pointer = saved_char;
33367 demand_empty_rest_of_line ();
33368 return;
33369 }
33370
33371 as_bad (_("unknown floating point format `%s'\n"), name);
33372 *input_line_pointer = saved_char;
33373 ignore_rest_of_line ();
33374}
ee065d83 33375
794ba86a 33376/* Copy symbol information. */
f31fef98 33377
794ba86a
DJ		 33378void
33379arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
33380{
33381 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
33382}
e04befd0 33383
f31fef98 33384#ifdef OBJ_ELF
e04befd0
AS		 33385/* Given a symbolic attribute NAME, return the proper integer value.
33386 Returns -1 if the attribute is not known. */
f31fef98 33387
e04befd0
AS		 33388int
33389arm_convert_symbolic_attribute (const char *name)
33390{
f31fef98
NC		 33391 static const struct
33392 {
33393 const char * name;
33394 const int tag;
33395 }
33396 attribute_table[] =
33397 {
33398 /* When you modify this table you should
33399 also modify the list in doc/c-arm.texi. */
e04befd0 33400#define T(tag) {#tag, tag}
f31fef98
NC		 33401 T (Tag_CPU_raw_name),
33402 T (Tag_CPU_name),
33403 T (Tag_CPU_arch),
33404 T (Tag_CPU_arch_profile),
33405 T (Tag_ARM_ISA_use),
33406 T (Tag_THUMB_ISA_use),
75375b3e 33407 T (Tag_FP_arch),
f31fef98
NC		 33408 T (Tag_VFP_arch),
33409 T (Tag_WMMX_arch),
33410 T (Tag_Advanced_SIMD_arch),
33411 T (Tag_PCS_config),
33412 T (Tag_ABI_PCS_R9_use),
33413 T (Tag_ABI_PCS_RW_data),
33414 T (Tag_ABI_PCS_RO_data),
33415 T (Tag_ABI_PCS_GOT_use),
33416 T (Tag_ABI_PCS_wchar_t),
33417 T (Tag_ABI_FP_rounding),
33418 T (Tag_ABI_FP_denormal),
33419 T (Tag_ABI_FP_exceptions),
33420 T (Tag_ABI_FP_user_exceptions),
33421 T (Tag_ABI_FP_number_model),
75375b3e 33422 T (Tag_ABI_align_needed),
f31fef98 33423 T (Tag_ABI_align8_needed),
75375b3e 33424 T (Tag_ABI_align_preserved),
f31fef98
NC		 33425 T (Tag_ABI_align8_preserved),
33426 T (Tag_ABI_enum_size),
33427 T (Tag_ABI_HardFP_use),
33428 T (Tag_ABI_VFP_args),
33429 T (Tag_ABI_WMMX_args),
33430 T (Tag_ABI_optimization_goals),
33431 T (Tag_ABI_FP_optimization_goals),
33432 T (Tag_compatibility),
33433 T (Tag_CPU_unaligned_access),
75375b3e 33434 T (Tag_FP_HP_extension),
f31fef98
NC		 33435 T (Tag_VFP_HP_extension),
33436 T (Tag_ABI_FP_16bit_format),
cd21e546
MGD		 33437 T (Tag_MPextension_use),
33438 T (Tag_DIV_use),
f31fef98
NC		 33439 T (Tag_nodefaults),
33440 T (Tag_also_compatible_with),
33441 T (Tag_conformance),
33442 T (Tag_T2EE_use),
33443 T (Tag_Virtualization_use),
15afaa63 33444 T (Tag_DSP_extension),
a7ad558c 33445 T (Tag_MVE_arch),
cd21e546 33446 /* We deliberately do not include Tag_MPextension_use_legacy. */
e04befd0 33447#undef T
f31fef98 33448 };
e04befd0
AS		 33449 unsigned int i;
33450
33451 if (name == NULL)
33452 return -1;
33453
f31fef98 33454 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
c921be7d 33455 if (streq (name, attribute_table[i].name))
e04befd0
AS		 33456 return attribute_table[i].tag;
33457
33458 return -1;
33459}
267bf995 33460
93ef582d
NC		 33461/* Apply sym value for relocations only in the case that they are for
33462 local symbols in the same segment as the fixup and you have the
33463 respective architectural feature for blx and simple switches. */
0198d5e6 33464
267bf995 33465int
93ef582d 33466arm_apply_sym_value (struct fix * fixP, segT this_seg)
267bf995
RR		 33467{
33468 if (fixP->fx_addsy
33469 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
93ef582d
NC		 33470 /* PR 17444: If the local symbol is in a different section then a reloc
33471 will always be generated for it, so applying the symbol value now
33472 will result in a double offset being stored in the relocation. */
33473 && (S_GET_SEGMENT (fixP->fx_addsy) == this_seg)
34e77a92 33474 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
267bf995
RR		 33475 {
33476 switch (fixP->fx_r_type)
33477 {
33478 case BFD_RELOC_ARM_PCREL_BLX:
33479 case BFD_RELOC_THUMB_PCREL_BRANCH23:
33480 if (ARM_IS_FUNC (fixP->fx_addsy))
33481 return 1;
33482 break;
33483
33484 case BFD_RELOC_ARM_PCREL_CALL:
33485 case BFD_RELOC_THUMB_PCREL_BLX:
33486 if (THUMB_IS_FUNC (fixP->fx_addsy))
93ef582d 33487 return 1;
267bf995
RR		 33488 break;
33489
33490 default:
33491 break;
33492 }
33493
33494 }
33495 return 0;
33496}
f31fef98 33497#endif /* OBJ_ELF */
GDB Binutils - Deliverables
This page took 4.469593 seconds and 4 git commands to generate.