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gdb/testsuite/gdb.base/stap-probe: Minor clean-up
[deliverable/binutils-gdb.git] / gas / config / tc-avr.c
CommitLineData
adde6300
AM		 1/* tc-avr.c -- Assembler code for the ATMEL AVR
2
b3adc24a 3 Copyright (C) 1999-2020 Free Software Foundation, Inc.
adde6300
AM		 4 Contributed by Denis Chertykov <denisc@overta.ru>
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
adde6300
AM		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
4b4da160
NC		 20 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
adde6300 22
adde6300 23#include "as.h"
3882b010 24#include "safe-ctype.h"
adde6300 25#include "subsegs.h"
fb5b7503 26#include "dwarf2dbg.h"
af3ecb4a 27#include "dw2gencfi.h"
eac7440d 28#include "elf/avr.h"
fdd410ac
AB		 29#include "elf32-avr.h"
30
31/* For building a linked list of AVR_PROPERTY_RECORD structures. */
32struct avr_property_record_link
33{
34 struct avr_property_record record;
35 struct avr_property_record_link *next;
36};
adde6300 37
1188e082
DC		 38struct avr_opcodes_s
39{
e0471c16
TS		 40 const char * name;
41 const char * constraints;
42 const char * opcode;
dc191a8f
NC		 43 int insn_size; /* In words. */
44 int isa;
45 unsigned int bin_opcode;
1188e082
DC		 46};
47
48#define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
8cc66334 49{#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},
1188e082
DC		 50
51struct avr_opcodes_s avr_opcodes[] =
52{
53 #include "opcode/avr.h"
8cc66334 54 {NULL, NULL, NULL, 0, 0, 0}
1188e082
DC		 55};
56
32f76c67
GJL		 57
58/* Stuff for the `__gcc_isr' pseudo instruction.
59
60 Purpose of the pseudo instruction is to emit more efficient ISR prologues
61 and epilogues than GCC currently does. GCC has no explicit (on RTL level)
62 modelling of SREG, TMP_REG or ZERO_REG. These regs are used implicitly
63 during instruction printing. That doesn't hurt too much for ordinary
64 functions, however for small ISRs there might be some overhead.
65
66 As implementing http://gcc.gnu.org/PR20296 would imply an almost complete
67 rewite of GCC's AVR back-end (which might pop up less optimized code in
68 other places), we provide a pseudo-instruction which is resolved by GAS
69 into ISR prologue / epilogue as expected by GCC.
70
71 Using GAS for this purpose has the additional benefit that it can scan
72 code emit by inline asm which is opaque to GCC.
73
74 The pseudo-instruction is only supposed to handle the starting of
75 prologue and the ending of epilogues (without RETI) which deal with
76 SREG, TMP_REG and ZERO_REG and one additional, optional general purpose
77 register.
78
79 __gcc_isr consists of 3 different "chunks":
80
81 __gcc_isr 1
82 Chunk 1 (ISR_CHUNK_Prologue)
83 Start the ISR code. Will be replaced by ISR prologue by next Done chunk.
84 Must be the 1st chunk in a file or follow a Done chunk from previous
85 ISR (which has been patched already).
86
87 It will finish the current frag and emit a new frag of
88 type rs_machine_dependent, subtype ISR_CHUNK_Prologue.
89
90 __gcc_isr 2
91 Chunk 2 (ISR_CHUNK_Epilogue)
92 Will be replaced by ISR epilogue by next Done chunk. Must follow
93 chunk 1 (Prologue) or chunk 2 (Epilogue). Functions might come
94 without epilogue or with more than one epilogue, and even code
95 located statically after the last epilogue might belong to a function.
96
97 It will finish the current frag and emit a new frag of
98 type rs_machine_dependent, subtype ISR_CHUNK_Epilogue.
99
100 __gcc_isr 0, Rx
101 Chunk 0 (ISR_CHUNK_Done)
102 Must follow chunk 1 (Prologue) or chunk 2 (Epilogue) and finishes
103 the ISR code. Only GCC can know where a function's code ends.
104
105 It triggers the patch-up of all rs_machine_dependent frags in the
106 current frag chain and turns them into ordinary rs_fill code frags.
107
108 If Rx is a register > ZERO_REG then GCC also wants to push / pop Rx.
109 If neither TMP_REG nor ZERO_REG are needed, Rx will be used in
110 the push / pop sequence avoiding the need for TMP_REG / ZERO_REG.
111 If Rx <= ZERO_REG then GCC doesn't assume anything about Rx.
112
113 Assumptions:
114
115 o GCC takes care of code that is opaque to GAS like tail calls
116 or non-local goto.
117
118 o Using SEI / CLI does not count as clobbering SREG. This is
119 because a final RETI will restore the I-flag.
120
121 o Using OUT or ST* is supposed not to clobber SREG. Sequences like
122
123 IN-SREG + CLI + Atomic-Code + OUT-SREG
124
125 will still work as expected because the scan will reveal any
126 clobber of SREG other than I-flag and emit PUSH / POP of SREG.
127*/
128
129enum
130 {
131 ISR_CHUNK_Done = 0,
132 ISR_CHUNK_Prologue = 1,
133 ISR_CHUNK_Epilogue = 2
134 };
135
136static struct
137{
138 /* Previous __gcc_isr chunk (one of the enums above)
139 and it's location for diagnostics. */
140 int prev_chunk;
141 unsigned line;
142 const char *file;
143 /* Replacer for __gcc_isr.n_pushed once we know how many regs are
144 pushed by the Prologue chunk. */
145 symbolS *sym_n_pushed;
146
147 /* Set and used during parse from chunk 1 (Prologue) up to chunk 0 (Done).
148 Set by `avr_update_gccisr' and used by `avr_patch_gccisr_frag'. */
149 int need_reg_tmp;
150 int need_reg_zero;
151 int need_sreg;
152} avr_isr;
153
154static void avr_gccisr_operands (struct avr_opcodes_s*, char**);
155static void avr_update_gccisr (struct avr_opcodes_s*, int, int);
156static struct avr_opcodes_s *avr_gccisr_opcode;
157
adde6300
AM		 158const char comment_chars[] = ";";
159const char line_comment_chars[] = "#";
160const char line_separator_chars[] = "$";
161
adde6300
AM		 162const char *md_shortopts = "m:";
163struct mcu_type_s
164{
e0471c16 165 const char *name;
adde6300
AM		 166 int isa;
167 int mach;
168};
169
1f8ae5e6 170/* XXX - devices that don't seem to exist (renamed, replaced with larger
7b21ac3f 171 ones, or planned but never produced), left here for compatibility. */
1f8ae5e6 172
adde6300
AM		 173static struct mcu_type_s mcu_types[] =
174{
7b21ac3f 175 {"avr1", AVR_ISA_AVR1, bfd_mach_avr1},
33eaf5de 176/* TODO: instruction set for avr2 architecture should be AVR_ISA_AVR2,
99700d6f
NC		 177 but set to AVR_ISA_AVR25 for some following version
178 of GCC (from 4.3) for backward compatibility. */
7b21ac3f
EW		 179 {"avr2", AVR_ISA_AVR25, bfd_mach_avr2},
180 {"avr25", AVR_ISA_AVR25, bfd_mach_avr25},
33eaf5de 181/* TODO: instruction set for avr3 architecture should be AVR_ISA_AVR3,
99700d6f 182 but set to AVR_ISA_AVR3_ALL for some following version
7b21ac3f
EW		 183 of GCC (from 4.3) for backward compatibility. */
184 {"avr3", AVR_ISA_AVR3_ALL, bfd_mach_avr3},
185 {"avr31", AVR_ISA_AVR31, bfd_mach_avr31},
186 {"avr35", AVR_ISA_AVR35, bfd_mach_avr35},
187 {"avr4", AVR_ISA_AVR4, bfd_mach_avr4},
33eaf5de 188/* TODO: instruction set for avr5 architecture should be AVR_ISA_AVR5,
99700d6f 189 but set to AVR_ISA_AVR51 for some following version
7b21ac3f
EW		 190 of GCC (from 4.3) for backward compatibility. */
191 {"avr5", AVR_ISA_AVR51, bfd_mach_avr5},
192 {"avr51", AVR_ISA_AVR51, bfd_mach_avr51},
193 {"avr6", AVR_ISA_AVR6, bfd_mach_avr6},
8cc66334
EW		 194 {"avrxmega1", AVR_ISA_XMEGA, bfd_mach_avrxmega1},
195 {"avrxmega2", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
196 {"avrxmega3", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
197 {"avrxmega4", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
198 {"avrxmega5", AVR_ISA_XMEGA, bfd_mach_avrxmega5},
199 {"avrxmega6", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
200 {"avrxmega7", AVR_ISA_XMEGA, bfd_mach_avrxmega7},
f36e8886 201 {"avrtiny", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
28c9d252 202 {"at90s1200", AVR_ISA_1200, bfd_mach_avr1},
7b21ac3f
EW		 203 {"attiny11", AVR_ISA_AVR1, bfd_mach_avr1},
204 {"attiny12", AVR_ISA_AVR1, bfd_mach_avr1},
205 {"attiny15", AVR_ISA_AVR1, bfd_mach_avr1},
206 {"attiny28", AVR_ISA_AVR1, bfd_mach_avr1},
207 {"at90s2313", AVR_ISA_AVR2, bfd_mach_avr2},
208 {"at90s2323", AVR_ISA_AVR2, bfd_mach_avr2},
209 {"at90s2333", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 4433 */
210 {"at90s2343", AVR_ISA_AVR2, bfd_mach_avr2},
211 {"attiny22", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 2343 */
d669d37f 212 {"attiny26", AVR_ISA_2xxe, bfd_mach_avr2},
7b21ac3f
EW		 213 {"at90s4414", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 8515 */
214 {"at90s4433", AVR_ISA_AVR2, bfd_mach_avr2},
215 {"at90s4434", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 8535 */
216 {"at90s8515", AVR_ISA_AVR2, bfd_mach_avr2},
217 {"at90c8534", AVR_ISA_AVR2, bfd_mach_avr2},
218 {"at90s8535", AVR_ISA_AVR2, bfd_mach_avr2},
255d9eec 219 {"ata5272", AVR_ISA_AVR25, bfd_mach_avr25},
7b21ac3f
EW		 220 {"attiny13", AVR_ISA_AVR25, bfd_mach_avr25},
221 {"attiny13a", AVR_ISA_AVR25, bfd_mach_avr25},
222 {"attiny2313", AVR_ISA_AVR25, bfd_mach_avr25},
8453da2e 223 {"attiny2313a",AVR_ISA_AVR25, bfd_mach_avr25},
7b21ac3f 224 {"attiny24", AVR_ISA_AVR25, bfd_mach_avr25},
8453da2e
EW		 225 {"attiny24a", AVR_ISA_AVR25, bfd_mach_avr25},
226 {"attiny4313", AVR_ISA_AVR25, bfd_mach_avr25},
7b21ac3f 227 {"attiny44", AVR_ISA_AVR25, bfd_mach_avr25},
8453da2e 228 {"attiny44a", AVR_ISA_AVR25, bfd_mach_avr25},
7b21ac3f 229 {"attiny84", AVR_ISA_AVR25, bfd_mach_avr25},
e760a81b 230 {"attiny84a", AVR_ISA_AVR25, bfd_mach_avr25},
7b21ac3f
EW		 231 {"attiny25", AVR_ISA_AVR25, bfd_mach_avr25},
232 {"attiny45", AVR_ISA_AVR25, bfd_mach_avr25},
233 {"attiny85", AVR_ISA_AVR25, bfd_mach_avr25},
234 {"attiny261", AVR_ISA_AVR25, bfd_mach_avr25},
8453da2e 235 {"attiny261a", AVR_ISA_AVR25, bfd_mach_avr25},
7b21ac3f 236 {"attiny461", AVR_ISA_AVR25, bfd_mach_avr25},
e760a81b 237 {"attiny461a", AVR_ISA_AVR25, bfd_mach_avr25},
7b21ac3f 238 {"attiny861", AVR_ISA_AVR25, bfd_mach_avr25},
8453da2e 239 {"attiny861a", AVR_ISA_AVR25, bfd_mach_avr25},
2b02f87c 240 {"attiny87", AVR_ISA_AVR25, bfd_mach_avr25},
7b21ac3f
EW		 241 {"attiny43u", AVR_ISA_AVR25, bfd_mach_avr25},
242 {"attiny48", AVR_ISA_AVR25, bfd_mach_avr25},
243 {"attiny88", AVR_ISA_AVR25, bfd_mach_avr25},
255d9eec 244 {"attiny828", AVR_ISA_AVR25, bfd_mach_avr25},
7b21ac3f
EW		 245 {"at86rf401", AVR_ISA_RF401, bfd_mach_avr25},
246 {"at43usb355", AVR_ISA_AVR3, bfd_mach_avr3},
247 {"at76c711", AVR_ISA_AVR3, bfd_mach_avr3},
248 {"atmega103", AVR_ISA_AVR31, bfd_mach_avr31},
249 {"at43usb320", AVR_ISA_AVR31, bfd_mach_avr31},
250 {"attiny167", AVR_ISA_AVR35, bfd_mach_avr35},
251 {"at90usb82", AVR_ISA_AVR35, bfd_mach_avr35},
252 {"at90usb162", AVR_ISA_AVR35, bfd_mach_avr35},
255d9eec 253 {"ata5505", AVR_ISA_AVR35, bfd_mach_avr35},
11908008
EW		 254 {"atmega8u2", AVR_ISA_AVR35, bfd_mach_avr35},
255 {"atmega16u2", AVR_ISA_AVR35, bfd_mach_avr35},
256 {"atmega32u2", AVR_ISA_AVR35, bfd_mach_avr35},
255d9eec 257 {"attiny1634", AVR_ISA_AVR35, bfd_mach_avr35},
28c9d252 258 {"atmega8", AVR_ISA_M8, bfd_mach_avr4},
8be59acb 259 {"ata6289", AVR_ISA_AVR4, bfd_mach_avr4},
255d9eec
DC		 260 {"atmega8a", AVR_ISA_M8, bfd_mach_avr4},
261 {"ata6285", AVR_ISA_AVR4, bfd_mach_avr4},
262 {"ata6286", AVR_ISA_AVR4, bfd_mach_avr4},
7b21ac3f 263 {"atmega48", AVR_ISA_AVR4, bfd_mach_avr4},
e760a81b 264 {"atmega48a", AVR_ISA_AVR4, bfd_mach_avr4},
255d9eec 265 {"atmega48pa", AVR_ISA_AVR4, bfd_mach_avr4},
7b21ac3f
EW		 266 {"atmega48p", AVR_ISA_AVR4, bfd_mach_avr4},
267 {"atmega88", AVR_ISA_AVR4, bfd_mach_avr4},
e760a81b 268 {"atmega88a", AVR_ISA_AVR4, bfd_mach_avr4},
7b21ac3f 269 {"atmega88p", AVR_ISA_AVR4, bfd_mach_avr4},
e760a81b 270 {"atmega88pa", AVR_ISA_AVR4, bfd_mach_avr4},
28c9d252
NC		 271 {"atmega8515", AVR_ISA_M8, bfd_mach_avr4},
272 {"atmega8535", AVR_ISA_M8, bfd_mach_avr4},
7b21ac3f
EW		 273 {"atmega8hva", AVR_ISA_AVR4, bfd_mach_avr4},
274 {"at90pwm1", AVR_ISA_AVR4, bfd_mach_avr4},
275 {"at90pwm2", AVR_ISA_AVR4, bfd_mach_avr4},
276 {"at90pwm2b", AVR_ISA_AVR4, bfd_mach_avr4},
277 {"at90pwm3", AVR_ISA_AVR4, bfd_mach_avr4},
278 {"at90pwm3b", AVR_ISA_AVR4, bfd_mach_avr4},
2b02f87c 279 {"at90pwm81", AVR_ISA_AVR4, bfd_mach_avr4},
255d9eec
DC		 280 {"at90pwm161", AVR_ISA_AVR5, bfd_mach_avr5},
281 {"ata5790", AVR_ISA_AVR5, bfd_mach_avr5},
282 {"ata5795", AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 283 {"atmega16", AVR_ISA_AVR5, bfd_mach_avr5},
e760a81b 284 {"atmega16a", AVR_ISA_AVR5, bfd_mach_avr5},
28c9d252 285 {"atmega161", AVR_ISA_M161, bfd_mach_avr5},
7b21ac3f 286 {"atmega162", AVR_ISA_AVR5, bfd_mach_avr5},
28c9d252 287 {"atmega163", AVR_ISA_M161, bfd_mach_avr5},
e760a81b 288 {"atmega164a", AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 289 {"atmega164p", AVR_ISA_AVR5, bfd_mach_avr5},
255d9eec 290 {"atmega164pa",AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 291 {"atmega165", AVR_ISA_AVR5, bfd_mach_avr5},
e760a81b 292 {"atmega165a", AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 293 {"atmega165p", AVR_ISA_AVR5, bfd_mach_avr5},
255d9eec 294 {"atmega165pa",AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 295 {"atmega168", AVR_ISA_AVR5, bfd_mach_avr5},
e760a81b 296 {"atmega168a", AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 297 {"atmega168p", AVR_ISA_AVR5, bfd_mach_avr5},
255d9eec 298 {"atmega168pa",AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 299 {"atmega169", AVR_ISA_AVR5, bfd_mach_avr5},
e760a81b 300 {"atmega169a", AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 301 {"atmega169p", AVR_ISA_AVR5, bfd_mach_avr5},
e760a81b 302 {"atmega169pa",AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 303 {"atmega32", AVR_ISA_AVR5, bfd_mach_avr5},
255d9eec 304 {"atmega32a", AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 305 {"atmega323", AVR_ISA_AVR5, bfd_mach_avr5},
e760a81b 306 {"atmega324a", AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 307 {"atmega324p", AVR_ISA_AVR5, bfd_mach_avr5},
e760a81b 308 {"atmega324pa",AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 309 {"atmega325", AVR_ISA_AVR5, bfd_mach_avr5},
e760a81b 310 {"atmega325a", AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 311 {"atmega325p", AVR_ISA_AVR5, bfd_mach_avr5},
b8c610a7 312 {"atmega325pa",AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 313 {"atmega3250", AVR_ISA_AVR5, bfd_mach_avr5},
e760a81b 314 {"atmega3250a",AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 315 {"atmega3250p",AVR_ISA_AVR5, bfd_mach_avr5},
b8c610a7 316 {"atmega3250pa",AVR_ISA_AVR5, bfd_mach_avr5},
e760a81b 317 {"atmega328", AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f
EW		 318 {"atmega328p", AVR_ISA_AVR5, bfd_mach_avr5},
319 {"atmega329", AVR_ISA_AVR5, bfd_mach_avr5},
e760a81b 320 {"atmega329a", AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 321 {"atmega329p", AVR_ISA_AVR5, bfd_mach_avr5},
e760a81b 322 {"atmega329pa",AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 323 {"atmega3290", AVR_ISA_AVR5, bfd_mach_avr5},
e760a81b 324 {"atmega3290a",AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 325 {"atmega3290p",AVR_ISA_AVR5, bfd_mach_avr5},
b8c610a7 326 {"atmega3290pa",AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 327 {"atmega406", AVR_ISA_AVR5, bfd_mach_avr5},
255d9eec
DC		 328 {"atmega64rfr2", AVR_ISA_AVR5, bfd_mach_avr5},
329 {"atmega644rfr2",AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 330 {"atmega64", AVR_ISA_AVR5, bfd_mach_avr5},
255d9eec 331 {"atmega64a", AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f
EW		 332 {"atmega640", AVR_ISA_AVR5, bfd_mach_avr5},
333 {"atmega644", AVR_ISA_AVR5, bfd_mach_avr5},
e760a81b 334 {"atmega644a", AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 335 {"atmega644p", AVR_ISA_AVR5, bfd_mach_avr5},
8453da2e 336 {"atmega644pa",AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 337 {"atmega645", AVR_ISA_AVR5, bfd_mach_avr5},
e760a81b
EW		 338 {"atmega645a", AVR_ISA_AVR5, bfd_mach_avr5},
339 {"atmega645p", AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 340 {"atmega649", AVR_ISA_AVR5, bfd_mach_avr5},
e760a81b
EW		 341 {"atmega649a", AVR_ISA_AVR5, bfd_mach_avr5},
342 {"atmega649p", AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 343 {"atmega6450", AVR_ISA_AVR5, bfd_mach_avr5},
e760a81b
EW		 344 {"atmega6450a",AVR_ISA_AVR5, bfd_mach_avr5},
345 {"atmega6450p",AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 346 {"atmega6490", AVR_ISA_AVR5, bfd_mach_avr5},
e760a81b
EW		 347 {"atmega6490a",AVR_ISA_AVR5, bfd_mach_avr5},
348 {"atmega6490p",AVR_ISA_AVR5, bfd_mach_avr5},
4d13caa0
NC		 349 {"atmega64rfr2",AVR_ISA_AVR5, bfd_mach_avr5},
350 {"atmega644rfr2",AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 351 {"atmega16hva",AVR_ISA_AVR5, bfd_mach_avr5},
255d9eec 352 {"atmega16hva2",AVR_ISA_AVR5, bfd_mach_avr5},
2b02f87c 353 {"atmega16hvb",AVR_ISA_AVR5, bfd_mach_avr5},
b8c610a7 354 {"atmega16hvbrevb",AVR_ISA_AVR5,bfd_mach_avr5},
2b02f87c 355 {"atmega32hvb",AVR_ISA_AVR5, bfd_mach_avr5},
b8c610a7 356 {"atmega32hvbrevb",AVR_ISA_AVR5,bfd_mach_avr5},
e760a81b 357 {"atmega64hve",AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f
EW		 358 {"at90can32" , AVR_ISA_AVR5, bfd_mach_avr5},
359 {"at90can64" , AVR_ISA_AVR5, bfd_mach_avr5},
b8c610a7 360 {"at90pwm161", AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f
EW		 361 {"at90pwm216", AVR_ISA_AVR5, bfd_mach_avr5},
362 {"at90pwm316", AVR_ISA_AVR5, bfd_mach_avr5},
363 {"atmega32c1", AVR_ISA_AVR5, bfd_mach_avr5},
2b02f87c
NC		 364 {"atmega64c1", AVR_ISA_AVR5, bfd_mach_avr5},
365 {"atmega16m1", AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 366 {"atmega32m1", AVR_ISA_AVR5, bfd_mach_avr5},
2b02f87c
NC		 367 {"atmega64m1", AVR_ISA_AVR5, bfd_mach_avr5},
368 {"atmega16u4", AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 369 {"atmega32u4", AVR_ISA_AVR5, bfd_mach_avr5},
2b02f87c 370 {"atmega32u6", AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f
EW		 371 {"at90usb646", AVR_ISA_AVR5, bfd_mach_avr5},
372 {"at90usb647", AVR_ISA_AVR5, bfd_mach_avr5},
2b02f87c 373 {"at90scr100", AVR_ISA_AVR5, bfd_mach_avr5},
28c9d252 374 {"at94k", AVR_ISA_94K, bfd_mach_avr5},
e760a81b 375 {"m3000", AVR_ISA_AVR5, bfd_mach_avr5},
7b21ac3f 376 {"atmega128", AVR_ISA_AVR51, bfd_mach_avr51},
255d9eec 377 {"atmega128a", AVR_ISA_AVR51, bfd_mach_avr51},
7b21ac3f
EW		 378 {"atmega1280", AVR_ISA_AVR51, bfd_mach_avr51},
379 {"atmega1281", AVR_ISA_AVR51, bfd_mach_avr51},
255d9eec 380 {"atmega1284", AVR_ISA_AVR51, bfd_mach_avr51},
7b21ac3f 381 {"atmega1284p",AVR_ISA_AVR51, bfd_mach_avr51},
17f4880d 382 {"atmega128rfa1",AVR_ISA_AVR51, bfd_mach_avr51},
4d13caa0
NC		 383 {"atmega128rfr2",AVR_ISA_AVR51, bfd_mach_avr51},
384 {"atmega1284rfr2",AVR_ISA_AVR51, bfd_mach_avr51},
7b21ac3f
EW		 385 {"at90can128", AVR_ISA_AVR51, bfd_mach_avr51},
386 {"at90usb1286",AVR_ISA_AVR51, bfd_mach_avr51},
387 {"at90usb1287",AVR_ISA_AVR51, bfd_mach_avr51},
388 {"atmega2560", AVR_ISA_AVR6, bfd_mach_avr6},
389 {"atmega2561", AVR_ISA_AVR6, bfd_mach_avr6},
4d13caa0
NC		 390 {"atmega256rfr2", AVR_ISA_AVR6, bfd_mach_avr6},
391 {"atmega2564rfr2", AVR_ISA_AVR6, bfd_mach_avr6},
8cc66334 392 {"atxmega16a4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
255d9eec
DC		 393 {"atxmega16a4u",AVR_ISA_XMEGAU, bfd_mach_avrxmega2},
394 {"atxmega16c4", AVR_ISA_XMEGAU, bfd_mach_avrxmega2},
8cc66334
EW		 395 {"atxmega16d4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
396 {"atxmega32a4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
255d9eec
DC		 397 {"atxmega32a4u",AVR_ISA_XMEGAU, bfd_mach_avrxmega2},
398 {"atxmega32c4", AVR_ISA_XMEGAU, bfd_mach_avrxmega2},
8cc66334 399 {"atxmega32d4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
255d9eec
DC		 400 {"atxmega32e5", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
401 {"atxmega16e5", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
402 {"atxmega8e5", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
6f8a4444 403 {"atxmega32x1", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
f27dadca
GJL		 404 {"attiny212", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
405 {"attiny214", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
406 {"attiny412", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
407 {"attiny414", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
f4203b2b
JL		 408 {"attiny416", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
409 {"attiny417", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
f27dadca 410 {"attiny814", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
f4203b2b
JL		 411 {"attiny816", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
412 {"attiny817", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
f27dadca
GJL		 413 {"attiny1614", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
414 {"attiny1616", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
415 {"attiny1617", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
416 {"attiny3214", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
417 {"attiny3216", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
418 {"attiny3217", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
8cc66334 419 {"atxmega64a3", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
255d9eec
DC		 420 {"atxmega64a3u",AVR_ISA_XMEGAU, bfd_mach_avrxmega4},
421 {"atxmega64a4u",AVR_ISA_XMEGAU, bfd_mach_avrxmega4},
422 {"atxmega64b1", AVR_ISA_XMEGAU, bfd_mach_avrxmega4},
423 {"atxmega64b3", AVR_ISA_XMEGAU, bfd_mach_avrxmega4},
424 {"atxmega64c3", AVR_ISA_XMEGAU, bfd_mach_avrxmega4},
8cc66334 425 {"atxmega64d3", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
255d9eec 426 {"atxmega64d4", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
8cc66334 427 {"atxmega64a1", AVR_ISA_XMEGA, bfd_mach_avrxmega5},
7bab7634 428 {"atxmega64a1u",AVR_ISA_XMEGAU, bfd_mach_avrxmega5},
8cc66334 429 {"atxmega128a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
255d9eec 430 {"atxmega128a3u",AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
7bab7634 431 {"atxmega128b1", AVR_ISA_XMEGAU, bfd_mach_avrxmega6},
255d9eec
DC		 432 {"atxmega128b3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
433 {"atxmega128c3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
8cc66334 434 {"atxmega128d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
255d9eec 435 {"atxmega128d4", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
8cc66334 436 {"atxmega192a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
255d9eec
DC		 437 {"atxmega192a3u",AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
438 {"atxmega192c3", AVR_ISA_XMEGAU, bfd_mach_avrxmega6},
8cc66334
EW		 439 {"atxmega192d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
440 {"atxmega256a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
255d9eec 441 {"atxmega256a3u",AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
8cc66334 442 {"atxmega256a3b",AVR_ISA_XMEGA, bfd_mach_avrxmega6},
7bab7634 443 {"atxmega256a3bu",AVR_ISA_XMEGAU, bfd_mach_avrxmega6},
255d9eec 444 {"atxmega256c3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
8cc66334 445 {"atxmega256d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
255d9eec
DC		 446 {"atxmega384c3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
447 {"atxmega384d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
8cc66334 448 {"atxmega128a1", AVR_ISA_XMEGA, bfd_mach_avrxmega7},
7bab7634 449 {"atxmega128a1u", AVR_ISA_XMEGAU, bfd_mach_avrxmega7},
255d9eec 450 {"atxmega128a4u", AVR_ISA_XMEGAU, bfd_mach_avrxmega7},
f36e8886
BS		 451 {"attiny4", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
452 {"attiny5", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
453 {"attiny9", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
454 {"attiny10", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
455 {"attiny20", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
456 {"attiny40", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
adde6300
AM		 457 {NULL, 0, 0}
458};
459
af910977 460
adde6300 461/* Current MCU type. */
7b21ac3f 462static struct mcu_type_s default_mcu = {"avr2", AVR_ISA_AVR2, bfd_mach_avr2};
af910977 463static struct mcu_type_s specified_mcu;
dc191a8f 464static struct mcu_type_s * avr_mcu = & default_mcu;
adde6300 465
00d2865b
NC		 466/* AVR target-specific switches. */
467struct avr_opt_s
468{
dc191a8f
NC		 469 int all_opcodes; /* -mall-opcodes: accept all known AVR opcodes. */
470 int no_skip_bug; /* -mno-skip-bug: no warnings for skipping 2-word insns. */
471 int no_wrap; /* -mno-wrap: reject rjmp/rcall with 8K wrap-around. */
edc9e9a6
AB		 472 int no_link_relax; /* -mno-link-relax / -mlink-relax: generate (or not)
473 relocations for linker relaxation. */
32f76c67 474 int have_gccisr; /* Whether "__gcc_isr" is a known (pseudo) insn. */
00d2865b
NC		 475};
476
32f76c67 477static struct avr_opt_s avr_opt = { 0, 0, 0, 0, 0 };
00d2865b 478
adde6300
AM		 479const char EXP_CHARS[] = "eE";
480const char FLT_CHARS[] = "dD";
dc191a8f
NC		 481
482static void avr_set_arch (int);
adde6300
AM		 483
484/* The target specific pseudo-ops which we support. */
485const pseudo_typeS md_pseudo_table[] =
486{
487 {"arch", avr_set_arch, 0},
488 { NULL, NULL, 0}
489};
490
491#define LDI_IMMEDIATE(x) (((x) & 0xf) | (((x) << 4) & 0xf00))
adde6300 492
dc191a8f
NC		 493#define EXP_MOD_NAME(i) exp_mod[i].name
494#define EXP_MOD_RELOC(i) exp_mod[i].reloc
495#define EXP_MOD_NEG_RELOC(i) exp_mod[i].neg_reloc
496#define HAVE_PM_P(i) exp_mod[i].have_pm
adde6300
AM		 497
498struct exp_mod_s
499{
e0471c16 500 const char * name;
dc191a8f
NC		 501 bfd_reloc_code_real_type reloc;
502 bfd_reloc_code_real_type neg_reloc;
503 int have_pm;
adde6300
AM		 504};
505
c6a7ab1f
NC		 506static struct exp_mod_s exp_mod[] =
507{
adde6300
AM		 508 {"hh8", BFD_RELOC_AVR_HH8_LDI, BFD_RELOC_AVR_HH8_LDI_NEG, 1},
509 {"pm_hh8", BFD_RELOC_AVR_HH8_LDI_PM, BFD_RELOC_AVR_HH8_LDI_PM_NEG, 0},
510 {"hi8", BFD_RELOC_AVR_HI8_LDI, BFD_RELOC_AVR_HI8_LDI_NEG, 1},
511 {"pm_hi8", BFD_RELOC_AVR_HI8_LDI_PM, BFD_RELOC_AVR_HI8_LDI_PM_NEG, 0},
512 {"lo8", BFD_RELOC_AVR_LO8_LDI, BFD_RELOC_AVR_LO8_LDI_NEG, 1},
513 {"pm_lo8", BFD_RELOC_AVR_LO8_LDI_PM, BFD_RELOC_AVR_LO8_LDI_PM_NEG, 0},
df406460 514 {"hlo8", BFD_RELOC_AVR_HH8_LDI, BFD_RELOC_AVR_HH8_LDI_NEG, 0},
e4efb665 515 {"hhi8", BFD_RELOC_AVR_MS8_LDI, BFD_RELOC_AVR_MS8_LDI_NEG, 0},
adde6300
AM		 516};
517
2b0f3761 518/* A union used to store indices into the exp_mod[] array
8ad7c533
NC		 519 in a hash table which expects void * data types. */
520typedef union
521{
522 void * ptr;
523 int index;
524} mod_index;
525
adde6300
AM		 526/* Opcode hash table. */
527static struct hash_control *avr_hash;
528
529/* Reloc modifiers hash control (hh8,hi8,lo8,pm_xx). */
530static struct hash_control *avr_mod_hash;
531
32f76c67
GJL		 532/* Whether some opcode does not change SREG. */
533static struct hash_control *avr_no_sreg_hash;
534
535static const char* const avr_no_sreg[] =
536 {
537 /* Arithmetic */
538 "ldi", "swap", "mov", "movw",
539 /* Special instructions. I-Flag will be restored by RETI, and we don't
540 consider I-Flag as being clobbered when changed. */
541 "sei", "cli", "reti", "brie", "brid",
542 "nop", "wdr", "sleep",
543 /* Load / Store */
544 "ld", "ldd", "lds", "pop", "in", "lpm", "elpm",
545 "st", "std", "sts", "push", "out",
546 /* Jumps and Calls. Calls might call code that changes SREG.
547 GCC has to filter out ABI calls. The non-ABI transparent calls
548 must use [R]CALL and are filtered out now by not mentioning them. */
549 "rjmp", "jmp", "ijmp", "ret",
550 /* Skipping. Branches need SREG to be set, hence we regard them
551 as if they changed SREG and don't list them here. */
552 "sbrc", "sbrs", "sbic", "sbis", "cpse",
553 /* I/O Manipulation */
554 "sbi", "cbi",
555 /* Read-Modify-Write */
556 "lac", "las", "lat", "xch"
557 };
558
00d2865b 559#define OPTION_MMCU 'm'
dc191a8f
NC		 560enum options
561{
562 OPTION_ALL_OPCODES = OPTION_MD_BASE + 1,
563 OPTION_NO_SKIP_BUG,
af910977 564 OPTION_NO_WRAP,
e4ef1b6c 565 OPTION_ISA_RMW,
edc9e9a6 566 OPTION_LINK_RELAX,
32f76c67
GJL		 567 OPTION_NO_LINK_RELAX,
568 OPTION_HAVE_GCCISR
dc191a8f 569};
adde6300 570
c6a7ab1f
NC		 571struct option md_longopts[] =
572{
00d2865b
NC		 573 { "mmcu", required_argument, NULL, OPTION_MMCU },
574 { "mall-opcodes", no_argument, NULL, OPTION_ALL_OPCODES },
575 { "mno-skip-bug", no_argument, NULL, OPTION_NO_SKIP_BUG },
576 { "mno-wrap", no_argument, NULL, OPTION_NO_WRAP },
af910977 577 { "mrmw", no_argument, NULL, OPTION_ISA_RMW },
e4ef1b6c 578 { "mlink-relax", no_argument, NULL, OPTION_LINK_RELAX },
edc9e9a6 579 { "mno-link-relax", no_argument, NULL, OPTION_NO_LINK_RELAX },
32f76c67 580 { "mgcc-isr", no_argument, NULL, OPTION_HAVE_GCCISR },
00d2865b 581 { NULL, no_argument, NULL, 0 }
adde6300 582};
adde6300 583
c6a7ab1f 584size_t md_longopts_size = sizeof (md_longopts);
00d2865b
NC		 585
586/* Display nicely formatted list of known MCU names. */
c6a7ab1f 587
00d2865b 588static void
dc191a8f 589show_mcu_list (FILE *stream)
00d2865b
NC		 590{
591 int i, x;
592
593 fprintf (stream, _("Known MCU names:"));
594 x = 1000;
1dab94dd 595
00d2865b
NC		 596 for (i = 0; mcu_types[i].name; i++)
597 {
598 int len = strlen (mcu_types[i].name);
1dab94dd 599
00d2865b 600 x += len + 1;
1dab94dd 601
00d2865b 602 if (x < 75)
c6a7ab1f 603 fprintf (stream, " %s", mcu_types[i].name);
00d2865b
NC		 604 else
605 {
606 fprintf (stream, "\n %s", mcu_types[i].name);
607 x = len + 2;
608 }
609 }
1dab94dd 610
c6a7ab1f 611 fprintf (stream, "\n");
00d2865b
NC		 612}
613
adde6300 614static inline char *
dc191a8f 615skip_space (char *s)
adde6300
AM		 616{
617 while (*s == ' ' || *s == '\t')
618 ++s;
619 return s;
620}
621
622/* Extract one word from FROM and copy it to TO. */
c6a7ab1f 623
adde6300
AM		 624static char *
625extract_word (char *from, char *to, int limit)
626{
adde6300
AM		 627 char *op_end;
628 int size = 0;
629
630 /* Drop leading whitespace. */
631 from = skip_space (from);
632 *to = 0;
c6a7ab1f 633
adde6300 634 /* Find the op code end. */
87975d2a 635 for (op_end = from; *op_end != 0 && is_part_of_name (*op_end);)
adde6300
AM		 636 {
637 to[size++] = *op_end++;
638 if (size + 1 >= limit)
639 break;
640 }
1dab94dd 641
adde6300
AM		 642 to[size] = 0;
643 return op_end;
644}
645
646int
dc191a8f
NC		 647md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
648 asection *seg ATTRIBUTE_UNUSED)
adde6300
AM		 649{
650 abort ();
651 return 0;
652}
653
654void
dc191a8f 655md_show_usage (FILE *stream)
adde6300 656{
00d2865b 657 fprintf (stream,
4fb8d1c6 658 _("AVR Assembler options:\n"
adde6300
AM		 659 " -mmcu=[avr-name] select microcontroller variant\n"
660 " [avr-name] can be:\n"
7b21ac3f
EW		 661 " avr1 - classic AVR core without data RAM\n"
662 " avr2 - classic AVR core with up to 8K program memory\n"
663 " avr25 - classic AVR core with up to 8K program memory\n"
664 " plus the MOVW instruction\n"
665 " avr3 - classic AVR core with up to 64K program memory\n"
666 " avr31 - classic AVR core with up to 128K program memory\n"
667 " avr35 - classic AVR core with up to 64K program memory\n"
668 " plus the MOVW instruction\n"
669 " avr4 - enhanced AVR core with up to 8K program memory\n"
670 " avr5 - enhanced AVR core with up to 64K program memory\n"
671 " avr51 - enhanced AVR core with up to 128K program memory\n"
672 " avr6 - enhanced AVR core with up to 256K program memory\n"
8c997c27 673 " avrxmega2 - XMEGA, > 8K, < 64K FLASH, < 64K RAM\n"
f27dadca 674 " avrxmega3 - XMEGA, RAM + FLASH < 64K, Flash visible in RAM\n"
8cc66334
EW		 675 " avrxmega4 - XMEGA, > 64K, <= 128K FLASH, <= 64K RAM\n"
676 " avrxmega5 - XMEGA, > 64K, <= 128K FLASH, > 64K RAM\n"
677 " avrxmega6 - XMEGA, > 128K, <= 256K FLASH, <= 64K RAM\n"
678 " avrxmega7 - XMEGA, > 128K, <= 256K FLASH, > 64K RAM\n"
f36e8886 679 " avrtiny - AVR Tiny core with 16 gp registers\n"));
00d2865b
NC		 680 fprintf (stream,
681 _(" -mall-opcodes accept all AVR opcodes, even if not supported by MCU\n"
682 " -mno-skip-bug disable warnings for skipping two-word instructions\n"
683 " (default for avr4, avr5)\n"
684 " -mno-wrap reject rjmp/rcall instructions with 8K wrap-around\n"
af910977
DC		 685 " (default for avr3, avr5)\n"
686 " -mrmw accept Read-Modify-Write instructions\n"
edc9e9a6
AB		 687 " -mlink-relax generate relocations for linker relaxation (default)\n"
688 " -mno-link-relax don't generate relocations for linker relaxation.\n"
32f76c67 689 " -mgcc-isr accept the __gcc_isr pseudo-instruction.\n"
edc9e9a6 690 ));
00d2865b 691 show_mcu_list (stream);
adde6300
AM		 692}
693
694static void
dc191a8f 695avr_set_arch (int dummy ATTRIBUTE_UNUSED)
adde6300 696{
dc191a8f 697 char str[20];
1dab94dd 698
adde6300 699 input_line_pointer = extract_word (input_line_pointer, str, 20);
00d2865b 700 md_parse_option (OPTION_MMCU, str);
adde6300
AM		 701 bfd_set_arch_mach (stdoutput, TARGET_ARCH, avr_mcu->mach);
702}
703
704int
17b9d67d 705md_parse_option (int c, const char *arg)
adde6300 706{
00d2865b 707 switch (c)
adde6300 708 {
00d2865b
NC		 709 case OPTION_MMCU:
710 {
711 int i;
00d2865b
NC		 712
713 for (i = 0; mcu_types[i].name; ++i)
f73e41ef 714 if (strcasecmp (mcu_types[i].name, arg) == 0)
00d2865b 715 break;
adde6300 716
00d2865b
NC		 717 if (!mcu_types[i].name)
718 {
719 show_mcu_list (stderr);
720 as_fatal (_("unknown MCU: %s\n"), arg);
721 }
65aa24b6 722
00d2865b
NC		 723 /* It is OK to redefine mcu type within the same avr[1-5] bfd machine
724 type - this for allows passing -mmcu=... via gcc ASM_SPEC as well
725 as .arch ... in the asm output at the same time. */
00d2865b 726 if (avr_mcu == &default_mcu || avr_mcu->mach == mcu_types[i].mach)
e1fa0163
NC		 727 {
728 specified_mcu.name = mcu_types[i].name;
729 specified_mcu.isa |= mcu_types[i].isa;
730 specified_mcu.mach = mcu_types[i].mach;
731 avr_mcu = &specified_mcu;
732 }
00d2865b
NC		 733 else
734 as_fatal (_("redefinition of mcu type `%s' to `%s'"),
735 avr_mcu->name, mcu_types[i].name);
736 return 1;
737 }
738 case OPTION_ALL_OPCODES:
739 avr_opt.all_opcodes = 1;
740 return 1;
741 case OPTION_NO_SKIP_BUG:
742 avr_opt.no_skip_bug = 1;
743 return 1;
744 case OPTION_NO_WRAP:
745 avr_opt.no_wrap = 1;
adde6300 746 return 1;
af910977
DC		 747 case OPTION_ISA_RMW:
748 specified_mcu.isa |= AVR_ISA_RMW;
749 return 1;
e4ef1b6c 750 case OPTION_LINK_RELAX:
edc9e9a6
AB		 751 avr_opt.no_link_relax = 0;
752 return 1;
753 case OPTION_NO_LINK_RELAX:
754 avr_opt.no_link_relax = 1;
e4ef1b6c 755 return 1;
32f76c67
GJL		 756 case OPTION_HAVE_GCCISR:
757 avr_opt.have_gccisr = 1;
758 return 1;
adde6300 759 }
1dab94dd 760
adde6300
AM		 761 return 0;
762}
763
32f76c67
GJL		 764
765/* Implement `md_undefined_symbol' */
766/* If we are in `__gcc_isr' chunk, pop up `__gcc_isr.n_pushed.<NUM>'
767 instead of `__gcc_isr.n_pushed'. This will be resolved by the Done
768 chunk in `avr_patch_gccisr_frag' to the number of PUSHes produced by
769 the Prologue chunk. */
770
adde6300 771symbolS *
32f76c67 772avr_undefined_symbol (char *name)
adde6300 773{
32f76c67
GJL		 774 if (ISR_CHUNK_Done != avr_isr.prev_chunk
775 && 0 == strcmp (name, "__gcc_isr.n_pushed"))
776 {
777 if (!avr_isr.sym_n_pushed)
778 {
779 static unsigned suffix;
780 char xname[30];
781 sprintf (xname, "%s.%03u", name, (++suffix) % 1000);
782 avr_isr.sym_n_pushed = symbol_new (xname, undefined_section,
783 (valueT) 0, &zero_address_frag);
784 }
785 return avr_isr.sym_n_pushed;
786 }
787
dc191a8f 788 return NULL;
adde6300
AM		 789}
790
6d4af3c2 791const char *
dc191a8f 792md_atof (int type, char *litP, int *sizeP)
adde6300 793{
499ac353 794 return ieee_md_atof (type, litP, sizeP, FALSE);
adde6300
AM		 795}
796
797void
dc191a8f
NC		 798md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
799 asection *sec ATTRIBUTE_UNUSED,
800 fragS *fragP ATTRIBUTE_UNUSED)
adde6300
AM		 801{
802 abort ();
803}
804
adde6300 805void
dc191a8f 806md_begin (void)
adde6300 807{
df136245 808 unsigned int i;
adde6300 809 struct avr_opcodes_s *opcode;
dc191a8f 810
c6a7ab1f 811 avr_hash = hash_new ();
adde6300
AM		 812
813 /* Insert unique names into hash table. This hash table then provides a
814 quick index to the first opcode with a particular name in the opcode
815 table. */
adde6300
AM		 816 for (opcode = avr_opcodes; opcode->name; opcode++)
817 hash_insert (avr_hash, opcode->name, (char *) opcode);
818
819 avr_mod_hash = hash_new ();
820
dc191a8f 821 for (i = 0; i < ARRAY_SIZE (exp_mod); ++i)
8ad7c533
NC		 822 {
823 mod_index m;
824
825 m.index = i + 10;
826 hash_insert (avr_mod_hash, EXP_MOD_NAME (i), m.ptr);
827 }
c6a7ab1f 828
32f76c67
GJL		 829 avr_no_sreg_hash = hash_new ();
830
831 for (i = 0; i < ARRAY_SIZE (avr_no_sreg); ++i)
832 {
833 gas_assert (hash_find (avr_hash, avr_no_sreg[i]));
834 hash_insert (avr_no_sreg_hash, avr_no_sreg[i], (char*) 4 /* dummy */);
835 }
836
837 avr_gccisr_opcode = (struct avr_opcodes_s*) hash_find (avr_hash, "__gcc_isr");
838 gas_assert (avr_gccisr_opcode);
839
adde6300 840 bfd_set_arch_mach (stdoutput, TARGET_ARCH, avr_mcu->mach);
edc9e9a6 841 linkrelax = !avr_opt.no_link_relax;
adde6300
AM		 842}
843
df136245 844/* Resolve STR as a constant expression and return the result.
c6a7ab1f 845 If result greater than MAX then error. */
df136245
DC		 846
847static unsigned int
dc191a8f 848avr_get_constant (char *str, int max)
df136245
DC		 849{
850 expressionS ex;
dc191a8f 851
df136245
DC		 852 str = skip_space (str);
853 input_line_pointer = str;
dc191a8f 854 expression (& ex);
df136245
DC		 855
856 if (ex.X_op != O_constant)
857 as_bad (_("constant value required"));
858
859 if (ex.X_add_number > max || ex.X_add_number < 0)
73f4d86e 860 as_bad (_("number must be positive and less than %d"), max + 1);
1dab94dd 861
df136245
DC		 862 return ex.X_add_number;
863}
864
dc191a8f 865/* Parse for ldd/std offset. */
df136245 866
dc191a8f
NC		 867static void
868avr_offset_expression (expressionS *exp)
adde6300 869{
dc191a8f
NC		 870 char *str = input_line_pointer;
871 char *tmp;
872 char op[8];
adde6300 873
dc191a8f
NC		 874 tmp = str;
875 str = extract_word (str, op, sizeof (op));
876
877 input_line_pointer = tmp;
878 expression (exp);
879
880 /* Warn about expressions that fail to use lo8 (). */
881 if (exp->X_op == O_constant)
adde6300 882 {
dc191a8f 883 int x = exp->X_add_number;
28c9d252 884
dc191a8f
NC		 885 if (x < -255 || x > 255)
886 as_warn (_("constant out of 8-bit range: %d"), x);
887 }
888}
adde6300 889
dc191a8f 890/* Parse ordinary expression. */
adde6300 891
dc191a8f
NC		 892static char *
893parse_exp (char *s, expressionS *op)
894{
895 input_line_pointer = s;
896 expression (op);
897 if (op->X_op == O_absent)
898 as_bad (_("missing operand"));
899 return input_line_pointer;
900}
1dab94dd 901
dc191a8f
NC		 902/* Parse special expressions (needed for LDI command):
903 xx8 (address)
904 xx8 (-address)
905 pm_xx8 (address)
906 pm_xx8 (-address)
907 where xx is: hh, hi, lo. */
adde6300 908
dc191a8f
NC		 909static bfd_reloc_code_real_type
910avr_ldi_expression (expressionS *exp)
911{
912 char *str = input_line_pointer;
913 char *tmp;
914 char op[8];
915 int mod;
28c9d252
NC		 916 int linker_stubs_should_be_generated = 0;
917
dc191a8f 918 tmp = str;
adde6300 919
dc191a8f 920 str = extract_word (str, op, sizeof (op));
adde6300 921
dc191a8f
NC		 922 if (op[0])
923 {
8ad7c533 924 mod_index m;
28c9d252 925
8ad7c533
NC		 926 m.ptr = hash_find (avr_mod_hash, op);
927 mod = m.index;
1dab94dd 928
dc191a8f
NC		 929 if (mod)
930 {
931 int closes = 0;
b170af93 932
dc191a8f
NC		 933 mod -= 10;
934 str = skip_space (str);
00d2865b 935
dc191a8f
NC		 936 if (*str == '(')
937 {
28c9d252 938 bfd_reloc_code_real_type reloc_to_return;
dc191a8f 939 int neg_p = 0;
00d2865b 940
dc191a8f 941 ++str;
00d2865b 942
dc191a8f 943 if (strncmp ("pm(", str, 3) == 0
28c9d252
NC		 944 || strncmp ("gs(",str,3) == 0
945 || strncmp ("-(gs(",str,5) == 0
dc191a8f
NC		 946 || strncmp ("-(pm(", str, 5) == 0)
947 {
948 if (HAVE_PM_P (mod))
949 {
950 ++mod;
951 ++closes;
952 }
953 else
954 as_bad (_("illegal expression"));
b170af93 955
28c9d252
NC		 956 if (str[0] == 'g' || str[2] == 'g')
957 linker_stubs_should_be_generated = 1;
958
dc191a8f
NC		 959 if (*str == '-')
960 {
961 neg_p = 1;
962 ++closes;
963 str += 5;
964 }
965 else
966 str += 3;
967 }
adde6300 968
dc191a8f
NC		 969 if (*str == '-' && *(str + 1) == '(')
970 {
971 neg_p ^= 1;
972 ++closes;
973 str += 2;
974 }
750bce0e 975
dc191a8f
NC		 976 input_line_pointer = str;
977 expression (exp);
750bce0e 978
dc191a8f
NC		 979 do
980 {
981 if (*input_line_pointer != ')')
982 {
983 as_bad (_("`)' required"));
984 break;
985 }
986 input_line_pointer++;
987 }
988 while (closes--);
989
28c9d252
NC		 990 reloc_to_return =
991 neg_p ? EXP_MOD_NEG_RELOC (mod) : EXP_MOD_RELOC (mod);
992 if (linker_stubs_should_be_generated)
993 {
994 switch (reloc_to_return)
995 {
996 case BFD_RELOC_AVR_LO8_LDI_PM:
997 reloc_to_return = BFD_RELOC_AVR_LO8_LDI_GS;
998 break;
999 case BFD_RELOC_AVR_HI8_LDI_PM:
1000 reloc_to_return = BFD_RELOC_AVR_HI8_LDI_GS;
1001 break;
1002
1003 default:
0a903bab
NC		 1004 /* PR 5523: Do not generate a warning here,
1005 legitimate code can trigger this case. */
1006 break;
28c9d252
NC		 1007 }
1008 }
1009 return reloc_to_return;
dc191a8f
NC		 1010 }
1011 }
1012 }
750bce0e
NC		 1013
1014 input_line_pointer = tmp;
1015 expression (exp);
1016
1017 /* Warn about expressions that fail to use lo8 (). */
1018 if (exp->X_op == O_constant)
1019 {
1020 int x = exp->X_add_number;
dc191a8f 1021
750bce0e
NC		 1022 if (x < -255 || x > 255)
1023 as_warn (_("constant out of 8-bit range: %d"), x);
1024 }
dc191a8f
NC		 1025
1026 return BFD_RELOC_AVR_LDI;
750bce0e
NC		 1027}
1028
df136245 1029/* Parse one instruction operand.
c6a7ab1f
NC		 1030 Return operand bitmask. Also fixups can be generated. */
1031
adde6300 1032static unsigned int
dc191a8f
NC		 1033avr_operand (struct avr_opcodes_s *opcode,
1034 int where,
e0471c16 1035 const char *op,
32f76c67
GJL		 1036 char **line,
1037 int *pregno)
adde6300 1038{
adde6300 1039 expressionS op_expr;
df136245
DC		 1040 unsigned int op_mask = 0;
1041 char *str = skip_space (*line);
adde6300 1042
adde6300
AM		 1043 switch (*op)
1044 {
1045 /* Any register operand. */
1046 case 'w':
1047 case 'd':
1048 case 'r':
b170af93
DC		 1049 case 'a':
1050 case 'v':
75f58085
BS		 1051 {
1052 char * old_str = str;
1053 char *lower;
1054 char r_name[20];
1dab94dd 1055
75f58085
BS		 1056 str = extract_word (str, r_name, sizeof (r_name));
1057 for (lower = r_name; *lower; ++lower)
1058 {
1059 if (*lower >= 'A' && *lower <= 'Z')
1060 *lower += 'a' - 'A';
1061 }
1062
1063 if (r_name[0] == 'r' && ISDIGIT (r_name[1]) && r_name[2] == 0)
1064 /* Single-digit register number, ie r0-r9. */
1065 op_mask = r_name[1] - '0';
1066 else if (r_name[0] == 'r' && ISDIGIT (r_name[1])
1067 && ISDIGIT (r_name[2]) && r_name[3] == 0)
1068 /* Double-digit register number, ie r10 - r32. */
1069 op_mask = (r_name[1] - '0') * 10 + r_name[2] - '0';
1070 else if (r_name[0] >= 'x' && r_name[0] <= 'z'
1071 && (r_name[1] == 'l' || r_name[1] == 'h') && r_name[2] == 0)
1072 /* Registers r26-r31 referred to by name, ie xl, xh, yl, yh, zl, zh. */
1073 op_mask = (r_name[0] - 'x') * 2 + (r_name[1] == 'h') + 26;
1074 else if ((*op == 'v' || *op == 'w')
1075 && r_name[0] >= 'x' && r_name[0] <= 'z' && r_name[1] == 0)
1076 /* For the movw and addiw instructions, refer to registers x, y and z by name. */
1077 op_mask = (r_name[0] - 'x') * 2 + 26;
1078 else
1079 {
1080 /* Numeric or symbolic constant register number. */
1081 op_mask = avr_get_constant (old_str, 31);
1082 str = input_line_pointer;
1083 }
1084 }
f36e8886 1085
32f76c67
GJL		 1086 if (pregno)
1087 *pregno = op_mask;
1088
f36e8886
BS		 1089 if (avr_mcu->mach == bfd_mach_avrtiny)
1090 {
1091 if (op_mask < 16 || op_mask > 31)
1092 {
1093 as_bad (_("register name or number from 16 to 31 required"));
1094 break;
1095 }
1096 }
1097 else if (op_mask > 31)
1098 {
1099 as_bad (_("register name or number from 0 to 31 required"));
1100 break;
1101 }
1dab94dd 1102
c6a7ab1f
NC		 1103 switch (*op)
1104 {
1105 case 'a':
1106 if (op_mask < 16 || op_mask > 23)
1107 as_bad (_("register r16-r23 required"));
1108 op_mask -= 16;
1109 break;
1dab94dd 1110
c6a7ab1f
NC		 1111 case 'd':
1112 if (op_mask < 16)
1113 as_bad (_("register number above 15 required"));
1114 op_mask -= 16;
1115 break;
1dab94dd 1116
c6a7ab1f
NC		 1117 case 'v':
1118 if (op_mask & 1)
1119 as_bad (_("even register number required"));
1120 op_mask >>= 1;
1121 break;
1dab94dd 1122
c6a7ab1f 1123 case 'w':
65b1d096 1124 if ((op_mask & 1) || op_mask < 24)
c6a7ab1f 1125 as_bad (_("register r24, r26, r28 or r30 required"));
65b1d096 1126 op_mask = (op_mask - 24) >> 1;
c6a7ab1f
NC		 1127 break;
1128 }
1129 break;
adde6300
AM		 1130
1131 case 'e':
1132 {
1133 char c;
1dab94dd 1134
adde6300
AM		 1135 if (*str == '-')
1136 {
c6a7ab1f 1137 str = skip_space (str + 1);
adde6300
AM		 1138 op_mask = 0x1002;
1139 }
3882b010 1140 c = TOLOWER (*str);
adde6300
AM		 1141 if (c == 'x')
1142 op_mask |= 0x100c;
1143 else if (c == 'y')
1144 op_mask |= 0x8;
1145 else if (c != 'z')
00d2865b 1146 as_bad (_("pointer register (X, Y or Z) required"));
adde6300 1147
c6a7ab1f 1148 str = skip_space (str + 1);
adde6300
AM		 1149 if (*str == '+')
1150 {
1151 ++str;
1152 if (op_mask & 2)
00d2865b 1153 as_bad (_("cannot both predecrement and postincrement"));
adde6300
AM		 1154 op_mask |= 0x1001;
1155 }
e38c9cc2 1156
1188e082 1157 /* avr1 can do "ld r,Z" and "st Z,r" but no other pointer
e38c9cc2 1158 registers, no predecrement, no postincrement. */
00d2865b
NC		 1159 if (!avr_opt.all_opcodes && (op_mask & 0x100F)
1160 && !(avr_mcu->isa & AVR_ISA_SRAM))
1161 as_bad (_("addressing mode not supported"));
adde6300
AM		 1162 }
1163 break;
1164
b170af93 1165 case 'z':
c6a7ab1f
NC		 1166 if (*str == '-')
1167 as_bad (_("can't predecrement"));
1dab94dd 1168
c6a7ab1f
NC		 1169 if (! (*str == 'z' || *str == 'Z'))
1170 as_bad (_("pointer register Z required"));
1dab94dd 1171
c6a7ab1f
NC		 1172 str = skip_space (str + 1);
1173
1174 if (*str == '+')
1175 {
1176 ++str;
e0471c16 1177 const char *s;
8cc66334
EW		 1178 for (s = opcode->opcode; *s; ++s)
1179 {
1180 if (*s == '+')
1181 op_mask |= (1 << (15 - (s - opcode->opcode)));
1182 }
c6a7ab1f 1183 }
d669d37f
NC		 1184
1185 /* attiny26 can do "lpm" and "lpm r,Z" but not "lpm r,Z+". */
1186 if (!avr_opt.all_opcodes
1187 && (op_mask & 0x0001)
1188 && !(avr_mcu->isa & AVR_ISA_MOVW))
1189 as_bad (_("postincrement not supported"));
b170af93
DC		 1190 break;
1191
adde6300
AM		 1192 case 'b':
1193 {
3882b010 1194 char c = TOLOWER (*str++);
1dab94dd 1195
adde6300
AM		 1196 if (c == 'y')
1197 op_mask |= 0x8;
1198 else if (c != 'z')
00d2865b 1199 as_bad (_("pointer register (Y or Z) required"));
adde6300
AM		 1200 str = skip_space (str);
1201 if (*str++ == '+')
1202 {
750bce0e
NC		 1203 input_line_pointer = str;
1204 avr_offset_expression (& op_expr);
adde6300 1205 str = input_line_pointer;
750bce0e
NC		 1206 fix_new_exp (frag_now, where, 3,
1207 &op_expr, FALSE, BFD_RELOC_AVR_6);
adde6300
AM		 1208 }
1209 }
1210 break;
1211
1212 case 'h':
c6a7ab1f
NC		 1213 str = parse_exp (str, &op_expr);
1214 fix_new_exp (frag_now, where, opcode->insn_size * 2,
b34976b6 1215 &op_expr, FALSE, BFD_RELOC_AVR_CALL);
adde6300
AM		 1216 break;
1217
1218 case 'L':
c6a7ab1f
NC		 1219 str = parse_exp (str, &op_expr);
1220 fix_new_exp (frag_now, where, opcode->insn_size * 2,
b34976b6 1221 &op_expr, TRUE, BFD_RELOC_AVR_13_PCREL);
adde6300
AM		 1222 break;
1223
1224 case 'l':
c6a7ab1f
NC		 1225 str = parse_exp (str, &op_expr);
1226 fix_new_exp (frag_now, where, opcode->insn_size * 2,
b34976b6 1227 &op_expr, TRUE, BFD_RELOC_AVR_7_PCREL);
adde6300
AM		 1228 break;
1229
1230 case 'i':
c6a7ab1f
NC		 1231 str = parse_exp (str, &op_expr);
1232 fix_new_exp (frag_now, where + 2, opcode->insn_size * 2,
b34976b6 1233 &op_expr, FALSE, BFD_RELOC_16);
adde6300
AM		 1234 break;
1235
f36e8886
BS		 1236 case 'j':
1237 str = parse_exp (str, &op_expr);
1238 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1239 &op_expr, FALSE, BFD_RELOC_AVR_LDS_STS_16);
1240 break;
1241
adde6300
AM		 1242 case 'M':
1243 {
1244 bfd_reloc_code_real_type r_type;
1dab94dd 1245
c6a7ab1f
NC		 1246 input_line_pointer = str;
1247 r_type = avr_ldi_expression (&op_expr);
1248 str = input_line_pointer;
adde6300 1249 fix_new_exp (frag_now, where, 3,
b34976b6 1250 &op_expr, FALSE, r_type);
adde6300
AM		 1251 }
1252 break;
1253
1254 case 'n':
1255 {
1256 unsigned int x;
1dab94dd 1257
adde6300
AM		 1258 x = ~avr_get_constant (str, 255);
1259 str = input_line_pointer;
1260 op_mask |= (x & 0xf) | ((x << 4) & 0xf00);
1261 }
1262 break;
1263
32f76c67
GJL		 1264 case 'N':
1265 {
1266 unsigned int x;
1267
1268 x = avr_get_constant (str, 255);
1269 str = input_line_pointer;
1270 op_mask = x;
1271 }
1272 break;
1273
adde6300 1274 case 'K':
750bce0e
NC		 1275 input_line_pointer = str;
1276 avr_offset_expression (& op_expr);
1277 str = input_line_pointer;
1278 fix_new_exp (frag_now, where, 3,
1279 & op_expr, FALSE, BFD_RELOC_AVR_6_ADIW);
adde6300
AM		 1280 break;
1281
1282 case 'S':
1283 case 's':
1284 {
1285 unsigned int x;
1dab94dd 1286
adde6300
AM		 1287 x = avr_get_constant (str, 7);
1288 str = input_line_pointer;
1289 if (*op == 'S')
1290 x <<= 4;
1291 op_mask |= x;
1292 }
1293 break;
1294
1295 case 'P':
75f58085
BS		 1296 str = parse_exp (str, &op_expr);
1297 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1298 &op_expr, FALSE, BFD_RELOC_AVR_PORT6);
adde6300
AM		 1299 break;
1300
1301 case 'p':
75f58085
BS		 1302 str = parse_exp (str, &op_expr);
1303 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1304 &op_expr, FALSE, BFD_RELOC_AVR_PORT5);
adde6300 1305 break;
1dab94dd 1306
8cc66334
EW		 1307 case 'E':
1308 {
1309 unsigned int x;
1310
1311 x = avr_get_constant (str, 15);
1312 str = input_line_pointer;
1313 op_mask |= (x << 4);
1314 }
1315 break;
99700d6f 1316
1188e082
DC		 1317 case '?':
1318 break;
1dab94dd 1319
adde6300 1320 default:
00d2865b 1321 as_bad (_("unknown constraint `%c'"), *op);
adde6300 1322 }
1dab94dd 1323
adde6300
AM		 1324 *line = str;
1325 return op_mask;
1326}
1327
95e42ad4
NC		 1328/* TC_FRAG_INIT hook */
1329
1330void
1331avr_frag_init (fragS *frag)
1332{
1333 memset (& frag->tc_frag_data, 0, sizeof frag->tc_frag_data);
1334}
1335
1336
dc191a8f
NC		 1337/* Parse instruction operands.
1338 Return binary opcode. */
1339
1340static unsigned int
1341avr_operands (struct avr_opcodes_s *opcode, char **line)
1342{
e0471c16 1343 const char *op = opcode->constraints;
dc191a8f
NC		 1344 unsigned int bin = opcode->bin_opcode;
1345 char *frag = frag_more (opcode->insn_size * 2);
1346 char *str = *line;
1347 int where = frag - frag_now->fr_literal;
32f76c67
GJL		 1348 int regno1 = -2;
1349 int regno2 = -2;
dc191a8f
NC		 1350
1351 /* Opcode have operands. */
1352 if (*op)
1353 {
1354 unsigned int reg1 = 0;
1355 unsigned int reg2 = 0;
1356 int reg1_present = 0;
1357 int reg2_present = 0;
1358
1359 /* Parse first operand. */
1360 if (REGISTER_P (*op))
1361 reg1_present = 1;
32f76c67 1362 reg1 = avr_operand (opcode, where, op, &str, &regno1);
dc191a8f
NC		 1363 ++op;
1364
1365 /* Parse second operand. */
1366 if (*op)
1367 {
1368 if (*op == ',')
1369 ++op;
1370
1371 if (*op == '=')
1372 {
1373 reg2 = reg1;
1374 reg2_present = 1;
32f76c67 1375 regno2 = regno1;
dc191a8f
NC		 1376 }
1377 else
1378 {
1379 if (REGISTER_P (*op))
1380 reg2_present = 1;
1381
1382 str = skip_space (str);
1383 if (*str++ != ',')
1384 as_bad (_("`,' required"));
1385 str = skip_space (str);
1386
32f76c67 1387 reg2 = avr_operand (opcode, where, op, &str, &regno2);
dc191a8f
NC		 1388 }
1389
1390 if (reg1_present && reg2_present)
1391 reg2 = (reg2 & 0xf) | ((reg2 << 5) & 0x200);
1392 else if (reg2_present)
1393 reg2 <<= 4;
1394 }
1395 if (reg1_present)
1396 reg1 <<= 4;
1397 bin |= reg1 | reg2;
1398 }
1399
32f76c67
GJL		 1400 if (avr_opt.have_gccisr)
1401 avr_update_gccisr (opcode, regno1, regno2);
1402
dc191a8f
NC		 1403 /* Detect undefined combinations (like ld r31,Z+). */
1404 if (!avr_opt.all_opcodes && AVR_UNDEF_P (bin))
1405 as_warn (_("undefined combination of operands"));
1406
1407 if (opcode->insn_size == 2)
1408 {
1409 /* Warn if the previous opcode was cpse/sbic/sbis/sbrc/sbrs
1410 (AVR core bug, fixed in the newer devices). */
1411 if (!(avr_opt.no_skip_bug ||
1412 (avr_mcu->isa & (AVR_ISA_MUL | AVR_ISA_MOVW)))
95e42ad4 1413 && AVR_SKIP_P (frag_now->tc_frag_data.prev_opcode))
dc191a8f
NC		 1414 as_warn (_("skipping two-word instruction"));
1415
1416 bfd_putl32 ((bfd_vma) bin, frag);
1417 }
1418 else
1419 bfd_putl16 ((bfd_vma) bin, frag);
1420
95e42ad4 1421 frag_now->tc_frag_data.prev_opcode = bin;
dc191a8f
NC		 1422 *line = str;
1423 return bin;
1424}
1425
adde6300
AM		 1426/* GAS will call this function for each section at the end of the assembly,
1427 to permit the CPU backend to adjust the alignment of a section. */
c6a7ab1f 1428
adde6300 1429valueT
dc191a8f 1430md_section_align (asection *seg, valueT addr)
adde6300 1431{
fd361982 1432 int align = bfd_section_alignment (seg);
dce55a03 1433 return ((addr + (1 << align) - 1) & (-1UL << align));
adde6300
AM		 1434}
1435
1436/* If you define this macro, it should return the offset between the
1437 address of a PC relative fixup and the position from which the PC
1438 relative adjustment should be made. On many processors, the base
1439 of a PC relative instruction is the next instruction, so this
1440 macro would return the length of an instruction. */
c6a7ab1f 1441
adde6300 1442long
dc191a8f 1443md_pcrel_from_section (fixS *fixp, segT sec)
adde6300 1444{
c6a7ab1f 1445 if (fixp->fx_addsy != (symbolS *) NULL
adde6300
AM		 1446 && (!S_IS_DEFINED (fixp->fx_addsy)
1447 || (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
1448 return 0;
1dab94dd 1449
adde6300
AM		 1450 return fixp->fx_frag->fr_address + fixp->fx_where;
1451}
1452
e4ef1b6c
DC		 1453static bfd_boolean
1454relaxable_section (asection *sec)
1455{
edc9e9a6
AB		 1456 return ((sec->flags & SEC_DEBUGGING) == 0
1457 && (sec->flags & SEC_CODE) != 0
1458 && (sec->flags & SEC_ALLOC) != 0);
e4ef1b6c
DC		 1459}
1460
75f58085 1461/* Does whatever the xtensa port does. */
e4ef1b6c
DC		 1462int
1463avr_validate_fix_sub (fixS *fix)
1464{
1465 segT add_symbol_segment, sub_symbol_segment;
1466
1467 /* The difference of two symbols should be resolved by the assembler when
1468 linkrelax is not set. If the linker may relax the section containing
1469 the symbols, then an Xtensa DIFF relocation must be generated so that
1470 the linker knows to adjust the difference value. */
1471 if (!linkrelax || fix->fx_addsy == NULL)
1472 return 0;
1473
1474 /* Make sure both symbols are in the same segment, and that segment is
1475 "normal" and relaxable. If the segment is not "normal", then the
1476 fix is not valid. If the segment is not "relaxable", then the fix
1477 should have been handled earlier. */
1478 add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy);
1479 if (! SEG_NORMAL (add_symbol_segment) ||
1480 ! relaxable_section (add_symbol_segment))
1481 return 0;
1482
1483 sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy);
1484 return (sub_symbol_segment == add_symbol_segment);
1485}
1486
1487/* TC_FORCE_RELOCATION hook */
1488
1489/* If linkrelax is turned on, and the symbol to relocate
1490 against is in a relaxable segment, don't compute the value -
75f58085 1491 generate a relocation instead. */
e4ef1b6c
DC		 1492int
1493avr_force_relocation (fixS *fix)
1494{
1495 if (linkrelax && fix->fx_addsy
1496 && relaxable_section (S_GET_SEGMENT (fix->fx_addsy)))
1497 return 1;
1498
1499 return generic_force_reloc (fix);
1500}
1501
adde6300 1502/* GAS will call this for each fixup. It should store the correct
c6a7ab1f
NC		 1503 value in the object file. */
1504
94f592af 1505void
dc191a8f 1506md_apply_fix (fixS *fixP, valueT * valP, segT seg)
adde6300
AM		 1507{
1508 unsigned char *where;
1509 unsigned long insn;
a161fe53 1510 long value = *valP;
adde6300 1511
94f592af
NC		 1512 if (fixP->fx_addsy == (symbolS *) NULL)
1513 fixP->fx_done = 1;
1514
87733541
AM		 1515 else if (fixP->fx_pcrel)
1516 {
1517 segT s = S_GET_SEGMENT (fixP->fx_addsy);
1518
1519 if (s == seg || s == absolute_section)
1520 {
1521 value += S_GET_VALUE (fixP->fx_addsy);
1522 fixP->fx_done = 1;
1523 }
1524 }
e4ef1b6c
DC		 1525 else if (linkrelax && fixP->fx_subsy)
1526 {
1527 /* For a subtraction relocation expression, generate one
1528 of the DIFF relocs, with the value being the difference.
1529 Note that a sym1 - sym2 expression is adjusted into a
1530 section_start_sym + sym4_offset_from_section_start - sym1
1531 expression. fixP->fx_addsy holds the section start symbol,
1532 fixP->fx_offset holds sym2's offset, and fixP->fx_subsy
1533 holds sym1. Calculate the current difference and write value,
75f58085
BS		 1534 but leave fx_offset as is - during relaxation,
1535 fx_offset - value gives sym1's value. */
e4ef1b6c
DC		 1536
1537 switch (fixP->fx_r_type)
1538 {
1539 case BFD_RELOC_8:
1540 fixP->fx_r_type = BFD_RELOC_AVR_DIFF8;
1541 break;
1542 case BFD_RELOC_16:
1543 fixP->fx_r_type = BFD_RELOC_AVR_DIFF16;
1544 break;
1545 case BFD_RELOC_32:
1546 fixP->fx_r_type = BFD_RELOC_AVR_DIFF32;
1547 break;
1548 default:
1549 as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
1550 break;
1551 }
1552
1553 value = S_GET_VALUE (fixP->fx_addsy) +
1554 fixP->fx_offset - S_GET_VALUE (fixP->fx_subsy);
491793b5 1555 *valP = value;
e4ef1b6c
DC		 1556
1557 fixP->fx_subsy = NULL;
1558 }
a161fe53
AM		 1559 /* We don't actually support subtracting a symbol. */
1560 if (fixP->fx_subsy != (symbolS *) NULL)
1561 as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
1dab94dd 1562
e4ef1b6c
DC		 1563 /* For the DIFF relocs, write the value into the object file while still
1564 keeping fx_done FALSE, as both the difference (recorded in the object file)
75f58085 1565 and the sym offset (part of fixP) are needed at link relax time. */
e4ef1b6c 1566 where = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
94f592af 1567 switch (fixP->fx_r_type)
adde6300
AM		 1568 {
1569 default:
94f592af 1570 fixP->fx_no_overflow = 1;
adde6300
AM		 1571 break;
1572 case BFD_RELOC_AVR_7_PCREL:
1573 case BFD_RELOC_AVR_13_PCREL:
1574 case BFD_RELOC_32:
1575 case BFD_RELOC_16:
e4ef1b6c
DC		 1576 break;
1577 case BFD_RELOC_AVR_DIFF8:
1578 *where = value;
1579 break;
1580 case BFD_RELOC_AVR_DIFF16:
1581 bfd_putl16 ((bfd_vma) value, where);
1582 break;
1583 case BFD_RELOC_AVR_DIFF32:
1584 bfd_putl32 ((bfd_vma) value, where);
1585 break;
adde6300
AM		 1586 case BFD_RELOC_AVR_CALL:
1587 break;
1588 }
1589
94f592af 1590 if (fixP->fx_done)
adde6300
AM		 1591 {
1592 /* Fetch the instruction, insert the fully resolved operand
1593 value, and stuff the instruction back again. */
2132e3a3 1594 where = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
adde6300
AM		 1595 insn = bfd_getl16 (where);
1596
94f592af 1597 switch (fixP->fx_r_type)
adde6300
AM		 1598 {
1599 case BFD_RELOC_AVR_7_PCREL:
1600 if (value & 1)
94f592af 1601 as_bad_where (fixP->fx_file, fixP->fx_line,
adde6300 1602 _("odd address operand: %ld"), value);
1dab94dd 1603
adde6300
AM		 1604 /* Instruction addresses are always right-shifted by 1. */
1605 value >>= 1;
1606 --value; /* Correct PC. */
1dab94dd 1607
adde6300 1608 if (value < -64 || value > 63)
94f592af 1609 as_bad_where (fixP->fx_file, fixP->fx_line,
adde6300
AM		 1610 _("operand out of range: %ld"), value);
1611 value = (value << 3) & 0x3f8;
1612 bfd_putl16 ((bfd_vma) (value | insn), where);
1613 break;
1614
1615 case BFD_RELOC_AVR_13_PCREL:
1616 if (value & 1)
94f592af 1617 as_bad_where (fixP->fx_file, fixP->fx_line,
adde6300 1618 _("odd address operand: %ld"), value);
1dab94dd 1619
adde6300
AM		 1620 /* Instruction addresses are always right-shifted by 1. */
1621 value >>= 1;
1622 --value; /* Correct PC. */
adde6300
AM		 1623
1624 if (value < -2048 || value > 2047)
1625 {
65aa24b6 1626 /* No wrap for devices with >8K of program memory. */
00d2865b 1627 if ((avr_mcu->isa & AVR_ISA_MEGA) || avr_opt.no_wrap)
94f592af 1628 as_bad_where (fixP->fx_file, fixP->fx_line,
adde6300
AM		 1629 _("operand out of range: %ld"), value);
1630 }
1631
1632 value &= 0xfff;
1633 bfd_putl16 ((bfd_vma) (value | insn), where);
1634 break;
1635
1636 case BFD_RELOC_32:
0b649256 1637 bfd_putl32 ((bfd_vma) value, where);
adde6300
AM		 1638 break;
1639
1640 case BFD_RELOC_16:
1641 bfd_putl16 ((bfd_vma) value, where);
1642 break;
1643
17e57237
NC		 1644 case BFD_RELOC_8:
1645 if (value > 255 || value < -128)
1646 as_warn_where (fixP->fx_file, fixP->fx_line,
1647 _("operand out of range: %ld"), value);
1648 *where = value;
1649 break;
1650
adde6300 1651 case BFD_RELOC_AVR_16_PM:
c6a7ab1f 1652 bfd_putl16 ((bfd_vma) (value >> 1), where);
adde6300
AM		 1653 break;
1654
750bce0e
NC		 1655 case BFD_RELOC_AVR_LDI:
1656 if (value > 255)
1657 as_bad_where (fixP->fx_file, fixP->fx_line,
1658 _("operand out of range: %ld"), value);
1659 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value), where);
1660 break;
1661
f36e8886
BS		 1662 case BFD_RELOC_AVR_LDS_STS_16:
1663 if ((value < 0x40) || (value > 0xBF))
1664 as_warn_where (fixP->fx_file, fixP->fx_line,
1665 _("operand out of range: 0x%lx"),
1666 (unsigned long)value);
1667 insn |= ((value & 0xF) | ((value & 0x30) << 5) | ((value & 0x40) << 2));
1668 bfd_putl16 ((bfd_vma) insn, where);
1669 break;
1670
750bce0e
NC		 1671 case BFD_RELOC_AVR_6:
1672 if ((value > 63) || (value < 0))
1673 as_bad_where (fixP->fx_file, fixP->fx_line,
1674 _("operand out of range: %ld"), value);
f36e8886
BS		 1675 bfd_putl16 ((bfd_vma) insn | ((value & 7) | ((value & (3 << 3)) << 7)
1676 | ((value & (1 << 5)) << 8)), where);
750bce0e
NC		 1677 break;
1678
1679 case BFD_RELOC_AVR_6_ADIW:
1680 if ((value > 63) || (value < 0))
1681 as_bad_where (fixP->fx_file, fixP->fx_line,
1682 _("operand out of range: %ld"), value);
1683 bfd_putl16 ((bfd_vma) insn | (value & 0xf) | ((value & 0x30) << 2), where);
1684 break;
1685
adde6300
AM		 1686 case BFD_RELOC_AVR_LO8_LDI:
1687 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value), where);
1688 break;
1689
adde6300
AM		 1690 case BFD_RELOC_AVR_HI8_LDI:
1691 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 8), where);
1692 break;
1693
df406460 1694 case BFD_RELOC_AVR_MS8_LDI:
adde6300
AM		 1695 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 24), where);
1696 break;
1697
1698 case BFD_RELOC_AVR_HH8_LDI:
1699 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 16), where);
1700 break;
1701
1702 case BFD_RELOC_AVR_LO8_LDI_NEG:
1703 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value), where);
1704 break;
1705
adde6300
AM		 1706 case BFD_RELOC_AVR_HI8_LDI_NEG:
1707 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 8), where);
1708 break;
1709
df406460 1710 case BFD_RELOC_AVR_MS8_LDI_NEG:
adde6300
AM		 1711 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 24), where);
1712 break;
1713
1714 case BFD_RELOC_AVR_HH8_LDI_NEG:
1715 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 16), where);
1716 break;
1717
1718 case BFD_RELOC_AVR_LO8_LDI_PM:
1719 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 1), where);
1720 break;
1721
1722 case BFD_RELOC_AVR_HI8_LDI_PM:
1723 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 9), where);
1724 break;
1725
1726 case BFD_RELOC_AVR_HH8_LDI_PM:
1727 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 17), where);
1728 break;
1729
1730 case BFD_RELOC_AVR_LO8_LDI_PM_NEG:
1731 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 1), where);
1732 break;
1733
1734 case BFD_RELOC_AVR_HI8_LDI_PM_NEG:
1735 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 9), where);
1736 break;
1737
1738 case BFD_RELOC_AVR_HH8_LDI_PM_NEG:
1739 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 17), where);
1740 break;
1741
1742 case BFD_RELOC_AVR_CALL:
1743 {
1744 unsigned long x;
1dab94dd 1745
adde6300
AM		 1746 x = bfd_getl16 (where);
1747 if (value & 1)
94f592af 1748 as_bad_where (fixP->fx_file, fixP->fx_line,
adde6300
AM		 1749 _("odd address operand: %ld"), value);
1750 value >>= 1;
1751 x |= ((value & 0x10000) | ((value << 3) & 0x1f00000)) >> 16;
1752 bfd_putl16 ((bfd_vma) x, where);
c6a7ab1f 1753 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2);
adde6300
AM		 1754 }
1755 break;
1756
99700d6f
NC		 1757 case BFD_RELOC_AVR_8_LO:
1758 *where = 0xff & value;
1759 break;
1760
1761 case BFD_RELOC_AVR_8_HI:
1762 *where = 0xff & (value >> 8);
1763 break;
1764
40551fb8 1765 case BFD_RELOC_AVR_8_HLO:
99700d6f
NC		 1766 *where = 0xff & (value >> 16);
1767 break;
1768
1769 default:
c6a7ab1f 1770 as_fatal (_("line %d: unknown relocation type: 0x%x"),
94f592af 1771 fixP->fx_line, fixP->fx_r_type);
adde6300 1772 break;
75f58085
BS		 1773
1774 case BFD_RELOC_AVR_PORT6:
1775 if (value > 63)
1776 as_bad_where (fixP->fx_file, fixP->fx_line,
1777 _("operand out of range: %ld"), value);
1778 bfd_putl16 ((bfd_vma) insn | ((value & 0x30) << 5) | (value & 0x0f), where);
1779 break;
1780
1781 case BFD_RELOC_AVR_PORT5:
1782 if (value > 31)
1783 as_bad_where (fixP->fx_file, fixP->fx_line,
1784 _("operand out of range: %ld"), value);
1785 bfd_putl16 ((bfd_vma) insn | ((value & 0x1f) << 3), where);
1786 break;
adde6300
AM		 1787 }
1788 }
1789 else
1790 {
a61a9fbc 1791 switch ((int) fixP->fx_r_type)
adde6300
AM		 1792 {
1793 case -BFD_RELOC_AVR_HI8_LDI_NEG:
1794 case -BFD_RELOC_AVR_HI8_LDI:
1795 case -BFD_RELOC_AVR_LO8_LDI_NEG:
1796 case -BFD_RELOC_AVR_LO8_LDI:
94f592af 1797 as_bad_where (fixP->fx_file, fixP->fx_line,
adde6300 1798 _("only constant expression allowed"));
94f592af 1799 fixP->fx_done = 1;
adde6300
AM		 1800 break;
1801 default:
1802 break;
1803 }
adde6300 1804 }
adde6300
AM		 1805}
1806
7be1c489
AM		 1807/* GAS will call this to generate a reloc, passing the resulting reloc
1808 to `bfd_install_relocation'. This currently works poorly, as
1809 `bfd_install_relocation' often does the wrong thing, and instances of
1810 `tc_gen_reloc' have been written to work around the problems, which
1811 in turns makes it difficult to fix `bfd_install_relocation'. */
adde6300
AM		 1812
1813/* If while processing a fixup, a reloc really needs to be created
1814 then it is done here. */
1815
1816arelent *
dc191a8f
NC		 1817tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED,
1818 fixS *fixp)
adde6300
AM		 1819{
1820 arelent *reloc;
328e7bfd 1821 bfd_reloc_code_real_type code = fixp->fx_r_type;
adde6300 1822
94d4433a 1823 if (fixp->fx_subsy != NULL)
df406460 1824 {
94d4433a 1825 as_bad_where (fixp->fx_file, fixp->fx_line, _("expression too complex"));
df406460
NC		 1826 return NULL;
1827 }
1828
325801bd 1829 reloc = XNEW (arelent);
adde6300 1830
325801bd 1831 reloc->sym_ptr_ptr = XNEW (asymbol *);
adde6300
AM		 1832 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1833
1834 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
328e7bfd
DC		 1835
1836 if ((fixp->fx_r_type == BFD_RELOC_32) && (fixp->fx_pcrel))
1837 {
1838 if (seg->use_rela_p)
1839 fixp->fx_offset -= md_pcrel_from_section (fixp, seg);
1840 else
1841 fixp->fx_offset = reloc->address;
1842
1843 code = BFD_RELOC_32_PCREL;
1844 }
1845
1846 reloc->addend = fixp->fx_offset;
1847
1848 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1849
adde6300
AM		 1850 if (reloc->howto == (reloc_howto_type *) NULL)
1851 {
1852 as_bad_where (fixp->fx_file, fixp->fx_line,
c6a7ab1f
NC		 1853 _("reloc %d not supported by object file format"),
1854 (int) fixp->fx_r_type);
adde6300
AM		 1855 return NULL;
1856 }
1857
1858 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1859 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1860 reloc->address = fixp->fx_offset;
1861
adde6300
AM		 1862
1863 return reloc;
1864}
1865
adde6300 1866void
dc191a8f 1867md_assemble (char *str)
adde6300 1868{
c6a7ab1f 1869 struct avr_opcodes_s *opcode;
adde6300
AM		 1870 char op[11];
1871
c6a7ab1f 1872 str = skip_space (extract_word (str, op, sizeof (op)));
adde6300
AM		 1873
1874 if (!op[0])
00d2865b 1875 as_bad (_("can't find opcode "));
adde6300
AM		 1876
1877 opcode = (struct avr_opcodes_s *) hash_find (avr_hash, op);
1878
f36e8886
BS		 1879 if (opcode && !avr_opt.all_opcodes)
1880 {
75f58085 1881 /* Check if the instruction's ISA bit is ON in the ISA bits of the part
f36e8886 1882 specified by the user. If not look for other instructions
75f58085 1883 specifications with same mnemonic who's ISA bits matches.
f36e8886
BS		 1884
1885 This requires include/opcode/avr.h to have the instructions with
33eaf5de 1886 same mnemonic to be specified in sequence. */
f36e8886
BS		 1887
1888 while ((opcode->isa & avr_mcu->isa) != opcode->isa)
1889 {
1890 opcode++;
75f58085 1891
f36e8886
BS		 1892 if (opcode->name && strcmp(op, opcode->name))
1893 {
75f58085 1894 as_bad (_("illegal opcode %s for mcu %s"),
f36e8886
BS		 1895 opcode->name, avr_mcu->name);
1896 return;
1897 }
1898 }
75f58085 1899 }
f36e8886 1900
adde6300
AM		 1901 if (opcode == NULL)
1902 {
00d2865b 1903 as_bad (_("unknown opcode `%s'"), op);
adde6300
AM		 1904 return;
1905 }
1906
32f76c67
GJL		 1907 if (opcode == avr_gccisr_opcode
1908 && !avr_opt.have_gccisr)
1909 {
1910 as_bad (_("pseudo instruction `%s' not supported"), op);
1911 return;
1912 }
1913
b170af93 1914 /* Special case for opcodes with optional operands (lpm, elpm) -
1188e082 1915 version with operands exists in avr_opcodes[] in the next entry. */
c6a7ab1f 1916
1188e082
DC		 1917 if (*str && *opcode->constraints == '?')
1918 ++opcode;
b170af93 1919
d4f4f3fb
AM		 1920 dwarf2_emit_insn (0);
1921
adde6300
AM		 1922 /* We used to set input_line_pointer to the result of get_operands,
1923 but that is wrong. Our caller assumes we don't change it. */
1924 {
1925 char *t = input_line_pointer;
dc191a8f 1926
32f76c67
GJL		 1927 if (opcode == avr_gccisr_opcode)
1928 avr_gccisr_operands (opcode, &str);
1929 else
1930 avr_operands (opcode, &str);
b170af93 1931 if (*skip_space (str))
00d2865b 1932 as_bad (_("garbage at end of line"));
adde6300
AM		 1933 input_line_pointer = t;
1934 }
1935}
1936
62ebcb5c 1937const exp_mod_data_t exp_mod_data[] =
99700d6f
NC		 1938{
1939 /* Default, must be first. */
1940 { "", 0, BFD_RELOC_16, "" },
1941 /* Divides by 2 to get word address. Generate Stub. */
1942 { "gs", 2, BFD_RELOC_AVR_16_PM, "`gs' " },
1943 { "pm", 2, BFD_RELOC_AVR_16_PM, "`pm' " },
1944 /* The following are used together with avr-gcc's __memx address space
1945 in order to initialize a 24-bit pointer variable with a 24-bit address.
40551fb8
NC		 1946 For address in flash, hlo8 will contain the flash segment if the
1947 symbol is located in flash. If the symbol is located in RAM; hlo8
99700d6f
NC		 1948 will contain 0x80 which matches avr-gcc's notion of how 24-bit RAM/flash
1949 addresses linearize address space. */
1950 { "lo8", 1, BFD_RELOC_AVR_8_LO, "`lo8' " },
1951 { "hi8", 1, BFD_RELOC_AVR_8_HI, "`hi8' " },
40551fb8
NC		 1952 { "hlo8", 1, BFD_RELOC_AVR_8_HLO, "`hlo8' " },
1953 { "hh8", 1, BFD_RELOC_AVR_8_HLO, "`hh8' " },
99700d6f
NC		 1954};
1955
99700d6f
NC		 1956/* Parse special CONS expression: pm (expression) or alternatively
1957 gs (expression). These are used for addressing program memory. Moreover,
40551fb8 1958 define lo8 (expression), hi8 (expression) and hlo8 (expression). */
c6a7ab1f 1959
62ebcb5c 1960const exp_mod_data_t *
dc191a8f 1961avr_parse_cons_expression (expressionS *exp, int nbytes)
adde6300 1962{
c6a7ab1f 1963 char *tmp;
814f1489 1964 unsigned int i;
adde6300 1965
adde6300
AM		 1966 tmp = input_line_pointer = skip_space (input_line_pointer);
1967
99700d6f
NC		 1968 /* The first entry of exp_mod_data[] contains an entry if no
1969 expression modifier is present. Skip it. */
1970
814f1489 1971 for (i = 0; i < ARRAY_SIZE (exp_mod_data); i++)
adde6300 1972 {
814f1489 1973 const exp_mod_data_t *pexp = &exp_mod_data[i];
99700d6f 1974 int len = strlen (pexp->name);
1dab94dd 1975
99700d6f
NC		 1976 if (nbytes == pexp->nbytes
1977 && strncasecmp (input_line_pointer, pexp->name, len) == 0)
adde6300
AM		 1978 {
1979 input_line_pointer = skip_space (input_line_pointer + len);
1dab94dd 1980
adde6300
AM		 1981 if (*input_line_pointer == '(')
1982 {
1983 input_line_pointer = skip_space (input_line_pointer + 1);
adde6300 1984 expression (exp);
1dab94dd 1985
adde6300 1986 if (*input_line_pointer == ')')
62ebcb5c
AM		 1987 {
1988 ++input_line_pointer;
1989 return pexp;
1990 }
adde6300
AM		 1991 else
1992 {
00d2865b 1993 as_bad (_("`)' required"));
62ebcb5c 1994 return &exp_mod_data[0];
adde6300 1995 }
adde6300 1996 }
1dab94dd 1997
adde6300 1998 input_line_pointer = tmp;
99700d6f
NC		 1999
2000 break;
adde6300
AM		 2001 }
2002 }
1dab94dd 2003
adde6300 2004 expression (exp);
62ebcb5c 2005 return &exp_mod_data[0];
adde6300
AM		 2006}
2007
2008void
dc191a8f
NC		 2009avr_cons_fix_new (fragS *frag,
2010 int where,
2011 int nbytes,
62ebcb5c
AM		 2012 expressionS *exp,
2013 const exp_mod_data_t *pexp_mod_data)
adde6300 2014{
99700d6f
NC		 2015 int bad = 0;
2016
2017 switch (pexp_mod_data->reloc)
adde6300 2018 {
99700d6f 2019 default:
17e57237
NC		 2020 if (nbytes == 1)
2021 fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_8);
2022 else if (nbytes == 2)
b34976b6 2023 fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_16);
adde6300 2024 else if (nbytes == 4)
b34976b6 2025 fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_32);
adde6300 2026 else
99700d6f
NC		 2027 bad = 1;
2028 break;
2029
2030 case BFD_RELOC_AVR_16_PM:
2031 case BFD_RELOC_AVR_8_LO:
2032 case BFD_RELOC_AVR_8_HI:
40551fb8 2033 case BFD_RELOC_AVR_8_HLO:
99700d6f
NC		 2034 if (nbytes == pexp_mod_data->nbytes)
2035 fix_new_exp (frag, where, nbytes, exp, FALSE, pexp_mod_data->reloc);
adde6300 2036 else
99700d6f
NC		 2037 bad = 1;
2038 break;
adde6300 2039 }
99700d6f
NC		 2040
2041 if (bad)
33eaf5de 2042 as_bad (_("illegal %s relocation size: %d"), pexp_mod_data->error, nbytes);
adde6300 2043}
af3ecb4a 2044
71863e73
NC		 2045static bfd_boolean
2046mcu_has_3_byte_pc (void)
2047{
75f58085 2048 int mach = avr_mcu->mach;
71863e73 2049
75f58085
BS		 2050 return mach == bfd_mach_avr6
2051 || mach == bfd_mach_avrxmega6
71863e73
NC		 2052 || mach == bfd_mach_avrxmega7;
2053}
2054
af3ecb4a
RH		 2055void
2056tc_cfi_frame_initial_instructions (void)
2057{
2058 /* AVR6 pushes 3 bytes for calls. */
71863e73 2059 int return_size = (mcu_has_3_byte_pc () ? 3 : 2);
af3ecb4a
RH		 2060
2061 /* The CFA is the caller's stack location before the call insn. */
2062 /* Note that the stack pointer is dwarf register number 32. */
2063 cfi_add_CFA_def_cfa (32, return_size);
2064
2065 /* Note that AVR consistently uses post-decrement, which means that things
33eaf5de 2066 do not line up the same way as for targets that use pre-decrement. */
af3ecb4a
RH		 2067 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, 1-return_size);
2068}
e4ef1b6c
DC		 2069
2070bfd_boolean
2071avr_allow_local_subtract (expressionS * left,
2072 expressionS * right,
2073 segT section)
2074{
75f58085 2075 /* If we are not in relaxation mode, subtraction is OK. */
e4ef1b6c
DC		 2076 if (!linkrelax)
2077 return TRUE;
2078
2079 /* If the symbols are not in a code section then they are OK. */
2080 if ((section->flags & SEC_CODE) == 0)
2081 return TRUE;
2082
2083 if (left->X_add_symbol == right->X_add_symbol)
2084 return TRUE;
2085
2086 /* We have to assume that there may be instructions between the
2087 two symbols and that relaxation may increase the distance between
2088 them. */
2089 return FALSE;
2090}
eac7440d
AB		 2091
2092void
2093avr_elf_final_processing (void)
2094{
2095 if (linkrelax)
2096 elf_elfheader (stdoutput)->e_flags |= EF_AVR_LINKRELAX_PREPARED;
2097}
fdd410ac
AB		 2098
2099/* Write out the header of a .avr.prop section into the area pointed to by
2100 DATA. The RECORD_COUNT will be placed in the header as the number of
2101 records that are to follow.
2102 The area DATA must be big enough the receive the header, which is
2103 AVR_PROPERTY_SECTION_HEADER_SIZE bytes long. */
2104
2105static char *
2106avr_output_property_section_header (char *data,
2107 unsigned int record_count)
2108{
2109 char *orig_data = data;
2110
2111 md_number_to_chars (data, AVR_PROPERTY_RECORDS_VERSION, 1);
2112 data++;
2113 /* There's space for a single byte flags field, but right now there's
2114 nothing to go in here, so just set the value to zero. */
2115 md_number_to_chars (data, 0, 1);
2116 data++;
2117 md_number_to_chars (data, record_count, 2);
2118 data+=2;
2119
2120 gas_assert (data - orig_data == AVR_PROPERTY_SECTION_HEADER_SIZE);
2121
2122 return data;
2123}
2124
2125/* Return the number of bytes required to store RECORD into the .avr.prop
2126 section. The size returned is the compressed size that corresponds to
2127 how the record will be written out in AVR_OUTPUT_PROPERTY_RECORD. */
2128
2129static int
2130avr_record_size (const struct avr_property_record *record)
2131{
2132 /* The first 5 bytes are a 4-byte address, followed by a 1-byte type
2133 identifier. */
2134 int size = 5;
2135
2136 switch (record->type)
2137 {
2138 case RECORD_ORG:
2139 size += 0; /* No extra information. */
2140 break;
2141
2142 case RECORD_ORG_AND_FILL:
2143 size += 4; /* A 4-byte fill value. */
2144 break;
2145
2146 case RECORD_ALIGN:
2147 size += 4; /* A 4-byte alignment value. */
2148 break;
2149
2150 case RECORD_ALIGN_AND_FILL:
2151 size += 8; /* A 4-byte alignment, and 4-byte fill value. */
2152 break;
2153
2154 default:
2155 as_fatal (_("unknown record type %d (in %s)"),
2156 record->type, __PRETTY_FUNCTION__);
2157 }
2158
2159 return size;
2160}
2161
2162/* Write out RECORD. FRAG_BASE points to the start of the data area setup
2163 to hold all of the .avr.prop content, FRAG_PTR points to the next
2164 writable location. The data area must be big enough to hold all of the
2165 records. The size of the data written out for this RECORD must match
2166 the size from AVR_RECORD_SIZE. */
2167
2168static char *
2169avr_output_property_record (char * const frag_base, char *frag_ptr,
2170 const struct avr_property_record *record)
2171{
2172 fixS *fix;
2173 int where;
2174 char *init_frag_ptr = frag_ptr;
2175
2176 where = frag_ptr - frag_base;
2177 fix = fix_new (frag_now, where, 4,
2178 section_symbol (record->section),
2179 record->offset, FALSE, BFD_RELOC_32);
2180 fix->fx_file = "<internal>";
2181 fix->fx_line = 0;
2182 frag_ptr += 4;
2183
2184 md_number_to_chars (frag_ptr, (bfd_byte) record->type, 1);
2185 frag_ptr += 1;
2186
2187 /* Write out the rest of the data. */
2188 switch (record->type)
2189 {
2190 case RECORD_ORG:
2191 break;
2192
2193 case RECORD_ORG_AND_FILL:
2194 md_number_to_chars (frag_ptr, record->data.org.fill, 4);
2195 frag_ptr += 4;
2196 break;
2197
2198 case RECORD_ALIGN:
2199 md_number_to_chars (frag_ptr, record->data.align.bytes, 4);
2200 frag_ptr += 4;
2201 break;
2202
2203 case RECORD_ALIGN_AND_FILL:
2204 md_number_to_chars (frag_ptr, record->data.align.bytes, 4);
431ff075 2205 md_number_to_chars (frag_ptr + 4, record->data.align.fill, 4);
fdd410ac
AB		 2206 frag_ptr += 8;
2207 break;
2208
2209 default:
2210 as_fatal (_("unknown record type %d (in %s)"),
2211 record->type, __PRETTY_FUNCTION__);
2212 }
2213
2214 gas_assert (frag_ptr - init_frag_ptr == avr_record_size (record));
2215
2216 return frag_ptr;
2217}
2218
2219/* Create the section to hold the AVR property information. Return the
2220 section. */
2221
2222static asection *
2223avr_create_property_section (void)
2224{
2225 asection *sec;
2226 flagword flags = (SEC_RELOC | SEC_HAS_CONTENTS | SEC_READONLY);
2227 const char *section_name = AVR_PROPERTY_RECORD_SECTION_NAME;
2228
2229 sec = bfd_make_section (stdoutput, section_name);
2230 if (sec == NULL)
2231 as_fatal (_("Failed to create property section `%s'\n"), section_name);
fd361982 2232 bfd_set_section_flags (sec, flags);
fdd410ac
AB		 2233 sec->output_section = sec;
2234 return sec;
2235}
2236
2237/* This hook is called when alignment is performed, and allows us to
2238 capture the details of both .org and .align directives. */
2239
2240void
2241avr_handle_align (fragS *fragP)
2242{
2243 if (linkrelax)
2244 {
2245 /* Ignore alignment requests at FR_ADDRESS 0, these are at the very
2246 start of a section, and will be handled by the standard section
2247 alignment mechanism. */
2248 if ((fragP->fr_type == rs_align
2249 || fragP->fr_type == rs_align_code)
fdd410ac
AB		 2250 && fragP->fr_offset > 0)
2251 {
431ff075
AB		 2252 char *p = fragP->fr_literal + fragP->fr_fix;
2253
fdd410ac
AB		 2254 fragP->tc_frag_data.is_align = TRUE;
2255 fragP->tc_frag_data.alignment = fragP->fr_offset;
431ff075
AB		 2256 fragP->tc_frag_data.fill = *p;
2257 fragP->tc_frag_data.has_fill = (fragP->tc_frag_data.fill != 0);
fdd410ac
AB		 2258 }
2259
2260 if (fragP->fr_type == rs_org && fragP->fr_offset > 0)
2261 {
2262 char *p = fragP->fr_literal + fragP->fr_fix;
2263
2264 fragP->tc_frag_data.is_org = TRUE;
2265 fragP->tc_frag_data.fill = *p;
2266 fragP->tc_frag_data.has_fill = (fragP->tc_frag_data.fill != 0);
2267 }
2268 }
2269}
2270
2271/* Return TRUE if this section is not one for which we need to record
2272 information in the avr property section. */
2273
2274static bfd_boolean
2275exclude_section_from_property_tables (segT sec)
2276{
2277 /* Only generate property information for sections on which linker
2278 relaxation could be performed. */
2279 return !relaxable_section (sec);
2280}
2281
2282/* Create a property record for fragment FRAGP from section SEC and place
2283 it into an AVR_PROPERTY_RECORD_LINK structure, which can then formed
2284 into a linked list by the caller. */
2285
2286static struct avr_property_record_link *
2287create_record_for_frag (segT sec, fragS *fragP)
2288{
ef7a9369 2289 struct avr_property_record_link *prop_rec_link;
fdd410ac 2290
325801bd 2291 prop_rec_link = XCNEW (struct avr_property_record_link);
431ff075 2292 gas_assert (fragP->fr_next != NULL);
fdd410ac
AB		 2293
2294 if (fragP->tc_frag_data.is_org)
2295 {
ef7a9369
SKS		 2296 prop_rec_link->record.offset = fragP->fr_next->fr_address;
2297 prop_rec_link->record.section = sec;
fdd410ac
AB		 2298
2299 if (fragP->tc_frag_data.has_fill)
2300 {
ef7a9369
SKS		 2301 prop_rec_link->record.data.org.fill = fragP->tc_frag_data.fill;
2302 prop_rec_link->record.type = RECORD_ORG_AND_FILL;
fdd410ac
AB		 2303 }
2304 else
ef7a9369 2305 prop_rec_link->record.type = RECORD_ORG;
fdd410ac
AB		 2306 }
2307 else
2308 {
431ff075 2309 prop_rec_link->record.offset = fragP->fr_next->fr_address;
ef7a9369 2310 prop_rec_link->record.section = sec;
fdd410ac
AB		 2311
2312 gas_assert (fragP->tc_frag_data.is_align);
2313 if (fragP->tc_frag_data.has_fill)
2314 {
ef7a9369
SKS		 2315 prop_rec_link->record.data.align.fill = fragP->tc_frag_data.fill;
2316 prop_rec_link->record.type = RECORD_ALIGN_AND_FILL;
fdd410ac
AB		 2317 }
2318 else
ef7a9369
SKS		 2319 prop_rec_link->record.type = RECORD_ALIGN;
2320 prop_rec_link->record.data.align.bytes = fragP->tc_frag_data.alignment;
fdd410ac
AB		 2321 }
2322
ef7a9369 2323 return prop_rec_link;
fdd410ac
AB		 2324}
2325
2326/* Build a list of AVR_PROPERTY_RECORD_LINK structures for section SEC, and
2327 merged them onto the list pointed to by NEXT_PTR. Return a pointer to
2328 the last list item created. */
2329
2330static struct avr_property_record_link **
2331append_records_for_section (segT sec,
2332 struct avr_property_record_link **next_ptr)
2333{
2334 segment_info_type *seginfo = seg_info (sec);
2335 fragS *fragP;
2336
2337 if (seginfo && seginfo->frchainP)
2338 {
2339 for (fragP = seginfo->frchainP->frch_root;
2340 fragP;
2341 fragP = fragP->fr_next)
2342 {
2343 if (fragP->tc_frag_data.is_align
2344 || fragP->tc_frag_data.is_org)
2345 {
2346 /* Create a single new entry. */
2347 struct avr_property_record_link *new_link
2348 = create_record_for_frag (sec, fragP);
2349
2350 *next_ptr = new_link;
2351 next_ptr = &new_link->next;
2352 }
2353 }
2354 }
2355
2356 return next_ptr;
2357}
2358
2359/* Create the AVR property section and fill it with records of .org and
2360 .align directives that were used. The section is only created if it
2361 will actually have any content. */
2362
2363static void
2364avr_create_and_fill_property_section (void)
2365{
2366 segT *seclist;
2367 asection *prop_sec;
2368 struct avr_property_record_link *r_list, **next_ptr;
2369 char *frag_ptr, *frag_base;
2370 bfd_size_type sec_size;
2371 struct avr_property_record_link *rec;
2372 unsigned int record_count;
2373
2374 /* First walk over all sections. For sections on which linker
2375 relaxation could be applied, extend the record list. The record list
2376 holds information that the linker will need to know. */
2377
2378 prop_sec = NULL;
2379 r_list = NULL;
2380 next_ptr = &r_list;
2381 for (seclist = &stdoutput->sections;
2382 seclist && *seclist;
2383 seclist = &(*seclist)->next)
2384 {
2385 segT sec = *seclist;
2386
2387 if (exclude_section_from_property_tables (sec))
2388 continue;
2389
2390 next_ptr = append_records_for_section (sec, next_ptr);
2391 }
2392
2393 /* Create property section and ensure the size is correct. We've already
2394 passed the point where gas could size this for us. */
2395 sec_size = AVR_PROPERTY_SECTION_HEADER_SIZE;
2396 record_count = 0;
2397 for (rec = r_list; rec != NULL; rec = rec->next)
2398 {
2399 record_count++;
2400 sec_size += avr_record_size (&rec->record);
2401 }
2402
2403 if (record_count == 0)
2404 return;
2405
2406 prop_sec = avr_create_property_section ();
fd361982 2407 bfd_set_section_size (prop_sec, sec_size);
fdd410ac
AB		 2408
2409 subseg_set (prop_sec, 0);
2410 frag_base = frag_more (sec_size);
2411
2412 frag_ptr =
2413 avr_output_property_section_header (frag_base, record_count);
2414
2415 for (rec = r_list; rec != NULL; rec = rec->next)
2416 frag_ptr = avr_output_property_record (frag_base, frag_ptr, &rec->record);
2417
2418 frag_wane (frag_now);
2419 frag_new (0);
2420 frag_wane (frag_now);
2421}
2422
2423/* We're using this hook to build up the AVR property section. It's called
2424 late in the assembly process which suits our needs. */
2425void
2426avr_post_relax_hook (void)
2427{
2428 avr_create_and_fill_property_section ();
2429}
32f76c67
GJL		 2430
2431
2432/* Accumulate information about instruction sequence to `avr_isr':
2433 wheter TMP_REG, ZERO_REG and SREG might be touched. Used during parse.
2434 REG1 is either -1 or a register number used by the instruction as input
2435 or output operand. Similar for REG2. */
2436
2437static void
2438avr_update_gccisr (struct avr_opcodes_s *opcode, int reg1, int reg2)
2439{
2440 const int tiny_p = avr_mcu->mach == bfd_mach_avrtiny;
2441 const int reg_tmp = tiny_p ? 16 : 0;
2442 const int reg_zero = 1 + reg_tmp;
2443
2444 if (ISR_CHUNK_Done == avr_isr.prev_chunk
2445 || (avr_isr.need_sreg
2446 && avr_isr.need_reg_tmp
2447 && avr_isr.need_reg_zero))
2448 {
2449 /* Nothing (more) to do */
2450 return;
2451 }
2452
2453 /* SREG: Look up instructions that don't clobber SREG. */
2454
2455 if (!avr_isr.need_sreg
2456 && !hash_find (avr_no_sreg_hash, opcode->name))
2457 {
2458 avr_isr.need_sreg = 1;
2459 }
2460
2461 /* Handle explicit register operands. Record *any* use as clobber.
2462 This is because TMP_REG and ZERO_REG are not global and using
2463 them makes no sense without a previous set. */
2464
2465 avr_isr.need_reg_tmp |= reg1 == reg_tmp || reg2 == reg_tmp;
2466 avr_isr.need_reg_zero |= reg1 == reg_zero || reg2 == reg_zero;
2467
2468 /* Handle implicit register operands and some opaque stuff. */
2469
2470 if (strstr (opcode->name, "lpm")
2471 && '?' == *opcode->constraints)
2472 {
2473 avr_isr.need_reg_tmp = 1;
2474 }
2475
2476 if (strstr (opcode->name, "call")
2477 || strstr (opcode->name, "mul")
2478 || 0 == strcmp (opcode->name, "des")
2479 || (0 == strcmp (opcode->name, "movw")
2480 && (reg1 == reg_tmp || reg2 == reg_tmp)))
2481 {
2482 avr_isr.need_reg_tmp = 1;
2483 avr_isr.need_reg_zero = 1;
2484 }
2485}
2486
2487
2488/* Emit some 1-word instruction to **PWHERE and advance *PWHERE by the number
2489 of octets written. INSN specifies the desired instruction and REG is the
2490 register used by it. This function is only used with restricted subset of
2491 instructions as might be emit by `__gcc_isr'. IN / OUT will use SREG
2492 and LDI loads 0. */
2493
2494static void
2495avr_emit_insn (const char *insn, int reg, char **pwhere)
2496{
2497 const int sreg = 0x3f;
2498 unsigned bin = 0;
2499 const struct avr_opcodes_s *op
2500 = (struct avr_opcodes_s*) hash_find (avr_hash, insn);
2501
2502 /* We only have to deal with: IN, OUT, PUSH, POP, CLR, LDI 0. All of
2503 these deal with at least one Reg and are 1-word instructions. */
2504
2505 gas_assert (op && 1 == op->insn_size);
2506 gas_assert (reg >= 0 && reg <= 31);
2507
2508 if (strchr (op->constraints, 'r'))
2509 {
2510 bin = op->bin_opcode | (reg << 4);
2511 }
2512 else if (strchr (op->constraints, 'd'))
2513 {
2514 gas_assert (reg >= 16);
2515 bin = op->bin_opcode | ((reg & 0xf) << 4);
2516 }
2517 else
2518 abort();
2519
2520 if (strchr (op->constraints, 'P'))
2521 {
2522 bin |= ((sreg & 0x30) << 5) | (sreg & 0x0f);
2523 }
2524 else if (0 == strcmp ("r=r", op->constraints))
2525 {
2526 bin |= ((reg & 0x10) << 5) | (reg & 0x0f);
2527 }
2528 else
2529 gas_assert (0 == strcmp ("r", op->constraints)
2530 || 0 == strcmp ("ldi", op->name));
2531
2532 bfd_putl16 ((bfd_vma) bin, *pwhere);
2533 (*pwhere) += 2 * op->insn_size;
2534}
2535
2536
2537/* Turn rs_machine_dependent frag *FR into an ordinary rs_fill code frag,
2538 using information gathered in `avr_isr'. REG is the register number as
2539 supplied by Done chunk "__gcc_isr 0,REG". */
2540
2541static void
2542avr_patch_gccisr_frag (fragS *fr, int reg)
2543{
2544 int treg;
2545 int n_pushed = 0;
2546 char *where = fr->fr_literal;
2547 const int tiny_p = avr_mcu->mach == bfd_mach_avrtiny;
2548 const int reg_tmp = tiny_p ? 16 : 0;
2549 const int reg_zero = 1 + reg_tmp;
2550
2551 /* Clearing ZERO_REG on non-Tiny needs CLR which clobbers SREG. */
2552
2553 avr_isr.need_sreg |= !tiny_p && avr_isr.need_reg_zero;
2554
2555 /* A working register to PUSH / POP the SREG. We might use the register
2556 as supplied by ISR_CHUNK_Done for that purpose as GCC wants to push
2557 it anyways. If GCC passes ZERO_REG or TMP_REG, it has no clue (and
2558 no additional regs to safe) and we use that reg. */
2559
2560 treg
2561 = avr_isr.need_reg_tmp ? reg_tmp
2562 : avr_isr.need_reg_zero ? reg_zero
2563 : avr_isr.need_sreg ? reg
2564 : reg > reg_zero ? reg
2565 : -1;
2566
2567 if (treg >= 0)
2568 {
2569 /* Non-empty prologue / epilogue */
2570
2571 if (ISR_CHUNK_Prologue == fr->fr_subtype)
2572 {
2573 avr_emit_insn ("push", treg, &where);
2574 n_pushed++;
2575
2576 if (avr_isr.need_sreg)
2577 {
2578 avr_emit_insn ("in", treg, &where);
2579 avr_emit_insn ("push", treg, &where);
2580 n_pushed++;
2581 }
2582
2583 if (avr_isr.need_reg_zero)
2584 {
2585 if (reg_zero != treg)
2586 {
2587 avr_emit_insn ("push", reg_zero, &where);
2588 n_pushed++;
2589 }
2590 avr_emit_insn (tiny_p ? "ldi" : "clr", reg_zero, &where);
2591 }
2592
2593 if (reg > reg_zero && reg != treg)
2594 {
2595 avr_emit_insn ("push", reg, &where);
2596 n_pushed++;
2597 }
2598 }
2599 else if (ISR_CHUNK_Epilogue == fr->fr_subtype)
2600 {
2601 /* Same logic as in Prologue but in reverse order and with counter
2602 parts of either instruction: POP instead of PUSH and OUT instead
2603 of IN. Clearing ZERO_REG has no couter part. */
2604
2605 if (reg > reg_zero && reg != treg)
2606 avr_emit_insn ("pop", reg, &where);
2607
2608 if (avr_isr.need_reg_zero
2609 && reg_zero != treg)
2610 avr_emit_insn ("pop", reg_zero, &where);
2611
2612 if (avr_isr.need_sreg)
2613 {
2614 avr_emit_insn ("pop", treg, &where);
2615 avr_emit_insn ("out", treg, &where);
2616 }
2617
2618 avr_emit_insn ("pop", treg, &where);
2619 }
2620 else
2621 abort();
2622 } /* treg >= 0 */
2623
2624 if (ISR_CHUNK_Prologue == fr->fr_subtype
2625 && avr_isr.sym_n_pushed)
2626 {
2627 symbolS *sy = avr_isr.sym_n_pushed;
2628 /* Turn magic `__gcc_isr.n_pushed' into its now known value. */
2629
8d1015a8 2630 S_SET_VALUE (sy, n_pushed);
32f76c67
GJL		 2631 S_SET_SEGMENT (sy, expr_section);
2632 avr_isr.sym_n_pushed = NULL;
2633 }
2634
2635 /* Turn frag into ordinary code frag of now known size. */
2636
2637 fr->fr_var = 0;
871a6bd2
AM		 2638 fr->fr_fix = where - fr->fr_literal;
2639 gas_assert (fr->fr_fix <= (valueT) fr->fr_offset);
32f76c67
GJL		 2640 fr->fr_offset = 0;
2641 fr->fr_type = rs_fill;
2642 fr->fr_subtype = 0;
2643}
2644
2645
2646/* Implements `__gcc_isr' pseudo-instruction. For Prologue and Epilogue
2647 chunks, emit a new rs_machine_dependent frag. For Done chunks, traverse
2648 the current segment and patch all rs_machine_dependent frags to become
2649 appropriate rs_fill code frags. If chunks are seen in an odd ordering,
2650 throw an error instead. */
2651
2652static void
2653avr_gccisr_operands (struct avr_opcodes_s *opcode, char **line)
2654{
2655 int bad = 0;
2656 int chunk, reg = 0;
2657 char *str = *line;
2658
2659 gas_assert (avr_opt.have_gccisr);
2660
2661 /* We only use operands "N" and "r" which don't pop new fix-ups. */
2662
2663 /* 1st operand: Which chunk of __gcc_isr: 0...2. */
2664
2665 chunk = avr_operand (opcode, -1, "N", &str, NULL);
2666 if (chunk < 0 || chunk > 2)
2667 as_bad (_("%s requires value 0-2 as operand 1"), opcode->name);
2668
2669 if (ISR_CHUNK_Done == chunk)
2670 {
2671 /* 2nd operand: A register to push / pop. */
2672
2673 str = skip_space (str);
2674 if (*str == '\0' || *str++ != ',')
2675 as_bad (_("`,' required"));
2676 else
2677 avr_operand (opcode, -1, "r", &str, &reg);
2678 }
2679
2680 *line = str;
2681
2682 /* Chunks must follow in a specific order:
2683 - Prologue: Exactly one
2684 - Epilogue: Any number
2685 - Done: Exactly one. */
2686 bad |= ISR_CHUNK_Prologue == chunk && avr_isr.prev_chunk != ISR_CHUNK_Done;
2687 bad |= ISR_CHUNK_Epilogue == chunk && avr_isr.prev_chunk == ISR_CHUNK_Done;
2688 bad |= ISR_CHUNK_Done == chunk && avr_isr.prev_chunk == ISR_CHUNK_Done;
2689 if (bad)
2690 {
2691 if (avr_isr.file)
2692 as_bad (_("`%s %d' after `%s %d' from %s:%u"), opcode->name, chunk,
2693 opcode->name, avr_isr.prev_chunk, avr_isr.file, avr_isr.line);
2694 else
2695 as_bad (_("`%s %d' but no chunk open yet"), opcode->name, chunk);
2696 }
2697
2698 if (!had_errors())
2699 {
2700 /* The longest sequence (prologue) might have up to 6 insns (words):
2701
2702 push R0
2703 in R0, SREG
2704 push R0
2705 push R1
2706 clr R1
2707 push Rx
2708 */
2709 unsigned int size = 2 * 6;
2710 fragS *fr;
2711
2712 switch (chunk)
2713 {
2714 case ISR_CHUNK_Prologue:
2715 avr_isr.need_reg_tmp = 0;
2716 avr_isr.need_reg_zero = 0;
2717 avr_isr.need_sreg = 0;
2718 avr_isr.sym_n_pushed = NULL;
2719 /* FALLTHRU */
2720
2721 case ISR_CHUNK_Epilogue:
2722 /* Emit a new rs_machine_dependent fragment into the fragment chain.
2723 It will be patched and cleaned up once we see the matching
2724 ISR_CHUNK_Done. */
2725 frag_wane (frag_now);
2726 frag_new (0);
2727 frag_more (size);
2728
2729 frag_now->fr_var = 1;
2730 frag_now->fr_offset = size;
2731 frag_now->fr_fix = 0;
2732 frag_now->fr_type = rs_machine_dependent;
2733 frag_now->fr_subtype = chunk;
2734 frag_new (size);
2735 break;
2736
2737 case ISR_CHUNK_Done:
2738 /* Traverse all frags of the current subseg and turn ones of type
2739 rs_machine_dependent into ordinary code as expected by GCC. */
2740
2741 for (fr = frchain_now->frch_root; fr; fr = fr->fr_next)
2742 if (fr->fr_type == rs_machine_dependent)
2743 avr_patch_gccisr_frag (fr, reg);
2744 break;
2745
2746 default:
2747 abort();
2748 break;
2749 }
2750 } /* !had_errors */
2751
2752 avr_isr.prev_chunk = chunk;
2753 avr_isr.file = as_where (&avr_isr.line);
2754}
2755
2756
2757/* Callback used by the function below. Diagnose any dangling stuff from
2758 `__gcc_isr', i.e. frags of type rs_machine_dependent. Such frags should
2759 have been resolved during parse by ISR_CHUNK_Done. If such a frag is
2760 seen, report an error and turn it into something harmless. */
2761
2762static void
2763avr_check_gccisr_done (bfd *abfd ATTRIBUTE_UNUSED,
2764 segT section,
2765 void *xxx ATTRIBUTE_UNUSED)
2766{
2767 segment_info_type *info = seg_info (section);
2768
2769 if (SEG_NORMAL (section)
2770 /* BFD may have introduced its own sections without using
2771 subseg_new, so it is possible that seg_info is NULL. */
2772 && info)
2773 {
2774 fragS *fr;
2775 frchainS *frch;
2776
2777 for (frch = info->frchainP; frch; frch = frch->frch_next)
2778 for (fr = frch->frch_root; fr; fr = fr->fr_next)
2779 if (fr->fr_type == rs_machine_dependent)
2780 {
2781 if (avr_isr.file)
2782 as_bad_where (avr_isr.file, avr_isr.line,
2783 _("dangling `__gcc_isr %d'"), avr_isr.prev_chunk);
2784 else if (!had_errors())
2785 as_bad (_("dangling `__gcc_isr'"));
2786
2787 avr_isr.file = NULL;
2788
2789 /* Avoid Internal errors due to rs_machine_dependent in the
2790 remainder: Turn frag into something harmless. */
2791 fr->fr_var = 0;
2792 fr->fr_fix = 0;
2793 fr->fr_offset = 0;
2794 fr->fr_type = rs_fill;
2795 fr->fr_subtype = 0;
2796 }
2797 }
2798}
2799
2800
2801/* Implement `md_pre_output_hook' */
2802/* Run over all relevant sections and diagnose any dangling `__gcc_isr'.
2803 This runs after parsing all inputs but before relaxing and writing. */
2804
2805void
2806avr_pre_output_hook (void)
2807{
2808 if (avr_opt.have_gccisr)
2809 bfd_map_over_sections (stdoutput, avr_check_gccisr_done, NULL);
2810}
GDB Binutils - Deliverables
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