PR 10437
[deliverable/binutils-gdb.git] / gas / config / tc-fr30.c
CommitLineData
252b5132 1/* tc-fr30.c -- Assembler for the Fujitsu FR30.
20203fb9 2 Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2009
ae6063d4 3 Free Software Foundation, Inc.
252b5132
RH
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
ec2655a6 9 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
4b4da160
NC
19 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
20 Boston, MA 02110-1301, USA. */
252b5132 21
252b5132 22#include "as.h"
3882b010 23#include "safe-ctype.h"
81d4177b 24#include "subsegs.h"
252b5132
RH
25#include "symcat.h"
26#include "opcodes/fr30-desc.h"
27#include "opcodes/fr30-opc.h"
28#include "cgen.h"
29
30/* Structure to hold all of the different components describing
31 an individual instruction. */
32typedef struct
33{
34 const CGEN_INSN * insn;
35 const CGEN_INSN * orig_insn;
36 CGEN_FIELDS fields;
37#if CGEN_INT_INSN_P
38 CGEN_INSN_INT buffer [1];
39#define INSN_VALUE(buf) (*(buf))
40#else
41 unsigned char buffer [CGEN_MAX_INSN_SIZE];
42#define INSN_VALUE(buf) (buf)
43#endif
44 char * addr;
45 fragS * frag;
46 int num_fixups;
47 fixS * fixups [GAS_CGEN_MAX_FIXUPS];
48 int indices [MAX_OPERAND_INSTANCES];
49}
50fr30_insn;
51
52const char comment_chars[] = ";";
53const char line_comment_chars[] = "#";
54const char line_separator_chars[] = "|";
55const char EXP_CHARS[] = "eE";
56const char FLT_CHARS[] = "dD";
57\f
58#define FR30_SHORTOPTS ""
59const char * md_shortopts = FR30_SHORTOPTS;
60
61struct option md_longopts[] =
62{
63 {NULL, no_argument, NULL, 0}
64};
65size_t md_longopts_size = sizeof (md_longopts);
66
67int
ea1562b3
NC
68md_parse_option (int c ATTRIBUTE_UNUSED,
69 char *arg ATTRIBUTE_UNUSED)
252b5132
RH
70{
71 switch (c)
72 {
73 default:
74 return 0;
75 }
76 return 1;
77}
78
79void
ea1562b3 80md_show_usage (FILE * stream)
252b5132
RH
81{
82 fprintf (stream, _(" FR30 specific command line options:\n"));
81d4177b 83}
252b5132
RH
84
85/* The target specific pseudo-ops which we support. */
86const pseudo_typeS md_pseudo_table[] =
87{
88 { "word", cons, 4 },
89 { NULL, NULL, 0 }
90};
91
92\f
93void
ea1562b3 94md_begin (void)
252b5132 95{
252b5132 96 /* Initialize the `cgen' interface. */
81d4177b 97
252b5132
RH
98 /* Set the machine number and endian. */
99 gas_cgen_cpu_desc = fr30_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0,
100 CGEN_CPU_OPEN_ENDIAN,
101 CGEN_ENDIAN_BIG,
102 CGEN_CPU_OPEN_END);
103 fr30_cgen_init_asm (gas_cgen_cpu_desc);
104
105 /* This is a callback from cgen to gas to parse operands. */
106 cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
107}
108
109void
ea1562b3 110md_assemble (char *str)
252b5132
RH
111{
112 static int last_insn_had_delay_slot = 0;
113 fr30_insn insn;
33b5881a 114 char *errmsg;
252b5132
RH
115
116 /* Initialize GAS's cgen interface for a new instruction. */
117 gas_cgen_init_parse ();
118
119 insn.insn = fr30_cgen_assemble_insn
120 (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
81d4177b 121
252b5132
RH
122 if (!insn.insn)
123 {
20203fb9 124 as_bad ("%s", errmsg);
252b5132
RH
125 return;
126 }
127
128 /* Doesn't really matter what we pass for RELAX_P here. */
129 gas_cgen_finish_insn (insn.insn, insn.buffer,
130 CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
131
132 /* Warn about invalid insns in delay slots. */
133 if (last_insn_had_delay_slot
134 && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_NOT_IN_DELAY_SLOT))
135 as_warn (_("Instruction %s not allowed in a delay slot."),
136 CGEN_INSN_NAME (insn.insn));
137
138 last_insn_had_delay_slot
139 = CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_DELAY_SLOT);
140}
141
142/* The syntax in the manual says constants begin with '#'.
143 We just ignore it. */
144
81d4177b 145void
ea1562b3 146md_operand (expressionS * expressionP)
252b5132
RH
147{
148 if (* input_line_pointer == '#')
149 {
150 input_line_pointer ++;
151 expression (expressionP);
152 }
153}
154
155valueT
ea1562b3 156md_section_align (segT segment, valueT size)
252b5132
RH
157{
158 int align = bfd_get_section_alignment (stdoutput, segment);
ea1562b3 159
252b5132
RH
160 return ((size + (1 << align) - 1) & (-1 << align));
161}
162
163symbolS *
ea1562b3 164md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132 165{
ea1562b3 166 return NULL;
252b5132
RH
167}
168\f
169/* Interface to relax_segment. */
170
171/* FIXME: Build table by hand, get it working, then machine generate. */
172
173const relax_typeS md_relax_table[] =
174{
175/* The fields are:
176 1) most positive reach of this state,
177 2) most negative reach of this state,
178 3) how many bytes this mode will add to the size of the current frag
179 4) which index into the table to try if we can't fit into this one. */
180
181 /* The first entry must be unused because an `rlx_more' value of zero ends
182 each list. */
183 {1, 1, 0, 0},
184
185 /* The displacement used by GAS is from the end of the 2 byte insn,
186 so we subtract 2 from the following. */
187 /* 16 bit insn, 8 bit disp -> 10 bit range.
188 This doesn't handle a branch in the right slot at the border:
189 the "& -4" isn't taken into account. It's not important enough to
190 complicate things over it, so we subtract an extra 2 (or + 2 in -ve
191 case). */
192 {511 - 2 - 2, -512 - 2 + 2, 0, 2 },
193 /* 32 bit insn, 24 bit disp -> 26 bit range. */
194 {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 },
195 /* Same thing, but with leading nop for alignment. */
196 {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 }
197};
198
252b5132
RH
199/* Return an initial guess of the length by which a fragment must grow to
200 hold a branch to reach its destination.
201 Also updates fr_type/fr_subtype as necessary.
202
203 Called just before doing relaxation.
204 Any symbol that is now undefined will not become defined.
205 The guess for fr_var is ACTUALLY the growth beyond fr_fix.
206 Whatever we do to grow fr_fix or fr_var contributes to our returned value.
207 Although it may not be explicit in the frag, pretend fr_var starts with a
208 0 value. */
209
210int
ea1562b3 211md_estimate_size_before_relax (fragS * fragP, segT segment)
252b5132 212{
252b5132
RH
213 /* The only thing we have to handle here are symbols outside of the
214 current segment. They may be undefined or in a different segment in
215 which case linker scripts may place them anywhere.
216 However, we can't finish the fragment here and emit the reloc as insn
217 alignment requirements may move the insn about. */
218
219 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
220 {
221 /* The symbol is undefined in this segment.
222 Change the relaxation subtype to the max allowable and leave
223 all further handling to md_convert_frag. */
224 fragP->fr_subtype = 2;
225
252b5132
RH
226 {
227 const CGEN_INSN * insn;
228 int i;
229
230 /* Update the recorded insn.
231 Fortunately we don't have to look very far.
232 FIXME: Change this to record in the instruction the next higher
233 relaxable insn to use. */
234 for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++)
235 {
236 if ((strcmp (CGEN_INSN_MNEMONIC (insn),
237 CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn))
238 == 0)
b11dcf4e 239 && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED))
252b5132
RH
240 break;
241 }
242 if (i == 4)
243 abort ();
244
245 fragP->fr_cgen.insn = insn;
246 return 2;
247 }
252b5132
RH
248 }
249
606ab118
AM
250 /* Return the size of the variable part of the frag. */
251 return md_relax_table[fragP->fr_subtype].rlx_length;
81d4177b 252}
252b5132
RH
253
254/* *fragP has been relaxed to its final size, and now needs to have
255 the bytes inside it modified to conform to the new size.
256
257 Called after relaxation is finished.
258 fragP->fr_type == rs_machine_dependent.
259 fragP->fr_subtype is the subtype of what the address relaxed to. */
260
261void
ea1562b3
NC
262md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
263 segT sec ATTRIBUTE_UNUSED,
264 fragS *fragP ATTRIBUTE_UNUSED)
252b5132 265{
252b5132
RH
266}
267\f
268/* Functions concerning relocs. */
269
270/* The location from which a PC relative jump should be calculated,
271 given a PC relative reloc. */
272
273long
ea1562b3 274md_pcrel_from_section (fixS * fixP, segT sec)
252b5132
RH
275{
276 if (fixP->fx_addsy != (symbolS *) NULL
277 && (! S_IS_DEFINED (fixP->fx_addsy)
278 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
ea1562b3
NC
279 /* The symbol is undefined (or is defined but not in this section).
280 Let the linker figure it out. */
281 return 0;
252b5132
RH
282
283 return (fixP->fx_frag->fr_address + fixP->fx_where) & ~1;
284}
285
286/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
287 Returns BFD_RELOC_NONE if no reloc type can be found.
288 *FIXP may be modified if desired. */
289
290bfd_reloc_code_real_type
ea1562b3
NC
291md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED,
292 const CGEN_OPERAND *operand,
293 fixS *fixP)
252b5132
RH
294{
295 switch (operand->type)
296 {
297 case FR30_OPERAND_LABEL9: fixP->fx_pcrel = 1; return BFD_RELOC_FR30_9_PCREL;
298 case FR30_OPERAND_LABEL12: fixP->fx_pcrel = 1; return BFD_RELOC_FR30_12_PCREL;
299 case FR30_OPERAND_DISP10: return BFD_RELOC_FR30_10_IN_8;
300 case FR30_OPERAND_DISP9: return BFD_RELOC_FR30_9_IN_8;
301 case FR30_OPERAND_DISP8: return BFD_RELOC_FR30_8_IN_8;
302 case FR30_OPERAND_UDISP6: return BFD_RELOC_FR30_6_IN_4;
303 case FR30_OPERAND_I8: return BFD_RELOC_8;
304 case FR30_OPERAND_I32: return BFD_RELOC_FR30_48;
305 case FR30_OPERAND_I20: return BFD_RELOC_FR30_20;
ea1562b3 306 default : /* Avoid -Wall warning. */
252b5132
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307 break;
308 }
309
310 return BFD_RELOC_NONE;
311}
252b5132
RH
312\f
313/* Write a value out to the object file, using the appropriate endianness. */
314
315void
ea1562b3 316md_number_to_chars (char * buf, valueT val, int n)
252b5132
RH
317{
318 number_to_chars_bigendian (buf, val, n);
319}
320
252b5132 321char *
ea1562b3 322md_atof (int type, char * litP, int * sizeP)
252b5132 323{
499ac353 324 return ieee_md_atof (type, litP, sizeP, TRUE);
252b5132
RH
325}
326
327/* Worker function for fr30_is_colon_insn(). */
328static char
ea1562b3 329restore_colon (int advance_i_l_p_by)
252b5132
RH
330{
331 char c;
81d4177b 332
252b5132
RH
333 /* Restore the colon, and advance input_line_pointer to
334 the end of the new symbol. */
335 * input_line_pointer = ':';
336 input_line_pointer += advance_i_l_p_by;
337 c = * input_line_pointer;
338 * input_line_pointer = 0;
81d4177b 339
252b5132
RH
340 return c;
341}
342
343/* Determines if the symbol starting at START and ending in
344 a colon that was at the location pointed to by INPUT_LINE_POINTER
345 (but which has now been replaced bu a NUL) is in fact an
346 LDI:8, LDI:20, LDI:32, CALL:D. JMP:D, RET:D or Bcc:D instruction.
347 If it is, then it restores the colon, advances INPUT_LINE_POINTER
348 to the real end of the instruction/symbol, and returns the character
349 that really terminated the symbol. Otherwise it returns 0. */
350char
ea1562b3 351fr30_is_colon_insn (char * start)
252b5132
RH
352{
353 char * i_l_p = input_line_pointer;
354
ea1562b3 355 /* Check to see if the symbol parsed so far is 'ldi'. */
252b5132
RH
356 if ( (start[0] != 'l' && start[0] != 'L')
357 || (start[1] != 'd' && start[1] != 'D')
358 || (start[2] != 'i' && start[2] != 'I')
359 || start[3] != 0)
360 {
361 /* Nope - check to see a 'd' follows the colon. */
362 if ( (i_l_p[1] == 'd' || i_l_p[1] == 'D')
363 && (i_l_p[2] == ' ' || i_l_p[2] == '\t' || i_l_p[2] == '\n'))
364 {
365 /* Yup - it might be delay slot instruction. */
366 int i;
367 static char * delay_insns [] =
368 {
369 "call", "jmp", "ret", "bra", "bno",
370 "beq", "bne", "bc", "bnc", "bn",
371 "bp", "bv", "bnv", "blt", "bge",
372 "ble", "bgt", "bls", "bhi"
373 };
374
375 for (i = sizeof (delay_insns) / sizeof (delay_insns[0]); i--;)
376 {
377 char * insn = delay_insns[i];
378 int len = strlen (insn);
379
380 if (start [len] != 0)
381 continue;
81d4177b 382
252b5132 383 while (len --)
3882b010 384 if (TOLOWER (start [len]) != insn [len])
252b5132 385 break;
81d4177b 386
252b5132
RH
387 if (len == -1)
388 return restore_colon (1);
389 }
390 }
391
392 /* Nope - it is a normal label. */
393 return 0;
394 }
395
ea1562b3 396 /* Check to see if the text following the colon is '8'. */
252b5132
RH
397 if (i_l_p[1] == '8' && (i_l_p[2] == ' ' || i_l_p[2] == '\t'))
398 return restore_colon (2);
399
ea1562b3 400 /* Check to see if the text following the colon is '20'. */
252b5132
RH
401 else if (i_l_p[1] == '2' && i_l_p[2] =='0' && (i_l_p[3] == ' ' || i_l_p[3] == '\t'))
402 return restore_colon (3);
403
ea1562b3 404 /* Check to see if the text following the colon is '32'. */
252b5132
RH
405 else if (i_l_p[1] == '3' && i_l_p[2] =='2' && (i_l_p[3] == ' ' || i_l_p[3] == '\t'))
406 return restore_colon (3);
407
408 return 0;
409}
410
b34976b6 411bfd_boolean
ea1562b3 412fr30_fix_adjustable (fixS * fixP)
252b5132 413{
ea1562b3 414 /* We need the symbol name for the VTABLE entries. */
a161fe53 415 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
252b5132
RH
416 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
417 return 0;
418
419 return 1;
420}
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