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Update year range in copyright notice of binutils files
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
219d1afa 2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d 68#define LOCK_PREFIX 5
4e9ac44a
L		 69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 136}
137arch_entry;
138
293f5f65
L		 139/* Used to turn off indicated flags. */
140typedef struct
141{
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145}
146noarch_entry;
147
78f12dd3 148static void update_code_flag (int, int);
e3bb37b5
L		 149static void set_code_flag (int);
150static void set_16bit_gcc_code_flag (int);
151static void set_intel_syntax (int);
1efbbeb4 152static void set_intel_mnemonic (int);
db51cc60 153static void set_allow_index_reg (int);
7bab8ab5 154static void set_check (int);
e3bb37b5 155static void set_cpu_arch (int);
6482c264 156#ifdef TE_PE
e3bb37b5 157static void pe_directive_secrel (int);
6482c264 158#endif
e3bb37b5
L		 159static void signed_cons (int);
160static char *output_invalid (int c);
ee86248c
JB		 161static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
a7619375 165static int i386_att_operand (char *);
e3bb37b5 166static int i386_intel_operand (char *, int);
ee86248c
JB		 167static int i386_intel_simplify (expressionS *);
168static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 169static const reg_entry *parse_register (char *, char **);
170static char *parse_insn (char *, char *);
171static char *parse_operands (char *, const char *);
172static void swap_operands (void);
4d456e3d 173static void swap_2_operands (int, int);
e3bb37b5
L		 174static void optimize_imm (void);
175static void optimize_disp (void);
83b16ac6 176static const insn_template *match_template (char);
e3bb37b5
L		 177static int check_string (void);
178static int process_suffix (void);
179static int check_byte_reg (void);
180static int check_long_reg (void);
181static int check_qword_reg (void);
182static int check_word_reg (void);
183static int finalize_imm (void);
184static int process_operands (void);
185static const seg_entry *build_modrm_byte (void);
186static void output_insn (void);
187static void output_imm (fragS *, offsetT);
188static void output_disp (fragS *, offsetT);
29b0f896 189#ifndef I386COFF
e3bb37b5 190static void s_bss (int);
252b5132 191#endif
17d4e2a2
L		 192#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193static void handle_large_common (int small ATTRIBUTE_UNUSED);
194#endif
252b5132 195
a847613f 196static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 197
43234a1e
L		 198/* This struct describes rounding control and SAE in the instruction. */
199struct RC_Operation
200{
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210};
211
212static struct RC_Operation rc_op;
213
214/* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217struct Mask_Operation
218{
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223};
224
225static struct Mask_Operation mask_op;
226
227/* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229struct Broadcast_Operation
230{
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236};
237
238static struct Broadcast_Operation broadcast_op;
239
c0f3af97
L		 240/* VEX prefix. */
241typedef struct
242{
43234a1e
L		 243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
c0f3af97
L		 245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248} vex_prefix;
249
252b5132 250/* 'md_assemble ()' gathers together information and puts it into a
47926f60 251 i386_insn. */
252b5132 252
520dc8e8
AM		 253union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
a65babc9
L		 260enum i386_error
261 {
86e026a4 262 operand_size_mismatch,
a65babc9
L		 263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
6c30d220
L		 271 unsupported,
272 invalid_vsib_address,
7bab8ab5 273 invalid_vector_register_set,
43234a1e
L		 274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
a65babc9
L		 284 };
285
252b5132
RH		 286struct _i386_insn
287 {
47926f60 288 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 289 insn_template tm;
252b5132 290
7d5e4556
L		 291 /* SUFFIX holds the instruction size suffix for byte, word, dword
292 or qword, if given. */
252b5132
RH		 293 char suffix;
294
47926f60 295 /* OPERANDS gives the number of given operands. */
252b5132
RH		 296 unsigned int operands;
297
298 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
299 of given register, displacement, memory operands and immediate
47926f60 300 operands. */
252b5132
RH		 301 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
302
303 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 304 use OP[i] for the corresponding operand. */
40fb9820 305 i386_operand_type types[MAX_OPERANDS];
252b5132 306
520dc8e8
AM		 307 /* Displacement expression, immediate expression, or register for each
308 operand. */
309 union i386_op op[MAX_OPERANDS];
252b5132 310
3e73aa7c
JH		 311 /* Flags for operands. */
312 unsigned int flags[MAX_OPERANDS];
313#define Operand_PCrel 1
314
252b5132 315 /* Relocation type for operand */
f86103b7 316 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 317
252b5132
RH		 318 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
319 the base index byte below. */
320 const reg_entry *base_reg;
321 const reg_entry *index_reg;
322 unsigned int log2_scale_factor;
323
324 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 325 explicit segment overrides are given. */
ce8a8b2f 326 const seg_entry *seg[2];
252b5132 327
8325cc63
JB		 328 /* Copied first memory operand string, for re-checking. */
329 char *memop1_string;
330
252b5132
RH		 331 /* PREFIX holds all the given prefix opcodes (usually null).
332 PREFIXES is the number of prefix opcodes. */
333 unsigned int prefixes;
334 unsigned char prefix[MAX_PREFIXES];
335
336 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 337 addressing modes of this insn are encoded. */
252b5132 338 modrm_byte rm;
3e73aa7c 339 rex_byte rex;
43234a1e 340 rex_byte vrex;
252b5132 341 sib_byte sib;
c0f3af97 342 vex_prefix vex;
b6169b20 343
43234a1e
L		 344 /* Masking attributes. */
345 struct Mask_Operation *mask;
346
347 /* Rounding control and SAE attributes. */
348 struct RC_Operation *rounding;
349
350 /* Broadcasting attributes. */
351 struct Broadcast_Operation *broadcast;
352
353 /* Compressed disp8*N attribute. */
354 unsigned int memshift;
355
86fa6981
L		 356 /* Prefer load or store in encoding. */
357 enum
358 {
359 dir_encoding_default = 0,
360 dir_encoding_load,
361 dir_encoding_store
362 } dir_encoding;
891edac4 363
a501d77e
L		 364 /* Prefer 8bit or 32bit displacement in encoding. */
365 enum
366 {
367 disp_encoding_default = 0,
368 disp_encoding_8bit,
369 disp_encoding_32bit
370 } disp_encoding;
f8a5c266 371
86fa6981
L		 372 /* How to encode vector instructions. */
373 enum
374 {
375 vex_encoding_default = 0,
376 vex_encoding_vex2,
377 vex_encoding_vex3,
378 vex_encoding_evex
379 } vec_encoding;
380
d5de92cf
L		 381 /* REP prefix. */
382 const char *rep_prefix;
383
165de32a
L		 384 /* HLE prefix. */
385 const char *hle_prefix;
42164a71 386
7e8b059b
L		 387 /* Have BND prefix. */
388 const char *bnd_prefix;
389
04ef582a
L		 390 /* Have NOTRACK prefix. */
391 const char *notrack_prefix;
392
891edac4 393 /* Error message. */
a65babc9 394 enum i386_error error;
252b5132
RH		 395 };
396
397typedef struct _i386_insn i386_insn;
398
43234a1e
L		 399/* Link RC type with corresponding string, that'll be looked for in
400 asm. */
401struct RC_name
402{
403 enum rc_type type;
404 const char *name;
405 unsigned int len;
406};
407
408static const struct RC_name RC_NamesTable[] =
409{
410 { rne, STRING_COMMA_LEN ("rn-sae") },
411 { rd, STRING_COMMA_LEN ("rd-sae") },
412 { ru, STRING_COMMA_LEN ("ru-sae") },
413 { rz, STRING_COMMA_LEN ("rz-sae") },
414 { saeonly, STRING_COMMA_LEN ("sae") },
415};
416
252b5132
RH		 417/* List of chars besides those in app.c:symbol_chars that can start an
418 operand. Used to prevent the scrubber eating vital white-space. */
86fa6981 419const char extra_symbol_chars[] = "*%-([{}"
252b5132 420#ifdef LEX_AT
32137342
NC		 421 "@"
422#endif
423#ifdef LEX_QM
424 "?"
252b5132 425#endif
32137342 426 ;
252b5132 427
29b0f896
AM		 428#if (defined (TE_I386AIX) \
429 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 430 && !defined (TE_GNU) \
29b0f896 431 && !defined (TE_LINUX) \
8d63c93e
RM		 432 && !defined (TE_NACL) \
433 && !defined (TE_NETWARE) \
29b0f896 434 && !defined (TE_FreeBSD) \
5b806d27 435 && !defined (TE_DragonFly) \
29b0f896 436 && !defined (TE_NetBSD)))
252b5132 437/* This array holds the chars that always start a comment. If the
b3b91714
AM		 438 pre-processor is disabled, these aren't very useful. The option
439 --divide will remove '/' from this list. */
440const char *i386_comment_chars = "#/";
441#define SVR4_COMMENT_CHARS 1
252b5132 442#define PREFIX_SEPARATOR '\\'
252b5132 443
b3b91714
AM		 444#else
445const char *i386_comment_chars = "#";
446#define PREFIX_SEPARATOR '/'
447#endif
448
252b5132
RH		 449/* This array holds the chars that only start a comment at the beginning of
450 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 451 .line and .file directives will appear in the pre-processed output.
452 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 453 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 454 #NO_APP at the beginning of its output.
455 Also note that comments started like this one will always work if
252b5132 456 '/' isn't otherwise defined. */
b3b91714 457const char line_comment_chars[] = "#/";
252b5132 458
63a0b638 459const char line_separator_chars[] = ";";
252b5132 460
ce8a8b2f
AM		 461/* Chars that can be used to separate mant from exp in floating point
462 nums. */
252b5132
RH		 463const char EXP_CHARS[] = "eE";
464
ce8a8b2f
AM		 465/* Chars that mean this number is a floating point constant
466 As in 0f12.456
467 or 0d1.2345e12. */
252b5132
RH		 468const char FLT_CHARS[] = "fFdDxX";
469
ce8a8b2f 470/* Tables for lexical analysis. */
252b5132
RH		 471static char mnemonic_chars[256];
472static char register_chars[256];
473static char operand_chars[256];
474static char identifier_chars[256];
475static char digit_chars[256];
476
ce8a8b2f 477/* Lexical macros. */
252b5132
RH		 478#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
479#define is_operand_char(x) (operand_chars[(unsigned char) x])
480#define is_register_char(x) (register_chars[(unsigned char) x])
481#define is_space_char(x) ((x) == ' ')
482#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
483#define is_digit_char(x) (digit_chars[(unsigned char) x])
484
0234cb7c 485/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 486static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
487
488/* md_assemble() always leaves the strings it's passed unaltered. To
489 effect this we maintain a stack of saved characters that we've smashed
490 with '\0's (indicating end of strings for various sub-fields of the
47926f60 491 assembler instruction). */
252b5132 492static char save_stack[32];
ce8a8b2f 493static char *save_stack_p;
252b5132
RH		 494#define END_STRING_AND_SAVE(s) \
495 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
496#define RESTORE_END_STRING(s) \
497 do { *(s) = *--save_stack_p; } while (0)
498
47926f60 499/* The instruction we're assembling. */
252b5132
RH		 500static i386_insn i;
501
502/* Possible templates for current insn. */
503static const templates *current_templates;
504
31b2323c
L		 505/* Per instruction expressionS buffers: max displacements & immediates. */
506static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
507static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 508
47926f60 509/* Current operand we are working on. */
ee86248c 510static int this_operand = -1;
252b5132 511
3e73aa7c
JH		 512/* We support four different modes. FLAG_CODE variable is used to distinguish
513 these. */
514
515enum flag_code {
516 CODE_32BIT,
517 CODE_16BIT,
518 CODE_64BIT };
519
520static enum flag_code flag_code;
4fa24527 521static unsigned int object_64bit;
862be3fb 522static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 523static int use_rela_relocations = 0;
524
7af8ed2d
NC		 525#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
526 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
527 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
528
351f65ca
L		 529/* The ELF ABI to use. */
530enum x86_elf_abi
531{
532 I386_ABI,
7f56bc95
L		 533 X86_64_ABI,
534 X86_64_X32_ABI
351f65ca
L		 535};
536
537static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 538#endif
351f65ca 539
167ad85b
TG		 540#if defined (TE_PE) || defined (TE_PEP)
541/* Use big object file format. */
542static int use_big_obj = 0;
543#endif
544
8dcea932
L		 545#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
546/* 1 if generating code for a shared library. */
547static int shared = 0;
548#endif
549
47926f60
KH		 550/* 1 for intel syntax,
551 0 if att syntax. */
552static int intel_syntax = 0;
252b5132 553
e89c5eaa
L		 554/* 1 for Intel64 ISA,
555 0 if AMD64 ISA. */
556static int intel64;
557
1efbbeb4
L		 558/* 1 for intel mnemonic,
559 0 if att mnemonic. */
560static int intel_mnemonic = !SYSV386_COMPAT;
561
5209009a 562/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 563static int old_gcc = OLDGCC_COMPAT;
564
a60de03c
JB		 565/* 1 if pseudo registers are permitted. */
566static int allow_pseudo_reg = 0;
567
47926f60
KH		 568/* 1 if register prefix % not required. */
569static int allow_naked_reg = 0;
252b5132 570
33eaf5de 571/* 1 if the assembler should add BND prefix for all control-transferring
7e8b059b
L		 572 instructions supporting it, even if this prefix wasn't specified
573 explicitly. */
574static int add_bnd_prefix = 0;
575
ba104c83 576/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 577static int allow_index_reg = 0;
578
d022bddd
IT		 579/* 1 if the assembler should ignore LOCK prefix, even if it was
580 specified explicitly. */
581static int omit_lock_prefix = 0;
582
e4e00185
AS		 583/* 1 if the assembler should encode lfence, mfence, and sfence as
584 "lock addl $0, (%{re}sp)". */
585static int avoid_fence = 0;
586
0cb4071e
L		 587/* 1 if the assembler should generate relax relocations. */
588
589static int generate_relax_relocations
590 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
591
7bab8ab5 592static enum check_kind
daf50ae7 593 {
7bab8ab5
JB		 594 check_none = 0,
595 check_warning,
596 check_error
daf50ae7 597 }
7bab8ab5 598sse_check, operand_check = check_warning;
daf50ae7 599
2ca3ace5
L		 600/* Register prefix used for error message. */
601static const char *register_prefix = "%";
602
47926f60
KH		 603/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
604 leave, push, and pop instructions so that gcc has the same stack
605 frame as in 32 bit mode. */
606static char stackop_size = '\0';
eecb386c 607
12b55ccc
L		 608/* Non-zero to optimize code alignment. */
609int optimize_align_code = 1;
610
47926f60
KH		 611/* Non-zero to quieten some warnings. */
612static int quiet_warnings = 0;
a38cf1db 613
47926f60
KH		 614/* CPU name. */
615static const char *cpu_arch_name = NULL;
6305a203 616static char *cpu_sub_arch_name = NULL;
a38cf1db 617
47926f60 618/* CPU feature flags. */
40fb9820
L		 619static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
620
ccc9c027
L		 621/* If we have selected a cpu we are generating instructions for. */
622static int cpu_arch_tune_set = 0;
623
9103f4f4 624/* Cpu we are generating instructions for. */
fbf3f584 625enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 626
627/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 628static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 629
ccc9c027 630/* CPU instruction set architecture used. */
fbf3f584 631enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 632
9103f4f4 633/* CPU feature flags of instruction set architecture used. */
fbf3f584 634i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 635
fddf5b5b
AM		 636/* If set, conditional jumps are not automatically promoted to handle
637 larger than a byte offset. */
638static unsigned int no_cond_jump_promotion = 0;
639
c0f3af97
L		 640/* Encode SSE instructions with VEX prefix. */
641static unsigned int sse2avx;
642
539f890d
L		 643/* Encode scalar AVX instructions with specific vector length. */
644static enum
645 {
646 vex128 = 0,
647 vex256
648 } avxscalar;
649
43234a1e
L		 650/* Encode scalar EVEX LIG instructions with specific vector length. */
651static enum
652 {
653 evexl128 = 0,
654 evexl256,
655 evexl512
656 } evexlig;
657
658/* Encode EVEX WIG instructions with specific evex.w. */
659static enum
660 {
661 evexw0 = 0,
662 evexw1
663 } evexwig;
664
d3d3c6db
IT		 665/* Value to encode in EVEX RC bits, for SAE-only instructions. */
666static enum rc_type evexrcig = rne;
667
29b0f896 668/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 669static symbolS *GOT_symbol;
29b0f896 670
a4447b93
RH		 671/* The dwarf2 return column, adjusted for 32 or 64 bit. */
672unsigned int x86_dwarf2_return_column;
673
674/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
675int x86_cie_data_alignment;
676
252b5132 677/* Interface to relax_segment.
fddf5b5b
AM		 678 There are 3 major relax states for 386 jump insns because the
679 different types of jumps add different sizes to frags when we're
680 figuring out what sort of jump to choose to reach a given label. */
252b5132 681
47926f60 682/* Types. */
93c2a809
AM		 683#define UNCOND_JUMP 0
684#define COND_JUMP 1
685#define COND_JUMP86 2
fddf5b5b 686
47926f60 687/* Sizes. */
252b5132
RH		 688#define CODE16 1
689#define SMALL 0
29b0f896 690#define SMALL16 (SMALL | CODE16)
252b5132 691#define BIG 2
29b0f896 692#define BIG16 (BIG | CODE16)
252b5132
RH		 693
694#ifndef INLINE
695#ifdef __GNUC__
696#define INLINE __inline__
697#else
698#define INLINE
699#endif
700#endif
701
fddf5b5b
AM		 702#define ENCODE_RELAX_STATE(type, size) \
703 ((relax_substateT) (((type) << 2) | (size)))
704#define TYPE_FROM_RELAX_STATE(s) \
705 ((s) >> 2)
706#define DISP_SIZE_FROM_RELAX_STATE(s) \
707 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 708
709/* This table is used by relax_frag to promote short jumps to long
710 ones where necessary. SMALL (short) jumps may be promoted to BIG
711 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
712 don't allow a short jump in a 32 bit code segment to be promoted to
713 a 16 bit offset jump because it's slower (requires data size
714 prefix), and doesn't work, unless the destination is in the bottom
715 64k of the code segment (The top 16 bits of eip are zeroed). */
716
717const relax_typeS md_relax_table[] =
718{
24eab124
AM		 719 /* The fields are:
720 1) most positive reach of this state,
721 2) most negative reach of this state,
93c2a809 722 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 723 4) which index into the table to try if we can't fit into this one. */
252b5132 724
fddf5b5b 725 /* UNCOND_JUMP states. */
93c2a809
AM		 726 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
727 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
728 /* dword jmp adds 4 bytes to frag:
729 0 extra opcode bytes, 4 displacement bytes. */
252b5132 730 {0, 0, 4, 0},
93c2a809
AM		 731 /* word jmp adds 2 byte2 to frag:
732 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 733 {0, 0, 2, 0},
734
93c2a809
AM		 735 /* COND_JUMP states. */
736 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
737 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
738 /* dword conditionals adds 5 bytes to frag:
739 1 extra opcode byte, 4 displacement bytes. */
740 {0, 0, 5, 0},
fddf5b5b 741 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 742 1 extra opcode byte, 2 displacement bytes. */
743 {0, 0, 3, 0},
744
745 /* COND_JUMP86 states. */
746 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
747 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
748 /* dword conditionals adds 5 bytes to frag:
749 1 extra opcode byte, 4 displacement bytes. */
750 {0, 0, 5, 0},
751 /* word conditionals add 4 bytes to frag:
752 1 displacement byte and a 3 byte long branch insn. */
753 {0, 0, 4, 0}
252b5132
RH		 754};
755
9103f4f4
L		 756static const arch_entry cpu_arch[] =
757{
89507696
JB		 758 /* Do not replace the first two entries - i386_target_format()
759 relies on them being there in this order. */
8a2c8fef 760 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 761 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 762 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 763 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 764 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 765 CPU_NONE_FLAGS, 0 },
8a2c8fef 766 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 767 CPU_I186_FLAGS, 0 },
8a2c8fef 768 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 769 CPU_I286_FLAGS, 0 },
8a2c8fef 770 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 771 CPU_I386_FLAGS, 0 },
8a2c8fef 772 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 773 CPU_I486_FLAGS, 0 },
8a2c8fef 774 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 775 CPU_I586_FLAGS, 0 },
8a2c8fef 776 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 777 CPU_I686_FLAGS, 0 },
8a2c8fef 778 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 779 CPU_I586_FLAGS, 0 },
8a2c8fef 780 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 781 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 782 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 783 CPU_P2_FLAGS, 0 },
8a2c8fef 784 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 785 CPU_P3_FLAGS, 0 },
8a2c8fef 786 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 787 CPU_P4_FLAGS, 0 },
8a2c8fef 788 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 789 CPU_CORE_FLAGS, 0 },
8a2c8fef 790 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 791 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 792 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 793 CPU_CORE_FLAGS, 1 },
8a2c8fef 794 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 795 CPU_CORE_FLAGS, 0 },
8a2c8fef 796 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 797 CPU_CORE2_FLAGS, 1 },
8a2c8fef 798 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 799 CPU_CORE2_FLAGS, 0 },
8a2c8fef 800 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 801 CPU_COREI7_FLAGS, 0 },
8a2c8fef 802 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 803 CPU_L1OM_FLAGS, 0 },
7a9068fe 804 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 805 CPU_K1OM_FLAGS, 0 },
81486035 806 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 807 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 808 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 809 CPU_K6_FLAGS, 0 },
8a2c8fef 810 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 811 CPU_K6_2_FLAGS, 0 },
8a2c8fef 812 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 813 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 814 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 815 CPU_K8_FLAGS, 1 },
8a2c8fef 816 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 817 CPU_K8_FLAGS, 0 },
8a2c8fef 818 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 819 CPU_K8_FLAGS, 0 },
8a2c8fef 820 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 821 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 822 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 823 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 824 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 825 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 826 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 827 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 828 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 829 CPU_BDVER4_FLAGS, 0 },
029f3522 830 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 831 CPU_ZNVER1_FLAGS, 0 },
7b458c12 832 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 833 CPU_BTVER1_FLAGS, 0 },
7b458c12 834 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 835 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 836 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 837 CPU_8087_FLAGS, 0 },
8a2c8fef 838 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 839 CPU_287_FLAGS, 0 },
8a2c8fef 840 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 841 CPU_387_FLAGS, 0 },
1848e567
L		 842 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
843 CPU_687_FLAGS, 0 },
8a2c8fef 844 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 845 CPU_MMX_FLAGS, 0 },
8a2c8fef 846 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 847 CPU_SSE_FLAGS, 0 },
8a2c8fef 848 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 849 CPU_SSE2_FLAGS, 0 },
8a2c8fef 850 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 851 CPU_SSE3_FLAGS, 0 },
8a2c8fef 852 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 853 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 854 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 855 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 856 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 857 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 858 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 859 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 860 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 861 CPU_AVX_FLAGS, 0 },
6c30d220 862 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 863 CPU_AVX2_FLAGS, 0 },
43234a1e 864 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 865 CPU_AVX512F_FLAGS, 0 },
43234a1e 866 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 867 CPU_AVX512CD_FLAGS, 0 },
43234a1e 868 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 869 CPU_AVX512ER_FLAGS, 0 },
43234a1e 870 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 871 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 872 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 873 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 874 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 875 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 876 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 877 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 878 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 879 CPU_VMX_FLAGS, 0 },
8729a6f6 880 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 881 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 882 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 883 CPU_SMX_FLAGS, 0 },
8a2c8fef 884 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 885 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 886 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 887 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 888 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 889 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 890 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 891 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 892 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 893 CPU_AES_FLAGS, 0 },
8a2c8fef 894 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 895 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 896 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 897 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 898 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 899 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 900 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 901 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 902 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 903 CPU_F16C_FLAGS, 0 },
6c30d220 904 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 905 CPU_BMI2_FLAGS, 0 },
8a2c8fef 906 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 907 CPU_FMA_FLAGS, 0 },
8a2c8fef 908 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 909 CPU_FMA4_FLAGS, 0 },
8a2c8fef 910 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 911 CPU_XOP_FLAGS, 0 },
8a2c8fef 912 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 913 CPU_LWP_FLAGS, 0 },
8a2c8fef 914 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 915 CPU_MOVBE_FLAGS, 0 },
60aa667e 916 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 917 CPU_CX16_FLAGS, 0 },
8a2c8fef 918 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 919 CPU_EPT_FLAGS, 0 },
6c30d220 920 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 921 CPU_LZCNT_FLAGS, 0 },
42164a71 922 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 923 CPU_HLE_FLAGS, 0 },
42164a71 924 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 925 CPU_RTM_FLAGS, 0 },
6c30d220 926 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 927 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 928 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 929 CPU_CLFLUSH_FLAGS, 0 },
22109423 930 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 931 CPU_NOP_FLAGS, 0 },
8a2c8fef 932 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 933 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 934 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 935 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 936 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 937 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 938 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 939 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 940 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 941 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 942 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 943 CPU_SVME_FLAGS, 1 },
8a2c8fef 944 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 945 CPU_SVME_FLAGS, 0 },
8a2c8fef 946 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 947 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 948 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 949 CPU_ABM_FLAGS, 0 },
87973e9f 950 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 951 CPU_BMI_FLAGS, 0 },
2a2a0f38 952 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 953 CPU_TBM_FLAGS, 0 },
e2e1fcde 954 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 955 CPU_ADX_FLAGS, 0 },
e2e1fcde 956 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 957 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 958 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 959 CPU_PRFCHW_FLAGS, 0 },
5c111e37 960 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 961 CPU_SMAP_FLAGS, 0 },
7e8b059b 962 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 963 CPU_MPX_FLAGS, 0 },
a0046408 964 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 965 CPU_SHA_FLAGS, 0 },
963f3586 966 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 967 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 968 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 969 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 970 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 971 CPU_SE1_FLAGS, 0 },
c5e7287a 972 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 973 CPU_CLWB_FLAGS, 0 },
2cc1b5aa 974 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 975 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 976 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 977 CPU_AVX512VBMI_FLAGS, 0 },
920d2ddc
IT		 978 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
979 CPU_AVX512_4FMAPS_FLAGS, 0 },
47acf0bd
IT		 980 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
981 CPU_AVX512_4VNNIW_FLAGS, 0 },
620214f7
IT		 982 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
983 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
53467f57
IT		 984 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
985 CPU_AVX512_VBMI2_FLAGS, 0 },
8cfcb765
IT		 986 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
987 CPU_AVX512_VNNI_FLAGS, 0 },
ee6872be
IT		 988 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
989 CPU_AVX512_BITALG_FLAGS, 0 },
029f3522 990 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 991 CPU_CLZERO_FLAGS, 0 },
9916071f 992 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 993 CPU_MWAITX_FLAGS, 0 },
8eab4136 994 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 995 CPU_OSPKE_FLAGS, 0 },
8bc52696 996 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 997 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 998 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
999 CPU_PTWRITE_FLAGS, 0 },
603555e5
L		 1000 { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN,
1001 CPU_CET_FLAGS, 0 },
48521003
IT		 1002 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1003 CPU_GFNI_FLAGS, 0 },
8dcf1fad
IT		 1004 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1005 CPU_VAES_FLAGS, 0 },
ff1982d5
IT		 1006 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1007 CPU_VPCLMULQDQ_FLAGS, 0 },
293f5f65
L		 1008};
1009
1010static const noarch_entry cpu_noarch[] =
1011{
1012 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 1013 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1014 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1015 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 1016 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1017 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 1018 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1019 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1020 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1021 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1022 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1023 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 1024 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 1025 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 1026 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1027 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1028 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1029 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1030 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1031 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1032 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1033 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1034 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
920d2ddc 1035 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
47acf0bd 1036 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
620214f7 1037 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
53467f57 1038 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
8cfcb765 1039 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
ee6872be 1040 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
e413e4e9
AM		 1041};
1042
704209c0 1043#ifdef I386COFF
a6c24e68
NC		 1044/* Like s_lcomm_internal in gas/read.c but the alignment string
1045 is allowed to be optional. */
1046
1047static symbolS *
1048pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1049{
1050 addressT align = 0;
1051
1052 SKIP_WHITESPACE ();
1053
7ab9ffdd 1054 if (needs_align
a6c24e68
NC		 1055 && *input_line_pointer == ',')
1056 {
1057 align = parse_align (needs_align - 1);
7ab9ffdd 1058
a6c24e68
NC		 1059 if (align == (addressT) -1)
1060 return NULL;
1061 }
1062 else
1063 {
1064 if (size >= 8)
1065 align = 3;
1066 else if (size >= 4)
1067 align = 2;
1068 else if (size >= 2)
1069 align = 1;
1070 else
1071 align = 0;
1072 }
1073
1074 bss_alloc (symbolP, size, align);
1075 return symbolP;
1076}
1077
704209c0 1078static void
a6c24e68
NC		 1079pe_lcomm (int needs_align)
1080{
1081 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1082}
704209c0 1083#endif
a6c24e68 1084
29b0f896
AM		 1085const pseudo_typeS md_pseudo_table[] =
1086{
1087#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1088 {"align", s_align_bytes, 0},
1089#else
1090 {"align", s_align_ptwo, 0},
1091#endif
1092 {"arch", set_cpu_arch, 0},
1093#ifndef I386COFF
1094 {"bss", s_bss, 0},
a6c24e68
NC		 1095#else
1096 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1097#endif
1098 {"ffloat", float_cons, 'f'},
1099 {"dfloat", float_cons, 'd'},
1100 {"tfloat", float_cons, 'x'},
1101 {"value", cons, 2},
d182319b 1102 {"slong", signed_cons, 4},
29b0f896
AM		 1103 {"noopt", s_ignore, 0},
1104 {"optim", s_ignore, 0},
1105 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1106 {"code16", set_code_flag, CODE_16BIT},
1107 {"code32", set_code_flag, CODE_32BIT},
da5f19a2 1108#ifdef BFD64
29b0f896 1109 {"code64", set_code_flag, CODE_64BIT},
da5f19a2 1110#endif
29b0f896
AM		 1111 {"intel_syntax", set_intel_syntax, 1},
1112 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1113 {"intel_mnemonic", set_intel_mnemonic, 1},
1114 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1115 {"allow_index_reg", set_allow_index_reg, 1},
1116 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1117 {"sse_check", set_check, 0},
1118 {"operand_check", set_check, 1},
3b22753a
L		 1119#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1120 {"largecomm", handle_large_common, 0},
07a53e5c 1121#else
e3bb37b5 1122 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1123 {"loc", dwarf2_directive_loc, 0},
1124 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1125#endif
6482c264
NC		 1126#ifdef TE_PE
1127 {"secrel32", pe_directive_secrel, 0},
1128#endif
29b0f896
AM		 1129 {0, 0, 0}
1130};
1131
1132/* For interface with expression (). */
1133extern char *input_line_pointer;
1134
1135/* Hash table for instruction mnemonic lookup. */
1136static struct hash_control *op_hash;
1137
1138/* Hash table for register lookup. */
1139static struct hash_control *reg_hash;
1140\f
252b5132 1141void
e3bb37b5 1142i386_align_code (fragS *fragP, int count)
252b5132 1143{
ce8a8b2f
AM		 1144 /* Various efficient no-op patterns for aligning code labels.
1145 Note: Don't try to assemble the instructions in the comments.
1146 0L and 0w are not legal. */
bad6e36d 1147 static const unsigned char f32_1[] =
252b5132 1148 {0x90}; /* nop */
bad6e36d 1149 static const unsigned char f32_2[] =
ccc9c027 1150 {0x66,0x90}; /* xchg %ax,%ax */
bad6e36d 1151 static const unsigned char f32_3[] =
252b5132 1152 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
bad6e36d 1153 static const unsigned char f32_4[] =
252b5132 1154 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1155 static const unsigned char f32_5[] =
252b5132
RH		 1156 {0x90, /* nop */
1157 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1158 static const unsigned char f32_6[] =
252b5132 1159 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
bad6e36d 1160 static const unsigned char f32_7[] =
252b5132 1161 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1162 static const unsigned char f32_8[] =
252b5132
RH		 1163 {0x90, /* nop */
1164 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1165 static const unsigned char f32_9[] =
252b5132
RH		 1166 {0x89,0xf6, /* movl %esi,%esi */
1167 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1168 static const unsigned char f32_10[] =
252b5132
RH		 1169 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1170 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1171 static const unsigned char f32_11[] =
252b5132
RH		 1172 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1173 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1174 static const unsigned char f32_12[] =
252b5132
RH		 1175 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1176 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
bad6e36d 1177 static const unsigned char f32_13[] =
252b5132
RH		 1178 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1179 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1180 static const unsigned char f32_14[] =
252b5132
RH		 1181 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1182 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1183 static const unsigned char f16_3[] =
c3332e24 1184 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
bad6e36d 1185 static const unsigned char f16_4[] =
252b5132 1186 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1187 static const unsigned char f16_5[] =
252b5132
RH		 1188 {0x90, /* nop */
1189 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1190 static const unsigned char f16_6[] =
252b5132
RH		 1191 {0x89,0xf6, /* mov %si,%si */
1192 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1193 static const unsigned char f16_7[] =
252b5132
RH		 1194 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1195 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1196 static const unsigned char f16_8[] =
252b5132
RH		 1197 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1198 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1199 static const unsigned char jump_31[] =
76bc74dc
L		 1200 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1201 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1202 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1203 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
bad6e36d 1204 static const unsigned char *const f32_patt[] = {
252b5132 1205 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1206 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132 1207 };
bad6e36d 1208 static const unsigned char *const f16_patt[] = {
76bc74dc 1209 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1210 };
ccc9c027 1211 /* nopl (%[re]ax) */
bad6e36d 1212 static const unsigned char alt_3[] =
ccc9c027
L		 1213 {0x0f,0x1f,0x00};
1214 /* nopl 0(%[re]ax) */
bad6e36d 1215 static const unsigned char alt_4[] =
ccc9c027
L		 1216 {0x0f,0x1f,0x40,0x00};
1217 /* nopl 0(%[re]ax,%[re]ax,1) */
bad6e36d 1218 static const unsigned char alt_5[] =
ccc9c027
L		 1219 {0x0f,0x1f,0x44,0x00,0x00};
1220 /* nopw 0(%[re]ax,%[re]ax,1) */
bad6e36d 1221 static const unsigned char alt_6[] =
ccc9c027
L		 1222 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1223 /* nopl 0L(%[re]ax) */
bad6e36d 1224 static const unsigned char alt_7[] =
ccc9c027
L		 1225 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1226 /* nopl 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1227 static const unsigned char alt_8[] =
ccc9c027
L		 1228 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1229 /* nopw 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1230 static const unsigned char alt_9[] =
ccc9c027
L		 1231 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1232 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
bad6e36d 1233 static const unsigned char alt_10[] =
ccc9c027 1234 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
bad6e36d 1235 static const unsigned char *const alt_patt[] = {
ccc9c027 1236 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1237 alt_9, alt_10
ccc9c027 1238 };
252b5132 1239
76bc74dc
L		 1240 /* Only align for at least a positive non-zero boundary. */
1241 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1242 return;
3e73aa7c 1243
ccc9c027
L		 1244 /* We need to decide which NOP sequence to use for 32bit and
1245 64bit. When -mtune= is used:
4eed87de 1246
76bc74dc
L		 1247 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1248 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1249 2. For the rest, alt_patt will be used.
1250
1251 When -mtune= isn't used, alt_patt will be used if
22109423 1252 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1253 be used.
ccc9c027
L		 1254
1255 When -march= or .arch is used, we can't use anything beyond
1256 cpu_arch_isa_flags. */
1257
1258 if (flag_code == CODE_16BIT)
1259 {
ccc9c027 1260 if (count > 8)
33fef721 1261 {
76bc74dc
L		 1262 memcpy (fragP->fr_literal + fragP->fr_fix,
1263 jump_31, count);
1264 /* Adjust jump offset. */
1265 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1266 }
76bc74dc
L		 1267 else
1268 memcpy (fragP->fr_literal + fragP->fr_fix,
1269 f16_patt[count - 1], count);
252b5132 1270 }
33fef721 1271 else
ccc9c027 1272 {
bad6e36d 1273 const unsigned char *const *patt = NULL;
ccc9c027 1274
fbf3f584 1275 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1276 {
1277 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1278 switch (cpu_arch_tune)
1279 {
1280 case PROCESSOR_UNKNOWN:
1281 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1282 optimize with nops. */
1283 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1284 patt = alt_patt;
ccc9c027
L		 1285 else
1286 patt = f32_patt;
1287 break;
ccc9c027
L		 1288 case PROCESSOR_PENTIUM4:
1289 case PROCESSOR_NOCONA:
ef05d495 1290 case PROCESSOR_CORE:
76bc74dc 1291 case PROCESSOR_CORE2:
bd5295b2 1292 case PROCESSOR_COREI7:
3632d14b 1293 case PROCESSOR_L1OM:
7a9068fe 1294 case PROCESSOR_K1OM:
76bc74dc 1295 case PROCESSOR_GENERIC64:
ccc9c027
L		 1296 case PROCESSOR_K6:
1297 case PROCESSOR_ATHLON:
1298 case PROCESSOR_K8:
4eed87de 1299 case PROCESSOR_AMDFAM10:
8aedb9fe 1300 case PROCESSOR_BD:
029f3522 1301 case PROCESSOR_ZNVER:
7b458c12 1302 case PROCESSOR_BT:
80b8656c 1303 patt = alt_patt;
ccc9c027 1304 break;
76bc74dc 1305 case PROCESSOR_I386:
ccc9c027
L		 1306 case PROCESSOR_I486:
1307 case PROCESSOR_PENTIUM:
2dde1948 1308 case PROCESSOR_PENTIUMPRO:
81486035 1309 case PROCESSOR_IAMCU:
ccc9c027
L		 1310 case PROCESSOR_GENERIC32:
1311 patt = f32_patt;
1312 break;
4eed87de 1313 }
ccc9c027
L		 1314 }
1315 else
1316 {
fbf3f584 1317 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1318 {
1319 case PROCESSOR_UNKNOWN:
e6a14101 1320 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1321 PROCESSOR_UNKNOWN. */
1322 abort ();
1323 break;
1324
76bc74dc 1325 case PROCESSOR_I386:
ccc9c027
L		 1326 case PROCESSOR_I486:
1327 case PROCESSOR_PENTIUM:
81486035 1328 case PROCESSOR_IAMCU:
ccc9c027
L		 1329 case PROCESSOR_K6:
1330 case PROCESSOR_ATHLON:
1331 case PROCESSOR_K8:
4eed87de 1332 case PROCESSOR_AMDFAM10:
8aedb9fe 1333 case PROCESSOR_BD:
029f3522 1334 case PROCESSOR_ZNVER:
7b458c12 1335 case PROCESSOR_BT:
ccc9c027
L		 1336 case PROCESSOR_GENERIC32:
1337 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1338 with nops. */
1339 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1340 patt = alt_patt;
ccc9c027
L		 1341 else
1342 patt = f32_patt;
1343 break;
76bc74dc
L		 1344 case PROCESSOR_PENTIUMPRO:
1345 case PROCESSOR_PENTIUM4:
1346 case PROCESSOR_NOCONA:
1347 case PROCESSOR_CORE:
ef05d495 1348 case PROCESSOR_CORE2:
bd5295b2 1349 case PROCESSOR_COREI7:
3632d14b 1350 case PROCESSOR_L1OM:
7a9068fe 1351 case PROCESSOR_K1OM:
22109423 1352 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1353 patt = alt_patt;
ccc9c027
L		 1354 else
1355 patt = f32_patt;
1356 break;
1357 case PROCESSOR_GENERIC64:
80b8656c 1358 patt = alt_patt;
ccc9c027 1359 break;
4eed87de 1360 }
ccc9c027
L		 1361 }
1362
76bc74dc
L		 1363 if (patt == f32_patt)
1364 {
1365 /* If the padding is less than 15 bytes, we use the normal
1366 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1367 its offset. */
1368 int limit;
76ba9986 1369
711eedef
L		 1370 /* For 64bit, the limit is 3 bytes. */
1371 if (flag_code == CODE_64BIT
1372 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1373 limit = 3;
1374 else
1375 limit = 15;
1376 if (count < limit)
76bc74dc
L		 1377 memcpy (fragP->fr_literal + fragP->fr_fix,
1378 patt[count - 1], count);
1379 else
1380 {
1381 memcpy (fragP->fr_literal + fragP->fr_fix,
1382 jump_31, count);
1383 /* Adjust jump offset. */
1384 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1385 }
1386 }
1387 else
1388 {
80b8656c
L		 1389 /* Maximum length of an instruction is 10 byte. If the
1390 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1391 we have to break it into smaller pieces. */
1392 int padding = count;
80b8656c 1393 while (padding > 10)
76bc74dc 1394 {
80b8656c 1395 padding -= 10;
76bc74dc 1396 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1397 patt [9], 10);
76bc74dc
L		 1398 }
1399
1400 if (padding)
1401 memcpy (fragP->fr_literal + fragP->fr_fix,
1402 patt [padding - 1], padding);
1403 }
ccc9c027 1404 }
33fef721 1405 fragP->fr_var = count;
252b5132
RH		 1406}
1407
c6fb90c8 1408static INLINE int
0dfbf9d7 1409operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1410{
0dfbf9d7 1411 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1412 {
1413 case 3:
0dfbf9d7 1414 if (x->array[2])
c6fb90c8 1415 return 0;
1a0670f3 1416 /* Fall through. */
c6fb90c8 1417 case 2:
0dfbf9d7 1418 if (x->array[1])
c6fb90c8 1419 return 0;
1a0670f3 1420 /* Fall through. */
c6fb90c8 1421 case 1:
0dfbf9d7 1422 return !x->array[0];
c6fb90c8
L		 1423 default:
1424 abort ();
1425 }
40fb9820
L		 1426}
1427
c6fb90c8 1428static INLINE void
0dfbf9d7 1429operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1430{
0dfbf9d7 1431 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1432 {
1433 case 3:
0dfbf9d7 1434 x->array[2] = v;
1a0670f3 1435 /* Fall through. */
c6fb90c8 1436 case 2:
0dfbf9d7 1437 x->array[1] = v;
1a0670f3 1438 /* Fall through. */
c6fb90c8 1439 case 1:
0dfbf9d7 1440 x->array[0] = v;
1a0670f3 1441 /* Fall through. */
c6fb90c8
L		 1442 break;
1443 default:
1444 abort ();
1445 }
1446}
40fb9820 1447
c6fb90c8 1448static INLINE int
0dfbf9d7
L		 1449operand_type_equal (const union i386_operand_type *x,
1450 const union i386_operand_type *y)
c6fb90c8 1451{
0dfbf9d7 1452 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1453 {
1454 case 3:
0dfbf9d7 1455 if (x->array[2] != y->array[2])
c6fb90c8 1456 return 0;
1a0670f3 1457 /* Fall through. */
c6fb90c8 1458 case 2:
0dfbf9d7 1459 if (x->array[1] != y->array[1])
c6fb90c8 1460 return 0;
1a0670f3 1461 /* Fall through. */
c6fb90c8 1462 case 1:
0dfbf9d7 1463 return x->array[0] == y->array[0];
c6fb90c8
L		 1464 break;
1465 default:
1466 abort ();
1467 }
1468}
40fb9820 1469
0dfbf9d7
L		 1470static INLINE int
1471cpu_flags_all_zero (const union i386_cpu_flags *x)
1472{
1473 switch (ARRAY_SIZE(x->array))
1474 {
53467f57
IT		 1475 case 4:
1476 if (x->array[3])
1477 return 0;
1478 /* Fall through. */
0dfbf9d7
L		 1479 case 3:
1480 if (x->array[2])
1481 return 0;
1a0670f3 1482 /* Fall through. */
0dfbf9d7
L		 1483 case 2:
1484 if (x->array[1])
1485 return 0;
1a0670f3 1486 /* Fall through. */
0dfbf9d7
L		 1487 case 1:
1488 return !x->array[0];
1489 default:
1490 abort ();
1491 }
1492}
1493
0dfbf9d7
L		 1494static INLINE int
1495cpu_flags_equal (const union i386_cpu_flags *x,
1496 const union i386_cpu_flags *y)
1497{
1498 switch (ARRAY_SIZE(x->array))
1499 {
53467f57
IT		 1500 case 4:
1501 if (x->array[3] != y->array[3])
1502 return 0;
1503 /* Fall through. */
0dfbf9d7
L		 1504 case 3:
1505 if (x->array[2] != y->array[2])
1506 return 0;
1a0670f3 1507 /* Fall through. */
0dfbf9d7
L		 1508 case 2:
1509 if (x->array[1] != y->array[1])
1510 return 0;
1a0670f3 1511 /* Fall through. */
0dfbf9d7
L		 1512 case 1:
1513 return x->array[0] == y->array[0];
1514 break;
1515 default:
1516 abort ();
1517 }
1518}
c6fb90c8
L		 1519
1520static INLINE int
1521cpu_flags_check_cpu64 (i386_cpu_flags f)
1522{
1523 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1524 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1525}
1526
c6fb90c8
L		 1527static INLINE i386_cpu_flags
1528cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1529{
c6fb90c8
L		 1530 switch (ARRAY_SIZE (x.array))
1531 {
53467f57
IT		 1532 case 4:
1533 x.array [3] &= y.array [3];
1534 /* Fall through. */
c6fb90c8
L		 1535 case 3:
1536 x.array [2] &= y.array [2];
1a0670f3 1537 /* Fall through. */
c6fb90c8
L		 1538 case 2:
1539 x.array [1] &= y.array [1];
1a0670f3 1540 /* Fall through. */
c6fb90c8
L		 1541 case 1:
1542 x.array [0] &= y.array [0];
1543 break;
1544 default:
1545 abort ();
1546 }
1547 return x;
1548}
40fb9820 1549
c6fb90c8
L		 1550static INLINE i386_cpu_flags
1551cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1552{
c6fb90c8 1553 switch (ARRAY_SIZE (x.array))
40fb9820 1554 {
53467f57
IT		 1555 case 4:
1556 x.array [3] |= y.array [3];
1557 /* Fall through. */
c6fb90c8
L		 1558 case 3:
1559 x.array [2] |= y.array [2];
1a0670f3 1560 /* Fall through. */
c6fb90c8
L		 1561 case 2:
1562 x.array [1] |= y.array [1];
1a0670f3 1563 /* Fall through. */
c6fb90c8
L		 1564 case 1:
1565 x.array [0] |= y.array [0];
40fb9820
L		 1566 break;
1567 default:
1568 abort ();
1569 }
40fb9820
L		 1570 return x;
1571}
1572
309d3373
JB		 1573static INLINE i386_cpu_flags
1574cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1575{
1576 switch (ARRAY_SIZE (x.array))
1577 {
53467f57
IT		 1578 case 4:
1579 x.array [3] &= ~y.array [3];
1580 /* Fall through. */
309d3373
JB		 1581 case 3:
1582 x.array [2] &= ~y.array [2];
1a0670f3 1583 /* Fall through. */
309d3373
JB		 1584 case 2:
1585 x.array [1] &= ~y.array [1];
1a0670f3 1586 /* Fall through. */
309d3373
JB		 1587 case 1:
1588 x.array [0] &= ~y.array [0];
1589 break;
1590 default:
1591 abort ();
1592 }
1593 return x;
1594}
1595
c0f3af97
L		 1596#define CPU_FLAGS_ARCH_MATCH 0x1
1597#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1598#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1599#define CPU_FLAGS_PCLMUL_MATCH 0x8
1600#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1601
a5ff0eb2 1602#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1603 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1604 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1605#define CPU_FLAGS_PERFECT_MATCH \
1606 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1607
1608/* Return CPU flags match bits. */
3629bb00 1609
40fb9820 1610static int
d3ce72d0 1611cpu_flags_match (const insn_template *t)
40fb9820 1612{
c0f3af97
L		 1613 i386_cpu_flags x = t->cpu_flags;
1614 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1615
1616 x.bitfield.cpu64 = 0;
1617 x.bitfield.cpuno64 = 0;
1618
0dfbf9d7 1619 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1620 {
1621 /* This instruction is available on all archs. */
1622 match |= CPU_FLAGS_32BIT_MATCH;
1623 }
3629bb00
L		 1624 else
1625 {
c0f3af97 1626 /* This instruction is available only on some archs. */
3629bb00
L		 1627 i386_cpu_flags cpu = cpu_arch_flags;
1628
3629bb00 1629 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1630 if (!cpu_flags_all_zero (&cpu))
1631 {
a5ff0eb2
L		 1632 if (x.bitfield.cpuavx)
1633 {
ce2f5b3c 1634 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1635 if (cpu.bitfield.cpuavx)
1636 {
1637 /* Check SSE2AVX. */
1638 if (!t->opcode_modifier.sse2avx|| sse2avx)
1639 {
1640 match |= (CPU_FLAGS_ARCH_MATCH
1641 | CPU_FLAGS_AVX_MATCH);
1642 /* Check AES. */
1643 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1644 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1645 /* Check PCLMUL. */
1646 if (!x.bitfield.cpupclmul
1647 || cpu.bitfield.cpupclmul)
1648 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1649 }
1650 }
1651 else
1652 match |= CPU_FLAGS_ARCH_MATCH;
1653 }
73b090a9
L		 1654 else if (x.bitfield.cpuavx512vl)
1655 {
1656 /* Match AVX512VL. */
1657 if (cpu.bitfield.cpuavx512vl)
1658 {
1659 /* Need another match. */
1660 cpu.bitfield.cpuavx512vl = 0;
1661 if (!cpu_flags_all_zero (&cpu))
1662 match |= CPU_FLAGS_32BIT_MATCH;
1663 else
1664 match |= CPU_FLAGS_ARCH_MATCH;
1665 }
1666 else
1667 match |= CPU_FLAGS_ARCH_MATCH;
1668 }
a5ff0eb2 1669 else
c0f3af97
L		 1670 match |= CPU_FLAGS_32BIT_MATCH;
1671 }
3629bb00 1672 }
c0f3af97 1673 return match;
40fb9820
L		 1674}
1675
c6fb90c8
L		 1676static INLINE i386_operand_type
1677operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1678{
c6fb90c8
L		 1679 switch (ARRAY_SIZE (x.array))
1680 {
1681 case 3:
1682 x.array [2] &= y.array [2];
1a0670f3 1683 /* Fall through. */
c6fb90c8
L		 1684 case 2:
1685 x.array [1] &= y.array [1];
1a0670f3 1686 /* Fall through. */
c6fb90c8
L		 1687 case 1:
1688 x.array [0] &= y.array [0];
1689 break;
1690 default:
1691 abort ();
1692 }
1693 return x;
40fb9820
L		 1694}
1695
c6fb90c8
L		 1696static INLINE i386_operand_type
1697operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1698{
c6fb90c8 1699 switch (ARRAY_SIZE (x.array))
40fb9820 1700 {
c6fb90c8
L		 1701 case 3:
1702 x.array [2] |= y.array [2];
1a0670f3 1703 /* Fall through. */
c6fb90c8
L		 1704 case 2:
1705 x.array [1] |= y.array [1];
1a0670f3 1706 /* Fall through. */
c6fb90c8
L		 1707 case 1:
1708 x.array [0] |= y.array [0];
40fb9820
L		 1709 break;
1710 default:
1711 abort ();
1712 }
c6fb90c8
L		 1713 return x;
1714}
40fb9820 1715
c6fb90c8
L		 1716static INLINE i386_operand_type
1717operand_type_xor (i386_operand_type x, i386_operand_type y)
1718{
1719 switch (ARRAY_SIZE (x.array))
1720 {
1721 case 3:
1722 x.array [2] ^= y.array [2];
1a0670f3 1723 /* Fall through. */
c6fb90c8
L		 1724 case 2:
1725 x.array [1] ^= y.array [1];
1a0670f3 1726 /* Fall through. */
c6fb90c8
L		 1727 case 1:
1728 x.array [0] ^= y.array [0];
1729 break;
1730 default:
1731 abort ();
1732 }
40fb9820
L		 1733 return x;
1734}
1735
1736static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1737static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1738static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1739static const i386_operand_type inoutportreg
1740 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1741static const i386_operand_type reg16_inoutportreg
1742 = OPERAND_TYPE_REG16_INOUTPORTREG;
1743static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1744static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1745static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1746static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1747static const i386_operand_type anydisp
1748 = OPERAND_TYPE_ANYDISP;
40fb9820 1749static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
43234a1e 1750static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1751static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1752static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1753static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1754static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1755static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1756static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1757static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1758static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1759static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1760static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1761
1762enum operand_type
1763{
1764 reg,
40fb9820
L		 1765 imm,
1766 disp,
1767 anymem
1768};
1769
c6fb90c8 1770static INLINE int
40fb9820
L		 1771operand_type_check (i386_operand_type t, enum operand_type c)
1772{
1773 switch (c)
1774 {
1775 case reg:
dc821c5f 1776 return t.bitfield.reg;
40fb9820 1777
40fb9820
L		 1778 case imm:
1779 return (t.bitfield.imm8
1780 || t.bitfield.imm8s
1781 || t.bitfield.imm16
1782 || t.bitfield.imm32
1783 || t.bitfield.imm32s
1784 || t.bitfield.imm64);
1785
1786 case disp:
1787 return (t.bitfield.disp8
1788 || t.bitfield.disp16
1789 || t.bitfield.disp32
1790 || t.bitfield.disp32s
1791 || t.bitfield.disp64);
1792
1793 case anymem:
1794 return (t.bitfield.disp8
1795 || t.bitfield.disp16
1796 || t.bitfield.disp32
1797 || t.bitfield.disp32s
1798 || t.bitfield.disp64
1799 || t.bitfield.baseindex);
1800
1801 default:
1802 abort ();
1803 }
2cfe26b6
AM		 1804
1805 return 0;
40fb9820
L		 1806}
1807
ca0d63fe 1808/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
5c07affc
L		 1809 operand J for instruction template T. */
1810
1811static INLINE int
d3ce72d0 1812match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1813{
1814 return !((i.types[j].bitfield.byte
1815 && !t->operand_types[j].bitfield.byte)
1816 || (i.types[j].bitfield.word
1817 && !t->operand_types[j].bitfield.word)
1818 || (i.types[j].bitfield.dword
1819 && !t->operand_types[j].bitfield.dword)
1820 || (i.types[j].bitfield.qword
ca0d63fe
JB		 1821 && !t->operand_types[j].bitfield.qword)
1822 || (i.types[j].bitfield.tbyte
1823 && !t->operand_types[j].bitfield.tbyte));
5c07affc
L		 1824}
1825
1b54b8d7
JB		 1826/* Return 1 if there is no conflict in SIMD register on
1827 operand J for instruction template T. */
1828
1829static INLINE int
1830match_simd_size (const insn_template *t, unsigned int j)
1831{
1832 return !((i.types[j].bitfield.xmmword
1833 && !t->operand_types[j].bitfield.xmmword)
1834 || (i.types[j].bitfield.ymmword
1835 && !t->operand_types[j].bitfield.ymmword)
1836 || (i.types[j].bitfield.zmmword
1837 && !t->operand_types[j].bitfield.zmmword));
1838}
1839
5c07affc
L		 1840/* Return 1 if there is no conflict in any size on operand J for
1841 instruction template T. */
1842
1843static INLINE int
d3ce72d0 1844match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1845{
1846 return (match_reg_size (t, j)
1847 && !((i.types[j].bitfield.unspecified
af508cb9 1848 && !i.broadcast
5c07affc
L		 1849 && !t->operand_types[j].bitfield.unspecified)
1850 || (i.types[j].bitfield.fword
1851 && !t->operand_types[j].bitfield.fword)
1b54b8d7
JB		 1852 /* For scalar opcode templates to allow register and memory
1853 operands at the same time, some special casing is needed
1854 here. */
1855 || ((t->operand_types[j].bitfield.regsimd
1856 && !t->opcode_modifier.broadcast
1857 && (t->operand_types[j].bitfield.dword
1858 || t->operand_types[j].bitfield.qword))
1859 ? (i.types[j].bitfield.xmmword
1860 || i.types[j].bitfield.ymmword
1861 || i.types[j].bitfield.zmmword)
1862 : !match_simd_size(t, j))));
5c07affc
L		 1863}
1864
1865/* Return 1 if there is no size conflict on any operands for
1866 instruction template T. */
1867
1868static INLINE int
d3ce72d0 1869operand_size_match (const insn_template *t)
5c07affc
L		 1870{
1871 unsigned int j;
1872 int match = 1;
1873
1874 /* Don't check jump instructions. */
1875 if (t->opcode_modifier.jump
1876 || t->opcode_modifier.jumpbyte
1877 || t->opcode_modifier.jumpdword
1878 || t->opcode_modifier.jumpintersegment)
1879 return match;
1880
1881 /* Check memory and accumulator operand size. */
1882 for (j = 0; j < i.operands; j++)
1883 {
1b54b8d7
JB		 1884 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1885 && t->operand_types[j].bitfield.anysize)
5c07affc
L		 1886 continue;
1887
1b54b8d7 1888 if (t->operand_types[j].bitfield.reg
dc821c5f 1889 && !match_reg_size (t, j))
5c07affc
L		 1890 {
1891 match = 0;
1892 break;
1893 }
1894
1b54b8d7
JB		 1895 if (t->operand_types[j].bitfield.regsimd
1896 && !match_simd_size (t, j))
1897 {
1898 match = 0;
1899 break;
1900 }
1901
1902 if (t->operand_types[j].bitfield.acc
1903 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
1904 {
1905 match = 0;
1906 break;
1907 }
1908
5c07affc
L		 1909 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1910 {
1911 match = 0;
1912 break;
1913 }
1914 }
1915
891edac4 1916 if (match)
5c07affc 1917 return match;
891edac4
L		 1918 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1919 {
1920mismatch:
86e026a4 1921 i.error = operand_size_mismatch;
891edac4
L		 1922 return 0;
1923 }
5c07affc
L		 1924
1925 /* Check reverse. */
9c2799c2 1926 gas_assert (i.operands == 2);
5c07affc
L		 1927
1928 match = 1;
1929 for (j = 0; j < 2; j++)
1930 {
dc821c5f
JB		 1931 if ((t->operand_types[j].bitfield.reg
1932 || t->operand_types[j].bitfield.acc)
5c07affc 1933 && !match_reg_size (t, j ? 0 : 1))
891edac4 1934 goto mismatch;
5c07affc
L		 1935
1936 if (i.types[j].bitfield.mem
1937 && !match_mem_size (t, j ? 0 : 1))
891edac4 1938 goto mismatch;
5c07affc
L		 1939 }
1940
1941 return match;
1942}
1943
c6fb90c8 1944static INLINE int
40fb9820
L		 1945operand_type_match (i386_operand_type overlap,
1946 i386_operand_type given)
1947{
1948 i386_operand_type temp = overlap;
1949
1950 temp.bitfield.jumpabsolute = 0;
7d5e4556 1951 temp.bitfield.unspecified = 0;
5c07affc
L		 1952 temp.bitfield.byte = 0;
1953 temp.bitfield.word = 0;
1954 temp.bitfield.dword = 0;
1955 temp.bitfield.fword = 0;
1956 temp.bitfield.qword = 0;
1957 temp.bitfield.tbyte = 0;
1958 temp.bitfield.xmmword = 0;
c0f3af97 1959 temp.bitfield.ymmword = 0;
43234a1e 1960 temp.bitfield.zmmword = 0;
0dfbf9d7 1961 if (operand_type_all_zero (&temp))
891edac4 1962 goto mismatch;
40fb9820 1963
891edac4
L		 1964 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1965 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1966 return 1;
1967
1968mismatch:
a65babc9 1969 i.error = operand_type_mismatch;
891edac4 1970 return 0;
40fb9820
L		 1971}
1972
7d5e4556 1973/* If given types g0 and g1 are registers they must be of the same type
10c17abd
JB		 1974 unless the expected operand type register overlap is null.
1975 Memory operand size of certain SIMD instructions is also being checked
1976 here. */
40fb9820 1977
c6fb90c8 1978static INLINE int
dc821c5f 1979operand_type_register_match (i386_operand_type g0,
40fb9820 1980 i386_operand_type t0,
40fb9820
L		 1981 i386_operand_type g1,
1982 i386_operand_type t1)
1983{
10c17abd
JB		 1984 if (!g0.bitfield.reg
1985 && !g0.bitfield.regsimd
1986 && (!operand_type_check (g0, anymem)
1987 || g0.bitfield.unspecified
1988 || !t0.bitfield.regsimd))
40fb9820
L		 1989 return 1;
1990
10c17abd
JB		 1991 if (!g1.bitfield.reg
1992 && !g1.bitfield.regsimd
1993 && (!operand_type_check (g1, anymem)
1994 || g1.bitfield.unspecified
1995 || !t1.bitfield.regsimd))
40fb9820
L		 1996 return 1;
1997
dc821c5f
JB		 1998 if (g0.bitfield.byte == g1.bitfield.byte
1999 && g0.bitfield.word == g1.bitfield.word
2000 && g0.bitfield.dword == g1.bitfield.dword
10c17abd
JB		 2001 && g0.bitfield.qword == g1.bitfield.qword
2002 && g0.bitfield.xmmword == g1.bitfield.xmmword
2003 && g0.bitfield.ymmword == g1.bitfield.ymmword
2004 && g0.bitfield.zmmword == g1.bitfield.zmmword)
40fb9820
L		 2005 return 1;
2006
dc821c5f
JB		 2007 if (!(t0.bitfield.byte & t1.bitfield.byte)
2008 && !(t0.bitfield.word & t1.bitfield.word)
2009 && !(t0.bitfield.dword & t1.bitfield.dword)
10c17abd
JB		 2010 && !(t0.bitfield.qword & t1.bitfield.qword)
2011 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2012 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2013 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
891edac4
L		 2014 return 1;
2015
a65babc9 2016 i.error = register_type_mismatch;
891edac4
L		 2017
2018 return 0;
40fb9820
L		 2019}
2020
4c692bc7
JB		 2021static INLINE unsigned int
2022register_number (const reg_entry *r)
2023{
2024 unsigned int nr = r->reg_num;
2025
2026 if (r->reg_flags & RegRex)
2027 nr += 8;
2028
200cbe0f
L		 2029 if (r->reg_flags & RegVRex)
2030 nr += 16;
2031
4c692bc7
JB		 2032 return nr;
2033}
2034
252b5132 2035static INLINE unsigned int
40fb9820 2036mode_from_disp_size (i386_operand_type t)
252b5132 2037{
b5014f7a 2038 if (t.bitfield.disp8)
40fb9820
L		 2039 return 1;
2040 else if (t.bitfield.disp16
2041 || t.bitfield.disp32
2042 || t.bitfield.disp32s)
2043 return 2;
2044 else
2045 return 0;
252b5132
RH		 2046}
2047
2048static INLINE int
65879393 2049fits_in_signed_byte (addressT num)
252b5132 2050{
65879393 2051 return num + 0x80 <= 0xff;
47926f60 2052}
252b5132
RH		 2053
2054static INLINE int
65879393 2055fits_in_unsigned_byte (addressT num)
252b5132 2056{
65879393 2057 return num <= 0xff;
47926f60 2058}
252b5132
RH		 2059
2060static INLINE int
65879393 2061fits_in_unsigned_word (addressT num)
252b5132 2062{
65879393 2063 return num <= 0xffff;
47926f60 2064}
252b5132
RH		 2065
2066static INLINE int
65879393 2067fits_in_signed_word (addressT num)
252b5132 2068{
65879393 2069 return num + 0x8000 <= 0xffff;
47926f60 2070}
2a962e6d 2071
3e73aa7c 2072static INLINE int
65879393 2073fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2074{
2075#ifndef BFD64
2076 return 1;
2077#else
65879393 2078 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 2079#endif
2080} /* fits_in_signed_long() */
2a962e6d 2081
3e73aa7c 2082static INLINE int
65879393 2083fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2084{
2085#ifndef BFD64
2086 return 1;
2087#else
65879393 2088 return num <= 0xffffffff;
3e73aa7c
JH		 2089#endif
2090} /* fits_in_unsigned_long() */
252b5132 2091
43234a1e 2092static INLINE int
b5014f7a 2093fits_in_disp8 (offsetT num)
43234a1e
L		 2094{
2095 int shift = i.memshift;
2096 unsigned int mask;
2097
2098 if (shift == -1)
2099 abort ();
2100
2101 mask = (1 << shift) - 1;
2102
2103 /* Return 0 if NUM isn't properly aligned. */
2104 if ((num & mask))
2105 return 0;
2106
2107 /* Check if NUM will fit in 8bit after shift. */
2108 return fits_in_signed_byte (num >> shift);
2109}
2110
a683cc34
SP		 2111static INLINE int
2112fits_in_imm4 (offsetT num)
2113{
2114 return (num & 0xf) == num;
2115}
2116
40fb9820 2117static i386_operand_type
e3bb37b5 2118smallest_imm_type (offsetT num)
252b5132 2119{
40fb9820 2120 i386_operand_type t;
7ab9ffdd 2121
0dfbf9d7 2122 operand_type_set (&t, 0);
40fb9820
L		 2123 t.bitfield.imm64 = 1;
2124
2125 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2126 {
2127 /* This code is disabled on the 486 because all the Imm1 forms
2128 in the opcode table are slower on the i486. They're the
2129 versions with the implicitly specified single-position
2130 displacement, which has another syntax if you really want to
2131 use that form. */
40fb9820
L		 2132 t.bitfield.imm1 = 1;
2133 t.bitfield.imm8 = 1;
2134 t.bitfield.imm8s = 1;
2135 t.bitfield.imm16 = 1;
2136 t.bitfield.imm32 = 1;
2137 t.bitfield.imm32s = 1;
2138 }
2139 else if (fits_in_signed_byte (num))
2140 {
2141 t.bitfield.imm8 = 1;
2142 t.bitfield.imm8s = 1;
2143 t.bitfield.imm16 = 1;
2144 t.bitfield.imm32 = 1;
2145 t.bitfield.imm32s = 1;
2146 }
2147 else if (fits_in_unsigned_byte (num))
2148 {
2149 t.bitfield.imm8 = 1;
2150 t.bitfield.imm16 = 1;
2151 t.bitfield.imm32 = 1;
2152 t.bitfield.imm32s = 1;
2153 }
2154 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2155 {
2156 t.bitfield.imm16 = 1;
2157 t.bitfield.imm32 = 1;
2158 t.bitfield.imm32s = 1;
2159 }
2160 else if (fits_in_signed_long (num))
2161 {
2162 t.bitfield.imm32 = 1;
2163 t.bitfield.imm32s = 1;
2164 }
2165 else if (fits_in_unsigned_long (num))
2166 t.bitfield.imm32 = 1;
2167
2168 return t;
47926f60 2169}
252b5132 2170
847f7ad4 2171static offsetT
e3bb37b5 2172offset_in_range (offsetT val, int size)
847f7ad4 2173{
508866be 2174 addressT mask;
ba2adb93 2175
847f7ad4
AM		 2176 switch (size)
2177 {
508866be
L		 2178 case 1: mask = ((addressT) 1 << 8) - 1; break;
2179 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2180 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2181#ifdef BFD64
2182 case 8: mask = ((addressT) 2 << 63) - 1; break;
2183#endif
47926f60 2184 default: abort ();
847f7ad4
AM		 2185 }
2186
9de868bf
L		 2187#ifdef BFD64
2188 /* If BFD64, sign extend val for 32bit address mode. */
2189 if (flag_code != CODE_64BIT
2190 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2191 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2192 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2193#endif
ba2adb93 2194
47926f60 2195 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2196 {
2197 char buf1[40], buf2[40];
2198
2199 sprint_value (buf1, val);
2200 sprint_value (buf2, val & mask);
2201 as_warn (_("%s shortened to %s"), buf1, buf2);
2202 }
2203 return val & mask;
2204}
2205
c32fa91d
L		 2206enum PREFIX_GROUP
2207{
2208 PREFIX_EXIST = 0,
2209 PREFIX_LOCK,
2210 PREFIX_REP,
04ef582a 2211 PREFIX_DS,
c32fa91d
L		 2212 PREFIX_OTHER
2213};
2214
2215/* Returns
2216 a. PREFIX_EXIST if attempting to add a prefix where one from the
2217 same class already exists.
2218 b. PREFIX_LOCK if lock prefix is added.
2219 c. PREFIX_REP if rep/repne prefix is added.
04ef582a
L		 2220 d. PREFIX_DS if ds prefix is added.
2221 e. PREFIX_OTHER if other prefix is added.
c32fa91d
L		 2222 */
2223
2224static enum PREFIX_GROUP
e3bb37b5 2225add_prefix (unsigned int prefix)
252b5132 2226{
c32fa91d 2227 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2228 unsigned int q;
252b5132 2229
29b0f896
AM		 2230 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2231 && flag_code == CODE_64BIT)
b1905489 2232 {
161a04f6
L		 2233 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2234 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2235 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2236 ret = PREFIX_EXIST;
b1905489
JB		 2237 q = REX_PREFIX;
2238 }
3e73aa7c 2239 else
b1905489
JB		 2240 {
2241 switch (prefix)
2242 {
2243 default:
2244 abort ();
2245
b1905489 2246 case DS_PREFIX_OPCODE:
04ef582a
L		 2247 ret = PREFIX_DS;
2248 /* Fall through. */
2249 case CS_PREFIX_OPCODE:
b1905489
JB		 2250 case ES_PREFIX_OPCODE:
2251 case FS_PREFIX_OPCODE:
2252 case GS_PREFIX_OPCODE:
2253 case SS_PREFIX_OPCODE:
2254 q = SEG_PREFIX;
2255 break;
2256
2257 case REPNE_PREFIX_OPCODE:
2258 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2259 q = REP_PREFIX;
2260 ret = PREFIX_REP;
2261 break;
2262
b1905489 2263 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2264 q = LOCK_PREFIX;
2265 ret = PREFIX_LOCK;
b1905489
JB		 2266 break;
2267
2268 case FWAIT_OPCODE:
2269 q = WAIT_PREFIX;
2270 break;
2271
2272 case ADDR_PREFIX_OPCODE:
2273 q = ADDR_PREFIX;
2274 break;
2275
2276 case DATA_PREFIX_OPCODE:
2277 q = DATA_PREFIX;
2278 break;
2279 }
2280 if (i.prefix[q] != 0)
c32fa91d 2281 ret = PREFIX_EXIST;
b1905489 2282 }
252b5132 2283
b1905489 2284 if (ret)
252b5132 2285 {
b1905489
JB		 2286 if (!i.prefix[q])
2287 ++i.prefixes;
2288 i.prefix[q] |= prefix;
252b5132 2289 }
b1905489
JB		 2290 else
2291 as_bad (_("same type of prefix used twice"));
252b5132 2292
252b5132
RH		 2293 return ret;
2294}
2295
2296static void
78f12dd3 2297update_code_flag (int value, int check)
eecb386c 2298{
78f12dd3
L		 2299 PRINTF_LIKE ((*as_error));
2300
1e9cc1c2 2301 flag_code = (enum flag_code) value;
40fb9820
L		 2302 if (flag_code == CODE_64BIT)
2303 {
2304 cpu_arch_flags.bitfield.cpu64 = 1;
2305 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2306 }
2307 else
2308 {
2309 cpu_arch_flags.bitfield.cpu64 = 0;
2310 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2311 }
2312 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2313 {
78f12dd3
L		 2314 if (check)
2315 as_error = as_fatal;
2316 else
2317 as_error = as_bad;
2318 (*as_error) (_("64bit mode not supported on `%s'."),
2319 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2320 }
40fb9820 2321 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2322 {
78f12dd3
L		 2323 if (check)
2324 as_error = as_fatal;
2325 else
2326 as_error = as_bad;
2327 (*as_error) (_("32bit mode not supported on `%s'."),
2328 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2329 }
eecb386c
AM		 2330 stackop_size = '\0';
2331}
2332
78f12dd3
L		 2333static void
2334set_code_flag (int value)
2335{
2336 update_code_flag (value, 0);
2337}
2338
eecb386c 2339static void
e3bb37b5 2340set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2341{
1e9cc1c2 2342 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2343 if (flag_code != CODE_16BIT)
2344 abort ();
2345 cpu_arch_flags.bitfield.cpu64 = 0;
2346 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2347 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2348}
2349
2350static void
e3bb37b5 2351set_intel_syntax (int syntax_flag)
252b5132
RH		 2352{
2353 /* Find out if register prefixing is specified. */
2354 int ask_naked_reg = 0;
2355
2356 SKIP_WHITESPACE ();
29b0f896 2357 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2358 {
d02603dc
NC		 2359 char *string;
2360 int e = get_symbol_name (&string);
252b5132 2361
47926f60 2362 if (strcmp (string, "prefix") == 0)
252b5132 2363 ask_naked_reg = 1;
47926f60 2364 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2365 ask_naked_reg = -1;
2366 else
d0b47220 2367 as_bad (_("bad argument to syntax directive."));
d02603dc 2368 (void) restore_line_pointer (e);
252b5132
RH		 2369 }
2370 demand_empty_rest_of_line ();
c3332e24 2371
252b5132
RH		 2372 intel_syntax = syntax_flag;
2373
2374 if (ask_naked_reg == 0)
f86103b7
AM		 2375 allow_naked_reg = (intel_syntax
2376 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2377 else
2378 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2379
ee86248c 2380 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2381
e4a3b5a4 2382 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2383 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2384 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2385}
2386
1efbbeb4
L		 2387static void
2388set_intel_mnemonic (int mnemonic_flag)
2389{
e1d4d893 2390 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2391}
2392
db51cc60
L		 2393static void
2394set_allow_index_reg (int flag)
2395{
2396 allow_index_reg = flag;
2397}
2398
cb19c032 2399static void
7bab8ab5 2400set_check (int what)
cb19c032 2401{
7bab8ab5
JB		 2402 enum check_kind *kind;
2403 const char *str;
2404
2405 if (what)
2406 {
2407 kind = &operand_check;
2408 str = "operand";
2409 }
2410 else
2411 {
2412 kind = &sse_check;
2413 str = "sse";
2414 }
2415
cb19c032
L		 2416 SKIP_WHITESPACE ();
2417
2418 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2419 {
d02603dc
NC		 2420 char *string;
2421 int e = get_symbol_name (&string);
cb19c032
L		 2422
2423 if (strcmp (string, "none") == 0)
7bab8ab5 2424 *kind = check_none;
cb19c032 2425 else if (strcmp (string, "warning") == 0)
7bab8ab5 2426 *kind = check_warning;
cb19c032 2427 else if (strcmp (string, "error") == 0)
7bab8ab5 2428 *kind = check_error;
cb19c032 2429 else
7bab8ab5 2430 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2431 (void) restore_line_pointer (e);
cb19c032
L		 2432 }
2433 else
7bab8ab5 2434 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2435
2436 demand_empty_rest_of_line ();
2437}
2438
8a9036a4
L		 2439static void
2440check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2441 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2442{
2443#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2444 static const char *arch;
2445
2446 /* Intel LIOM is only supported on ELF. */
2447 if (!IS_ELF)
2448 return;
2449
2450 if (!arch)
2451 {
2452 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2453 use default_arch. */
2454 arch = cpu_arch_name;
2455 if (!arch)
2456 arch = default_arch;
2457 }
2458
81486035
L		 2459 /* If we are targeting Intel MCU, we must enable it. */
2460 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2461 || new_flag.bitfield.cpuiamcu)
2462 return;
2463
3632d14b 2464 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2465 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2466 || new_flag.bitfield.cpul1om)
8a9036a4 2467 return;
76ba9986 2468
7a9068fe
L		 2469 /* If we are targeting Intel K1OM, we must enable it. */
2470 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2471 || new_flag.bitfield.cpuk1om)
2472 return;
2473
8a9036a4
L		 2474 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2475#endif
2476}
2477
e413e4e9 2478static void
e3bb37b5 2479set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2480{
47926f60 2481 SKIP_WHITESPACE ();
e413e4e9 2482
29b0f896 2483 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2484 {
d02603dc
NC		 2485 char *string;
2486 int e = get_symbol_name (&string);
91d6fa6a 2487 unsigned int j;
40fb9820 2488 i386_cpu_flags flags;
e413e4e9 2489
91d6fa6a 2490 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2491 {
91d6fa6a 2492 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2493 {
91d6fa6a 2494 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2495
5c6af06e
JB		 2496 if (*string != '.')
2497 {
91d6fa6a 2498 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2499 cpu_sub_arch_name = NULL;
91d6fa6a 2500 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2501 if (flag_code == CODE_64BIT)
2502 {
2503 cpu_arch_flags.bitfield.cpu64 = 1;
2504 cpu_arch_flags.bitfield.cpuno64 = 0;
2505 }
2506 else
2507 {
2508 cpu_arch_flags.bitfield.cpu64 = 0;
2509 cpu_arch_flags.bitfield.cpuno64 = 1;
2510 }
91d6fa6a
NC		 2511 cpu_arch_isa = cpu_arch[j].type;
2512 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2513 if (!cpu_arch_tune_set)
2514 {
2515 cpu_arch_tune = cpu_arch_isa;
2516 cpu_arch_tune_flags = cpu_arch_isa_flags;
2517 }
5c6af06e
JB		 2518 break;
2519 }
40fb9820 2520
293f5f65
L		 2521 flags = cpu_flags_or (cpu_arch_flags,
2522 cpu_arch[j].flags);
81486035 2523
5b64d091 2524 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2525 {
6305a203
L		 2526 if (cpu_sub_arch_name)
2527 {
2528 char *name = cpu_sub_arch_name;
2529 cpu_sub_arch_name = concat (name,
91d6fa6a 2530 cpu_arch[j].name,
1bf57e9f 2531 (const char *) NULL);
6305a203
L		 2532 free (name);
2533 }
2534 else
91d6fa6a 2535 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2536 cpu_arch_flags = flags;
a586129e 2537 cpu_arch_isa_flags = flags;
5c6af06e 2538 }
d02603dc 2539 (void) restore_line_pointer (e);
5c6af06e
JB		 2540 demand_empty_rest_of_line ();
2541 return;
e413e4e9
AM		 2542 }
2543 }
293f5f65
L		 2544
2545 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2546 {
33eaf5de 2547 /* Disable an ISA extension. */
293f5f65
L		 2548 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2549 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2550 {
2551 flags = cpu_flags_and_not (cpu_arch_flags,
2552 cpu_noarch[j].flags);
2553 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2554 {
2555 if (cpu_sub_arch_name)
2556 {
2557 char *name = cpu_sub_arch_name;
2558 cpu_sub_arch_name = concat (name, string,
2559 (const char *) NULL);
2560 free (name);
2561 }
2562 else
2563 cpu_sub_arch_name = xstrdup (string);
2564 cpu_arch_flags = flags;
2565 cpu_arch_isa_flags = flags;
2566 }
2567 (void) restore_line_pointer (e);
2568 demand_empty_rest_of_line ();
2569 return;
2570 }
2571
2572 j = ARRAY_SIZE (cpu_arch);
2573 }
2574
91d6fa6a 2575 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2576 as_bad (_("no such architecture: `%s'"), string);
2577
2578 *input_line_pointer = e;
2579 }
2580 else
2581 as_bad (_("missing cpu architecture"));
2582
fddf5b5b
AM		 2583 no_cond_jump_promotion = 0;
2584 if (*input_line_pointer == ','
29b0f896 2585 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2586 {
d02603dc
NC		 2587 char *string;
2588 char e;
2589
2590 ++input_line_pointer;
2591 e = get_symbol_name (&string);
fddf5b5b
AM		 2592
2593 if (strcmp (string, "nojumps") == 0)
2594 no_cond_jump_promotion = 1;
2595 else if (strcmp (string, "jumps") == 0)
2596 ;
2597 else
2598 as_bad (_("no such architecture modifier: `%s'"), string);
2599
d02603dc 2600 (void) restore_line_pointer (e);
fddf5b5b
AM		 2601 }
2602
e413e4e9
AM		 2603 demand_empty_rest_of_line ();
2604}
2605
8a9036a4
L		 2606enum bfd_architecture
2607i386_arch (void)
2608{
3632d14b 2609 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2610 {
2611 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2612 || flag_code != CODE_64BIT)
2613 as_fatal (_("Intel L1OM is 64bit ELF only"));
2614 return bfd_arch_l1om;
2615 }
7a9068fe
L		 2616 else if (cpu_arch_isa == PROCESSOR_K1OM)
2617 {
2618 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2619 || flag_code != CODE_64BIT)
2620 as_fatal (_("Intel K1OM is 64bit ELF only"));
2621 return bfd_arch_k1om;
2622 }
81486035
L		 2623 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2624 {
2625 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2626 || flag_code == CODE_64BIT)
2627 as_fatal (_("Intel MCU is 32bit ELF only"));
2628 return bfd_arch_iamcu;
2629 }
8a9036a4
L		 2630 else
2631 return bfd_arch_i386;
2632}
2633
b9d79e03 2634unsigned long
7016a5d5 2635i386_mach (void)
b9d79e03 2636{
351f65ca 2637 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2638 {
3632d14b 2639 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2640 {
351f65ca
L		 2641 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2642 || default_arch[6] != '\0')
8a9036a4
L		 2643 as_fatal (_("Intel L1OM is 64bit ELF only"));
2644 return bfd_mach_l1om;
2645 }
7a9068fe
L		 2646 else if (cpu_arch_isa == PROCESSOR_K1OM)
2647 {
2648 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2649 || default_arch[6] != '\0')
2650 as_fatal (_("Intel K1OM is 64bit ELF only"));
2651 return bfd_mach_k1om;
2652 }
351f65ca 2653 else if (default_arch[6] == '\0')
8a9036a4 2654 return bfd_mach_x86_64;
351f65ca
L		 2655 else
2656 return bfd_mach_x64_32;
8a9036a4 2657 }
5197d474
L		 2658 else if (!strcmp (default_arch, "i386")
2659 || !strcmp (default_arch, "iamcu"))
81486035
L		 2660 {
2661 if (cpu_arch_isa == PROCESSOR_IAMCU)
2662 {
2663 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2664 as_fatal (_("Intel MCU is 32bit ELF only"));
2665 return bfd_mach_i386_iamcu;
2666 }
2667 else
2668 return bfd_mach_i386_i386;
2669 }
b9d79e03 2670 else
2b5d6a91 2671 as_fatal (_("unknown architecture"));
b9d79e03 2672}
b9d79e03 2673\f
252b5132 2674void
7016a5d5 2675md_begin (void)
252b5132
RH		 2676{
2677 const char *hash_err;
2678
86fa6981
L		 2679 /* Support pseudo prefixes like {disp32}. */
2680 lex_type ['{'] = LEX_BEGIN_NAME;
2681
47926f60 2682 /* Initialize op_hash hash table. */
252b5132
RH		 2683 op_hash = hash_new ();
2684
2685 {
d3ce72d0 2686 const insn_template *optab;
29b0f896 2687 templates *core_optab;
252b5132 2688
47926f60
KH		 2689 /* Setup for loop. */
2690 optab = i386_optab;
add39d23 2691 core_optab = XNEW (templates);
252b5132
RH		 2692 core_optab->start = optab;
2693
2694 while (1)
2695 {
2696 ++optab;
2697 if (optab->name == NULL
2698 || strcmp (optab->name, (optab - 1)->name) != 0)
2699 {
2700 /* different name --> ship out current template list;
47926f60 2701 add to hash table; & begin anew. */
252b5132
RH		 2702 core_optab->end = optab;
2703 hash_err = hash_insert (op_hash,
2704 (optab - 1)->name,
5a49b8ac 2705 (void *) core_optab);
252b5132
RH		 2706 if (hash_err)
2707 {
b37df7c4 2708 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2709 (optab - 1)->name,
2710 hash_err);
2711 }
2712 if (optab->name == NULL)
2713 break;
add39d23 2714 core_optab = XNEW (templates);
252b5132
RH		 2715 core_optab->start = optab;
2716 }
2717 }
2718 }
2719
47926f60 2720 /* Initialize reg_hash hash table. */
252b5132
RH		 2721 reg_hash = hash_new ();
2722 {
29b0f896 2723 const reg_entry *regtab;
c3fe08fa 2724 unsigned int regtab_size = i386_regtab_size;
252b5132 2725
c3fe08fa 2726 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2727 {
5a49b8ac 2728 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2729 if (hash_err)
b37df7c4 2730 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2731 regtab->reg_name,
2732 hash_err);
252b5132
RH		 2733 }
2734 }
2735
47926f60 2736 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2737 {
29b0f896
AM		 2738 int c;
2739 char *p;
252b5132
RH		 2740
2741 for (c = 0; c < 256; c++)
2742 {
3882b010 2743 if (ISDIGIT (c))
252b5132
RH		 2744 {
2745 digit_chars[c] = c;
2746 mnemonic_chars[c] = c;
2747 register_chars[c] = c;
2748 operand_chars[c] = c;
2749 }
3882b010 2750 else if (ISLOWER (c))
252b5132
RH		 2751 {
2752 mnemonic_chars[c] = c;
2753 register_chars[c] = c;
2754 operand_chars[c] = c;
2755 }
3882b010 2756 else if (ISUPPER (c))
252b5132 2757 {
3882b010 2758 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2759 register_chars[c] = mnemonic_chars[c];
2760 operand_chars[c] = c;
2761 }
43234a1e 2762 else if (c == '{' || c == '}')
86fa6981
L		 2763 {
2764 mnemonic_chars[c] = c;
2765 operand_chars[c] = c;
2766 }
252b5132 2767
3882b010 2768 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2769 identifier_chars[c] = c;
2770 else if (c >= 128)
2771 {
2772 identifier_chars[c] = c;
2773 operand_chars[c] = c;
2774 }
2775 }
2776
2777#ifdef LEX_AT
2778 identifier_chars['@'] = '@';
32137342
NC		 2779#endif
2780#ifdef LEX_QM
2781 identifier_chars['?'] = '?';
2782 operand_chars['?'] = '?';
252b5132 2783#endif
252b5132 2784 digit_chars['-'] = '-';
c0f3af97 2785 mnemonic_chars['_'] = '_';
791fe849 2786 mnemonic_chars['-'] = '-';
0003779b 2787 mnemonic_chars['.'] = '.';
252b5132
RH		 2788 identifier_chars['_'] = '_';
2789 identifier_chars['.'] = '.';
2790
2791 for (p = operand_special_chars; *p != '\0'; p++)
2792 operand_chars[(unsigned char) *p] = *p;
2793 }
2794
a4447b93
RH		 2795 if (flag_code == CODE_64BIT)
2796 {
ca19b261
KT		 2797#if defined (OBJ_COFF) && defined (TE_PE)
2798 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2799 ? 32 : 16);
2800#else
a4447b93 2801 x86_dwarf2_return_column = 16;
ca19b261 2802#endif
61ff971f 2803 x86_cie_data_alignment = -8;
a4447b93
RH		 2804 }
2805 else
2806 {
2807 x86_dwarf2_return_column = 8;
2808 x86_cie_data_alignment = -4;
2809 }
252b5132
RH		 2810}
2811
2812void
e3bb37b5 2813i386_print_statistics (FILE *file)
252b5132
RH		 2814{
2815 hash_print_statistics (file, "i386 opcode", op_hash);
2816 hash_print_statistics (file, "i386 register", reg_hash);
2817}
2818\f
252b5132
RH		 2819#ifdef DEBUG386
2820
ce8a8b2f 2821/* Debugging routines for md_assemble. */
d3ce72d0 2822static void pte (insn_template *);
40fb9820 2823static void pt (i386_operand_type);
e3bb37b5
L		 2824static void pe (expressionS *);
2825static void ps (symbolS *);
252b5132
RH		 2826
2827static void
e3bb37b5 2828pi (char *line, i386_insn *x)
252b5132 2829{
09137c09 2830 unsigned int j;
252b5132
RH		 2831
2832 fprintf (stdout, "%s: template ", line);
2833 pte (&x->tm);
09f131f2
JH		 2834 fprintf (stdout, " address: base %s index %s scale %x\n",
2835 x->base_reg ? x->base_reg->reg_name : "none",
2836 x->index_reg ? x->index_reg->reg_name : "none",
2837 x->log2_scale_factor);
2838 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2839 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2840 fprintf (stdout, " sib: base %x index %x scale %x\n",
2841 x->sib.base, x->sib.index, x->sib.scale);
2842 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2843 (x->rex & REX_W) != 0,
2844 (x->rex & REX_R) != 0,
2845 (x->rex & REX_X) != 0,
2846 (x->rex & REX_B) != 0);
09137c09 2847 for (j = 0; j < x->operands; j++)
252b5132 2848 {
09137c09
SP		 2849 fprintf (stdout, " #%d: ", j + 1);
2850 pt (x->types[j]);
252b5132 2851 fprintf (stdout, "\n");
dc821c5f 2852 if (x->types[j].bitfield.reg
09137c09 2853 || x->types[j].bitfield.regmmx
1b54b8d7 2854 || x->types[j].bitfield.regsimd
09137c09
SP		 2855 || x->types[j].bitfield.sreg2
2856 || x->types[j].bitfield.sreg3
2857 || x->types[j].bitfield.control
2858 || x->types[j].bitfield.debug
2859 || x->types[j].bitfield.test)
2860 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2861 if (operand_type_check (x->types[j], imm))
2862 pe (x->op[j].imms);
2863 if (operand_type_check (x->types[j], disp))
2864 pe (x->op[j].disps);
252b5132
RH		 2865 }
2866}
2867
2868static void
d3ce72d0 2869pte (insn_template *t)
252b5132 2870{
09137c09 2871 unsigned int j;
252b5132 2872 fprintf (stdout, " %d operands ", t->operands);
47926f60 2873 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2874 if (t->extension_opcode != None)
2875 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2876 if (t->opcode_modifier.d)
252b5132 2877 fprintf (stdout, "D");
40fb9820 2878 if (t->opcode_modifier.w)
252b5132
RH		 2879 fprintf (stdout, "W");
2880 fprintf (stdout, "\n");
09137c09 2881 for (j = 0; j < t->operands; j++)
252b5132 2882 {
09137c09
SP		 2883 fprintf (stdout, " #%d type ", j + 1);
2884 pt (t->operand_types[j]);
252b5132
RH		 2885 fprintf (stdout, "\n");
2886 }
2887}
2888
2889static void
e3bb37b5 2890pe (expressionS *e)
252b5132 2891{
24eab124 2892 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2893 fprintf (stdout, " add_number %ld (%lx)\n",
2894 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2895 if (e->X_add_symbol)
2896 {
2897 fprintf (stdout, " add_symbol ");
2898 ps (e->X_add_symbol);
2899 fprintf (stdout, "\n");
2900 }
2901 if (e->X_op_symbol)
2902 {
2903 fprintf (stdout, " op_symbol ");
2904 ps (e->X_op_symbol);
2905 fprintf (stdout, "\n");
2906 }
2907}
2908
2909static void
e3bb37b5 2910ps (symbolS *s)
252b5132
RH		 2911{
2912 fprintf (stdout, "%s type %s%s",
2913 S_GET_NAME (s),
2914 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2915 segment_name (S_GET_SEGMENT (s)));
2916}
2917
7b81dfbb 2918static struct type_name
252b5132 2919 {
40fb9820
L		 2920 i386_operand_type mask;
2921 const char *name;
252b5132 2922 }
7b81dfbb 2923const type_names[] =
252b5132 2924{
40fb9820
L		 2925 { OPERAND_TYPE_REG8, "r8" },
2926 { OPERAND_TYPE_REG16, "r16" },
2927 { OPERAND_TYPE_REG32, "r32" },
2928 { OPERAND_TYPE_REG64, "r64" },
2929 { OPERAND_TYPE_IMM8, "i8" },
2930 { OPERAND_TYPE_IMM8, "i8s" },
2931 { OPERAND_TYPE_IMM16, "i16" },
2932 { OPERAND_TYPE_IMM32, "i32" },
2933 { OPERAND_TYPE_IMM32S, "i32s" },
2934 { OPERAND_TYPE_IMM64, "i64" },
2935 { OPERAND_TYPE_IMM1, "i1" },
2936 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2937 { OPERAND_TYPE_DISP8, "d8" },
2938 { OPERAND_TYPE_DISP16, "d16" },
2939 { OPERAND_TYPE_DISP32, "d32" },
2940 { OPERAND_TYPE_DISP32S, "d32s" },
2941 { OPERAND_TYPE_DISP64, "d64" },
2942 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2943 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2944 { OPERAND_TYPE_CONTROL, "control reg" },
2945 { OPERAND_TYPE_TEST, "test reg" },
2946 { OPERAND_TYPE_DEBUG, "debug reg" },
2947 { OPERAND_TYPE_FLOATREG, "FReg" },
2948 { OPERAND_TYPE_FLOATACC, "FAcc" },
2949 { OPERAND_TYPE_SREG2, "SReg2" },
2950 { OPERAND_TYPE_SREG3, "SReg3" },
2951 { OPERAND_TYPE_ACC, "Acc" },
2952 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2953 { OPERAND_TYPE_REGMMX, "rMMX" },
2954 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2955 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2956 { OPERAND_TYPE_REGZMM, "rZMM" },
2957 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2958 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2959};
2960
2961static void
40fb9820 2962pt (i386_operand_type t)
252b5132 2963{
40fb9820 2964 unsigned int j;
c6fb90c8 2965 i386_operand_type a;
252b5132 2966
40fb9820 2967 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2968 {
2969 a = operand_type_and (t, type_names[j].mask);
0349dc08 2970 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2971 fprintf (stdout, "%s, ", type_names[j].name);
2972 }
252b5132
RH		 2973 fflush (stdout);
2974}
2975
2976#endif /* DEBUG386 */
2977\f
252b5132 2978static bfd_reloc_code_real_type
3956db08 2979reloc (unsigned int size,
64e74474
AM		 2980 int pcrel,
2981 int sign,
2982 bfd_reloc_code_real_type other)
252b5132 2983{
47926f60 2984 if (other != NO_RELOC)
3956db08 2985 {
91d6fa6a 2986 reloc_howto_type *rel;
3956db08
JB		 2987
2988 if (size == 8)
2989 switch (other)
2990 {
64e74474
AM		 2991 case BFD_RELOC_X86_64_GOT32:
2992 return BFD_RELOC_X86_64_GOT64;
2993 break;
553d1284
L		 2994 case BFD_RELOC_X86_64_GOTPLT64:
2995 return BFD_RELOC_X86_64_GOTPLT64;
2996 break;
64e74474
AM		 2997 case BFD_RELOC_X86_64_PLTOFF64:
2998 return BFD_RELOC_X86_64_PLTOFF64;
2999 break;
3000 case BFD_RELOC_X86_64_GOTPC32:
3001 other = BFD_RELOC_X86_64_GOTPC64;
3002 break;
3003 case BFD_RELOC_X86_64_GOTPCREL:
3004 other = BFD_RELOC_X86_64_GOTPCREL64;
3005 break;
3006 case BFD_RELOC_X86_64_TPOFF32:
3007 other = BFD_RELOC_X86_64_TPOFF64;
3008 break;
3009 case BFD_RELOC_X86_64_DTPOFF32:
3010 other = BFD_RELOC_X86_64_DTPOFF64;
3011 break;
3012 default:
3013 break;
3956db08 3014 }
e05278af 3015
8ce3d284 3016#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 3017 if (other == BFD_RELOC_SIZE32)
3018 {
3019 if (size == 8)
1ab668bf 3020 other = BFD_RELOC_SIZE64;
8fd4256d 3021 if (pcrel)
1ab668bf
AM		 3022 {
3023 as_bad (_("there are no pc-relative size relocations"));
3024 return NO_RELOC;
3025 }
8fd4256d 3026 }
8ce3d284 3027#endif
8fd4256d 3028
e05278af 3029 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 3030 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 3031 sign = -1;
3032
91d6fa6a
NC		 3033 rel = bfd_reloc_type_lookup (stdoutput, other);
3034 if (!rel)
3956db08 3035 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 3036 else if (size != bfd_get_reloc_size (rel))
3956db08 3037 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 3038 bfd_get_reloc_size (rel),
3956db08 3039 size);
91d6fa6a 3040 else if (pcrel && !rel->pc_relative)
3956db08 3041 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 3042 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 3043 && !sign)
91d6fa6a 3044 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 3045 && sign > 0))
3956db08
JB		 3046 as_bad (_("relocated field and relocation type differ in signedness"));
3047 else
3048 return other;
3049 return NO_RELOC;
3050 }
252b5132
RH		 3051
3052 if (pcrel)
3053 {
3e73aa7c 3054 if (!sign)
3956db08 3055 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 3056 switch (size)
3057 {
3058 case 1: return BFD_RELOC_8_PCREL;
3059 case 2: return BFD_RELOC_16_PCREL;
d258b828 3060 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 3061 case 8: return BFD_RELOC_64_PCREL;
252b5132 3062 }
3956db08 3063 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 3064 }
3065 else
3066 {
3956db08 3067 if (sign > 0)
e5cb08ac 3068 switch (size)
3e73aa7c
JH		 3069 {
3070 case 4: return BFD_RELOC_X86_64_32S;
3071 }
3072 else
3073 switch (size)
3074 {
3075 case 1: return BFD_RELOC_8;
3076 case 2: return BFD_RELOC_16;
3077 case 4: return BFD_RELOC_32;
3078 case 8: return BFD_RELOC_64;
3079 }
3956db08
JB		 3080 as_bad (_("cannot do %s %u byte relocation"),
3081 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 3082 }
3083
0cc9e1d3 3084 return NO_RELOC;
252b5132
RH		 3085}
3086
47926f60
KH		 3087/* Here we decide which fixups can be adjusted to make them relative to
3088 the beginning of the section instead of the symbol. Basically we need
3089 to make sure that the dynamic relocations are done correctly, so in
3090 some cases we force the original symbol to be used. */
3091
252b5132 3092int
e3bb37b5 3093tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3094{
6d249963 3095#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3096 if (!IS_ELF)
31312f95
AM		 3097 return 1;
3098
a161fe53
AM		 3099 /* Don't adjust pc-relative references to merge sections in 64-bit
3100 mode. */
3101 if (use_rela_relocations
3102 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3103 && fixP->fx_pcrel)
252b5132 3104 return 0;
31312f95 3105
8d01d9a9
AJ		 3106 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3107 and changed later by validate_fix. */
3108 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3109 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3110 return 0;
3111
8fd4256d
L		 3112 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3113 for size relocations. */
3114 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3115 || fixP->fx_r_type == BFD_RELOC_SIZE64
3116 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3117 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3118 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3119 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3120 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3121 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3122 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3123 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3124 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3125 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3126 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3127 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3128 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3129 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3130 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3131 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3132 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3133 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3134 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3135 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3136 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3137 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3138 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3139 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3140 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3141 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3142 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3143 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3144 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3145 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3146 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3147 return 0;
31312f95 3148#endif
252b5132
RH		 3149 return 1;
3150}
252b5132 3151
b4cac588 3152static int
e3bb37b5 3153intel_float_operand (const char *mnemonic)
252b5132 3154{
9306ca4a
JB		 3155 /* Note that the value returned is meaningful only for opcodes with (memory)
3156 operands, hence the code here is free to improperly handle opcodes that
3157 have no operands (for better performance and smaller code). */
3158
3159 if (mnemonic[0] != 'f')
3160 return 0; /* non-math */
3161
3162 switch (mnemonic[1])
3163 {
3164 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3165 the fs segment override prefix not currently handled because no
3166 call path can make opcodes without operands get here */
3167 case 'i':
3168 return 2 /* integer op */;
3169 case 'l':
3170 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3171 return 3; /* fldcw/fldenv */
3172 break;
3173 case 'n':
3174 if (mnemonic[2] != 'o' /* fnop */)
3175 return 3; /* non-waiting control op */
3176 break;
3177 case 'r':
3178 if (mnemonic[2] == 's')
3179 return 3; /* frstor/frstpm */
3180 break;
3181 case 's':
3182 if (mnemonic[2] == 'a')
3183 return 3; /* fsave */
3184 if (mnemonic[2] == 't')
3185 {
3186 switch (mnemonic[3])
3187 {
3188 case 'c': /* fstcw */
3189 case 'd': /* fstdw */
3190 case 'e': /* fstenv */
3191 case 's': /* fsts[gw] */
3192 return 3;
3193 }
3194 }
3195 break;
3196 case 'x':
3197 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3198 return 0; /* fxsave/fxrstor are not really math ops */
3199 break;
3200 }
252b5132 3201
9306ca4a 3202 return 1;
252b5132
RH		 3203}
3204
c0f3af97
L		 3205/* Build the VEX prefix. */
3206
3207static void
d3ce72d0 3208build_vex_prefix (const insn_template *t)
c0f3af97
L		 3209{
3210 unsigned int register_specifier;
3211 unsigned int implied_prefix;
3212 unsigned int vector_length;
3213
3214 /* Check register specifier. */
3215 if (i.vex.register_specifier)
43234a1e
L		 3216 {
3217 register_specifier =
3218 ~register_number (i.vex.register_specifier) & 0xf;
3219 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3220 }
c0f3af97
L		 3221 else
3222 register_specifier = 0xf;
3223
33eaf5de 3224 /* Use 2-byte VEX prefix by swapping destination and source
fa99fab2 3225 operand. */
86fa6981
L		 3226 if (i.vec_encoding != vex_encoding_vex3
3227 && i.dir_encoding == dir_encoding_default
fa99fab2 3228 && i.operands == i.reg_operands
7f399153 3229 && i.tm.opcode_modifier.vexopcode == VEX0F
86fa6981 3230 && i.tm.opcode_modifier.load
fa99fab2
L		 3231 && i.rex == REX_B)
3232 {
3233 unsigned int xchg = i.operands - 1;
3234 union i386_op temp_op;
3235 i386_operand_type temp_type;
3236
3237 temp_type = i.types[xchg];
3238 i.types[xchg] = i.types[0];
3239 i.types[0] = temp_type;
3240 temp_op = i.op[xchg];
3241 i.op[xchg] = i.op[0];
3242 i.op[0] = temp_op;
3243
9c2799c2 3244 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3245
3246 i.rex = REX_R;
3247 xchg = i.rm.regmem;
3248 i.rm.regmem = i.rm.reg;
3249 i.rm.reg = xchg;
3250
3251 /* Use the next insn. */
3252 i.tm = t[1];
3253 }
3254
539f890d
L		 3255 if (i.tm.opcode_modifier.vex == VEXScalar)
3256 vector_length = avxscalar;
10c17abd
JB		 3257 else if (i.tm.opcode_modifier.vex == VEX256)
3258 vector_length = 1;
539f890d 3259 else
10c17abd
JB		 3260 {
3261 unsigned int op;
3262
3263 vector_length = 0;
3264 for (op = 0; op < t->operands; ++op)
3265 if (t->operand_types[op].bitfield.xmmword
3266 && t->operand_types[op].bitfield.ymmword
3267 && i.types[op].bitfield.ymmword)
3268 {
3269 vector_length = 1;
3270 break;
3271 }
3272 }
c0f3af97
L		 3273
3274 switch ((i.tm.base_opcode >> 8) & 0xff)
3275 {
3276 case 0:
3277 implied_prefix = 0;
3278 break;
3279 case DATA_PREFIX_OPCODE:
3280 implied_prefix = 1;
3281 break;
3282 case REPE_PREFIX_OPCODE:
3283 implied_prefix = 2;
3284 break;
3285 case REPNE_PREFIX_OPCODE:
3286 implied_prefix = 3;
3287 break;
3288 default:
3289 abort ();
3290 }
3291
3292 /* Use 2-byte VEX prefix if possible. */
86fa6981
L		 3293 if (i.vec_encoding != vex_encoding_vex3
3294 && i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3295 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3296 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3297 {
3298 /* 2-byte VEX prefix. */
3299 unsigned int r;
3300
3301 i.vex.length = 2;
3302 i.vex.bytes[0] = 0xc5;
3303
3304 /* Check the REX.R bit. */
3305 r = (i.rex & REX_R) ? 0 : 1;
3306 i.vex.bytes[1] = (r << 7
3307 | register_specifier << 3
3308 | vector_length << 2
3309 | implied_prefix);
3310 }
3311 else
3312 {
3313 /* 3-byte VEX prefix. */
3314 unsigned int m, w;
3315
f88c9eb0 3316 i.vex.length = 3;
f88c9eb0 3317
7f399153 3318 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3319 {
7f399153
L		 3320 case VEX0F:
3321 m = 0x1;
80de6e00 3322 i.vex.bytes[0] = 0xc4;
7f399153
L		 3323 break;
3324 case VEX0F38:
3325 m = 0x2;
80de6e00 3326 i.vex.bytes[0] = 0xc4;
7f399153
L		 3327 break;
3328 case VEX0F3A:
3329 m = 0x3;
80de6e00 3330 i.vex.bytes[0] = 0xc4;
7f399153
L		 3331 break;
3332 case XOP08:
5dd85c99
SP		 3333 m = 0x8;
3334 i.vex.bytes[0] = 0x8f;
7f399153
L		 3335 break;
3336 case XOP09:
f88c9eb0
SP		 3337 m = 0x9;
3338 i.vex.bytes[0] = 0x8f;
7f399153
L		 3339 break;
3340 case XOP0A:
f88c9eb0
SP		 3341 m = 0xa;
3342 i.vex.bytes[0] = 0x8f;
7f399153
L		 3343 break;
3344 default:
3345 abort ();
f88c9eb0 3346 }
c0f3af97 3347
c0f3af97
L		 3348 /* The high 3 bits of the second VEX byte are 1's compliment
3349 of RXB bits from REX. */
3350 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3351
3352 /* Check the REX.W bit. */
3353 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3354 if (i.tm.opcode_modifier.vexw == VEXW1)
3355 w = 1;
c0f3af97
L		 3356
3357 i.vex.bytes[2] = (w << 7
3358 | register_specifier << 3
3359 | vector_length << 2
3360 | implied_prefix);
3361 }
3362}
3363
43234a1e
L		 3364/* Build the EVEX prefix. */
3365
3366static void
3367build_evex_prefix (void)
3368{
3369 unsigned int register_specifier;
3370 unsigned int implied_prefix;
3371 unsigned int m, w;
3372 rex_byte vrex_used = 0;
3373
3374 /* Check register specifier. */
3375 if (i.vex.register_specifier)
3376 {
3377 gas_assert ((i.vrex & REX_X) == 0);
3378
3379 register_specifier = i.vex.register_specifier->reg_num;
3380 if ((i.vex.register_specifier->reg_flags & RegRex))
3381 register_specifier += 8;
3382 /* The upper 16 registers are encoded in the fourth byte of the
3383 EVEX prefix. */
3384 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3385 i.vex.bytes[3] = 0x8;
3386 register_specifier = ~register_specifier & 0xf;
3387 }
3388 else
3389 {
3390 register_specifier = 0xf;
3391
3392 /* Encode upper 16 vector index register in the fourth byte of
3393 the EVEX prefix. */
3394 if (!(i.vrex & REX_X))
3395 i.vex.bytes[3] = 0x8;
3396 else
3397 vrex_used |= REX_X;
3398 }
3399
3400 switch ((i.tm.base_opcode >> 8) & 0xff)
3401 {
3402 case 0:
3403 implied_prefix = 0;
3404 break;
3405 case DATA_PREFIX_OPCODE:
3406 implied_prefix = 1;
3407 break;
3408 case REPE_PREFIX_OPCODE:
3409 implied_prefix = 2;
3410 break;
3411 case REPNE_PREFIX_OPCODE:
3412 implied_prefix = 3;
3413 break;
3414 default:
3415 abort ();
3416 }
3417
3418 /* 4 byte EVEX prefix. */
3419 i.vex.length = 4;
3420 i.vex.bytes[0] = 0x62;
3421
3422 /* mmmm bits. */
3423 switch (i.tm.opcode_modifier.vexopcode)
3424 {
3425 case VEX0F:
3426 m = 1;
3427 break;
3428 case VEX0F38:
3429 m = 2;
3430 break;
3431 case VEX0F3A:
3432 m = 3;
3433 break;
3434 default:
3435 abort ();
3436 break;
3437 }
3438
3439 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3440 bits from REX. */
3441 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3442
3443 /* The fifth bit of the second EVEX byte is 1's compliment of the
3444 REX_R bit in VREX. */
3445 if (!(i.vrex & REX_R))
3446 i.vex.bytes[1] |= 0x10;
3447 else
3448 vrex_used |= REX_R;
3449
3450 if ((i.reg_operands + i.imm_operands) == i.operands)
3451 {
3452 /* When all operands are registers, the REX_X bit in REX is not
3453 used. We reuse it to encode the upper 16 registers, which is
3454 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3455 as 1's compliment. */
3456 if ((i.vrex & REX_B))
3457 {
3458 vrex_used |= REX_B;
3459 i.vex.bytes[1] &= ~0x40;
3460 }
3461 }
3462
3463 /* EVEX instructions shouldn't need the REX prefix. */
3464 i.vrex &= ~vrex_used;
3465 gas_assert (i.vrex == 0);
3466
3467 /* Check the REX.W bit. */
3468 w = (i.rex & REX_W) ? 1 : 0;
3469 if (i.tm.opcode_modifier.vexw)
3470 {
3471 if (i.tm.opcode_modifier.vexw == VEXW1)
3472 w = 1;
3473 }
3474 /* If w is not set it means we are dealing with WIG instruction. */
3475 else if (!w)
3476 {
3477 if (evexwig == evexw1)
3478 w = 1;
3479 }
3480
3481 /* Encode the U bit. */
3482 implied_prefix |= 0x4;
3483
3484 /* The third byte of the EVEX prefix. */
3485 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3486
3487 /* The fourth byte of the EVEX prefix. */
3488 /* The zeroing-masking bit. */
3489 if (i.mask && i.mask->zeroing)
3490 i.vex.bytes[3] |= 0x80;
3491
3492 /* Don't always set the broadcast bit if there is no RC. */
3493 if (!i.rounding)
3494 {
3495 /* Encode the vector length. */
3496 unsigned int vec_length;
3497
3498 switch (i.tm.opcode_modifier.evex)
3499 {
3500 case EVEXLIG: /* LL' is ignored */
3501 vec_length = evexlig << 5;
3502 break;
3503 case EVEX128:
3504 vec_length = 0 << 5;
3505 break;
3506 case EVEX256:
3507 vec_length = 1 << 5;
3508 break;
3509 case EVEX512:
3510 vec_length = 2 << 5;
3511 break;
3512 default:
3513 abort ();
3514 break;
3515 }
3516 i.vex.bytes[3] |= vec_length;
3517 /* Encode the broadcast bit. */
3518 if (i.broadcast)
3519 i.vex.bytes[3] |= 0x10;
3520 }
3521 else
3522 {
3523 if (i.rounding->type != saeonly)
3524 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3525 else
d3d3c6db 3526 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3527 }
3528
3529 if (i.mask && i.mask->mask)
3530 i.vex.bytes[3] |= i.mask->mask->reg_num;
3531}
3532
65da13b5
L		 3533static void
3534process_immext (void)
3535{
3536 expressionS *exp;
3537
4c692bc7
JB		 3538 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3539 && i.operands > 0)
65da13b5 3540 {
4c692bc7
JB		 3541 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3542 with an opcode suffix which is coded in the same place as an
3543 8-bit immediate field would be.
3544 Here we check those operands and remove them afterwards. */
65da13b5
L		 3545 unsigned int x;
3546
3547 for (x = 0; x < i.operands; x++)
4c692bc7 3548 if (register_number (i.op[x].regs) != x)
65da13b5 3549 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3550 register_prefix, i.op[x].regs->reg_name, x + 1,
3551 i.tm.name);
3552
3553 i.operands = 0;
65da13b5
L		 3554 }
3555
9916071f
AP		 3556 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3557 {
3558 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3559 suffix which is coded in the same place as an 8-bit immediate
3560 field would be.
3561 Here we check those operands and remove them afterwards. */
3562 unsigned int x;
3563
3564 if (i.operands != 3)
3565 abort();
3566
3567 for (x = 0; x < 2; x++)
3568 if (register_number (i.op[x].regs) != x)
3569 goto bad_register_operand;
3570
3571 /* Check for third operand for mwaitx/monitorx insn. */
3572 if (register_number (i.op[x].regs)
3573 != (x + (i.tm.extension_opcode == 0xfb)))
3574 {
3575bad_register_operand:
3576 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3577 register_prefix, i.op[x].regs->reg_name, x+1,
3578 i.tm.name);
3579 }
3580
3581 i.operands = 0;
3582 }
3583
c0f3af97 3584 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3585 which is coded in the same place as an 8-bit immediate field
3586 would be. Here we fake an 8-bit immediate operand from the
3587 opcode suffix stored in tm.extension_opcode.
3588
c1e679ec 3589 AVX instructions also use this encoding, for some of
c0f3af97 3590 3 argument instructions. */
65da13b5 3591
43234a1e 3592 gas_assert (i.imm_operands <= 1
7ab9ffdd 3593 && (i.operands <= 2
43234a1e
L		 3594 || ((i.tm.opcode_modifier.vex
3595 || i.tm.opcode_modifier.evex)
7ab9ffdd 3596 && i.operands <= 4)));
65da13b5
L		 3597
3598 exp = &im_expressions[i.imm_operands++];
3599 i.op[i.operands].imms = exp;
3600 i.types[i.operands] = imm8;
3601 i.operands++;
3602 exp->X_op = O_constant;
3603 exp->X_add_number = i.tm.extension_opcode;
3604 i.tm.extension_opcode = None;
3605}
3606
42164a71
L		 3607
3608static int
3609check_hle (void)
3610{
3611 switch (i.tm.opcode_modifier.hleprefixok)
3612 {
3613 default:
3614 abort ();
82c2def5 3615 case HLEPrefixNone:
165de32a
L		 3616 as_bad (_("invalid instruction `%s' after `%s'"),
3617 i.tm.name, i.hle_prefix);
42164a71 3618 return 0;
82c2def5 3619 case HLEPrefixLock:
42164a71
L		 3620 if (i.prefix[LOCK_PREFIX])
3621 return 1;
165de32a 3622 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3623 return 0;
82c2def5 3624 case HLEPrefixAny:
42164a71 3625 return 1;
82c2def5 3626 case HLEPrefixRelease:
42164a71
L		 3627 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3628 {
3629 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3630 i.tm.name);
3631 return 0;
3632 }
3633 if (i.mem_operands == 0
3634 || !operand_type_check (i.types[i.operands - 1], anymem))
3635 {
3636 as_bad (_("memory destination needed for instruction `%s'"
3637 " after `xrelease'"), i.tm.name);
3638 return 0;
3639 }
3640 return 1;
3641 }
3642}
3643
252b5132
RH		 3644/* This is the guts of the machine-dependent assembler. LINE points to a
3645 machine dependent instruction. This function is supposed to emit
3646 the frags/bytes it assembles to. */
3647
3648void
65da13b5 3649md_assemble (char *line)
252b5132 3650{
40fb9820 3651 unsigned int j;
83b16ac6 3652 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 3653 const insn_template *t;
252b5132 3654
47926f60 3655 /* Initialize globals. */
252b5132
RH		 3656 memset (&i, '\0', sizeof (i));
3657 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3658 i.reloc[j] = NO_RELOC;
252b5132
RH		 3659 memset (disp_expressions, '\0', sizeof (disp_expressions));
3660 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3661 save_stack_p = save_stack;
252b5132
RH		 3662
3663 /* First parse an instruction mnemonic & call i386_operand for the operands.
3664 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3665 start of a (possibly prefixed) mnemonic. */
252b5132 3666
29b0f896
AM		 3667 line = parse_insn (line, mnemonic);
3668 if (line == NULL)
3669 return;
83b16ac6 3670 mnem_suffix = i.suffix;
252b5132 3671
29b0f896 3672 line = parse_operands (line, mnemonic);
ee86248c 3673 this_operand = -1;
8325cc63
JB		 3674 xfree (i.memop1_string);
3675 i.memop1_string = NULL;
29b0f896
AM		 3676 if (line == NULL)
3677 return;
252b5132 3678
29b0f896
AM		 3679 /* Now we've parsed the mnemonic into a set of templates, and have the
3680 operands at hand. */
3681
3682 /* All intel opcodes have reversed operands except for "bound" and
3683 "enter". We also don't reverse intersegment "jmp" and "call"
3684 instructions with 2 immediate operands so that the immediate segment
050dfa73 3685 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3686 if (intel_syntax
3687 && i.operands > 1
29b0f896 3688 && (strcmp (mnemonic, "bound") != 0)
30123838 3689 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3690 && !(operand_type_check (i.types[0], imm)
3691 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3692 swap_operands ();
3693
ec56d5c0
JB		 3694 /* The order of the immediates should be reversed
3695 for 2 immediates extrq and insertq instructions */
3696 if (i.imm_operands == 2
3697 && (strcmp (mnemonic, "extrq") == 0
3698 || strcmp (mnemonic, "insertq") == 0))
3699 swap_2_operands (0, 1);
3700
29b0f896
AM		 3701 if (i.imm_operands)
3702 optimize_imm ();
3703
b300c311
L		 3704 /* Don't optimize displacement for movabs since it only takes 64bit
3705 displacement. */
3706 if (i.disp_operands
a501d77e 3707 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3708 && (flag_code != CODE_64BIT
3709 || strcmp (mnemonic, "movabs") != 0))
3710 optimize_disp ();
29b0f896
AM		 3711
3712 /* Next, we find a template that matches the given insn,
3713 making sure the overlap of the given operands types is consistent
3714 with the template operand types. */
252b5132 3715
83b16ac6 3716 if (!(t = match_template (mnem_suffix)))
29b0f896 3717 return;
252b5132 3718
7bab8ab5 3719 if (sse_check != check_none
81f8a913 3720 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3721 && (i.tm.cpu_flags.bitfield.cpusse
3722 || i.tm.cpu_flags.bitfield.cpusse2
3723 || i.tm.cpu_flags.bitfield.cpusse3
3724 || i.tm.cpu_flags.bitfield.cpussse3
3725 || i.tm.cpu_flags.bitfield.cpusse4_1
3726 || i.tm.cpu_flags.bitfield.cpusse4_2))
3727 {
7bab8ab5 3728 (sse_check == check_warning
daf50ae7
L		 3729 ? as_warn
3730 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3731 }
3732
321fd21e
L		 3733 /* Zap movzx and movsx suffix. The suffix has been set from
3734 "word ptr" or "byte ptr" on the source operand in Intel syntax
3735 or extracted from mnemonic in AT&T syntax. But we'll use
3736 the destination register to choose the suffix for encoding. */
3737 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3738 {
321fd21e
L		 3739 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3740 there is no suffix, the default will be byte extension. */
3741 if (i.reg_operands != 2
3742 && !i.suffix
7ab9ffdd 3743 && intel_syntax)
321fd21e
L		 3744 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3745
3746 i.suffix = 0;
cd61ebfe 3747 }
24eab124 3748
40fb9820 3749 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3750 if (!add_prefix (FWAIT_OPCODE))
3751 return;
252b5132 3752
d5de92cf
L		 3753 /* Check if REP prefix is OK. */
3754 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3755 {
3756 as_bad (_("invalid instruction `%s' after `%s'"),
3757 i.tm.name, i.rep_prefix);
3758 return;
3759 }
3760
c1ba0266
L		 3761 /* Check for lock without a lockable instruction. Destination operand
3762 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3763 if (i.prefix[LOCK_PREFIX]
3764 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3765 || i.mem_operands == 0
3766 || (i.tm.base_opcode != 0x86
3767 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3768 {
3769 as_bad (_("expecting lockable instruction after `lock'"));
3770 return;
3771 }
3772
42164a71 3773 /* Check if HLE prefix is OK. */
165de32a 3774 if (i.hle_prefix && !check_hle ())
42164a71
L		 3775 return;
3776
7e8b059b
L		 3777 /* Check BND prefix. */
3778 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3779 as_bad (_("expecting valid branch instruction after `bnd'"));
3780
04ef582a 3781 /* Check NOTRACK prefix. */
9fef80d6
L		 3782 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
3783 as_bad (_("expecting indirect branch instruction after `notrack'"));
04ef582a 3784
327e8c42
JB		 3785 if (i.tm.cpu_flags.bitfield.cpumpx)
3786 {
3787 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
3788 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3789 else if (flag_code != CODE_16BIT
3790 ? i.prefix[ADDR_PREFIX]
3791 : i.mem_operands && !i.prefix[ADDR_PREFIX])
3792 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3793 }
7e8b059b
L		 3794
3795 /* Insert BND prefix. */
3796 if (add_bnd_prefix
3797 && i.tm.opcode_modifier.bndprefixok
3798 && !i.prefix[BND_PREFIX])
3799 add_prefix (BND_PREFIX_OPCODE);
3800
29b0f896 3801 /* Check string instruction segment overrides. */
40fb9820 3802 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3803 {
3804 if (!check_string ())
5dd0794d 3805 return;
fc0763e6 3806 i.disp_operands = 0;
29b0f896 3807 }
5dd0794d 3808
29b0f896
AM		 3809 if (!process_suffix ())
3810 return;
e413e4e9 3811
bc0844ae
L		 3812 /* Update operand types. */
3813 for (j = 0; j < i.operands; j++)
3814 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3815
29b0f896
AM		 3816 /* Make still unresolved immediate matches conform to size of immediate
3817 given in i.suffix. */
3818 if (!finalize_imm ())
3819 return;
252b5132 3820
40fb9820 3821 if (i.types[0].bitfield.imm1)
29b0f896 3822 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3823
9afe6eb8
L		 3824 /* We only need to check those implicit registers for instructions
3825 with 3 operands or less. */
3826 if (i.operands <= 3)
3827 for (j = 0; j < i.operands; j++)
3828 if (i.types[j].bitfield.inoutportreg
3829 || i.types[j].bitfield.shiftcount
1b54b8d7 3830 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
9afe6eb8 3831 i.reg_operands--;
40fb9820 3832
c0f3af97
L		 3833 /* ImmExt should be processed after SSE2AVX. */
3834 if (!i.tm.opcode_modifier.sse2avx
3835 && i.tm.opcode_modifier.immext)
65da13b5 3836 process_immext ();
252b5132 3837
29b0f896
AM		 3838 /* For insns with operands there are more diddles to do to the opcode. */
3839 if (i.operands)
3840 {
3841 if (!process_operands ())
3842 return;
3843 }
40fb9820 3844 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3845 {
3846 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3847 as_warn (_("translating to `%sp'"), i.tm.name);
3848 }
252b5132 3849
9e5e5283
L		 3850 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3851 {
3852 if (flag_code == CODE_16BIT)
3853 {
3854 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3855 i.tm.name);
3856 return;
3857 }
c0f3af97 3858
9e5e5283
L		 3859 if (i.tm.opcode_modifier.vex)
3860 build_vex_prefix (t);
3861 else
3862 build_evex_prefix ();
3863 }
43234a1e 3864
5dd85c99
SP		 3865 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3866 instructions may define INT_OPCODE as well, so avoid this corner
3867 case for those instructions that use MODRM. */
3868 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3869 && !i.tm.opcode_modifier.modrm
3870 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3871 {
3872 i.tm.base_opcode = INT3_OPCODE;
3873 i.imm_operands = 0;
3874 }
252b5132 3875
40fb9820
L		 3876 if ((i.tm.opcode_modifier.jump
3877 || i.tm.opcode_modifier.jumpbyte
3878 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3879 && i.op[0].disps->X_op == O_constant)
3880 {
3881 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3882 the absolute address given by the constant. Since ix86 jumps and
3883 calls are pc relative, we need to generate a reloc. */
3884 i.op[0].disps->X_add_symbol = &abs_symbol;
3885 i.op[0].disps->X_op = O_symbol;
3886 }
252b5132 3887
40fb9820 3888 if (i.tm.opcode_modifier.rex64)
161a04f6 3889 i.rex |= REX_W;
252b5132 3890
29b0f896
AM		 3891 /* For 8 bit registers we need an empty rex prefix. Also if the
3892 instruction already has a prefix, we need to convert old
3893 registers to new ones. */
773f551c 3894
dc821c5f 3895 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
29b0f896 3896 && (i.op[0].regs->reg_flags & RegRex64) != 0)
dc821c5f 3897 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
29b0f896 3898 && (i.op[1].regs->reg_flags & RegRex64) != 0)
dc821c5f
JB		 3899 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
3900 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
29b0f896
AM		 3901 && i.rex != 0))
3902 {
3903 int x;
726c5dcd 3904
29b0f896
AM		 3905 i.rex |= REX_OPCODE;
3906 for (x = 0; x < 2; x++)
3907 {
3908 /* Look for 8 bit operand that uses old registers. */
dc821c5f 3909 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
29b0f896 3910 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3911 {
29b0f896
AM		 3912 /* In case it is "hi" register, give up. */
3913 if (i.op[x].regs->reg_num > 3)
a540244d 3914 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3915 "instruction requiring REX prefix."),
a540244d 3916 register_prefix, i.op[x].regs->reg_name);
773f551c 3917
29b0f896
AM		 3918 /* Otherwise it is equivalent to the extended register.
3919 Since the encoding doesn't change this is merely
3920 cosmetic cleanup for debug output. */
3921
3922 i.op[x].regs = i.op[x].regs + 8;
773f551c 3923 }
29b0f896
AM		 3924 }
3925 }
773f551c 3926
7ab9ffdd 3927 if (i.rex != 0)
29b0f896
AM		 3928 add_prefix (REX_OPCODE | i.rex);
3929
3930 /* We are ready to output the insn. */
3931 output_insn ();
3932}
3933
3934static char *
e3bb37b5 3935parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3936{
3937 char *l = line;
3938 char *token_start = l;
3939 char *mnem_p;
5c6af06e 3940 int supported;
d3ce72d0 3941 const insn_template *t;
b6169b20 3942 char *dot_p = NULL;
29b0f896 3943
29b0f896
AM		 3944 while (1)
3945 {
3946 mnem_p = mnemonic;
3947 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3948 {
b6169b20
L		 3949 if (*mnem_p == '.')
3950 dot_p = mnem_p;
29b0f896
AM		 3951 mnem_p++;
3952 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3953 {
29b0f896
AM		 3954 as_bad (_("no such instruction: `%s'"), token_start);
3955 return NULL;
3956 }
3957 l++;
3958 }
3959 if (!is_space_char (*l)
3960 && *l != END_OF_INSN
e44823cf
JB		 3961 && (intel_syntax
3962 || (*l != PREFIX_SEPARATOR
3963 && *l != ',')))
29b0f896
AM		 3964 {
3965 as_bad (_("invalid character %s in mnemonic"),
3966 output_invalid (*l));
3967 return NULL;
3968 }
3969 if (token_start == l)
3970 {
e44823cf 3971 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3972 as_bad (_("expecting prefix; got nothing"));
3973 else
3974 as_bad (_("expecting mnemonic; got nothing"));
3975 return NULL;
3976 }
45288df1 3977
29b0f896 3978 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3979 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3980
29b0f896
AM		 3981 if (*l != END_OF_INSN
3982 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3983 && current_templates
40fb9820 3984 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3985 {
c6fb90c8 3986 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3987 {
3988 as_bad ((flag_code != CODE_64BIT
3989 ? _("`%s' is only supported in 64-bit mode")
3990 : _("`%s' is not supported in 64-bit mode")),
3991 current_templates->start->name);
3992 return NULL;
3993 }
29b0f896
AM		 3994 /* If we are in 16-bit mode, do not allow addr16 or data16.
3995 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3996 if ((current_templates->start->opcode_modifier.size16
3997 || current_templates->start->opcode_modifier.size32)
29b0f896 3998 && flag_code != CODE_64BIT
40fb9820 3999 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 4000 ^ (flag_code == CODE_16BIT)))
4001 {
4002 as_bad (_("redundant %s prefix"),
4003 current_templates->start->name);
4004 return NULL;
45288df1 4005 }
86fa6981 4006 if (current_templates->start->opcode_length == 0)
29b0f896 4007 {
86fa6981
L		 4008 /* Handle pseudo prefixes. */
4009 switch (current_templates->start->base_opcode)
4010 {
4011 case 0x0:
4012 /* {disp8} */
4013 i.disp_encoding = disp_encoding_8bit;
4014 break;
4015 case 0x1:
4016 /* {disp32} */
4017 i.disp_encoding = disp_encoding_32bit;
4018 break;
4019 case 0x2:
4020 /* {load} */
4021 i.dir_encoding = dir_encoding_load;
4022 break;
4023 case 0x3:
4024 /* {store} */
4025 i.dir_encoding = dir_encoding_store;
4026 break;
4027 case 0x4:
4028 /* {vex2} */
4029 i.vec_encoding = vex_encoding_vex2;
4030 break;
4031 case 0x5:
4032 /* {vex3} */
4033 i.vec_encoding = vex_encoding_vex3;
4034 break;
4035 case 0x6:
4036 /* {evex} */
4037 i.vec_encoding = vex_encoding_evex;
4038 break;
4039 default:
4040 abort ();
4041 }
4042 }
4043 else
4044 {
4045 /* Add prefix, checking for repeated prefixes. */
4e9ac44a 4046 switch (add_prefix (current_templates->start->base_opcode))
86fa6981 4047 {
4e9ac44a
L		 4048 case PREFIX_EXIST:
4049 return NULL;
4050 case PREFIX_DS:
4051 if (current_templates->start->cpu_flags.bitfield.cpucet)
4052 i.notrack_prefix = current_templates->start->name;
4053 break;
4054 case PREFIX_REP:
4055 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4056 i.hle_prefix = current_templates->start->name;
4057 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4058 i.bnd_prefix = current_templates->start->name;
4059 else
4060 i.rep_prefix = current_templates->start->name;
4061 break;
4062 default:
4063 break;
86fa6981 4064 }
29b0f896
AM		 4065 }
4066 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4067 token_start = ++l;
4068 }
4069 else
4070 break;
4071 }
45288df1 4072
30a55f88 4073 if (!current_templates)
b6169b20 4074 {
f8a5c266
L		 4075 /* Check if we should swap operand or force 32bit displacement in
4076 encoding. */
30a55f88 4077 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
86fa6981 4078 i.dir_encoding = dir_encoding_store;
8d63c93e 4079 else if (mnem_p - 3 == dot_p
a501d77e
L		 4080 && dot_p[1] == 'd'
4081 && dot_p[2] == '8')
4082 i.disp_encoding = disp_encoding_8bit;
8d63c93e 4083 else if (mnem_p - 4 == dot_p
f8a5c266
L		 4084 && dot_p[1] == 'd'
4085 && dot_p[2] == '3'
4086 && dot_p[3] == '2')
a501d77e 4087 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 4088 else
4089 goto check_suffix;
4090 mnem_p = dot_p;
4091 *dot_p = '\0';
d3ce72d0 4092 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 4093 }
4094
29b0f896
AM		 4095 if (!current_templates)
4096 {
b6169b20 4097check_suffix:
29b0f896
AM		 4098 /* See if we can get a match by trimming off a suffix. */
4099 switch (mnem_p[-1])
4100 {
4101 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 4102 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4103 i.suffix = SHORT_MNEM_SUFFIX;
4104 else
1a0670f3 4105 /* Fall through. */
29b0f896
AM		 4106 case BYTE_MNEM_SUFFIX:
4107 case QWORD_MNEM_SUFFIX:
4108 i.suffix = mnem_p[-1];
4109 mnem_p[-1] = '\0';
d3ce72d0
NC		 4110 current_templates = (const templates *) hash_find (op_hash,
4111 mnemonic);
29b0f896
AM		 4112 break;
4113 case SHORT_MNEM_SUFFIX:
4114 case LONG_MNEM_SUFFIX:
4115 if (!intel_syntax)
4116 {
4117 i.suffix = mnem_p[-1];
4118 mnem_p[-1] = '\0';
d3ce72d0
NC		 4119 current_templates = (const templates *) hash_find (op_hash,
4120 mnemonic);
29b0f896
AM		 4121 }
4122 break;
252b5132 4123
29b0f896
AM		 4124 /* Intel Syntax. */
4125 case 'd':
4126 if (intel_syntax)
4127 {
9306ca4a 4128 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 4129 i.suffix = SHORT_MNEM_SUFFIX;
4130 else
4131 i.suffix = LONG_MNEM_SUFFIX;
4132 mnem_p[-1] = '\0';
d3ce72d0
NC		 4133 current_templates = (const templates *) hash_find (op_hash,
4134 mnemonic);
29b0f896
AM		 4135 }
4136 break;
4137 }
4138 if (!current_templates)
4139 {
4140 as_bad (_("no such instruction: `%s'"), token_start);
4141 return NULL;
4142 }
4143 }
252b5132 4144
40fb9820
L		 4145 if (current_templates->start->opcode_modifier.jump
4146 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 4147 {
4148 /* Check for a branch hint. We allow ",pt" and ",pn" for
4149 predict taken and predict not taken respectively.
4150 I'm not sure that branch hints actually do anything on loop
4151 and jcxz insns (JumpByte) for current Pentium4 chips. They
4152 may work in the future and it doesn't hurt to accept them
4153 now. */
4154 if (l[0] == ',' && l[1] == 'p')
4155 {
4156 if (l[2] == 't')
4157 {
4158 if (!add_prefix (DS_PREFIX_OPCODE))
4159 return NULL;
4160 l += 3;
4161 }
4162 else if (l[2] == 'n')
4163 {
4164 if (!add_prefix (CS_PREFIX_OPCODE))
4165 return NULL;
4166 l += 3;
4167 }
4168 }
4169 }
4170 /* Any other comma loses. */
4171 if (*l == ',')
4172 {
4173 as_bad (_("invalid character %s in mnemonic"),
4174 output_invalid (*l));
4175 return NULL;
4176 }
252b5132 4177
29b0f896 4178 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4179 supported = 0;
4180 for (t = current_templates->start; t < current_templates->end; ++t)
4181 {
c0f3af97
L		 4182 supported |= cpu_flags_match (t);
4183 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 4184 goto skip;
5c6af06e 4185 }
3629bb00 4186
c0f3af97 4187 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 4188 {
4189 as_bad (flag_code == CODE_64BIT
4190 ? _("`%s' is not supported in 64-bit mode")
4191 : _("`%s' is only supported in 64-bit mode"),
4192 current_templates->start->name);
4193 return NULL;
4194 }
c0f3af97 4195 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 4196 {
3629bb00 4197 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 4198 current_templates->start->name,
41aacd83 4199 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 4200 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4201 return NULL;
29b0f896 4202 }
3629bb00
L		 4203
4204skip:
4205 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 4206 && (flag_code != CODE_16BIT))
29b0f896
AM		 4207 {
4208 as_warn (_("use .code16 to ensure correct addressing mode"));
4209 }
252b5132 4210
29b0f896
AM		 4211 return l;
4212}
252b5132 4213
29b0f896 4214static char *
e3bb37b5 4215parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4216{
4217 char *token_start;
3138f287 4218
29b0f896
AM		 4219 /* 1 if operand is pending after ','. */
4220 unsigned int expecting_operand = 0;
252b5132 4221
29b0f896
AM		 4222 /* Non-zero if operand parens not balanced. */
4223 unsigned int paren_not_balanced;
4224
4225 while (*l != END_OF_INSN)
4226 {
4227 /* Skip optional white space before operand. */
4228 if (is_space_char (*l))
4229 ++l;
d02603dc 4230 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4231 {
4232 as_bad (_("invalid character %s before operand %d"),
4233 output_invalid (*l),
4234 i.operands + 1);
4235 return NULL;
4236 }
d02603dc 4237 token_start = l; /* After white space. */
29b0f896
AM		 4238 paren_not_balanced = 0;
4239 while (paren_not_balanced || *l != ',')
4240 {
4241 if (*l == END_OF_INSN)
4242 {
4243 if (paren_not_balanced)
4244 {
4245 if (!intel_syntax)
4246 as_bad (_("unbalanced parenthesis in operand %d."),
4247 i.operands + 1);
4248 else
4249 as_bad (_("unbalanced brackets in operand %d."),
4250 i.operands + 1);
4251 return NULL;
4252 }
4253 else
4254 break; /* we are done */
4255 }
d02603dc 4256 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4257 {
4258 as_bad (_("invalid character %s in operand %d"),
4259 output_invalid (*l),
4260 i.operands + 1);
4261 return NULL;
4262 }
4263 if (!intel_syntax)
4264 {
4265 if (*l == '(')
4266 ++paren_not_balanced;
4267 if (*l == ')')
4268 --paren_not_balanced;
4269 }
4270 else
4271 {
4272 if (*l == '[')
4273 ++paren_not_balanced;
4274 if (*l == ']')
4275 --paren_not_balanced;
4276 }
4277 l++;
4278 }
4279 if (l != token_start)
4280 { /* Yes, we've read in another operand. */
4281 unsigned int operand_ok;
4282 this_operand = i.operands++;
4283 if (i.operands > MAX_OPERANDS)
4284 {
4285 as_bad (_("spurious operands; (%d operands/instruction max)"),
4286 MAX_OPERANDS);
4287 return NULL;
4288 }
9d46ce34 4289 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4290 /* Now parse operand adding info to 'i' as we go along. */
4291 END_STRING_AND_SAVE (l);
4292
4293 if (intel_syntax)
4294 operand_ok =
4295 i386_intel_operand (token_start,
4296 intel_float_operand (mnemonic));
4297 else
a7619375 4298 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4299
4300 RESTORE_END_STRING (l);
4301 if (!operand_ok)
4302 return NULL;
4303 }
4304 else
4305 {
4306 if (expecting_operand)
4307 {
4308 expecting_operand_after_comma:
4309 as_bad (_("expecting operand after ','; got nothing"));
4310 return NULL;
4311 }
4312 if (*l == ',')
4313 {
4314 as_bad (_("expecting operand before ','; got nothing"));
4315 return NULL;
4316 }
4317 }
7f3f1ea2 4318
29b0f896
AM		 4319 /* Now *l must be either ',' or END_OF_INSN. */
4320 if (*l == ',')
4321 {
4322 if (*++l == END_OF_INSN)
4323 {
4324 /* Just skip it, if it's \n complain. */
4325 goto expecting_operand_after_comma;
4326 }
4327 expecting_operand = 1;
4328 }
4329 }
4330 return l;
4331}
7f3f1ea2 4332
050dfa73 4333static void
4d456e3d 4334swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4335{
4336 union i386_op temp_op;
40fb9820 4337 i386_operand_type temp_type;
050dfa73 4338 enum bfd_reloc_code_real temp_reloc;
4eed87de 4339
050dfa73
MM		 4340 temp_type = i.types[xchg2];
4341 i.types[xchg2] = i.types[xchg1];
4342 i.types[xchg1] = temp_type;
4343 temp_op = i.op[xchg2];
4344 i.op[xchg2] = i.op[xchg1];
4345 i.op[xchg1] = temp_op;
4346 temp_reloc = i.reloc[xchg2];
4347 i.reloc[xchg2] = i.reloc[xchg1];
4348 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4349
4350 if (i.mask)
4351 {
4352 if (i.mask->operand == xchg1)
4353 i.mask->operand = xchg2;
4354 else if (i.mask->operand == xchg2)
4355 i.mask->operand = xchg1;
4356 }
4357 if (i.broadcast)
4358 {
4359 if (i.broadcast->operand == xchg1)
4360 i.broadcast->operand = xchg2;
4361 else if (i.broadcast->operand == xchg2)
4362 i.broadcast->operand = xchg1;
4363 }
4364 if (i.rounding)
4365 {
4366 if (i.rounding->operand == xchg1)
4367 i.rounding->operand = xchg2;
4368 else if (i.rounding->operand == xchg2)
4369 i.rounding->operand = xchg1;
4370 }
050dfa73
MM		 4371}
4372
29b0f896 4373static void
e3bb37b5 4374swap_operands (void)
29b0f896 4375{
b7c61d9a 4376 switch (i.operands)
050dfa73 4377 {
c0f3af97 4378 case 5:
b7c61d9a 4379 case 4:
4d456e3d 4380 swap_2_operands (1, i.operands - 2);
1a0670f3 4381 /* Fall through. */
b7c61d9a
L		 4382 case 3:
4383 case 2:
4d456e3d 4384 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4385 break;
4386 default:
4387 abort ();
29b0f896 4388 }
29b0f896
AM		 4389
4390 if (i.mem_operands == 2)
4391 {
4392 const seg_entry *temp_seg;
4393 temp_seg = i.seg[0];
4394 i.seg[0] = i.seg[1];
4395 i.seg[1] = temp_seg;
4396 }
4397}
252b5132 4398
29b0f896
AM		 4399/* Try to ensure constant immediates are represented in the smallest
4400 opcode possible. */
4401static void
e3bb37b5 4402optimize_imm (void)
29b0f896
AM		 4403{
4404 char guess_suffix = 0;
4405 int op;
252b5132 4406
29b0f896
AM		 4407 if (i.suffix)
4408 guess_suffix = i.suffix;
4409 else if (i.reg_operands)
4410 {
4411 /* Figure out a suffix from the last register operand specified.
4412 We can't do this properly yet, ie. excluding InOutPortReg,
4413 but the following works for instructions with immediates.
4414 In any case, we can't set i.suffix yet. */
4415 for (op = i.operands; --op >= 0;)
dc821c5f 4416 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
7ab9ffdd 4417 {
40fb9820
L		 4418 guess_suffix = BYTE_MNEM_SUFFIX;
4419 break;
4420 }
dc821c5f 4421 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
252b5132 4422 {
40fb9820
L		 4423 guess_suffix = WORD_MNEM_SUFFIX;
4424 break;
4425 }
dc821c5f 4426 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
40fb9820
L		 4427 {
4428 guess_suffix = LONG_MNEM_SUFFIX;
4429 break;
4430 }
dc821c5f 4431 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
40fb9820
L		 4432 {
4433 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4434 break;
252b5132 4435 }
29b0f896
AM		 4436 }
4437 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4438 guess_suffix = WORD_MNEM_SUFFIX;
4439
4440 for (op = i.operands; --op >= 0;)
40fb9820 4441 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4442 {
4443 switch (i.op[op].imms->X_op)
252b5132 4444 {
29b0f896
AM		 4445 case O_constant:
4446 /* If a suffix is given, this operand may be shortened. */
4447 switch (guess_suffix)
252b5132 4448 {
29b0f896 4449 case LONG_MNEM_SUFFIX:
40fb9820
L		 4450 i.types[op].bitfield.imm32 = 1;
4451 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4452 break;
4453 case WORD_MNEM_SUFFIX:
40fb9820
L		 4454 i.types[op].bitfield.imm16 = 1;
4455 i.types[op].bitfield.imm32 = 1;
4456 i.types[op].bitfield.imm32s = 1;
4457 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4458 break;
4459 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4460 i.types[op].bitfield.imm8 = 1;
4461 i.types[op].bitfield.imm8s = 1;
4462 i.types[op].bitfield.imm16 = 1;
4463 i.types[op].bitfield.imm32 = 1;
4464 i.types[op].bitfield.imm32s = 1;
4465 i.types[op].bitfield.imm64 = 1;
29b0f896 4466 break;
252b5132 4467 }
252b5132 4468
29b0f896
AM		 4469 /* If this operand is at most 16 bits, convert it
4470 to a signed 16 bit number before trying to see
4471 whether it will fit in an even smaller size.
4472 This allows a 16-bit operand such as $0xffe0 to
4473 be recognised as within Imm8S range. */
40fb9820 4474 if ((i.types[op].bitfield.imm16)
29b0f896 4475 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4476 {
29b0f896
AM		 4477 i.op[op].imms->X_add_number =
4478 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4479 }
a28def75
L		 4480#ifdef BFD64
4481 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4482 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4483 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4484 == 0))
4485 {
4486 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4487 ^ ((offsetT) 1 << 31))
4488 - ((offsetT) 1 << 31));
4489 }
a28def75 4490#endif
40fb9820 4491 i.types[op]
c6fb90c8
L		 4492 = operand_type_or (i.types[op],
4493 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4494
29b0f896
AM		 4495 /* We must avoid matching of Imm32 templates when 64bit
4496 only immediate is available. */
4497 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4498 i.types[op].bitfield.imm32 = 0;
29b0f896 4499 break;
252b5132 4500
29b0f896
AM		 4501 case O_absent:
4502 case O_register:
4503 abort ();
4504
4505 /* Symbols and expressions. */
4506 default:
9cd96992
JB		 4507 /* Convert symbolic operand to proper sizes for matching, but don't
4508 prevent matching a set of insns that only supports sizes other
4509 than those matching the insn suffix. */
4510 {
40fb9820 4511 i386_operand_type mask, allowed;
d3ce72d0 4512 const insn_template *t;
9cd96992 4513
0dfbf9d7
L		 4514 operand_type_set (&mask, 0);
4515 operand_type_set (&allowed, 0);
40fb9820 4516
4eed87de
AM		 4517 for (t = current_templates->start;
4518 t < current_templates->end;
4519 ++t)
c6fb90c8
L		 4520 allowed = operand_type_or (allowed,
4521 t->operand_types[op]);
9cd96992
JB		 4522 switch (guess_suffix)
4523 {
4524 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4525 mask.bitfield.imm64 = 1;
4526 mask.bitfield.imm32s = 1;
9cd96992
JB		 4527 break;
4528 case LONG_MNEM_SUFFIX:
40fb9820 4529 mask.bitfield.imm32 = 1;
9cd96992
JB		 4530 break;
4531 case WORD_MNEM_SUFFIX:
40fb9820 4532 mask.bitfield.imm16 = 1;
9cd96992
JB		 4533 break;
4534 case BYTE_MNEM_SUFFIX:
40fb9820 4535 mask.bitfield.imm8 = 1;
9cd96992
JB		 4536 break;
4537 default:
9cd96992
JB		 4538 break;
4539 }
c6fb90c8 4540 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4541 if (!operand_type_all_zero (&allowed))
c6fb90c8 4542 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4543 }
29b0f896 4544 break;
252b5132 4545 }
29b0f896
AM		 4546 }
4547}
47926f60 4548
29b0f896
AM		 4549/* Try to use the smallest displacement type too. */
4550static void
e3bb37b5 4551optimize_disp (void)
29b0f896
AM		 4552{
4553 int op;
3e73aa7c 4554
29b0f896 4555 for (op = i.operands; --op >= 0;)
40fb9820 4556 if (operand_type_check (i.types[op], disp))
252b5132 4557 {
b300c311 4558 if (i.op[op].disps->X_op == O_constant)
252b5132 4559 {
91d6fa6a 4560 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4561
40fb9820 4562 if (i.types[op].bitfield.disp16
91d6fa6a 4563 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4564 {
4565 /* If this operand is at most 16 bits, convert
4566 to a signed 16 bit number and don't use 64bit
4567 displacement. */
91d6fa6a 4568 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4569 i.types[op].bitfield.disp64 = 0;
b300c311 4570 }
a28def75
L		 4571#ifdef BFD64
4572 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4573 if (i.types[op].bitfield.disp32
91d6fa6a 4574 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4575 {
4576 /* If this operand is at most 32 bits, convert
4577 to a signed 32 bit number and don't use 64bit
4578 displacement. */
91d6fa6a
NC		 4579 op_disp &= (((offsetT) 2 << 31) - 1);
4580 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4581 i.types[op].bitfield.disp64 = 0;
b300c311 4582 }
a28def75 4583#endif
91d6fa6a 4584 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4585 {
40fb9820
L		 4586 i.types[op].bitfield.disp8 = 0;
4587 i.types[op].bitfield.disp16 = 0;
4588 i.types[op].bitfield.disp32 = 0;
4589 i.types[op].bitfield.disp32s = 0;
4590 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4591 i.op[op].disps = 0;
4592 i.disp_operands--;
4593 }
4594 else if (flag_code == CODE_64BIT)
4595 {
91d6fa6a 4596 if (fits_in_signed_long (op_disp))
28a9d8f5 4597 {
40fb9820
L		 4598 i.types[op].bitfield.disp64 = 0;
4599 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4600 }
0e1147d9 4601 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4602 && fits_in_unsigned_long (op_disp))
40fb9820 4603 i.types[op].bitfield.disp32 = 1;
b300c311 4604 }
40fb9820
L		 4605 if ((i.types[op].bitfield.disp32
4606 || i.types[op].bitfield.disp32s
4607 || i.types[op].bitfield.disp16)
b5014f7a 4608 && fits_in_disp8 (op_disp))
40fb9820 4609 i.types[op].bitfield.disp8 = 1;
252b5132 4610 }
67a4f2b7
AO		 4611 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4612 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4613 {
4614 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4615 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4616 i.types[op].bitfield.disp8 = 0;
4617 i.types[op].bitfield.disp16 = 0;
4618 i.types[op].bitfield.disp32 = 0;
4619 i.types[op].bitfield.disp32s = 0;
4620 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4621 }
4622 else
b300c311 4623 /* We only support 64bit displacement on constants. */
40fb9820 4624 i.types[op].bitfield.disp64 = 0;
252b5132 4625 }
29b0f896
AM		 4626}
4627
6c30d220
L		 4628/* Check if operands are valid for the instruction. */
4629
4630static int
4631check_VecOperands (const insn_template *t)
4632{
43234a1e
L		 4633 unsigned int op;
4634
6c30d220
L		 4635 /* Without VSIB byte, we can't have a vector register for index. */
4636 if (!t->opcode_modifier.vecsib
4637 && i.index_reg
1b54b8d7
JB		 4638 && (i.index_reg->reg_type.bitfield.xmmword
4639 || i.index_reg->reg_type.bitfield.ymmword
4640 || i.index_reg->reg_type.bitfield.zmmword))
6c30d220
L		 4641 {
4642 i.error = unsupported_vector_index_register;
4643 return 1;
4644 }
4645
ad8ecc81
MZ		 4646 /* Check if default mask is allowed. */
4647 if (t->opcode_modifier.nodefmask
4648 && (!i.mask || i.mask->mask->reg_num == 0))
4649 {
4650 i.error = no_default_mask;
4651 return 1;
4652 }
4653
7bab8ab5
JB		 4654 /* For VSIB byte, we need a vector register for index, and all vector
4655 registers must be distinct. */
4656 if (t->opcode_modifier.vecsib)
4657 {
4658 if (!i.index_reg
6c30d220 4659 || !((t->opcode_modifier.vecsib == VecSIB128
1b54b8d7 4660 && i.index_reg->reg_type.bitfield.xmmword)
6c30d220 4661 || (t->opcode_modifier.vecsib == VecSIB256
1b54b8d7 4662 && i.index_reg->reg_type.bitfield.ymmword)
43234a1e 4663 || (t->opcode_modifier.vecsib == VecSIB512
1b54b8d7 4664 && i.index_reg->reg_type.bitfield.zmmword)))
7bab8ab5
JB		 4665 {
4666 i.error = invalid_vsib_address;
4667 return 1;
4668 }
4669
43234a1e
L		 4670 gas_assert (i.reg_operands == 2 || i.mask);
4671 if (i.reg_operands == 2 && !i.mask)
4672 {
1b54b8d7
JB		 4673 gas_assert (i.types[0].bitfield.regsimd);
4674 gas_assert (i.types[0].bitfield.xmmword
4675 || i.types[0].bitfield.ymmword);
4676 gas_assert (i.types[2].bitfield.regsimd);
4677 gas_assert (i.types[2].bitfield.xmmword
4678 || i.types[2].bitfield.ymmword);
43234a1e
L		 4679 if (operand_check == check_none)
4680 return 0;
4681 if (register_number (i.op[0].regs)
4682 != register_number (i.index_reg)
4683 && register_number (i.op[2].regs)
4684 != register_number (i.index_reg)
4685 && register_number (i.op[0].regs)
4686 != register_number (i.op[2].regs))
4687 return 0;
4688 if (operand_check == check_error)
4689 {
4690 i.error = invalid_vector_register_set;
4691 return 1;
4692 }
4693 as_warn (_("mask, index, and destination registers should be distinct"));
4694 }
8444f82a
MZ		 4695 else if (i.reg_operands == 1 && i.mask)
4696 {
1b54b8d7
JB		 4697 if (i.types[1].bitfield.regsimd
4698 && (i.types[1].bitfield.xmmword
4699 || i.types[1].bitfield.ymmword
4700 || i.types[1].bitfield.zmmword)
8444f82a
MZ		 4701 && (register_number (i.op[1].regs)
4702 == register_number (i.index_reg)))
4703 {
4704 if (operand_check == check_error)
4705 {
4706 i.error = invalid_vector_register_set;
4707 return 1;
4708 }
4709 if (operand_check != check_none)
4710 as_warn (_("index and destination registers should be distinct"));
4711 }
4712 }
43234a1e 4713 }
7bab8ab5 4714
43234a1e
L		 4715 /* Check if broadcast is supported by the instruction and is applied
4716 to the memory operand. */
4717 if (i.broadcast)
4718 {
4719 int broadcasted_opnd_size;
4720
4721 /* Check if specified broadcast is supported in this instruction,
4722 and it's applied to memory operand of DWORD or QWORD type,
4723 depending on VecESize. */
4724 if (i.broadcast->type != t->opcode_modifier.broadcast
4725 || !i.types[i.broadcast->operand].bitfield.mem
4726 || (t->opcode_modifier.vecesize == 0
4727 && !i.types[i.broadcast->operand].bitfield.dword
4728 && !i.types[i.broadcast->operand].bitfield.unspecified)
4729 || (t->opcode_modifier.vecesize == 1
4730 && !i.types[i.broadcast->operand].bitfield.qword
4731 && !i.types[i.broadcast->operand].bitfield.unspecified))
4732 goto bad_broadcast;
4733
4734 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4735 if (i.broadcast->type == BROADCAST_1TO16)
4736 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4737 else if (i.broadcast->type == BROADCAST_1TO8)
4738 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4739 else if (i.broadcast->type == BROADCAST_1TO4)
4740 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4741 else if (i.broadcast->type == BROADCAST_1TO2)
4742 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4743 else
4744 goto bad_broadcast;
4745
4746 if ((broadcasted_opnd_size == 256
4747 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4748 || (broadcasted_opnd_size == 512
4749 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4750 {
4751 bad_broadcast:
4752 i.error = unsupported_broadcast;
4753 return 1;
4754 }
4755 }
4756 /* If broadcast is supported in this instruction, we need to check if
4757 operand of one-element size isn't specified without broadcast. */
4758 else if (t->opcode_modifier.broadcast && i.mem_operands)
4759 {
4760 /* Find memory operand. */
4761 for (op = 0; op < i.operands; op++)
4762 if (operand_type_check (i.types[op], anymem))
4763 break;
4764 gas_assert (op < i.operands);
4765 /* Check size of the memory operand. */
4766 if ((t->opcode_modifier.vecesize == 0
4767 && i.types[op].bitfield.dword)
4768 || (t->opcode_modifier.vecesize == 1
4769 && i.types[op].bitfield.qword))
4770 {
4771 i.error = broadcast_needed;
4772 return 1;
4773 }
4774 }
4775
4776 /* Check if requested masking is supported. */
4777 if (i.mask
4778 && (!t->opcode_modifier.masking
4779 || (i.mask->zeroing
4780 && t->opcode_modifier.masking == MERGING_MASKING)))
4781 {
4782 i.error = unsupported_masking;
4783 return 1;
4784 }
4785
4786 /* Check if masking is applied to dest operand. */
4787 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4788 {
4789 i.error = mask_not_on_destination;
4790 return 1;
4791 }
4792
43234a1e
L		 4793 /* Check RC/SAE. */
4794 if (i.rounding)
4795 {
4796 if ((i.rounding->type != saeonly
4797 && !t->opcode_modifier.staticrounding)
4798 || (i.rounding->type == saeonly
4799 && (t->opcode_modifier.staticrounding
4800 || !t->opcode_modifier.sae)))
4801 {
4802 i.error = unsupported_rc_sae;
4803 return 1;
4804 }
4805 /* If the instruction has several immediate operands and one of
4806 them is rounding, the rounding operand should be the last
4807 immediate operand. */
4808 if (i.imm_operands > 1
4809 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4810 {
43234a1e 4811 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4812 return 1;
4813 }
6c30d220
L		 4814 }
4815
43234a1e 4816 /* Check vector Disp8 operand. */
b5014f7a
JB		 4817 if (t->opcode_modifier.disp8memshift
4818 && i.disp_encoding != disp_encoding_32bit)
43234a1e
L		 4819 {
4820 if (i.broadcast)
4821 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4822 else
4823 i.memshift = t->opcode_modifier.disp8memshift;
4824
4825 for (op = 0; op < i.operands; op++)
4826 if (operand_type_check (i.types[op], disp)
4827 && i.op[op].disps->X_op == O_constant)
4828 {
b5014f7a 4829 if (fits_in_disp8 (i.op[op].disps->X_add_number))
43234a1e 4830 {
b5014f7a
JB		 4831 i.types[op].bitfield.disp8 = 1;
4832 return 0;
43234a1e 4833 }
b5014f7a 4834 i.types[op].bitfield.disp8 = 0;
43234a1e
L		 4835 }
4836 }
b5014f7a
JB		 4837
4838 i.memshift = 0;
43234a1e 4839
6c30d220
L		 4840 return 0;
4841}
4842
43f3e2ee 4843/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4844 operand types. */
4845
4846static int
4847VEX_check_operands (const insn_template *t)
4848{
86fa6981 4849 if (i.vec_encoding == vex_encoding_evex)
43234a1e 4850 {
86fa6981
L		 4851 /* This instruction must be encoded with EVEX prefix. */
4852 if (!t->opcode_modifier.evex)
4853 {
4854 i.error = unsupported;
4855 return 1;
4856 }
4857 return 0;
43234a1e
L		 4858 }
4859
a683cc34 4860 if (!t->opcode_modifier.vex)
86fa6981
L		 4861 {
4862 /* This instruction template doesn't have VEX prefix. */
4863 if (i.vec_encoding != vex_encoding_default)
4864 {
4865 i.error = unsupported;
4866 return 1;
4867 }
4868 return 0;
4869 }
a683cc34
SP		 4870
4871 /* Only check VEX_Imm4, which must be the first operand. */
4872 if (t->operand_types[0].bitfield.vec_imm4)
4873 {
4874 if (i.op[0].imms->X_op != O_constant
4875 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4876 {
a65babc9 4877 i.error = bad_imm4;
891edac4
L		 4878 return 1;
4879 }
a683cc34
SP		 4880
4881 /* Turn off Imm8 so that update_imm won't complain. */
4882 i.types[0] = vec_imm4;
4883 }
4884
4885 return 0;
4886}
4887
d3ce72d0 4888static const insn_template *
83b16ac6 4889match_template (char mnem_suffix)
29b0f896
AM		 4890{
4891 /* Points to template once we've found it. */
d3ce72d0 4892 const insn_template *t;
40fb9820 4893 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4894 i386_operand_type overlap4;
29b0f896 4895 unsigned int found_reverse_match;
83b16ac6 4896 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 4897 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4898 int addr_prefix_disp;
a5c311ca 4899 unsigned int j;
3629bb00 4900 unsigned int found_cpu_match;
45664ddb 4901 unsigned int check_register;
5614d22c 4902 enum i386_error specific_error = 0;
29b0f896 4903
c0f3af97
L		 4904#if MAX_OPERANDS != 5
4905# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4906#endif
4907
29b0f896 4908 found_reverse_match = 0;
539e75ad 4909 addr_prefix_disp = -1;
40fb9820
L		 4910
4911 memset (&suffix_check, 0, sizeof (suffix_check));
4912 if (i.suffix == BYTE_MNEM_SUFFIX)
4913 suffix_check.no_bsuf = 1;
4914 else if (i.suffix == WORD_MNEM_SUFFIX)
4915 suffix_check.no_wsuf = 1;
4916 else if (i.suffix == SHORT_MNEM_SUFFIX)
4917 suffix_check.no_ssuf = 1;
4918 else if (i.suffix == LONG_MNEM_SUFFIX)
4919 suffix_check.no_lsuf = 1;
4920 else if (i.suffix == QWORD_MNEM_SUFFIX)
4921 suffix_check.no_qsuf = 1;
4922 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4923 suffix_check.no_ldsuf = 1;
29b0f896 4924
83b16ac6
JB		 4925 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
4926 if (intel_syntax)
4927 {
4928 switch (mnem_suffix)
4929 {
4930 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
4931 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
4932 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
4933 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
4934 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
4935 }
4936 }
4937
01559ecc
L		 4938 /* Must have right number of operands. */
4939 i.error = number_of_operands_mismatch;
4940
45aa61fe 4941 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4942 {
539e75ad
L		 4943 addr_prefix_disp = -1;
4944
29b0f896
AM		 4945 if (i.operands != t->operands)
4946 continue;
4947
50aecf8c 4948 /* Check processor support. */
a65babc9 4949 i.error = unsupported;
c0f3af97
L		 4950 found_cpu_match = (cpu_flags_match (t)
4951 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4952 if (!found_cpu_match)
4953 continue;
4954
e1d4d893 4955 /* Check old gcc support. */
a65babc9 4956 i.error = old_gcc_only;
e1d4d893
L		 4957 if (!old_gcc && t->opcode_modifier.oldgcc)
4958 continue;
4959
4960 /* Check AT&T mnemonic. */
a65babc9 4961 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4962 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4963 continue;
4964
e92bae62 4965 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 4966 i.error = unsupported_syntax;
5c07affc 4967 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 4968 || (!intel_syntax && t->opcode_modifier.intelsyntax)
4969 || (intel64 && t->opcode_modifier.amd64)
4970 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 4971 continue;
4972
20592a94 4973 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4974 i.error = invalid_instruction_suffix;
567e4e96
L		 4975 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4976 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4977 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4978 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4979 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4980 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4981 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 4982 continue;
83b16ac6
JB		 4983 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4984 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
4985 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
4986 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
4987 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
4988 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
4989 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
4990 continue;
29b0f896 4991
5c07affc 4992 if (!operand_size_match (t))
7d5e4556 4993 continue;
539e75ad 4994
5c07affc
L		 4995 for (j = 0; j < MAX_OPERANDS; j++)
4996 operand_types[j] = t->operand_types[j];
4997
45aa61fe
AM		 4998 /* In general, don't allow 64-bit operands in 32-bit mode. */
4999 if (i.suffix == QWORD_MNEM_SUFFIX
5000 && flag_code != CODE_64BIT
5001 && (intel_syntax
40fb9820 5002 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 5003 && !intel_float_operand (t->name))
5004 : intel_float_operand (t->name) != 2)
40fb9820 5005 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5006 && !operand_types[0].bitfield.regsimd)
40fb9820 5007 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5008 && !operand_types[t->operands > 1].bitfield.regsimd))
45aa61fe
AM		 5009 && (t->base_opcode != 0x0fc7
5010 || t->extension_opcode != 1 /* cmpxchg8b */))
5011 continue;
5012
192dc9c6
JB		 5013 /* In general, don't allow 32-bit operands on pre-386. */
5014 else if (i.suffix == LONG_MNEM_SUFFIX
5015 && !cpu_arch_flags.bitfield.cpui386
5016 && (intel_syntax
5017 ? (!t->opcode_modifier.ignoresize
5018 && !intel_float_operand (t->name))
5019 : intel_float_operand (t->name) != 2)
5020 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5021 && !operand_types[0].bitfield.regsimd)
192dc9c6 5022 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5023 && !operand_types[t->operands > 1].bitfield.regsimd)))
192dc9c6
JB		 5024 continue;
5025
29b0f896 5026 /* Do not verify operands when there are none. */
50aecf8c 5027 else
29b0f896 5028 {
c6fb90c8 5029 if (!t->operands)
2dbab7d5
L		 5030 /* We've found a match; break out of loop. */
5031 break;
29b0f896 5032 }
252b5132 5033
539e75ad
L		 5034 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5035 into Disp32/Disp16/Disp32 operand. */
5036 if (i.prefix[ADDR_PREFIX] != 0)
5037 {
40fb9820 5038 /* There should be only one Disp operand. */
539e75ad
L		 5039 switch (flag_code)
5040 {
5041 case CODE_16BIT:
40fb9820
L		 5042 for (j = 0; j < MAX_OPERANDS; j++)
5043 {
5044 if (operand_types[j].bitfield.disp16)
5045 {
5046 addr_prefix_disp = j;
5047 operand_types[j].bitfield.disp32 = 1;
5048 operand_types[j].bitfield.disp16 = 0;
5049 break;
5050 }
5051 }
539e75ad
L		 5052 break;
5053 case CODE_32BIT:
40fb9820
L		 5054 for (j = 0; j < MAX_OPERANDS; j++)
5055 {
5056 if (operand_types[j].bitfield.disp32)
5057 {
5058 addr_prefix_disp = j;
5059 operand_types[j].bitfield.disp32 = 0;
5060 operand_types[j].bitfield.disp16 = 1;
5061 break;
5062 }
5063 }
539e75ad
L		 5064 break;
5065 case CODE_64BIT:
40fb9820
L		 5066 for (j = 0; j < MAX_OPERANDS; j++)
5067 {
5068 if (operand_types[j].bitfield.disp64)
5069 {
5070 addr_prefix_disp = j;
5071 operand_types[j].bitfield.disp64 = 0;
5072 operand_types[j].bitfield.disp32 = 1;
5073 break;
5074 }
5075 }
539e75ad
L		 5076 break;
5077 }
539e75ad
L		 5078 }
5079
02a86693
L		 5080 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5081 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5082 continue;
5083
56ffb741
L		 5084 /* We check register size if needed. */
5085 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 5086 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 5087 switch (t->operands)
5088 {
5089 case 1:
40fb9820 5090 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 5091 continue;
5092 break;
5093 case 2:
33eaf5de 5094 /* xchg %eax, %eax is a special case. It is an alias for nop
8b38ad71
L		 5095 only in 32bit mode and we can use opcode 0x90. In 64bit
5096 mode, we can't use 0x90 for xchg %eax, %eax since it should
5097 zero-extend %eax to %rax. */
5098 if (flag_code == CODE_64BIT
5099 && t->base_opcode == 0x90
0dfbf9d7
L		 5100 && operand_type_equal (&i.types [0], &acc32)
5101 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 5102 continue;
86fa6981
L		 5103 /* If we want store form, we reverse direction of operands. */
5104 if (i.dir_encoding == dir_encoding_store
5105 && t->opcode_modifier.d)
5106 goto check_reverse;
1a0670f3 5107 /* Fall through. */
b6169b20 5108
29b0f896 5109 case 3:
86fa6981
L		 5110 /* If we want store form, we skip the current load. */
5111 if (i.dir_encoding == dir_encoding_store
5112 && i.mem_operands == 0
5113 && t->opcode_modifier.load)
fa99fab2 5114 continue;
1a0670f3 5115 /* Fall through. */
f48ff2ae 5116 case 4:
c0f3af97 5117 case 5:
c6fb90c8 5118 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 5119 if (!operand_type_match (overlap0, i.types[0])
5120 || !operand_type_match (overlap1, i.types[1])
45664ddb 5121 || (check_register
dc821c5f 5122 && !operand_type_register_match (i.types[0],
40fb9820 5123 operand_types[0],
dc821c5f 5124 i.types[1],
40fb9820 5125 operand_types[1])))
29b0f896
AM		 5126 {
5127 /* Check if other direction is valid ... */
40fb9820 5128 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 5129 continue;
5130
b6169b20 5131check_reverse:
29b0f896 5132 /* Try reversing direction of operands. */
c6fb90c8
L		 5133 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5134 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 5135 if (!operand_type_match (overlap0, i.types[0])
5136 || !operand_type_match (overlap1, i.types[1])
45664ddb 5137 || (check_register
dc821c5f 5138 && !operand_type_register_match (i.types[0],
45664ddb 5139 operand_types[1],
45664ddb
L		 5140 i.types[1],
5141 operand_types[0])))
29b0f896
AM		 5142 {
5143 /* Does not match either direction. */
5144 continue;
5145 }
5146 /* found_reverse_match holds which of D or FloatDR
5147 we've found. */
40fb9820 5148 if (t->opcode_modifier.d)
8a2ed489 5149 found_reverse_match = Opcode_D;
40fb9820 5150 else if (t->opcode_modifier.floatd)
8a2ed489
L		 5151 found_reverse_match = Opcode_FloatD;
5152 else
5153 found_reverse_match = 0;
40fb9820 5154 if (t->opcode_modifier.floatr)
8a2ed489 5155 found_reverse_match |= Opcode_FloatR;
29b0f896 5156 }
f48ff2ae 5157 else
29b0f896 5158 {
f48ff2ae 5159 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5160 switch (t->operands)
5161 {
c0f3af97
L		 5162 case 5:
5163 overlap4 = operand_type_and (i.types[4],
5164 operand_types[4]);
1a0670f3 5165 /* Fall through. */
d1cbb4db 5166 case 4:
c6fb90c8
L		 5167 overlap3 = operand_type_and (i.types[3],
5168 operand_types[3]);
1a0670f3 5169 /* Fall through. */
d1cbb4db 5170 case 3:
c6fb90c8
L		 5171 overlap2 = operand_type_and (i.types[2],
5172 operand_types[2]);
d1cbb4db
L		 5173 break;
5174 }
29b0f896 5175
f48ff2ae
L		 5176 switch (t->operands)
5177 {
c0f3af97
L		 5178 case 5:
5179 if (!operand_type_match (overlap4, i.types[4])
dc821c5f 5180 || !operand_type_register_match (i.types[3],
c0f3af97 5181 operand_types[3],
c0f3af97
L		 5182 i.types[4],
5183 operand_types[4]))
5184 continue;
1a0670f3 5185 /* Fall through. */
f48ff2ae 5186 case 4:
40fb9820 5187 if (!operand_type_match (overlap3, i.types[3])
45664ddb 5188 || (check_register
dc821c5f 5189 && !operand_type_register_match (i.types[2],
45664ddb 5190 operand_types[2],
45664ddb
L		 5191 i.types[3],
5192 operand_types[3])))
f48ff2ae 5193 continue;
1a0670f3 5194 /* Fall through. */
f48ff2ae
L		 5195 case 3:
5196 /* Here we make use of the fact that there are no
5197 reverse match 3 operand instructions, and all 3
5198 operand instructions only need to be checked for
5199 register consistency between operands 2 and 3. */
40fb9820 5200 if (!operand_type_match (overlap2, i.types[2])
45664ddb 5201 || (check_register
dc821c5f 5202 && !operand_type_register_match (i.types[1],
45664ddb 5203 operand_types[1],
45664ddb
L		 5204 i.types[2],
5205 operand_types[2])))
f48ff2ae
L		 5206 continue;
5207 break;
5208 }
29b0f896 5209 }
f48ff2ae 5210 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5211 slip through to break. */
5212 }
3629bb00 5213 if (!found_cpu_match)
29b0f896
AM		 5214 {
5215 found_reverse_match = 0;
5216 continue;
5217 }
c0f3af97 5218
5614d22c
JB		 5219 /* Check if vector and VEX operands are valid. */
5220 if (check_VecOperands (t) || VEX_check_operands (t))
5221 {
5222 specific_error = i.error;
5223 continue;
5224 }
a683cc34 5225
29b0f896
AM		 5226 /* We've found a match; break out of loop. */
5227 break;
5228 }
5229
5230 if (t == current_templates->end)
5231 {
5232 /* We found no match. */
a65babc9 5233 const char *err_msg;
5614d22c 5234 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5235 {
5236 default:
5237 abort ();
86e026a4 5238 case operand_size_mismatch:
a65babc9
L		 5239 err_msg = _("operand size mismatch");
5240 break;
5241 case operand_type_mismatch:
5242 err_msg = _("operand type mismatch");
5243 break;
5244 case register_type_mismatch:
5245 err_msg = _("register type mismatch");
5246 break;
5247 case number_of_operands_mismatch:
5248 err_msg = _("number of operands mismatch");
5249 break;
5250 case invalid_instruction_suffix:
5251 err_msg = _("invalid instruction suffix");
5252 break;
5253 case bad_imm4:
4a2608e3 5254 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 5255 break;
5256 case old_gcc_only:
5257 err_msg = _("only supported with old gcc");
5258 break;
5259 case unsupported_with_intel_mnemonic:
5260 err_msg = _("unsupported with Intel mnemonic");
5261 break;
5262 case unsupported_syntax:
5263 err_msg = _("unsupported syntax");
5264 break;
5265 case unsupported:
35262a23 5266 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5267 current_templates->start->name);
5268 return NULL;
6c30d220
L		 5269 case invalid_vsib_address:
5270 err_msg = _("invalid VSIB address");
5271 break;
7bab8ab5
JB		 5272 case invalid_vector_register_set:
5273 err_msg = _("mask, index, and destination registers must be distinct");
5274 break;
6c30d220
L		 5275 case unsupported_vector_index_register:
5276 err_msg = _("unsupported vector index register");
5277 break;
43234a1e
L		 5278 case unsupported_broadcast:
5279 err_msg = _("unsupported broadcast");
5280 break;
5281 case broadcast_not_on_src_operand:
5282 err_msg = _("broadcast not on source memory operand");
5283 break;
5284 case broadcast_needed:
5285 err_msg = _("broadcast is needed for operand of such type");
5286 break;
5287 case unsupported_masking:
5288 err_msg = _("unsupported masking");
5289 break;
5290 case mask_not_on_destination:
5291 err_msg = _("mask not on destination operand");
5292 break;
5293 case no_default_mask:
5294 err_msg = _("default mask isn't allowed");
5295 break;
5296 case unsupported_rc_sae:
5297 err_msg = _("unsupported static rounding/sae");
5298 break;
5299 case rc_sae_operand_not_last_imm:
5300 if (intel_syntax)
5301 err_msg = _("RC/SAE operand must precede immediate operands");
5302 else
5303 err_msg = _("RC/SAE operand must follow immediate operands");
5304 break;
5305 case invalid_register_operand:
5306 err_msg = _("invalid register operand");
5307 break;
a65babc9
L		 5308 }
5309 as_bad (_("%s for `%s'"), err_msg,
891edac4 5310 current_templates->start->name);
fa99fab2 5311 return NULL;
29b0f896 5312 }
252b5132 5313
29b0f896
AM		 5314 if (!quiet_warnings)
5315 {
5316 if (!intel_syntax
40fb9820
L		 5317 && (i.types[0].bitfield.jumpabsolute
5318 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5319 {
5320 as_warn (_("indirect %s without `*'"), t->name);
5321 }
5322
40fb9820
L		 5323 if (t->opcode_modifier.isprefix
5324 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5325 {
5326 /* Warn them that a data or address size prefix doesn't
5327 affect assembly of the next line of code. */
5328 as_warn (_("stand-alone `%s' prefix"), t->name);
5329 }
5330 }
5331
5332 /* Copy the template we found. */
5333 i.tm = *t;
539e75ad
L		 5334
5335 if (addr_prefix_disp != -1)
5336 i.tm.operand_types[addr_prefix_disp]
5337 = operand_types[addr_prefix_disp];
5338
29b0f896
AM		 5339 if (found_reverse_match)
5340 {
5341 /* If we found a reverse match we must alter the opcode
5342 direction bit. found_reverse_match holds bits to change
5343 (different for int & float insns). */
5344
5345 i.tm.base_opcode ^= found_reverse_match;
5346
539e75ad
L		 5347 i.tm.operand_types[0] = operand_types[1];
5348 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5349 }
5350
fa99fab2 5351 return t;
29b0f896
AM		 5352}
5353
5354static int
e3bb37b5 5355check_string (void)
29b0f896 5356{
40fb9820
L		 5357 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5358 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5359 {
5360 if (i.seg[0] != NULL && i.seg[0] != &es)
5361 {
a87af027 5362 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5363 i.tm.name,
a87af027
JB		 5364 mem_op + 1,
5365 register_prefix);
29b0f896
AM		 5366 return 0;
5367 }
5368 /* There's only ever one segment override allowed per instruction.
5369 This instruction possibly has a legal segment override on the
5370 second operand, so copy the segment to where non-string
5371 instructions store it, allowing common code. */
5372 i.seg[0] = i.seg[1];
5373 }
40fb9820 5374 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5375 {
5376 if (i.seg[1] != NULL && i.seg[1] != &es)
5377 {
a87af027 5378 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5379 i.tm.name,
a87af027
JB		 5380 mem_op + 2,
5381 register_prefix);
29b0f896
AM		 5382 return 0;
5383 }
5384 }
5385 return 1;
5386}
5387
5388static int
543613e9 5389process_suffix (void)
29b0f896
AM		 5390{
5391 /* If matched instruction specifies an explicit instruction mnemonic
5392 suffix, use it. */
40fb9820
L		 5393 if (i.tm.opcode_modifier.size16)
5394 i.suffix = WORD_MNEM_SUFFIX;
5395 else if (i.tm.opcode_modifier.size32)
5396 i.suffix = LONG_MNEM_SUFFIX;
5397 else if (i.tm.opcode_modifier.size64)
5398 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5399 else if (i.reg_operands)
5400 {
5401 /* If there's no instruction mnemonic suffix we try to invent one
5402 based on register operands. */
5403 if (!i.suffix)
5404 {
5405 /* We take i.suffix from the last register operand specified,
5406 Destination register type is more significant than source
381d071f
L		 5407 register type. crc32 in SSE4.2 prefers source register
5408 type. */
5409 if (i.tm.base_opcode == 0xf20f38f1)
5410 {
dc821c5f 5411 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
40fb9820 5412 i.suffix = WORD_MNEM_SUFFIX;
dc821c5f 5413 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
40fb9820 5414 i.suffix = LONG_MNEM_SUFFIX;
dc821c5f 5415 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
40fb9820 5416 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5417 }
9344ff29 5418 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5419 {
dc821c5f 5420 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
20592a94
L		 5421 i.suffix = BYTE_MNEM_SUFFIX;
5422 }
381d071f
L		 5423
5424 if (!i.suffix)
5425 {
5426 int op;
5427
20592a94
L		 5428 if (i.tm.base_opcode == 0xf20f38f1
5429 || i.tm.base_opcode == 0xf20f38f0)
5430 {
5431 /* We have to know the operand size for crc32. */
5432 as_bad (_("ambiguous memory operand size for `%s`"),
5433 i.tm.name);
5434 return 0;
5435 }
5436
381d071f 5437 for (op = i.operands; --op >= 0;)
b76bc5d5
JB		 5438 if (!i.tm.operand_types[op].bitfield.inoutportreg
5439 && !i.tm.operand_types[op].bitfield.shiftcount)
381d071f 5440 {
dc821c5f 5441 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
40fb9820
L		 5442 {
5443 i.suffix = BYTE_MNEM_SUFFIX;
5444 break;
5445 }
dc821c5f 5446 if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
40fb9820
L		 5447 {
5448 i.suffix = WORD_MNEM_SUFFIX;
5449 break;
5450 }
dc821c5f 5451 if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
40fb9820
L		 5452 {
5453 i.suffix = LONG_MNEM_SUFFIX;
5454 break;
5455 }
dc821c5f 5456 if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
40fb9820
L		 5457 {
5458 i.suffix = QWORD_MNEM_SUFFIX;
5459 break;
5460 }
381d071f
L		 5461 }
5462 }
29b0f896
AM		 5463 }
5464 else if (i.suffix == BYTE_MNEM_SUFFIX)
5465 {
2eb952a4
L		 5466 if (intel_syntax
5467 && i.tm.opcode_modifier.ignoresize
5468 && i.tm.opcode_modifier.no_bsuf)
5469 i.suffix = 0;
5470 else if (!check_byte_reg ())
29b0f896
AM		 5471 return 0;
5472 }
5473 else if (i.suffix == LONG_MNEM_SUFFIX)
5474 {
2eb952a4
L		 5475 if (intel_syntax
5476 && i.tm.opcode_modifier.ignoresize
5477 && i.tm.opcode_modifier.no_lsuf)
5478 i.suffix = 0;
5479 else if (!check_long_reg ())
29b0f896
AM		 5480 return 0;
5481 }
5482 else if (i.suffix == QWORD_MNEM_SUFFIX)
5483 {
955e1e6a
L		 5484 if (intel_syntax
5485 && i.tm.opcode_modifier.ignoresize
5486 && i.tm.opcode_modifier.no_qsuf)
5487 i.suffix = 0;
5488 else if (!check_qword_reg ())
29b0f896
AM		 5489 return 0;
5490 }
5491 else if (i.suffix == WORD_MNEM_SUFFIX)
5492 {
2eb952a4
L		 5493 if (intel_syntax
5494 && i.tm.opcode_modifier.ignoresize
5495 && i.tm.opcode_modifier.no_wsuf)
5496 i.suffix = 0;
5497 else if (!check_word_reg ())
29b0f896
AM		 5498 return 0;
5499 }
c0f3af97 5500 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5501 || i.suffix == YMMWORD_MNEM_SUFFIX
5502 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5503 {
43234a1e 5504 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5505 should check if it is a valid suffix. */
5506 }
40fb9820 5507 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5508 /* Do nothing if the instruction is going to ignore the prefix. */
5509 ;
5510 else
5511 abort ();
5512 }
40fb9820 5513 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5514 && !i.suffix
5515 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5516 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5517 {
5518 i.suffix = stackop_size;
5519 }
9306ca4a
JB		 5520 else if (intel_syntax
5521 && !i.suffix
40fb9820
L		 5522 && (i.tm.operand_types[0].bitfield.jumpabsolute
5523 || i.tm.opcode_modifier.jumpbyte
5524 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5525 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5526 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5527 {
5528 switch (flag_code)
5529 {
5530 case CODE_64BIT:
40fb9820 5531 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5532 {
5533 i.suffix = QWORD_MNEM_SUFFIX;
5534 break;
5535 }
1a0670f3 5536 /* Fall through. */
9306ca4a 5537 case CODE_32BIT:
40fb9820 5538 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5539 i.suffix = LONG_MNEM_SUFFIX;
5540 break;
5541 case CODE_16BIT:
40fb9820 5542 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5543 i.suffix = WORD_MNEM_SUFFIX;
5544 break;
5545 }
5546 }
252b5132 5547
9306ca4a 5548 if (!i.suffix)
29b0f896 5549 {
9306ca4a
JB		 5550 if (!intel_syntax)
5551 {
40fb9820 5552 if (i.tm.opcode_modifier.w)
9306ca4a 5553 {
4eed87de
AM		 5554 as_bad (_("no instruction mnemonic suffix given and "
5555 "no register operands; can't size instruction"));
9306ca4a
JB		 5556 return 0;
5557 }
5558 }
5559 else
5560 {
40fb9820 5561 unsigned int suffixes;
7ab9ffdd 5562
40fb9820
L		 5563 suffixes = !i.tm.opcode_modifier.no_bsuf;
5564 if (!i.tm.opcode_modifier.no_wsuf)
5565 suffixes |= 1 << 1;
5566 if (!i.tm.opcode_modifier.no_lsuf)
5567 suffixes |= 1 << 2;
fc4adea1 5568 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5569 suffixes |= 1 << 3;
5570 if (!i.tm.opcode_modifier.no_ssuf)
5571 suffixes |= 1 << 4;
c2b9da16 5572 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
40fb9820
L		 5573 suffixes |= 1 << 5;
5574
5575 /* There are more than suffix matches. */
5576 if (i.tm.opcode_modifier.w
9306ca4a 5577 || ((suffixes & (suffixes - 1))
40fb9820
L		 5578 && !i.tm.opcode_modifier.defaultsize
5579 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5580 {
5581 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5582 return 0;
5583 }
5584 }
29b0f896 5585 }
252b5132 5586
9306ca4a
JB		 5587 /* Change the opcode based on the operand size given by i.suffix;
5588 We don't need to change things for byte insns. */
5589
582d5edd
L		 5590 if (i.suffix
5591 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5592 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5593 && i.suffix != YMMWORD_MNEM_SUFFIX
5594 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5595 {
5596 /* It's not a byte, select word/dword operation. */
40fb9820 5597 if (i.tm.opcode_modifier.w)
29b0f896 5598 {
40fb9820 5599 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5600 i.tm.base_opcode |= 8;
5601 else
5602 i.tm.base_opcode |= 1;
5603 }
0f3f3d8b 5604
29b0f896
AM		 5605 /* Now select between word & dword operations via the operand
5606 size prefix, except for instructions that will ignore this
5607 prefix anyway. */
ca61edf2 5608 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5609 {
ca61edf2
L		 5610 /* The address size override prefix changes the size of the
5611 first operand. */
40fb9820 5612 if ((flag_code == CODE_32BIT
dc821c5f 5613 && i.op->regs[0].reg_type.bitfield.word)
40fb9820 5614 || (flag_code != CODE_32BIT
dc821c5f 5615 && i.op->regs[0].reg_type.bitfield.dword))
cb712a9e
L		 5616 if (!add_prefix (ADDR_PREFIX_OPCODE))
5617 return 0;
5618 }
5619 else if (i.suffix != QWORD_MNEM_SUFFIX
5620 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5621 && !i.tm.opcode_modifier.ignoresize
5622 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5623 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5624 || (flag_code == CODE_64BIT
40fb9820 5625 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5626 {
5627 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5628
40fb9820 5629 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5630 prefix = ADDR_PREFIX_OPCODE;
252b5132 5631
29b0f896
AM		 5632 if (!add_prefix (prefix))
5633 return 0;
24eab124 5634 }
252b5132 5635
29b0f896
AM		 5636 /* Set mode64 for an operand. */
5637 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5638 && flag_code == CODE_64BIT
40fb9820 5639 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5640 {
5641 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5642 need rex64. cmpxchg8b is also a special case. */
5643 if (! (i.operands == 2
5644 && i.tm.base_opcode == 0x90
5645 && i.tm.extension_opcode == None
0dfbf9d7
L		 5646 && operand_type_equal (&i.types [0], &acc64)
5647 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5648 && ! (i.operands == 1
5649 && i.tm.base_opcode == 0xfc7
5650 && i.tm.extension_opcode == 1
40fb9820
L		 5651 && !operand_type_check (i.types [0], reg)
5652 && operand_type_check (i.types [0], anymem)))
f6bee062 5653 i.rex |= REX_W;
46e883c5 5654 }
3e73aa7c 5655
29b0f896
AM		 5656 /* Size floating point instruction. */
5657 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5658 if (i.tm.opcode_modifier.floatmf)
543613e9 5659 i.tm.base_opcode ^= 4;
29b0f896 5660 }
7ecd2f8b 5661
29b0f896
AM		 5662 return 1;
5663}
3e73aa7c 5664
29b0f896 5665static int
543613e9 5666check_byte_reg (void)
29b0f896
AM		 5667{
5668 int op;
543613e9 5669
29b0f896
AM		 5670 for (op = i.operands; --op >= 0;)
5671 {
dc821c5f
JB		 5672 /* Skip non-register operands. */
5673 if (!i.types[op].bitfield.reg)
5674 continue;
5675
29b0f896
AM		 5676 /* If this is an eight bit register, it's OK. If it's the 16 or
5677 32 bit version of an eight bit register, we will just use the
5678 low portion, and that's OK too. */
dc821c5f 5679 if (i.types[op].bitfield.byte)
29b0f896
AM		 5680 continue;
5681
5a819eb9
JB		 5682 /* I/O port address operands are OK too. */
5683 if (i.tm.operand_types[op].bitfield.inoutportreg)
5684 continue;
5685
9344ff29
L		 5686 /* crc32 doesn't generate this warning. */
5687 if (i.tm.base_opcode == 0xf20f38f0)
5688 continue;
5689
dc821c5f
JB		 5690 if ((i.types[op].bitfield.word
5691 || i.types[op].bitfield.dword
5692 || i.types[op].bitfield.qword)
5a819eb9
JB		 5693 && i.op[op].regs->reg_num < 4
5694 /* Prohibit these changes in 64bit mode, since the lowering
5695 would be more complicated. */
5696 && flag_code != CODE_64BIT)
29b0f896 5697 {
29b0f896 5698#if REGISTER_WARNINGS
5a819eb9 5699 if (!quiet_warnings)
a540244d
L		 5700 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5701 register_prefix,
dc821c5f 5702 (i.op[op].regs + (i.types[op].bitfield.word
29b0f896
AM		 5703 ? REGNAM_AL - REGNAM_AX
5704 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5705 register_prefix,
29b0f896
AM		 5706 i.op[op].regs->reg_name,
5707 i.suffix);
5708#endif
5709 continue;
5710 }
5711 /* Any other register is bad. */
dc821c5f 5712 if (i.types[op].bitfield.reg
40fb9820 5713 || i.types[op].bitfield.regmmx
1b54b8d7 5714 || i.types[op].bitfield.regsimd
40fb9820
L		 5715 || i.types[op].bitfield.sreg2
5716 || i.types[op].bitfield.sreg3
5717 || i.types[op].bitfield.control
5718 || i.types[op].bitfield.debug
ca0d63fe 5719 || i.types[op].bitfield.test)
29b0f896 5720 {
a540244d
L		 5721 as_bad (_("`%s%s' not allowed with `%s%c'"),
5722 register_prefix,
29b0f896
AM		 5723 i.op[op].regs->reg_name,
5724 i.tm.name,
5725 i.suffix);
5726 return 0;
5727 }
5728 }
5729 return 1;
5730}
5731
5732static int
e3bb37b5 5733check_long_reg (void)
29b0f896
AM		 5734{
5735 int op;
5736
5737 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 5738 /* Skip non-register operands. */
5739 if (!i.types[op].bitfield.reg)
5740 continue;
29b0f896
AM		 5741 /* Reject eight bit registers, except where the template requires
5742 them. (eg. movzb) */
dc821c5f
JB		 5743 else if (i.types[op].bitfield.byte
5744 && (i.tm.operand_types[op].bitfield.reg
5745 || i.tm.operand_types[op].bitfield.acc)
5746 && (i.tm.operand_types[op].bitfield.word
5747 || i.tm.operand_types[op].bitfield.dword))
29b0f896 5748 {
a540244d
L		 5749 as_bad (_("`%s%s' not allowed with `%s%c'"),
5750 register_prefix,
29b0f896
AM		 5751 i.op[op].regs->reg_name,
5752 i.tm.name,
5753 i.suffix);
5754 return 0;
5755 }
e4630f71 5756 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5757 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 5758 && i.types[op].bitfield.word
5759 && (i.tm.operand_types[op].bitfield.reg
5760 || i.tm.operand_types[op].bitfield.acc)
5761 && i.tm.operand_types[op].bitfield.dword)
29b0f896
AM		 5762 {
5763 /* Prohibit these changes in the 64bit mode, since the
5764 lowering is more complicated. */
5765 if (flag_code == CODE_64BIT)
252b5132 5766 {
2b5d6a91 5767 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5768 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5769 i.suffix);
5770 return 0;
252b5132 5771 }
29b0f896 5772#if REGISTER_WARNINGS
cecf1424
JB		 5773 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5774 register_prefix,
5775 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5776 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5777#endif
252b5132 5778 }
e4630f71 5779 /* Warn if the r prefix on a general reg is present. */
dc821c5f
JB		 5780 else if (i.types[op].bitfield.qword
5781 && (i.tm.operand_types[op].bitfield.reg
5782 || i.tm.operand_types[op].bitfield.acc)
5783 && i.tm.operand_types[op].bitfield.dword)
252b5132 5784 {
34828aad 5785 if (intel_syntax
ca61edf2 5786 && i.tm.opcode_modifier.toqword
1b54b8d7 5787 && !i.types[0].bitfield.regsimd)
34828aad 5788 {
ca61edf2 5789 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5790 i.suffix = QWORD_MNEM_SUFFIX;
5791 }
5792 else
5793 {
2b5d6a91 5794 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5795 register_prefix, i.op[op].regs->reg_name,
5796 i.suffix);
5797 return 0;
5798 }
29b0f896
AM		 5799 }
5800 return 1;
5801}
252b5132 5802
29b0f896 5803static int
e3bb37b5 5804check_qword_reg (void)
29b0f896
AM		 5805{
5806 int op;
252b5132 5807
29b0f896 5808 for (op = i.operands; --op >= 0; )
dc821c5f
JB		 5809 /* Skip non-register operands. */
5810 if (!i.types[op].bitfield.reg)
5811 continue;
29b0f896
AM		 5812 /* Reject eight bit registers, except where the template requires
5813 them. (eg. movzb) */
dc821c5f
JB		 5814 else if (i.types[op].bitfield.byte
5815 && (i.tm.operand_types[op].bitfield.reg
5816 || i.tm.operand_types[op].bitfield.acc)
5817 && (i.tm.operand_types[op].bitfield.word
5818 || i.tm.operand_types[op].bitfield.dword))
29b0f896 5819 {
a540244d
L		 5820 as_bad (_("`%s%s' not allowed with `%s%c'"),
5821 register_prefix,
29b0f896
AM		 5822 i.op[op].regs->reg_name,
5823 i.tm.name,
5824 i.suffix);
5825 return 0;
5826 }
e4630f71 5827 /* Warn if the r prefix on a general reg is missing. */
dc821c5f
JB		 5828 else if ((i.types[op].bitfield.word
5829 || i.types[op].bitfield.dword)
5830 && (i.tm.operand_types[op].bitfield.reg
5831 || i.tm.operand_types[op].bitfield.acc)
5832 && i.tm.operand_types[op].bitfield.qword)
29b0f896
AM		 5833 {
5834 /* Prohibit these changes in the 64bit mode, since the
5835 lowering is more complicated. */
34828aad 5836 if (intel_syntax
ca61edf2 5837 && i.tm.opcode_modifier.todword
1b54b8d7 5838 && !i.types[0].bitfield.regsimd)
34828aad 5839 {
ca61edf2 5840 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5841 i.suffix = LONG_MNEM_SUFFIX;
5842 }
5843 else
5844 {
2b5d6a91 5845 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5846 register_prefix, i.op[op].regs->reg_name,
5847 i.suffix);
5848 return 0;
5849 }
252b5132 5850 }
29b0f896
AM		 5851 return 1;
5852}
252b5132 5853
29b0f896 5854static int
e3bb37b5 5855check_word_reg (void)
29b0f896
AM		 5856{
5857 int op;
5858 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 5859 /* Skip non-register operands. */
5860 if (!i.types[op].bitfield.reg)
5861 continue;
29b0f896
AM		 5862 /* Reject eight bit registers, except where the template requires
5863 them. (eg. movzb) */
dc821c5f
JB		 5864 else if (i.types[op].bitfield.byte
5865 && (i.tm.operand_types[op].bitfield.reg
5866 || i.tm.operand_types[op].bitfield.acc)
5867 && (i.tm.operand_types[op].bitfield.word
5868 || i.tm.operand_types[op].bitfield.dword))
29b0f896 5869 {
a540244d
L		 5870 as_bad (_("`%s%s' not allowed with `%s%c'"),
5871 register_prefix,
29b0f896
AM		 5872 i.op[op].regs->reg_name,
5873 i.tm.name,
5874 i.suffix);
5875 return 0;
5876 }
e4630f71 5877 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5878 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 5879 && (i.types[op].bitfield.dword
5880 || i.types[op].bitfield.qword)
5881 && (i.tm.operand_types[op].bitfield.reg
5882 || i.tm.operand_types[op].bitfield.acc)
5883 && i.tm.operand_types[op].bitfield.word)
252b5132 5884 {
29b0f896
AM		 5885 /* Prohibit these changes in the 64bit mode, since the
5886 lowering is more complicated. */
5887 if (flag_code == CODE_64BIT)
252b5132 5888 {
2b5d6a91 5889 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5890 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5891 i.suffix);
5892 return 0;
252b5132 5893 }
29b0f896 5894#if REGISTER_WARNINGS
cecf1424
JB		 5895 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5896 register_prefix,
5897 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5898 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5899#endif
5900 }
5901 return 1;
5902}
252b5132 5903
29b0f896 5904static int
40fb9820 5905update_imm (unsigned int j)
29b0f896 5906{
bc0844ae 5907 i386_operand_type overlap = i.types[j];
40fb9820
L		 5908 if ((overlap.bitfield.imm8
5909 || overlap.bitfield.imm8s
5910 || overlap.bitfield.imm16
5911 || overlap.bitfield.imm32
5912 || overlap.bitfield.imm32s
5913 || overlap.bitfield.imm64)
0dfbf9d7
L		 5914 && !operand_type_equal (&overlap, &imm8)
5915 && !operand_type_equal (&overlap, &imm8s)
5916 && !operand_type_equal (&overlap, &imm16)
5917 && !operand_type_equal (&overlap, &imm32)
5918 && !operand_type_equal (&overlap, &imm32s)
5919 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5920 {
5921 if (i.suffix)
5922 {
40fb9820
L		 5923 i386_operand_type temp;
5924
0dfbf9d7 5925 operand_type_set (&temp, 0);
7ab9ffdd 5926 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5927 {
5928 temp.bitfield.imm8 = overlap.bitfield.imm8;
5929 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5930 }
5931 else if (i.suffix == WORD_MNEM_SUFFIX)
5932 temp.bitfield.imm16 = overlap.bitfield.imm16;
5933 else if (i.suffix == QWORD_MNEM_SUFFIX)
5934 {
5935 temp.bitfield.imm64 = overlap.bitfield.imm64;
5936 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5937 }
5938 else
5939 temp.bitfield.imm32 = overlap.bitfield.imm32;
5940 overlap = temp;
29b0f896 5941 }
0dfbf9d7
L		 5942 else if (operand_type_equal (&overlap, &imm16_32_32s)
5943 || operand_type_equal (&overlap, &imm16_32)
5944 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5945 {
40fb9820 5946 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5947 overlap = imm16;
40fb9820 5948 else
65da13b5 5949 overlap = imm32s;
29b0f896 5950 }
0dfbf9d7
L		 5951 if (!operand_type_equal (&overlap, &imm8)
5952 && !operand_type_equal (&overlap, &imm8s)
5953 && !operand_type_equal (&overlap, &imm16)
5954 && !operand_type_equal (&overlap, &imm32)
5955 && !operand_type_equal (&overlap, &imm32s)
5956 && !operand_type_equal (&overlap, &imm64))
29b0f896 5957 {
4eed87de
AM		 5958 as_bad (_("no instruction mnemonic suffix given; "
5959 "can't determine immediate size"));
29b0f896
AM		 5960 return 0;
5961 }
5962 }
40fb9820 5963 i.types[j] = overlap;
29b0f896 5964
40fb9820
L		 5965 return 1;
5966}
5967
5968static int
5969finalize_imm (void)
5970{
bc0844ae 5971 unsigned int j, n;
29b0f896 5972
bc0844ae
L		 5973 /* Update the first 2 immediate operands. */
5974 n = i.operands > 2 ? 2 : i.operands;
5975 if (n)
5976 {
5977 for (j = 0; j < n; j++)
5978 if (update_imm (j) == 0)
5979 return 0;
40fb9820 5980
bc0844ae
L		 5981 /* The 3rd operand can't be immediate operand. */
5982 gas_assert (operand_type_check (i.types[2], imm) == 0);
5983 }
29b0f896
AM		 5984
5985 return 1;
5986}
5987
5988static int
e3bb37b5 5989process_operands (void)
29b0f896
AM		 5990{
5991 /* Default segment register this instruction will use for memory
5992 accesses. 0 means unknown. This is only for optimizing out
5993 unnecessary segment overrides. */
5994 const seg_entry *default_seg = 0;
5995
2426c15f 5996 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5997 {
91d6fa6a
NC		 5998 unsigned int dupl = i.operands;
5999 unsigned int dest = dupl - 1;
9fcfb3d7
L		 6000 unsigned int j;
6001
c0f3af97 6002 /* The destination must be an xmm register. */
9c2799c2 6003 gas_assert (i.reg_operands
91d6fa6a 6004 && MAX_OPERANDS > dupl
7ab9ffdd 6005 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97 6006
1b54b8d7
JB		 6007 if (i.tm.operand_types[0].bitfield.acc
6008 && i.tm.operand_types[0].bitfield.xmmword)
e2ec9d29 6009 {
8cd7925b 6010 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 6011 {
6012 /* Keep xmm0 for instructions with VEX prefix and 3
6013 sources. */
1b54b8d7
JB		 6014 i.tm.operand_types[0].bitfield.acc = 0;
6015 i.tm.operand_types[0].bitfield.regsimd = 1;
c0f3af97
L		 6016 goto duplicate;
6017 }
e2ec9d29 6018 else
c0f3af97
L		 6019 {
6020 /* We remove the first xmm0 and keep the number of
6021 operands unchanged, which in fact duplicates the
6022 destination. */
6023 for (j = 1; j < i.operands; j++)
6024 {
6025 i.op[j - 1] = i.op[j];
6026 i.types[j - 1] = i.types[j];
6027 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6028 }
6029 }
6030 }
6031 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 6032 {
91d6fa6a 6033 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 6034 && (i.tm.opcode_modifier.vexsources
6035 == VEX3SOURCES));
c0f3af97
L		 6036
6037 /* Add the implicit xmm0 for instructions with VEX prefix
6038 and 3 sources. */
6039 for (j = i.operands; j > 0; j--)
6040 {
6041 i.op[j] = i.op[j - 1];
6042 i.types[j] = i.types[j - 1];
6043 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6044 }
6045 i.op[0].regs
6046 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 6047 i.types[0] = regxmm;
c0f3af97
L		 6048 i.tm.operand_types[0] = regxmm;
6049
6050 i.operands += 2;
6051 i.reg_operands += 2;
6052 i.tm.operands += 2;
6053
91d6fa6a 6054 dupl++;
c0f3af97 6055 dest++;
91d6fa6a
NC		 6056 i.op[dupl] = i.op[dest];
6057 i.types[dupl] = i.types[dest];
6058 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 6059 }
c0f3af97
L		 6060 else
6061 {
6062duplicate:
6063 i.operands++;
6064 i.reg_operands++;
6065 i.tm.operands++;
6066
91d6fa6a
NC		 6067 i.op[dupl] = i.op[dest];
6068 i.types[dupl] = i.types[dest];
6069 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 6070 }
6071
6072 if (i.tm.opcode_modifier.immext)
6073 process_immext ();
6074 }
1b54b8d7
JB		 6075 else if (i.tm.operand_types[0].bitfield.acc
6076 && i.tm.operand_types[0].bitfield.xmmword)
c0f3af97
L		 6077 {
6078 unsigned int j;
6079
9fcfb3d7
L		 6080 for (j = 1; j < i.operands; j++)
6081 {
6082 i.op[j - 1] = i.op[j];
6083 i.types[j - 1] = i.types[j];
6084
6085 /* We need to adjust fields in i.tm since they are used by
6086 build_modrm_byte. */
6087 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6088 }
6089
e2ec9d29
L		 6090 i.operands--;
6091 i.reg_operands--;
e2ec9d29
L		 6092 i.tm.operands--;
6093 }
920d2ddc
IT		 6094 else if (i.tm.opcode_modifier.implicitquadgroup)
6095 {
6096 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
10c17abd 6097 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
920d2ddc
IT		 6098 unsigned int regnum = register_number (i.op[1].regs);
6099 unsigned int first_reg_in_group = regnum & ~3;
6100 unsigned int last_reg_in_group = first_reg_in_group + 3;
6101 if (regnum != first_reg_in_group) {
6102 as_warn (_("the second source register `%s%s' implicitly denotes"
6103 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
6104 register_prefix, i.op[1].regs->reg_name,
6105 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6106 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6107 i.tm.name);
6108 }
6109 }
e2ec9d29
L		 6110 else if (i.tm.opcode_modifier.regkludge)
6111 {
6112 /* The imul $imm, %reg instruction is converted into
6113 imul $imm, %reg, %reg, and the clr %reg instruction
6114 is converted into xor %reg, %reg. */
6115
6116 unsigned int first_reg_op;
6117
6118 if (operand_type_check (i.types[0], reg))
6119 first_reg_op = 0;
6120 else
6121 first_reg_op = 1;
6122 /* Pretend we saw the extra register operand. */
9c2799c2 6123 gas_assert (i.reg_operands == 1
7ab9ffdd 6124 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 6125 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6126 i.types[first_reg_op + 1] = i.types[first_reg_op];
6127 i.operands++;
6128 i.reg_operands++;
29b0f896
AM		 6129 }
6130
40fb9820 6131 if (i.tm.opcode_modifier.shortform)
29b0f896 6132 {
40fb9820
L		 6133 if (i.types[0].bitfield.sreg2
6134 || i.types[0].bitfield.sreg3)
29b0f896 6135 {
4eed87de
AM		 6136 if (i.tm.base_opcode == POP_SEG_SHORT
6137 && i.op[0].regs->reg_num == 1)
29b0f896 6138 {
a87af027 6139 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6140 return 0;
29b0f896 6141 }
4eed87de
AM		 6142 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6143 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6144 i.rex |= REX_B;
4eed87de
AM		 6145 }
6146 else
6147 {
7ab9ffdd 6148 /* The register or float register operand is in operand
85f10a01 6149 0 or 1. */
40fb9820 6150 unsigned int op;
7ab9ffdd 6151
ca0d63fe 6152 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
7ab9ffdd
L		 6153 || operand_type_check (i.types[0], reg))
6154 op = 0;
6155 else
6156 op = 1;
4eed87de
AM		 6157 /* Register goes in low 3 bits of opcode. */
6158 i.tm.base_opcode |= i.op[op].regs->reg_num;
6159 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6160 i.rex |= REX_B;
40fb9820 6161 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6162 {
4eed87de
AM		 6163 /* Warn about some common errors, but press on regardless.
6164 The first case can be generated by gcc (<= 2.8.1). */
6165 if (i.operands == 2)
6166 {
6167 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6168 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6169 register_prefix, i.op[!intel_syntax].regs->reg_name,
6170 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6171 }
6172 else
6173 {
6174 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6175 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6176 register_prefix, i.op[0].regs->reg_name);
4eed87de 6177 }
29b0f896
AM		 6178 }
6179 }
6180 }
40fb9820 6181 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6182 {
6183 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6184 must be put into the modrm byte). Now, we make the modrm and
6185 index base bytes based on all the info we've collected. */
29b0f896
AM		 6186
6187 default_seg = build_modrm_byte ();
6188 }
8a2ed489 6189 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6190 {
6191 default_seg = &ds;
6192 }
40fb9820 6193 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6194 {
6195 /* For the string instructions that allow a segment override
6196 on one of their operands, the default segment is ds. */
6197 default_seg = &ds;
6198 }
6199
75178d9d
L		 6200 if (i.tm.base_opcode == 0x8d /* lea */
6201 && i.seg[0]
6202 && !quiet_warnings)
30123838 6203 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6204
6205 /* If a segment was explicitly specified, and the specified segment
6206 is not the default, use an opcode prefix to select it. If we
6207 never figured out what the default segment is, then default_seg
6208 will be zero at this point, and the specified segment prefix will
6209 always be used. */
29b0f896
AM		 6210 if ((i.seg[0]) && (i.seg[0] != default_seg))
6211 {
6212 if (!add_prefix (i.seg[0]->seg_prefix))
6213 return 0;
6214 }
6215 return 1;
6216}
6217
6218static const seg_entry *
e3bb37b5 6219build_modrm_byte (void)
29b0f896
AM		 6220{
6221 const seg_entry *default_seg = 0;
c0f3af97 6222 unsigned int source, dest;
8cd7925b 6223 int vex_3_sources;
c0f3af97
L		 6224
6225 /* The first operand of instructions with VEX prefix and 3 sources
6226 must be VEX_Imm4. */
8cd7925b 6227 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6228 if (vex_3_sources)
6229 {
91d6fa6a 6230 unsigned int nds, reg_slot;
4c2c6516 6231 expressionS *exp;
c0f3af97 6232
922d8de8 6233 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 6234 && i.tm.opcode_modifier.immext)
6235 {
6236 dest = i.operands - 2;
6237 gas_assert (dest == 3);
6238 }
922d8de8 6239 else
a683cc34 6240 dest = i.operands - 1;
c0f3af97 6241 nds = dest - 1;
922d8de8 6242
a683cc34
SP		 6243 /* There are 2 kinds of instructions:
6244 1. 5 operands: 4 register operands or 3 register operands
6245 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 6246 VexW0 or VexW1. The destination must be either XMM, YMM or
6247 ZMM register.
a683cc34
SP		 6248 2. 4 operands: 4 register operands or 3 register operands
6249 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 6250 gas_assert ((i.reg_operands == 4
a683cc34
SP		 6251 || (i.reg_operands == 3 && i.mem_operands == 1))
6252 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6253 && (i.tm.opcode_modifier.veximmext
6254 || (i.imm_operands == 1
6255 && i.types[0].bitfield.vec_imm4
6256 && (i.tm.opcode_modifier.vexw == VEXW0
6257 || i.tm.opcode_modifier.vexw == VEXW1)
10c17abd 6258 && i.tm.operand_types[dest].bitfield.regsimd)));
a683cc34
SP		 6259
6260 if (i.imm_operands == 0)
6261 {
6262 /* When there is no immediate operand, generate an 8bit
6263 immediate operand to encode the first operand. */
6264 exp = &im_expressions[i.imm_operands++];
6265 i.op[i.operands].imms = exp;
6266 i.types[i.operands] = imm8;
6267 i.operands++;
6268 /* If VexW1 is set, the first operand is the source and
6269 the second operand is encoded in the immediate operand. */
6270 if (i.tm.opcode_modifier.vexw == VEXW1)
6271 {
6272 source = 0;
6273 reg_slot = 1;
6274 }
6275 else
6276 {
6277 source = 1;
6278 reg_slot = 0;
6279 }
6280
6281 /* FMA swaps REG and NDS. */
6282 if (i.tm.cpu_flags.bitfield.cpufma)
6283 {
6284 unsigned int tmp;
6285 tmp = reg_slot;
6286 reg_slot = nds;
6287 nds = tmp;
6288 }
6289
10c17abd 6290 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
a683cc34 6291 exp->X_op = O_constant;
4c692bc7 6292 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6293 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6294 }
922d8de8 6295 else
a683cc34
SP		 6296 {
6297 unsigned int imm_slot;
6298
6299 if (i.tm.opcode_modifier.vexw == VEXW0)
6300 {
6301 /* If VexW0 is set, the third operand is the source and
6302 the second operand is encoded in the immediate
6303 operand. */
6304 source = 2;
6305 reg_slot = 1;
6306 }
6307 else
6308 {
6309 /* VexW1 is set, the second operand is the source and
6310 the third operand is encoded in the immediate
6311 operand. */
6312 source = 1;
6313 reg_slot = 2;
6314 }
6315
6316 if (i.tm.opcode_modifier.immext)
6317 {
33eaf5de 6318 /* When ImmExt is set, the immediate byte is the last
a683cc34
SP		 6319 operand. */
6320 imm_slot = i.operands - 1;
6321 source--;
6322 reg_slot--;
6323 }
6324 else
6325 {
6326 imm_slot = 0;
6327
6328 /* Turn on Imm8 so that output_imm will generate it. */
6329 i.types[imm_slot].bitfield.imm8 = 1;
6330 }
6331
10c17abd 6332 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
a683cc34 6333 i.op[imm_slot].imms->X_add_number
4c692bc7 6334 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6335 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6336 }
6337
10c17abd 6338 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
dae39acc 6339 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6340 }
6341 else
6342 source = dest = 0;
29b0f896
AM		 6343
6344 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6345 implicit registers do not count. If there are 3 register
6346 operands, it must be a instruction with VexNDS. For a
6347 instruction with VexNDD, the destination register is encoded
6348 in VEX prefix. If there are 4 register operands, it must be
6349 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6350 if (i.mem_operands == 0
6351 && ((i.reg_operands == 2
2426c15f 6352 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6353 || (i.reg_operands == 3
2426c15f 6354 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6355 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6356 {
cab737b9
L		 6357 switch (i.operands)
6358 {
6359 case 2:
6360 source = 0;
6361 break;
6362 case 3:
c81128dc
L		 6363 /* When there are 3 operands, one of them may be immediate,
6364 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6365 the first operand must be shift count register (cl) or it
6366 is an instruction with VexNDS. */
9c2799c2 6367 gas_assert (i.imm_operands == 1
7ab9ffdd 6368 || (i.imm_operands == 0
2426c15f 6369 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6370 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6371 if (operand_type_check (i.types[0], imm)
6372 || i.types[0].bitfield.shiftcount)
6373 source = 1;
6374 else
6375 source = 0;
cab737b9
L		 6376 break;
6377 case 4:
368d64cc
L		 6378 /* When there are 4 operands, the first two must be 8bit
6379 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6380 one.
6381
6382 For instructions with VexNDS, if the first operand
6383 an imm8, the source operand is the 2nd one. If the last
6384 operand is imm8, the source operand is the first one. */
9c2799c2 6385 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6386 && i.types[0].bitfield.imm8
6387 && i.types[1].bitfield.imm8)
2426c15f 6388 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6389 && i.imm_operands == 1
6390 && (i.types[0].bitfield.imm8
43234a1e
L		 6391 || i.types[i.operands - 1].bitfield.imm8
6392 || i.rounding)));
9f2670f2
L		 6393 if (i.imm_operands == 2)
6394 source = 2;
6395 else
c0f3af97
L		 6396 {
6397 if (i.types[0].bitfield.imm8)
6398 source = 1;
6399 else
6400 source = 0;
6401 }
c0f3af97
L		 6402 break;
6403 case 5:
43234a1e
L		 6404 if (i.tm.opcode_modifier.evex)
6405 {
6406 /* For EVEX instructions, when there are 5 operands, the
6407 first one must be immediate operand. If the second one
6408 is immediate operand, the source operand is the 3th
6409 one. If the last one is immediate operand, the source
6410 operand is the 2nd one. */
6411 gas_assert (i.imm_operands == 2
6412 && i.tm.opcode_modifier.sae
6413 && operand_type_check (i.types[0], imm));
6414 if (operand_type_check (i.types[1], imm))
6415 source = 2;
6416 else if (operand_type_check (i.types[4], imm))
6417 source = 1;
6418 else
6419 abort ();
6420 }
cab737b9
L		 6421 break;
6422 default:
6423 abort ();
6424 }
6425
c0f3af97
L		 6426 if (!vex_3_sources)
6427 {
6428 dest = source + 1;
6429
43234a1e
L		 6430 /* RC/SAE operand could be between DEST and SRC. That happens
6431 when one operand is GPR and the other one is XMM/YMM/ZMM
6432 register. */
6433 if (i.rounding && i.rounding->operand == (int) dest)
6434 dest++;
6435
2426c15f 6436 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6437 {
43234a1e 6438 /* For instructions with VexNDS, the register-only source
c5d0745b 6439 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
43234a1e
L		 6440 register. It is encoded in VEX prefix. We need to
6441 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6442
6443 i386_operand_type op;
6444 unsigned int vvvv;
6445
6446 /* Check register-only source operand when two source
6447 operands are swapped. */
6448 if (!i.tm.operand_types[source].bitfield.baseindex
6449 && i.tm.operand_types[dest].bitfield.baseindex)
6450 {
6451 vvvv = source;
6452 source = dest;
6453 }
6454 else
6455 vvvv = dest;
6456
6457 op = i.tm.operand_types[vvvv];
fa99fab2 6458 op.bitfield.regmem = 0;
c0f3af97 6459 if ((dest + 1) >= i.operands
dc821c5f
JB		 6460 || ((!op.bitfield.reg
6461 || (!op.bitfield.dword && !op.bitfield.qword))
10c17abd 6462 && !op.bitfield.regsimd
43234a1e 6463 && !operand_type_equal (&op, &regmask)))
c0f3af97 6464 abort ();
f12dc422 6465 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6466 dest++;
6467 }
6468 }
29b0f896
AM		 6469
6470 i.rm.mode = 3;
6471 /* One of the register operands will be encoded in the i.tm.reg
6472 field, the other in the combined i.tm.mode and i.tm.regmem
6473 fields. If no form of this instruction supports a memory
6474 destination operand, then we assume the source operand may
6475 sometimes be a memory operand and so we need to store the
6476 destination in the i.rm.reg field. */
40fb9820
L		 6477 if (!i.tm.operand_types[dest].bitfield.regmem
6478 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6479 {
6480 i.rm.reg = i.op[dest].regs->reg_num;
6481 i.rm.regmem = i.op[source].regs->reg_num;
6482 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6483 i.rex |= REX_R;
43234a1e
L		 6484 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6485 i.vrex |= REX_R;
29b0f896 6486 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6487 i.rex |= REX_B;
43234a1e
L		 6488 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6489 i.vrex |= REX_B;
29b0f896
AM		 6490 }
6491 else
6492 {
6493 i.rm.reg = i.op[source].regs->reg_num;
6494 i.rm.regmem = i.op[dest].regs->reg_num;
6495 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6496 i.rex |= REX_B;
43234a1e
L		 6497 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6498 i.vrex |= REX_B;
29b0f896 6499 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6500 i.rex |= REX_R;
43234a1e
L		 6501 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6502 i.vrex |= REX_R;
29b0f896 6503 }
161a04f6 6504 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6505 {
40fb9820
L		 6506 if (!i.types[0].bitfield.control
6507 && !i.types[1].bitfield.control)
c4a530c5 6508 abort ();
161a04f6 6509 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6510 add_prefix (LOCK_PREFIX_OPCODE);
6511 }
29b0f896
AM		 6512 }
6513 else
6514 { /* If it's not 2 reg operands... */
c0f3af97
L		 6515 unsigned int mem;
6516
29b0f896
AM		 6517 if (i.mem_operands)
6518 {
6519 unsigned int fake_zero_displacement = 0;
99018f42 6520 unsigned int op;
4eed87de 6521
7ab9ffdd
L		 6522 for (op = 0; op < i.operands; op++)
6523 if (operand_type_check (i.types[op], anymem))
6524 break;
7ab9ffdd 6525 gas_assert (op < i.operands);
29b0f896 6526
6c30d220
L		 6527 if (i.tm.opcode_modifier.vecsib)
6528 {
6529 if (i.index_reg->reg_num == RegEiz
6530 || i.index_reg->reg_num == RegRiz)
6531 abort ();
6532
6533 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6534 if (!i.base_reg)
6535 {
6536 i.sib.base = NO_BASE_REGISTER;
6537 i.sib.scale = i.log2_scale_factor;
6538 i.types[op].bitfield.disp8 = 0;
6539 i.types[op].bitfield.disp16 = 0;
6540 i.types[op].bitfield.disp64 = 0;
43083a50 6541 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6c30d220
L		 6542 {
6543 /* Must be 32 bit */
6544 i.types[op].bitfield.disp32 = 1;
6545 i.types[op].bitfield.disp32s = 0;
6546 }
6547 else
6548 {
6549 i.types[op].bitfield.disp32 = 0;
6550 i.types[op].bitfield.disp32s = 1;
6551 }
6552 }
6553 i.sib.index = i.index_reg->reg_num;
6554 if ((i.index_reg->reg_flags & RegRex) != 0)
6555 i.rex |= REX_X;
43234a1e
L		 6556 if ((i.index_reg->reg_flags & RegVRex) != 0)
6557 i.vrex |= REX_X;
6c30d220
L		 6558 }
6559
29b0f896
AM		 6560 default_seg = &ds;
6561
6562 if (i.base_reg == 0)
6563 {
6564 i.rm.mode = 0;
6565 if (!i.disp_operands)
9bb129e8 6566 fake_zero_displacement = 1;
29b0f896
AM		 6567 if (i.index_reg == 0)
6568 {
6c30d220 6569 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6570 /* Operand is just <disp> */
20f0a1fc 6571 if (flag_code == CODE_64BIT)
29b0f896
AM		 6572 {
6573 /* 64bit mode overwrites the 32bit absolute
6574 addressing by RIP relative addressing and
6575 absolute addressing is encoded by one of the
6576 redundant SIB forms. */
6577 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6578 i.sib.base = NO_BASE_REGISTER;
6579 i.sib.index = NO_INDEX_REGISTER;
fc225355 6580 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6581 ? disp32s : disp32);
20f0a1fc 6582 }
fc225355
L		 6583 else if ((flag_code == CODE_16BIT)
6584 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6585 {
6586 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6587 i.types[op] = disp16;
20f0a1fc
NC		 6588 }
6589 else
6590 {
6591 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6592 i.types[op] = disp32;
29b0f896
AM		 6593 }
6594 }
6c30d220 6595 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6596 {
6c30d220 6597 /* !i.base_reg && i.index_reg */
db51cc60
L		 6598 if (i.index_reg->reg_num == RegEiz
6599 || i.index_reg->reg_num == RegRiz)
6600 i.sib.index = NO_INDEX_REGISTER;
6601 else
6602 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6603 i.sib.base = NO_BASE_REGISTER;
6604 i.sib.scale = i.log2_scale_factor;
6605 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 6606 i.types[op].bitfield.disp8 = 0;
6607 i.types[op].bitfield.disp16 = 0;
6608 i.types[op].bitfield.disp64 = 0;
43083a50 6609 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
40fb9820
L		 6610 {
6611 /* Must be 32 bit */
6612 i.types[op].bitfield.disp32 = 1;
6613 i.types[op].bitfield.disp32s = 0;
6614 }
29b0f896 6615 else
40fb9820
L		 6616 {
6617 i.types[op].bitfield.disp32 = 0;
6618 i.types[op].bitfield.disp32s = 1;
6619 }
29b0f896 6620 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6621 i.rex |= REX_X;
29b0f896
AM		 6622 }
6623 }
6624 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6625 else if (i.base_reg->reg_num == RegRip ||
6626 i.base_reg->reg_num == RegEip)
29b0f896 6627 {
6c30d220 6628 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6629 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6630 i.types[op].bitfield.disp8 = 0;
6631 i.types[op].bitfield.disp16 = 0;
6632 i.types[op].bitfield.disp32 = 0;
6633 i.types[op].bitfield.disp32s = 1;
6634 i.types[op].bitfield.disp64 = 0;
71903a11 6635 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6636 if (! i.disp_operands)
6637 fake_zero_displacement = 1;
29b0f896 6638 }
dc821c5f 6639 else if (i.base_reg->reg_type.bitfield.word)
29b0f896 6640 {
6c30d220 6641 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6642 switch (i.base_reg->reg_num)
6643 {
6644 case 3: /* (%bx) */
6645 if (i.index_reg == 0)
6646 i.rm.regmem = 7;
6647 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6648 i.rm.regmem = i.index_reg->reg_num - 6;
6649 break;
6650 case 5: /* (%bp) */
6651 default_seg = &ss;
6652 if (i.index_reg == 0)
6653 {
6654 i.rm.regmem = 6;
40fb9820 6655 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6656 {
6657 /* fake (%bp) into 0(%bp) */
b5014f7a 6658 i.types[op].bitfield.disp8 = 1;
252b5132 6659 fake_zero_displacement = 1;
29b0f896
AM		 6660 }
6661 }
6662 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6663 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6664 break;
6665 default: /* (%si) -> 4 or (%di) -> 5 */
6666 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6667 }
6668 i.rm.mode = mode_from_disp_size (i.types[op]);
6669 }
6670 else /* i.base_reg and 32/64 bit mode */
6671 {
6672 if (flag_code == CODE_64BIT
40fb9820
L		 6673 && operand_type_check (i.types[op], disp))
6674 {
6675 i386_operand_type temp;
0dfbf9d7 6676 operand_type_set (&temp, 0);
40fb9820
L		 6677 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
6678 i.types[op] = temp;
6679 if (i.prefix[ADDR_PREFIX] == 0)
6680 i.types[op].bitfield.disp32s = 1;
6681 else
6682 i.types[op].bitfield.disp32 = 1;
6683 }
20f0a1fc 6684
6c30d220
L		 6685 if (!i.tm.opcode_modifier.vecsib)
6686 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6687 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6688 i.rex |= REX_B;
29b0f896
AM		 6689 i.sib.base = i.base_reg->reg_num;
6690 /* x86-64 ignores REX prefix bit here to avoid decoder
6691 complications. */
848930b2
JB		 6692 if (!(i.base_reg->reg_flags & RegRex)
6693 && (i.base_reg->reg_num == EBP_REG_NUM
6694 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6695 default_seg = &ss;
848930b2 6696 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6697 {
848930b2 6698 fake_zero_displacement = 1;
b5014f7a 6699 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6700 }
6701 i.sib.scale = i.log2_scale_factor;
6702 if (i.index_reg == 0)
6703 {
6c30d220 6704 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6705 /* <disp>(%esp) becomes two byte modrm with no index
6706 register. We've already stored the code for esp
6707 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6708 Any base register besides %esp will not use the
6709 extra modrm byte. */
6710 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6711 }
6c30d220 6712 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6713 {
db51cc60
L		 6714 if (i.index_reg->reg_num == RegEiz
6715 || i.index_reg->reg_num == RegRiz)
6716 i.sib.index = NO_INDEX_REGISTER;
6717 else
6718 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6719 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6720 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6721 i.rex |= REX_X;
29b0f896 6722 }
67a4f2b7
AO		 6723
6724 if (i.disp_operands
6725 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6726 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6727 i.rm.mode = 0;
6728 else
a501d77e
L		 6729 {
6730 if (!fake_zero_displacement
6731 && !i.disp_operands
6732 && i.disp_encoding)
6733 {
6734 fake_zero_displacement = 1;
6735 if (i.disp_encoding == disp_encoding_8bit)
6736 i.types[op].bitfield.disp8 = 1;
6737 else
6738 i.types[op].bitfield.disp32 = 1;
6739 }
6740 i.rm.mode = mode_from_disp_size (i.types[op]);
6741 }
29b0f896 6742 }
252b5132 6743
29b0f896
AM		 6744 if (fake_zero_displacement)
6745 {
6746 /* Fakes a zero displacement assuming that i.types[op]
6747 holds the correct displacement size. */
6748 expressionS *exp;
6749
9c2799c2 6750 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6751 exp = &disp_expressions[i.disp_operands++];
6752 i.op[op].disps = exp;
6753 exp->X_op = O_constant;
6754 exp->X_add_number = 0;
6755 exp->X_add_symbol = (symbolS *) 0;
6756 exp->X_op_symbol = (symbolS *) 0;
6757 }
c0f3af97
L		 6758
6759 mem = op;
29b0f896 6760 }
c0f3af97
L		 6761 else
6762 mem = ~0;
252b5132 6763
8c43a48b 6764 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6765 {
6766 if (operand_type_check (i.types[0], imm))
6767 i.vex.register_specifier = NULL;
6768 else
6769 {
6770 /* VEX.vvvv encodes one of the sources when the first
6771 operand is not an immediate. */
1ef99a7b 6772 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6773 i.vex.register_specifier = i.op[0].regs;
6774 else
6775 i.vex.register_specifier = i.op[1].regs;
6776 }
6777
6778 /* Destination is a XMM register encoded in the ModRM.reg
6779 and VEX.R bit. */
6780 i.rm.reg = i.op[2].regs->reg_num;
6781 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6782 i.rex |= REX_R;
6783
6784 /* ModRM.rm and VEX.B encodes the other source. */
6785 if (!i.mem_operands)
6786 {
6787 i.rm.mode = 3;
6788
1ef99a7b 6789 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6790 i.rm.regmem = i.op[1].regs->reg_num;
6791 else
6792 i.rm.regmem = i.op[0].regs->reg_num;
6793
6794 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6795 i.rex |= REX_B;
6796 }
6797 }
2426c15f 6798 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6799 {
6800 i.vex.register_specifier = i.op[2].regs;
6801 if (!i.mem_operands)
6802 {
6803 i.rm.mode = 3;
6804 i.rm.regmem = i.op[1].regs->reg_num;
6805 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6806 i.rex |= REX_B;
6807 }
6808 }
29b0f896
AM		 6809 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6810 (if any) based on i.tm.extension_opcode. Again, we must be
6811 careful to make sure that segment/control/debug/test/MMX
6812 registers are coded into the i.rm.reg field. */
f88c9eb0 6813 else if (i.reg_operands)
29b0f896 6814 {
99018f42 6815 unsigned int op;
7ab9ffdd
L		 6816 unsigned int vex_reg = ~0;
6817
6818 for (op = 0; op < i.operands; op++)
dc821c5f 6819 if (i.types[op].bitfield.reg
7ab9ffdd 6820 || i.types[op].bitfield.regmmx
1b54b8d7 6821 || i.types[op].bitfield.regsimd
7e8b059b 6822 || i.types[op].bitfield.regbnd
43234a1e 6823 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6824 || i.types[op].bitfield.sreg2
6825 || i.types[op].bitfield.sreg3
6826 || i.types[op].bitfield.control
6827 || i.types[op].bitfield.debug
6828 || i.types[op].bitfield.test)
6829 break;
c0209578 6830
7ab9ffdd
L		 6831 if (vex_3_sources)
6832 op = dest;
2426c15f 6833 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6834 {
6835 /* For instructions with VexNDS, the register-only
6836 source operand is encoded in VEX prefix. */
6837 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6838
7ab9ffdd 6839 if (op > mem)
c0f3af97 6840 {
7ab9ffdd
L		 6841 vex_reg = op++;
6842 gas_assert (op < i.operands);
c0f3af97
L		 6843 }
6844 else
c0f3af97 6845 {
f12dc422
L		 6846 /* Check register-only source operand when two source
6847 operands are swapped. */
6848 if (!i.tm.operand_types[op].bitfield.baseindex
6849 && i.tm.operand_types[op + 1].bitfield.baseindex)
6850 {
6851 vex_reg = op;
6852 op += 2;
6853 gas_assert (mem == (vex_reg + 1)
6854 && op < i.operands);
6855 }
6856 else
6857 {
6858 vex_reg = op + 1;
6859 gas_assert (vex_reg < i.operands);
6860 }
c0f3af97 6861 }
7ab9ffdd 6862 }
2426c15f 6863 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6864 {
f12dc422 6865 /* For instructions with VexNDD, the register destination
7ab9ffdd 6866 is encoded in VEX prefix. */
f12dc422
L		 6867 if (i.mem_operands == 0)
6868 {
6869 /* There is no memory operand. */
6870 gas_assert ((op + 2) == i.operands);
6871 vex_reg = op + 1;
6872 }
6873 else
8d63c93e 6874 {
f12dc422
L		 6875 /* There are only 2 operands. */
6876 gas_assert (op < 2 && i.operands == 2);
6877 vex_reg = 1;
6878 }
7ab9ffdd
L		 6879 }
6880 else
6881 gas_assert (op < i.operands);
99018f42 6882
7ab9ffdd
L		 6883 if (vex_reg != (unsigned int) ~0)
6884 {
f12dc422 6885 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6886
dc821c5f
JB		 6887 if ((!type->bitfield.reg
6888 || (!type->bitfield.dword && !type->bitfield.qword))
10c17abd 6889 && !type->bitfield.regsimd
43234a1e 6890 && !operand_type_equal (type, &regmask))
7ab9ffdd 6891 abort ();
f88c9eb0 6892
7ab9ffdd
L		 6893 i.vex.register_specifier = i.op[vex_reg].regs;
6894 }
6895
1b9f0c97
L		 6896 /* Don't set OP operand twice. */
6897 if (vex_reg != op)
7ab9ffdd 6898 {
1b9f0c97
L		 6899 /* If there is an extension opcode to put here, the
6900 register number must be put into the regmem field. */
6901 if (i.tm.extension_opcode != None)
6902 {
6903 i.rm.regmem = i.op[op].regs->reg_num;
6904 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6905 i.rex |= REX_B;
43234a1e
L		 6906 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6907 i.vrex |= REX_B;
1b9f0c97
L		 6908 }
6909 else
6910 {
6911 i.rm.reg = i.op[op].regs->reg_num;
6912 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6913 i.rex |= REX_R;
43234a1e
L		 6914 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6915 i.vrex |= REX_R;
1b9f0c97 6916 }
7ab9ffdd 6917 }
252b5132 6918
29b0f896
AM		 6919 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6920 must set it to 3 to indicate this is a register operand
6921 in the regmem field. */
6922 if (!i.mem_operands)
6923 i.rm.mode = 3;
6924 }
252b5132 6925
29b0f896 6926 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6927 if (i.tm.extension_opcode != None)
29b0f896
AM		 6928 i.rm.reg = i.tm.extension_opcode;
6929 }
6930 return default_seg;
6931}
252b5132 6932
29b0f896 6933static void
e3bb37b5 6934output_branch (void)
29b0f896
AM		 6935{
6936 char *p;
f8a5c266 6937 int size;
29b0f896
AM		 6938 int code16;
6939 int prefix;
6940 relax_substateT subtype;
6941 symbolS *sym;
6942 offsetT off;
6943
f8a5c266 6944 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6945 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6946
6947 prefix = 0;
6948 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6949 {
29b0f896
AM		 6950 prefix = 1;
6951 i.prefixes -= 1;
6952 code16 ^= CODE16;
252b5132 6953 }
29b0f896
AM		 6954 /* Pentium4 branch hints. */
6955 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6956 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6957 {
29b0f896
AM		 6958 prefix++;
6959 i.prefixes--;
6960 }
6961 if (i.prefix[REX_PREFIX] != 0)
6962 {
6963 prefix++;
6964 i.prefixes--;
2f66722d
AM		 6965 }
6966
7e8b059b
L		 6967 /* BND prefixed jump. */
6968 if (i.prefix[BND_PREFIX] != 0)
6969 {
6970 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6971 i.prefixes -= 1;
6972 }
6973
29b0f896
AM		 6974 if (i.prefixes != 0 && !intel_syntax)
6975 as_warn (_("skipping prefixes on this instruction"));
6976
6977 /* It's always a symbol; End frag & setup for relax.
6978 Make sure there is enough room in this frag for the largest
6979 instruction we may generate in md_convert_frag. This is 2
6980 bytes for the opcode and room for the prefix and largest
6981 displacement. */
6982 frag_grow (prefix + 2 + 4);
6983 /* Prefix and 1 opcode byte go in fr_fix. */
6984 p = frag_more (prefix + 1);
6985 if (i.prefix[DATA_PREFIX] != 0)
6986 *p++ = DATA_PREFIX_OPCODE;
6987 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6988 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6989 *p++ = i.prefix[SEG_PREFIX];
6990 if (i.prefix[REX_PREFIX] != 0)
6991 *p++ = i.prefix[REX_PREFIX];
6992 *p = i.tm.base_opcode;
6993
6994 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6995 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6996 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6997 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6998 else
f8a5c266 6999 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 7000 subtype |= code16;
3e73aa7c 7001
29b0f896
AM		 7002 sym = i.op[0].disps->X_add_symbol;
7003 off = i.op[0].disps->X_add_number;
3e73aa7c 7004
29b0f896
AM		 7005 if (i.op[0].disps->X_op != O_constant
7006 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 7007 {
29b0f896
AM		 7008 /* Handle complex expressions. */
7009 sym = make_expr_symbol (i.op[0].disps);
7010 off = 0;
7011 }
3e73aa7c 7012
29b0f896
AM		 7013 /* 1 possible extra opcode + 4 byte displacement go in var part.
7014 Pass reloc in fr_var. */
d258b828 7015 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 7016}
3e73aa7c 7017
29b0f896 7018static void
e3bb37b5 7019output_jump (void)
29b0f896
AM		 7020{
7021 char *p;
7022 int size;
3e02c1cc 7023 fixS *fixP;
29b0f896 7024
40fb9820 7025 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 7026 {
7027 /* This is a loop or jecxz type instruction. */
7028 size = 1;
7029 if (i.prefix[ADDR_PREFIX] != 0)
7030 {
7031 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7032 i.prefixes -= 1;
7033 }
7034 /* Pentium4 branch hints. */
7035 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7036 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7037 {
7038 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7039 i.prefixes--;
3e73aa7c
JH		 7040 }
7041 }
29b0f896
AM		 7042 else
7043 {
7044 int code16;
3e73aa7c 7045
29b0f896
AM		 7046 code16 = 0;
7047 if (flag_code == CODE_16BIT)
7048 code16 = CODE16;
3e73aa7c 7049
29b0f896
AM		 7050 if (i.prefix[DATA_PREFIX] != 0)
7051 {
7052 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7053 i.prefixes -= 1;
7054 code16 ^= CODE16;
7055 }
252b5132 7056
29b0f896
AM		 7057 size = 4;
7058 if (code16)
7059 size = 2;
7060 }
9fcc94b6 7061
29b0f896
AM		 7062 if (i.prefix[REX_PREFIX] != 0)
7063 {
7064 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7065 i.prefixes -= 1;
7066 }
252b5132 7067
7e8b059b
L		 7068 /* BND prefixed jump. */
7069 if (i.prefix[BND_PREFIX] != 0)
7070 {
7071 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7072 i.prefixes -= 1;
7073 }
7074
29b0f896
AM		 7075 if (i.prefixes != 0 && !intel_syntax)
7076 as_warn (_("skipping prefixes on this instruction"));
e0890092 7077
42164a71
L		 7078 p = frag_more (i.tm.opcode_length + size);
7079 switch (i.tm.opcode_length)
7080 {
7081 case 2:
7082 *p++ = i.tm.base_opcode >> 8;
1a0670f3 7083 /* Fall through. */
42164a71
L		 7084 case 1:
7085 *p++ = i.tm.base_opcode;
7086 break;
7087 default:
7088 abort ();
7089 }
e0890092 7090
3e02c1cc 7091 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7092 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 7093
7094 /* All jumps handled here are signed, but don't use a signed limit
7095 check for 32 and 16 bit jumps as we want to allow wrap around at
7096 4G and 64k respectively. */
7097 if (size == 1)
7098 fixP->fx_signed = 1;
29b0f896 7099}
e0890092 7100
29b0f896 7101static void
e3bb37b5 7102output_interseg_jump (void)
29b0f896
AM		 7103{
7104 char *p;
7105 int size;
7106 int prefix;
7107 int code16;
252b5132 7108
29b0f896
AM		 7109 code16 = 0;
7110 if (flag_code == CODE_16BIT)
7111 code16 = CODE16;
a217f122 7112
29b0f896
AM		 7113 prefix = 0;
7114 if (i.prefix[DATA_PREFIX] != 0)
7115 {
7116 prefix = 1;
7117 i.prefixes -= 1;
7118 code16 ^= CODE16;
7119 }
7120 if (i.prefix[REX_PREFIX] != 0)
7121 {
7122 prefix++;
7123 i.prefixes -= 1;
7124 }
252b5132 7125
29b0f896
AM		 7126 size = 4;
7127 if (code16)
7128 size = 2;
252b5132 7129
29b0f896
AM		 7130 if (i.prefixes != 0 && !intel_syntax)
7131 as_warn (_("skipping prefixes on this instruction"));
252b5132 7132
29b0f896
AM		 7133 /* 1 opcode; 2 segment; offset */
7134 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7135
29b0f896
AM		 7136 if (i.prefix[DATA_PREFIX] != 0)
7137 *p++ = DATA_PREFIX_OPCODE;
252b5132 7138
29b0f896
AM		 7139 if (i.prefix[REX_PREFIX] != 0)
7140 *p++ = i.prefix[REX_PREFIX];
252b5132 7141
29b0f896
AM		 7142 *p++ = i.tm.base_opcode;
7143 if (i.op[1].imms->X_op == O_constant)
7144 {
7145 offsetT n = i.op[1].imms->X_add_number;
252b5132 7146
29b0f896
AM		 7147 if (size == 2
7148 && !fits_in_unsigned_word (n)
7149 && !fits_in_signed_word (n))
7150 {
7151 as_bad (_("16-bit jump out of range"));
7152 return;
7153 }
7154 md_number_to_chars (p, n, size);
7155 }
7156 else
7157 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7158 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7159 if (i.op[0].imms->X_op != O_constant)
7160 as_bad (_("can't handle non absolute segment in `%s'"),
7161 i.tm.name);
7162 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7163}
a217f122 7164
29b0f896 7165static void
e3bb37b5 7166output_insn (void)
29b0f896 7167{
2bbd9c25
JJ		 7168 fragS *insn_start_frag;
7169 offsetT insn_start_off;
7170
29b0f896
AM		 7171 /* Tie dwarf2 debug info to the address at the start of the insn.
7172 We can't do this after the insn has been output as the current
7173 frag may have been closed off. eg. by frag_var. */
7174 dwarf2_emit_insn (0);
7175
2bbd9c25
JJ		 7176 insn_start_frag = frag_now;
7177 insn_start_off = frag_now_fix ();
7178
29b0f896 7179 /* Output jumps. */
40fb9820 7180 if (i.tm.opcode_modifier.jump)
29b0f896 7181 output_branch ();
40fb9820
L		 7182 else if (i.tm.opcode_modifier.jumpbyte
7183 || i.tm.opcode_modifier.jumpdword)
29b0f896 7184 output_jump ();
40fb9820 7185 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7186 output_interseg_jump ();
7187 else
7188 {
7189 /* Output normal instructions here. */
7190 char *p;
7191 unsigned char *q;
47465058 7192 unsigned int j;
331d2d0d 7193 unsigned int prefix;
4dffcebc 7194
e4e00185
AS		 7195 if (avoid_fence
7196 && i.tm.base_opcode == 0xfae
7197 && i.operands == 1
7198 && i.imm_operands == 1
7199 && (i.op[0].imms->X_add_number == 0xe8
7200 || i.op[0].imms->X_add_number == 0xf0
7201 || i.op[0].imms->X_add_number == 0xf8))
7202 {
7203 /* Encode lfence, mfence, and sfence as
7204 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7205 offsetT val = 0x240483f0ULL;
7206 p = frag_more (5);
7207 md_number_to_chars (p, val, 5);
7208 return;
7209 }
7210
d022bddd
IT		 7211 /* Some processors fail on LOCK prefix. This options makes
7212 assembler ignore LOCK prefix and serves as a workaround. */
7213 if (omit_lock_prefix)
7214 {
7215 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7216 return;
7217 i.prefix[LOCK_PREFIX] = 0;
7218 }
7219
43234a1e
L		 7220 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7221 don't need the explicit prefix. */
7222 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7223 {
c0f3af97 7224 switch (i.tm.opcode_length)
bc4bd9ab 7225 {
c0f3af97
L		 7226 case 3:
7227 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7228 {
c0f3af97
L		 7229 prefix = (i.tm.base_opcode >> 24) & 0xff;
7230 goto check_prefix;
7231 }
7232 break;
7233 case 2:
7234 if ((i.tm.base_opcode & 0xff0000) != 0)
7235 {
7236 prefix = (i.tm.base_opcode >> 16) & 0xff;
7237 if (i.tm.cpu_flags.bitfield.cpupadlock)
7238 {
4dffcebc 7239check_prefix:
c0f3af97 7240 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7241 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7242 != REPE_PREFIX_OPCODE))
7243 add_prefix (prefix);
7244 }
7245 else
4dffcebc
L		 7246 add_prefix (prefix);
7247 }
c0f3af97
L		 7248 break;
7249 case 1:
7250 break;
390c91cf
L		 7251 case 0:
7252 /* Check for pseudo prefixes. */
7253 as_bad_where (insn_start_frag->fr_file,
7254 insn_start_frag->fr_line,
7255 _("pseudo prefix without instruction"));
7256 return;
c0f3af97
L		 7257 default:
7258 abort ();
bc4bd9ab 7259 }
c0f3af97 7260
6d19a37a 7261#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7262 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7263 R_X86_64_GOTTPOFF relocation so that linker can safely
7264 perform IE->LE optimization. */
7265 if (x86_elf_abi == X86_64_X32_ABI
7266 && i.operands == 2
7267 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7268 && i.prefix[REX_PREFIX] == 0)
7269 add_prefix (REX_OPCODE);
6d19a37a 7270#endif
cf61b747 7271
c0f3af97
L		 7272 /* The prefix bytes. */
7273 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7274 if (*q)
7275 FRAG_APPEND_1_CHAR (*q);
0f10071e 7276 }
ae5c1c7b 7277 else
c0f3af97
L		 7278 {
7279 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7280 if (*q)
7281 switch (j)
7282 {
7283 case REX_PREFIX:
7284 /* REX byte is encoded in VEX prefix. */
7285 break;
7286 case SEG_PREFIX:
7287 case ADDR_PREFIX:
7288 FRAG_APPEND_1_CHAR (*q);
7289 break;
7290 default:
7291 /* There should be no other prefixes for instructions
7292 with VEX prefix. */
7293 abort ();
7294 }
7295
43234a1e
L		 7296 /* For EVEX instructions i.vrex should become 0 after
7297 build_evex_prefix. For VEX instructions upper 16 registers
7298 aren't available, so VREX should be 0. */
7299 if (i.vrex)
7300 abort ();
c0f3af97
L		 7301 /* Now the VEX prefix. */
7302 p = frag_more (i.vex.length);
7303 for (j = 0; j < i.vex.length; j++)
7304 p[j] = i.vex.bytes[j];
7305 }
252b5132 7306
29b0f896 7307 /* Now the opcode; be careful about word order here! */
4dffcebc 7308 if (i.tm.opcode_length == 1)
29b0f896
AM		 7309 {
7310 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7311 }
7312 else
7313 {
4dffcebc 7314 switch (i.tm.opcode_length)
331d2d0d 7315 {
43234a1e
L		 7316 case 4:
7317 p = frag_more (4);
7318 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7319 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7320 break;
4dffcebc 7321 case 3:
331d2d0d
L		 7322 p = frag_more (3);
7323 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7324 break;
7325 case 2:
7326 p = frag_more (2);
7327 break;
7328 default:
7329 abort ();
7330 break;
331d2d0d 7331 }
0f10071e 7332
29b0f896
AM		 7333 /* Put out high byte first: can't use md_number_to_chars! */
7334 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7335 *p = i.tm.base_opcode & 0xff;
7336 }
3e73aa7c 7337
29b0f896 7338 /* Now the modrm byte and sib byte (if present). */
40fb9820 7339 if (i.tm.opcode_modifier.modrm)
29b0f896 7340 {
4a3523fa
L		 7341 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7342 | i.rm.reg << 3
7343 | i.rm.mode << 6));
29b0f896
AM		 7344 /* If i.rm.regmem == ESP (4)
7345 && i.rm.mode != (Register mode)
7346 && not 16 bit
7347 ==> need second modrm byte. */
7348 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7349 && i.rm.mode != 3
dc821c5f 7350 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
4a3523fa
L		 7351 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7352 | i.sib.index << 3
7353 | i.sib.scale << 6));
29b0f896 7354 }
3e73aa7c 7355
29b0f896 7356 if (i.disp_operands)
2bbd9c25 7357 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7358
29b0f896 7359 if (i.imm_operands)
2bbd9c25 7360 output_imm (insn_start_frag, insn_start_off);
29b0f896 7361 }
252b5132 7362
29b0f896
AM		 7363#ifdef DEBUG386
7364 if (flag_debug)
7365 {
7b81dfbb 7366 pi ("" /*line*/, &i);
29b0f896
AM		 7367 }
7368#endif /* DEBUG386 */
7369}
252b5132 7370
e205caa7
L		 7371/* Return the size of the displacement operand N. */
7372
7373static int
7374disp_size (unsigned int n)
7375{
7376 int size = 4;
43234a1e 7377
b5014f7a 7378 if (i.types[n].bitfield.disp64)
40fb9820
L		 7379 size = 8;
7380 else if (i.types[n].bitfield.disp8)
7381 size = 1;
7382 else if (i.types[n].bitfield.disp16)
7383 size = 2;
e205caa7
L		 7384 return size;
7385}
7386
7387/* Return the size of the immediate operand N. */
7388
7389static int
7390imm_size (unsigned int n)
7391{
7392 int size = 4;
40fb9820
L		 7393 if (i.types[n].bitfield.imm64)
7394 size = 8;
7395 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7396 size = 1;
7397 else if (i.types[n].bitfield.imm16)
7398 size = 2;
e205caa7
L		 7399 return size;
7400}
7401
29b0f896 7402static void
64e74474 7403output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7404{
7405 char *p;
7406 unsigned int n;
252b5132 7407
29b0f896
AM		 7408 for (n = 0; n < i.operands; n++)
7409 {
b5014f7a 7410 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 7411 {
7412 if (i.op[n].disps->X_op == O_constant)
7413 {
e205caa7 7414 int size = disp_size (n);
43234a1e 7415 offsetT val = i.op[n].disps->X_add_number;
252b5132 7416
b5014f7a 7417 val = offset_in_range (val >> i.memshift, size);
29b0f896
AM		 7418 p = frag_more (size);
7419 md_number_to_chars (p, val, size);
7420 }
7421 else
7422 {
f86103b7 7423 enum bfd_reloc_code_real reloc_type;
e205caa7 7424 int size = disp_size (n);
40fb9820 7425 int sign = i.types[n].bitfield.disp32s;
29b0f896 7426 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7427 fixS *fixP;
29b0f896 7428
e205caa7 7429 /* We can't have 8 bit displacement here. */
9c2799c2 7430 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7431
29b0f896
AM		 7432 /* The PC relative address is computed relative
7433 to the instruction boundary, so in case immediate
7434 fields follows, we need to adjust the value. */
7435 if (pcrel && i.imm_operands)
7436 {
29b0f896 7437 unsigned int n1;
e205caa7 7438 int sz = 0;
252b5132 7439
29b0f896 7440 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7441 if (operand_type_check (i.types[n1], imm))
252b5132 7442 {
e205caa7
L		 7443 /* Only one immediate is allowed for PC
7444 relative address. */
9c2799c2 7445 gas_assert (sz == 0);
e205caa7
L		 7446 sz = imm_size (n1);
7447 i.op[n].disps->X_add_number -= sz;
252b5132 7448 }
29b0f896 7449 /* We should find the immediate. */
9c2799c2 7450 gas_assert (sz != 0);
29b0f896 7451 }
520dc8e8 7452
29b0f896 7453 p = frag_more (size);
d258b828 7454 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7455 if (GOT_symbol
2bbd9c25 7456 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7457 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7458 || reloc_type == BFD_RELOC_X86_64_32S
7459 || (reloc_type == BFD_RELOC_64
7460 && object_64bit))
d6ab8113
JB		 7461 && (i.op[n].disps->X_op == O_symbol
7462 || (i.op[n].disps->X_op == O_add
7463 && ((symbol_get_value_expression
7464 (i.op[n].disps->X_op_symbol)->X_op)
7465 == O_subtract))))
7466 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7467 {
7468 offsetT add;
7469
7470 if (insn_start_frag == frag_now)
7471 add = (p - frag_now->fr_literal) - insn_start_off;
7472 else
7473 {
7474 fragS *fr;
7475
7476 add = insn_start_frag->fr_fix - insn_start_off;
7477 for (fr = insn_start_frag->fr_next;
7478 fr && fr != frag_now; fr = fr->fr_next)
7479 add += fr->fr_fix;
7480 add += p - frag_now->fr_literal;
7481 }
7482
4fa24527 7483 if (!object_64bit)
7b81dfbb
AJ		 7484 {
7485 reloc_type = BFD_RELOC_386_GOTPC;
7486 i.op[n].imms->X_add_number += add;
7487 }
7488 else if (reloc_type == BFD_RELOC_64)
7489 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7490 else
7b81dfbb
AJ		 7491 /* Don't do the adjustment for x86-64, as there
7492 the pcrel addressing is relative to the _next_
7493 insn, and that is taken care of in other code. */
d6ab8113 7494 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7495 }
02a86693
L		 7496 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7497 size, i.op[n].disps, pcrel,
7498 reloc_type);
7499 /* Check for "call/jmp *mem", "mov mem, %reg",
7500 "test %reg, mem" and "binop mem, %reg" where binop
7501 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7502 instructions. Always generate R_386_GOT32X for
7503 "sym*GOT" operand in 32-bit mode. */
7504 if ((generate_relax_relocations
7505 || (!object_64bit
7506 && i.rm.mode == 0
7507 && i.rm.regmem == 5))
7508 && (i.rm.mode == 2
7509 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7510 && ((i.operands == 1
7511 && i.tm.base_opcode == 0xff
7512 && (i.rm.reg == 2 || i.rm.reg == 4))
7513 || (i.operands == 2
7514 && (i.tm.base_opcode == 0x8b
7515 || i.tm.base_opcode == 0x85
7516 || (i.tm.base_opcode & 0xc7) == 0x03))))
7517 {
7518 if (object_64bit)
7519 {
7520 fixP->fx_tcbit = i.rex != 0;
7521 if (i.base_reg
7522 && (i.base_reg->reg_num == RegRip
7523 || i.base_reg->reg_num == RegEip))
7524 fixP->fx_tcbit2 = 1;
7525 }
7526 else
7527 fixP->fx_tcbit2 = 1;
7528 }
29b0f896
AM		 7529 }
7530 }
7531 }
7532}
252b5132 7533
29b0f896 7534static void
64e74474 7535output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7536{
7537 char *p;
7538 unsigned int n;
252b5132 7539
29b0f896
AM		 7540 for (n = 0; n < i.operands; n++)
7541 {
43234a1e
L		 7542 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7543 if (i.rounding && (int) n == i.rounding->operand)
7544 continue;
7545
40fb9820 7546 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7547 {
7548 if (i.op[n].imms->X_op == O_constant)
7549 {
e205caa7 7550 int size = imm_size (n);
29b0f896 7551 offsetT val;
b4cac588 7552
29b0f896
AM		 7553 val = offset_in_range (i.op[n].imms->X_add_number,
7554 size);
7555 p = frag_more (size);
7556 md_number_to_chars (p, val, size);
7557 }
7558 else
7559 {
7560 /* Not absolute_section.
7561 Need a 32-bit fixup (don't support 8bit
7562 non-absolute imms). Try to support other
7563 sizes ... */
f86103b7 7564 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7565 int size = imm_size (n);
7566 int sign;
29b0f896 7567
40fb9820 7568 if (i.types[n].bitfield.imm32s
a7d61044 7569 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7570 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7571 sign = 1;
e205caa7
L		 7572 else
7573 sign = 0;
520dc8e8 7574
29b0f896 7575 p = frag_more (size);
d258b828 7576 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7577
2bbd9c25
JJ		 7578 /* This is tough to explain. We end up with this one if we
7579 * have operands that look like
7580 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7581 * obtain the absolute address of the GOT, and it is strongly
7582 * preferable from a performance point of view to avoid using
7583 * a runtime relocation for this. The actual sequence of
7584 * instructions often look something like:
7585 *
7586 * call .L66
7587 * .L66:
7588 * popl %ebx
7589 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7590 *
7591 * The call and pop essentially return the absolute address
7592 * of the label .L66 and store it in %ebx. The linker itself
7593 * will ultimately change the first operand of the addl so
7594 * that %ebx points to the GOT, but to keep things simple, the
7595 * .o file must have this operand set so that it generates not
7596 * the absolute address of .L66, but the absolute address of
7597 * itself. This allows the linker itself simply treat a GOTPC
7598 * relocation as asking for a pcrel offset to the GOT to be
7599 * added in, and the addend of the relocation is stored in the
7600 * operand field for the instruction itself.
7601 *
7602 * Our job here is to fix the operand so that it would add
7603 * the correct offset so that %ebx would point to itself. The
7604 * thing that is tricky is that .-.L66 will point to the
7605 * beginning of the instruction, so we need to further modify
7606 * the operand so that it will point to itself. There are
7607 * other cases where you have something like:
7608 *
7609 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7610 *
7611 * and here no correction would be required. Internally in
7612 * the assembler we treat operands of this form as not being
7613 * pcrel since the '.' is explicitly mentioned, and I wonder
7614 * whether it would simplify matters to do it this way. Who
7615 * knows. In earlier versions of the PIC patches, the
7616 * pcrel_adjust field was used to store the correction, but
7617 * since the expression is not pcrel, I felt it would be
7618 * confusing to do it this way. */
7619
d6ab8113 7620 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7621 || reloc_type == BFD_RELOC_X86_64_32S
7622 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7623 && GOT_symbol
7624 && GOT_symbol == i.op[n].imms->X_add_symbol
7625 && (i.op[n].imms->X_op == O_symbol
7626 || (i.op[n].imms->X_op == O_add
7627 && ((symbol_get_value_expression
7628 (i.op[n].imms->X_op_symbol)->X_op)
7629 == O_subtract))))
7630 {
2bbd9c25
JJ		 7631 offsetT add;
7632
7633 if (insn_start_frag == frag_now)
7634 add = (p - frag_now->fr_literal) - insn_start_off;
7635 else
7636 {
7637 fragS *fr;
7638
7639 add = insn_start_frag->fr_fix - insn_start_off;
7640 for (fr = insn_start_frag->fr_next;
7641 fr && fr != frag_now; fr = fr->fr_next)
7642 add += fr->fr_fix;
7643 add += p - frag_now->fr_literal;
7644 }
7645
4fa24527 7646 if (!object_64bit)
d6ab8113 7647 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7648 else if (size == 4)
d6ab8113 7649 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7650 else if (size == 8)
7651 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7652 i.op[n].imms->X_add_number += add;
29b0f896 7653 }
29b0f896
AM		 7654 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7655 i.op[n].imms, 0, reloc_type);
7656 }
7657 }
7658 }
252b5132
RH		 7659}
7660\f
d182319b
JB		 7661/* x86_cons_fix_new is called via the expression parsing code when a
7662 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7663static int cons_sign = -1;
7664
7665void
e3bb37b5 7666x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7667 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7668{
d258b828 7669 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7670
7671#ifdef TE_PE
7672 if (exp->X_op == O_secrel)
7673 {
7674 exp->X_op = O_symbol;
7675 r = BFD_RELOC_32_SECREL;
7676 }
7677#endif
7678
7679 fix_new_exp (frag, off, len, exp, 0, r);
7680}
7681
357d1bd8
L		 7682/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7683 purpose of the `.dc.a' internal pseudo-op. */
7684
7685int
7686x86_address_bytes (void)
7687{
7688 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7689 return 4;
7690 return stdoutput->arch_info->bits_per_address / 8;
7691}
7692
d382c579
TG		 7693#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7694 || defined (LEX_AT)
d258b828 7695# define lex_got(reloc, adjust, types) NULL
718ddfc0 7696#else
f3c180ae
AM		 7697/* Parse operands of the form
7698 <symbol>@GOTOFF+<nnn>
7699 and similar .plt or .got references.
7700
7701 If we find one, set up the correct relocation in RELOC and copy the
7702 input string, minus the `@GOTOFF' into a malloc'd buffer for
7703 parsing by the calling routine. Return this buffer, and if ADJUST
7704 is non-null set it to the length of the string we removed from the
7705 input line. Otherwise return NULL. */
7706static char *
91d6fa6a 7707lex_got (enum bfd_reloc_code_real *rel,
64e74474 7708 int *adjust,
d258b828 7709 i386_operand_type *types)
f3c180ae 7710{
7b81dfbb
AJ		 7711 /* Some of the relocations depend on the size of what field is to
7712 be relocated. But in our callers i386_immediate and i386_displacement
7713 we don't yet know the operand size (this will be set by insn
7714 matching). Hence we record the word32 relocation here,
7715 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7716 static const struct {
7717 const char *str;
cff8d58a 7718 int len;
4fa24527 7719 const enum bfd_reloc_code_real rel[2];
40fb9820 7720 const i386_operand_type types64;
f3c180ae 7721 } gotrel[] = {
8ce3d284 7722#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7723 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7724 BFD_RELOC_SIZE32 },
7725 OPERAND_TYPE_IMM32_64 },
8ce3d284 7726#endif
cff8d58a
L		 7727 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7728 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7729 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7730 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7731 BFD_RELOC_X86_64_PLT32 },
40fb9820 7732 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7733 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7734 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7735 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7736 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7737 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7738 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7739 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7740 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7741 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7742 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7743 BFD_RELOC_X86_64_TLSGD },
40fb9820 7744 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7745 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7746 _dummy_first_bfd_reloc_code_real },
40fb9820 7747 OPERAND_TYPE_NONE },
cff8d58a
L		 7748 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7749 BFD_RELOC_X86_64_TLSLD },
40fb9820 7750 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7751 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7752 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7753 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7754 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7755 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7756 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7757 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7758 _dummy_first_bfd_reloc_code_real },
40fb9820 7759 OPERAND_TYPE_NONE },
cff8d58a
L		 7760 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7761 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7762 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7763 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7764 _dummy_first_bfd_reloc_code_real },
40fb9820 7765 OPERAND_TYPE_NONE },
cff8d58a
L		 7766 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7767 _dummy_first_bfd_reloc_code_real },
40fb9820 7768 OPERAND_TYPE_NONE },
cff8d58a
L		 7769 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7770 BFD_RELOC_X86_64_GOT32 },
40fb9820 7771 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7772 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7773 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7774 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7775 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7776 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7777 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7778 };
7779 char *cp;
7780 unsigned int j;
7781
d382c579 7782#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7783 if (!IS_ELF)
7784 return NULL;
d382c579 7785#endif
718ddfc0 7786
f3c180ae 7787 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7788 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7789 return NULL;
7790
47465058 7791 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7792 {
cff8d58a 7793 int len = gotrel[j].len;
28f81592 7794 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7795 {
4fa24527 7796 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7797 {
28f81592
AM		 7798 int first, second;
7799 char *tmpbuf, *past_reloc;
f3c180ae 7800
91d6fa6a 7801 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7802
3956db08
JB		 7803 if (types)
7804 {
7805 if (flag_code != CODE_64BIT)
40fb9820
L		 7806 {
7807 types->bitfield.imm32 = 1;
7808 types->bitfield.disp32 = 1;
7809 }
3956db08
JB		 7810 else
7811 *types = gotrel[j].types64;
7812 }
7813
8fd4256d 7814 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7815 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7816
28f81592 7817 /* The length of the first part of our input line. */
f3c180ae 7818 first = cp - input_line_pointer;
28f81592
AM		 7819
7820 /* The second part goes from after the reloc token until
67c11a9b 7821 (and including) an end_of_line char or comma. */
28f81592 7822 past_reloc = cp + 1 + len;
67c11a9b
AM		 7823 cp = past_reloc;
7824 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7825 ++cp;
7826 second = cp + 1 - past_reloc;
28f81592
AM		 7827
7828 /* Allocate and copy string. The trailing NUL shouldn't
7829 be necessary, but be safe. */
add39d23 7830 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 7831 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7832 if (second != 0 && *past_reloc != ' ')
7833 /* Replace the relocation token with ' ', so that
7834 errors like foo@GOTOFF1 will be detected. */
7835 tmpbuf[first++] = ' ';
af89796a
L		 7836 else
7837 /* Increment length by 1 if the relocation token is
7838 removed. */
7839 len++;
7840 if (adjust)
7841 *adjust = len;
0787a12d
AM		 7842 memcpy (tmpbuf + first, past_reloc, second);
7843 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7844 return tmpbuf;
7845 }
7846
4fa24527
JB		 7847 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7848 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7849 return NULL;
7850 }
7851 }
7852
7853 /* Might be a symbol version string. Don't as_bad here. */
7854 return NULL;
7855}
4e4f7c87 7856#endif
f3c180ae 7857
a988325c
NC		 7858#ifdef TE_PE
7859#ifdef lex_got
7860#undef lex_got
7861#endif
7862/* Parse operands of the form
7863 <symbol>@SECREL32+<nnn>
7864
7865 If we find one, set up the correct relocation in RELOC and copy the
7866 input string, minus the `@SECREL32' into a malloc'd buffer for
7867 parsing by the calling routine. Return this buffer, and if ADJUST
7868 is non-null set it to the length of the string we removed from the
34bca508
L		 7869 input line. Otherwise return NULL.
7870
a988325c
NC		 7871 This function is copied from the ELF version above adjusted for PE targets. */
7872
7873static char *
7874lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7875 int *adjust ATTRIBUTE_UNUSED,
d258b828 7876 i386_operand_type *types)
a988325c
NC		 7877{
7878 static const struct
7879 {
7880 const char *str;
7881 int len;
7882 const enum bfd_reloc_code_real rel[2];
7883 const i386_operand_type types64;
7884 }
7885 gotrel[] =
7886 {
7887 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7888 BFD_RELOC_32_SECREL },
7889 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7890 };
7891
7892 char *cp;
7893 unsigned j;
7894
7895 for (cp = input_line_pointer; *cp != '@'; cp++)
7896 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7897 return NULL;
7898
7899 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7900 {
7901 int len = gotrel[j].len;
7902
7903 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7904 {
7905 if (gotrel[j].rel[object_64bit] != 0)
7906 {
7907 int first, second;
7908 char *tmpbuf, *past_reloc;
7909
7910 *rel = gotrel[j].rel[object_64bit];
7911 if (adjust)
7912 *adjust = len;
7913
7914 if (types)
7915 {
7916 if (flag_code != CODE_64BIT)
7917 {
7918 types->bitfield.imm32 = 1;
7919 types->bitfield.disp32 = 1;
7920 }
7921 else
7922 *types = gotrel[j].types64;
7923 }
7924
7925 /* The length of the first part of our input line. */
7926 first = cp - input_line_pointer;
7927
7928 /* The second part goes from after the reloc token until
7929 (and including) an end_of_line char or comma. */
7930 past_reloc = cp + 1 + len;
7931 cp = past_reloc;
7932 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7933 ++cp;
7934 second = cp + 1 - past_reloc;
7935
7936 /* Allocate and copy string. The trailing NUL shouldn't
7937 be necessary, but be safe. */
add39d23 7938 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 7939 memcpy (tmpbuf, input_line_pointer, first);
7940 if (second != 0 && *past_reloc != ' ')
7941 /* Replace the relocation token with ' ', so that
7942 errors like foo@SECLREL321 will be detected. */
7943 tmpbuf[first++] = ' ';
7944 memcpy (tmpbuf + first, past_reloc, second);
7945 tmpbuf[first + second] = '\0';
7946 return tmpbuf;
7947 }
7948
7949 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7950 gotrel[j].str, 1 << (5 + object_64bit));
7951 return NULL;
7952 }
7953 }
7954
7955 /* Might be a symbol version string. Don't as_bad here. */
7956 return NULL;
7957}
7958
7959#endif /* TE_PE */
7960
62ebcb5c 7961bfd_reloc_code_real_type
e3bb37b5 7962x86_cons (expressionS *exp, int size)
f3c180ae 7963{
62ebcb5c
AM		 7964 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7965
ee86248c
JB		 7966 intel_syntax = -intel_syntax;
7967
3c7b9c2c 7968 exp->X_md = 0;
4fa24527 7969 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7970 {
7971 /* Handle @GOTOFF and the like in an expression. */
7972 char *save;
7973 char *gotfree_input_line;
4a57f2cf 7974 int adjust = 0;
f3c180ae
AM		 7975
7976 save = input_line_pointer;
d258b828 7977 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7978 if (gotfree_input_line)
7979 input_line_pointer = gotfree_input_line;
7980
7981 expression (exp);
7982
7983 if (gotfree_input_line)
7984 {
7985 /* expression () has merrily parsed up to the end of line,
7986 or a comma - in the wrong buffer. Transfer how far
7987 input_line_pointer has moved to the right buffer. */
7988 input_line_pointer = (save
7989 + (input_line_pointer - gotfree_input_line)
7990 + adjust);
7991 free (gotfree_input_line);
3992d3b7
AM		 7992 if (exp->X_op == O_constant
7993 || exp->X_op == O_absent
7994 || exp->X_op == O_illegal
0398aac5 7995 || exp->X_op == O_register
3992d3b7
AM		 7996 || exp->X_op == O_big)
7997 {
7998 char c = *input_line_pointer;
7999 *input_line_pointer = 0;
8000 as_bad (_("missing or invalid expression `%s'"), save);
8001 *input_line_pointer = c;
8002 }
f3c180ae
AM		 8003 }
8004 }
8005 else
8006 expression (exp);
ee86248c
JB		 8007
8008 intel_syntax = -intel_syntax;
8009
8010 if (intel_syntax)
8011 i386_intel_simplify (exp);
62ebcb5c
AM		 8012
8013 return got_reloc;
f3c180ae 8014}
f3c180ae 8015
9f32dd5b
L		 8016static void
8017signed_cons (int size)
6482c264 8018{
d182319b
JB		 8019 if (flag_code == CODE_64BIT)
8020 cons_sign = 1;
8021 cons (size);
8022 cons_sign = -1;
6482c264
NC		 8023}
8024
d182319b 8025#ifdef TE_PE
6482c264 8026static void
7016a5d5 8027pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 8028{
8029 expressionS exp;
8030
8031 do
8032 {
8033 expression (&exp);
8034 if (exp.X_op == O_symbol)
8035 exp.X_op = O_secrel;
8036
8037 emit_expr (&exp, 4);
8038 }
8039 while (*input_line_pointer++ == ',');
8040
8041 input_line_pointer--;
8042 demand_empty_rest_of_line ();
8043}
6482c264
NC		 8044#endif
8045
43234a1e
L		 8046/* Handle Vector operations. */
8047
8048static char *
8049check_VecOperations (char *op_string, char *op_end)
8050{
8051 const reg_entry *mask;
8052 const char *saved;
8053 char *end_op;
8054
8055 while (*op_string
8056 && (op_end == NULL || op_string < op_end))
8057 {
8058 saved = op_string;
8059 if (*op_string == '{')
8060 {
8061 op_string++;
8062
8063 /* Check broadcasts. */
8064 if (strncmp (op_string, "1to", 3) == 0)
8065 {
8066 int bcst_type;
8067
8068 if (i.broadcast)
8069 goto duplicated_vec_op;
8070
8071 op_string += 3;
8072 if (*op_string == '8')
8073 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 8074 else if (*op_string == '4')
8075 bcst_type = BROADCAST_1TO4;
8076 else if (*op_string == '2')
8077 bcst_type = BROADCAST_1TO2;
43234a1e
L		 8078 else if (*op_string == '1'
8079 && *(op_string+1) == '6')
8080 {
8081 bcst_type = BROADCAST_1TO16;
8082 op_string++;
8083 }
8084 else
8085 {
8086 as_bad (_("Unsupported broadcast: `%s'"), saved);
8087 return NULL;
8088 }
8089 op_string++;
8090
8091 broadcast_op.type = bcst_type;
8092 broadcast_op.operand = this_operand;
8093 i.broadcast = &broadcast_op;
8094 }
8095 /* Check masking operation. */
8096 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8097 {
8098 /* k0 can't be used for write mask. */
6d2cd6b2 8099 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
43234a1e 8100 {
6d2cd6b2
JB		 8101 as_bad (_("`%s%s' can't be used for write mask"),
8102 register_prefix, mask->reg_name);
43234a1e
L		 8103 return NULL;
8104 }
8105
8106 if (!i.mask)
8107 {
8108 mask_op.mask = mask;
8109 mask_op.zeroing = 0;
8110 mask_op.operand = this_operand;
8111 i.mask = &mask_op;
8112 }
8113 else
8114 {
8115 if (i.mask->mask)
8116 goto duplicated_vec_op;
8117
8118 i.mask->mask = mask;
8119
8120 /* Only "{z}" is allowed here. No need to check
8121 zeroing mask explicitly. */
8122 if (i.mask->operand != this_operand)
8123 {
8124 as_bad (_("invalid write mask `%s'"), saved);
8125 return NULL;
8126 }
8127 }
8128
8129 op_string = end_op;
8130 }
8131 /* Check zeroing-flag for masking operation. */
8132 else if (*op_string == 'z')
8133 {
8134 if (!i.mask)
8135 {
8136 mask_op.mask = NULL;
8137 mask_op.zeroing = 1;
8138 mask_op.operand = this_operand;
8139 i.mask = &mask_op;
8140 }
8141 else
8142 {
8143 if (i.mask->zeroing)
8144 {
8145 duplicated_vec_op:
8146 as_bad (_("duplicated `%s'"), saved);
8147 return NULL;
8148 }
8149
8150 i.mask->zeroing = 1;
8151
8152 /* Only "{%k}" is allowed here. No need to check mask
8153 register explicitly. */
8154 if (i.mask->operand != this_operand)
8155 {
8156 as_bad (_("invalid zeroing-masking `%s'"),
8157 saved);
8158 return NULL;
8159 }
8160 }
8161
8162 op_string++;
8163 }
8164 else
8165 goto unknown_vec_op;
8166
8167 if (*op_string != '}')
8168 {
8169 as_bad (_("missing `}' in `%s'"), saved);
8170 return NULL;
8171 }
8172 op_string++;
8173 continue;
8174 }
8175 unknown_vec_op:
8176 /* We don't know this one. */
8177 as_bad (_("unknown vector operation: `%s'"), saved);
8178 return NULL;
8179 }
8180
6d2cd6b2
JB		 8181 if (i.mask && i.mask->zeroing && !i.mask->mask)
8182 {
8183 as_bad (_("zeroing-masking only allowed with write mask"));
8184 return NULL;
8185 }
8186
43234a1e
L		 8187 return op_string;
8188}
8189
252b5132 8190static int
70e41ade 8191i386_immediate (char *imm_start)
252b5132
RH		 8192{
8193 char *save_input_line_pointer;
f3c180ae 8194 char *gotfree_input_line;
252b5132 8195 segT exp_seg = 0;
47926f60 8196 expressionS *exp;
40fb9820
L		 8197 i386_operand_type types;
8198
0dfbf9d7 8199 operand_type_set (&types, ~0);
252b5132
RH		 8200
8201 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8202 {
31b2323c
L		 8203 as_bad (_("at most %d immediate operands are allowed"),
8204 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8205 return 0;
8206 }
8207
8208 exp = &im_expressions[i.imm_operands++];
520dc8e8 8209 i.op[this_operand].imms = exp;
252b5132
RH		 8210
8211 if (is_space_char (*imm_start))
8212 ++imm_start;
8213
8214 save_input_line_pointer = input_line_pointer;
8215 input_line_pointer = imm_start;
8216
d258b828 8217 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8218 if (gotfree_input_line)
8219 input_line_pointer = gotfree_input_line;
252b5132
RH		 8220
8221 exp_seg = expression (exp);
8222
83183c0c 8223 SKIP_WHITESPACE ();
43234a1e
L		 8224
8225 /* Handle vector operations. */
8226 if (*input_line_pointer == '{')
8227 {
8228 input_line_pointer = check_VecOperations (input_line_pointer,
8229 NULL);
8230 if (input_line_pointer == NULL)
8231 return 0;
8232 }
8233
252b5132 8234 if (*input_line_pointer)
f3c180ae 8235 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8236
8237 input_line_pointer = save_input_line_pointer;
f3c180ae 8238 if (gotfree_input_line)
ee86248c
JB		 8239 {
8240 free (gotfree_input_line);
8241
8242 if (exp->X_op == O_constant || exp->X_op == O_register)
8243 exp->X_op = O_illegal;
8244 }
8245
8246 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8247}
252b5132 8248
ee86248c
JB		 8249static int
8250i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8251 i386_operand_type types, const char *imm_start)
8252{
8253 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8254 {
313c53d1
L		 8255 if (imm_start)
8256 as_bad (_("missing or invalid immediate expression `%s'"),
8257 imm_start);
3992d3b7 8258 return 0;
252b5132 8259 }
3e73aa7c 8260 else if (exp->X_op == O_constant)
252b5132 8261 {
47926f60 8262 /* Size it properly later. */
40fb9820 8263 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8264 /* If not 64bit, sign extend val. */
8265 if (flag_code != CODE_64BIT
4eed87de
AM		 8266 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8267 exp->X_add_number
8268 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8269 }
4c63da97 8270#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8271 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8272 && exp_seg != absolute_section
47926f60 8273 && exp_seg != text_section
24eab124
AM		 8274 && exp_seg != data_section
8275 && exp_seg != bss_section
8276 && exp_seg != undefined_section
f86103b7 8277 && !bfd_is_com_section (exp_seg))
252b5132 8278 {
d0b47220 8279 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8280 return 0;
8281 }
8282#endif
a841bdf5 8283 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8284 {
313c53d1
L		 8285 if (imm_start)
8286 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8287 return 0;
8288 }
252b5132
RH		 8289 else
8290 {
8291 /* This is an address. The size of the address will be
24eab124 8292 determined later, depending on destination register,
3e73aa7c 8293 suffix, or the default for the section. */
40fb9820
L		 8294 i.types[this_operand].bitfield.imm8 = 1;
8295 i.types[this_operand].bitfield.imm16 = 1;
8296 i.types[this_operand].bitfield.imm32 = 1;
8297 i.types[this_operand].bitfield.imm32s = 1;
8298 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8299 i.types[this_operand] = operand_type_and (i.types[this_operand],
8300 types);
252b5132
RH		 8301 }
8302
8303 return 1;
8304}
8305
551c1ca1 8306static char *
e3bb37b5 8307i386_scale (char *scale)
252b5132 8308{
551c1ca1
AM		 8309 offsetT val;
8310 char *save = input_line_pointer;
252b5132 8311
551c1ca1
AM		 8312 input_line_pointer = scale;
8313 val = get_absolute_expression ();
8314
8315 switch (val)
252b5132 8316 {
551c1ca1 8317 case 1:
252b5132
RH		 8318 i.log2_scale_factor = 0;
8319 break;
551c1ca1 8320 case 2:
252b5132
RH		 8321 i.log2_scale_factor = 1;
8322 break;
551c1ca1 8323 case 4:
252b5132
RH		 8324 i.log2_scale_factor = 2;
8325 break;
551c1ca1 8326 case 8:
252b5132
RH		 8327 i.log2_scale_factor = 3;
8328 break;
8329 default:
a724f0f4
JB		 8330 {
8331 char sep = *input_line_pointer;
8332
8333 *input_line_pointer = '\0';
8334 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8335 scale);
8336 *input_line_pointer = sep;
8337 input_line_pointer = save;
8338 return NULL;
8339 }
252b5132 8340 }
29b0f896 8341 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8342 {
8343 as_warn (_("scale factor of %d without an index register"),
24eab124 8344 1 << i.log2_scale_factor);
252b5132 8345 i.log2_scale_factor = 0;
252b5132 8346 }
551c1ca1
AM		 8347 scale = input_line_pointer;
8348 input_line_pointer = save;
8349 return scale;
252b5132
RH		 8350}
8351
252b5132 8352static int
e3bb37b5 8353i386_displacement (char *disp_start, char *disp_end)
252b5132 8354{
29b0f896 8355 expressionS *exp;
252b5132
RH		 8356 segT exp_seg = 0;
8357 char *save_input_line_pointer;
f3c180ae 8358 char *gotfree_input_line;
40fb9820
L		 8359 int override;
8360 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8361 int ret;
252b5132 8362
31b2323c
L		 8363 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8364 {
8365 as_bad (_("at most %d displacement operands are allowed"),
8366 MAX_MEMORY_OPERANDS);
8367 return 0;
8368 }
8369
0dfbf9d7 8370 operand_type_set (&bigdisp, 0);
40fb9820
L		 8371 if ((i.types[this_operand].bitfield.jumpabsolute)
8372 || (!current_templates->start->opcode_modifier.jump
8373 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8374 {
40fb9820 8375 bigdisp.bitfield.disp32 = 1;
e05278af 8376 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8377 if (flag_code == CODE_64BIT)
8378 {
8379 if (!override)
8380 {
8381 bigdisp.bitfield.disp32s = 1;
8382 bigdisp.bitfield.disp64 = 1;
8383 }
8384 }
8385 else if ((flag_code == CODE_16BIT) ^ override)
8386 {
8387 bigdisp.bitfield.disp32 = 0;
8388 bigdisp.bitfield.disp16 = 1;
8389 }
e05278af
JB		 8390 }
8391 else
8392 {
8393 /* For PC-relative branches, the width of the displacement
8394 is dependent upon data size, not address size. */
e05278af 8395 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8396 if (flag_code == CODE_64BIT)
8397 {
8398 if (override || i.suffix == WORD_MNEM_SUFFIX)
8399 bigdisp.bitfield.disp16 = 1;
8400 else
8401 {
8402 bigdisp.bitfield.disp32 = 1;
8403 bigdisp.bitfield.disp32s = 1;
8404 }
8405 }
8406 else
e05278af
JB		 8407 {
8408 if (!override)
8409 override = (i.suffix == (flag_code != CODE_16BIT
8410 ? WORD_MNEM_SUFFIX
8411 : LONG_MNEM_SUFFIX));
40fb9820
L		 8412 bigdisp.bitfield.disp32 = 1;
8413 if ((flag_code == CODE_16BIT) ^ override)
8414 {
8415 bigdisp.bitfield.disp32 = 0;
8416 bigdisp.bitfield.disp16 = 1;
8417 }
e05278af 8418 }
e05278af 8419 }
c6fb90c8
L		 8420 i.types[this_operand] = operand_type_or (i.types[this_operand],
8421 bigdisp);
252b5132
RH		 8422
8423 exp = &disp_expressions[i.disp_operands];
520dc8e8 8424 i.op[this_operand].disps = exp;
252b5132
RH		 8425 i.disp_operands++;
8426 save_input_line_pointer = input_line_pointer;
8427 input_line_pointer = disp_start;
8428 END_STRING_AND_SAVE (disp_end);
8429
8430#ifndef GCC_ASM_O_HACK
8431#define GCC_ASM_O_HACK 0
8432#endif
8433#if GCC_ASM_O_HACK
8434 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8435 if (i.types[this_operand].bitfield.baseIndex
24eab124 8436 && displacement_string_end[-1] == '+')
252b5132
RH		 8437 {
8438 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8439 constraint within gcc asm statements.
8440 For instance:
8441
8442 #define _set_tssldt_desc(n,addr,limit,type) \
8443 __asm__ __volatile__ ( \
8444 "movw %w2,%0\n\t" \
8445 "movw %w1,2+%0\n\t" \
8446 "rorl $16,%1\n\t" \
8447 "movb %b1,4+%0\n\t" \
8448 "movb %4,5+%0\n\t" \
8449 "movb $0,6+%0\n\t" \
8450 "movb %h1,7+%0\n\t" \
8451 "rorl $16,%1" \
8452 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8453
8454 This works great except that the output assembler ends
8455 up looking a bit weird if it turns out that there is
8456 no offset. You end up producing code that looks like:
8457
8458 #APP
8459 movw $235,(%eax)
8460 movw %dx,2+(%eax)
8461 rorl $16,%edx
8462 movb %dl,4+(%eax)
8463 movb $137,5+(%eax)
8464 movb $0,6+(%eax)
8465 movb %dh,7+(%eax)
8466 rorl $16,%edx
8467 #NO_APP
8468
47926f60 8469 So here we provide the missing zero. */
24eab124
AM		 8470
8471 *displacement_string_end = '0';
252b5132
RH		 8472 }
8473#endif
d258b828 8474 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8475 if (gotfree_input_line)
8476 input_line_pointer = gotfree_input_line;
252b5132 8477
24eab124 8478 exp_seg = expression (exp);
252b5132 8479
636c26b0
AM		 8480 SKIP_WHITESPACE ();
8481 if (*input_line_pointer)
8482 as_bad (_("junk `%s' after expression"), input_line_pointer);
8483#if GCC_ASM_O_HACK
8484 RESTORE_END_STRING (disp_end + 1);
8485#endif
636c26b0 8486 input_line_pointer = save_input_line_pointer;
636c26b0 8487 if (gotfree_input_line)
ee86248c
JB		 8488 {
8489 free (gotfree_input_line);
8490
8491 if (exp->X_op == O_constant || exp->X_op == O_register)
8492 exp->X_op = O_illegal;
8493 }
8494
8495 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8496
8497 RESTORE_END_STRING (disp_end);
8498
8499 return ret;
8500}
8501
8502static int
8503i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8504 i386_operand_type types, const char *disp_start)
8505{
8506 i386_operand_type bigdisp;
8507 int ret = 1;
636c26b0 8508
24eab124
AM		 8509 /* We do this to make sure that the section symbol is in
8510 the symbol table. We will ultimately change the relocation
47926f60 8511 to be relative to the beginning of the section. */
1ae12ab7 8512 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8513 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8514 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8515 {
636c26b0 8516 if (exp->X_op != O_symbol)
3992d3b7 8517 goto inv_disp;
636c26b0 8518
e5cb08ac 8519 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8520 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8521 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8522 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8523 exp->X_op = O_subtract;
8524 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8525 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8526 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8527 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8528 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8529 else
29b0f896 8530 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8531 }
252b5132 8532
3992d3b7
AM		 8533 else if (exp->X_op == O_absent
8534 || exp->X_op == O_illegal
ee86248c 8535 || exp->X_op == O_big)
2daf4fd8 8536 {
3992d3b7
AM		 8537 inv_disp:
8538 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8539 disp_start);
3992d3b7 8540 ret = 0;
2daf4fd8
AM		 8541 }
8542
0e1147d9
L		 8543 else if (flag_code == CODE_64BIT
8544 && !i.prefix[ADDR_PREFIX]
8545 && exp->X_op == O_constant)
8546 {
8547 /* Since displacement is signed extended to 64bit, don't allow
8548 disp32 and turn off disp32s if they are out of range. */
8549 i.types[this_operand].bitfield.disp32 = 0;
8550 if (!fits_in_signed_long (exp->X_add_number))
8551 {
8552 i.types[this_operand].bitfield.disp32s = 0;
8553 if (i.types[this_operand].bitfield.baseindex)
8554 {
8555 as_bad (_("0x%lx out range of signed 32bit displacement"),
8556 (long) exp->X_add_number);
8557 ret = 0;
8558 }
8559 }
8560 }
8561
4c63da97 8562#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8563 else if (exp->X_op != O_constant
8564 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8565 && exp_seg != absolute_section
8566 && exp_seg != text_section
8567 && exp_seg != data_section
8568 && exp_seg != bss_section
8569 && exp_seg != undefined_section
8570 && !bfd_is_com_section (exp_seg))
24eab124 8571 {
d0b47220 8572 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8573 ret = 0;
24eab124 8574 }
252b5132 8575#endif
3956db08 8576
40fb9820
L		 8577 /* Check if this is a displacement only operand. */
8578 bigdisp = i.types[this_operand];
8579 bigdisp.bitfield.disp8 = 0;
8580 bigdisp.bitfield.disp16 = 0;
8581 bigdisp.bitfield.disp32 = 0;
8582 bigdisp.bitfield.disp32s = 0;
8583 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8584 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8585 i.types[this_operand] = operand_type_and (i.types[this_operand],
8586 types);
3956db08 8587
3992d3b7 8588 return ret;
252b5132
RH		 8589}
8590
2abc2bec
JB		 8591/* Return the active addressing mode, taking address override and
8592 registers forming the address into consideration. Update the
8593 address override prefix if necessary. */
47926f60 8594
2abc2bec
JB		 8595static enum flag_code
8596i386_addressing_mode (void)
252b5132 8597{
be05d201
L		 8598 enum flag_code addr_mode;
8599
8600 if (i.prefix[ADDR_PREFIX])
8601 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8602 else
8603 {
8604 addr_mode = flag_code;
8605
24eab124 8606#if INFER_ADDR_PREFIX
be05d201
L		 8607 if (i.mem_operands == 0)
8608 {
8609 /* Infer address prefix from the first memory operand. */
8610 const reg_entry *addr_reg = i.base_reg;
8611
8612 if (addr_reg == NULL)
8613 addr_reg = i.index_reg;
eecb386c 8614
be05d201
L		 8615 if (addr_reg)
8616 {
8617 if (addr_reg->reg_num == RegEip
8618 || addr_reg->reg_num == RegEiz
dc821c5f 8619 || addr_reg->reg_type.bitfield.dword)
be05d201
L		 8620 addr_mode = CODE_32BIT;
8621 else if (flag_code != CODE_64BIT
dc821c5f 8622 && addr_reg->reg_type.bitfield.word)
be05d201
L		 8623 addr_mode = CODE_16BIT;
8624
8625 if (addr_mode != flag_code)
8626 {
8627 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8628 i.prefixes += 1;
8629 /* Change the size of any displacement too. At most one
8630 of Disp16 or Disp32 is set.
8631 FIXME. There doesn't seem to be any real need for
8632 separate Disp16 and Disp32 flags. The same goes for
8633 Imm16 and Imm32. Removing them would probably clean
8634 up the code quite a lot. */
8635 if (flag_code != CODE_64BIT
8636 && (i.types[this_operand].bitfield.disp16
8637 || i.types[this_operand].bitfield.disp32))
8638 i.types[this_operand]
8639 = operand_type_xor (i.types[this_operand], disp16_32);
8640 }
8641 }
8642 }
24eab124 8643#endif
be05d201
L		 8644 }
8645
2abc2bec
JB		 8646 return addr_mode;
8647}
8648
8649/* Make sure the memory operand we've been dealt is valid.
8650 Return 1 on success, 0 on a failure. */
8651
8652static int
8653i386_index_check (const char *operand_string)
8654{
8655 const char *kind = "base/index";
8656 enum flag_code addr_mode = i386_addressing_mode ();
8657
fc0763e6
JB		 8658 if (current_templates->start->opcode_modifier.isstring
8659 && !current_templates->start->opcode_modifier.immext
8660 && (current_templates->end[-1].opcode_modifier.isstring
8661 || i.mem_operands))
8662 {
8663 /* Memory operands of string insns are special in that they only allow
8664 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8665 const reg_entry *expected_reg;
8666 static const char *di_si[][2] =
8667 {
8668 { "esi", "edi" },
8669 { "si", "di" },
8670 { "rsi", "rdi" }
8671 };
8672 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8673
8674 kind = "string address";
8675
8325cc63 8676 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 8677 {
8678 i386_operand_type type = current_templates->end[-1].operand_types[0];
8679
8680 if (!type.bitfield.baseindex
8681 || ((!i.mem_operands != !intel_syntax)
8682 && current_templates->end[-1].operand_types[1]
8683 .bitfield.baseindex))
8684 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8685 expected_reg = hash_find (reg_hash,
8686 di_si[addr_mode][type.bitfield.esseg]);
8687
fc0763e6
JB		 8688 }
8689 else
be05d201 8690 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8691
be05d201
L		 8692 if (i.base_reg != expected_reg
8693 || i.index_reg
fc0763e6 8694 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8695 {
be05d201
L		 8696 /* The second memory operand must have the same size as
8697 the first one. */
8698 if (i.mem_operands
8699 && i.base_reg
8700 && !((addr_mode == CODE_64BIT
dc821c5f 8701 && i.base_reg->reg_type.bitfield.qword)
be05d201 8702 || (addr_mode == CODE_32BIT
dc821c5f
JB		 8703 ? i.base_reg->reg_type.bitfield.dword
8704 : i.base_reg->reg_type.bitfield.word)))
be05d201
L		 8705 goto bad_address;
8706
fc0763e6
JB		 8707 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8708 operand_string,
8709 intel_syntax ? '[' : '(',
8710 register_prefix,
be05d201 8711 expected_reg->reg_name,
fc0763e6 8712 intel_syntax ? ']' : ')');
be05d201 8713 return 1;
fc0763e6 8714 }
be05d201
L		 8715 else
8716 return 1;
8717
8718bad_address:
8719 as_bad (_("`%s' is not a valid %s expression"),
8720 operand_string, kind);
8721 return 0;
3e73aa7c
JH		 8722 }
8723 else
8724 {
be05d201
L		 8725 if (addr_mode != CODE_16BIT)
8726 {
8727 /* 32-bit/64-bit checks. */
8728 if ((i.base_reg
8729 && (addr_mode == CODE_64BIT
dc821c5f
JB		 8730 ? !i.base_reg->reg_type.bitfield.qword
8731 : !i.base_reg->reg_type.bitfield.dword)
be05d201
L		 8732 && (i.index_reg
8733 || (i.base_reg->reg_num
8734 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8735 || (i.index_reg
1b54b8d7
JB		 8736 && !i.index_reg->reg_type.bitfield.xmmword
8737 && !i.index_reg->reg_type.bitfield.ymmword
8738 && !i.index_reg->reg_type.bitfield.zmmword
be05d201 8739 && ((addr_mode == CODE_64BIT
dc821c5f 8740 ? !(i.index_reg->reg_type.bitfield.qword
be05d201 8741 || i.index_reg->reg_num == RegRiz)
dc821c5f 8742 : !(i.index_reg->reg_type.bitfield.dword
be05d201
L		 8743 || i.index_reg->reg_num == RegEiz))
8744 || !i.index_reg->reg_type.bitfield.baseindex)))
8745 goto bad_address;
8178be5b
JB		 8746
8747 /* bndmk, bndldx, and bndstx have special restrictions. */
8748 if (current_templates->start->base_opcode == 0xf30f1b
8749 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
8750 {
8751 /* They cannot use RIP-relative addressing. */
8752 if (i.base_reg && i.base_reg->reg_num == RegRip)
8753 {
8754 as_bad (_("`%s' cannot be used here"), operand_string);
8755 return 0;
8756 }
8757
8758 /* bndldx and bndstx ignore their scale factor. */
8759 if (current_templates->start->base_opcode != 0xf30f1b
8760 && i.log2_scale_factor)
8761 as_warn (_("register scaling is being ignored here"));
8762 }
be05d201
L		 8763 }
8764 else
3e73aa7c 8765 {
be05d201 8766 /* 16-bit checks. */
3e73aa7c 8767 if ((i.base_reg
dc821c5f 8768 && (!i.base_reg->reg_type.bitfield.word
40fb9820 8769 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8770 || (i.index_reg
dc821c5f 8771 && (!i.index_reg->reg_type.bitfield.word
40fb9820 8772 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8773 || !(i.base_reg
8774 && i.base_reg->reg_num < 6
8775 && i.index_reg->reg_num >= 6
8776 && i.log2_scale_factor == 0))))
be05d201 8777 goto bad_address;
3e73aa7c
JH		 8778 }
8779 }
be05d201 8780 return 1;
24eab124 8781}
252b5132 8782
43234a1e
L		 8783/* Handle vector immediates. */
8784
8785static int
8786RC_SAE_immediate (const char *imm_start)
8787{
8788 unsigned int match_found, j;
8789 const char *pstr = imm_start;
8790 expressionS *exp;
8791
8792 if (*pstr != '{')
8793 return 0;
8794
8795 pstr++;
8796 match_found = 0;
8797 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8798 {
8799 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8800 {
8801 if (!i.rounding)
8802 {
8803 rc_op.type = RC_NamesTable[j].type;
8804 rc_op.operand = this_operand;
8805 i.rounding = &rc_op;
8806 }
8807 else
8808 {
8809 as_bad (_("duplicated `%s'"), imm_start);
8810 return 0;
8811 }
8812 pstr += RC_NamesTable[j].len;
8813 match_found = 1;
8814 break;
8815 }
8816 }
8817 if (!match_found)
8818 return 0;
8819
8820 if (*pstr++ != '}')
8821 {
8822 as_bad (_("Missing '}': '%s'"), imm_start);
8823 return 0;
8824 }
8825 /* RC/SAE immediate string should contain nothing more. */;
8826 if (*pstr != 0)
8827 {
8828 as_bad (_("Junk after '}': '%s'"), imm_start);
8829 return 0;
8830 }
8831
8832 exp = &im_expressions[i.imm_operands++];
8833 i.op[this_operand].imms = exp;
8834
8835 exp->X_op = O_constant;
8836 exp->X_add_number = 0;
8837 exp->X_add_symbol = (symbolS *) 0;
8838 exp->X_op_symbol = (symbolS *) 0;
8839
8840 i.types[this_operand].bitfield.imm8 = 1;
8841 return 1;
8842}
8843
8325cc63
JB		 8844/* Only string instructions can have a second memory operand, so
8845 reduce current_templates to just those if it contains any. */
8846static int
8847maybe_adjust_templates (void)
8848{
8849 const insn_template *t;
8850
8851 gas_assert (i.mem_operands == 1);
8852
8853 for (t = current_templates->start; t < current_templates->end; ++t)
8854 if (t->opcode_modifier.isstring)
8855 break;
8856
8857 if (t < current_templates->end)
8858 {
8859 static templates aux_templates;
8860 bfd_boolean recheck;
8861
8862 aux_templates.start = t;
8863 for (; t < current_templates->end; ++t)
8864 if (!t->opcode_modifier.isstring)
8865 break;
8866 aux_templates.end = t;
8867
8868 /* Determine whether to re-check the first memory operand. */
8869 recheck = (aux_templates.start != current_templates->start
8870 || t != current_templates->end);
8871
8872 current_templates = &aux_templates;
8873
8874 if (recheck)
8875 {
8876 i.mem_operands = 0;
8877 if (i.memop1_string != NULL
8878 && i386_index_check (i.memop1_string) == 0)
8879 return 0;
8880 i.mem_operands = 1;
8881 }
8882 }
8883
8884 return 1;
8885}
8886
fc0763e6 8887/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8888 on error. */
252b5132 8889
252b5132 8890static int
a7619375 8891i386_att_operand (char *operand_string)
252b5132 8892{
af6bdddf
AM		 8893 const reg_entry *r;
8894 char *end_op;
24eab124 8895 char *op_string = operand_string;
252b5132 8896
24eab124 8897 if (is_space_char (*op_string))
252b5132
RH		 8898 ++op_string;
8899
24eab124 8900 /* We check for an absolute prefix (differentiating,
47926f60 8901 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8902 if (*op_string == ABSOLUTE_PREFIX)
8903 {
8904 ++op_string;
8905 if (is_space_char (*op_string))
8906 ++op_string;
40fb9820 8907 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8908 }
252b5132 8909
47926f60 8910 /* Check if operand is a register. */
4d1bb795 8911 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8912 {
40fb9820
L		 8913 i386_operand_type temp;
8914
24eab124
AM		 8915 /* Check for a segment override by searching for ':' after a
8916 segment register. */
8917 op_string = end_op;
8918 if (is_space_char (*op_string))
8919 ++op_string;
40fb9820
L		 8920 if (*op_string == ':'
8921 && (r->reg_type.bitfield.sreg2
8922 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8923 {
8924 switch (r->reg_num)
8925 {
8926 case 0:
8927 i.seg[i.mem_operands] = &es;
8928 break;
8929 case 1:
8930 i.seg[i.mem_operands] = &cs;
8931 break;
8932 case 2:
8933 i.seg[i.mem_operands] = &ss;
8934 break;
8935 case 3:
8936 i.seg[i.mem_operands] = &ds;
8937 break;
8938 case 4:
8939 i.seg[i.mem_operands] = &fs;
8940 break;
8941 case 5:
8942 i.seg[i.mem_operands] = &gs;
8943 break;
8944 }
252b5132 8945
24eab124 8946 /* Skip the ':' and whitespace. */
252b5132
RH		 8947 ++op_string;
8948 if (is_space_char (*op_string))
24eab124 8949 ++op_string;
252b5132 8950
24eab124
AM		 8951 if (!is_digit_char (*op_string)
8952 && !is_identifier_char (*op_string)
8953 && *op_string != '('
8954 && *op_string != ABSOLUTE_PREFIX)
8955 {
8956 as_bad (_("bad memory operand `%s'"), op_string);
8957 return 0;
8958 }
47926f60 8959 /* Handle case of %es:*foo. */
24eab124
AM		 8960 if (*op_string == ABSOLUTE_PREFIX)
8961 {
8962 ++op_string;
8963 if (is_space_char (*op_string))
8964 ++op_string;
40fb9820 8965 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8966 }
8967 goto do_memory_reference;
8968 }
43234a1e
L		 8969
8970 /* Handle vector operations. */
8971 if (*op_string == '{')
8972 {
8973 op_string = check_VecOperations (op_string, NULL);
8974 if (op_string == NULL)
8975 return 0;
8976 }
8977
24eab124
AM		 8978 if (*op_string)
8979 {
d0b47220 8980 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8981 return 0;
8982 }
40fb9820
L		 8983 temp = r->reg_type;
8984 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8985 i.types[this_operand] = operand_type_or (i.types[this_operand],
8986 temp);
7d5e4556 8987 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8988 i.op[this_operand].regs = r;
24eab124
AM		 8989 i.reg_operands++;
8990 }
af6bdddf
AM		 8991 else if (*op_string == REGISTER_PREFIX)
8992 {
8993 as_bad (_("bad register name `%s'"), op_string);
8994 return 0;
8995 }
24eab124 8996 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8997 {
24eab124 8998 ++op_string;
40fb9820 8999 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 9000 {
d0b47220 9001 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 9002 return 0;
9003 }
9004 if (!i386_immediate (op_string))
9005 return 0;
9006 }
43234a1e
L		 9007 else if (RC_SAE_immediate (operand_string))
9008 {
9009 /* If it is a RC or SAE immediate, do nothing. */
9010 ;
9011 }
24eab124
AM		 9012 else if (is_digit_char (*op_string)
9013 || is_identifier_char (*op_string)
d02603dc 9014 || *op_string == '"'
e5cb08ac 9015 || *op_string == '(')
24eab124 9016 {
47926f60 9017 /* This is a memory reference of some sort. */
af6bdddf 9018 char *base_string;
252b5132 9019
47926f60 9020 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 9021 char *displacement_string_start;
9022 char *displacement_string_end;
43234a1e 9023 char *vop_start;
252b5132 9024
24eab124 9025 do_memory_reference:
8325cc63
JB		 9026 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9027 return 0;
24eab124 9028 if ((i.mem_operands == 1
40fb9820 9029 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 9030 || i.mem_operands == 2)
9031 {
9032 as_bad (_("too many memory references for `%s'"),
9033 current_templates->start->name);
9034 return 0;
9035 }
252b5132 9036
24eab124
AM		 9037 /* Check for base index form. We detect the base index form by
9038 looking for an ')' at the end of the operand, searching
9039 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9040 after the '('. */
af6bdddf 9041 base_string = op_string + strlen (op_string);
c3332e24 9042
43234a1e
L		 9043 /* Handle vector operations. */
9044 vop_start = strchr (op_string, '{');
9045 if (vop_start && vop_start < base_string)
9046 {
9047 if (check_VecOperations (vop_start, base_string) == NULL)
9048 return 0;
9049 base_string = vop_start;
9050 }
9051
af6bdddf
AM		 9052 --base_string;
9053 if (is_space_char (*base_string))
9054 --base_string;
252b5132 9055
47926f60 9056 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 9057 displacement_string_start = op_string;
9058 displacement_string_end = base_string + 1;
252b5132 9059
24eab124
AM		 9060 if (*base_string == ')')
9061 {
af6bdddf 9062 char *temp_string;
24eab124
AM		 9063 unsigned int parens_balanced = 1;
9064 /* We've already checked that the number of left & right ()'s are
47926f60 9065 equal, so this loop will not be infinite. */
24eab124
AM		 9066 do
9067 {
9068 base_string--;
9069 if (*base_string == ')')
9070 parens_balanced++;
9071 if (*base_string == '(')
9072 parens_balanced--;
9073 }
9074 while (parens_balanced);
c3332e24 9075
af6bdddf 9076 temp_string = base_string;
c3332e24 9077
24eab124 9078 /* Skip past '(' and whitespace. */
252b5132
RH		 9079 ++base_string;
9080 if (is_space_char (*base_string))
24eab124 9081 ++base_string;
252b5132 9082
af6bdddf 9083 if (*base_string == ','
4eed87de
AM		 9084 || ((i.base_reg = parse_register (base_string, &end_op))
9085 != NULL))
252b5132 9086 {
af6bdddf 9087 displacement_string_end = temp_string;
252b5132 9088
40fb9820 9089 i.types[this_operand].bitfield.baseindex = 1;
252b5132 9090
af6bdddf 9091 if (i.base_reg)
24eab124 9092 {
24eab124
AM		 9093 base_string = end_op;
9094 if (is_space_char (*base_string))
9095 ++base_string;
af6bdddf
AM		 9096 }
9097
9098 /* There may be an index reg or scale factor here. */
9099 if (*base_string == ',')
9100 {
9101 ++base_string;
9102 if (is_space_char (*base_string))
9103 ++base_string;
9104
4eed87de
AM		 9105 if ((i.index_reg = parse_register (base_string, &end_op))
9106 != NULL)
24eab124 9107 {
af6bdddf 9108 base_string = end_op;
24eab124
AM		 9109 if (is_space_char (*base_string))
9110 ++base_string;
af6bdddf
AM		 9111 if (*base_string == ',')
9112 {
9113 ++base_string;
9114 if (is_space_char (*base_string))
9115 ++base_string;
9116 }
e5cb08ac 9117 else if (*base_string != ')')
af6bdddf 9118 {
4eed87de
AM		 9119 as_bad (_("expecting `,' or `)' "
9120 "after index register in `%s'"),
af6bdddf
AM		 9121 operand_string);
9122 return 0;
9123 }
24eab124 9124 }
af6bdddf 9125 else if (*base_string == REGISTER_PREFIX)
24eab124 9126 {
f76bf5e0
L		 9127 end_op = strchr (base_string, ',');
9128 if (end_op)
9129 *end_op = '\0';
af6bdddf 9130 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 9131 return 0;
9132 }
252b5132 9133
47926f60 9134 /* Check for scale factor. */
551c1ca1 9135 if (*base_string != ')')
af6bdddf 9136 {
551c1ca1
AM		 9137 char *end_scale = i386_scale (base_string);
9138
9139 if (!end_scale)
af6bdddf 9140 return 0;
24eab124 9141
551c1ca1 9142 base_string = end_scale;
af6bdddf
AM		 9143 if (is_space_char (*base_string))
9144 ++base_string;
9145 if (*base_string != ')')
9146 {
4eed87de
AM		 9147 as_bad (_("expecting `)' "
9148 "after scale factor in `%s'"),
af6bdddf
AM		 9149 operand_string);
9150 return 0;
9151 }
9152 }
9153 else if (!i.index_reg)
24eab124 9154 {
4eed87de
AM		 9155 as_bad (_("expecting index register or scale factor "
9156 "after `,'; got '%c'"),
af6bdddf 9157 *base_string);
24eab124
AM		 9158 return 0;
9159 }
9160 }
af6bdddf 9161 else if (*base_string != ')')
24eab124 9162 {
4eed87de
AM		 9163 as_bad (_("expecting `,' or `)' "
9164 "after base register in `%s'"),
af6bdddf 9165 operand_string);
24eab124
AM		 9166 return 0;
9167 }
c3332e24 9168 }
af6bdddf 9169 else if (*base_string == REGISTER_PREFIX)
c3332e24 9170 {
f76bf5e0
L		 9171 end_op = strchr (base_string, ',');
9172 if (end_op)
9173 *end_op = '\0';
af6bdddf 9174 as_bad (_("bad register name `%s'"), base_string);
24eab124 9175 return 0;
c3332e24 9176 }
24eab124
AM		 9177 }
9178
9179 /* If there's an expression beginning the operand, parse it,
9180 assuming displacement_string_start and
9181 displacement_string_end are meaningful. */
9182 if (displacement_string_start != displacement_string_end)
9183 {
9184 if (!i386_displacement (displacement_string_start,
9185 displacement_string_end))
9186 return 0;
9187 }
9188
9189 /* Special case for (%dx) while doing input/output op. */
9190 if (i.base_reg
0dfbf9d7
L		 9191 && operand_type_equal (&i.base_reg->reg_type,
9192 &reg16_inoutportreg)
24eab124
AM		 9193 && i.index_reg == 0
9194 && i.log2_scale_factor == 0
9195 && i.seg[i.mem_operands] == 0
40fb9820 9196 && !operand_type_check (i.types[this_operand], disp))
24eab124 9197 {
65da13b5 9198 i.types[this_operand] = inoutportreg;
24eab124
AM		 9199 return 1;
9200 }
9201
eecb386c
AM		 9202 if (i386_index_check (operand_string) == 0)
9203 return 0;
5c07affc 9204 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9205 if (i.mem_operands == 0)
9206 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9207 i.mem_operands++;
9208 }
9209 else
ce8a8b2f
AM		 9210 {
9211 /* It's not a memory operand; argh! */
24eab124
AM		 9212 as_bad (_("invalid char %s beginning operand %d `%s'"),
9213 output_invalid (*op_string),
9214 this_operand + 1,
9215 op_string);
9216 return 0;
9217 }
47926f60 9218 return 1; /* Normal return. */
252b5132
RH		 9219}
9220\f
fa94de6b
RM		 9221/* Calculate the maximum variable size (i.e., excluding fr_fix)
9222 that an rs_machine_dependent frag may reach. */
9223
9224unsigned int
9225i386_frag_max_var (fragS *frag)
9226{
9227 /* The only relaxable frags are for jumps.
9228 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9229 gas_assert (frag->fr_type == rs_machine_dependent);
9230 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9231}
9232
b084df0b
L		 9233#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9234static int
8dcea932 9235elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9236{
9237 /* STT_GNU_IFUNC symbol must go through PLT. */
9238 if ((symbol_get_bfdsym (fr_symbol)->flags
9239 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9240 return 0;
9241
9242 if (!S_IS_EXTERNAL (fr_symbol))
9243 /* Symbol may be weak or local. */
9244 return !S_IS_WEAK (fr_symbol);
9245
8dcea932
L		 9246 /* Global symbols with non-default visibility can't be preempted. */
9247 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9248 return 1;
9249
9250 if (fr_var != NO_RELOC)
9251 switch ((enum bfd_reloc_code_real) fr_var)
9252 {
9253 case BFD_RELOC_386_PLT32:
9254 case BFD_RELOC_X86_64_PLT32:
33eaf5de 9255 /* Symbol with PLT relocation may be preempted. */
8dcea932
L		 9256 return 0;
9257 default:
9258 abort ();
9259 }
9260
b084df0b
L		 9261 /* Global symbols with default visibility in a shared library may be
9262 preempted by another definition. */
8dcea932 9263 return !shared;
b084df0b
L		 9264}
9265#endif
9266
ee7fcc42
AM		 9267/* md_estimate_size_before_relax()
9268
9269 Called just before relax() for rs_machine_dependent frags. The x86
9270 assembler uses these frags to handle variable size jump
9271 instructions.
9272
9273 Any symbol that is now undefined will not become defined.
9274 Return the correct fr_subtype in the frag.
9275 Return the initial "guess for variable size of frag" to caller.
9276 The guess is actually the growth beyond the fixed part. Whatever
9277 we do to grow the fixed or variable part contributes to our
9278 returned value. */
9279
252b5132 9280int
7016a5d5 9281md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9282{
252b5132 9283 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9284 check for un-relaxable symbols. On an ELF system, we can't relax
9285 an externally visible symbol, because it may be overridden by a
9286 shared library. */
9287 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9288#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9289 || (IS_ELF
8dcea932
L		 9290 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9291 fragP->fr_var))
fbeb56a4
DK		 9292#endif
9293#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9294 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9295 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9296#endif
9297 )
252b5132 9298 {
b98ef147
AM		 9299 /* Symbol is undefined in this segment, or we need to keep a
9300 reloc so that weak symbols can be overridden. */
9301 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9302 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9303 unsigned char *opcode;
9304 int old_fr_fix;
f6af82bd 9305
ee7fcc42 9306 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9307 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9308 else if (size == 2)
f6af82bd
AM		 9309 reloc_type = BFD_RELOC_16_PCREL;
9310 else
9311 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9312
ee7fcc42
AM		 9313 old_fr_fix = fragP->fr_fix;
9314 opcode = (unsigned char *) fragP->fr_opcode;
9315
fddf5b5b 9316 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9317 {
fddf5b5b
AM		 9318 case UNCOND_JUMP:
9319 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9320 opcode[0] = 0xe9;
252b5132 9321 fragP->fr_fix += size;
062cd5e7
AS		 9322 fix_new (fragP, old_fr_fix, size,
9323 fragP->fr_symbol,
9324 fragP->fr_offset, 1,
9325 reloc_type);
252b5132
RH		 9326 break;
9327
fddf5b5b 9328 case COND_JUMP86:
412167cb
AM		 9329 if (size == 2
9330 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9331 {
9332 /* Negate the condition, and branch past an
9333 unconditional jump. */
9334 opcode[0] ^= 1;
9335 opcode[1] = 3;
9336 /* Insert an unconditional jump. */
9337 opcode[2] = 0xe9;
9338 /* We added two extra opcode bytes, and have a two byte
9339 offset. */
9340 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9341 fix_new (fragP, old_fr_fix + 2, 2,
9342 fragP->fr_symbol,
9343 fragP->fr_offset, 1,
9344 reloc_type);
fddf5b5b
AM		 9345 break;
9346 }
9347 /* Fall through. */
9348
9349 case COND_JUMP:
412167cb
AM		 9350 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9351 {
3e02c1cc
AM		 9352 fixS *fixP;
9353
412167cb 9354 fragP->fr_fix += 1;
3e02c1cc
AM		 9355 fixP = fix_new (fragP, old_fr_fix, 1,
9356 fragP->fr_symbol,
9357 fragP->fr_offset, 1,
9358 BFD_RELOC_8_PCREL);
9359 fixP->fx_signed = 1;
412167cb
AM		 9360 break;
9361 }
93c2a809 9362
24eab124 9363 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9364 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9365 opcode[1] = opcode[0] + 0x10;
f6af82bd 9366 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9367 /* We've added an opcode byte. */
9368 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9369 fix_new (fragP, old_fr_fix + 1, size,
9370 fragP->fr_symbol,
9371 fragP->fr_offset, 1,
9372 reloc_type);
252b5132 9373 break;
fddf5b5b
AM		 9374
9375 default:
9376 BAD_CASE (fragP->fr_subtype);
9377 break;
252b5132
RH		 9378 }
9379 frag_wane (fragP);
ee7fcc42 9380 return fragP->fr_fix - old_fr_fix;
252b5132 9381 }
93c2a809 9382
93c2a809
AM		 9383 /* Guess size depending on current relax state. Initially the relax
9384 state will correspond to a short jump and we return 1, because
9385 the variable part of the frag (the branch offset) is one byte
9386 long. However, we can relax a section more than once and in that
9387 case we must either set fr_subtype back to the unrelaxed state,
9388 or return the value for the appropriate branch. */
9389 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9390}
9391
47926f60
KH		 9392/* Called after relax() is finished.
9393
9394 In: Address of frag.
9395 fr_type == rs_machine_dependent.
9396 fr_subtype is what the address relaxed to.
9397
9398 Out: Any fixSs and constants are set up.
9399 Caller will turn frag into a ".space 0". */
9400
252b5132 9401void
7016a5d5
TG		 9402md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9403 fragS *fragP)
252b5132 9404{
29b0f896 9405 unsigned char *opcode;
252b5132 9406 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9407 offsetT target_address;
9408 offsetT opcode_address;
252b5132 9409 unsigned int extension = 0;
847f7ad4 9410 offsetT displacement_from_opcode_start;
252b5132
RH		 9411
9412 opcode = (unsigned char *) fragP->fr_opcode;
9413
47926f60 9414 /* Address we want to reach in file space. */
252b5132 9415 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9416
47926f60 9417 /* Address opcode resides at in file space. */
252b5132
RH		 9418 opcode_address = fragP->fr_address + fragP->fr_fix;
9419
47926f60 9420 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9421 displacement_from_opcode_start = target_address - opcode_address;
9422
fddf5b5b 9423 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9424 {
47926f60
KH		 9425 /* Don't have to change opcode. */
9426 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9427 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9428 }
9429 else
9430 {
9431 if (no_cond_jump_promotion
9432 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9433 as_warn_where (fragP->fr_file, fragP->fr_line,
9434 _("long jump required"));
252b5132 9435
fddf5b5b
AM		 9436 switch (fragP->fr_subtype)
9437 {
9438 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9439 extension = 4; /* 1 opcode + 4 displacement */
9440 opcode[0] = 0xe9;
9441 where_to_put_displacement = &opcode[1];
9442 break;
252b5132 9443
fddf5b5b
AM		 9444 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9445 extension = 2; /* 1 opcode + 2 displacement */
9446 opcode[0] = 0xe9;
9447 where_to_put_displacement = &opcode[1];
9448 break;
252b5132 9449
fddf5b5b
AM		 9450 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9451 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9452 extension = 5; /* 2 opcode + 4 displacement */
9453 opcode[1] = opcode[0] + 0x10;
9454 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9455 where_to_put_displacement = &opcode[2];
9456 break;
252b5132 9457
fddf5b5b
AM		 9458 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9459 extension = 3; /* 2 opcode + 2 displacement */
9460 opcode[1] = opcode[0] + 0x10;
9461 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9462 where_to_put_displacement = &opcode[2];
9463 break;
252b5132 9464
fddf5b5b
AM		 9465 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9466 extension = 4;
9467 opcode[0] ^= 1;
9468 opcode[1] = 3;
9469 opcode[2] = 0xe9;
9470 where_to_put_displacement = &opcode[3];
9471 break;
9472
9473 default:
9474 BAD_CASE (fragP->fr_subtype);
9475 break;
9476 }
252b5132 9477 }
fddf5b5b 9478
7b81dfbb
AJ		 9479 /* If size if less then four we are sure that the operand fits,
9480 but if it's 4, then it could be that the displacement is larger
9481 then -/+ 2GB. */
9482 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9483 && object_64bit
9484 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9485 + ((addressT) 1 << 31))
9486 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9487 {
9488 as_bad_where (fragP->fr_file, fragP->fr_line,
9489 _("jump target out of range"));
9490 /* Make us emit 0. */
9491 displacement_from_opcode_start = extension;
9492 }
47926f60 9493 /* Now put displacement after opcode. */
252b5132
RH		 9494 md_number_to_chars ((char *) where_to_put_displacement,
9495 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9496 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9497 fragP->fr_fix += extension;
9498}
9499\f
7016a5d5 9500/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9501 by our caller that we have all the info we need to fix it up.
9502
7016a5d5
TG		 9503 Parameter valP is the pointer to the value of the bits.
9504
252b5132
RH		 9505 On the 386, immediates, displacements, and data pointers are all in
9506 the same (little-endian) format, so we don't need to care about which
9507 we are handling. */
9508
94f592af 9509void
7016a5d5 9510md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9511{
94f592af 9512 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9513 valueT value = *valP;
252b5132 9514
f86103b7 9515#if !defined (TE_Mach)
93382f6d
AM		 9516 if (fixP->fx_pcrel)
9517 {
9518 switch (fixP->fx_r_type)
9519 {
5865bb77
ILT		 9520 default:
9521 break;
9522
d6ab8113
JB		 9523 case BFD_RELOC_64:
9524 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9525 break;
93382f6d 9526 case BFD_RELOC_32:
ae8887b5 9527 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9528 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9529 break;
9530 case BFD_RELOC_16:
9531 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9532 break;
9533 case BFD_RELOC_8:
9534 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9535 break;
9536 }
9537 }
252b5132 9538
a161fe53 9539 if (fixP->fx_addsy != NULL
31312f95 9540 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9541 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9542 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9543 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9544 && !use_rela_relocations)
252b5132 9545 {
31312f95
AM		 9546 /* This is a hack. There should be a better way to handle this.
9547 This covers for the fact that bfd_install_relocation will
9548 subtract the current location (for partial_inplace, PC relative
9549 relocations); see more below. */
252b5132 9550#ifndef OBJ_AOUT
718ddfc0 9551 if (IS_ELF
252b5132
RH		 9552#ifdef TE_PE
9553 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9554#endif
9555 )
9556 value += fixP->fx_where + fixP->fx_frag->fr_address;
9557#endif
9558#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9559 if (IS_ELF)
252b5132 9560 {
6539b54b 9561 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9562
6539b54b 9563 if ((sym_seg == seg
2f66722d 9564 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9565 && sym_seg != absolute_section))
af65af87 9566 && !generic_force_reloc (fixP))
2f66722d
AM		 9567 {
9568 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9569 bfd_install_relocation subtracts them out again. I think
9570 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9571 it. FIXME. */
9572 value += fixP->fx_where + fixP->fx_frag->fr_address;
9573 }
252b5132
RH		 9574 }
9575#endif
9576#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9577 /* For some reason, the PE format does not store a
9578 section address offset for a PC relative symbol. */
9579 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9580 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9581 value += md_pcrel_from (fixP);
9582#endif
9583 }
fbeb56a4 9584#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9585 if (fixP->fx_addsy != NULL
9586 && S_IS_WEAK (fixP->fx_addsy)
9587 /* PR 16858: Do not modify weak function references. */
9588 && ! fixP->fx_pcrel)
fbeb56a4 9589 {
296a8689
NC		 9590#if !defined (TE_PEP)
9591 /* For x86 PE weak function symbols are neither PC-relative
9592 nor do they set S_IS_FUNCTION. So the only reliable way
9593 to detect them is to check the flags of their containing
9594 section. */
9595 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9596 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9597 ;
9598 else
9599#endif
fbeb56a4
DK		 9600 value -= S_GET_VALUE (fixP->fx_addsy);
9601 }
9602#endif
252b5132
RH		 9603
9604 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9605 and we must not disappoint it. */
252b5132 9606#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9607 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9608 switch (fixP->fx_r_type)
9609 {
9610 case BFD_RELOC_386_PLT32:
3e73aa7c 9611 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9612 /* Make the jump instruction point to the address of the operand. At
9613 runtime we merely add the offset to the actual PLT entry. */
9614 value = -4;
9615 break;
31312f95 9616
13ae64f3
JJ		 9617 case BFD_RELOC_386_TLS_GD:
9618 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9619 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9620 case BFD_RELOC_386_TLS_IE:
9621 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9622 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9623 case BFD_RELOC_X86_64_TLSGD:
9624 case BFD_RELOC_X86_64_TLSLD:
9625 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9626 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9627 value = 0; /* Fully resolved at runtime. No addend. */
9628 /* Fallthrough */
9629 case BFD_RELOC_386_TLS_LE:
9630 case BFD_RELOC_386_TLS_LDO_32:
9631 case BFD_RELOC_386_TLS_LE_32:
9632 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9633 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9634 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9635 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9636 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9637 break;
9638
67a4f2b7
AO		 9639 case BFD_RELOC_386_TLS_DESC_CALL:
9640 case BFD_RELOC_X86_64_TLSDESC_CALL:
9641 value = 0; /* Fully resolved at runtime. No addend. */
9642 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9643 fixP->fx_done = 0;
9644 return;
9645
47926f60
KH		 9646 case BFD_RELOC_VTABLE_INHERIT:
9647 case BFD_RELOC_VTABLE_ENTRY:
9648 fixP->fx_done = 0;
94f592af 9649 return;
47926f60
KH		 9650
9651 default:
9652 break;
9653 }
9654#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9655 *valP = value;
f86103b7 9656#endif /* !defined (TE_Mach) */
3e73aa7c 9657
3e73aa7c 9658 /* Are we finished with this relocation now? */
c6682705 9659 if (fixP->fx_addsy == NULL)
3e73aa7c 9660 fixP->fx_done = 1;
fbeb56a4
DK		 9661#if defined (OBJ_COFF) && defined (TE_PE)
9662 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9663 {
9664 fixP->fx_done = 0;
9665 /* Remember value for tc_gen_reloc. */
9666 fixP->fx_addnumber = value;
9667 /* Clear out the frag for now. */
9668 value = 0;
9669 }
9670#endif
3e73aa7c
JH		 9671 else if (use_rela_relocations)
9672 {
9673 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9674 /* Remember value for tc_gen_reloc. */
9675 fixP->fx_addnumber = value;
3e73aa7c
JH		 9676 value = 0;
9677 }
f86103b7 9678
94f592af 9679 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9680}
252b5132 9681\f
6d4af3c2 9682const char *
499ac353 9683md_atof (int type, char *litP, int *sizeP)
252b5132 9684{
499ac353
NC		 9685 /* This outputs the LITTLENUMs in REVERSE order;
9686 in accord with the bigendian 386. */
9687 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9688}
9689\f
2d545b82 9690static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9691
252b5132 9692static char *
e3bb37b5 9693output_invalid (int c)
252b5132 9694{
3882b010 9695 if (ISPRINT (c))
f9f21a03
L		 9696 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9697 "'%c'", c);
252b5132 9698 else
f9f21a03 9699 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9700 "(0x%x)", (unsigned char) c);
252b5132
RH		 9701 return output_invalid_buf;
9702}
9703
af6bdddf 9704/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9705
9706static const reg_entry *
4d1bb795 9707parse_real_register (char *reg_string, char **end_op)
252b5132 9708{
af6bdddf
AM		 9709 char *s = reg_string;
9710 char *p;
252b5132
RH		 9711 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9712 const reg_entry *r;
9713
9714 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9715 if (*s == REGISTER_PREFIX)
9716 ++s;
9717
9718 if (is_space_char (*s))
9719 ++s;
9720
9721 p = reg_name_given;
af6bdddf 9722 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9723 {
9724 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9725 return (const reg_entry *) NULL;
9726 s++;
252b5132
RH		 9727 }
9728
6588847e
DN		 9729 /* For naked regs, make sure that we are not dealing with an identifier.
9730 This prevents confusing an identifier like `eax_var' with register
9731 `eax'. */
9732 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9733 return (const reg_entry *) NULL;
9734
af6bdddf 9735 *end_op = s;
252b5132
RH		 9736
9737 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9738
5f47d35b 9739 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9740 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9741 {
5f47d35b
AM		 9742 if (is_space_char (*s))
9743 ++s;
9744 if (*s == '(')
9745 {
af6bdddf 9746 ++s;
5f47d35b
AM		 9747 if (is_space_char (*s))
9748 ++s;
9749 if (*s >= '0' && *s <= '7')
9750 {
db557034 9751 int fpr = *s - '0';
af6bdddf 9752 ++s;
5f47d35b
AM		 9753 if (is_space_char (*s))
9754 ++s;
9755 if (*s == ')')
9756 {
9757 *end_op = s + 1;
1e9cc1c2 9758 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9759 know (r);
9760 return r + fpr;
5f47d35b 9761 }
5f47d35b 9762 }
47926f60 9763 /* We have "%st(" then garbage. */
5f47d35b
AM		 9764 return (const reg_entry *) NULL;
9765 }
9766 }
9767
a60de03c
JB		 9768 if (r == NULL || allow_pseudo_reg)
9769 return r;
9770
0dfbf9d7 9771 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9772 return (const reg_entry *) NULL;
9773
dc821c5f 9774 if ((r->reg_type.bitfield.dword
192dc9c6
JB		 9775 || r->reg_type.bitfield.sreg3
9776 || r->reg_type.bitfield.control
9777 || r->reg_type.bitfield.debug
9778 || r->reg_type.bitfield.test)
9779 && !cpu_arch_flags.bitfield.cpui386)
9780 return (const reg_entry *) NULL;
9781
ca0d63fe 9782 if (r->reg_type.bitfield.tbyte
309d3373
JB		 9783 && !cpu_arch_flags.bitfield.cpu8087
9784 && !cpu_arch_flags.bitfield.cpu287
9785 && !cpu_arch_flags.bitfield.cpu387)
9786 return (const reg_entry *) NULL;
9787
1848e567 9788 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
192dc9c6
JB		 9789 return (const reg_entry *) NULL;
9790
1b54b8d7 9791 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
192dc9c6
JB		 9792 return (const reg_entry *) NULL;
9793
1b54b8d7 9794 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
40f12533
L		 9795 return (const reg_entry *) NULL;
9796
1b54b8d7 9797 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
1848e567
L		 9798 return (const reg_entry *) NULL;
9799
9800 if (r->reg_type.bitfield.regmask
9801 && !cpu_arch_flags.bitfield.cpuregmask)
43234a1e
L		 9802 return (const reg_entry *) NULL;
9803
db51cc60 9804 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9805 if (!allow_index_reg
db51cc60
L		 9806 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9807 return (const reg_entry *) NULL;
9808
43234a1e
L		 9809 /* Upper 16 vector register is only available with VREX in 64bit
9810 mode. */
9811 if ((r->reg_flags & RegVRex))
9812 {
86fa6981
L		 9813 if (i.vec_encoding == vex_encoding_default)
9814 i.vec_encoding = vex_encoding_evex;
9815
43234a1e 9816 if (!cpu_arch_flags.bitfield.cpuvrex
86fa6981 9817 || i.vec_encoding != vex_encoding_evex
43234a1e
L		 9818 || flag_code != CODE_64BIT)
9819 return (const reg_entry *) NULL;
43234a1e
L		 9820 }
9821
a60de03c 9822 if (((r->reg_flags & (RegRex64 | RegRex))
dc821c5f 9823 || r->reg_type.bitfield.qword)
40fb9820 9824 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9825 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9826 && flag_code != CODE_64BIT)
20f0a1fc 9827 return (const reg_entry *) NULL;
1ae00879 9828
b7240065
JB		 9829 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9830 return (const reg_entry *) NULL;
9831
252b5132
RH		 9832 return r;
9833}
4d1bb795
JB		 9834
9835/* REG_STRING starts *before* REGISTER_PREFIX. */
9836
9837static const reg_entry *
9838parse_register (char *reg_string, char **end_op)
9839{
9840 const reg_entry *r;
9841
9842 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9843 r = parse_real_register (reg_string, end_op);
9844 else
9845 r = NULL;
9846 if (!r)
9847 {
9848 char *save = input_line_pointer;
9849 char c;
9850 symbolS *symbolP;
9851
9852 input_line_pointer = reg_string;
d02603dc 9853 c = get_symbol_name (&reg_string);
4d1bb795
JB		 9854 symbolP = symbol_find (reg_string);
9855 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9856 {
9857 const expressionS *e = symbol_get_value_expression (symbolP);
9858
0398aac5 9859 know (e->X_op == O_register);
4eed87de 9860 know (e->X_add_number >= 0
c3fe08fa 9861 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9862 r = i386_regtab + e->X_add_number;
d3bb6b49 9863 if ((r->reg_flags & RegVRex))
86fa6981 9864 i.vec_encoding = vex_encoding_evex;
4d1bb795
JB		 9865 *end_op = input_line_pointer;
9866 }
9867 *input_line_pointer = c;
9868 input_line_pointer = save;
9869 }
9870 return r;
9871}
9872
9873int
9874i386_parse_name (char *name, expressionS *e, char *nextcharP)
9875{
9876 const reg_entry *r;
9877 char *end = input_line_pointer;
9878
9879 *end = *nextcharP;
9880 r = parse_register (name, &input_line_pointer);
9881 if (r && end <= input_line_pointer)
9882 {
9883 *nextcharP = *input_line_pointer;
9884 *input_line_pointer = 0;
9885 e->X_op = O_register;
9886 e->X_add_number = r - i386_regtab;
9887 return 1;
9888 }
9889 input_line_pointer = end;
9890 *end = 0;
ee86248c 9891 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9892}
9893
9894void
9895md_operand (expressionS *e)
9896{
ee86248c
JB		 9897 char *end;
9898 const reg_entry *r;
4d1bb795 9899
ee86248c
JB		 9900 switch (*input_line_pointer)
9901 {
9902 case REGISTER_PREFIX:
9903 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9904 if (r)
9905 {
9906 e->X_op = O_register;
9907 e->X_add_number = r - i386_regtab;
9908 input_line_pointer = end;
9909 }
ee86248c
JB		 9910 break;
9911
9912 case '[':
9c2799c2 9913 gas_assert (intel_syntax);
ee86248c
JB		 9914 end = input_line_pointer++;
9915 expression (e);
9916 if (*input_line_pointer == ']')
9917 {
9918 ++input_line_pointer;
9919 e->X_op_symbol = make_expr_symbol (e);
9920 e->X_add_symbol = NULL;
9921 e->X_add_number = 0;
9922 e->X_op = O_index;
9923 }
9924 else
9925 {
9926 e->X_op = O_absent;
9927 input_line_pointer = end;
9928 }
9929 break;
4d1bb795
JB		 9930 }
9931}
9932
252b5132 9933\f
4cc782b5 9934#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9935const char *md_shortopts = "kVQ:sqn";
252b5132 9936#else
12b55ccc 9937const char *md_shortopts = "qn";
252b5132 9938#endif
6e0b89ee 9939
3e73aa7c 9940#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9941#define OPTION_64 (OPTION_MD_BASE + 1)
9942#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9943#define OPTION_MARCH (OPTION_MD_BASE + 3)
9944#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9945#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9946#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9947#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9948#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9949#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9950#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9951#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9952#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9953#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9954#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9955#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9956#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9957#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9958#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 9959#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9960#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9961#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9962#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9963#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 9964#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
0cb4071e 9965#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
b3b91714 9966
99ad8390
NC		 9967struct option md_longopts[] =
9968{
3e73aa7c 9969 {"32", no_argument, NULL, OPTION_32},
321098a5 9970#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9971 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9972 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9973#endif
9974#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9975 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 9976 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 9977#endif
b3b91714 9978 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9979 {"march", required_argument, NULL, OPTION_MARCH},
9980 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9981 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9982 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9983 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9984 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9985 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9986 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9987 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9988 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9989 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9990 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9991 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9992 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9993# if defined (TE_PE) || defined (TE_PEP)
9994 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9995#endif
d1982f93 9996 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 9997 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 9998 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 9999 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 10000 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10001 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 10002 {NULL, no_argument, NULL, 0}
10003};
10004size_t md_longopts_size = sizeof (md_longopts);
10005
10006int
17b9d67d 10007md_parse_option (int c, const char *arg)
252b5132 10008{
91d6fa6a 10009 unsigned int j;
293f5f65 10010 char *arch, *next, *saved;
9103f4f4 10011
252b5132
RH		 10012 switch (c)
10013 {
12b55ccc
L		 10014 case 'n':
10015 optimize_align_code = 0;
10016 break;
10017
a38cf1db
AM		 10018 case 'q':
10019 quiet_warnings = 1;
252b5132
RH		 10020 break;
10021
10022#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 10023 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10024 should be emitted or not. FIXME: Not implemented. */
10025 case 'Q':
252b5132
RH		 10026 break;
10027
10028 /* -V: SVR4 argument to print version ID. */
10029 case 'V':
10030 print_version_id ();
10031 break;
10032
a38cf1db
AM		 10033 /* -k: Ignore for FreeBSD compatibility. */
10034 case 'k':
252b5132 10035 break;
4cc782b5
ILT		 10036
10037 case 's':
10038 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 10039 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 10040 break;
8dcea932
L		 10041
10042 case OPTION_MSHARED:
10043 shared = 1;
10044 break;
99ad8390 10045#endif
321098a5 10046#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10047 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 10048 case OPTION_64:
10049 {
10050 const char **list, **l;
10051
3e73aa7c
JH		 10052 list = bfd_target_list ();
10053 for (l = list; *l != NULL; l++)
8620418b 10054 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 10055 || strcmp (*l, "coff-x86-64") == 0
10056 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 10057 || strcmp (*l, "pei-x86-64") == 0
10058 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 10059 {
10060 default_arch = "x86_64";
10061 break;
10062 }
3e73aa7c 10063 if (*l == NULL)
2b5d6a91 10064 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 10065 free (list);
10066 }
10067 break;
10068#endif
252b5132 10069
351f65ca 10070#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10071 case OPTION_X32:
351f65ca
L		 10072 if (IS_ELF)
10073 {
10074 const char **list, **l;
10075
10076 list = bfd_target_list ();
10077 for (l = list; *l != NULL; l++)
10078 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10079 {
10080 default_arch = "x86_64:32";
10081 break;
10082 }
10083 if (*l == NULL)
2b5d6a91 10084 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 10085 free (list);
10086 }
10087 else
10088 as_fatal (_("32bit x86_64 is only supported for ELF"));
10089 break;
10090#endif
10091
6e0b89ee
AM		 10092 case OPTION_32:
10093 default_arch = "i386";
10094 break;
10095
b3b91714
AM		 10096 case OPTION_DIVIDE:
10097#ifdef SVR4_COMMENT_CHARS
10098 {
10099 char *n, *t;
10100 const char *s;
10101
add39d23 10102 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 10103 t = n;
10104 for (s = i386_comment_chars; *s != '\0'; s++)
10105 if (*s != '/')
10106 *t++ = *s;
10107 *t = '\0';
10108 i386_comment_chars = n;
10109 }
10110#endif
10111 break;
10112
9103f4f4 10113 case OPTION_MARCH:
293f5f65
L		 10114 saved = xstrdup (arg);
10115 arch = saved;
10116 /* Allow -march=+nosse. */
10117 if (*arch == '+')
10118 arch++;
6305a203 10119 do
9103f4f4 10120 {
6305a203 10121 if (*arch == '.')
2b5d6a91 10122 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10123 next = strchr (arch, '+');
10124 if (next)
10125 *next++ = '\0';
91d6fa6a 10126 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10127 {
91d6fa6a 10128 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 10129 {
6305a203 10130 /* Processor. */
1ded5609
JB		 10131 if (! cpu_arch[j].flags.bitfield.cpui386)
10132 continue;
10133
91d6fa6a 10134 cpu_arch_name = cpu_arch[j].name;
6305a203 10135 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 10136 cpu_arch_flags = cpu_arch[j].flags;
10137 cpu_arch_isa = cpu_arch[j].type;
10138 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 10139 if (!cpu_arch_tune_set)
10140 {
10141 cpu_arch_tune = cpu_arch_isa;
10142 cpu_arch_tune_flags = cpu_arch_isa_flags;
10143 }
10144 break;
10145 }
91d6fa6a
NC		 10146 else if (*cpu_arch [j].name == '.'
10147 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203 10148 {
33eaf5de 10149 /* ISA extension. */
6305a203 10150 i386_cpu_flags flags;
309d3373 10151
293f5f65
L		 10152 flags = cpu_flags_or (cpu_arch_flags,
10153 cpu_arch[j].flags);
81486035 10154
5b64d091 10155 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10156 {
10157 if (cpu_sub_arch_name)
10158 {
10159 char *name = cpu_sub_arch_name;
10160 cpu_sub_arch_name = concat (name,
91d6fa6a 10161 cpu_arch[j].name,
1bf57e9f 10162 (const char *) NULL);
6305a203
L		 10163 free (name);
10164 }
10165 else
91d6fa6a 10166 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10167 cpu_arch_flags = flags;
a586129e 10168 cpu_arch_isa_flags = flags;
6305a203
L		 10169 }
10170 break;
ccc9c027 10171 }
9103f4f4 10172 }
6305a203 10173
293f5f65
L		 10174 if (j >= ARRAY_SIZE (cpu_arch))
10175 {
33eaf5de 10176 /* Disable an ISA extension. */
293f5f65
L		 10177 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10178 if (strcmp (arch, cpu_noarch [j].name) == 0)
10179 {
10180 i386_cpu_flags flags;
10181
10182 flags = cpu_flags_and_not (cpu_arch_flags,
10183 cpu_noarch[j].flags);
10184 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10185 {
10186 if (cpu_sub_arch_name)
10187 {
10188 char *name = cpu_sub_arch_name;
10189 cpu_sub_arch_name = concat (arch,
10190 (const char *) NULL);
10191 free (name);
10192 }
10193 else
10194 cpu_sub_arch_name = xstrdup (arch);
10195 cpu_arch_flags = flags;
10196 cpu_arch_isa_flags = flags;
10197 }
10198 break;
10199 }
10200
10201 if (j >= ARRAY_SIZE (cpu_noarch))
10202 j = ARRAY_SIZE (cpu_arch);
10203 }
10204
91d6fa6a 10205 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10206 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10207
10208 arch = next;
9103f4f4 10209 }
293f5f65
L		 10210 while (next != NULL);
10211 free (saved);
9103f4f4
L		 10212 break;
10213
10214 case OPTION_MTUNE:
10215 if (*arg == '.')
2b5d6a91 10216 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10217 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10218 {
91d6fa6a 10219 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10220 {
ccc9c027 10221 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10222 cpu_arch_tune = cpu_arch [j].type;
10223 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10224 break;
10225 }
10226 }
91d6fa6a 10227 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10228 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10229 break;
10230
1efbbeb4
L		 10231 case OPTION_MMNEMONIC:
10232 if (strcasecmp (arg, "att") == 0)
10233 intel_mnemonic = 0;
10234 else if (strcasecmp (arg, "intel") == 0)
10235 intel_mnemonic = 1;
10236 else
2b5d6a91 10237 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10238 break;
10239
10240 case OPTION_MSYNTAX:
10241 if (strcasecmp (arg, "att") == 0)
10242 intel_syntax = 0;
10243 else if (strcasecmp (arg, "intel") == 0)
10244 intel_syntax = 1;
10245 else
2b5d6a91 10246 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10247 break;
10248
10249 case OPTION_MINDEX_REG:
10250 allow_index_reg = 1;
10251 break;
10252
10253 case OPTION_MNAKED_REG:
10254 allow_naked_reg = 1;
10255 break;
10256
10257 case OPTION_MOLD_GCC:
10258 old_gcc = 1;
1efbbeb4
L		 10259 break;
10260
c0f3af97
L		 10261 case OPTION_MSSE2AVX:
10262 sse2avx = 1;
10263 break;
10264
daf50ae7
L		 10265 case OPTION_MSSE_CHECK:
10266 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10267 sse_check = check_error;
daf50ae7 10268 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10269 sse_check = check_warning;
daf50ae7 10270 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10271 sse_check = check_none;
daf50ae7 10272 else
2b5d6a91 10273 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10274 break;
10275
7bab8ab5
JB		 10276 case OPTION_MOPERAND_CHECK:
10277 if (strcasecmp (arg, "error") == 0)
10278 operand_check = check_error;
10279 else if (strcasecmp (arg, "warning") == 0)
10280 operand_check = check_warning;
10281 else if (strcasecmp (arg, "none") == 0)
10282 operand_check = check_none;
10283 else
10284 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10285 break;
10286
539f890d
L		 10287 case OPTION_MAVXSCALAR:
10288 if (strcasecmp (arg, "128") == 0)
10289 avxscalar = vex128;
10290 else if (strcasecmp (arg, "256") == 0)
10291 avxscalar = vex256;
10292 else
2b5d6a91 10293 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10294 break;
10295
7e8b059b
L		 10296 case OPTION_MADD_BND_PREFIX:
10297 add_bnd_prefix = 1;
10298 break;
10299
43234a1e
L		 10300 case OPTION_MEVEXLIG:
10301 if (strcmp (arg, "128") == 0)
10302 evexlig = evexl128;
10303 else if (strcmp (arg, "256") == 0)
10304 evexlig = evexl256;
10305 else if (strcmp (arg, "512") == 0)
10306 evexlig = evexl512;
10307 else
10308 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10309 break;
10310
d3d3c6db
IT		 10311 case OPTION_MEVEXRCIG:
10312 if (strcmp (arg, "rne") == 0)
10313 evexrcig = rne;
10314 else if (strcmp (arg, "rd") == 0)
10315 evexrcig = rd;
10316 else if (strcmp (arg, "ru") == 0)
10317 evexrcig = ru;
10318 else if (strcmp (arg, "rz") == 0)
10319 evexrcig = rz;
10320 else
10321 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10322 break;
10323
43234a1e
L		 10324 case OPTION_MEVEXWIG:
10325 if (strcmp (arg, "0") == 0)
10326 evexwig = evexw0;
10327 else if (strcmp (arg, "1") == 0)
10328 evexwig = evexw1;
10329 else
10330 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10331 break;
10332
167ad85b
TG		 10333# if defined (TE_PE) || defined (TE_PEP)
10334 case OPTION_MBIG_OBJ:
10335 use_big_obj = 1;
10336 break;
10337#endif
10338
d1982f93 10339 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10340 if (strcasecmp (arg, "yes") == 0)
10341 omit_lock_prefix = 1;
10342 else if (strcasecmp (arg, "no") == 0)
10343 omit_lock_prefix = 0;
10344 else
10345 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10346 break;
10347
e4e00185
AS		 10348 case OPTION_MFENCE_AS_LOCK_ADD:
10349 if (strcasecmp (arg, "yes") == 0)
10350 avoid_fence = 1;
10351 else if (strcasecmp (arg, "no") == 0)
10352 avoid_fence = 0;
10353 else
10354 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10355 break;
10356
0cb4071e
L		 10357 case OPTION_MRELAX_RELOCATIONS:
10358 if (strcasecmp (arg, "yes") == 0)
10359 generate_relax_relocations = 1;
10360 else if (strcasecmp (arg, "no") == 0)
10361 generate_relax_relocations = 0;
10362 else
10363 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10364 break;
10365
5db04b09 10366 case OPTION_MAMD64:
e89c5eaa 10367 intel64 = 0;
5db04b09
L		 10368 break;
10369
10370 case OPTION_MINTEL64:
e89c5eaa 10371 intel64 = 1;
5db04b09
L		 10372 break;
10373
252b5132
RH		 10374 default:
10375 return 0;
10376 }
10377 return 1;
10378}
10379
8a2c8fef
L		 10380#define MESSAGE_TEMPLATE \
10381" "
10382
293f5f65
L		 10383static char *
10384output_message (FILE *stream, char *p, char *message, char *start,
10385 int *left_p, const char *name, int len)
10386{
10387 int size = sizeof (MESSAGE_TEMPLATE);
10388 int left = *left_p;
10389
10390 /* Reserve 2 spaces for ", " or ",\0" */
10391 left -= len + 2;
10392
10393 /* Check if there is any room. */
10394 if (left >= 0)
10395 {
10396 if (p != start)
10397 {
10398 *p++ = ',';
10399 *p++ = ' ';
10400 }
10401 p = mempcpy (p, name, len);
10402 }
10403 else
10404 {
10405 /* Output the current message now and start a new one. */
10406 *p++ = ',';
10407 *p = '\0';
10408 fprintf (stream, "%s\n", message);
10409 p = start;
10410 left = size - (start - message) - len - 2;
10411
10412 gas_assert (left >= 0);
10413
10414 p = mempcpy (p, name, len);
10415 }
10416
10417 *left_p = left;
10418 return p;
10419}
10420
8a2c8fef 10421static void
1ded5609 10422show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10423{
10424 static char message[] = MESSAGE_TEMPLATE;
10425 char *start = message + 27;
10426 char *p;
10427 int size = sizeof (MESSAGE_TEMPLATE);
10428 int left;
10429 const char *name;
10430 int len;
10431 unsigned int j;
10432
10433 p = start;
10434 left = size - (start - message);
10435 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10436 {
10437 /* Should it be skipped? */
10438 if (cpu_arch [j].skip)
10439 continue;
10440
10441 name = cpu_arch [j].name;
10442 len = cpu_arch [j].len;
10443 if (*name == '.')
10444 {
10445 /* It is an extension. Skip if we aren't asked to show it. */
10446 if (ext)
10447 {
10448 name++;
10449 len--;
10450 }
10451 else
10452 continue;
10453 }
10454 else if (ext)
10455 {
10456 /* It is an processor. Skip if we show only extension. */
10457 continue;
10458 }
1ded5609
JB		 10459 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10460 {
10461 /* It is an impossible processor - skip. */
10462 continue;
10463 }
8a2c8fef 10464
293f5f65 10465 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10466 }
10467
293f5f65
L		 10468 /* Display disabled extensions. */
10469 if (ext)
10470 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10471 {
10472 name = cpu_noarch [j].name;
10473 len = cpu_noarch [j].len;
10474 p = output_message (stream, p, message, start, &left, name,
10475 len);
10476 }
10477
8a2c8fef
L		 10478 *p = '\0';
10479 fprintf (stream, "%s\n", message);
10480}
10481
252b5132 10482void
8a2c8fef 10483md_show_usage (FILE *stream)
252b5132 10484{
4cc782b5
ILT		 10485#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10486 fprintf (stream, _("\
a38cf1db
AM		 10487 -Q ignored\n\
10488 -V print assembler version number\n\
b3b91714
AM		 10489 -k ignored\n"));
10490#endif
10491 fprintf (stream, _("\
12b55ccc 10492 -n Do not optimize code alignment\n\
b3b91714
AM		 10493 -q quieten some warnings\n"));
10494#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10495 fprintf (stream, _("\
a38cf1db 10496 -s ignored\n"));
b3b91714 10497#endif
321098a5
L		 10498#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10499 || defined (TE_PE) || defined (TE_PEP))
751d281c 10500 fprintf (stream, _("\
570561f7 10501 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10502#endif
b3b91714
AM		 10503#ifdef SVR4_COMMENT_CHARS
10504 fprintf (stream, _("\
10505 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10506#else
10507 fprintf (stream, _("\
b3b91714 10508 --divide ignored\n"));
4cc782b5 10509#endif
9103f4f4 10510 fprintf (stream, _("\
6305a203 10511 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10512 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10513 show_arch (stream, 0, 1);
8a2c8fef
L		 10514 fprintf (stream, _("\
10515 EXTENSION is combination of:\n"));
1ded5609 10516 show_arch (stream, 1, 0);
6305a203 10517 fprintf (stream, _("\
8a2c8fef 10518 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10519 show_arch (stream, 0, 0);
ba104c83 10520 fprintf (stream, _("\
c0f3af97
L		 10521 -msse2avx encode SSE instructions with VEX prefix\n"));
10522 fprintf (stream, _("\
daf50ae7
L		 10523 -msse-check=[none|error|warning]\n\
10524 check SSE instructions\n"));
10525 fprintf (stream, _("\
7bab8ab5
JB		 10526 -moperand-check=[none|error|warning]\n\
10527 check operand combinations for validity\n"));
10528 fprintf (stream, _("\
539f890d
L		 10529 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10530 length\n"));
10531 fprintf (stream, _("\
43234a1e
L		 10532 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10533 length\n"));
10534 fprintf (stream, _("\
10535 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10536 for EVEX.W bit ignored instructions\n"));
10537 fprintf (stream, _("\
d3d3c6db
IT		 10538 -mevexrcig=[rne|rd|ru|rz]\n\
10539 encode EVEX instructions with specific EVEX.RC value\n\
10540 for SAE-only ignored instructions\n"));
10541 fprintf (stream, _("\
ba104c83
L		 10542 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10543 fprintf (stream, _("\
10544 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10545 fprintf (stream, _("\
10546 -mindex-reg support pseudo index registers\n"));
10547 fprintf (stream, _("\
10548 -mnaked-reg don't require `%%' prefix for registers\n"));
10549 fprintf (stream, _("\
10550 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10551 fprintf (stream, _("\
10552 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10553 fprintf (stream, _("\
10554 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10555# if defined (TE_PE) || defined (TE_PEP)
10556 fprintf (stream, _("\
10557 -mbig-obj generate big object files\n"));
10558#endif
d022bddd
IT		 10559 fprintf (stream, _("\
10560 -momit-lock-prefix=[no|yes]\n\
10561 strip all lock prefixes\n"));
5db04b09 10562 fprintf (stream, _("\
e4e00185
AS		 10563 -mfence-as-lock-add=[no|yes]\n\
10564 encode lfence, mfence and sfence as\n\
10565 lock addl $0x0, (%%{re}sp)\n"));
10566 fprintf (stream, _("\
0cb4071e
L		 10567 -mrelax-relocations=[no|yes]\n\
10568 generate relax relocations\n"));
10569 fprintf (stream, _("\
5db04b09
L		 10570 -mamd64 accept only AMD64 ISA\n"));
10571 fprintf (stream, _("\
10572 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10573}
10574
3e73aa7c 10575#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10576 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10577 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10578
10579/* Pick the target format to use. */
10580
47926f60 10581const char *
e3bb37b5 10582i386_target_format (void)
252b5132 10583{
351f65ca
L		 10584 if (!strncmp (default_arch, "x86_64", 6))
10585 {
10586 update_code_flag (CODE_64BIT, 1);
10587 if (default_arch[6] == '\0')
7f56bc95 10588 x86_elf_abi = X86_64_ABI;
351f65ca 10589 else
7f56bc95 10590 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10591 }
3e73aa7c 10592 else if (!strcmp (default_arch, "i386"))
78f12dd3 10593 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10594 else if (!strcmp (default_arch, "iamcu"))
10595 {
10596 update_code_flag (CODE_32BIT, 1);
10597 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10598 {
10599 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10600 cpu_arch_name = "iamcu";
10601 cpu_sub_arch_name = NULL;
10602 cpu_arch_flags = iamcu_flags;
10603 cpu_arch_isa = PROCESSOR_IAMCU;
10604 cpu_arch_isa_flags = iamcu_flags;
10605 if (!cpu_arch_tune_set)
10606 {
10607 cpu_arch_tune = cpu_arch_isa;
10608 cpu_arch_tune_flags = cpu_arch_isa_flags;
10609 }
10610 }
8d471ec1 10611 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 10612 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10613 cpu_arch_name);
10614 }
3e73aa7c 10615 else
2b5d6a91 10616 as_fatal (_("unknown architecture"));
89507696
JB		 10617
10618 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10619 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10620 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10621 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10622
252b5132
RH		 10623 switch (OUTPUT_FLAVOR)
10624 {
9384f2ff 10625#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10626 case bfd_target_aout_flavour:
47926f60 10627 return AOUT_TARGET_FORMAT;
4c63da97 10628#endif
9384f2ff
AM		 10629#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10630# if defined (TE_PE) || defined (TE_PEP)
10631 case bfd_target_coff_flavour:
167ad85b
TG		 10632 if (flag_code == CODE_64BIT)
10633 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10634 else
10635 return "pe-i386";
9384f2ff 10636# elif defined (TE_GO32)
0561d57c
JK		 10637 case bfd_target_coff_flavour:
10638 return "coff-go32";
9384f2ff 10639# else
252b5132
RH		 10640 case bfd_target_coff_flavour:
10641 return "coff-i386";
9384f2ff 10642# endif
4c63da97 10643#endif
3e73aa7c 10644#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10645 case bfd_target_elf_flavour:
3e73aa7c 10646 {
351f65ca
L		 10647 const char *format;
10648
10649 switch (x86_elf_abi)
4fa24527 10650 {
351f65ca
L		 10651 default:
10652 format = ELF_TARGET_FORMAT;
10653 break;
7f56bc95 10654 case X86_64_ABI:
351f65ca 10655 use_rela_relocations = 1;
4fa24527 10656 object_64bit = 1;
351f65ca
L		 10657 format = ELF_TARGET_FORMAT64;
10658 break;
7f56bc95 10659 case X86_64_X32_ABI:
4fa24527 10660 use_rela_relocations = 1;
351f65ca 10661 object_64bit = 1;
862be3fb 10662 disallow_64bit_reloc = 1;
351f65ca
L		 10663 format = ELF_TARGET_FORMAT32;
10664 break;
4fa24527 10665 }
3632d14b 10666 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10667 {
7f56bc95 10668 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10669 as_fatal (_("Intel L1OM is 64bit only"));
10670 return ELF_TARGET_L1OM_FORMAT;
10671 }
b49f93f6 10672 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10673 {
10674 if (x86_elf_abi != X86_64_ABI)
10675 as_fatal (_("Intel K1OM is 64bit only"));
10676 return ELF_TARGET_K1OM_FORMAT;
10677 }
81486035
L		 10678 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10679 {
10680 if (x86_elf_abi != I386_ABI)
10681 as_fatal (_("Intel MCU is 32bit only"));
10682 return ELF_TARGET_IAMCU_FORMAT;
10683 }
8a9036a4 10684 else
351f65ca 10685 return format;
3e73aa7c 10686 }
e57f8c65
TG		 10687#endif
10688#if defined (OBJ_MACH_O)
10689 case bfd_target_mach_o_flavour:
d382c579
TG		 10690 if (flag_code == CODE_64BIT)
10691 {
10692 use_rela_relocations = 1;
10693 object_64bit = 1;
10694 return "mach-o-x86-64";
10695 }
10696 else
10697 return "mach-o-i386";
4c63da97 10698#endif
252b5132
RH		 10699 default:
10700 abort ();
10701 return NULL;
10702 }
10703}
10704
47926f60 10705#endif /* OBJ_MAYBE_ more than one */
252b5132 10706\f
252b5132 10707symbolS *
7016a5d5 10708md_undefined_symbol (char *name)
252b5132 10709{
18dc2407
ILT		 10710 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10711 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10712 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10713 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10714 {
10715 if (!GOT_symbol)
10716 {
10717 if (symbol_find (name))
10718 as_bad (_("GOT already in symbol table"));
10719 GOT_symbol = symbol_new (name, undefined_section,
10720 (valueT) 0, &zero_address_frag);
10721 };
10722 return GOT_symbol;
10723 }
252b5132
RH		 10724 return 0;
10725}
10726
10727/* Round up a section size to the appropriate boundary. */
47926f60 10728
252b5132 10729valueT
7016a5d5 10730md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10731{
4c63da97
AM		 10732#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10733 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10734 {
10735 /* For a.out, force the section size to be aligned. If we don't do
10736 this, BFD will align it for us, but it will not write out the
10737 final bytes of the section. This may be a bug in BFD, but it is
10738 easier to fix it here since that is how the other a.out targets
10739 work. */
10740 int align;
10741
10742 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 10743 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 10744 }
252b5132
RH		 10745#endif
10746
10747 return size;
10748}
10749
10750/* On the i386, PC-relative offsets are relative to the start of the
10751 next instruction. That is, the address of the offset, plus its
10752 size, since the offset is always the last part of the insn. */
10753
10754long
e3bb37b5 10755md_pcrel_from (fixS *fixP)
252b5132
RH		 10756{
10757 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10758}
10759
10760#ifndef I386COFF
10761
10762static void
e3bb37b5 10763s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10764{
29b0f896 10765 int temp;
252b5132 10766
8a75718c
JB		 10767#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10768 if (IS_ELF)
10769 obj_elf_section_change_hook ();
10770#endif
252b5132
RH		 10771 temp = get_absolute_expression ();
10772 subseg_set (bss_section, (subsegT) temp);
10773 demand_empty_rest_of_line ();
10774}
10775
10776#endif
10777
252b5132 10778void
e3bb37b5 10779i386_validate_fix (fixS *fixp)
252b5132 10780{
02a86693 10781 if (fixp->fx_subsy)
252b5132 10782 {
02a86693 10783 if (fixp->fx_subsy == GOT_symbol)
23df1078 10784 {
02a86693
L		 10785 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10786 {
10787 if (!object_64bit)
10788 abort ();
10789#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10790 if (fixp->fx_tcbit2)
56ceb5b5
L		 10791 fixp->fx_r_type = (fixp->fx_tcbit
10792 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10793 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 10794 else
10795#endif
10796 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10797 }
d6ab8113 10798 else
02a86693
L		 10799 {
10800 if (!object_64bit)
10801 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10802 else
10803 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10804 }
10805 fixp->fx_subsy = 0;
23df1078 10806 }
252b5132 10807 }
02a86693
L		 10808#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10809 else if (!object_64bit)
10810 {
10811 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10812 && fixp->fx_tcbit2)
10813 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10814 }
10815#endif
252b5132
RH		 10816}
10817
252b5132 10818arelent *
7016a5d5 10819tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10820{
10821 arelent *rel;
10822 bfd_reloc_code_real_type code;
10823
10824 switch (fixp->fx_r_type)
10825 {
8ce3d284 10826#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10827 case BFD_RELOC_SIZE32:
10828 case BFD_RELOC_SIZE64:
10829 if (S_IS_DEFINED (fixp->fx_addsy)
10830 && !S_IS_EXTERNAL (fixp->fx_addsy))
10831 {
10832 /* Resolve size relocation against local symbol to size of
10833 the symbol plus addend. */
10834 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10835 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10836 && !fits_in_unsigned_long (value))
10837 as_bad_where (fixp->fx_file, fixp->fx_line,
10838 _("symbol size computation overflow"));
10839 fixp->fx_addsy = NULL;
10840 fixp->fx_subsy = NULL;
10841 md_apply_fix (fixp, (valueT *) &value, NULL);
10842 return NULL;
10843 }
8ce3d284 10844#endif
1a0670f3 10845 /* Fall through. */
8fd4256d 10846
3e73aa7c
JH		 10847 case BFD_RELOC_X86_64_PLT32:
10848 case BFD_RELOC_X86_64_GOT32:
10849 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10850 case BFD_RELOC_X86_64_GOTPCRELX:
10851 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 10852 case BFD_RELOC_386_PLT32:
10853 case BFD_RELOC_386_GOT32:
02a86693 10854 case BFD_RELOC_386_GOT32X:
252b5132
RH		 10855 case BFD_RELOC_386_GOTOFF:
10856 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10857 case BFD_RELOC_386_TLS_GD:
10858 case BFD_RELOC_386_TLS_LDM:
10859 case BFD_RELOC_386_TLS_LDO_32:
10860 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10861 case BFD_RELOC_386_TLS_IE:
10862 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10863 case BFD_RELOC_386_TLS_LE_32:
10864 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10865 case BFD_RELOC_386_TLS_GOTDESC:
10866 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10867 case BFD_RELOC_X86_64_TLSGD:
10868 case BFD_RELOC_X86_64_TLSLD:
10869 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10870 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10871 case BFD_RELOC_X86_64_GOTTPOFF:
10872 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10873 case BFD_RELOC_X86_64_TPOFF64:
10874 case BFD_RELOC_X86_64_GOTOFF64:
10875 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10876 case BFD_RELOC_X86_64_GOT64:
10877 case BFD_RELOC_X86_64_GOTPCREL64:
10878 case BFD_RELOC_X86_64_GOTPC64:
10879 case BFD_RELOC_X86_64_GOTPLT64:
10880 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10881 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10882 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10883 case BFD_RELOC_RVA:
10884 case BFD_RELOC_VTABLE_ENTRY:
10885 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10886#ifdef TE_PE
10887 case BFD_RELOC_32_SECREL:
10888#endif
252b5132
RH		 10889 code = fixp->fx_r_type;
10890 break;
dbbaec26
L		 10891 case BFD_RELOC_X86_64_32S:
10892 if (!fixp->fx_pcrel)
10893 {
10894 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10895 code = fixp->fx_r_type;
10896 break;
10897 }
1a0670f3 10898 /* Fall through. */
252b5132 10899 default:
93382f6d 10900 if (fixp->fx_pcrel)
252b5132 10901 {
93382f6d
AM		 10902 switch (fixp->fx_size)
10903 {
10904 default:
b091f402
AM		 10905 as_bad_where (fixp->fx_file, fixp->fx_line,
10906 _("can not do %d byte pc-relative relocation"),
10907 fixp->fx_size);
93382f6d
AM		 10908 code = BFD_RELOC_32_PCREL;
10909 break;
10910 case 1: code = BFD_RELOC_8_PCREL; break;
10911 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10912 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10913#ifdef BFD64
10914 case 8: code = BFD_RELOC_64_PCREL; break;
10915#endif
93382f6d
AM		 10916 }
10917 }
10918 else
10919 {
10920 switch (fixp->fx_size)
10921 {
10922 default:
b091f402
AM		 10923 as_bad_where (fixp->fx_file, fixp->fx_line,
10924 _("can not do %d byte relocation"),
10925 fixp->fx_size);
93382f6d
AM		 10926 code = BFD_RELOC_32;
10927 break;
10928 case 1: code = BFD_RELOC_8; break;
10929 case 2: code = BFD_RELOC_16; break;
10930 case 4: code = BFD_RELOC_32; break;
937149dd 10931#ifdef BFD64
3e73aa7c 10932 case 8: code = BFD_RELOC_64; break;
937149dd 10933#endif
93382f6d 10934 }
252b5132
RH		 10935 }
10936 break;
10937 }
252b5132 10938
d182319b
JB		 10939 if ((code == BFD_RELOC_32
10940 || code == BFD_RELOC_32_PCREL
10941 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10942 && GOT_symbol
10943 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10944 {
4fa24527 10945 if (!object_64bit)
d6ab8113
JB		 10946 code = BFD_RELOC_386_GOTPC;
10947 else
10948 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10949 }
7b81dfbb
AJ		 10950 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10951 && GOT_symbol
10952 && fixp->fx_addsy == GOT_symbol)
10953 {
10954 code = BFD_RELOC_X86_64_GOTPC64;
10955 }
252b5132 10956
add39d23
TS		 10957 rel = XNEW (arelent);
10958 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 10959 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10960
10961 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10962
3e73aa7c
JH		 10963 if (!use_rela_relocations)
10964 {
10965 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10966 vtable entry to be used in the relocation's section offset. */
10967 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10968 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10969#if defined (OBJ_COFF) && defined (TE_PE)
10970 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10971 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10972 else
10973#endif
c6682705 10974 rel->addend = 0;
3e73aa7c
JH		 10975 }
10976 /* Use the rela in 64bit mode. */
252b5132 10977 else
3e73aa7c 10978 {
862be3fb
L		 10979 if (disallow_64bit_reloc)
10980 switch (code)
10981 {
862be3fb
L		 10982 case BFD_RELOC_X86_64_DTPOFF64:
10983 case BFD_RELOC_X86_64_TPOFF64:
10984 case BFD_RELOC_64_PCREL:
10985 case BFD_RELOC_X86_64_GOTOFF64:
10986 case BFD_RELOC_X86_64_GOT64:
10987 case BFD_RELOC_X86_64_GOTPCREL64:
10988 case BFD_RELOC_X86_64_GOTPC64:
10989 case BFD_RELOC_X86_64_GOTPLT64:
10990 case BFD_RELOC_X86_64_PLTOFF64:
10991 as_bad_where (fixp->fx_file, fixp->fx_line,
10992 _("cannot represent relocation type %s in x32 mode"),
10993 bfd_get_reloc_code_name (code));
10994 break;
10995 default:
10996 break;
10997 }
10998
062cd5e7
AS		 10999 if (!fixp->fx_pcrel)
11000 rel->addend = fixp->fx_offset;
11001 else
11002 switch (code)
11003 {
11004 case BFD_RELOC_X86_64_PLT32:
11005 case BFD_RELOC_X86_64_GOT32:
11006 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11007 case BFD_RELOC_X86_64_GOTPCRELX:
11008 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 11009 case BFD_RELOC_X86_64_TLSGD:
11010 case BFD_RELOC_X86_64_TLSLD:
11011 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 11012 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11013 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 11014 rel->addend = fixp->fx_offset - fixp->fx_size;
11015 break;
11016 default:
11017 rel->addend = (section->vma
11018 - fixp->fx_size
11019 + fixp->fx_addnumber
11020 + md_pcrel_from (fixp));
11021 break;
11022 }
3e73aa7c
JH		 11023 }
11024
252b5132
RH		 11025 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11026 if (rel->howto == NULL)
11027 {
11028 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 11029 _("cannot represent relocation type %s"),
252b5132
RH		 11030 bfd_get_reloc_code_name (code));
11031 /* Set howto to a garbage value so that we can keep going. */
11032 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 11033 gas_assert (rel->howto != NULL);
252b5132
RH		 11034 }
11035
11036 return rel;
11037}
11038
ee86248c 11039#include "tc-i386-intel.c"
54cfded0 11040
a60de03c
JB		 11041void
11042tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 11043{
a60de03c
JB		 11044 int saved_naked_reg;
11045 char saved_register_dot;
54cfded0 11046
a60de03c
JB		 11047 saved_naked_reg = allow_naked_reg;
11048 allow_naked_reg = 1;
11049 saved_register_dot = register_chars['.'];
11050 register_chars['.'] = '.';
11051 allow_pseudo_reg = 1;
11052 expression_and_evaluate (exp);
11053 allow_pseudo_reg = 0;
11054 register_chars['.'] = saved_register_dot;
11055 allow_naked_reg = saved_naked_reg;
11056
e96d56a1 11057 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 11058 {
a60de03c
JB		 11059 if ((addressT) exp->X_add_number < i386_regtab_size)
11060 {
11061 exp->X_op = O_constant;
11062 exp->X_add_number = i386_regtab[exp->X_add_number]
11063 .dw2_regnum[flag_code >> 1];
11064 }
11065 else
11066 exp->X_op = O_illegal;
54cfded0 11067 }
54cfded0
AM		 11068}
11069
11070void
11071tc_x86_frame_initial_instructions (void)
11072{
a60de03c
JB		 11073 static unsigned int sp_regno[2];
11074
11075 if (!sp_regno[flag_code >> 1])
11076 {
11077 char *saved_input = input_line_pointer;
11078 char sp[][4] = {"esp", "rsp"};
11079 expressionS exp;
a4447b93 11080
a60de03c
JB		 11081 input_line_pointer = sp[flag_code >> 1];
11082 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 11083 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 11084 sp_regno[flag_code >> 1] = exp.X_add_number;
11085 input_line_pointer = saved_input;
11086 }
a4447b93 11087
61ff971f
L		 11088 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11089 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 11090}
d2b2c203 11091
d7921315
L		 11092int
11093x86_dwarf2_addr_size (void)
11094{
11095#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11096 if (x86_elf_abi == X86_64_X32_ABI)
11097 return 4;
11098#endif
11099 return bfd_arch_bits_per_address (stdoutput) / 8;
11100}
11101
d2b2c203
DJ		 11102int
11103i386_elf_section_type (const char *str, size_t len)
11104{
11105 if (flag_code == CODE_64BIT
11106 && len == sizeof ("unwind") - 1
11107 && strncmp (str, "unwind", 6) == 0)
11108 return SHT_X86_64_UNWIND;
11109
11110 return -1;
11111}
bb41ade5 11112
ad5fec3b
EB		 11113#ifdef TE_SOLARIS
11114void
11115i386_solaris_fix_up_eh_frame (segT sec)
11116{
11117 if (flag_code == CODE_64BIT)
11118 elf_section_type (sec) = SHT_X86_64_UNWIND;
11119}
11120#endif
11121
bb41ade5
AM		 11122#ifdef TE_PE
11123void
11124tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11125{
91d6fa6a 11126 expressionS exp;
bb41ade5 11127
91d6fa6a
NC		 11128 exp.X_op = O_secrel;
11129 exp.X_add_symbol = symbol;
11130 exp.X_add_number = 0;
11131 emit_expr (&exp, size);
bb41ade5
AM		 11132}
11133#endif
3b22753a
L		 11134
11135#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11136/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11137
01e1a5bc 11138bfd_vma
6d4af3c2 11139x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 11140{
11141 if (flag_code == CODE_64BIT)
11142 {
11143 if (letter == 'l')
11144 return SHF_X86_64_LARGE;
11145
8f3bae45 11146 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 11147 }
3b22753a 11148 else
8f3bae45 11149 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 11150 return -1;
11151}
11152
01e1a5bc 11153bfd_vma
3b22753a
L		 11154x86_64_section_word (char *str, size_t len)
11155{
8620418b 11156 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11157 return SHF_X86_64_LARGE;
11158
11159 return -1;
11160}
11161
11162static void
11163handle_large_common (int small ATTRIBUTE_UNUSED)
11164{
11165 if (flag_code != CODE_64BIT)
11166 {
11167 s_comm_internal (0, elf_common_parse);
11168 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11169 }
11170 else
11171 {
11172 static segT lbss_section;
11173 asection *saved_com_section_ptr = elf_com_section_ptr;
11174 asection *saved_bss_section = bss_section;
11175
11176 if (lbss_section == NULL)
11177 {
11178 flagword applicable;
11179 segT seg = now_seg;
11180 subsegT subseg = now_subseg;
11181
11182 /* The .lbss section is for local .largecomm symbols. */
11183 lbss_section = subseg_new (".lbss", 0);
11184 applicable = bfd_applicable_section_flags (stdoutput);
11185 bfd_set_section_flags (stdoutput, lbss_section,
11186 applicable & SEC_ALLOC);
11187 seg_info (lbss_section)->bss = 1;
11188
11189 subseg_set (seg, subseg);
11190 }
11191
11192 elf_com_section_ptr = &_bfd_elf_large_com_section;
11193 bss_section = lbss_section;
11194
11195 s_comm_internal (0, elf_common_parse);
11196
11197 elf_com_section_ptr = saved_com_section_ptr;
11198 bss_section = saved_bss_section;
11199 }
11200}
11201#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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