Commit | Line | Data |
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252b5132 | 1 | /* i386.c -- Assemble code for the Intel 80386 |
f7e42eb4 | 2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
0f10071e | 3 | 2000, 2001, 2002, 2003, 2004 |
47926f60 | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | |
6 | This file is part of GAS, the GNU Assembler. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS; see the file COPYING. If not, write to the Free | |
20 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
21 | 02111-1307, USA. */ | |
22 | ||
47926f60 KH |
23 | /* Intel 80386 machine specific gas. |
24 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 25 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
27 | Bugs & suggestions are completely welcome. This is free software. |
28 | Please help us make it better. */ | |
252b5132 | 29 | |
252b5132 | 30 | #include "as.h" |
3882b010 | 31 | #include "safe-ctype.h" |
252b5132 | 32 | #include "subsegs.h" |
316e2c05 | 33 | #include "dwarf2dbg.h" |
54cfded0 | 34 | #include "dw2gencfi.h" |
252b5132 | 35 | #include "opcode/i386.h" |
d2b2c203 | 36 | #include "elf/x86-64.h" |
252b5132 | 37 | |
252b5132 RH |
38 | #ifndef REGISTER_WARNINGS |
39 | #define REGISTER_WARNINGS 1 | |
40 | #endif | |
41 | ||
c3332e24 | 42 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 43 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
44 | #endif |
45 | ||
252b5132 RH |
46 | #ifndef SCALE1_WHEN_NO_INDEX |
47 | /* Specifying a scale factor besides 1 when there is no index is | |
48 | futile. eg. `mov (%ebx,2),%al' does exactly the same as | |
49 | `mov (%ebx),%al'. To slavishly follow what the programmer | |
50 | specified, set SCALE1_WHEN_NO_INDEX to 0. */ | |
51 | #define SCALE1_WHEN_NO_INDEX 1 | |
52 | #endif | |
53 | ||
29b0f896 AM |
54 | #ifndef DEFAULT_ARCH |
55 | #define DEFAULT_ARCH "i386" | |
246fcdee | 56 | #endif |
252b5132 | 57 | |
edde18a5 AM |
58 | #ifndef INLINE |
59 | #if __GNUC__ >= 2 | |
60 | #define INLINE __inline__ | |
61 | #else | |
62 | #define INLINE | |
63 | #endif | |
64 | #endif | |
65 | ||
29b0f896 AM |
66 | static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int)); |
67 | static INLINE int fits_in_signed_byte PARAMS ((offsetT)); | |
68 | static INLINE int fits_in_unsigned_byte PARAMS ((offsetT)); | |
69 | static INLINE int fits_in_unsigned_word PARAMS ((offsetT)); | |
70 | static INLINE int fits_in_signed_word PARAMS ((offsetT)); | |
71 | static INLINE int fits_in_unsigned_long PARAMS ((offsetT)); | |
72 | static INLINE int fits_in_signed_long PARAMS ((offsetT)); | |
847f7ad4 AM |
73 | static int smallest_imm_type PARAMS ((offsetT)); |
74 | static offsetT offset_in_range PARAMS ((offsetT, int)); | |
252b5132 | 75 | static int add_prefix PARAMS ((unsigned int)); |
3e73aa7c | 76 | static void set_code_flag PARAMS ((int)); |
47926f60 | 77 | static void set_16bit_gcc_code_flag PARAMS ((int)); |
252b5132 | 78 | static void set_intel_syntax PARAMS ((int)); |
e413e4e9 | 79 | static void set_cpu_arch PARAMS ((int)); |
6482c264 NC |
80 | #ifdef TE_PE |
81 | static void pe_directive_secrel PARAMS ((int)); | |
82 | #endif | |
29b0f896 AM |
83 | static char *output_invalid PARAMS ((int c)); |
84 | static int i386_operand PARAMS ((char *operand_string)); | |
85 | static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float)); | |
86 | static const reg_entry *parse_register PARAMS ((char *reg_string, | |
87 | char **end_op)); | |
88 | static char *parse_insn PARAMS ((char *, char *)); | |
89 | static char *parse_operands PARAMS ((char *, const char *)); | |
90 | static void swap_operands PARAMS ((void)); | |
91 | static void optimize_imm PARAMS ((void)); | |
92 | static void optimize_disp PARAMS ((void)); | |
93 | static int match_template PARAMS ((void)); | |
94 | static int check_string PARAMS ((void)); | |
95 | static int process_suffix PARAMS ((void)); | |
96 | static int check_byte_reg PARAMS ((void)); | |
97 | static int check_long_reg PARAMS ((void)); | |
98 | static int check_qword_reg PARAMS ((void)); | |
99 | static int check_word_reg PARAMS ((void)); | |
100 | static int finalize_imm PARAMS ((void)); | |
101 | static int process_operands PARAMS ((void)); | |
102 | static const seg_entry *build_modrm_byte PARAMS ((void)); | |
103 | static void output_insn PARAMS ((void)); | |
104 | static void output_branch PARAMS ((void)); | |
105 | static void output_jump PARAMS ((void)); | |
106 | static void output_interseg_jump PARAMS ((void)); | |
2bbd9c25 JJ |
107 | static void output_imm PARAMS ((fragS *insn_start_frag, |
108 | offsetT insn_start_off)); | |
109 | static void output_disp PARAMS ((fragS *insn_start_frag, | |
110 | offsetT insn_start_off)); | |
29b0f896 AM |
111 | #ifndef I386COFF |
112 | static void s_bss PARAMS ((int)); | |
252b5132 RH |
113 | #endif |
114 | ||
a847613f | 115 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 116 | |
252b5132 | 117 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 118 | i386_insn. */ |
252b5132 | 119 | |
520dc8e8 AM |
120 | union i386_op |
121 | { | |
122 | expressionS *disps; | |
123 | expressionS *imms; | |
124 | const reg_entry *regs; | |
125 | }; | |
126 | ||
252b5132 RH |
127 | struct _i386_insn |
128 | { | |
47926f60 | 129 | /* TM holds the template for the insn were currently assembling. */ |
252b5132 RH |
130 | template tm; |
131 | ||
132 | /* SUFFIX holds the instruction mnemonic suffix if given. | |
133 | (e.g. 'l' for 'movl') */ | |
134 | char suffix; | |
135 | ||
47926f60 | 136 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
137 | unsigned int operands; |
138 | ||
139 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
140 | of given register, displacement, memory operands and immediate | |
47926f60 | 141 | operands. */ |
252b5132 RH |
142 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
143 | ||
144 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 145 | use OP[i] for the corresponding operand. */ |
252b5132 RH |
146 | unsigned int types[MAX_OPERANDS]; |
147 | ||
520dc8e8 AM |
148 | /* Displacement expression, immediate expression, or register for each |
149 | operand. */ | |
150 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 151 | |
3e73aa7c JH |
152 | /* Flags for operands. */ |
153 | unsigned int flags[MAX_OPERANDS]; | |
154 | #define Operand_PCrel 1 | |
155 | ||
252b5132 | 156 | /* Relocation type for operand */ |
f86103b7 | 157 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 158 | |
252b5132 RH |
159 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
160 | the base index byte below. */ | |
161 | const reg_entry *base_reg; | |
162 | const reg_entry *index_reg; | |
163 | unsigned int log2_scale_factor; | |
164 | ||
165 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 166 | explicit segment overrides are given. */ |
ce8a8b2f | 167 | const seg_entry *seg[2]; |
252b5132 RH |
168 | |
169 | /* PREFIX holds all the given prefix opcodes (usually null). | |
170 | PREFIXES is the number of prefix opcodes. */ | |
171 | unsigned int prefixes; | |
172 | unsigned char prefix[MAX_PREFIXES]; | |
173 | ||
174 | /* RM and SIB are the modrm byte and the sib byte where the | |
175 | addressing modes of this insn are encoded. */ | |
176 | ||
177 | modrm_byte rm; | |
3e73aa7c | 178 | rex_byte rex; |
252b5132 RH |
179 | sib_byte sib; |
180 | }; | |
181 | ||
182 | typedef struct _i386_insn i386_insn; | |
183 | ||
184 | /* List of chars besides those in app.c:symbol_chars that can start an | |
185 | operand. Used to prevent the scrubber eating vital white-space. */ | |
32137342 | 186 | const char extra_symbol_chars[] = "*%-([" |
252b5132 | 187 | #ifdef LEX_AT |
32137342 NC |
188 | "@" |
189 | #endif | |
190 | #ifdef LEX_QM | |
191 | "?" | |
252b5132 | 192 | #endif |
32137342 | 193 | ; |
252b5132 | 194 | |
29b0f896 AM |
195 | #if (defined (TE_I386AIX) \ |
196 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
197 | && !defined (TE_LINUX) \ | |
32137342 | 198 | && !defined (TE_NETWARE) \ |
29b0f896 AM |
199 | && !defined (TE_FreeBSD) \ |
200 | && !defined (TE_NetBSD))) | |
252b5132 | 201 | /* This array holds the chars that always start a comment. If the |
ce8a8b2f | 202 | pre-processor is disabled, these aren't very useful. */ |
252b5132 RH |
203 | const char comment_chars[] = "#/"; |
204 | #define PREFIX_SEPARATOR '\\' | |
252b5132 RH |
205 | |
206 | /* This array holds the chars that only start a comment at the beginning of | |
207 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
208 | .line and .file directives will appear in the pre-processed output. |
209 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 210 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
211 | #NO_APP at the beginning of its output. |
212 | Also note that comments started like this one will always work if | |
252b5132 | 213 | '/' isn't otherwise defined. */ |
0d9f6d04 | 214 | const char line_comment_chars[] = "#"; |
29b0f896 | 215 | |
252b5132 | 216 | #else |
29b0f896 AM |
217 | /* Putting '/' here makes it impossible to use the divide operator. |
218 | However, we need it for compatibility with SVR4 systems. */ | |
219 | const char comment_chars[] = "#"; | |
220 | #define PREFIX_SEPARATOR '/' | |
221 | ||
0d9f6d04 | 222 | const char line_comment_chars[] = "/#"; |
252b5132 RH |
223 | #endif |
224 | ||
63a0b638 | 225 | const char line_separator_chars[] = ";"; |
252b5132 | 226 | |
ce8a8b2f AM |
227 | /* Chars that can be used to separate mant from exp in floating point |
228 | nums. */ | |
252b5132 RH |
229 | const char EXP_CHARS[] = "eE"; |
230 | ||
ce8a8b2f AM |
231 | /* Chars that mean this number is a floating point constant |
232 | As in 0f12.456 | |
233 | or 0d1.2345e12. */ | |
252b5132 RH |
234 | const char FLT_CHARS[] = "fFdDxX"; |
235 | ||
ce8a8b2f | 236 | /* Tables for lexical analysis. */ |
252b5132 RH |
237 | static char mnemonic_chars[256]; |
238 | static char register_chars[256]; | |
239 | static char operand_chars[256]; | |
240 | static char identifier_chars[256]; | |
241 | static char digit_chars[256]; | |
242 | ||
ce8a8b2f | 243 | /* Lexical macros. */ |
252b5132 RH |
244 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
245 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
246 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
247 | #define is_space_char(x) ((x) == ' ') | |
248 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
249 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
250 | ||
0234cb7c | 251 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
252 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
253 | ||
254 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
255 | effect this we maintain a stack of saved characters that we've smashed | |
256 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 257 | assembler instruction). */ |
252b5132 | 258 | static char save_stack[32]; |
ce8a8b2f | 259 | static char *save_stack_p; |
252b5132 RH |
260 | #define END_STRING_AND_SAVE(s) \ |
261 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
262 | #define RESTORE_END_STRING(s) \ | |
263 | do { *(s) = *--save_stack_p; } while (0) | |
264 | ||
47926f60 | 265 | /* The instruction we're assembling. */ |
252b5132 RH |
266 | static i386_insn i; |
267 | ||
268 | /* Possible templates for current insn. */ | |
269 | static const templates *current_templates; | |
270 | ||
47926f60 | 271 | /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */ |
252b5132 RH |
272 | static expressionS disp_expressions[2], im_expressions[2]; |
273 | ||
47926f60 KH |
274 | /* Current operand we are working on. */ |
275 | static int this_operand; | |
252b5132 | 276 | |
3e73aa7c JH |
277 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
278 | these. */ | |
279 | ||
280 | enum flag_code { | |
281 | CODE_32BIT, | |
282 | CODE_16BIT, | |
283 | CODE_64BIT }; | |
f3c180ae | 284 | #define NUM_FLAG_CODE ((int) CODE_64BIT + 1) |
3e73aa7c JH |
285 | |
286 | static enum flag_code flag_code; | |
287 | static int use_rela_relocations = 0; | |
288 | ||
289 | /* The names used to print error messages. */ | |
b77a7acd | 290 | static const char *flag_code_names[] = |
3e73aa7c JH |
291 | { |
292 | "32", | |
293 | "16", | |
294 | "64" | |
295 | }; | |
252b5132 | 296 | |
47926f60 KH |
297 | /* 1 for intel syntax, |
298 | 0 if att syntax. */ | |
299 | static int intel_syntax = 0; | |
252b5132 | 300 | |
47926f60 KH |
301 | /* 1 if register prefix % not required. */ |
302 | static int allow_naked_reg = 0; | |
252b5132 | 303 | |
47926f60 KH |
304 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
305 | leave, push, and pop instructions so that gcc has the same stack | |
306 | frame as in 32 bit mode. */ | |
307 | static char stackop_size = '\0'; | |
eecb386c | 308 | |
12b55ccc L |
309 | /* Non-zero to optimize code alignment. */ |
310 | int optimize_align_code = 1; | |
311 | ||
47926f60 KH |
312 | /* Non-zero to quieten some warnings. */ |
313 | static int quiet_warnings = 0; | |
a38cf1db | 314 | |
47926f60 KH |
315 | /* CPU name. */ |
316 | static const char *cpu_arch_name = NULL; | |
a38cf1db | 317 | |
47926f60 | 318 | /* CPU feature flags. */ |
29b0f896 | 319 | static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64; |
a38cf1db | 320 | |
fddf5b5b AM |
321 | /* If set, conditional jumps are not automatically promoted to handle |
322 | larger than a byte offset. */ | |
323 | static unsigned int no_cond_jump_promotion = 0; | |
324 | ||
29b0f896 AM |
325 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
326 | symbolS *GOT_symbol; | |
327 | ||
a4447b93 RH |
328 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
329 | unsigned int x86_dwarf2_return_column; | |
330 | ||
331 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
332 | int x86_cie_data_alignment; | |
333 | ||
252b5132 | 334 | /* Interface to relax_segment. |
fddf5b5b AM |
335 | There are 3 major relax states for 386 jump insns because the |
336 | different types of jumps add different sizes to frags when we're | |
337 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 338 | |
47926f60 | 339 | /* Types. */ |
93c2a809 AM |
340 | #define UNCOND_JUMP 0 |
341 | #define COND_JUMP 1 | |
342 | #define COND_JUMP86 2 | |
fddf5b5b | 343 | |
47926f60 | 344 | /* Sizes. */ |
252b5132 RH |
345 | #define CODE16 1 |
346 | #define SMALL 0 | |
29b0f896 | 347 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 348 | #define BIG 2 |
29b0f896 | 349 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
350 | |
351 | #ifndef INLINE | |
352 | #ifdef __GNUC__ | |
353 | #define INLINE __inline__ | |
354 | #else | |
355 | #define INLINE | |
356 | #endif | |
357 | #endif | |
358 | ||
fddf5b5b AM |
359 | #define ENCODE_RELAX_STATE(type, size) \ |
360 | ((relax_substateT) (((type) << 2) | (size))) | |
361 | #define TYPE_FROM_RELAX_STATE(s) \ | |
362 | ((s) >> 2) | |
363 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
364 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
365 | |
366 | /* This table is used by relax_frag to promote short jumps to long | |
367 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
368 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
369 | don't allow a short jump in a 32 bit code segment to be promoted to | |
370 | a 16 bit offset jump because it's slower (requires data size | |
371 | prefix), and doesn't work, unless the destination is in the bottom | |
372 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
373 | ||
374 | const relax_typeS md_relax_table[] = | |
375 | { | |
24eab124 AM |
376 | /* The fields are: |
377 | 1) most positive reach of this state, | |
378 | 2) most negative reach of this state, | |
93c2a809 | 379 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 380 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 381 | |
fddf5b5b | 382 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
383 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
384 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
385 | /* dword jmp adds 4 bytes to frag: | |
386 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 387 | {0, 0, 4, 0}, |
93c2a809 AM |
388 | /* word jmp adds 2 byte2 to frag: |
389 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
390 | {0, 0, 2, 0}, |
391 | ||
93c2a809 AM |
392 | /* COND_JUMP states. */ |
393 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
394 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
395 | /* dword conditionals adds 5 bytes to frag: | |
396 | 1 extra opcode byte, 4 displacement bytes. */ | |
397 | {0, 0, 5, 0}, | |
fddf5b5b | 398 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
399 | 1 extra opcode byte, 2 displacement bytes. */ |
400 | {0, 0, 3, 0}, | |
401 | ||
402 | /* COND_JUMP86 states. */ | |
403 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
404 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
405 | /* dword conditionals adds 5 bytes to frag: | |
406 | 1 extra opcode byte, 4 displacement bytes. */ | |
407 | {0, 0, 5, 0}, | |
408 | /* word conditionals add 4 bytes to frag: | |
409 | 1 displacement byte and a 3 byte long branch insn. */ | |
410 | {0, 0, 4, 0} | |
252b5132 RH |
411 | }; |
412 | ||
e413e4e9 AM |
413 | static const arch_entry cpu_arch[] = { |
414 | {"i8086", Cpu086 }, | |
415 | {"i186", Cpu086|Cpu186 }, | |
416 | {"i286", Cpu086|Cpu186|Cpu286 }, | |
417 | {"i386", Cpu086|Cpu186|Cpu286|Cpu386 }, | |
418 | {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 }, | |
419 | {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, | |
420 | {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, | |
421 | {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, | |
422 | {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, | |
a167610d | 423 | {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 }, |
3e73aa7c JH |
424 | {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow }, |
425 | {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow }, | |
a167610d | 426 | {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 }, |
e413e4e9 AM |
427 | {NULL, 0 } |
428 | }; | |
429 | ||
29b0f896 AM |
430 | const pseudo_typeS md_pseudo_table[] = |
431 | { | |
432 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
433 | {"align", s_align_bytes, 0}, | |
434 | #else | |
435 | {"align", s_align_ptwo, 0}, | |
436 | #endif | |
437 | {"arch", set_cpu_arch, 0}, | |
438 | #ifndef I386COFF | |
439 | {"bss", s_bss, 0}, | |
440 | #endif | |
441 | {"ffloat", float_cons, 'f'}, | |
442 | {"dfloat", float_cons, 'd'}, | |
443 | {"tfloat", float_cons, 'x'}, | |
444 | {"value", cons, 2}, | |
445 | {"noopt", s_ignore, 0}, | |
446 | {"optim", s_ignore, 0}, | |
447 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
448 | {"code16", set_code_flag, CODE_16BIT}, | |
449 | {"code32", set_code_flag, CODE_32BIT}, | |
450 | {"code64", set_code_flag, CODE_64BIT}, | |
451 | {"intel_syntax", set_intel_syntax, 1}, | |
452 | {"att_syntax", set_intel_syntax, 0}, | |
c6682705 | 453 | {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0}, |
29b0f896 | 454 | {"loc", dwarf2_directive_loc, 0}, |
6482c264 NC |
455 | #ifdef TE_PE |
456 | {"secrel32", pe_directive_secrel, 0}, | |
457 | #endif | |
29b0f896 AM |
458 | {0, 0, 0} |
459 | }; | |
460 | ||
461 | /* For interface with expression (). */ | |
462 | extern char *input_line_pointer; | |
463 | ||
464 | /* Hash table for instruction mnemonic lookup. */ | |
465 | static struct hash_control *op_hash; | |
466 | ||
467 | /* Hash table for register lookup. */ | |
468 | static struct hash_control *reg_hash; | |
469 | \f | |
252b5132 RH |
470 | void |
471 | i386_align_code (fragP, count) | |
472 | fragS *fragP; | |
473 | int count; | |
474 | { | |
ce8a8b2f AM |
475 | /* Various efficient no-op patterns for aligning code labels. |
476 | Note: Don't try to assemble the instructions in the comments. | |
477 | 0L and 0w are not legal. */ | |
252b5132 RH |
478 | static const char f32_1[] = |
479 | {0x90}; /* nop */ | |
480 | static const char f32_2[] = | |
481 | {0x89,0xf6}; /* movl %esi,%esi */ | |
482 | static const char f32_3[] = | |
483 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
484 | static const char f32_4[] = | |
485 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
486 | static const char f32_5[] = | |
487 | {0x90, /* nop */ | |
488 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
489 | static const char f32_6[] = | |
490 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
491 | static const char f32_7[] = | |
492 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
493 | static const char f32_8[] = | |
494 | {0x90, /* nop */ | |
495 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
496 | static const char f32_9[] = | |
497 | {0x89,0xf6, /* movl %esi,%esi */ | |
498 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
499 | static const char f32_10[] = | |
500 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
501 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
502 | static const char f32_11[] = | |
503 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
504 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
505 | static const char f32_12[] = | |
506 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
507 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
508 | static const char f32_13[] = | |
509 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
510 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
511 | static const char f32_14[] = | |
512 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
513 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
514 | static const char f32_15[] = | |
515 | {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ | |
516 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
c3332e24 AM |
517 | static const char f16_3[] = |
518 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ | |
252b5132 RH |
519 | static const char f16_4[] = |
520 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
521 | static const char f16_5[] = | |
522 | {0x90, /* nop */ | |
523 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
524 | static const char f16_6[] = | |
525 | {0x89,0xf6, /* mov %si,%si */ | |
526 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
527 | static const char f16_7[] = | |
528 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ | |
529 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
530 | static const char f16_8[] = | |
531 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ | |
532 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
533 | static const char *const f32_patt[] = { | |
534 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
535 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 | |
536 | }; | |
537 | static const char *const f16_patt[] = { | |
c3332e24 | 538 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8, |
252b5132 RH |
539 | f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 |
540 | }; | |
541 | ||
33fef721 JH |
542 | if (count <= 0 || count > 15) |
543 | return; | |
3e73aa7c | 544 | |
33fef721 JH |
545 | /* The recommended way to pad 64bit code is to use NOPs preceded by |
546 | maximally four 0x66 prefixes. Balance the size of nops. */ | |
547 | if (flag_code == CODE_64BIT) | |
252b5132 | 548 | { |
33fef721 JH |
549 | int i; |
550 | int nnops = (count + 3) / 4; | |
551 | int len = count / nnops; | |
552 | int remains = count - nnops * len; | |
553 | int pos = 0; | |
554 | ||
555 | for (i = 0; i < remains; i++) | |
252b5132 | 556 | { |
33fef721 JH |
557 | memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len); |
558 | fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90; | |
559 | pos += len + 1; | |
560 | } | |
561 | for (; i < nnops; i++) | |
562 | { | |
563 | memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1); | |
564 | fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90; | |
565 | pos += len; | |
252b5132 | 566 | } |
252b5132 | 567 | } |
33fef721 JH |
568 | else |
569 | if (flag_code == CODE_16BIT) | |
570 | { | |
571 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
572 | f16_patt[count - 1], count); | |
573 | if (count > 8) | |
574 | /* Adjust jump offset. */ | |
575 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
576 | } | |
577 | else | |
578 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
579 | f32_patt[count - 1], count); | |
580 | fragP->fr_var = count; | |
252b5132 RH |
581 | } |
582 | ||
252b5132 RH |
583 | static INLINE unsigned int |
584 | mode_from_disp_size (t) | |
585 | unsigned int t; | |
586 | { | |
3e73aa7c | 587 | return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0; |
252b5132 RH |
588 | } |
589 | ||
590 | static INLINE int | |
591 | fits_in_signed_byte (num) | |
847f7ad4 | 592 | offsetT num; |
252b5132 RH |
593 | { |
594 | return (num >= -128) && (num <= 127); | |
47926f60 | 595 | } |
252b5132 RH |
596 | |
597 | static INLINE int | |
598 | fits_in_unsigned_byte (num) | |
847f7ad4 | 599 | offsetT num; |
252b5132 RH |
600 | { |
601 | return (num & 0xff) == num; | |
47926f60 | 602 | } |
252b5132 RH |
603 | |
604 | static INLINE int | |
605 | fits_in_unsigned_word (num) | |
847f7ad4 | 606 | offsetT num; |
252b5132 RH |
607 | { |
608 | return (num & 0xffff) == num; | |
47926f60 | 609 | } |
252b5132 RH |
610 | |
611 | static INLINE int | |
612 | fits_in_signed_word (num) | |
847f7ad4 | 613 | offsetT num; |
252b5132 RH |
614 | { |
615 | return (-32768 <= num) && (num <= 32767); | |
47926f60 | 616 | } |
3e73aa7c JH |
617 | static INLINE int |
618 | fits_in_signed_long (num) | |
619 | offsetT num ATTRIBUTE_UNUSED; | |
620 | { | |
621 | #ifndef BFD64 | |
622 | return 1; | |
623 | #else | |
624 | return (!(((offsetT) -1 << 31) & num) | |
625 | || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); | |
626 | #endif | |
627 | } /* fits_in_signed_long() */ | |
628 | static INLINE int | |
629 | fits_in_unsigned_long (num) | |
630 | offsetT num ATTRIBUTE_UNUSED; | |
631 | { | |
632 | #ifndef BFD64 | |
633 | return 1; | |
634 | #else | |
635 | return (num & (((offsetT) 2 << 31) - 1)) == num; | |
636 | #endif | |
637 | } /* fits_in_unsigned_long() */ | |
252b5132 RH |
638 | |
639 | static int | |
640 | smallest_imm_type (num) | |
847f7ad4 | 641 | offsetT num; |
252b5132 | 642 | { |
a847613f | 643 | if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64)) |
e413e4e9 AM |
644 | { |
645 | /* This code is disabled on the 486 because all the Imm1 forms | |
646 | in the opcode table are slower on the i486. They're the | |
647 | versions with the implicitly specified single-position | |
648 | displacement, which has another syntax if you really want to | |
649 | use that form. */ | |
650 | if (num == 1) | |
3e73aa7c | 651 | return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64; |
e413e4e9 | 652 | } |
252b5132 | 653 | return (fits_in_signed_byte (num) |
3e73aa7c | 654 | ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64) |
252b5132 | 655 | : fits_in_unsigned_byte (num) |
3e73aa7c | 656 | ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64) |
252b5132 | 657 | : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) |
3e73aa7c JH |
658 | ? (Imm16 | Imm32 | Imm32S | Imm64) |
659 | : fits_in_signed_long (num) | |
660 | ? (Imm32 | Imm32S | Imm64) | |
661 | : fits_in_unsigned_long (num) | |
662 | ? (Imm32 | Imm64) | |
663 | : Imm64); | |
47926f60 | 664 | } |
252b5132 | 665 | |
847f7ad4 AM |
666 | static offsetT |
667 | offset_in_range (val, size) | |
668 | offsetT val; | |
669 | int size; | |
670 | { | |
508866be | 671 | addressT mask; |
ba2adb93 | 672 | |
847f7ad4 AM |
673 | switch (size) |
674 | { | |
508866be L |
675 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
676 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 677 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
678 | #ifdef BFD64 |
679 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
680 | #endif | |
47926f60 | 681 | default: abort (); |
847f7ad4 AM |
682 | } |
683 | ||
ba2adb93 | 684 | /* If BFD64, sign extend val. */ |
3e73aa7c JH |
685 | if (!use_rela_relocations) |
686 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) | |
687 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
ba2adb93 | 688 | |
47926f60 | 689 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
690 | { |
691 | char buf1[40], buf2[40]; | |
692 | ||
693 | sprint_value (buf1, val); | |
694 | sprint_value (buf2, val & mask); | |
695 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
696 | } | |
697 | return val & mask; | |
698 | } | |
699 | ||
252b5132 RH |
700 | /* Returns 0 if attempting to add a prefix where one from the same |
701 | class already exists, 1 if non rep/repne added, 2 if rep/repne | |
702 | added. */ | |
703 | static int | |
704 | add_prefix (prefix) | |
705 | unsigned int prefix; | |
706 | { | |
707 | int ret = 1; | |
708 | int q; | |
709 | ||
29b0f896 AM |
710 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
711 | && flag_code == CODE_64BIT) | |
3e73aa7c JH |
712 | q = REX_PREFIX; |
713 | else | |
714 | switch (prefix) | |
715 | { | |
716 | default: | |
717 | abort (); | |
718 | ||
719 | case CS_PREFIX_OPCODE: | |
720 | case DS_PREFIX_OPCODE: | |
721 | case ES_PREFIX_OPCODE: | |
722 | case FS_PREFIX_OPCODE: | |
723 | case GS_PREFIX_OPCODE: | |
724 | case SS_PREFIX_OPCODE: | |
725 | q = SEG_PREFIX; | |
726 | break; | |
252b5132 | 727 | |
3e73aa7c JH |
728 | case REPNE_PREFIX_OPCODE: |
729 | case REPE_PREFIX_OPCODE: | |
730 | ret = 2; | |
731 | /* fall thru */ | |
732 | case LOCK_PREFIX_OPCODE: | |
733 | q = LOCKREP_PREFIX; | |
734 | break; | |
252b5132 | 735 | |
3e73aa7c JH |
736 | case FWAIT_OPCODE: |
737 | q = WAIT_PREFIX; | |
738 | break; | |
252b5132 | 739 | |
3e73aa7c JH |
740 | case ADDR_PREFIX_OPCODE: |
741 | q = ADDR_PREFIX; | |
742 | break; | |
252b5132 | 743 | |
3e73aa7c JH |
744 | case DATA_PREFIX_OPCODE: |
745 | q = DATA_PREFIX; | |
746 | break; | |
747 | } | |
252b5132 | 748 | |
29b0f896 | 749 | if (i.prefix[q] != 0) |
252b5132 RH |
750 | { |
751 | as_bad (_("same type of prefix used twice")); | |
752 | return 0; | |
753 | } | |
754 | ||
755 | i.prefixes += 1; | |
756 | i.prefix[q] = prefix; | |
757 | return ret; | |
758 | } | |
759 | ||
760 | static void | |
3e73aa7c | 761 | set_code_flag (value) |
e5cb08ac | 762 | int value; |
eecb386c | 763 | { |
3e73aa7c JH |
764 | flag_code = value; |
765 | cpu_arch_flags &= ~(Cpu64 | CpuNo64); | |
766 | cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); | |
767 | if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer)) | |
768 | { | |
769 | as_bad (_("64bit mode not supported on this CPU.")); | |
770 | } | |
771 | if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386)) | |
772 | { | |
773 | as_bad (_("32bit mode not supported on this CPU.")); | |
774 | } | |
eecb386c AM |
775 | stackop_size = '\0'; |
776 | } | |
777 | ||
778 | static void | |
3e73aa7c JH |
779 | set_16bit_gcc_code_flag (new_code_flag) |
780 | int new_code_flag; | |
252b5132 | 781 | { |
3e73aa7c JH |
782 | flag_code = new_code_flag; |
783 | cpu_arch_flags &= ~(Cpu64 | CpuNo64); | |
784 | cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); | |
785 | stackop_size = 'l'; | |
252b5132 RH |
786 | } |
787 | ||
788 | static void | |
789 | set_intel_syntax (syntax_flag) | |
eecb386c | 790 | int syntax_flag; |
252b5132 RH |
791 | { |
792 | /* Find out if register prefixing is specified. */ | |
793 | int ask_naked_reg = 0; | |
794 | ||
795 | SKIP_WHITESPACE (); | |
29b0f896 | 796 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 RH |
797 | { |
798 | char *string = input_line_pointer; | |
799 | int e = get_symbol_end (); | |
800 | ||
47926f60 | 801 | if (strcmp (string, "prefix") == 0) |
252b5132 | 802 | ask_naked_reg = 1; |
47926f60 | 803 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
804 | ask_naked_reg = -1; |
805 | else | |
d0b47220 | 806 | as_bad (_("bad argument to syntax directive.")); |
252b5132 RH |
807 | *input_line_pointer = e; |
808 | } | |
809 | demand_empty_rest_of_line (); | |
c3332e24 | 810 | |
252b5132 RH |
811 | intel_syntax = syntax_flag; |
812 | ||
813 | if (ask_naked_reg == 0) | |
f86103b7 AM |
814 | allow_naked_reg = (intel_syntax |
815 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
816 | else |
817 | allow_naked_reg = (ask_naked_reg < 0); | |
818 | } | |
819 | ||
e413e4e9 AM |
820 | static void |
821 | set_cpu_arch (dummy) | |
47926f60 | 822 | int dummy ATTRIBUTE_UNUSED; |
e413e4e9 | 823 | { |
47926f60 | 824 | SKIP_WHITESPACE (); |
e413e4e9 | 825 | |
29b0f896 | 826 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 AM |
827 | { |
828 | char *string = input_line_pointer; | |
829 | int e = get_symbol_end (); | |
830 | int i; | |
831 | ||
832 | for (i = 0; cpu_arch[i].name; i++) | |
833 | { | |
834 | if (strcmp (string, cpu_arch[i].name) == 0) | |
835 | { | |
836 | cpu_arch_name = cpu_arch[i].name; | |
fddf5b5b AM |
837 | cpu_arch_flags = (cpu_arch[i].flags |
838 | | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64)); | |
e413e4e9 AM |
839 | break; |
840 | } | |
841 | } | |
842 | if (!cpu_arch[i].name) | |
843 | as_bad (_("no such architecture: `%s'"), string); | |
844 | ||
845 | *input_line_pointer = e; | |
846 | } | |
847 | else | |
848 | as_bad (_("missing cpu architecture")); | |
849 | ||
fddf5b5b AM |
850 | no_cond_jump_promotion = 0; |
851 | if (*input_line_pointer == ',' | |
29b0f896 | 852 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b AM |
853 | { |
854 | char *string = ++input_line_pointer; | |
855 | int e = get_symbol_end (); | |
856 | ||
857 | if (strcmp (string, "nojumps") == 0) | |
858 | no_cond_jump_promotion = 1; | |
859 | else if (strcmp (string, "jumps") == 0) | |
860 | ; | |
861 | else | |
862 | as_bad (_("no such architecture modifier: `%s'"), string); | |
863 | ||
864 | *input_line_pointer = e; | |
865 | } | |
866 | ||
e413e4e9 AM |
867 | demand_empty_rest_of_line (); |
868 | } | |
869 | ||
b9d79e03 JH |
870 | unsigned long |
871 | i386_mach () | |
872 | { | |
873 | if (!strcmp (default_arch, "x86_64")) | |
874 | return bfd_mach_x86_64; | |
875 | else if (!strcmp (default_arch, "i386")) | |
876 | return bfd_mach_i386_i386; | |
877 | else | |
878 | as_fatal (_("Unknown architecture")); | |
879 | } | |
b9d79e03 | 880 | \f |
252b5132 RH |
881 | void |
882 | md_begin () | |
883 | { | |
884 | const char *hash_err; | |
885 | ||
47926f60 | 886 | /* Initialize op_hash hash table. */ |
252b5132 RH |
887 | op_hash = hash_new (); |
888 | ||
889 | { | |
29b0f896 AM |
890 | const template *optab; |
891 | templates *core_optab; | |
252b5132 | 892 | |
47926f60 KH |
893 | /* Setup for loop. */ |
894 | optab = i386_optab; | |
252b5132 RH |
895 | core_optab = (templates *) xmalloc (sizeof (templates)); |
896 | core_optab->start = optab; | |
897 | ||
898 | while (1) | |
899 | { | |
900 | ++optab; | |
901 | if (optab->name == NULL | |
902 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
903 | { | |
904 | /* different name --> ship out current template list; | |
47926f60 | 905 | add to hash table; & begin anew. */ |
252b5132 RH |
906 | core_optab->end = optab; |
907 | hash_err = hash_insert (op_hash, | |
908 | (optab - 1)->name, | |
909 | (PTR) core_optab); | |
910 | if (hash_err) | |
911 | { | |
252b5132 RH |
912 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
913 | (optab - 1)->name, | |
914 | hash_err); | |
915 | } | |
916 | if (optab->name == NULL) | |
917 | break; | |
918 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
919 | core_optab->start = optab; | |
920 | } | |
921 | } | |
922 | } | |
923 | ||
47926f60 | 924 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
925 | reg_hash = hash_new (); |
926 | { | |
29b0f896 | 927 | const reg_entry *regtab; |
252b5132 RH |
928 | |
929 | for (regtab = i386_regtab; | |
930 | regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]); | |
931 | regtab++) | |
932 | { | |
933 | hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); | |
934 | if (hash_err) | |
3e73aa7c JH |
935 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
936 | regtab->reg_name, | |
937 | hash_err); | |
252b5132 RH |
938 | } |
939 | } | |
940 | ||
47926f60 | 941 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 942 | { |
29b0f896 AM |
943 | int c; |
944 | char *p; | |
252b5132 RH |
945 | |
946 | for (c = 0; c < 256; c++) | |
947 | { | |
3882b010 | 948 | if (ISDIGIT (c)) |
252b5132 RH |
949 | { |
950 | digit_chars[c] = c; | |
951 | mnemonic_chars[c] = c; | |
952 | register_chars[c] = c; | |
953 | operand_chars[c] = c; | |
954 | } | |
3882b010 | 955 | else if (ISLOWER (c)) |
252b5132 RH |
956 | { |
957 | mnemonic_chars[c] = c; | |
958 | register_chars[c] = c; | |
959 | operand_chars[c] = c; | |
960 | } | |
3882b010 | 961 | else if (ISUPPER (c)) |
252b5132 | 962 | { |
3882b010 | 963 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
964 | register_chars[c] = mnemonic_chars[c]; |
965 | operand_chars[c] = c; | |
966 | } | |
967 | ||
3882b010 | 968 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
969 | identifier_chars[c] = c; |
970 | else if (c >= 128) | |
971 | { | |
972 | identifier_chars[c] = c; | |
973 | operand_chars[c] = c; | |
974 | } | |
975 | } | |
976 | ||
977 | #ifdef LEX_AT | |
978 | identifier_chars['@'] = '@'; | |
32137342 NC |
979 | #endif |
980 | #ifdef LEX_QM | |
981 | identifier_chars['?'] = '?'; | |
982 | operand_chars['?'] = '?'; | |
252b5132 | 983 | #endif |
252b5132 RH |
984 | digit_chars['-'] = '-'; |
985 | identifier_chars['_'] = '_'; | |
986 | identifier_chars['.'] = '.'; | |
987 | ||
988 | for (p = operand_special_chars; *p != '\0'; p++) | |
989 | operand_chars[(unsigned char) *p] = *p; | |
990 | } | |
991 | ||
992 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
993 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
994 | { | |
995 | record_alignment (text_section, 2); | |
996 | record_alignment (data_section, 2); | |
997 | record_alignment (bss_section, 2); | |
998 | } | |
999 | #endif | |
a4447b93 RH |
1000 | |
1001 | if (flag_code == CODE_64BIT) | |
1002 | { | |
1003 | x86_dwarf2_return_column = 16; | |
1004 | x86_cie_data_alignment = -8; | |
1005 | } | |
1006 | else | |
1007 | { | |
1008 | x86_dwarf2_return_column = 8; | |
1009 | x86_cie_data_alignment = -4; | |
1010 | } | |
252b5132 RH |
1011 | } |
1012 | ||
1013 | void | |
1014 | i386_print_statistics (file) | |
1015 | FILE *file; | |
1016 | { | |
1017 | hash_print_statistics (file, "i386 opcode", op_hash); | |
1018 | hash_print_statistics (file, "i386 register", reg_hash); | |
1019 | } | |
1020 | \f | |
252b5132 RH |
1021 | #ifdef DEBUG386 |
1022 | ||
ce8a8b2f | 1023 | /* Debugging routines for md_assemble. */ |
252b5132 RH |
1024 | static void pi PARAMS ((char *, i386_insn *)); |
1025 | static void pte PARAMS ((template *)); | |
1026 | static void pt PARAMS ((unsigned int)); | |
1027 | static void pe PARAMS ((expressionS *)); | |
1028 | static void ps PARAMS ((symbolS *)); | |
1029 | ||
1030 | static void | |
1031 | pi (line, x) | |
1032 | char *line; | |
1033 | i386_insn *x; | |
1034 | { | |
09f131f2 | 1035 | unsigned int i; |
252b5132 RH |
1036 | |
1037 | fprintf (stdout, "%s: template ", line); | |
1038 | pte (&x->tm); | |
09f131f2 JH |
1039 | fprintf (stdout, " address: base %s index %s scale %x\n", |
1040 | x->base_reg ? x->base_reg->reg_name : "none", | |
1041 | x->index_reg ? x->index_reg->reg_name : "none", | |
1042 | x->log2_scale_factor); | |
1043 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 1044 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
1045 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
1046 | x->sib.base, x->sib.index, x->sib.scale); | |
1047 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
29b0f896 AM |
1048 | (x->rex & REX_MODE64) != 0, |
1049 | (x->rex & REX_EXTX) != 0, | |
1050 | (x->rex & REX_EXTY) != 0, | |
1051 | (x->rex & REX_EXTZ) != 0); | |
252b5132 RH |
1052 | for (i = 0; i < x->operands; i++) |
1053 | { | |
1054 | fprintf (stdout, " #%d: ", i + 1); | |
1055 | pt (x->types[i]); | |
1056 | fprintf (stdout, "\n"); | |
1057 | if (x->types[i] | |
3f4438ab | 1058 | & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM)) |
520dc8e8 | 1059 | fprintf (stdout, "%s\n", x->op[i].regs->reg_name); |
252b5132 | 1060 | if (x->types[i] & Imm) |
520dc8e8 | 1061 | pe (x->op[i].imms); |
252b5132 | 1062 | if (x->types[i] & Disp) |
520dc8e8 | 1063 | pe (x->op[i].disps); |
252b5132 RH |
1064 | } |
1065 | } | |
1066 | ||
1067 | static void | |
1068 | pte (t) | |
1069 | template *t; | |
1070 | { | |
09f131f2 | 1071 | unsigned int i; |
252b5132 | 1072 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 1073 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
1074 | if (t->extension_opcode != None) |
1075 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
1076 | if (t->opcode_modifier & D) | |
1077 | fprintf (stdout, "D"); | |
1078 | if (t->opcode_modifier & W) | |
1079 | fprintf (stdout, "W"); | |
1080 | fprintf (stdout, "\n"); | |
1081 | for (i = 0; i < t->operands; i++) | |
1082 | { | |
1083 | fprintf (stdout, " #%d type ", i + 1); | |
1084 | pt (t->operand_types[i]); | |
1085 | fprintf (stdout, "\n"); | |
1086 | } | |
1087 | } | |
1088 | ||
1089 | static void | |
1090 | pe (e) | |
1091 | expressionS *e; | |
1092 | { | |
24eab124 | 1093 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
1094 | fprintf (stdout, " add_number %ld (%lx)\n", |
1095 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
1096 | if (e->X_add_symbol) |
1097 | { | |
1098 | fprintf (stdout, " add_symbol "); | |
1099 | ps (e->X_add_symbol); | |
1100 | fprintf (stdout, "\n"); | |
1101 | } | |
1102 | if (e->X_op_symbol) | |
1103 | { | |
1104 | fprintf (stdout, " op_symbol "); | |
1105 | ps (e->X_op_symbol); | |
1106 | fprintf (stdout, "\n"); | |
1107 | } | |
1108 | } | |
1109 | ||
1110 | static void | |
1111 | ps (s) | |
1112 | symbolS *s; | |
1113 | { | |
1114 | fprintf (stdout, "%s type %s%s", | |
1115 | S_GET_NAME (s), | |
1116 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
1117 | segment_name (S_GET_SEGMENT (s))); | |
1118 | } | |
1119 | ||
1120 | struct type_name | |
1121 | { | |
1122 | unsigned int mask; | |
1123 | char *tname; | |
1124 | } | |
1125 | ||
29b0f896 | 1126 | static const type_names[] = |
252b5132 RH |
1127 | { |
1128 | { Reg8, "r8" }, | |
1129 | { Reg16, "r16" }, | |
1130 | { Reg32, "r32" }, | |
09f131f2 | 1131 | { Reg64, "r64" }, |
252b5132 RH |
1132 | { Imm8, "i8" }, |
1133 | { Imm8S, "i8s" }, | |
1134 | { Imm16, "i16" }, | |
1135 | { Imm32, "i32" }, | |
09f131f2 JH |
1136 | { Imm32S, "i32s" }, |
1137 | { Imm64, "i64" }, | |
252b5132 RH |
1138 | { Imm1, "i1" }, |
1139 | { BaseIndex, "BaseIndex" }, | |
1140 | { Disp8, "d8" }, | |
1141 | { Disp16, "d16" }, | |
1142 | { Disp32, "d32" }, | |
09f131f2 JH |
1143 | { Disp32S, "d32s" }, |
1144 | { Disp64, "d64" }, | |
252b5132 RH |
1145 | { InOutPortReg, "InOutPortReg" }, |
1146 | { ShiftCount, "ShiftCount" }, | |
1147 | { Control, "control reg" }, | |
1148 | { Test, "test reg" }, | |
1149 | { Debug, "debug reg" }, | |
1150 | { FloatReg, "FReg" }, | |
1151 | { FloatAcc, "FAcc" }, | |
1152 | { SReg2, "SReg2" }, | |
1153 | { SReg3, "SReg3" }, | |
1154 | { Acc, "Acc" }, | |
1155 | { JumpAbsolute, "Jump Absolute" }, | |
1156 | { RegMMX, "rMMX" }, | |
3f4438ab | 1157 | { RegXMM, "rXMM" }, |
252b5132 RH |
1158 | { EsSeg, "es" }, |
1159 | { 0, "" } | |
1160 | }; | |
1161 | ||
1162 | static void | |
1163 | pt (t) | |
1164 | unsigned int t; | |
1165 | { | |
29b0f896 | 1166 | const struct type_name *ty; |
252b5132 | 1167 | |
09f131f2 JH |
1168 | for (ty = type_names; ty->mask; ty++) |
1169 | if (t & ty->mask) | |
1170 | fprintf (stdout, "%s, ", ty->tname); | |
252b5132 RH |
1171 | fflush (stdout); |
1172 | } | |
1173 | ||
1174 | #endif /* DEBUG386 */ | |
1175 | \f | |
29b0f896 AM |
1176 | static bfd_reloc_code_real_type reloc |
1177 | PARAMS ((int, int, int, bfd_reloc_code_real_type)); | |
252b5132 RH |
1178 | |
1179 | static bfd_reloc_code_real_type | |
3e73aa7c | 1180 | reloc (size, pcrel, sign, other) |
252b5132 RH |
1181 | int size; |
1182 | int pcrel; | |
3e73aa7c | 1183 | int sign; |
252b5132 RH |
1184 | bfd_reloc_code_real_type other; |
1185 | { | |
47926f60 KH |
1186 | if (other != NO_RELOC) |
1187 | return other; | |
252b5132 RH |
1188 | |
1189 | if (pcrel) | |
1190 | { | |
3e73aa7c | 1191 | if (!sign) |
e5cb08ac | 1192 | as_bad (_("There are no unsigned pc-relative relocations")); |
252b5132 RH |
1193 | switch (size) |
1194 | { | |
1195 | case 1: return BFD_RELOC_8_PCREL; | |
1196 | case 2: return BFD_RELOC_16_PCREL; | |
1197 | case 4: return BFD_RELOC_32_PCREL; | |
1198 | } | |
d0b47220 | 1199 | as_bad (_("can not do %d byte pc-relative relocation"), size); |
252b5132 RH |
1200 | } |
1201 | else | |
1202 | { | |
3e73aa7c | 1203 | if (sign) |
e5cb08ac | 1204 | switch (size) |
3e73aa7c JH |
1205 | { |
1206 | case 4: return BFD_RELOC_X86_64_32S; | |
1207 | } | |
1208 | else | |
1209 | switch (size) | |
1210 | { | |
1211 | case 1: return BFD_RELOC_8; | |
1212 | case 2: return BFD_RELOC_16; | |
1213 | case 4: return BFD_RELOC_32; | |
1214 | case 8: return BFD_RELOC_64; | |
1215 | } | |
1216 | as_bad (_("can not do %s %d byte relocation"), | |
1217 | sign ? "signed" : "unsigned", size); | |
252b5132 RH |
1218 | } |
1219 | ||
bfb32b52 | 1220 | abort (); |
252b5132 RH |
1221 | return BFD_RELOC_NONE; |
1222 | } | |
1223 | ||
47926f60 KH |
1224 | /* Here we decide which fixups can be adjusted to make them relative to |
1225 | the beginning of the section instead of the symbol. Basically we need | |
1226 | to make sure that the dynamic relocations are done correctly, so in | |
1227 | some cases we force the original symbol to be used. */ | |
1228 | ||
252b5132 | 1229 | int |
c0c949c7 | 1230 | tc_i386_fix_adjustable (fixP) |
31312f95 | 1231 | fixS *fixP ATTRIBUTE_UNUSED; |
252b5132 | 1232 | { |
6d249963 | 1233 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
31312f95 AM |
1234 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) |
1235 | return 1; | |
1236 | ||
a161fe53 AM |
1237 | /* Don't adjust pc-relative references to merge sections in 64-bit |
1238 | mode. */ | |
1239 | if (use_rela_relocations | |
1240 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
1241 | && fixP->fx_pcrel) | |
252b5132 | 1242 | return 0; |
31312f95 | 1243 | |
8d01d9a9 AJ |
1244 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
1245 | and changed later by validate_fix. */ | |
1246 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
1247 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
1248 | return 0; | |
1249 | ||
ce8a8b2f | 1250 | /* adjust_reloc_syms doesn't know about the GOT. */ |
252b5132 RH |
1251 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
1252 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
1253 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
13ae64f3 JJ |
1254 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
1255 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
1256 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
1257 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
1258 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
1259 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
1260 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
1261 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
3e73aa7c JH |
1262 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
1263 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 1264 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
bffbf940 JJ |
1265 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
1266 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
1267 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
1268 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF | |
1269 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
252b5132 RH |
1270 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
1271 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1272 | return 0; | |
31312f95 | 1273 | #endif |
252b5132 RH |
1274 | return 1; |
1275 | } | |
252b5132 | 1276 | |
29b0f896 | 1277 | static int intel_float_operand PARAMS ((const char *mnemonic)); |
b4cac588 AM |
1278 | |
1279 | static int | |
252b5132 | 1280 | intel_float_operand (mnemonic) |
29b0f896 | 1281 | const char *mnemonic; |
252b5132 | 1282 | { |
47926f60 | 1283 | if (mnemonic[0] == 'f' && mnemonic[1] == 'i') |
cc5ca5ce | 1284 | return 2; |
252b5132 RH |
1285 | |
1286 | if (mnemonic[0] == 'f') | |
1287 | return 1; | |
1288 | ||
1289 | return 0; | |
1290 | } | |
1291 | ||
1292 | /* This is the guts of the machine-dependent assembler. LINE points to a | |
1293 | machine dependent instruction. This function is supposed to emit | |
1294 | the frags/bytes it assembles to. */ | |
1295 | ||
1296 | void | |
1297 | md_assemble (line) | |
1298 | char *line; | |
1299 | { | |
252b5132 | 1300 | int j; |
252b5132 RH |
1301 | char mnemonic[MAX_MNEM_SIZE]; |
1302 | ||
47926f60 | 1303 | /* Initialize globals. */ |
252b5132 RH |
1304 | memset (&i, '\0', sizeof (i)); |
1305 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 1306 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
1307 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
1308 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 1309 | save_stack_p = save_stack; |
252b5132 RH |
1310 | |
1311 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
1312 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 1313 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 1314 | |
29b0f896 AM |
1315 | line = parse_insn (line, mnemonic); |
1316 | if (line == NULL) | |
1317 | return; | |
252b5132 | 1318 | |
29b0f896 AM |
1319 | line = parse_operands (line, mnemonic); |
1320 | if (line == NULL) | |
1321 | return; | |
252b5132 | 1322 | |
29b0f896 AM |
1323 | /* Now we've parsed the mnemonic into a set of templates, and have the |
1324 | operands at hand. */ | |
1325 | ||
1326 | /* All intel opcodes have reversed operands except for "bound" and | |
1327 | "enter". We also don't reverse intersegment "jmp" and "call" | |
1328 | instructions with 2 immediate operands so that the immediate segment | |
1329 | precedes the offset, as it does when in AT&T mode. "enter" and the | |
1330 | intersegment "jmp" and "call" instructions are the only ones that | |
1331 | have two immediate operands. */ | |
1332 | if (intel_syntax && i.operands > 1 | |
1333 | && (strcmp (mnemonic, "bound") != 0) | |
1334 | && !((i.types[0] & Imm) && (i.types[1] & Imm))) | |
1335 | swap_operands (); | |
1336 | ||
1337 | if (i.imm_operands) | |
1338 | optimize_imm (); | |
1339 | ||
1340 | if (i.disp_operands) | |
1341 | optimize_disp (); | |
1342 | ||
1343 | /* Next, we find a template that matches the given insn, | |
1344 | making sure the overlap of the given operands types is consistent | |
1345 | with the template operand types. */ | |
252b5132 | 1346 | |
29b0f896 AM |
1347 | if (!match_template ()) |
1348 | return; | |
252b5132 | 1349 | |
cd61ebfe AM |
1350 | if (intel_syntax) |
1351 | { | |
1352 | /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */ | |
1353 | if (SYSV386_COMPAT | |
1354 | && (i.tm.base_opcode & 0xfffffde0) == 0xdce0) | |
1355 | i.tm.base_opcode ^= FloatR; | |
1356 | ||
1357 | /* Zap movzx and movsx suffix. The suffix may have been set from | |
1358 | "word ptr" or "byte ptr" on the source operand, but we'll use | |
1359 | the suffix later to choose the destination register. */ | |
1360 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
1361 | i.suffix = 0; | |
1362 | } | |
24eab124 | 1363 | |
29b0f896 AM |
1364 | if (i.tm.opcode_modifier & FWait) |
1365 | if (!add_prefix (FWAIT_OPCODE)) | |
1366 | return; | |
252b5132 | 1367 | |
29b0f896 AM |
1368 | /* Check string instruction segment overrides. */ |
1369 | if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0) | |
1370 | { | |
1371 | if (!check_string ()) | |
5dd0794d | 1372 | return; |
29b0f896 | 1373 | } |
5dd0794d | 1374 | |
29b0f896 AM |
1375 | if (!process_suffix ()) |
1376 | return; | |
e413e4e9 | 1377 | |
29b0f896 AM |
1378 | /* Make still unresolved immediate matches conform to size of immediate |
1379 | given in i.suffix. */ | |
1380 | if (!finalize_imm ()) | |
1381 | return; | |
252b5132 | 1382 | |
29b0f896 AM |
1383 | if (i.types[0] & Imm1) |
1384 | i.imm_operands = 0; /* kludge for shift insns. */ | |
1385 | if (i.types[0] & ImplicitRegister) | |
1386 | i.reg_operands--; | |
1387 | if (i.types[1] & ImplicitRegister) | |
1388 | i.reg_operands--; | |
1389 | if (i.types[2] & ImplicitRegister) | |
1390 | i.reg_operands--; | |
252b5132 | 1391 | |
29b0f896 AM |
1392 | if (i.tm.opcode_modifier & ImmExt) |
1393 | { | |
02fc3089 L |
1394 | expressionS *exp; |
1395 | ||
ca164297 L |
1396 | if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0) |
1397 | { | |
67c1ffbe | 1398 | /* These Intel Prescott New Instructions have the fixed |
ca164297 L |
1399 | operands with an opcode suffix which is coded in the same |
1400 | place as an 8-bit immediate field would be. Here we check | |
1401 | those operands and remove them afterwards. */ | |
1402 | unsigned int x; | |
1403 | ||
a4622f40 | 1404 | for (x = 0; x < i.operands; x++) |
ca164297 L |
1405 | if (i.op[x].regs->reg_num != x) |
1406 | as_bad (_("can't use register '%%%s' as operand %d in '%s'."), | |
1407 | i.op[x].regs->reg_name, x + 1, i.tm.name); | |
1408 | i.operands = 0; | |
1409 | } | |
1410 | ||
29b0f896 AM |
1411 | /* These AMD 3DNow! and Intel Katmai New Instructions have an |
1412 | opcode suffix which is coded in the same place as an 8-bit | |
1413 | immediate field would be. Here we fake an 8-bit immediate | |
1414 | operand from the opcode suffix stored in tm.extension_opcode. */ | |
252b5132 | 1415 | |
29b0f896 | 1416 | assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS); |
252b5132 | 1417 | |
29b0f896 AM |
1418 | exp = &im_expressions[i.imm_operands++]; |
1419 | i.op[i.operands].imms = exp; | |
1420 | i.types[i.operands++] = Imm8; | |
1421 | exp->X_op = O_constant; | |
1422 | exp->X_add_number = i.tm.extension_opcode; | |
1423 | i.tm.extension_opcode = None; | |
1424 | } | |
252b5132 | 1425 | |
29b0f896 AM |
1426 | /* For insns with operands there are more diddles to do to the opcode. */ |
1427 | if (i.operands) | |
1428 | { | |
1429 | if (!process_operands ()) | |
1430 | return; | |
1431 | } | |
1432 | else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) | |
1433 | { | |
1434 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
1435 | as_warn (_("translating to `%sp'"), i.tm.name); | |
1436 | } | |
252b5132 | 1437 | |
29b0f896 AM |
1438 | /* Handle conversion of 'int $3' --> special int3 insn. */ |
1439 | if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) | |
1440 | { | |
1441 | i.tm.base_opcode = INT3_OPCODE; | |
1442 | i.imm_operands = 0; | |
1443 | } | |
252b5132 | 1444 | |
29b0f896 AM |
1445 | if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword)) |
1446 | && i.op[0].disps->X_op == O_constant) | |
1447 | { | |
1448 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
1449 | the absolute address given by the constant. Since ix86 jumps and | |
1450 | calls are pc relative, we need to generate a reloc. */ | |
1451 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
1452 | i.op[0].disps->X_op = O_symbol; | |
1453 | } | |
252b5132 | 1454 | |
29b0f896 AM |
1455 | if ((i.tm.opcode_modifier & Rex64) != 0) |
1456 | i.rex |= REX_MODE64; | |
252b5132 | 1457 | |
29b0f896 AM |
1458 | /* For 8 bit registers we need an empty rex prefix. Also if the |
1459 | instruction already has a prefix, we need to convert old | |
1460 | registers to new ones. */ | |
773f551c | 1461 | |
29b0f896 AM |
1462 | if (((i.types[0] & Reg8) != 0 |
1463 | && (i.op[0].regs->reg_flags & RegRex64) != 0) | |
1464 | || ((i.types[1] & Reg8) != 0 | |
1465 | && (i.op[1].regs->reg_flags & RegRex64) != 0) | |
1466 | || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0) | |
1467 | && i.rex != 0)) | |
1468 | { | |
1469 | int x; | |
726c5dcd | 1470 | |
29b0f896 AM |
1471 | i.rex |= REX_OPCODE; |
1472 | for (x = 0; x < 2; x++) | |
1473 | { | |
1474 | /* Look for 8 bit operand that uses old registers. */ | |
1475 | if ((i.types[x] & Reg8) != 0 | |
1476 | && (i.op[x].regs->reg_flags & RegRex64) == 0) | |
773f551c | 1477 | { |
29b0f896 AM |
1478 | /* In case it is "hi" register, give up. */ |
1479 | if (i.op[x].regs->reg_num > 3) | |
0477af35 | 1480 | as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."), |
29b0f896 | 1481 | i.op[x].regs->reg_name); |
773f551c | 1482 | |
29b0f896 AM |
1483 | /* Otherwise it is equivalent to the extended register. |
1484 | Since the encoding doesn't change this is merely | |
1485 | cosmetic cleanup for debug output. */ | |
1486 | ||
1487 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 1488 | } |
29b0f896 AM |
1489 | } |
1490 | } | |
773f551c | 1491 | |
29b0f896 AM |
1492 | if (i.rex != 0) |
1493 | add_prefix (REX_OPCODE | i.rex); | |
1494 | ||
1495 | /* We are ready to output the insn. */ | |
1496 | output_insn (); | |
1497 | } | |
1498 | ||
1499 | static char * | |
1500 | parse_insn (line, mnemonic) | |
1501 | char *line; | |
1502 | char *mnemonic; | |
1503 | { | |
1504 | char *l = line; | |
1505 | char *token_start = l; | |
1506 | char *mnem_p; | |
1507 | ||
1508 | /* Non-zero if we found a prefix only acceptable with string insns. */ | |
1509 | const char *expecting_string_instruction = NULL; | |
45288df1 | 1510 | |
29b0f896 AM |
1511 | while (1) |
1512 | { | |
1513 | mnem_p = mnemonic; | |
1514 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
1515 | { | |
1516 | mnem_p++; | |
1517 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 1518 | { |
29b0f896 AM |
1519 | as_bad (_("no such instruction: `%s'"), token_start); |
1520 | return NULL; | |
1521 | } | |
1522 | l++; | |
1523 | } | |
1524 | if (!is_space_char (*l) | |
1525 | && *l != END_OF_INSN | |
1526 | && *l != PREFIX_SEPARATOR | |
1527 | && *l != ',') | |
1528 | { | |
1529 | as_bad (_("invalid character %s in mnemonic"), | |
1530 | output_invalid (*l)); | |
1531 | return NULL; | |
1532 | } | |
1533 | if (token_start == l) | |
1534 | { | |
1535 | if (*l == PREFIX_SEPARATOR) | |
1536 | as_bad (_("expecting prefix; got nothing")); | |
1537 | else | |
1538 | as_bad (_("expecting mnemonic; got nothing")); | |
1539 | return NULL; | |
1540 | } | |
45288df1 | 1541 | |
29b0f896 AM |
1542 | /* Look up instruction (or prefix) via hash table. */ |
1543 | current_templates = hash_find (op_hash, mnemonic); | |
47926f60 | 1544 | |
29b0f896 AM |
1545 | if (*l != END_OF_INSN |
1546 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
1547 | && current_templates | |
1548 | && (current_templates->start->opcode_modifier & IsPrefix)) | |
1549 | { | |
1550 | /* If we are in 16-bit mode, do not allow addr16 or data16. | |
1551 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
1552 | if ((current_templates->start->opcode_modifier & (Size16 | Size32)) | |
1553 | && flag_code != CODE_64BIT | |
1554 | && (((current_templates->start->opcode_modifier & Size32) != 0) | |
1555 | ^ (flag_code == CODE_16BIT))) | |
1556 | { | |
1557 | as_bad (_("redundant %s prefix"), | |
1558 | current_templates->start->name); | |
1559 | return NULL; | |
45288df1 | 1560 | } |
29b0f896 AM |
1561 | /* Add prefix, checking for repeated prefixes. */ |
1562 | switch (add_prefix (current_templates->start->base_opcode)) | |
1563 | { | |
1564 | case 0: | |
1565 | return NULL; | |
1566 | case 2: | |
1567 | expecting_string_instruction = current_templates->start->name; | |
1568 | break; | |
1569 | } | |
1570 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
1571 | token_start = ++l; | |
1572 | } | |
1573 | else | |
1574 | break; | |
1575 | } | |
45288df1 | 1576 | |
29b0f896 AM |
1577 | if (!current_templates) |
1578 | { | |
1579 | /* See if we can get a match by trimming off a suffix. */ | |
1580 | switch (mnem_p[-1]) | |
1581 | { | |
1582 | case WORD_MNEM_SUFFIX: | |
1583 | case BYTE_MNEM_SUFFIX: | |
1584 | case QWORD_MNEM_SUFFIX: | |
1585 | i.suffix = mnem_p[-1]; | |
1586 | mnem_p[-1] = '\0'; | |
1587 | current_templates = hash_find (op_hash, mnemonic); | |
1588 | break; | |
1589 | case SHORT_MNEM_SUFFIX: | |
1590 | case LONG_MNEM_SUFFIX: | |
1591 | if (!intel_syntax) | |
1592 | { | |
1593 | i.suffix = mnem_p[-1]; | |
1594 | mnem_p[-1] = '\0'; | |
1595 | current_templates = hash_find (op_hash, mnemonic); | |
1596 | } | |
1597 | break; | |
252b5132 | 1598 | |
29b0f896 AM |
1599 | /* Intel Syntax. */ |
1600 | case 'd': | |
1601 | if (intel_syntax) | |
1602 | { | |
1603 | if (intel_float_operand (mnemonic)) | |
1604 | i.suffix = SHORT_MNEM_SUFFIX; | |
1605 | else | |
1606 | i.suffix = LONG_MNEM_SUFFIX; | |
1607 | mnem_p[-1] = '\0'; | |
1608 | current_templates = hash_find (op_hash, mnemonic); | |
1609 | } | |
1610 | break; | |
1611 | } | |
1612 | if (!current_templates) | |
1613 | { | |
1614 | as_bad (_("no such instruction: `%s'"), token_start); | |
1615 | return NULL; | |
1616 | } | |
1617 | } | |
252b5132 | 1618 | |
29b0f896 AM |
1619 | if (current_templates->start->opcode_modifier & (Jump | JumpByte)) |
1620 | { | |
1621 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
1622 | predict taken and predict not taken respectively. | |
1623 | I'm not sure that branch hints actually do anything on loop | |
1624 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
1625 | may work in the future and it doesn't hurt to accept them | |
1626 | now. */ | |
1627 | if (l[0] == ',' && l[1] == 'p') | |
1628 | { | |
1629 | if (l[2] == 't') | |
1630 | { | |
1631 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
1632 | return NULL; | |
1633 | l += 3; | |
1634 | } | |
1635 | else if (l[2] == 'n') | |
1636 | { | |
1637 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
1638 | return NULL; | |
1639 | l += 3; | |
1640 | } | |
1641 | } | |
1642 | } | |
1643 | /* Any other comma loses. */ | |
1644 | if (*l == ',') | |
1645 | { | |
1646 | as_bad (_("invalid character %s in mnemonic"), | |
1647 | output_invalid (*l)); | |
1648 | return NULL; | |
1649 | } | |
252b5132 | 1650 | |
29b0f896 AM |
1651 | /* Check if instruction is supported on specified architecture. */ |
1652 | if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64)) | |
1653 | & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))) | |
1654 | { | |
1655 | as_warn (_("`%s' is not supported on `%s'"), | |
1656 | current_templates->start->name, cpu_arch_name); | |
1657 | } | |
1658 | else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT)) | |
1659 | { | |
1660 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
1661 | } | |
252b5132 | 1662 | |
29b0f896 AM |
1663 | /* Check for rep/repne without a string instruction. */ |
1664 | if (expecting_string_instruction | |
1665 | && !(current_templates->start->opcode_modifier & IsString)) | |
1666 | { | |
1667 | as_bad (_("expecting string instruction after `%s'"), | |
1668 | expecting_string_instruction); | |
1669 | return NULL; | |
1670 | } | |
252b5132 | 1671 | |
29b0f896 AM |
1672 | return l; |
1673 | } | |
252b5132 | 1674 | |
29b0f896 AM |
1675 | static char * |
1676 | parse_operands (l, mnemonic) | |
1677 | char *l; | |
1678 | const char *mnemonic; | |
1679 | { | |
1680 | char *token_start; | |
3138f287 | 1681 | |
29b0f896 AM |
1682 | /* 1 if operand is pending after ','. */ |
1683 | unsigned int expecting_operand = 0; | |
252b5132 | 1684 | |
29b0f896 AM |
1685 | /* Non-zero if operand parens not balanced. */ |
1686 | unsigned int paren_not_balanced; | |
1687 | ||
1688 | while (*l != END_OF_INSN) | |
1689 | { | |
1690 | /* Skip optional white space before operand. */ | |
1691 | if (is_space_char (*l)) | |
1692 | ++l; | |
1693 | if (!is_operand_char (*l) && *l != END_OF_INSN) | |
1694 | { | |
1695 | as_bad (_("invalid character %s before operand %d"), | |
1696 | output_invalid (*l), | |
1697 | i.operands + 1); | |
1698 | return NULL; | |
1699 | } | |
1700 | token_start = l; /* after white space */ | |
1701 | paren_not_balanced = 0; | |
1702 | while (paren_not_balanced || *l != ',') | |
1703 | { | |
1704 | if (*l == END_OF_INSN) | |
1705 | { | |
1706 | if (paren_not_balanced) | |
1707 | { | |
1708 | if (!intel_syntax) | |
1709 | as_bad (_("unbalanced parenthesis in operand %d."), | |
1710 | i.operands + 1); | |
1711 | else | |
1712 | as_bad (_("unbalanced brackets in operand %d."), | |
1713 | i.operands + 1); | |
1714 | return NULL; | |
1715 | } | |
1716 | else | |
1717 | break; /* we are done */ | |
1718 | } | |
1719 | else if (!is_operand_char (*l) && !is_space_char (*l)) | |
1720 | { | |
1721 | as_bad (_("invalid character %s in operand %d"), | |
1722 | output_invalid (*l), | |
1723 | i.operands + 1); | |
1724 | return NULL; | |
1725 | } | |
1726 | if (!intel_syntax) | |
1727 | { | |
1728 | if (*l == '(') | |
1729 | ++paren_not_balanced; | |
1730 | if (*l == ')') | |
1731 | --paren_not_balanced; | |
1732 | } | |
1733 | else | |
1734 | { | |
1735 | if (*l == '[') | |
1736 | ++paren_not_balanced; | |
1737 | if (*l == ']') | |
1738 | --paren_not_balanced; | |
1739 | } | |
1740 | l++; | |
1741 | } | |
1742 | if (l != token_start) | |
1743 | { /* Yes, we've read in another operand. */ | |
1744 | unsigned int operand_ok; | |
1745 | this_operand = i.operands++; | |
1746 | if (i.operands > MAX_OPERANDS) | |
1747 | { | |
1748 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
1749 | MAX_OPERANDS); | |
1750 | return NULL; | |
1751 | } | |
1752 | /* Now parse operand adding info to 'i' as we go along. */ | |
1753 | END_STRING_AND_SAVE (l); | |
1754 | ||
1755 | if (intel_syntax) | |
1756 | operand_ok = | |
1757 | i386_intel_operand (token_start, | |
1758 | intel_float_operand (mnemonic)); | |
1759 | else | |
1760 | operand_ok = i386_operand (token_start); | |
1761 | ||
1762 | RESTORE_END_STRING (l); | |
1763 | if (!operand_ok) | |
1764 | return NULL; | |
1765 | } | |
1766 | else | |
1767 | { | |
1768 | if (expecting_operand) | |
1769 | { | |
1770 | expecting_operand_after_comma: | |
1771 | as_bad (_("expecting operand after ','; got nothing")); | |
1772 | return NULL; | |
1773 | } | |
1774 | if (*l == ',') | |
1775 | { | |
1776 | as_bad (_("expecting operand before ','; got nothing")); | |
1777 | return NULL; | |
1778 | } | |
1779 | } | |
7f3f1ea2 | 1780 | |
29b0f896 AM |
1781 | /* Now *l must be either ',' or END_OF_INSN. */ |
1782 | if (*l == ',') | |
1783 | { | |
1784 | if (*++l == END_OF_INSN) | |
1785 | { | |
1786 | /* Just skip it, if it's \n complain. */ | |
1787 | goto expecting_operand_after_comma; | |
1788 | } | |
1789 | expecting_operand = 1; | |
1790 | } | |
1791 | } | |
1792 | return l; | |
1793 | } | |
7f3f1ea2 | 1794 | |
29b0f896 AM |
1795 | static void |
1796 | swap_operands () | |
1797 | { | |
1798 | union i386_op temp_op; | |
1799 | unsigned int temp_type; | |
f86103b7 | 1800 | enum bfd_reloc_code_real temp_reloc; |
29b0f896 AM |
1801 | int xchg1 = 0; |
1802 | int xchg2 = 0; | |
252b5132 | 1803 | |
29b0f896 AM |
1804 | if (i.operands == 2) |
1805 | { | |
1806 | xchg1 = 0; | |
1807 | xchg2 = 1; | |
1808 | } | |
1809 | else if (i.operands == 3) | |
1810 | { | |
1811 | xchg1 = 0; | |
1812 | xchg2 = 2; | |
1813 | } | |
1814 | temp_type = i.types[xchg2]; | |
1815 | i.types[xchg2] = i.types[xchg1]; | |
1816 | i.types[xchg1] = temp_type; | |
1817 | temp_op = i.op[xchg2]; | |
1818 | i.op[xchg2] = i.op[xchg1]; | |
1819 | i.op[xchg1] = temp_op; | |
1820 | temp_reloc = i.reloc[xchg2]; | |
1821 | i.reloc[xchg2] = i.reloc[xchg1]; | |
1822 | i.reloc[xchg1] = temp_reloc; | |
1823 | ||
1824 | if (i.mem_operands == 2) | |
1825 | { | |
1826 | const seg_entry *temp_seg; | |
1827 | temp_seg = i.seg[0]; | |
1828 | i.seg[0] = i.seg[1]; | |
1829 | i.seg[1] = temp_seg; | |
1830 | } | |
1831 | } | |
252b5132 | 1832 | |
29b0f896 AM |
1833 | /* Try to ensure constant immediates are represented in the smallest |
1834 | opcode possible. */ | |
1835 | static void | |
1836 | optimize_imm () | |
1837 | { | |
1838 | char guess_suffix = 0; | |
1839 | int op; | |
252b5132 | 1840 | |
29b0f896 AM |
1841 | if (i.suffix) |
1842 | guess_suffix = i.suffix; | |
1843 | else if (i.reg_operands) | |
1844 | { | |
1845 | /* Figure out a suffix from the last register operand specified. | |
1846 | We can't do this properly yet, ie. excluding InOutPortReg, | |
1847 | but the following works for instructions with immediates. | |
1848 | In any case, we can't set i.suffix yet. */ | |
1849 | for (op = i.operands; --op >= 0;) | |
1850 | if (i.types[op] & Reg) | |
252b5132 | 1851 | { |
29b0f896 AM |
1852 | if (i.types[op] & Reg8) |
1853 | guess_suffix = BYTE_MNEM_SUFFIX; | |
1854 | else if (i.types[op] & Reg16) | |
1855 | guess_suffix = WORD_MNEM_SUFFIX; | |
1856 | else if (i.types[op] & Reg32) | |
1857 | guess_suffix = LONG_MNEM_SUFFIX; | |
1858 | else if (i.types[op] & Reg64) | |
1859 | guess_suffix = QWORD_MNEM_SUFFIX; | |
1860 | break; | |
252b5132 | 1861 | } |
29b0f896 AM |
1862 | } |
1863 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
1864 | guess_suffix = WORD_MNEM_SUFFIX; | |
1865 | ||
1866 | for (op = i.operands; --op >= 0;) | |
1867 | if (i.types[op] & Imm) | |
1868 | { | |
1869 | switch (i.op[op].imms->X_op) | |
252b5132 | 1870 | { |
29b0f896 AM |
1871 | case O_constant: |
1872 | /* If a suffix is given, this operand may be shortened. */ | |
1873 | switch (guess_suffix) | |
252b5132 | 1874 | { |
29b0f896 AM |
1875 | case LONG_MNEM_SUFFIX: |
1876 | i.types[op] |= Imm32 | Imm64; | |
1877 | break; | |
1878 | case WORD_MNEM_SUFFIX: | |
1879 | i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64; | |
1880 | break; | |
1881 | case BYTE_MNEM_SUFFIX: | |
1882 | i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64; | |
1883 | break; | |
252b5132 | 1884 | } |
252b5132 | 1885 | |
29b0f896 AM |
1886 | /* If this operand is at most 16 bits, convert it |
1887 | to a signed 16 bit number before trying to see | |
1888 | whether it will fit in an even smaller size. | |
1889 | This allows a 16-bit operand such as $0xffe0 to | |
1890 | be recognised as within Imm8S range. */ | |
1891 | if ((i.types[op] & Imm16) | |
1892 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) | |
252b5132 | 1893 | { |
29b0f896 AM |
1894 | i.op[op].imms->X_add_number = |
1895 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
1896 | } | |
1897 | if ((i.types[op] & Imm32) | |
1898 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) | |
1899 | == 0)) | |
1900 | { | |
1901 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
1902 | ^ ((offsetT) 1 << 31)) | |
1903 | - ((offsetT) 1 << 31)); | |
1904 | } | |
1905 | i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number); | |
252b5132 | 1906 | |
29b0f896 AM |
1907 | /* We must avoid matching of Imm32 templates when 64bit |
1908 | only immediate is available. */ | |
1909 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
1910 | i.types[op] &= ~Imm32; | |
1911 | break; | |
252b5132 | 1912 | |
29b0f896 AM |
1913 | case O_absent: |
1914 | case O_register: | |
1915 | abort (); | |
1916 | ||
1917 | /* Symbols and expressions. */ | |
1918 | default: | |
1919 | /* Convert symbolic operand to proper sizes for matching. */ | |
1920 | switch (guess_suffix) | |
1921 | { | |
1922 | case QWORD_MNEM_SUFFIX: | |
1923 | i.types[op] = Imm64 | Imm32S; | |
1924 | break; | |
1925 | case LONG_MNEM_SUFFIX: | |
20f0a1fc | 1926 | i.types[op] = Imm32; |
29b0f896 AM |
1927 | break; |
1928 | case WORD_MNEM_SUFFIX: | |
20f0a1fc | 1929 | i.types[op] = Imm16; |
29b0f896 AM |
1930 | break; |
1931 | case BYTE_MNEM_SUFFIX: | |
20f0a1fc | 1932 | i.types[op] = Imm8 | Imm8S; |
29b0f896 | 1933 | break; |
252b5132 | 1934 | } |
29b0f896 | 1935 | break; |
252b5132 | 1936 | } |
29b0f896 AM |
1937 | } |
1938 | } | |
47926f60 | 1939 | |
29b0f896 AM |
1940 | /* Try to use the smallest displacement type too. */ |
1941 | static void | |
1942 | optimize_disp () | |
1943 | { | |
1944 | int op; | |
3e73aa7c | 1945 | |
29b0f896 AM |
1946 | for (op = i.operands; --op >= 0;) |
1947 | if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant) | |
252b5132 | 1948 | { |
29b0f896 AM |
1949 | offsetT disp = i.op[op].disps->X_add_number; |
1950 | ||
1951 | if (i.types[op] & Disp16) | |
252b5132 | 1952 | { |
29b0f896 AM |
1953 | /* We know this operand is at most 16 bits, so |
1954 | convert to a signed 16 bit number before trying | |
1955 | to see whether it will fit in an even smaller | |
1956 | size. */ | |
1957 | ||
1958 | disp = (((disp & 0xffff) ^ 0x8000) - 0x8000); | |
252b5132 | 1959 | } |
29b0f896 | 1960 | else if (i.types[op] & Disp32) |
252b5132 | 1961 | { |
29b0f896 AM |
1962 | /* We know this operand is at most 32 bits, so convert to a |
1963 | signed 32 bit number before trying to see whether it will | |
1964 | fit in an even smaller size. */ | |
1965 | disp &= (((offsetT) 2 << 31) - 1); | |
1966 | disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 1967 | } |
29b0f896 | 1968 | if (flag_code == CODE_64BIT) |
252b5132 | 1969 | { |
29b0f896 AM |
1970 | if (fits_in_signed_long (disp)) |
1971 | i.types[op] |= Disp32S; | |
1972 | if (fits_in_unsigned_long (disp)) | |
1973 | i.types[op] |= Disp32; | |
252b5132 | 1974 | } |
29b0f896 AM |
1975 | if ((i.types[op] & (Disp32 | Disp32S | Disp16)) |
1976 | && fits_in_signed_byte (disp)) | |
1977 | i.types[op] |= Disp8; | |
252b5132 | 1978 | } |
29b0f896 AM |
1979 | } |
1980 | ||
1981 | static int | |
1982 | match_template () | |
1983 | { | |
1984 | /* Points to template once we've found it. */ | |
1985 | const template *t; | |
1986 | unsigned int overlap0, overlap1, overlap2; | |
1987 | unsigned int found_reverse_match; | |
1988 | int suffix_check; | |
1989 | ||
1990 | #define MATCH(overlap, given, template) \ | |
1991 | ((overlap & ~JumpAbsolute) \ | |
1992 | && (((given) & (BaseIndex | JumpAbsolute)) \ | |
1993 | == ((overlap) & (BaseIndex | JumpAbsolute)))) | |
1994 | ||
1995 | /* If given types r0 and r1 are registers they must be of the same type | |
1996 | unless the expected operand type register overlap is null. | |
1997 | Note that Acc in a template matches every size of reg. */ | |
1998 | #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \ | |
1999 | (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \ | |
2000 | || ((g0) & Reg) == ((g1) & Reg) \ | |
2001 | || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 ) | |
2002 | ||
2003 | overlap0 = 0; | |
2004 | overlap1 = 0; | |
2005 | overlap2 = 0; | |
2006 | found_reverse_match = 0; | |
2007 | suffix_check = (i.suffix == BYTE_MNEM_SUFFIX | |
2008 | ? No_bSuf | |
2009 | : (i.suffix == WORD_MNEM_SUFFIX | |
2010 | ? No_wSuf | |
2011 | : (i.suffix == SHORT_MNEM_SUFFIX | |
2012 | ? No_sSuf | |
2013 | : (i.suffix == LONG_MNEM_SUFFIX | |
2014 | ? No_lSuf | |
2015 | : (i.suffix == QWORD_MNEM_SUFFIX | |
2016 | ? No_qSuf | |
2017 | : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX | |
2018 | ? No_xSuf : 0)))))); | |
2019 | ||
20f0a1fc NC |
2020 | t = current_templates->start; |
2021 | if (i.suffix == QWORD_MNEM_SUFFIX | |
2022 | && flag_code != CODE_64BIT | |
2023 | && (!intel_syntax | |
2024 | || (!(t->opcode_modifier & IgnoreSize) | |
2025 | && ! intel_float_operand (t->name))) | |
2026 | && (!(t->operand_types[0] & (RegMMX | RegXMM)) | |
2027 | || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM))) | |
2028 | && (t->base_opcode != 0x0fc7 | |
2029 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
2030 | t = current_templates->end; | |
2031 | for (; t < current_templates->end; t++) | |
29b0f896 AM |
2032 | { |
2033 | /* Must have right number of operands. */ | |
2034 | if (i.operands != t->operands) | |
2035 | continue; | |
2036 | ||
2037 | /* Check the suffix, except for some instructions in intel mode. */ | |
2038 | if ((t->opcode_modifier & suffix_check) | |
2039 | && !(intel_syntax | |
2040 | && (t->opcode_modifier & IgnoreSize)) | |
2041 | && !(intel_syntax | |
2042 | && t->base_opcode == 0xd9 | |
2043 | && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */ | |
2044 | || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */ | |
2045 | continue; | |
2046 | ||
2047 | /* Do not verify operands when there are none. */ | |
2048 | else if (!t->operands) | |
2049 | { | |
2050 | if (t->cpu_flags & ~cpu_arch_flags) | |
2051 | continue; | |
2052 | /* We've found a match; break out of loop. */ | |
2053 | break; | |
2054 | } | |
252b5132 | 2055 | |
29b0f896 AM |
2056 | overlap0 = i.types[0] & t->operand_types[0]; |
2057 | switch (t->operands) | |
2058 | { | |
2059 | case 1: | |
2060 | if (!MATCH (overlap0, i.types[0], t->operand_types[0])) | |
2061 | continue; | |
2062 | break; | |
2063 | case 2: | |
2064 | case 3: | |
2065 | overlap1 = i.types[1] & t->operand_types[1]; | |
2066 | if (!MATCH (overlap0, i.types[0], t->operand_types[0]) | |
2067 | || !MATCH (overlap1, i.types[1], t->operand_types[1]) | |
2068 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
2069 | t->operand_types[0], | |
2070 | overlap1, i.types[1], | |
2071 | t->operand_types[1])) | |
2072 | { | |
2073 | /* Check if other direction is valid ... */ | |
2074 | if ((t->opcode_modifier & (D | FloatD)) == 0) | |
2075 | continue; | |
2076 | ||
2077 | /* Try reversing direction of operands. */ | |
2078 | overlap0 = i.types[0] & t->operand_types[1]; | |
2079 | overlap1 = i.types[1] & t->operand_types[0]; | |
2080 | if (!MATCH (overlap0, i.types[0], t->operand_types[1]) | |
2081 | || !MATCH (overlap1, i.types[1], t->operand_types[0]) | |
2082 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
2083 | t->operand_types[1], | |
2084 | overlap1, i.types[1], | |
2085 | t->operand_types[0])) | |
2086 | { | |
2087 | /* Does not match either direction. */ | |
2088 | continue; | |
2089 | } | |
2090 | /* found_reverse_match holds which of D or FloatDR | |
2091 | we've found. */ | |
2092 | found_reverse_match = t->opcode_modifier & (D | FloatDR); | |
2093 | } | |
2094 | /* Found a forward 2 operand match here. */ | |
2095 | else if (t->operands == 3) | |
2096 | { | |
2097 | /* Here we make use of the fact that there are no | |
2098 | reverse match 3 operand instructions, and all 3 | |
2099 | operand instructions only need to be checked for | |
2100 | register consistency between operands 2 and 3. */ | |
2101 | overlap2 = i.types[2] & t->operand_types[2]; | |
2102 | if (!MATCH (overlap2, i.types[2], t->operand_types[2]) | |
2103 | || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1], | |
2104 | t->operand_types[1], | |
2105 | overlap2, i.types[2], | |
2106 | t->operand_types[2])) | |
2107 | ||
2108 | continue; | |
2109 | } | |
2110 | /* Found either forward/reverse 2 or 3 operand match here: | |
2111 | slip through to break. */ | |
2112 | } | |
2113 | if (t->cpu_flags & ~cpu_arch_flags) | |
2114 | { | |
2115 | found_reverse_match = 0; | |
2116 | continue; | |
2117 | } | |
2118 | /* We've found a match; break out of loop. */ | |
2119 | break; | |
2120 | } | |
2121 | ||
2122 | if (t == current_templates->end) | |
2123 | { | |
2124 | /* We found no match. */ | |
2125 | as_bad (_("suffix or operands invalid for `%s'"), | |
2126 | current_templates->start->name); | |
2127 | return 0; | |
2128 | } | |
252b5132 | 2129 | |
29b0f896 AM |
2130 | if (!quiet_warnings) |
2131 | { | |
2132 | if (!intel_syntax | |
2133 | && ((i.types[0] & JumpAbsolute) | |
2134 | != (t->operand_types[0] & JumpAbsolute))) | |
2135 | { | |
2136 | as_warn (_("indirect %s without `*'"), t->name); | |
2137 | } | |
2138 | ||
2139 | if ((t->opcode_modifier & (IsPrefix | IgnoreSize)) | |
2140 | == (IsPrefix | IgnoreSize)) | |
2141 | { | |
2142 | /* Warn them that a data or address size prefix doesn't | |
2143 | affect assembly of the next line of code. */ | |
2144 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
2145 | } | |
2146 | } | |
2147 | ||
2148 | /* Copy the template we found. */ | |
2149 | i.tm = *t; | |
2150 | if (found_reverse_match) | |
2151 | { | |
2152 | /* If we found a reverse match we must alter the opcode | |
2153 | direction bit. found_reverse_match holds bits to change | |
2154 | (different for int & float insns). */ | |
2155 | ||
2156 | i.tm.base_opcode ^= found_reverse_match; | |
2157 | ||
2158 | i.tm.operand_types[0] = t->operand_types[1]; | |
2159 | i.tm.operand_types[1] = t->operand_types[0]; | |
2160 | } | |
2161 | ||
2162 | return 1; | |
2163 | } | |
2164 | ||
2165 | static int | |
2166 | check_string () | |
2167 | { | |
2168 | int mem_op = (i.types[0] & AnyMem) ? 0 : 1; | |
2169 | if ((i.tm.operand_types[mem_op] & EsSeg) != 0) | |
2170 | { | |
2171 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
2172 | { | |
2173 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
2174 | i.tm.name, | |
2175 | mem_op + 1); | |
2176 | return 0; | |
2177 | } | |
2178 | /* There's only ever one segment override allowed per instruction. | |
2179 | This instruction possibly has a legal segment override on the | |
2180 | second operand, so copy the segment to where non-string | |
2181 | instructions store it, allowing common code. */ | |
2182 | i.seg[0] = i.seg[1]; | |
2183 | } | |
2184 | else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0) | |
2185 | { | |
2186 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
2187 | { | |
2188 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
2189 | i.tm.name, | |
2190 | mem_op + 2); | |
2191 | return 0; | |
2192 | } | |
2193 | } | |
2194 | return 1; | |
2195 | } | |
2196 | ||
2197 | static int | |
543613e9 | 2198 | process_suffix (void) |
29b0f896 AM |
2199 | { |
2200 | /* If matched instruction specifies an explicit instruction mnemonic | |
2201 | suffix, use it. */ | |
2202 | if (i.tm.opcode_modifier & (Size16 | Size32 | Size64)) | |
2203 | { | |
2204 | if (i.tm.opcode_modifier & Size16) | |
2205 | i.suffix = WORD_MNEM_SUFFIX; | |
2206 | else if (i.tm.opcode_modifier & Size64) | |
2207 | i.suffix = QWORD_MNEM_SUFFIX; | |
2208 | else | |
2209 | i.suffix = LONG_MNEM_SUFFIX; | |
2210 | } | |
2211 | else if (i.reg_operands) | |
2212 | { | |
2213 | /* If there's no instruction mnemonic suffix we try to invent one | |
2214 | based on register operands. */ | |
2215 | if (!i.suffix) | |
2216 | { | |
2217 | /* We take i.suffix from the last register operand specified, | |
2218 | Destination register type is more significant than source | |
2219 | register type. */ | |
2220 | int op; | |
543613e9 | 2221 | |
29b0f896 AM |
2222 | for (op = i.operands; --op >= 0;) |
2223 | if ((i.types[op] & Reg) | |
2224 | && !(i.tm.operand_types[op] & InOutPortReg)) | |
2225 | { | |
2226 | i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX : | |
2227 | (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX : | |
2228 | (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX : | |
2229 | LONG_MNEM_SUFFIX); | |
2230 | break; | |
2231 | } | |
2232 | } | |
2233 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
2234 | { | |
2235 | if (!check_byte_reg ()) | |
2236 | return 0; | |
2237 | } | |
2238 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
2239 | { | |
2240 | if (!check_long_reg ()) | |
2241 | return 0; | |
2242 | } | |
2243 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
2244 | { | |
2245 | if (!check_qword_reg ()) | |
2246 | return 0; | |
2247 | } | |
2248 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
2249 | { | |
2250 | if (!check_word_reg ()) | |
2251 | return 0; | |
2252 | } | |
2253 | else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize)) | |
2254 | /* Do nothing if the instruction is going to ignore the prefix. */ | |
2255 | ; | |
2256 | else | |
2257 | abort (); | |
2258 | } | |
2259 | else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix) | |
2260 | { | |
2261 | i.suffix = stackop_size; | |
543613e9 NC |
2262 | if (i.suffix == QWORD_MNEM_SUFFIX |
2263 | && (i.tm.opcode_modifier & No_qSuf)) | |
2264 | i.suffix = LONG_MNEM_SUFFIX; | |
29b0f896 | 2265 | } |
252b5132 | 2266 | |
29b0f896 AM |
2267 | /* Change the opcode based on the operand size given by i.suffix; |
2268 | We need not change things for byte insns. */ | |
29b0f896 AM |
2269 | if (!i.suffix && (i.tm.opcode_modifier & W)) |
2270 | { | |
2271 | as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction")); | |
2272 | return 0; | |
2273 | } | |
252b5132 | 2274 | |
29b0f896 AM |
2275 | if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX) |
2276 | { | |
2277 | /* It's not a byte, select word/dword operation. */ | |
2278 | if (i.tm.opcode_modifier & W) | |
2279 | { | |
2280 | if (i.tm.opcode_modifier & ShortForm) | |
2281 | i.tm.base_opcode |= 8; | |
2282 | else | |
2283 | i.tm.base_opcode |= 1; | |
2284 | } | |
0f3f3d8b | 2285 | |
29b0f896 AM |
2286 | /* Now select between word & dword operations via the operand |
2287 | size prefix, except for instructions that will ignore this | |
2288 | prefix anyway. */ | |
2289 | if (i.suffix != QWORD_MNEM_SUFFIX | |
9146926a AM |
2290 | && !(i.tm.opcode_modifier & IgnoreSize) |
2291 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) | |
2292 | || (flag_code == CODE_64BIT | |
2293 | && (i.tm.opcode_modifier & JumpByte)))) | |
24eab124 AM |
2294 | { |
2295 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 2296 | |
29b0f896 AM |
2297 | if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */ |
2298 | prefix = ADDR_PREFIX_OPCODE; | |
252b5132 | 2299 | |
29b0f896 AM |
2300 | if (!add_prefix (prefix)) |
2301 | return 0; | |
24eab124 | 2302 | } |
252b5132 | 2303 | |
29b0f896 AM |
2304 | /* Set mode64 for an operand. */ |
2305 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 2306 | && flag_code == CODE_64BIT |
29b0f896 | 2307 | && (i.tm.opcode_modifier & NoRex64) == 0) |
9146926a | 2308 | i.rex |= REX_MODE64; |
3e73aa7c | 2309 | |
29b0f896 AM |
2310 | /* Size floating point instruction. */ |
2311 | if (i.suffix == LONG_MNEM_SUFFIX) | |
543613e9 NC |
2312 | if (i.tm.opcode_modifier & FloatMF) |
2313 | i.tm.base_opcode ^= 4; | |
29b0f896 | 2314 | } |
7ecd2f8b | 2315 | |
29b0f896 AM |
2316 | return 1; |
2317 | } | |
3e73aa7c | 2318 | |
29b0f896 | 2319 | static int |
543613e9 | 2320 | check_byte_reg (void) |
29b0f896 AM |
2321 | { |
2322 | int op; | |
543613e9 | 2323 | |
29b0f896 AM |
2324 | for (op = i.operands; --op >= 0;) |
2325 | { | |
2326 | /* If this is an eight bit register, it's OK. If it's the 16 or | |
2327 | 32 bit version of an eight bit register, we will just use the | |
2328 | low portion, and that's OK too. */ | |
2329 | if (i.types[op] & Reg8) | |
2330 | continue; | |
2331 | ||
2332 | /* movzx and movsx should not generate this warning. */ | |
2333 | if (intel_syntax | |
2334 | && (i.tm.base_opcode == 0xfb7 | |
2335 | || i.tm.base_opcode == 0xfb6 | |
2336 | || i.tm.base_opcode == 0x63 | |
2337 | || i.tm.base_opcode == 0xfbe | |
2338 | || i.tm.base_opcode == 0xfbf)) | |
2339 | continue; | |
2340 | ||
2341 | if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4 | |
2342 | #if 0 | |
2343 | /* Check that the template allows eight bit regs. This | |
2344 | kills insns such as `orb $1,%edx', which maybe should be | |
2345 | allowed. */ | |
2346 | && (i.tm.operand_types[op] & (Reg8 | InOutPortReg)) | |
2347 | #endif | |
2348 | ) | |
2349 | { | |
2350 | /* Prohibit these changes in the 64bit mode, since the | |
2351 | lowering is more complicated. */ | |
2352 | if (flag_code == CODE_64BIT | |
2353 | && (i.tm.operand_types[op] & InOutPortReg) == 0) | |
2354 | { | |
0f3f3d8b | 2355 | as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), |
29b0f896 AM |
2356 | i.op[op].regs->reg_name, |
2357 | i.suffix); | |
2358 | return 0; | |
2359 | } | |
2360 | #if REGISTER_WARNINGS | |
2361 | if (!quiet_warnings | |
2362 | && (i.tm.operand_types[op] & InOutPortReg) == 0) | |
2363 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
2364 | (i.op[op].regs + (i.types[op] & Reg16 | |
2365 | ? REGNAM_AL - REGNAM_AX | |
2366 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
2367 | i.op[op].regs->reg_name, | |
2368 | i.suffix); | |
2369 | #endif | |
2370 | continue; | |
2371 | } | |
2372 | /* Any other register is bad. */ | |
2373 | if (i.types[op] & (Reg | RegMMX | RegXMM | |
2374 | | SReg2 | SReg3 | |
2375 | | Control | Debug | Test | |
2376 | | FloatReg | FloatAcc)) | |
2377 | { | |
2378 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
2379 | i.op[op].regs->reg_name, | |
2380 | i.tm.name, | |
2381 | i.suffix); | |
2382 | return 0; | |
2383 | } | |
2384 | } | |
2385 | return 1; | |
2386 | } | |
2387 | ||
2388 | static int | |
2389 | check_long_reg () | |
2390 | { | |
2391 | int op; | |
2392 | ||
2393 | for (op = i.operands; --op >= 0;) | |
2394 | /* Reject eight bit registers, except where the template requires | |
2395 | them. (eg. movzb) */ | |
2396 | if ((i.types[op] & Reg8) != 0 | |
2397 | && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) | |
2398 | { | |
2399 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
2400 | i.op[op].regs->reg_name, | |
2401 | i.tm.name, | |
2402 | i.suffix); | |
2403 | return 0; | |
2404 | } | |
2405 | /* Warn if the e prefix on a general reg is missing. */ | |
2406 | else if ((!quiet_warnings || flag_code == CODE_64BIT) | |
2407 | && (i.types[op] & Reg16) != 0 | |
2408 | && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) | |
2409 | { | |
2410 | /* Prohibit these changes in the 64bit mode, since the | |
2411 | lowering is more complicated. */ | |
2412 | if (flag_code == CODE_64BIT) | |
252b5132 | 2413 | { |
0f3f3d8b | 2414 | as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), |
29b0f896 AM |
2415 | i.op[op].regs->reg_name, |
2416 | i.suffix); | |
2417 | return 0; | |
252b5132 | 2418 | } |
29b0f896 AM |
2419 | #if REGISTER_WARNINGS |
2420 | else | |
2421 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
2422 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, | |
2423 | i.op[op].regs->reg_name, | |
2424 | i.suffix); | |
2425 | #endif | |
252b5132 | 2426 | } |
29b0f896 AM |
2427 | /* Warn if the r prefix on a general reg is missing. */ |
2428 | else if ((i.types[op] & Reg64) != 0 | |
2429 | && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) | |
252b5132 | 2430 | { |
0f3f3d8b | 2431 | as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), |
29b0f896 AM |
2432 | i.op[op].regs->reg_name, |
2433 | i.suffix); | |
2434 | return 0; | |
2435 | } | |
2436 | return 1; | |
2437 | } | |
252b5132 | 2438 | |
29b0f896 AM |
2439 | static int |
2440 | check_qword_reg () | |
2441 | { | |
2442 | int op; | |
252b5132 | 2443 | |
29b0f896 AM |
2444 | for (op = i.operands; --op >= 0; ) |
2445 | /* Reject eight bit registers, except where the template requires | |
2446 | them. (eg. movzb) */ | |
2447 | if ((i.types[op] & Reg8) != 0 | |
2448 | && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) | |
2449 | { | |
2450 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
2451 | i.op[op].regs->reg_name, | |
2452 | i.tm.name, | |
2453 | i.suffix); | |
2454 | return 0; | |
2455 | } | |
2456 | /* Warn if the e prefix on a general reg is missing. */ | |
2457 | else if (((i.types[op] & Reg16) != 0 | |
2458 | || (i.types[op] & Reg32) != 0) | |
2459 | && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) | |
2460 | { | |
2461 | /* Prohibit these changes in the 64bit mode, since the | |
2462 | lowering is more complicated. */ | |
0f3f3d8b | 2463 | as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), |
29b0f896 AM |
2464 | i.op[op].regs->reg_name, |
2465 | i.suffix); | |
2466 | return 0; | |
252b5132 | 2467 | } |
29b0f896 AM |
2468 | return 1; |
2469 | } | |
252b5132 | 2470 | |
29b0f896 AM |
2471 | static int |
2472 | check_word_reg () | |
2473 | { | |
2474 | int op; | |
2475 | for (op = i.operands; --op >= 0;) | |
2476 | /* Reject eight bit registers, except where the template requires | |
2477 | them. (eg. movzb) */ | |
2478 | if ((i.types[op] & Reg8) != 0 | |
2479 | && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) | |
2480 | { | |
2481 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
2482 | i.op[op].regs->reg_name, | |
2483 | i.tm.name, | |
2484 | i.suffix); | |
2485 | return 0; | |
2486 | } | |
2487 | /* Warn if the e prefix on a general reg is present. */ | |
2488 | else if ((!quiet_warnings || flag_code == CODE_64BIT) | |
2489 | && (i.types[op] & Reg32) != 0 | |
2490 | && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0) | |
252b5132 | 2491 | { |
29b0f896 AM |
2492 | /* Prohibit these changes in the 64bit mode, since the |
2493 | lowering is more complicated. */ | |
2494 | if (flag_code == CODE_64BIT) | |
252b5132 | 2495 | { |
0f3f3d8b | 2496 | as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), |
29b0f896 AM |
2497 | i.op[op].regs->reg_name, |
2498 | i.suffix); | |
2499 | return 0; | |
252b5132 | 2500 | } |
29b0f896 AM |
2501 | else |
2502 | #if REGISTER_WARNINGS | |
2503 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
2504 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, | |
2505 | i.op[op].regs->reg_name, | |
2506 | i.suffix); | |
2507 | #endif | |
2508 | } | |
2509 | return 1; | |
2510 | } | |
252b5132 | 2511 | |
29b0f896 AM |
2512 | static int |
2513 | finalize_imm () | |
2514 | { | |
2515 | unsigned int overlap0, overlap1, overlap2; | |
2516 | ||
2517 | overlap0 = i.types[0] & i.tm.operand_types[0]; | |
20f0a1fc | 2518 | if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64)) |
29b0f896 AM |
2519 | && overlap0 != Imm8 && overlap0 != Imm8S |
2520 | && overlap0 != Imm16 && overlap0 != Imm32S | |
2521 | && overlap0 != Imm32 && overlap0 != Imm64) | |
2522 | { | |
2523 | if (i.suffix) | |
2524 | { | |
2525 | overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX | |
2526 | ? Imm8 | Imm8S | |
2527 | : (i.suffix == WORD_MNEM_SUFFIX | |
2528 | ? Imm16 | |
2529 | : (i.suffix == QWORD_MNEM_SUFFIX | |
2530 | ? Imm64 | Imm32S | |
2531 | : Imm32))); | |
2532 | } | |
2533 | else if (overlap0 == (Imm16 | Imm32S | Imm32) | |
2534 | || overlap0 == (Imm16 | Imm32) | |
2535 | || overlap0 == (Imm16 | Imm32S)) | |
2536 | { | |
2537 | overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0) | |
2538 | ? Imm16 : Imm32S); | |
2539 | } | |
2540 | if (overlap0 != Imm8 && overlap0 != Imm8S | |
2541 | && overlap0 != Imm16 && overlap0 != Imm32S | |
2542 | && overlap0 != Imm32 && overlap0 != Imm64) | |
2543 | { | |
2544 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); | |
2545 | return 0; | |
2546 | } | |
2547 | } | |
2548 | i.types[0] = overlap0; | |
2549 | ||
2550 | overlap1 = i.types[1] & i.tm.operand_types[1]; | |
2551 | if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32)) | |
2552 | && overlap1 != Imm8 && overlap1 != Imm8S | |
2553 | && overlap1 != Imm16 && overlap1 != Imm32S | |
2554 | && overlap1 != Imm32 && overlap1 != Imm64) | |
2555 | { | |
2556 | if (i.suffix) | |
2557 | { | |
2558 | overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX | |
2559 | ? Imm8 | Imm8S | |
2560 | : (i.suffix == WORD_MNEM_SUFFIX | |
2561 | ? Imm16 | |
2562 | : (i.suffix == QWORD_MNEM_SUFFIX | |
2563 | ? Imm64 | Imm32S | |
2564 | : Imm32))); | |
2565 | } | |
2566 | else if (overlap1 == (Imm16 | Imm32 | Imm32S) | |
2567 | || overlap1 == (Imm16 | Imm32) | |
2568 | || overlap1 == (Imm16 | Imm32S)) | |
2569 | { | |
2570 | overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0) | |
2571 | ? Imm16 : Imm32S); | |
2572 | } | |
2573 | if (overlap1 != Imm8 && overlap1 != Imm8S | |
2574 | && overlap1 != Imm16 && overlap1 != Imm32S | |
2575 | && overlap1 != Imm32 && overlap1 != Imm64) | |
2576 | { | |
2577 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix); | |
2578 | return 0; | |
2579 | } | |
2580 | } | |
2581 | i.types[1] = overlap1; | |
2582 | ||
2583 | overlap2 = i.types[2] & i.tm.operand_types[2]; | |
2584 | assert ((overlap2 & Imm) == 0); | |
2585 | i.types[2] = overlap2; | |
2586 | ||
2587 | return 1; | |
2588 | } | |
2589 | ||
2590 | static int | |
2591 | process_operands () | |
2592 | { | |
2593 | /* Default segment register this instruction will use for memory | |
2594 | accesses. 0 means unknown. This is only for optimizing out | |
2595 | unnecessary segment overrides. */ | |
2596 | const seg_entry *default_seg = 0; | |
2597 | ||
2598 | /* The imul $imm, %reg instruction is converted into | |
2599 | imul $imm, %reg, %reg, and the clr %reg instruction | |
2600 | is converted into xor %reg, %reg. */ | |
2601 | if (i.tm.opcode_modifier & regKludge) | |
2602 | { | |
2603 | unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1; | |
2604 | /* Pretend we saw the extra register operand. */ | |
2605 | assert (i.op[first_reg_op + 1].regs == 0); | |
2606 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; | |
2607 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
2608 | i.reg_operands = 2; | |
2609 | } | |
2610 | ||
2611 | if (i.tm.opcode_modifier & ShortForm) | |
2612 | { | |
2613 | /* The register or float register operand is in operand 0 or 1. */ | |
2614 | unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; | |
2615 | /* Register goes in low 3 bits of opcode. */ | |
2616 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
2617 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
2618 | i.rex |= REX_EXTZ; | |
2619 | if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) | |
2620 | { | |
2621 | /* Warn about some common errors, but press on regardless. | |
2622 | The first case can be generated by gcc (<= 2.8.1). */ | |
2623 | if (i.operands == 2) | |
2624 | { | |
2625 | /* Reversed arguments on faddp, fsubp, etc. */ | |
2626 | as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name, | |
2627 | i.op[1].regs->reg_name, | |
2628 | i.op[0].regs->reg_name); | |
2629 | } | |
2630 | else | |
2631 | { | |
2632 | /* Extraneous `l' suffix on fp insn. */ | |
2633 | as_warn (_("translating to `%s %%%s'"), i.tm.name, | |
2634 | i.op[0].regs->reg_name); | |
2635 | } | |
2636 | } | |
2637 | } | |
2638 | else if (i.tm.opcode_modifier & Modrm) | |
2639 | { | |
2640 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
2641 | must be put into the modrm byte). Now, we make the modrm and |
2642 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
2643 | |
2644 | default_seg = build_modrm_byte (); | |
2645 | } | |
2646 | else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm)) | |
2647 | { | |
2648 | if (i.tm.base_opcode == POP_SEG_SHORT | |
2649 | && i.op[0].regs->reg_num == 1) | |
2650 | { | |
2651 | as_bad (_("you can't `pop %%cs'")); | |
2652 | return 0; | |
2653 | } | |
2654 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); | |
2655 | if ((i.op[0].regs->reg_flags & RegRex) != 0) | |
2656 | i.rex |= REX_EXTZ; | |
2657 | } | |
2658 | else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32) | |
2659 | { | |
2660 | default_seg = &ds; | |
2661 | } | |
2662 | else if ((i.tm.opcode_modifier & IsString) != 0) | |
2663 | { | |
2664 | /* For the string instructions that allow a segment override | |
2665 | on one of their operands, the default segment is ds. */ | |
2666 | default_seg = &ds; | |
2667 | } | |
2668 | ||
52271982 AM |
2669 | if (i.tm.base_opcode == 0x8d /* lea */ && i.seg[0] && !quiet_warnings) |
2670 | as_warn (_("segment override on `lea' is ineffectual")); | |
2671 | ||
2672 | /* If a segment was explicitly specified, and the specified segment | |
2673 | is not the default, use an opcode prefix to select it. If we | |
2674 | never figured out what the default segment is, then default_seg | |
2675 | will be zero at this point, and the specified segment prefix will | |
2676 | always be used. */ | |
29b0f896 AM |
2677 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
2678 | { | |
2679 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
2680 | return 0; | |
2681 | } | |
2682 | return 1; | |
2683 | } | |
2684 | ||
2685 | static const seg_entry * | |
2686 | build_modrm_byte () | |
2687 | { | |
2688 | const seg_entry *default_seg = 0; | |
2689 | ||
2690 | /* i.reg_operands MUST be the number of real register operands; | |
2691 | implicit registers do not count. */ | |
2692 | if (i.reg_operands == 2) | |
2693 | { | |
2694 | unsigned int source, dest; | |
2695 | source = ((i.types[0] | |
2696 | & (Reg | RegMMX | RegXMM | |
2697 | | SReg2 | SReg3 | |
2698 | | Control | Debug | Test)) | |
2699 | ? 0 : 1); | |
2700 | dest = source + 1; | |
2701 | ||
2702 | i.rm.mode = 3; | |
2703 | /* One of the register operands will be encoded in the i.tm.reg | |
2704 | field, the other in the combined i.tm.mode and i.tm.regmem | |
2705 | fields. If no form of this instruction supports a memory | |
2706 | destination operand, then we assume the source operand may | |
2707 | sometimes be a memory operand and so we need to store the | |
2708 | destination in the i.rm.reg field. */ | |
2709 | if ((i.tm.operand_types[dest] & AnyMem) == 0) | |
2710 | { | |
2711 | i.rm.reg = i.op[dest].regs->reg_num; | |
2712 | i.rm.regmem = i.op[source].regs->reg_num; | |
2713 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
2714 | i.rex |= REX_EXTX; | |
2715 | if ((i.op[source].regs->reg_flags & RegRex) != 0) | |
2716 | i.rex |= REX_EXTZ; | |
2717 | } | |
2718 | else | |
2719 | { | |
2720 | i.rm.reg = i.op[source].regs->reg_num; | |
2721 | i.rm.regmem = i.op[dest].regs->reg_num; | |
2722 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
2723 | i.rex |= REX_EXTZ; | |
2724 | if ((i.op[source].regs->reg_flags & RegRex) != 0) | |
2725 | i.rex |= REX_EXTX; | |
2726 | } | |
2727 | } | |
2728 | else | |
2729 | { /* If it's not 2 reg operands... */ | |
2730 | if (i.mem_operands) | |
2731 | { | |
2732 | unsigned int fake_zero_displacement = 0; | |
2733 | unsigned int op = ((i.types[0] & AnyMem) | |
2734 | ? 0 | |
2735 | : (i.types[1] & AnyMem) ? 1 : 2); | |
2736 | ||
2737 | default_seg = &ds; | |
2738 | ||
2739 | if (i.base_reg == 0) | |
2740 | { | |
2741 | i.rm.mode = 0; | |
2742 | if (!i.disp_operands) | |
2743 | fake_zero_displacement = 1; | |
2744 | if (i.index_reg == 0) | |
2745 | { | |
2746 | /* Operand is just <disp> */ | |
20f0a1fc | 2747 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
2748 | { |
2749 | /* 64bit mode overwrites the 32bit absolute | |
2750 | addressing by RIP relative addressing and | |
2751 | absolute addressing is encoded by one of the | |
2752 | redundant SIB forms. */ | |
2753 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2754 | i.sib.base = NO_BASE_REGISTER; | |
2755 | i.sib.index = NO_INDEX_REGISTER; | |
20f0a1fc NC |
2756 | i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32); |
2757 | } | |
2758 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) | |
2759 | { | |
2760 | i.rm.regmem = NO_BASE_REGISTER_16; | |
2761 | i.types[op] = Disp16; | |
2762 | } | |
2763 | else | |
2764 | { | |
2765 | i.rm.regmem = NO_BASE_REGISTER; | |
2766 | i.types[op] = Disp32; | |
29b0f896 AM |
2767 | } |
2768 | } | |
2769 | else /* !i.base_reg && i.index_reg */ | |
2770 | { | |
2771 | i.sib.index = i.index_reg->reg_num; | |
2772 | i.sib.base = NO_BASE_REGISTER; | |
2773 | i.sib.scale = i.log2_scale_factor; | |
2774 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2775 | i.types[op] &= ~Disp; | |
2776 | if (flag_code != CODE_64BIT) | |
2777 | i.types[op] |= Disp32; /* Must be 32 bit */ | |
2778 | else | |
2779 | i.types[op] |= Disp32S; | |
2780 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
2781 | i.rex |= REX_EXTY; | |
2782 | } | |
2783 | } | |
2784 | /* RIP addressing for 64bit mode. */ | |
2785 | else if (i.base_reg->reg_type == BaseIndex) | |
2786 | { | |
2787 | i.rm.regmem = NO_BASE_REGISTER; | |
20f0a1fc | 2788 | i.types[op] &= ~ Disp; |
29b0f896 AM |
2789 | i.types[op] |= Disp32S; |
2790 | i.flags[op] = Operand_PCrel; | |
20f0a1fc NC |
2791 | if (! i.disp_operands) |
2792 | fake_zero_displacement = 1; | |
29b0f896 AM |
2793 | } |
2794 | else if (i.base_reg->reg_type & Reg16) | |
2795 | { | |
2796 | switch (i.base_reg->reg_num) | |
2797 | { | |
2798 | case 3: /* (%bx) */ | |
2799 | if (i.index_reg == 0) | |
2800 | i.rm.regmem = 7; | |
2801 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
2802 | i.rm.regmem = i.index_reg->reg_num - 6; | |
2803 | break; | |
2804 | case 5: /* (%bp) */ | |
2805 | default_seg = &ss; | |
2806 | if (i.index_reg == 0) | |
2807 | { | |
2808 | i.rm.regmem = 6; | |
2809 | if ((i.types[op] & Disp) == 0) | |
2810 | { | |
2811 | /* fake (%bp) into 0(%bp) */ | |
2812 | i.types[op] |= Disp8; | |
252b5132 | 2813 | fake_zero_displacement = 1; |
29b0f896 AM |
2814 | } |
2815 | } | |
2816 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
2817 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
2818 | break; | |
2819 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
2820 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
2821 | } | |
2822 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
2823 | } | |
2824 | else /* i.base_reg and 32/64 bit mode */ | |
2825 | { | |
2826 | if (flag_code == CODE_64BIT | |
2827 | && (i.types[op] & Disp)) | |
20f0a1fc NC |
2828 | i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32); |
2829 | ||
29b0f896 AM |
2830 | i.rm.regmem = i.base_reg->reg_num; |
2831 | if ((i.base_reg->reg_flags & RegRex) != 0) | |
2832 | i.rex |= REX_EXTZ; | |
2833 | i.sib.base = i.base_reg->reg_num; | |
2834 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
2835 | complications. */ | |
2836 | if ((i.base_reg->reg_num & 7) == EBP_REG_NUM) | |
2837 | { | |
2838 | default_seg = &ss; | |
2839 | if (i.disp_operands == 0) | |
2840 | { | |
2841 | fake_zero_displacement = 1; | |
2842 | i.types[op] |= Disp8; | |
2843 | } | |
2844 | } | |
2845 | else if (i.base_reg->reg_num == ESP_REG_NUM) | |
2846 | { | |
2847 | default_seg = &ss; | |
2848 | } | |
2849 | i.sib.scale = i.log2_scale_factor; | |
2850 | if (i.index_reg == 0) | |
2851 | { | |
2852 | /* <disp>(%esp) becomes two byte modrm with no index | |
2853 | register. We've already stored the code for esp | |
2854 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
2855 | Any base register besides %esp will not use the | |
2856 | extra modrm byte. */ | |
2857 | i.sib.index = NO_INDEX_REGISTER; | |
2858 | #if !SCALE1_WHEN_NO_INDEX | |
2859 | /* Another case where we force the second modrm byte. */ | |
2860 | if (i.log2_scale_factor) | |
2861 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
252b5132 | 2862 | #endif |
29b0f896 AM |
2863 | } |
2864 | else | |
2865 | { | |
2866 | i.sib.index = i.index_reg->reg_num; | |
2867 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2868 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
2869 | i.rex |= REX_EXTY; | |
2870 | } | |
2871 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
2872 | } | |
252b5132 | 2873 | |
29b0f896 AM |
2874 | if (fake_zero_displacement) |
2875 | { | |
2876 | /* Fakes a zero displacement assuming that i.types[op] | |
2877 | holds the correct displacement size. */ | |
2878 | expressionS *exp; | |
2879 | ||
2880 | assert (i.op[op].disps == 0); | |
2881 | exp = &disp_expressions[i.disp_operands++]; | |
2882 | i.op[op].disps = exp; | |
2883 | exp->X_op = O_constant; | |
2884 | exp->X_add_number = 0; | |
2885 | exp->X_add_symbol = (symbolS *) 0; | |
2886 | exp->X_op_symbol = (symbolS *) 0; | |
2887 | } | |
2888 | } | |
252b5132 | 2889 | |
29b0f896 AM |
2890 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
2891 | (if any) based on i.tm.extension_opcode. Again, we must be | |
2892 | careful to make sure that segment/control/debug/test/MMX | |
2893 | registers are coded into the i.rm.reg field. */ | |
2894 | if (i.reg_operands) | |
2895 | { | |
2896 | unsigned int op = | |
2897 | ((i.types[0] | |
2898 | & (Reg | RegMMX | RegXMM | |
2899 | | SReg2 | SReg3 | |
2900 | | Control | Debug | Test)) | |
2901 | ? 0 | |
2902 | : ((i.types[1] | |
2903 | & (Reg | RegMMX | RegXMM | |
2904 | | SReg2 | SReg3 | |
2905 | | Control | Debug | Test)) | |
2906 | ? 1 | |
2907 | : 2)); | |
2908 | /* If there is an extension opcode to put here, the register | |
2909 | number must be put into the regmem field. */ | |
2910 | if (i.tm.extension_opcode != None) | |
2911 | { | |
2912 | i.rm.regmem = i.op[op].regs->reg_num; | |
2913 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
2914 | i.rex |= REX_EXTZ; | |
2915 | } | |
2916 | else | |
2917 | { | |
2918 | i.rm.reg = i.op[op].regs->reg_num; | |
2919 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
2920 | i.rex |= REX_EXTX; | |
2921 | } | |
252b5132 | 2922 | |
29b0f896 AM |
2923 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
2924 | must set it to 3 to indicate this is a register operand | |
2925 | in the regmem field. */ | |
2926 | if (!i.mem_operands) | |
2927 | i.rm.mode = 3; | |
2928 | } | |
252b5132 | 2929 | |
29b0f896 AM |
2930 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
2931 | if (i.tm.extension_opcode != None) | |
2932 | i.rm.reg = i.tm.extension_opcode; | |
2933 | } | |
2934 | return default_seg; | |
2935 | } | |
252b5132 | 2936 | |
29b0f896 AM |
2937 | static void |
2938 | output_branch () | |
2939 | { | |
2940 | char *p; | |
2941 | int code16; | |
2942 | int prefix; | |
2943 | relax_substateT subtype; | |
2944 | symbolS *sym; | |
2945 | offsetT off; | |
2946 | ||
2947 | code16 = 0; | |
2948 | if (flag_code == CODE_16BIT) | |
2949 | code16 = CODE16; | |
2950 | ||
2951 | prefix = 0; | |
2952 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 2953 | { |
29b0f896 AM |
2954 | prefix = 1; |
2955 | i.prefixes -= 1; | |
2956 | code16 ^= CODE16; | |
252b5132 | 2957 | } |
29b0f896 AM |
2958 | /* Pentium4 branch hints. */ |
2959 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
2960 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 2961 | { |
29b0f896 AM |
2962 | prefix++; |
2963 | i.prefixes--; | |
2964 | } | |
2965 | if (i.prefix[REX_PREFIX] != 0) | |
2966 | { | |
2967 | prefix++; | |
2968 | i.prefixes--; | |
2f66722d AM |
2969 | } |
2970 | ||
29b0f896 AM |
2971 | if (i.prefixes != 0 && !intel_syntax) |
2972 | as_warn (_("skipping prefixes on this instruction")); | |
2973 | ||
2974 | /* It's always a symbol; End frag & setup for relax. | |
2975 | Make sure there is enough room in this frag for the largest | |
2976 | instruction we may generate in md_convert_frag. This is 2 | |
2977 | bytes for the opcode and room for the prefix and largest | |
2978 | displacement. */ | |
2979 | frag_grow (prefix + 2 + 4); | |
2980 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
2981 | p = frag_more (prefix + 1); | |
2982 | if (i.prefix[DATA_PREFIX] != 0) | |
2983 | *p++ = DATA_PREFIX_OPCODE; | |
2984 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
2985 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
2986 | *p++ = i.prefix[SEG_PREFIX]; | |
2987 | if (i.prefix[REX_PREFIX] != 0) | |
2988 | *p++ = i.prefix[REX_PREFIX]; | |
2989 | *p = i.tm.base_opcode; | |
2990 | ||
2991 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
2992 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL); | |
2993 | else if ((cpu_arch_flags & Cpu386) != 0) | |
2994 | subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL); | |
2995 | else | |
2996 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL); | |
2997 | subtype |= code16; | |
3e73aa7c | 2998 | |
29b0f896 AM |
2999 | sym = i.op[0].disps->X_add_symbol; |
3000 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 3001 | |
29b0f896 AM |
3002 | if (i.op[0].disps->X_op != O_constant |
3003 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 3004 | { |
29b0f896 AM |
3005 | /* Handle complex expressions. */ |
3006 | sym = make_expr_symbol (i.op[0].disps); | |
3007 | off = 0; | |
3008 | } | |
3e73aa7c | 3009 | |
29b0f896 AM |
3010 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
3011 | Pass reloc in fr_var. */ | |
3012 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); | |
3013 | } | |
3e73aa7c | 3014 | |
29b0f896 AM |
3015 | static void |
3016 | output_jump () | |
3017 | { | |
3018 | char *p; | |
3019 | int size; | |
3e02c1cc | 3020 | fixS *fixP; |
29b0f896 AM |
3021 | |
3022 | if (i.tm.opcode_modifier & JumpByte) | |
3023 | { | |
3024 | /* This is a loop or jecxz type instruction. */ | |
3025 | size = 1; | |
3026 | if (i.prefix[ADDR_PREFIX] != 0) | |
3027 | { | |
3028 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
3029 | i.prefixes -= 1; | |
3030 | } | |
3031 | /* Pentium4 branch hints. */ | |
3032 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
3033 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
3034 | { | |
3035 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
3036 | i.prefixes--; | |
3e73aa7c JH |
3037 | } |
3038 | } | |
29b0f896 AM |
3039 | else |
3040 | { | |
3041 | int code16; | |
3e73aa7c | 3042 | |
29b0f896 AM |
3043 | code16 = 0; |
3044 | if (flag_code == CODE_16BIT) | |
3045 | code16 = CODE16; | |
3e73aa7c | 3046 | |
29b0f896 AM |
3047 | if (i.prefix[DATA_PREFIX] != 0) |
3048 | { | |
3049 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
3050 | i.prefixes -= 1; | |
3051 | code16 ^= CODE16; | |
3052 | } | |
252b5132 | 3053 | |
29b0f896 AM |
3054 | size = 4; |
3055 | if (code16) | |
3056 | size = 2; | |
3057 | } | |
9fcc94b6 | 3058 | |
29b0f896 AM |
3059 | if (i.prefix[REX_PREFIX] != 0) |
3060 | { | |
3061 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
3062 | i.prefixes -= 1; | |
3063 | } | |
252b5132 | 3064 | |
29b0f896 AM |
3065 | if (i.prefixes != 0 && !intel_syntax) |
3066 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 3067 | |
29b0f896 AM |
3068 | p = frag_more (1 + size); |
3069 | *p++ = i.tm.base_opcode; | |
e0890092 | 3070 | |
3e02c1cc AM |
3071 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
3072 | i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); | |
3073 | ||
3074 | /* All jumps handled here are signed, but don't use a signed limit | |
3075 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
3076 | 4G and 64k respectively. */ | |
3077 | if (size == 1) | |
3078 | fixP->fx_signed = 1; | |
29b0f896 | 3079 | } |
e0890092 | 3080 | |
29b0f896 AM |
3081 | static void |
3082 | output_interseg_jump () | |
3083 | { | |
3084 | char *p; | |
3085 | int size; | |
3086 | int prefix; | |
3087 | int code16; | |
252b5132 | 3088 | |
29b0f896 AM |
3089 | code16 = 0; |
3090 | if (flag_code == CODE_16BIT) | |
3091 | code16 = CODE16; | |
a217f122 | 3092 | |
29b0f896 AM |
3093 | prefix = 0; |
3094 | if (i.prefix[DATA_PREFIX] != 0) | |
3095 | { | |
3096 | prefix = 1; | |
3097 | i.prefixes -= 1; | |
3098 | code16 ^= CODE16; | |
3099 | } | |
3100 | if (i.prefix[REX_PREFIX] != 0) | |
3101 | { | |
3102 | prefix++; | |
3103 | i.prefixes -= 1; | |
3104 | } | |
252b5132 | 3105 | |
29b0f896 AM |
3106 | size = 4; |
3107 | if (code16) | |
3108 | size = 2; | |
252b5132 | 3109 | |
29b0f896 AM |
3110 | if (i.prefixes != 0 && !intel_syntax) |
3111 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 3112 | |
29b0f896 AM |
3113 | /* 1 opcode; 2 segment; offset */ |
3114 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 3115 | |
29b0f896 AM |
3116 | if (i.prefix[DATA_PREFIX] != 0) |
3117 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 3118 | |
29b0f896 AM |
3119 | if (i.prefix[REX_PREFIX] != 0) |
3120 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 3121 | |
29b0f896 AM |
3122 | *p++ = i.tm.base_opcode; |
3123 | if (i.op[1].imms->X_op == O_constant) | |
3124 | { | |
3125 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 3126 | |
29b0f896 AM |
3127 | if (size == 2 |
3128 | && !fits_in_unsigned_word (n) | |
3129 | && !fits_in_signed_word (n)) | |
3130 | { | |
3131 | as_bad (_("16-bit jump out of range")); | |
3132 | return; | |
3133 | } | |
3134 | md_number_to_chars (p, n, size); | |
3135 | } | |
3136 | else | |
3137 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
3138 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); | |
3139 | if (i.op[0].imms->X_op != O_constant) | |
3140 | as_bad (_("can't handle non absolute segment in `%s'"), | |
3141 | i.tm.name); | |
3142 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
3143 | } | |
a217f122 | 3144 | |
29b0f896 AM |
3145 | static void |
3146 | output_insn () | |
3147 | { | |
2bbd9c25 JJ |
3148 | fragS *insn_start_frag; |
3149 | offsetT insn_start_off; | |
3150 | ||
29b0f896 AM |
3151 | /* Tie dwarf2 debug info to the address at the start of the insn. |
3152 | We can't do this after the insn has been output as the current | |
3153 | frag may have been closed off. eg. by frag_var. */ | |
3154 | dwarf2_emit_insn (0); | |
3155 | ||
2bbd9c25 JJ |
3156 | insn_start_frag = frag_now; |
3157 | insn_start_off = frag_now_fix (); | |
3158 | ||
29b0f896 AM |
3159 | /* Output jumps. */ |
3160 | if (i.tm.opcode_modifier & Jump) | |
3161 | output_branch (); | |
3162 | else if (i.tm.opcode_modifier & (JumpByte | JumpDword)) | |
3163 | output_jump (); | |
3164 | else if (i.tm.opcode_modifier & JumpInterSegment) | |
3165 | output_interseg_jump (); | |
3166 | else | |
3167 | { | |
3168 | /* Output normal instructions here. */ | |
3169 | char *p; | |
3170 | unsigned char *q; | |
252b5132 | 3171 | |
0f10071e ML |
3172 | /* All opcodes on i386 have either 1 or 2 bytes, PadLock instructions |
3173 | have 3 bytes. We may use one more higher byte to specify a prefix | |
3174 | the instruction requires. */ | |
3175 | if ((i.tm.cpu_flags & CpuPadLock) != 0 | |
3176 | && (i.tm.base_opcode & 0xff000000) != 0) | |
3177 | { | |
3178 | unsigned int prefix; | |
3179 | prefix = (i.tm.base_opcode >> 24) & 0xff; | |
3180 | ||
3181 | if (prefix != REPE_PREFIX_OPCODE | |
3182 | || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE) | |
3183 | add_prefix (prefix); | |
3184 | } | |
3185 | else | |
3186 | if ((i.tm.cpu_flags & CpuPadLock) == 0 | |
3187 | && (i.tm.base_opcode & 0xff0000) != 0) | |
3188 | add_prefix ((i.tm.base_opcode >> 16) & 0xff); | |
252b5132 | 3189 | |
29b0f896 AM |
3190 | /* The prefix bytes. */ |
3191 | for (q = i.prefix; | |
3192 | q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]); | |
3193 | q++) | |
3194 | { | |
3195 | if (*q) | |
3196 | { | |
3197 | p = frag_more (1); | |
3198 | md_number_to_chars (p, (valueT) *q, 1); | |
3199 | } | |
3200 | } | |
252b5132 | 3201 | |
29b0f896 AM |
3202 | /* Now the opcode; be careful about word order here! */ |
3203 | if (fits_in_unsigned_byte (i.tm.base_opcode)) | |
3204 | { | |
3205 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
3206 | } | |
3207 | else | |
3208 | { | |
0f10071e ML |
3209 | if ((i.tm.cpu_flags & CpuPadLock) != 0) |
3210 | { | |
3211 | p = frag_more (3); | |
3212 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
3213 | } | |
3214 | else | |
3215 | p = frag_more (2); | |
3216 | ||
29b0f896 AM |
3217 | /* Put out high byte first: can't use md_number_to_chars! */ |
3218 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
3219 | *p = i.tm.base_opcode & 0xff; | |
3220 | } | |
3e73aa7c | 3221 | |
29b0f896 AM |
3222 | /* Now the modrm byte and sib byte (if present). */ |
3223 | if (i.tm.opcode_modifier & Modrm) | |
3224 | { | |
3225 | p = frag_more (1); | |
3226 | md_number_to_chars (p, | |
3227 | (valueT) (i.rm.regmem << 0 | |
3228 | | i.rm.reg << 3 | |
3229 | | i.rm.mode << 6), | |
3230 | 1); | |
3231 | /* If i.rm.regmem == ESP (4) | |
3232 | && i.rm.mode != (Register mode) | |
3233 | && not 16 bit | |
3234 | ==> need second modrm byte. */ | |
3235 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
3236 | && i.rm.mode != 3 | |
3237 | && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0)) | |
3238 | { | |
3239 | p = frag_more (1); | |
3240 | md_number_to_chars (p, | |
3241 | (valueT) (i.sib.base << 0 | |
3242 | | i.sib.index << 3 | |
3243 | | i.sib.scale << 6), | |
3244 | 1); | |
3245 | } | |
3246 | } | |
3e73aa7c | 3247 | |
29b0f896 | 3248 | if (i.disp_operands) |
2bbd9c25 | 3249 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 3250 | |
29b0f896 | 3251 | if (i.imm_operands) |
2bbd9c25 | 3252 | output_imm (insn_start_frag, insn_start_off); |
29b0f896 | 3253 | } |
252b5132 | 3254 | |
29b0f896 AM |
3255 | #ifdef DEBUG386 |
3256 | if (flag_debug) | |
3257 | { | |
3258 | pi (line, &i); | |
3259 | } | |
3260 | #endif /* DEBUG386 */ | |
3261 | } | |
252b5132 | 3262 | |
29b0f896 | 3263 | static void |
2bbd9c25 JJ |
3264 | output_disp (insn_start_frag, insn_start_off) |
3265 | fragS *insn_start_frag; | |
3266 | offsetT insn_start_off; | |
29b0f896 AM |
3267 | { |
3268 | char *p; | |
3269 | unsigned int n; | |
252b5132 | 3270 | |
29b0f896 AM |
3271 | for (n = 0; n < i.operands; n++) |
3272 | { | |
3273 | if (i.types[n] & Disp) | |
3274 | { | |
3275 | if (i.op[n].disps->X_op == O_constant) | |
3276 | { | |
3277 | int size; | |
3278 | offsetT val; | |
252b5132 | 3279 | |
29b0f896 AM |
3280 | size = 4; |
3281 | if (i.types[n] & (Disp8 | Disp16 | Disp64)) | |
3282 | { | |
3283 | size = 2; | |
3284 | if (i.types[n] & Disp8) | |
3285 | size = 1; | |
3286 | if (i.types[n] & Disp64) | |
3287 | size = 8; | |
3288 | } | |
3289 | val = offset_in_range (i.op[n].disps->X_add_number, | |
3290 | size); | |
3291 | p = frag_more (size); | |
3292 | md_number_to_chars (p, val, size); | |
3293 | } | |
3294 | else | |
3295 | { | |
f86103b7 | 3296 | enum bfd_reloc_code_real reloc_type; |
29b0f896 AM |
3297 | int size = 4; |
3298 | int sign = 0; | |
3299 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; | |
3300 | ||
3301 | /* The PC relative address is computed relative | |
3302 | to the instruction boundary, so in case immediate | |
3303 | fields follows, we need to adjust the value. */ | |
3304 | if (pcrel && i.imm_operands) | |
3305 | { | |
3306 | int imm_size = 4; | |
3307 | unsigned int n1; | |
252b5132 | 3308 | |
29b0f896 AM |
3309 | for (n1 = 0; n1 < i.operands; n1++) |
3310 | if (i.types[n1] & Imm) | |
252b5132 | 3311 | { |
29b0f896 | 3312 | if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64)) |
252b5132 | 3313 | { |
29b0f896 AM |
3314 | imm_size = 2; |
3315 | if (i.types[n1] & (Imm8 | Imm8S)) | |
3316 | imm_size = 1; | |
3317 | if (i.types[n1] & Imm64) | |
3318 | imm_size = 8; | |
252b5132 | 3319 | } |
29b0f896 | 3320 | break; |
252b5132 | 3321 | } |
29b0f896 AM |
3322 | /* We should find the immediate. */ |
3323 | if (n1 == i.operands) | |
3324 | abort (); | |
3325 | i.op[n].disps->X_add_number -= imm_size; | |
3326 | } | |
520dc8e8 | 3327 | |
29b0f896 AM |
3328 | if (i.types[n] & Disp32S) |
3329 | sign = 1; | |
3e73aa7c | 3330 | |
29b0f896 AM |
3331 | if (i.types[n] & (Disp16 | Disp64)) |
3332 | { | |
3333 | size = 2; | |
3334 | if (i.types[n] & Disp64) | |
3335 | size = 8; | |
3336 | } | |
520dc8e8 | 3337 | |
29b0f896 | 3338 | p = frag_more (size); |
2bbd9c25 | 3339 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
2bbd9c25 JJ |
3340 | if (reloc_type == BFD_RELOC_32 |
3341 | && GOT_symbol | |
3342 | && GOT_symbol == i.op[n].disps->X_add_symbol | |
3343 | && (i.op[n].disps->X_op == O_symbol | |
3344 | || (i.op[n].disps->X_op == O_add | |
3345 | && ((symbol_get_value_expression | |
3346 | (i.op[n].disps->X_op_symbol)->X_op) | |
3347 | == O_subtract)))) | |
3348 | { | |
3349 | offsetT add; | |
3350 | ||
3351 | if (insn_start_frag == frag_now) | |
3352 | add = (p - frag_now->fr_literal) - insn_start_off; | |
3353 | else | |
3354 | { | |
3355 | fragS *fr; | |
3356 | ||
3357 | add = insn_start_frag->fr_fix - insn_start_off; | |
3358 | for (fr = insn_start_frag->fr_next; | |
3359 | fr && fr != frag_now; fr = fr->fr_next) | |
3360 | add += fr->fr_fix; | |
3361 | add += p - frag_now->fr_literal; | |
3362 | } | |
3363 | ||
3364 | /* We don't support dynamic linking on x86-64 yet. */ | |
3365 | if (flag_code == CODE_64BIT) | |
3366 | abort (); | |
3367 | reloc_type = BFD_RELOC_386_GOTPC; | |
3368 | i.op[n].disps->X_add_number += add; | |
3369 | } | |
062cd5e7 | 3370 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
2bbd9c25 | 3371 | i.op[n].disps, pcrel, reloc_type); |
29b0f896 AM |
3372 | } |
3373 | } | |
3374 | } | |
3375 | } | |
252b5132 | 3376 | |
29b0f896 | 3377 | static void |
2bbd9c25 JJ |
3378 | output_imm (insn_start_frag, insn_start_off) |
3379 | fragS *insn_start_frag; | |
3380 | offsetT insn_start_off; | |
29b0f896 AM |
3381 | { |
3382 | char *p; | |
3383 | unsigned int n; | |
252b5132 | 3384 | |
29b0f896 AM |
3385 | for (n = 0; n < i.operands; n++) |
3386 | { | |
3387 | if (i.types[n] & Imm) | |
3388 | { | |
3389 | if (i.op[n].imms->X_op == O_constant) | |
3390 | { | |
3391 | int size; | |
3392 | offsetT val; | |
b4cac588 | 3393 | |
29b0f896 AM |
3394 | size = 4; |
3395 | if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64)) | |
3396 | { | |
3397 | size = 2; | |
3398 | if (i.types[n] & (Imm8 | Imm8S)) | |
3399 | size = 1; | |
3400 | else if (i.types[n] & Imm64) | |
3401 | size = 8; | |
3402 | } | |
3403 | val = offset_in_range (i.op[n].imms->X_add_number, | |
3404 | size); | |
3405 | p = frag_more (size); | |
3406 | md_number_to_chars (p, val, size); | |
3407 | } | |
3408 | else | |
3409 | { | |
3410 | /* Not absolute_section. | |
3411 | Need a 32-bit fixup (don't support 8bit | |
3412 | non-absolute imms). Try to support other | |
3413 | sizes ... */ | |
f86103b7 | 3414 | enum bfd_reloc_code_real reloc_type; |
29b0f896 AM |
3415 | int size = 4; |
3416 | int sign = 0; | |
3417 | ||
3418 | if ((i.types[n] & (Imm32S)) | |
3419 | && i.suffix == QWORD_MNEM_SUFFIX) | |
3420 | sign = 1; | |
3421 | if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64)) | |
3422 | { | |
3423 | size = 2; | |
3424 | if (i.types[n] & (Imm8 | Imm8S)) | |
3425 | size = 1; | |
3426 | if (i.types[n] & Imm64) | |
3427 | size = 8; | |
3428 | } | |
520dc8e8 | 3429 | |
29b0f896 AM |
3430 | p = frag_more (size); |
3431 | reloc_type = reloc (size, 0, sign, i.reloc[n]); | |
f86103b7 | 3432 | |
2bbd9c25 JJ |
3433 | /* This is tough to explain. We end up with this one if we |
3434 | * have operands that look like | |
3435 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
3436 | * obtain the absolute address of the GOT, and it is strongly | |
3437 | * preferable from a performance point of view to avoid using | |
3438 | * a runtime relocation for this. The actual sequence of | |
3439 | * instructions often look something like: | |
3440 | * | |
3441 | * call .L66 | |
3442 | * .L66: | |
3443 | * popl %ebx | |
3444 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
3445 | * | |
3446 | * The call and pop essentially return the absolute address | |
3447 | * of the label .L66 and store it in %ebx. The linker itself | |
3448 | * will ultimately change the first operand of the addl so | |
3449 | * that %ebx points to the GOT, but to keep things simple, the | |
3450 | * .o file must have this operand set so that it generates not | |
3451 | * the absolute address of .L66, but the absolute address of | |
3452 | * itself. This allows the linker itself simply treat a GOTPC | |
3453 | * relocation as asking for a pcrel offset to the GOT to be | |
3454 | * added in, and the addend of the relocation is stored in the | |
3455 | * operand field for the instruction itself. | |
3456 | * | |
3457 | * Our job here is to fix the operand so that it would add | |
3458 | * the correct offset so that %ebx would point to itself. The | |
3459 | * thing that is tricky is that .-.L66 will point to the | |
3460 | * beginning of the instruction, so we need to further modify | |
3461 | * the operand so that it will point to itself. There are | |
3462 | * other cases where you have something like: | |
3463 | * | |
3464 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
3465 | * | |
3466 | * and here no correction would be required. Internally in | |
3467 | * the assembler we treat operands of this form as not being | |
3468 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
3469 | * whether it would simplify matters to do it this way. Who | |
3470 | * knows. In earlier versions of the PIC patches, the | |
3471 | * pcrel_adjust field was used to store the correction, but | |
3472 | * since the expression is not pcrel, I felt it would be | |
3473 | * confusing to do it this way. */ | |
3474 | ||
29b0f896 AM |
3475 | if (reloc_type == BFD_RELOC_32 |
3476 | && GOT_symbol | |
3477 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
3478 | && (i.op[n].imms->X_op == O_symbol | |
3479 | || (i.op[n].imms->X_op == O_add | |
3480 | && ((symbol_get_value_expression | |
3481 | (i.op[n].imms->X_op_symbol)->X_op) | |
3482 | == O_subtract)))) | |
3483 | { | |
2bbd9c25 JJ |
3484 | offsetT add; |
3485 | ||
3486 | if (insn_start_frag == frag_now) | |
3487 | add = (p - frag_now->fr_literal) - insn_start_off; | |
3488 | else | |
3489 | { | |
3490 | fragS *fr; | |
3491 | ||
3492 | add = insn_start_frag->fr_fix - insn_start_off; | |
3493 | for (fr = insn_start_frag->fr_next; | |
3494 | fr && fr != frag_now; fr = fr->fr_next) | |
3495 | add += fr->fr_fix; | |
3496 | add += p - frag_now->fr_literal; | |
3497 | } | |
3498 | ||
29b0f896 AM |
3499 | /* We don't support dynamic linking on x86-64 yet. */ |
3500 | if (flag_code == CODE_64BIT) | |
3501 | abort (); | |
3502 | reloc_type = BFD_RELOC_386_GOTPC; | |
2bbd9c25 | 3503 | i.op[n].imms->X_add_number += add; |
29b0f896 | 3504 | } |
29b0f896 AM |
3505 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
3506 | i.op[n].imms, 0, reloc_type); | |
3507 | } | |
3508 | } | |
3509 | } | |
252b5132 RH |
3510 | } |
3511 | \f | |
f3c180ae | 3512 | #ifndef LEX_AT |
f86103b7 | 3513 | static char *lex_got PARAMS ((enum bfd_reloc_code_real *, int *)); |
f3c180ae AM |
3514 | |
3515 | /* Parse operands of the form | |
3516 | <symbol>@GOTOFF+<nnn> | |
3517 | and similar .plt or .got references. | |
3518 | ||
3519 | If we find one, set up the correct relocation in RELOC and copy the | |
3520 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
3521 | parsing by the calling routine. Return this buffer, and if ADJUST | |
3522 | is non-null set it to the length of the string we removed from the | |
3523 | input line. Otherwise return NULL. */ | |
3524 | static char * | |
3525 | lex_got (reloc, adjust) | |
f86103b7 | 3526 | enum bfd_reloc_code_real *reloc; |
f3c180ae AM |
3527 | int *adjust; |
3528 | { | |
3529 | static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" }; | |
3530 | static const struct { | |
3531 | const char *str; | |
f86103b7 | 3532 | const enum bfd_reloc_code_real rel[NUM_FLAG_CODE]; |
f3c180ae | 3533 | } gotrel[] = { |
13ae64f3 JJ |
3534 | { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } }, |
3535 | { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } }, | |
3536 | { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } }, | |
bffbf940 | 3537 | { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, BFD_RELOC_X86_64_TLSGD } }, |
13ae64f3 | 3538 | { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } }, |
bffbf940 JJ |
3539 | { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD } }, |
3540 | { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, BFD_RELOC_X86_64_GOTTPOFF } }, | |
3541 | { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, BFD_RELOC_X86_64_TPOFF32 } }, | |
13ae64f3 | 3542 | { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } }, |
bffbf940 | 3543 | { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, BFD_RELOC_X86_64_DTPOFF32 } }, |
37e55690 JJ |
3544 | { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0, 0 } }, |
3545 | { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0, 0 } }, | |
13ae64f3 | 3546 | { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } } |
f3c180ae AM |
3547 | }; |
3548 | char *cp; | |
3549 | unsigned int j; | |
3550 | ||
3551 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
3552 | if (is_end_of_line[(unsigned char) *cp]) | |
3553 | return NULL; | |
3554 | ||
3555 | for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++) | |
3556 | { | |
3557 | int len; | |
3558 | ||
3559 | len = strlen (gotrel[j].str); | |
28f81592 | 3560 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae AM |
3561 | { |
3562 | if (gotrel[j].rel[(unsigned int) flag_code] != 0) | |
3563 | { | |
28f81592 AM |
3564 | int first, second; |
3565 | char *tmpbuf, *past_reloc; | |
f3c180ae AM |
3566 | |
3567 | *reloc = gotrel[j].rel[(unsigned int) flag_code]; | |
28f81592 AM |
3568 | if (adjust) |
3569 | *adjust = len; | |
f3c180ae AM |
3570 | |
3571 | if (GOT_symbol == NULL) | |
3572 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
3573 | ||
3574 | /* Replace the relocation token with ' ', so that | |
3575 | errors like foo@GOTOFF1 will be detected. */ | |
28f81592 AM |
3576 | |
3577 | /* The length of the first part of our input line. */ | |
f3c180ae | 3578 | first = cp - input_line_pointer; |
28f81592 AM |
3579 | |
3580 | /* The second part goes from after the reloc token until | |
3581 | (and including) an end_of_line char. Don't use strlen | |
3582 | here as the end_of_line char may not be a NUL. */ | |
3583 | past_reloc = cp + 1 + len; | |
3584 | for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; ) | |
3585 | ; | |
3586 | second = cp - past_reloc; | |
3587 | ||
3588 | /* Allocate and copy string. The trailing NUL shouldn't | |
3589 | be necessary, but be safe. */ | |
3590 | tmpbuf = xmalloc (first + second + 2); | |
f3c180ae AM |
3591 | memcpy (tmpbuf, input_line_pointer, first); |
3592 | tmpbuf[first] = ' '; | |
28f81592 AM |
3593 | memcpy (tmpbuf + first + 1, past_reloc, second); |
3594 | tmpbuf[first + second + 1] = '\0'; | |
f3c180ae AM |
3595 | return tmpbuf; |
3596 | } | |
3597 | ||
3598 | as_bad (_("@%s reloc is not supported in %s bit mode"), | |
3599 | gotrel[j].str, mode_name[(unsigned int) flag_code]); | |
3600 | return NULL; | |
3601 | } | |
3602 | } | |
3603 | ||
3604 | /* Might be a symbol version string. Don't as_bad here. */ | |
3605 | return NULL; | |
3606 | } | |
3607 | ||
3608 | /* x86_cons_fix_new is called via the expression parsing code when a | |
3609 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
f86103b7 | 3610 | static enum bfd_reloc_code_real got_reloc = NO_RELOC; |
f3c180ae AM |
3611 | |
3612 | void | |
3613 | x86_cons_fix_new (frag, off, len, exp) | |
3614 | fragS *frag; | |
3615 | unsigned int off; | |
3616 | unsigned int len; | |
3617 | expressionS *exp; | |
3618 | { | |
f86103b7 | 3619 | enum bfd_reloc_code_real r = reloc (len, 0, 0, got_reloc); |
f3c180ae AM |
3620 | got_reloc = NO_RELOC; |
3621 | fix_new_exp (frag, off, len, exp, 0, r); | |
3622 | } | |
3623 | ||
3624 | void | |
3625 | x86_cons (exp, size) | |
3626 | expressionS *exp; | |
3627 | int size; | |
3628 | { | |
3629 | if (size == 4) | |
3630 | { | |
3631 | /* Handle @GOTOFF and the like in an expression. */ | |
3632 | char *save; | |
3633 | char *gotfree_input_line; | |
3634 | int adjust; | |
3635 | ||
3636 | save = input_line_pointer; | |
3637 | gotfree_input_line = lex_got (&got_reloc, &adjust); | |
3638 | if (gotfree_input_line) | |
3639 | input_line_pointer = gotfree_input_line; | |
3640 | ||
3641 | expression (exp); | |
3642 | ||
3643 | if (gotfree_input_line) | |
3644 | { | |
3645 | /* expression () has merrily parsed up to the end of line, | |
3646 | or a comma - in the wrong buffer. Transfer how far | |
3647 | input_line_pointer has moved to the right buffer. */ | |
3648 | input_line_pointer = (save | |
3649 | + (input_line_pointer - gotfree_input_line) | |
3650 | + adjust); | |
3651 | free (gotfree_input_line); | |
3652 | } | |
3653 | } | |
3654 | else | |
3655 | expression (exp); | |
3656 | } | |
3657 | #endif | |
3658 | ||
6482c264 NC |
3659 | #ifdef TE_PE |
3660 | ||
3661 | #define O_secrel (O_max + 1) | |
3662 | ||
3663 | void | |
3664 | x86_pe_cons_fix_new (frag, off, len, exp) | |
3665 | fragS *frag; | |
3666 | unsigned int off; | |
3667 | unsigned int len; | |
3668 | expressionS *exp; | |
3669 | { | |
3670 | enum bfd_reloc_code_real r = reloc (len, 0, 0, NO_RELOC); | |
3671 | ||
3672 | if (exp->X_op == O_secrel) | |
3673 | { | |
3674 | exp->X_op = O_symbol; | |
3675 | r = BFD_RELOC_32_SECREL; | |
3676 | } | |
3677 | ||
3678 | fix_new_exp (frag, off, len, exp, 0, r); | |
3679 | } | |
3680 | ||
3681 | static void | |
3682 | pe_directive_secrel (dummy) | |
3683 | int dummy ATTRIBUTE_UNUSED; | |
3684 | { | |
3685 | expressionS exp; | |
3686 | ||
3687 | do | |
3688 | { | |
3689 | expression (&exp); | |
3690 | if (exp.X_op == O_symbol) | |
3691 | exp.X_op = O_secrel; | |
3692 | ||
3693 | emit_expr (&exp, 4); | |
3694 | } | |
3695 | while (*input_line_pointer++ == ','); | |
3696 | ||
3697 | input_line_pointer--; | |
3698 | demand_empty_rest_of_line (); | |
3699 | } | |
3700 | ||
3701 | #endif | |
3702 | ||
252b5132 RH |
3703 | static int i386_immediate PARAMS ((char *)); |
3704 | ||
3705 | static int | |
3706 | i386_immediate (imm_start) | |
3707 | char *imm_start; | |
3708 | { | |
3709 | char *save_input_line_pointer; | |
f3c180ae AM |
3710 | #ifndef LEX_AT |
3711 | char *gotfree_input_line; | |
3712 | #endif | |
252b5132 | 3713 | segT exp_seg = 0; |
47926f60 | 3714 | expressionS *exp; |
252b5132 RH |
3715 | |
3716 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
3717 | { | |
d0b47220 | 3718 | as_bad (_("only 1 or 2 immediate operands are allowed")); |
252b5132 RH |
3719 | return 0; |
3720 | } | |
3721 | ||
3722 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 3723 | i.op[this_operand].imms = exp; |
252b5132 RH |
3724 | |
3725 | if (is_space_char (*imm_start)) | |
3726 | ++imm_start; | |
3727 | ||
3728 | save_input_line_pointer = input_line_pointer; | |
3729 | input_line_pointer = imm_start; | |
3730 | ||
3731 | #ifndef LEX_AT | |
f3c180ae AM |
3732 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL); |
3733 | if (gotfree_input_line) | |
3734 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
3735 | #endif |
3736 | ||
3737 | exp_seg = expression (exp); | |
3738 | ||
83183c0c | 3739 | SKIP_WHITESPACE (); |
252b5132 | 3740 | if (*input_line_pointer) |
f3c180ae | 3741 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
3742 | |
3743 | input_line_pointer = save_input_line_pointer; | |
f3c180ae AM |
3744 | #ifndef LEX_AT |
3745 | if (gotfree_input_line) | |
3746 | free (gotfree_input_line); | |
3747 | #endif | |
252b5132 | 3748 | |
2daf4fd8 | 3749 | if (exp->X_op == O_absent || exp->X_op == O_big) |
252b5132 | 3750 | { |
47926f60 | 3751 | /* Missing or bad expr becomes absolute 0. */ |
d0b47220 | 3752 | as_bad (_("missing or invalid immediate expression `%s' taken as 0"), |
24eab124 | 3753 | imm_start); |
252b5132 RH |
3754 | exp->X_op = O_constant; |
3755 | exp->X_add_number = 0; | |
3756 | exp->X_add_symbol = (symbolS *) 0; | |
3757 | exp->X_op_symbol = (symbolS *) 0; | |
252b5132 | 3758 | } |
3e73aa7c | 3759 | else if (exp->X_op == O_constant) |
252b5132 | 3760 | { |
47926f60 | 3761 | /* Size it properly later. */ |
3e73aa7c JH |
3762 | i.types[this_operand] |= Imm64; |
3763 | /* If BFD64, sign extend val. */ | |
3764 | if (!use_rela_relocations) | |
3765 | if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) | |
3766 | exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 3767 | } |
4c63da97 | 3768 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 3769 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 3770 | && exp_seg != absolute_section |
47926f60 | 3771 | && exp_seg != text_section |
24eab124 AM |
3772 | && exp_seg != data_section |
3773 | && exp_seg != bss_section | |
3774 | && exp_seg != undefined_section | |
f86103b7 | 3775 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 3776 | { |
d0b47220 | 3777 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
3778 | return 0; |
3779 | } | |
3780 | #endif | |
3781 | else | |
3782 | { | |
3783 | /* This is an address. The size of the address will be | |
24eab124 | 3784 | determined later, depending on destination register, |
3e73aa7c JH |
3785 | suffix, or the default for the section. */ |
3786 | i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64; | |
252b5132 RH |
3787 | } |
3788 | ||
3789 | return 1; | |
3790 | } | |
3791 | ||
551c1ca1 | 3792 | static char *i386_scale PARAMS ((char *)); |
252b5132 | 3793 | |
551c1ca1 | 3794 | static char * |
252b5132 RH |
3795 | i386_scale (scale) |
3796 | char *scale; | |
3797 | { | |
551c1ca1 AM |
3798 | offsetT val; |
3799 | char *save = input_line_pointer; | |
252b5132 | 3800 | |
551c1ca1 AM |
3801 | input_line_pointer = scale; |
3802 | val = get_absolute_expression (); | |
3803 | ||
3804 | switch (val) | |
252b5132 | 3805 | { |
551c1ca1 AM |
3806 | case 0: |
3807 | case 1: | |
252b5132 RH |
3808 | i.log2_scale_factor = 0; |
3809 | break; | |
551c1ca1 | 3810 | case 2: |
252b5132 RH |
3811 | i.log2_scale_factor = 1; |
3812 | break; | |
551c1ca1 | 3813 | case 4: |
252b5132 RH |
3814 | i.log2_scale_factor = 2; |
3815 | break; | |
551c1ca1 | 3816 | case 8: |
252b5132 RH |
3817 | i.log2_scale_factor = 3; |
3818 | break; | |
3819 | default: | |
252b5132 | 3820 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), |
24eab124 | 3821 | scale); |
551c1ca1 AM |
3822 | input_line_pointer = save; |
3823 | return NULL; | |
252b5132 | 3824 | } |
29b0f896 | 3825 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
3826 | { |
3827 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 3828 | 1 << i.log2_scale_factor); |
252b5132 RH |
3829 | #if SCALE1_WHEN_NO_INDEX |
3830 | i.log2_scale_factor = 0; | |
3831 | #endif | |
3832 | } | |
551c1ca1 AM |
3833 | scale = input_line_pointer; |
3834 | input_line_pointer = save; | |
3835 | return scale; | |
252b5132 RH |
3836 | } |
3837 | ||
3838 | static int i386_displacement PARAMS ((char *, char *)); | |
3839 | ||
3840 | static int | |
3841 | i386_displacement (disp_start, disp_end) | |
3842 | char *disp_start; | |
3843 | char *disp_end; | |
3844 | { | |
29b0f896 | 3845 | expressionS *exp; |
252b5132 RH |
3846 | segT exp_seg = 0; |
3847 | char *save_input_line_pointer; | |
f3c180ae AM |
3848 | #ifndef LEX_AT |
3849 | char *gotfree_input_line; | |
3850 | #endif | |
252b5132 RH |
3851 | int bigdisp = Disp32; |
3852 | ||
3e73aa7c | 3853 | if (flag_code == CODE_64BIT) |
7ecd2f8b | 3854 | { |
29b0f896 AM |
3855 | if (i.prefix[ADDR_PREFIX] == 0) |
3856 | bigdisp = Disp64; | |
7ecd2f8b JH |
3857 | } |
3858 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) | |
3859 | bigdisp = Disp16; | |
252b5132 RH |
3860 | i.types[this_operand] |= bigdisp; |
3861 | ||
3862 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 3863 | i.op[this_operand].disps = exp; |
252b5132 RH |
3864 | i.disp_operands++; |
3865 | save_input_line_pointer = input_line_pointer; | |
3866 | input_line_pointer = disp_start; | |
3867 | END_STRING_AND_SAVE (disp_end); | |
3868 | ||
3869 | #ifndef GCC_ASM_O_HACK | |
3870 | #define GCC_ASM_O_HACK 0 | |
3871 | #endif | |
3872 | #if GCC_ASM_O_HACK | |
3873 | END_STRING_AND_SAVE (disp_end + 1); | |
3874 | if ((i.types[this_operand] & BaseIndex) != 0 | |
24eab124 | 3875 | && displacement_string_end[-1] == '+') |
252b5132 RH |
3876 | { |
3877 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
3878 | constraint within gcc asm statements. |
3879 | For instance: | |
3880 | ||
3881 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
3882 | __asm__ __volatile__ ( \ | |
3883 | "movw %w2,%0\n\t" \ | |
3884 | "movw %w1,2+%0\n\t" \ | |
3885 | "rorl $16,%1\n\t" \ | |
3886 | "movb %b1,4+%0\n\t" \ | |
3887 | "movb %4,5+%0\n\t" \ | |
3888 | "movb $0,6+%0\n\t" \ | |
3889 | "movb %h1,7+%0\n\t" \ | |
3890 | "rorl $16,%1" \ | |
3891 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
3892 | ||
3893 | This works great except that the output assembler ends | |
3894 | up looking a bit weird if it turns out that there is | |
3895 | no offset. You end up producing code that looks like: | |
3896 | ||
3897 | #APP | |
3898 | movw $235,(%eax) | |
3899 | movw %dx,2+(%eax) | |
3900 | rorl $16,%edx | |
3901 | movb %dl,4+(%eax) | |
3902 | movb $137,5+(%eax) | |
3903 | movb $0,6+(%eax) | |
3904 | movb %dh,7+(%eax) | |
3905 | rorl $16,%edx | |
3906 | #NO_APP | |
3907 | ||
47926f60 | 3908 | So here we provide the missing zero. */ |
24eab124 AM |
3909 | |
3910 | *displacement_string_end = '0'; | |
252b5132 RH |
3911 | } |
3912 | #endif | |
3913 | #ifndef LEX_AT | |
f3c180ae AM |
3914 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL); |
3915 | if (gotfree_input_line) | |
3916 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
3917 | #endif |
3918 | ||
24eab124 | 3919 | exp_seg = expression (exp); |
252b5132 | 3920 | |
636c26b0 AM |
3921 | SKIP_WHITESPACE (); |
3922 | if (*input_line_pointer) | |
3923 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
3924 | #if GCC_ASM_O_HACK | |
3925 | RESTORE_END_STRING (disp_end + 1); | |
3926 | #endif | |
3927 | RESTORE_END_STRING (disp_end); | |
3928 | input_line_pointer = save_input_line_pointer; | |
3929 | #ifndef LEX_AT | |
3930 | if (gotfree_input_line) | |
3931 | free (gotfree_input_line); | |
3932 | #endif | |
3933 | ||
24eab124 AM |
3934 | /* We do this to make sure that the section symbol is in |
3935 | the symbol table. We will ultimately change the relocation | |
47926f60 | 3936 | to be relative to the beginning of the section. */ |
1ae12ab7 AM |
3937 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
3938 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) | |
24eab124 | 3939 | { |
636c26b0 AM |
3940 | if (exp->X_op != O_symbol) |
3941 | { | |
3942 | as_bad (_("bad expression used with @%s"), | |
3943 | (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL | |
3944 | ? "GOTPCREL" | |
3945 | : "GOTOFF")); | |
3946 | return 0; | |
3947 | } | |
3948 | ||
e5cb08ac | 3949 | if (S_IS_LOCAL (exp->X_add_symbol) |
24eab124 AM |
3950 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) |
3951 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); | |
24eab124 AM |
3952 | exp->X_op = O_subtract; |
3953 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 3954 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 3955 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
23df1078 | 3956 | else |
29b0f896 | 3957 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 3958 | } |
252b5132 | 3959 | |
2daf4fd8 AM |
3960 | if (exp->X_op == O_absent || exp->X_op == O_big) |
3961 | { | |
47926f60 | 3962 | /* Missing or bad expr becomes absolute 0. */ |
d0b47220 | 3963 | as_bad (_("missing or invalid displacement expression `%s' taken as 0"), |
2daf4fd8 AM |
3964 | disp_start); |
3965 | exp->X_op = O_constant; | |
3966 | exp->X_add_number = 0; | |
3967 | exp->X_add_symbol = (symbolS *) 0; | |
3968 | exp->X_op_symbol = (symbolS *) 0; | |
3969 | } | |
3970 | ||
4c63da97 | 3971 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
45288df1 | 3972 | if (exp->X_op != O_constant |
45288df1 | 3973 | && OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 3974 | && exp_seg != absolute_section |
45288df1 AM |
3975 | && exp_seg != text_section |
3976 | && exp_seg != data_section | |
3977 | && exp_seg != bss_section | |
31312f95 | 3978 | && exp_seg != undefined_section |
f86103b7 | 3979 | && !bfd_is_com_section (exp_seg)) |
24eab124 | 3980 | { |
d0b47220 | 3981 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
24eab124 AM |
3982 | return 0; |
3983 | } | |
252b5132 | 3984 | #endif |
3e73aa7c JH |
3985 | else if (flag_code == CODE_64BIT) |
3986 | i.types[this_operand] |= Disp32S | Disp32; | |
252b5132 RH |
3987 | return 1; |
3988 | } | |
3989 | ||
e5cb08ac | 3990 | static int i386_index_check PARAMS ((const char *)); |
252b5132 | 3991 | |
eecb386c | 3992 | /* Make sure the memory operand we've been dealt is valid. |
47926f60 KH |
3993 | Return 1 on success, 0 on a failure. */ |
3994 | ||
252b5132 | 3995 | static int |
eecb386c AM |
3996 | i386_index_check (operand_string) |
3997 | const char *operand_string; | |
252b5132 | 3998 | { |
3e73aa7c | 3999 | int ok; |
24eab124 | 4000 | #if INFER_ADDR_PREFIX |
eecb386c AM |
4001 | int fudged = 0; |
4002 | ||
24eab124 AM |
4003 | tryprefix: |
4004 | #endif | |
3e73aa7c | 4005 | ok = 1; |
20f0a1fc NC |
4006 | if (flag_code == CODE_64BIT) |
4007 | { | |
4008 | unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32); | |
4009 | ||
4010 | if ((i.base_reg | |
4011 | && ((i.base_reg->reg_type & RegXX) == 0) | |
4012 | && (i.base_reg->reg_type != BaseIndex | |
4013 | || i.index_reg)) | |
4014 | || (i.index_reg | |
4015 | && ((i.index_reg->reg_type & (RegXX | BaseIndex)) | |
4016 | != (RegXX | BaseIndex)))) | |
4017 | ok = 0; | |
3e73aa7c JH |
4018 | } |
4019 | else | |
4020 | { | |
4021 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) | |
4022 | { | |
4023 | /* 16bit checks. */ | |
4024 | if ((i.base_reg | |
29b0f896 AM |
4025 | && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex)) |
4026 | != (Reg16 | BaseIndex))) | |
3e73aa7c | 4027 | || (i.index_reg |
29b0f896 AM |
4028 | && (((i.index_reg->reg_type & (Reg16 | BaseIndex)) |
4029 | != (Reg16 | BaseIndex)) | |
4030 | || !(i.base_reg | |
4031 | && i.base_reg->reg_num < 6 | |
4032 | && i.index_reg->reg_num >= 6 | |
4033 | && i.log2_scale_factor == 0)))) | |
3e73aa7c JH |
4034 | ok = 0; |
4035 | } | |
4036 | else | |
e5cb08ac | 4037 | { |
3e73aa7c JH |
4038 | /* 32bit checks. */ |
4039 | if ((i.base_reg | |
4040 | && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32) | |
4041 | || (i.index_reg | |
29b0f896 AM |
4042 | && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex)) |
4043 | != (Reg32 | BaseIndex)))) | |
e5cb08ac | 4044 | ok = 0; |
3e73aa7c JH |
4045 | } |
4046 | } | |
4047 | if (!ok) | |
24eab124 AM |
4048 | { |
4049 | #if INFER_ADDR_PREFIX | |
20f0a1fc | 4050 | if (i.prefix[ADDR_PREFIX] == 0) |
24eab124 AM |
4051 | { |
4052 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
4053 | i.prefixes += 1; | |
b23bac36 AM |
4054 | /* Change the size of any displacement too. At most one of |
4055 | Disp16 or Disp32 is set. | |
4056 | FIXME. There doesn't seem to be any real need for separate | |
4057 | Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. | |
47926f60 | 4058 | Removing them would probably clean up the code quite a lot. */ |
20f0a1fc | 4059 | if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32))) |
29b0f896 | 4060 | i.types[this_operand] ^= (Disp16 | Disp32); |
eecb386c | 4061 | fudged = 1; |
24eab124 AM |
4062 | goto tryprefix; |
4063 | } | |
eecb386c AM |
4064 | if (fudged) |
4065 | as_bad (_("`%s' is not a valid base/index expression"), | |
4066 | operand_string); | |
4067 | else | |
c388dee8 | 4068 | #endif |
eecb386c AM |
4069 | as_bad (_("`%s' is not a valid %s bit base/index expression"), |
4070 | operand_string, | |
3e73aa7c | 4071 | flag_code_names[flag_code]); |
24eab124 | 4072 | } |
20f0a1fc | 4073 | return ok; |
24eab124 | 4074 | } |
252b5132 | 4075 | |
252b5132 | 4076 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero |
47926f60 | 4077 | on error. */ |
252b5132 | 4078 | |
252b5132 RH |
4079 | static int |
4080 | i386_operand (operand_string) | |
4081 | char *operand_string; | |
4082 | { | |
af6bdddf AM |
4083 | const reg_entry *r; |
4084 | char *end_op; | |
24eab124 | 4085 | char *op_string = operand_string; |
252b5132 | 4086 | |
24eab124 | 4087 | if (is_space_char (*op_string)) |
252b5132 RH |
4088 | ++op_string; |
4089 | ||
24eab124 | 4090 | /* We check for an absolute prefix (differentiating, |
47926f60 | 4091 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
4092 | if (*op_string == ABSOLUTE_PREFIX) |
4093 | { | |
4094 | ++op_string; | |
4095 | if (is_space_char (*op_string)) | |
4096 | ++op_string; | |
4097 | i.types[this_operand] |= JumpAbsolute; | |
4098 | } | |
252b5132 | 4099 | |
47926f60 | 4100 | /* Check if operand is a register. */ |
af6bdddf AM |
4101 | if ((*op_string == REGISTER_PREFIX || allow_naked_reg) |
4102 | && (r = parse_register (op_string, &end_op)) != NULL) | |
24eab124 | 4103 | { |
24eab124 AM |
4104 | /* Check for a segment override by searching for ':' after a |
4105 | segment register. */ | |
4106 | op_string = end_op; | |
4107 | if (is_space_char (*op_string)) | |
4108 | ++op_string; | |
4109 | if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) | |
4110 | { | |
4111 | switch (r->reg_num) | |
4112 | { | |
4113 | case 0: | |
4114 | i.seg[i.mem_operands] = &es; | |
4115 | break; | |
4116 | case 1: | |
4117 | i.seg[i.mem_operands] = &cs; | |
4118 | break; | |
4119 | case 2: | |
4120 | i.seg[i.mem_operands] = &ss; | |
4121 | break; | |
4122 | case 3: | |
4123 | i.seg[i.mem_operands] = &ds; | |
4124 | break; | |
4125 | case 4: | |
4126 | i.seg[i.mem_operands] = &fs; | |
4127 | break; | |
4128 | case 5: | |
4129 | i.seg[i.mem_operands] = &gs; | |
4130 | break; | |
4131 | } | |
252b5132 | 4132 | |
24eab124 | 4133 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
4134 | ++op_string; |
4135 | if (is_space_char (*op_string)) | |
24eab124 | 4136 | ++op_string; |
252b5132 | 4137 | |
24eab124 AM |
4138 | if (!is_digit_char (*op_string) |
4139 | && !is_identifier_char (*op_string) | |
4140 | && *op_string != '(' | |
4141 | && *op_string != ABSOLUTE_PREFIX) | |
4142 | { | |
4143 | as_bad (_("bad memory operand `%s'"), op_string); | |
4144 | return 0; | |
4145 | } | |
47926f60 | 4146 | /* Handle case of %es:*foo. */ |
24eab124 AM |
4147 | if (*op_string == ABSOLUTE_PREFIX) |
4148 | { | |
4149 | ++op_string; | |
4150 | if (is_space_char (*op_string)) | |
4151 | ++op_string; | |
4152 | i.types[this_operand] |= JumpAbsolute; | |
4153 | } | |
4154 | goto do_memory_reference; | |
4155 | } | |
4156 | if (*op_string) | |
4157 | { | |
d0b47220 | 4158 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
4159 | return 0; |
4160 | } | |
4161 | i.types[this_operand] |= r->reg_type & ~BaseIndex; | |
520dc8e8 | 4162 | i.op[this_operand].regs = r; |
24eab124 AM |
4163 | i.reg_operands++; |
4164 | } | |
af6bdddf AM |
4165 | else if (*op_string == REGISTER_PREFIX) |
4166 | { | |
4167 | as_bad (_("bad register name `%s'"), op_string); | |
4168 | return 0; | |
4169 | } | |
24eab124 | 4170 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 4171 | { |
24eab124 AM |
4172 | ++op_string; |
4173 | if (i.types[this_operand] & JumpAbsolute) | |
4174 | { | |
d0b47220 | 4175 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
4176 | return 0; |
4177 | } | |
4178 | if (!i386_immediate (op_string)) | |
4179 | return 0; | |
4180 | } | |
4181 | else if (is_digit_char (*op_string) | |
4182 | || is_identifier_char (*op_string) | |
e5cb08ac | 4183 | || *op_string == '(') |
24eab124 | 4184 | { |
47926f60 | 4185 | /* This is a memory reference of some sort. */ |
af6bdddf | 4186 | char *base_string; |
252b5132 | 4187 | |
47926f60 | 4188 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
4189 | char *displacement_string_start; |
4190 | char *displacement_string_end; | |
252b5132 | 4191 | |
24eab124 | 4192 | do_memory_reference: |
24eab124 AM |
4193 | if ((i.mem_operands == 1 |
4194 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
4195 | || i.mem_operands == 2) | |
4196 | { | |
4197 | as_bad (_("too many memory references for `%s'"), | |
4198 | current_templates->start->name); | |
4199 | return 0; | |
4200 | } | |
252b5132 | 4201 | |
24eab124 AM |
4202 | /* Check for base index form. We detect the base index form by |
4203 | looking for an ')' at the end of the operand, searching | |
4204 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
4205 | after the '('. */ | |
af6bdddf | 4206 | base_string = op_string + strlen (op_string); |
c3332e24 | 4207 | |
af6bdddf AM |
4208 | --base_string; |
4209 | if (is_space_char (*base_string)) | |
4210 | --base_string; | |
252b5132 | 4211 | |
47926f60 | 4212 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
4213 | displacement_string_start = op_string; |
4214 | displacement_string_end = base_string + 1; | |
252b5132 | 4215 | |
24eab124 AM |
4216 | if (*base_string == ')') |
4217 | { | |
af6bdddf | 4218 | char *temp_string; |
24eab124 AM |
4219 | unsigned int parens_balanced = 1; |
4220 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 4221 | equal, so this loop will not be infinite. */ |
24eab124 AM |
4222 | do |
4223 | { | |
4224 | base_string--; | |
4225 | if (*base_string == ')') | |
4226 | parens_balanced++; | |
4227 | if (*base_string == '(') | |
4228 | parens_balanced--; | |
4229 | } | |
4230 | while (parens_balanced); | |
c3332e24 | 4231 | |
af6bdddf | 4232 | temp_string = base_string; |
c3332e24 | 4233 | |
24eab124 | 4234 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
4235 | ++base_string; |
4236 | if (is_space_char (*base_string)) | |
24eab124 | 4237 | ++base_string; |
252b5132 | 4238 | |
af6bdddf AM |
4239 | if (*base_string == ',' |
4240 | || ((*base_string == REGISTER_PREFIX || allow_naked_reg) | |
4241 | && (i.base_reg = parse_register (base_string, &end_op)) != NULL)) | |
252b5132 | 4242 | { |
af6bdddf | 4243 | displacement_string_end = temp_string; |
252b5132 | 4244 | |
af6bdddf | 4245 | i.types[this_operand] |= BaseIndex; |
252b5132 | 4246 | |
af6bdddf | 4247 | if (i.base_reg) |
24eab124 | 4248 | { |
24eab124 AM |
4249 | base_string = end_op; |
4250 | if (is_space_char (*base_string)) | |
4251 | ++base_string; | |
af6bdddf AM |
4252 | } |
4253 | ||
4254 | /* There may be an index reg or scale factor here. */ | |
4255 | if (*base_string == ',') | |
4256 | { | |
4257 | ++base_string; | |
4258 | if (is_space_char (*base_string)) | |
4259 | ++base_string; | |
4260 | ||
4261 | if ((*base_string == REGISTER_PREFIX || allow_naked_reg) | |
4262 | && (i.index_reg = parse_register (base_string, &end_op)) != NULL) | |
24eab124 | 4263 | { |
af6bdddf | 4264 | base_string = end_op; |
24eab124 AM |
4265 | if (is_space_char (*base_string)) |
4266 | ++base_string; | |
af6bdddf AM |
4267 | if (*base_string == ',') |
4268 | { | |
4269 | ++base_string; | |
4270 | if (is_space_char (*base_string)) | |
4271 | ++base_string; | |
4272 | } | |
e5cb08ac | 4273 | else if (*base_string != ')') |
af6bdddf AM |
4274 | { |
4275 | as_bad (_("expecting `,' or `)' after index register in `%s'"), | |
4276 | operand_string); | |
4277 | return 0; | |
4278 | } | |
24eab124 | 4279 | } |
af6bdddf | 4280 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 4281 | { |
af6bdddf | 4282 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
4283 | return 0; |
4284 | } | |
252b5132 | 4285 | |
47926f60 | 4286 | /* Check for scale factor. */ |
551c1ca1 | 4287 | if (*base_string != ')') |
af6bdddf | 4288 | { |
551c1ca1 AM |
4289 | char *end_scale = i386_scale (base_string); |
4290 | ||
4291 | if (!end_scale) | |
af6bdddf | 4292 | return 0; |
24eab124 | 4293 | |
551c1ca1 | 4294 | base_string = end_scale; |
af6bdddf AM |
4295 | if (is_space_char (*base_string)) |
4296 | ++base_string; | |
4297 | if (*base_string != ')') | |
4298 | { | |
4299 | as_bad (_("expecting `)' after scale factor in `%s'"), | |
4300 | operand_string); | |
4301 | return 0; | |
4302 | } | |
4303 | } | |
4304 | else if (!i.index_reg) | |
24eab124 | 4305 | { |
af6bdddf AM |
4306 | as_bad (_("expecting index register or scale factor after `,'; got '%c'"), |
4307 | *base_string); | |
24eab124 AM |
4308 | return 0; |
4309 | } | |
4310 | } | |
af6bdddf | 4311 | else if (*base_string != ')') |
24eab124 | 4312 | { |
af6bdddf AM |
4313 | as_bad (_("expecting `,' or `)' after base register in `%s'"), |
4314 | operand_string); | |
24eab124 AM |
4315 | return 0; |
4316 | } | |
c3332e24 | 4317 | } |
af6bdddf | 4318 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 4319 | { |
af6bdddf | 4320 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 4321 | return 0; |
c3332e24 | 4322 | } |
24eab124 AM |
4323 | } |
4324 | ||
4325 | /* If there's an expression beginning the operand, parse it, | |
4326 | assuming displacement_string_start and | |
4327 | displacement_string_end are meaningful. */ | |
4328 | if (displacement_string_start != displacement_string_end) | |
4329 | { | |
4330 | if (!i386_displacement (displacement_string_start, | |
4331 | displacement_string_end)) | |
4332 | return 0; | |
4333 | } | |
4334 | ||
4335 | /* Special case for (%dx) while doing input/output op. */ | |
4336 | if (i.base_reg | |
4337 | && i.base_reg->reg_type == (Reg16 | InOutPortReg) | |
4338 | && i.index_reg == 0 | |
4339 | && i.log2_scale_factor == 0 | |
4340 | && i.seg[i.mem_operands] == 0 | |
4341 | && (i.types[this_operand] & Disp) == 0) | |
4342 | { | |
4343 | i.types[this_operand] = InOutPortReg; | |
4344 | return 1; | |
4345 | } | |
4346 | ||
eecb386c AM |
4347 | if (i386_index_check (operand_string) == 0) |
4348 | return 0; | |
24eab124 AM |
4349 | i.mem_operands++; |
4350 | } | |
4351 | else | |
ce8a8b2f AM |
4352 | { |
4353 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
4354 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
4355 | output_invalid (*op_string), | |
4356 | this_operand + 1, | |
4357 | op_string); | |
4358 | return 0; | |
4359 | } | |
47926f60 | 4360 | return 1; /* Normal return. */ |
252b5132 RH |
4361 | } |
4362 | \f | |
ee7fcc42 AM |
4363 | /* md_estimate_size_before_relax() |
4364 | ||
4365 | Called just before relax() for rs_machine_dependent frags. The x86 | |
4366 | assembler uses these frags to handle variable size jump | |
4367 | instructions. | |
4368 | ||
4369 | Any symbol that is now undefined will not become defined. | |
4370 | Return the correct fr_subtype in the frag. | |
4371 | Return the initial "guess for variable size of frag" to caller. | |
4372 | The guess is actually the growth beyond the fixed part. Whatever | |
4373 | we do to grow the fixed or variable part contributes to our | |
4374 | returned value. */ | |
4375 | ||
252b5132 RH |
4376 | int |
4377 | md_estimate_size_before_relax (fragP, segment) | |
29b0f896 AM |
4378 | fragS *fragP; |
4379 | segT segment; | |
252b5132 | 4380 | { |
252b5132 | 4381 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
4382 | check for un-relaxable symbols. On an ELF system, we can't relax |
4383 | an externally visible symbol, because it may be overridden by a | |
4384 | shared library. */ | |
4385 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 4386 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
31312f95 AM |
4387 | || (OUTPUT_FLAVOR == bfd_target_elf_flavour |
4388 | && (S_IS_EXTERNAL (fragP->fr_symbol) | |
4389 | || S_IS_WEAK (fragP->fr_symbol))) | |
b98ef147 AM |
4390 | #endif |
4391 | ) | |
252b5132 | 4392 | { |
b98ef147 AM |
4393 | /* Symbol is undefined in this segment, or we need to keep a |
4394 | reloc so that weak symbols can be overridden. */ | |
4395 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 4396 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
4397 | unsigned char *opcode; |
4398 | int old_fr_fix; | |
f6af82bd | 4399 | |
ee7fcc42 AM |
4400 | if (fragP->fr_var != NO_RELOC) |
4401 | reloc_type = fragP->fr_var; | |
b98ef147 | 4402 | else if (size == 2) |
f6af82bd AM |
4403 | reloc_type = BFD_RELOC_16_PCREL; |
4404 | else | |
4405 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 4406 | |
ee7fcc42 AM |
4407 | old_fr_fix = fragP->fr_fix; |
4408 | opcode = (unsigned char *) fragP->fr_opcode; | |
4409 | ||
fddf5b5b | 4410 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 4411 | { |
fddf5b5b AM |
4412 | case UNCOND_JUMP: |
4413 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 4414 | opcode[0] = 0xe9; |
252b5132 | 4415 | fragP->fr_fix += size; |
062cd5e7 AS |
4416 | fix_new (fragP, old_fr_fix, size, |
4417 | fragP->fr_symbol, | |
4418 | fragP->fr_offset, 1, | |
4419 | reloc_type); | |
252b5132 RH |
4420 | break; |
4421 | ||
fddf5b5b | 4422 | case COND_JUMP86: |
412167cb AM |
4423 | if (size == 2 |
4424 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
4425 | { |
4426 | /* Negate the condition, and branch past an | |
4427 | unconditional jump. */ | |
4428 | opcode[0] ^= 1; | |
4429 | opcode[1] = 3; | |
4430 | /* Insert an unconditional jump. */ | |
4431 | opcode[2] = 0xe9; | |
4432 | /* We added two extra opcode bytes, and have a two byte | |
4433 | offset. */ | |
4434 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
4435 | fix_new (fragP, old_fr_fix + 2, 2, |
4436 | fragP->fr_symbol, | |
4437 | fragP->fr_offset, 1, | |
4438 | reloc_type); | |
fddf5b5b AM |
4439 | break; |
4440 | } | |
4441 | /* Fall through. */ | |
4442 | ||
4443 | case COND_JUMP: | |
412167cb AM |
4444 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
4445 | { | |
3e02c1cc AM |
4446 | fixS *fixP; |
4447 | ||
412167cb | 4448 | fragP->fr_fix += 1; |
3e02c1cc AM |
4449 | fixP = fix_new (fragP, old_fr_fix, 1, |
4450 | fragP->fr_symbol, | |
4451 | fragP->fr_offset, 1, | |
4452 | BFD_RELOC_8_PCREL); | |
4453 | fixP->fx_signed = 1; | |
412167cb AM |
4454 | break; |
4455 | } | |
93c2a809 | 4456 | |
24eab124 | 4457 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 4458 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 4459 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 4460 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
4461 | /* We've added an opcode byte. */ |
4462 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
4463 | fix_new (fragP, old_fr_fix + 1, size, |
4464 | fragP->fr_symbol, | |
4465 | fragP->fr_offset, 1, | |
4466 | reloc_type); | |
252b5132 | 4467 | break; |
fddf5b5b AM |
4468 | |
4469 | default: | |
4470 | BAD_CASE (fragP->fr_subtype); | |
4471 | break; | |
252b5132 RH |
4472 | } |
4473 | frag_wane (fragP); | |
ee7fcc42 | 4474 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 4475 | } |
93c2a809 | 4476 | |
93c2a809 AM |
4477 | /* Guess size depending on current relax state. Initially the relax |
4478 | state will correspond to a short jump and we return 1, because | |
4479 | the variable part of the frag (the branch offset) is one byte | |
4480 | long. However, we can relax a section more than once and in that | |
4481 | case we must either set fr_subtype back to the unrelaxed state, | |
4482 | or return the value for the appropriate branch. */ | |
4483 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
4484 | } |
4485 | ||
47926f60 KH |
4486 | /* Called after relax() is finished. |
4487 | ||
4488 | In: Address of frag. | |
4489 | fr_type == rs_machine_dependent. | |
4490 | fr_subtype is what the address relaxed to. | |
4491 | ||
4492 | Out: Any fixSs and constants are set up. | |
4493 | Caller will turn frag into a ".space 0". */ | |
4494 | ||
252b5132 RH |
4495 | void |
4496 | md_convert_frag (abfd, sec, fragP) | |
ab9da554 ILT |
4497 | bfd *abfd ATTRIBUTE_UNUSED; |
4498 | segT sec ATTRIBUTE_UNUSED; | |
29b0f896 | 4499 | fragS *fragP; |
252b5132 | 4500 | { |
29b0f896 | 4501 | unsigned char *opcode; |
252b5132 | 4502 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
4503 | offsetT target_address; |
4504 | offsetT opcode_address; | |
252b5132 | 4505 | unsigned int extension = 0; |
847f7ad4 | 4506 | offsetT displacement_from_opcode_start; |
252b5132 RH |
4507 | |
4508 | opcode = (unsigned char *) fragP->fr_opcode; | |
4509 | ||
47926f60 | 4510 | /* Address we want to reach in file space. */ |
252b5132 | 4511 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 4512 | |
47926f60 | 4513 | /* Address opcode resides at in file space. */ |
252b5132 RH |
4514 | opcode_address = fragP->fr_address + fragP->fr_fix; |
4515 | ||
47926f60 | 4516 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
4517 | displacement_from_opcode_start = target_address - opcode_address; |
4518 | ||
fddf5b5b | 4519 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 4520 | { |
47926f60 KH |
4521 | /* Don't have to change opcode. */ |
4522 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 4523 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
4524 | } |
4525 | else | |
4526 | { | |
4527 | if (no_cond_jump_promotion | |
4528 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4529 | as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required")); | |
252b5132 | 4530 | |
fddf5b5b AM |
4531 | switch (fragP->fr_subtype) |
4532 | { | |
4533 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
4534 | extension = 4; /* 1 opcode + 4 displacement */ | |
4535 | opcode[0] = 0xe9; | |
4536 | where_to_put_displacement = &opcode[1]; | |
4537 | break; | |
252b5132 | 4538 | |
fddf5b5b AM |
4539 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
4540 | extension = 2; /* 1 opcode + 2 displacement */ | |
4541 | opcode[0] = 0xe9; | |
4542 | where_to_put_displacement = &opcode[1]; | |
4543 | break; | |
252b5132 | 4544 | |
fddf5b5b AM |
4545 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
4546 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
4547 | extension = 5; /* 2 opcode + 4 displacement */ | |
4548 | opcode[1] = opcode[0] + 0x10; | |
4549 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
4550 | where_to_put_displacement = &opcode[2]; | |
4551 | break; | |
252b5132 | 4552 | |
fddf5b5b AM |
4553 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
4554 | extension = 3; /* 2 opcode + 2 displacement */ | |
4555 | opcode[1] = opcode[0] + 0x10; | |
4556 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
4557 | where_to_put_displacement = &opcode[2]; | |
4558 | break; | |
252b5132 | 4559 | |
fddf5b5b AM |
4560 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
4561 | extension = 4; | |
4562 | opcode[0] ^= 1; | |
4563 | opcode[1] = 3; | |
4564 | opcode[2] = 0xe9; | |
4565 | where_to_put_displacement = &opcode[3]; | |
4566 | break; | |
4567 | ||
4568 | default: | |
4569 | BAD_CASE (fragP->fr_subtype); | |
4570 | break; | |
4571 | } | |
252b5132 | 4572 | } |
fddf5b5b | 4573 | |
47926f60 | 4574 | /* Now put displacement after opcode. */ |
252b5132 RH |
4575 | md_number_to_chars ((char *) where_to_put_displacement, |
4576 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 4577 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
4578 | fragP->fr_fix += extension; |
4579 | } | |
4580 | \f | |
47926f60 KH |
4581 | /* Size of byte displacement jmp. */ |
4582 | int md_short_jump_size = 2; | |
4583 | ||
4584 | /* Size of dword displacement jmp. */ | |
4585 | int md_long_jump_size = 5; | |
252b5132 | 4586 | |
47926f60 KH |
4587 | /* Size of relocation record. */ |
4588 | const int md_reloc_size = 8; | |
252b5132 RH |
4589 | |
4590 | void | |
4591 | md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
4592 | char *ptr; | |
4593 | addressT from_addr, to_addr; | |
ab9da554 ILT |
4594 | fragS *frag ATTRIBUTE_UNUSED; |
4595 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
252b5132 | 4596 | { |
847f7ad4 | 4597 | offsetT offset; |
252b5132 RH |
4598 | |
4599 | offset = to_addr - (from_addr + 2); | |
47926f60 KH |
4600 | /* Opcode for byte-disp jump. */ |
4601 | md_number_to_chars (ptr, (valueT) 0xeb, 1); | |
252b5132 RH |
4602 | md_number_to_chars (ptr + 1, (valueT) offset, 1); |
4603 | } | |
4604 | ||
4605 | void | |
4606 | md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
4607 | char *ptr; | |
4608 | addressT from_addr, to_addr; | |
a38cf1db AM |
4609 | fragS *frag ATTRIBUTE_UNUSED; |
4610 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
252b5132 | 4611 | { |
847f7ad4 | 4612 | offsetT offset; |
252b5132 | 4613 | |
a38cf1db AM |
4614 | offset = to_addr - (from_addr + 5); |
4615 | md_number_to_chars (ptr, (valueT) 0xe9, 1); | |
4616 | md_number_to_chars (ptr + 1, (valueT) offset, 4); | |
252b5132 RH |
4617 | } |
4618 | \f | |
4619 | /* Apply a fixup (fixS) to segment data, once it has been determined | |
4620 | by our caller that we have all the info we need to fix it up. | |
4621 | ||
4622 | On the 386, immediates, displacements, and data pointers are all in | |
4623 | the same (little-endian) format, so we don't need to care about which | |
4624 | we are handling. */ | |
4625 | ||
94f592af NC |
4626 | void |
4627 | md_apply_fix3 (fixP, valP, seg) | |
47926f60 KH |
4628 | /* The fix we're to put in. */ |
4629 | fixS *fixP; | |
47926f60 | 4630 | /* Pointer to the value of the bits. */ |
c6682705 | 4631 | valueT *valP; |
47926f60 KH |
4632 | /* Segment fix is from. */ |
4633 | segT seg ATTRIBUTE_UNUSED; | |
252b5132 | 4634 | { |
94f592af | 4635 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 4636 | valueT value = *valP; |
252b5132 | 4637 | |
f86103b7 | 4638 | #if !defined (TE_Mach) |
93382f6d AM |
4639 | if (fixP->fx_pcrel) |
4640 | { | |
4641 | switch (fixP->fx_r_type) | |
4642 | { | |
5865bb77 ILT |
4643 | default: |
4644 | break; | |
4645 | ||
93382f6d AM |
4646 | case BFD_RELOC_32: |
4647 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
4648 | break; | |
4649 | case BFD_RELOC_16: | |
4650 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
4651 | break; | |
4652 | case BFD_RELOC_8: | |
4653 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
4654 | break; | |
4655 | } | |
4656 | } | |
252b5132 | 4657 | |
a161fe53 | 4658 | if (fixP->fx_addsy != NULL |
31312f95 AM |
4659 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
4660 | || fixP->fx_r_type == BFD_RELOC_16_PCREL | |
4661 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) | |
4662 | && !use_rela_relocations) | |
252b5132 | 4663 | { |
31312f95 AM |
4664 | /* This is a hack. There should be a better way to handle this. |
4665 | This covers for the fact that bfd_install_relocation will | |
4666 | subtract the current location (for partial_inplace, PC relative | |
4667 | relocations); see more below. */ | |
252b5132 RH |
4668 | #ifndef OBJ_AOUT |
4669 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
4670 | #ifdef TE_PE | |
4671 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
4672 | #endif | |
4673 | ) | |
4674 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
4675 | #endif | |
4676 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2f66722d | 4677 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
252b5132 | 4678 | { |
6539b54b | 4679 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 4680 | |
6539b54b | 4681 | if ((sym_seg == seg |
2f66722d | 4682 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 4683 | && sym_seg != absolute_section)) |
ae6063d4 | 4684 | && !generic_force_reloc (fixP)) |
2f66722d AM |
4685 | { |
4686 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
4687 | bfd_install_relocation subtracts them out again. I think |
4688 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
4689 | it. FIXME. */ |
4690 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
4691 | } | |
252b5132 RH |
4692 | } |
4693 | #endif | |
4694 | #if defined (OBJ_COFF) && defined (TE_PE) | |
4695 | /* For some reason, the PE format does not store a section | |
24eab124 | 4696 | address offset for a PC relative symbol. */ |
252b5132 RH |
4697 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg) |
4698 | value += md_pcrel_from (fixP); | |
4699 | #endif | |
4700 | } | |
4701 | ||
4702 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 4703 | and we must not disappoint it. */ |
252b5132 RH |
4704 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
4705 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
4706 | && fixP->fx_addsy) | |
47926f60 KH |
4707 | switch (fixP->fx_r_type) |
4708 | { | |
4709 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 4710 | case BFD_RELOC_X86_64_PLT32: |
47926f60 KH |
4711 | /* Make the jump instruction point to the address of the operand. At |
4712 | runtime we merely add the offset to the actual PLT entry. */ | |
4713 | value = -4; | |
4714 | break; | |
31312f95 | 4715 | |
13ae64f3 JJ |
4716 | case BFD_RELOC_386_TLS_GD: |
4717 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 4718 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
4719 | case BFD_RELOC_386_TLS_IE: |
4720 | case BFD_RELOC_386_TLS_GOTIE: | |
bffbf940 JJ |
4721 | case BFD_RELOC_X86_64_TLSGD: |
4722 | case BFD_RELOC_X86_64_TLSLD: | |
4723 | case BFD_RELOC_X86_64_GOTTPOFF: | |
00f7efb6 JJ |
4724 | value = 0; /* Fully resolved at runtime. No addend. */ |
4725 | /* Fallthrough */ | |
4726 | case BFD_RELOC_386_TLS_LE: | |
4727 | case BFD_RELOC_386_TLS_LDO_32: | |
4728 | case BFD_RELOC_386_TLS_LE_32: | |
4729 | case BFD_RELOC_X86_64_DTPOFF32: | |
4730 | case BFD_RELOC_X86_64_TPOFF32: | |
4731 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
4732 | break; | |
4733 | ||
4734 | case BFD_RELOC_386_GOT32: | |
4735 | case BFD_RELOC_X86_64_GOT32: | |
47926f60 KH |
4736 | value = 0; /* Fully resolved at runtime. No addend. */ |
4737 | break; | |
47926f60 KH |
4738 | |
4739 | case BFD_RELOC_VTABLE_INHERIT: | |
4740 | case BFD_RELOC_VTABLE_ENTRY: | |
4741 | fixP->fx_done = 0; | |
94f592af | 4742 | return; |
47926f60 KH |
4743 | |
4744 | default: | |
4745 | break; | |
4746 | } | |
4747 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 4748 | *valP = value; |
f86103b7 | 4749 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 4750 | |
3e73aa7c | 4751 | /* Are we finished with this relocation now? */ |
c6682705 | 4752 | if (fixP->fx_addsy == NULL) |
3e73aa7c JH |
4753 | fixP->fx_done = 1; |
4754 | else if (use_rela_relocations) | |
4755 | { | |
4756 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
4757 | /* Remember value for tc_gen_reloc. */ |
4758 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
4759 | value = 0; |
4760 | } | |
f86103b7 | 4761 | |
94f592af | 4762 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 4763 | } |
252b5132 | 4764 | \f |
252b5132 RH |
4765 | #define MAX_LITTLENUMS 6 |
4766 | ||
47926f60 KH |
4767 | /* Turn the string pointed to by litP into a floating point constant |
4768 | of type TYPE, and emit the appropriate bytes. The number of | |
4769 | LITTLENUMS emitted is stored in *SIZEP. An error message is | |
4770 | returned, or NULL on OK. */ | |
4771 | ||
252b5132 RH |
4772 | char * |
4773 | md_atof (type, litP, sizeP) | |
2ab9b79e | 4774 | int type; |
252b5132 RH |
4775 | char *litP; |
4776 | int *sizeP; | |
4777 | { | |
4778 | int prec; | |
4779 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4780 | LITTLENUM_TYPE *wordP; | |
4781 | char *t; | |
4782 | ||
4783 | switch (type) | |
4784 | { | |
4785 | case 'f': | |
4786 | case 'F': | |
4787 | prec = 2; | |
4788 | break; | |
4789 | ||
4790 | case 'd': | |
4791 | case 'D': | |
4792 | prec = 4; | |
4793 | break; | |
4794 | ||
4795 | case 'x': | |
4796 | case 'X': | |
4797 | prec = 5; | |
4798 | break; | |
4799 | ||
4800 | default: | |
4801 | *sizeP = 0; | |
4802 | return _("Bad call to md_atof ()"); | |
4803 | } | |
4804 | t = atof_ieee (input_line_pointer, type, words); | |
4805 | if (t) | |
4806 | input_line_pointer = t; | |
4807 | ||
4808 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
4809 | /* This loops outputs the LITTLENUMs in REVERSE order; in accord with | |
4810 | the bigendian 386. */ | |
4811 | for (wordP = words + prec - 1; prec--;) | |
4812 | { | |
4813 | md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE)); | |
4814 | litP += sizeof (LITTLENUM_TYPE); | |
4815 | } | |
4816 | return 0; | |
4817 | } | |
4818 | \f | |
4819 | char output_invalid_buf[8]; | |
4820 | ||
252b5132 RH |
4821 | static char * |
4822 | output_invalid (c) | |
4823 | int c; | |
4824 | { | |
3882b010 | 4825 | if (ISPRINT (c)) |
252b5132 RH |
4826 | sprintf (output_invalid_buf, "'%c'", c); |
4827 | else | |
4828 | sprintf (output_invalid_buf, "(0x%x)", (unsigned) c); | |
4829 | return output_invalid_buf; | |
4830 | } | |
4831 | ||
af6bdddf | 4832 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
4833 | |
4834 | static const reg_entry * | |
4835 | parse_register (reg_string, end_op) | |
4836 | char *reg_string; | |
4837 | char **end_op; | |
4838 | { | |
af6bdddf AM |
4839 | char *s = reg_string; |
4840 | char *p; | |
252b5132 RH |
4841 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
4842 | const reg_entry *r; | |
4843 | ||
4844 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
4845 | if (*s == REGISTER_PREFIX) | |
4846 | ++s; | |
4847 | ||
4848 | if (is_space_char (*s)) | |
4849 | ++s; | |
4850 | ||
4851 | p = reg_name_given; | |
af6bdddf | 4852 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
4853 | { |
4854 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
4855 | return (const reg_entry *) NULL; |
4856 | s++; | |
252b5132 RH |
4857 | } |
4858 | ||
6588847e DN |
4859 | /* For naked regs, make sure that we are not dealing with an identifier. |
4860 | This prevents confusing an identifier like `eax_var' with register | |
4861 | `eax'. */ | |
4862 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
4863 | return (const reg_entry *) NULL; | |
4864 | ||
af6bdddf | 4865 | *end_op = s; |
252b5132 RH |
4866 | |
4867 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
4868 | ||
5f47d35b | 4869 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 4870 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 4871 | { |
5f47d35b AM |
4872 | if (is_space_char (*s)) |
4873 | ++s; | |
4874 | if (*s == '(') | |
4875 | { | |
af6bdddf | 4876 | ++s; |
5f47d35b AM |
4877 | if (is_space_char (*s)) |
4878 | ++s; | |
4879 | if (*s >= '0' && *s <= '7') | |
4880 | { | |
4881 | r = &i386_float_regtab[*s - '0']; | |
af6bdddf | 4882 | ++s; |
5f47d35b AM |
4883 | if (is_space_char (*s)) |
4884 | ++s; | |
4885 | if (*s == ')') | |
4886 | { | |
4887 | *end_op = s + 1; | |
4888 | return r; | |
4889 | } | |
5f47d35b | 4890 | } |
47926f60 | 4891 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
4892 | return (const reg_entry *) NULL; |
4893 | } | |
4894 | } | |
4895 | ||
1ae00879 | 4896 | if (r != NULL |
20f0a1fc | 4897 | && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0 |
1ae00879 | 4898 | && flag_code != CODE_64BIT) |
20f0a1fc | 4899 | return (const reg_entry *) NULL; |
1ae00879 | 4900 | |
252b5132 RH |
4901 | return r; |
4902 | } | |
4903 | \f | |
4cc782b5 | 4904 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12b55ccc | 4905 | const char *md_shortopts = "kVQ:sqn"; |
252b5132 | 4906 | #else |
12b55ccc | 4907 | const char *md_shortopts = "qn"; |
252b5132 | 4908 | #endif |
6e0b89ee | 4909 | |
252b5132 | 4910 | struct option md_longopts[] = { |
3e73aa7c JH |
4911 | #define OPTION_32 (OPTION_MD_BASE + 0) |
4912 | {"32", no_argument, NULL, OPTION_32}, | |
6e0b89ee | 4913 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3e73aa7c JH |
4914 | #define OPTION_64 (OPTION_MD_BASE + 1) |
4915 | {"64", no_argument, NULL, OPTION_64}, | |
6e0b89ee | 4916 | #endif |
252b5132 RH |
4917 | {NULL, no_argument, NULL, 0} |
4918 | }; | |
4919 | size_t md_longopts_size = sizeof (md_longopts); | |
4920 | ||
4921 | int | |
4922 | md_parse_option (c, arg) | |
4923 | int c; | |
ab9da554 | 4924 | char *arg ATTRIBUTE_UNUSED; |
252b5132 RH |
4925 | { |
4926 | switch (c) | |
4927 | { | |
12b55ccc L |
4928 | case 'n': |
4929 | optimize_align_code = 0; | |
4930 | break; | |
4931 | ||
a38cf1db AM |
4932 | case 'q': |
4933 | quiet_warnings = 1; | |
252b5132 RH |
4934 | break; |
4935 | ||
4936 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
4937 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
4938 | should be emitted or not. FIXME: Not implemented. */ | |
4939 | case 'Q': | |
252b5132 RH |
4940 | break; |
4941 | ||
4942 | /* -V: SVR4 argument to print version ID. */ | |
4943 | case 'V': | |
4944 | print_version_id (); | |
4945 | break; | |
4946 | ||
a38cf1db AM |
4947 | /* -k: Ignore for FreeBSD compatibility. */ |
4948 | case 'k': | |
252b5132 | 4949 | break; |
4cc782b5 ILT |
4950 | |
4951 | case 's': | |
4952 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 4953 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 4954 | break; |
6e0b89ee | 4955 | |
3e73aa7c JH |
4956 | case OPTION_64: |
4957 | { | |
4958 | const char **list, **l; | |
4959 | ||
3e73aa7c JH |
4960 | list = bfd_target_list (); |
4961 | for (l = list; *l != NULL; l++) | |
6e0b89ee AM |
4962 | if (strcmp (*l, "elf64-x86-64") == 0) |
4963 | { | |
4964 | default_arch = "x86_64"; | |
4965 | break; | |
4966 | } | |
3e73aa7c | 4967 | if (*l == NULL) |
6e0b89ee | 4968 | as_fatal (_("No compiled in support for x86_64")); |
3e73aa7c JH |
4969 | free (list); |
4970 | } | |
4971 | break; | |
4972 | #endif | |
252b5132 | 4973 | |
6e0b89ee AM |
4974 | case OPTION_32: |
4975 | default_arch = "i386"; | |
4976 | break; | |
4977 | ||
252b5132 RH |
4978 | default: |
4979 | return 0; | |
4980 | } | |
4981 | return 1; | |
4982 | } | |
4983 | ||
4984 | void | |
4985 | md_show_usage (stream) | |
4986 | FILE *stream; | |
4987 | { | |
4cc782b5 ILT |
4988 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
4989 | fprintf (stream, _("\ | |
a38cf1db AM |
4990 | -Q ignored\n\ |
4991 | -V print assembler version number\n\ | |
4992 | -k ignored\n\ | |
12b55ccc | 4993 | -n Do not optimize code alignment\n\ |
a38cf1db AM |
4994 | -q quieten some warnings\n\ |
4995 | -s ignored\n")); | |
4996 | #else | |
4997 | fprintf (stream, _("\ | |
12b55ccc | 4998 | -n Do not optimize code alignment\n\ |
a38cf1db | 4999 | -q quieten some warnings\n")); |
4cc782b5 | 5000 | #endif |
252b5132 RH |
5001 | } |
5002 | ||
3e73aa7c JH |
5003 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
5004 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) | |
252b5132 RH |
5005 | |
5006 | /* Pick the target format to use. */ | |
5007 | ||
47926f60 | 5008 | const char * |
252b5132 RH |
5009 | i386_target_format () |
5010 | { | |
3e73aa7c JH |
5011 | if (!strcmp (default_arch, "x86_64")) |
5012 | set_code_flag (CODE_64BIT); | |
5013 | else if (!strcmp (default_arch, "i386")) | |
5014 | set_code_flag (CODE_32BIT); | |
5015 | else | |
5016 | as_fatal (_("Unknown architecture")); | |
252b5132 RH |
5017 | switch (OUTPUT_FLAVOR) |
5018 | { | |
4c63da97 AM |
5019 | #ifdef OBJ_MAYBE_AOUT |
5020 | case bfd_target_aout_flavour: | |
47926f60 | 5021 | return AOUT_TARGET_FORMAT; |
4c63da97 AM |
5022 | #endif |
5023 | #ifdef OBJ_MAYBE_COFF | |
252b5132 RH |
5024 | case bfd_target_coff_flavour: |
5025 | return "coff-i386"; | |
4c63da97 | 5026 | #endif |
3e73aa7c | 5027 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 5028 | case bfd_target_elf_flavour: |
3e73aa7c | 5029 | { |
e5cb08ac KH |
5030 | if (flag_code == CODE_64BIT) |
5031 | use_rela_relocations = 1; | |
4ada7262 | 5032 | return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT; |
3e73aa7c | 5033 | } |
4c63da97 | 5034 | #endif |
252b5132 RH |
5035 | default: |
5036 | abort (); | |
5037 | return NULL; | |
5038 | } | |
5039 | } | |
5040 | ||
47926f60 | 5041 | #endif /* OBJ_MAYBE_ more than one */ |
a847613f AM |
5042 | |
5043 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) | |
5044 | void i386_elf_emit_arch_note () | |
5045 | { | |
5046 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
5047 | && cpu_arch_name != NULL) | |
5048 | { | |
5049 | char *p; | |
5050 | asection *seg = now_seg; | |
5051 | subsegT subseg = now_subseg; | |
5052 | Elf_Internal_Note i_note; | |
5053 | Elf_External_Note e_note; | |
5054 | asection *note_secp; | |
5055 | int len; | |
5056 | ||
5057 | /* Create the .note section. */ | |
5058 | note_secp = subseg_new (".note", 0); | |
5059 | bfd_set_section_flags (stdoutput, | |
5060 | note_secp, | |
5061 | SEC_HAS_CONTENTS | SEC_READONLY); | |
5062 | ||
5063 | /* Process the arch string. */ | |
5064 | len = strlen (cpu_arch_name); | |
5065 | ||
5066 | i_note.namesz = len + 1; | |
5067 | i_note.descsz = 0; | |
5068 | i_note.type = NT_ARCH; | |
5069 | p = frag_more (sizeof (e_note.namesz)); | |
5070 | md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz)); | |
5071 | p = frag_more (sizeof (e_note.descsz)); | |
5072 | md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz)); | |
5073 | p = frag_more (sizeof (e_note.type)); | |
5074 | md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type)); | |
5075 | p = frag_more (len + 1); | |
5076 | strcpy (p, cpu_arch_name); | |
5077 | ||
5078 | frag_align (2, 0, 0); | |
5079 | ||
5080 | subseg_set (seg, subseg); | |
5081 | } | |
5082 | } | |
5083 | #endif | |
252b5132 | 5084 | \f |
252b5132 RH |
5085 | symbolS * |
5086 | md_undefined_symbol (name) | |
5087 | char *name; | |
5088 | { | |
18dc2407 ILT |
5089 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
5090 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
5091 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
5092 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
5093 | { |
5094 | if (!GOT_symbol) | |
5095 | { | |
5096 | if (symbol_find (name)) | |
5097 | as_bad (_("GOT already in symbol table")); | |
5098 | GOT_symbol = symbol_new (name, undefined_section, | |
5099 | (valueT) 0, &zero_address_frag); | |
5100 | }; | |
5101 | return GOT_symbol; | |
5102 | } | |
252b5132 RH |
5103 | return 0; |
5104 | } | |
5105 | ||
5106 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 5107 | |
252b5132 RH |
5108 | valueT |
5109 | md_section_align (segment, size) | |
ab9da554 | 5110 | segT segment ATTRIBUTE_UNUSED; |
252b5132 RH |
5111 | valueT size; |
5112 | { | |
4c63da97 AM |
5113 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
5114 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
5115 | { | |
5116 | /* For a.out, force the section size to be aligned. If we don't do | |
5117 | this, BFD will align it for us, but it will not write out the | |
5118 | final bytes of the section. This may be a bug in BFD, but it is | |
5119 | easier to fix it here since that is how the other a.out targets | |
5120 | work. */ | |
5121 | int align; | |
5122 | ||
5123 | align = bfd_get_section_alignment (stdoutput, segment); | |
5124 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
5125 | } | |
252b5132 RH |
5126 | #endif |
5127 | ||
5128 | return size; | |
5129 | } | |
5130 | ||
5131 | /* On the i386, PC-relative offsets are relative to the start of the | |
5132 | next instruction. That is, the address of the offset, plus its | |
5133 | size, since the offset is always the last part of the insn. */ | |
5134 | ||
5135 | long | |
5136 | md_pcrel_from (fixP) | |
5137 | fixS *fixP; | |
5138 | { | |
5139 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
5140 | } | |
5141 | ||
5142 | #ifndef I386COFF | |
5143 | ||
5144 | static void | |
5145 | s_bss (ignore) | |
ab9da554 | 5146 | int ignore ATTRIBUTE_UNUSED; |
252b5132 | 5147 | { |
29b0f896 | 5148 | int temp; |
252b5132 RH |
5149 | |
5150 | temp = get_absolute_expression (); | |
5151 | subseg_set (bss_section, (subsegT) temp); | |
5152 | demand_empty_rest_of_line (); | |
5153 | } | |
5154 | ||
5155 | #endif | |
5156 | ||
252b5132 RH |
5157 | void |
5158 | i386_validate_fix (fixp) | |
5159 | fixS *fixp; | |
5160 | { | |
5161 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
5162 | { | |
3e73aa7c | 5163 | /* GOTOFF relocation are nonsense in 64bit mode. */ |
23df1078 JH |
5164 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
5165 | { | |
5166 | if (flag_code != CODE_64BIT) | |
5167 | abort (); | |
5168 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
5169 | } | |
5170 | else | |
5171 | { | |
5172 | if (flag_code == CODE_64BIT) | |
5173 | abort (); | |
5174 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
5175 | } | |
252b5132 RH |
5176 | fixp->fx_subsy = 0; |
5177 | } | |
5178 | } | |
5179 | ||
252b5132 RH |
5180 | arelent * |
5181 | tc_gen_reloc (section, fixp) | |
ab9da554 | 5182 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
5183 | fixS *fixp; |
5184 | { | |
5185 | arelent *rel; | |
5186 | bfd_reloc_code_real_type code; | |
5187 | ||
5188 | switch (fixp->fx_r_type) | |
5189 | { | |
3e73aa7c JH |
5190 | case BFD_RELOC_X86_64_PLT32: |
5191 | case BFD_RELOC_X86_64_GOT32: | |
5192 | case BFD_RELOC_X86_64_GOTPCREL: | |
252b5132 RH |
5193 | case BFD_RELOC_386_PLT32: |
5194 | case BFD_RELOC_386_GOT32: | |
5195 | case BFD_RELOC_386_GOTOFF: | |
5196 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
5197 | case BFD_RELOC_386_TLS_GD: |
5198 | case BFD_RELOC_386_TLS_LDM: | |
5199 | case BFD_RELOC_386_TLS_LDO_32: | |
5200 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
5201 | case BFD_RELOC_386_TLS_IE: |
5202 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
5203 | case BFD_RELOC_386_TLS_LE_32: |
5204 | case BFD_RELOC_386_TLS_LE: | |
3e73aa7c | 5205 | case BFD_RELOC_X86_64_32S: |
bffbf940 JJ |
5206 | case BFD_RELOC_X86_64_TLSGD: |
5207 | case BFD_RELOC_X86_64_TLSLD: | |
5208 | case BFD_RELOC_X86_64_DTPOFF32: | |
5209 | case BFD_RELOC_X86_64_GOTTPOFF: | |
5210 | case BFD_RELOC_X86_64_TPOFF32: | |
252b5132 RH |
5211 | case BFD_RELOC_RVA: |
5212 | case BFD_RELOC_VTABLE_ENTRY: | |
5213 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
5214 | #ifdef TE_PE |
5215 | case BFD_RELOC_32_SECREL: | |
5216 | #endif | |
252b5132 RH |
5217 | code = fixp->fx_r_type; |
5218 | break; | |
5219 | default: | |
93382f6d | 5220 | if (fixp->fx_pcrel) |
252b5132 | 5221 | { |
93382f6d AM |
5222 | switch (fixp->fx_size) |
5223 | { | |
5224 | default: | |
b091f402 AM |
5225 | as_bad_where (fixp->fx_file, fixp->fx_line, |
5226 | _("can not do %d byte pc-relative relocation"), | |
5227 | fixp->fx_size); | |
93382f6d AM |
5228 | code = BFD_RELOC_32_PCREL; |
5229 | break; | |
5230 | case 1: code = BFD_RELOC_8_PCREL; break; | |
5231 | case 2: code = BFD_RELOC_16_PCREL; break; | |
5232 | case 4: code = BFD_RELOC_32_PCREL; break; | |
5233 | } | |
5234 | } | |
5235 | else | |
5236 | { | |
5237 | switch (fixp->fx_size) | |
5238 | { | |
5239 | default: | |
b091f402 AM |
5240 | as_bad_where (fixp->fx_file, fixp->fx_line, |
5241 | _("can not do %d byte relocation"), | |
5242 | fixp->fx_size); | |
93382f6d AM |
5243 | code = BFD_RELOC_32; |
5244 | break; | |
5245 | case 1: code = BFD_RELOC_8; break; | |
5246 | case 2: code = BFD_RELOC_16; break; | |
5247 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 5248 | #ifdef BFD64 |
3e73aa7c | 5249 | case 8: code = BFD_RELOC_64; break; |
937149dd | 5250 | #endif |
93382f6d | 5251 | } |
252b5132 RH |
5252 | } |
5253 | break; | |
5254 | } | |
252b5132 RH |
5255 | |
5256 | if (code == BFD_RELOC_32 | |
5257 | && GOT_symbol | |
5258 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c JH |
5259 | { |
5260 | /* We don't support GOTPC on 64bit targets. */ | |
5261 | if (flag_code == CODE_64BIT) | |
bfb32b52 | 5262 | abort (); |
3e73aa7c JH |
5263 | code = BFD_RELOC_386_GOTPC; |
5264 | } | |
252b5132 RH |
5265 | |
5266 | rel = (arelent *) xmalloc (sizeof (arelent)); | |
49309057 ILT |
5267 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
5268 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
5269 | |
5270 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 CF |
5271 | |
5272 | #ifdef TE_PE | |
5273 | if (S_IS_WEAK (fixp->fx_addsy)) | |
5274 | rel->addend = rel->address - (*rel->sym_ptr_ptr)->value + 4; | |
5275 | else | |
5276 | #endif | |
3e73aa7c JH |
5277 | if (!use_rela_relocations) |
5278 | { | |
5279 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
5280 | vtable entry to be used in the relocation's section offset. */ | |
5281 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
5282 | rel->address = fixp->fx_offset; | |
252b5132 | 5283 | |
c6682705 | 5284 | rel->addend = 0; |
3e73aa7c JH |
5285 | } |
5286 | /* Use the rela in 64bit mode. */ | |
252b5132 | 5287 | else |
3e73aa7c | 5288 | { |
062cd5e7 AS |
5289 | if (!fixp->fx_pcrel) |
5290 | rel->addend = fixp->fx_offset; | |
5291 | else | |
5292 | switch (code) | |
5293 | { | |
5294 | case BFD_RELOC_X86_64_PLT32: | |
5295 | case BFD_RELOC_X86_64_GOT32: | |
5296 | case BFD_RELOC_X86_64_GOTPCREL: | |
bffbf940 JJ |
5297 | case BFD_RELOC_X86_64_TLSGD: |
5298 | case BFD_RELOC_X86_64_TLSLD: | |
5299 | case BFD_RELOC_X86_64_GOTTPOFF: | |
062cd5e7 AS |
5300 | rel->addend = fixp->fx_offset - fixp->fx_size; |
5301 | break; | |
5302 | default: | |
5303 | rel->addend = (section->vma | |
5304 | - fixp->fx_size | |
5305 | + fixp->fx_addnumber | |
5306 | + md_pcrel_from (fixp)); | |
5307 | break; | |
5308 | } | |
3e73aa7c JH |
5309 | } |
5310 | ||
252b5132 RH |
5311 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
5312 | if (rel->howto == NULL) | |
5313 | { | |
5314 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 5315 | _("cannot represent relocation type %s"), |
252b5132 RH |
5316 | bfd_get_reloc_code_name (code)); |
5317 | /* Set howto to a garbage value so that we can keep going. */ | |
5318 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
5319 | assert (rel->howto != NULL); | |
5320 | } | |
5321 | ||
5322 | return rel; | |
5323 | } | |
5324 | ||
64a0c779 DN |
5325 | \f |
5326 | /* Parse operands using Intel syntax. This implements a recursive descent | |
5327 | parser based on the BNF grammar published in Appendix B of the MASM 6.1 | |
5328 | Programmer's Guide. | |
5329 | ||
5330 | FIXME: We do not recognize the full operand grammar defined in the MASM | |
5331 | documentation. In particular, all the structure/union and | |
5332 | high-level macro operands are missing. | |
5333 | ||
5334 | Uppercase words are terminals, lower case words are non-terminals. | |
5335 | Objects surrounded by double brackets '[[' ']]' are optional. Vertical | |
5336 | bars '|' denote choices. Most grammar productions are implemented in | |
5337 | functions called 'intel_<production>'. | |
5338 | ||
5339 | Initial production is 'expr'. | |
5340 | ||
0477af35 | 5341 | addOp + | - | & | \| | << | >> |
64a0c779 DN |
5342 | |
5343 | alpha [a-zA-Z] | |
5344 | ||
5345 | byteRegister AL | AH | BL | BH | CL | CH | DL | DH | |
5346 | ||
5347 | constant digits [[ radixOverride ]] | |
5348 | ||
5349 | dataType BYTE | WORD | DWORD | QWORD | XWORD | |
5350 | ||
5351 | digits decdigit | |
b77a7acd AJ |
5352 | | digits decdigit |
5353 | | digits hexdigit | |
64a0c779 DN |
5354 | |
5355 | decdigit [0-9] | |
5356 | ||
5357 | e05 e05 addOp e06 | |
b77a7acd | 5358 | | e06 |
64a0c779 DN |
5359 | |
5360 | e06 e06 mulOp e09 | |
b77a7acd | 5361 | | e09 |
64a0c779 DN |
5362 | |
5363 | e09 OFFSET e10 | |
5364 | | e09 PTR e10 | |
5365 | | e09 : e10 | |
5366 | | e10 | |
5367 | ||
5368 | e10 e10 [ expr ] | |
b77a7acd | 5369 | | e11 |
64a0c779 DN |
5370 | |
5371 | e11 ( expr ) | |
b77a7acd | 5372 | | [ expr ] |
64a0c779 DN |
5373 | | constant |
5374 | | dataType | |
5375 | | id | |
5376 | | $ | |
5377 | | register | |
0477af35 | 5378 | | ~ |
64a0c779 DN |
5379 | |
5380 | => expr SHORT e05 | |
b77a7acd | 5381 | | e05 |
64a0c779 DN |
5382 | |
5383 | gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX | |
b77a7acd | 5384 | | BP | EBP | SP | ESP | DI | EDI | SI | ESI |
64a0c779 DN |
5385 | |
5386 | hexdigit a | b | c | d | e | f | |
b77a7acd | 5387 | | A | B | C | D | E | F |
64a0c779 DN |
5388 | |
5389 | id alpha | |
b77a7acd | 5390 | | id alpha |
64a0c779 DN |
5391 | | id decdigit |
5392 | ||
5393 | mulOp * | / | MOD | |
5394 | ||
5395 | quote " | ' | |
5396 | ||
5397 | register specialRegister | |
b77a7acd | 5398 | | gpRegister |
64a0c779 DN |
5399 | | byteRegister |
5400 | ||
5401 | segmentRegister CS | DS | ES | FS | GS | SS | |
5402 | ||
5403 | specialRegister CR0 | CR2 | CR3 | |
b77a7acd | 5404 | | DR0 | DR1 | DR2 | DR3 | DR6 | DR7 |
64a0c779 DN |
5405 | | TR3 | TR4 | TR5 | TR6 | TR7 |
5406 | ||
64a0c779 DN |
5407 | We simplify the grammar in obvious places (e.g., register parsing is |
5408 | done by calling parse_register) and eliminate immediate left recursion | |
5409 | to implement a recursive-descent parser. | |
5410 | ||
5411 | expr SHORT e05 | |
b77a7acd | 5412 | | e05 |
64a0c779 DN |
5413 | |
5414 | e05 e06 e05' | |
5415 | ||
5416 | e05' addOp e06 e05' | |
b77a7acd | 5417 | | Empty |
64a0c779 DN |
5418 | |
5419 | e06 e09 e06' | |
5420 | ||
5421 | e06' mulOp e09 e06' | |
b77a7acd | 5422 | | Empty |
64a0c779 DN |
5423 | |
5424 | e09 OFFSET e10 e09' | |
b77a7acd | 5425 | | e10 e09' |
64a0c779 DN |
5426 | |
5427 | e09' PTR e10 e09' | |
b77a7acd | 5428 | | : e10 e09' |
64a0c779 DN |
5429 | | Empty |
5430 | ||
5431 | e10 e11 e10' | |
5432 | ||
5433 | e10' [ expr ] e10' | |
b77a7acd | 5434 | | Empty |
64a0c779 DN |
5435 | |
5436 | e11 ( expr ) | |
b77a7acd | 5437 | | [ expr ] |
64a0c779 DN |
5438 | | BYTE |
5439 | | WORD | |
5440 | | DWORD | |
5441 | | QWORD | |
5442 | | XWORD | |
5443 | | . | |
5444 | | $ | |
5445 | | register | |
5446 | | id | |
0477af35 | 5447 | | ~ |
64a0c779 DN |
5448 | | constant */ |
5449 | ||
5450 | /* Parsing structure for the intel syntax parser. Used to implement the | |
5451 | semantic actions for the operand grammar. */ | |
5452 | struct intel_parser_s | |
5453 | { | |
5454 | char *op_string; /* The string being parsed. */ | |
5455 | int got_a_float; /* Whether the operand is a float. */ | |
4a1805b1 | 5456 | int op_modifier; /* Operand modifier. */ |
64a0c779 DN |
5457 | int is_mem; /* 1 if operand is memory reference. */ |
5458 | const reg_entry *reg; /* Last register reference found. */ | |
5459 | char *disp; /* Displacement string being built. */ | |
5460 | }; | |
5461 | ||
5462 | static struct intel_parser_s intel_parser; | |
5463 | ||
5464 | /* Token structure for parsing intel syntax. */ | |
5465 | struct intel_token | |
5466 | { | |
5467 | int code; /* Token code. */ | |
5468 | const reg_entry *reg; /* Register entry for register tokens. */ | |
5469 | char *str; /* String representation. */ | |
5470 | }; | |
5471 | ||
5472 | static struct intel_token cur_token, prev_token; | |
5473 | ||
50705ef4 AM |
5474 | /* Token codes for the intel parser. Since T_SHORT is already used |
5475 | by COFF, undefine it first to prevent a warning. */ | |
64a0c779 DN |
5476 | #define T_NIL -1 |
5477 | #define T_CONST 1 | |
5478 | #define T_REG 2 | |
5479 | #define T_BYTE 3 | |
5480 | #define T_WORD 4 | |
5481 | #define T_DWORD 5 | |
5482 | #define T_QWORD 6 | |
5483 | #define T_XWORD 7 | |
50705ef4 | 5484 | #undef T_SHORT |
64a0c779 DN |
5485 | #define T_SHORT 8 |
5486 | #define T_OFFSET 9 | |
5487 | #define T_PTR 10 | |
5488 | #define T_ID 11 | |
0477af35 | 5489 | #define T_SHIFTOP 12 |
64a0c779 DN |
5490 | |
5491 | /* Prototypes for intel parser functions. */ | |
5492 | static int intel_match_token PARAMS ((int code)); | |
cce0cbdc DN |
5493 | static void intel_get_token PARAMS ((void)); |
5494 | static void intel_putback_token PARAMS ((void)); | |
5495 | static int intel_expr PARAMS ((void)); | |
5496 | static int intel_e05 PARAMS ((void)); | |
5497 | static int intel_e05_1 PARAMS ((void)); | |
5498 | static int intel_e06 PARAMS ((void)); | |
5499 | static int intel_e06_1 PARAMS ((void)); | |
5500 | static int intel_e09 PARAMS ((void)); | |
5501 | static int intel_e09_1 PARAMS ((void)); | |
5502 | static int intel_e10 PARAMS ((void)); | |
5503 | static int intel_e10_1 PARAMS ((void)); | |
5504 | static int intel_e11 PARAMS ((void)); | |
64a0c779 | 5505 | |
64a0c779 DN |
5506 | static int |
5507 | i386_intel_operand (operand_string, got_a_float) | |
5508 | char *operand_string; | |
5509 | int got_a_float; | |
5510 | { | |
5511 | int ret; | |
5512 | char *p; | |
5513 | ||
5514 | /* Initialize token holders. */ | |
5515 | cur_token.code = prev_token.code = T_NIL; | |
5516 | cur_token.reg = prev_token.reg = NULL; | |
5517 | cur_token.str = prev_token.str = NULL; | |
5518 | ||
5519 | /* Initialize parser structure. */ | |
e5cb08ac | 5520 | p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1); |
64a0c779 DN |
5521 | if (p == NULL) |
5522 | abort (); | |
5523 | strcpy (intel_parser.op_string, operand_string); | |
5524 | intel_parser.got_a_float = got_a_float; | |
5525 | intel_parser.op_modifier = -1; | |
5526 | intel_parser.is_mem = 0; | |
5527 | intel_parser.reg = NULL; | |
e5cb08ac | 5528 | intel_parser.disp = (char *) malloc (strlen (operand_string) + 1); |
64a0c779 DN |
5529 | if (intel_parser.disp == NULL) |
5530 | abort (); | |
5531 | intel_parser.disp[0] = '\0'; | |
5532 | ||
5533 | /* Read the first token and start the parser. */ | |
5534 | intel_get_token (); | |
5535 | ret = intel_expr (); | |
5536 | ||
5537 | if (ret) | |
5538 | { | |
5539 | /* If we found a memory reference, hand it over to i386_displacement | |
5540 | to fill in the rest of the operand fields. */ | |
5541 | if (intel_parser.is_mem) | |
5542 | { | |
5543 | if ((i.mem_operands == 1 | |
5544 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
5545 | || i.mem_operands == 2) | |
5546 | { | |
5547 | as_bad (_("too many memory references for '%s'"), | |
5548 | current_templates->start->name); | |
5549 | ret = 0; | |
5550 | } | |
5551 | else | |
5552 | { | |
5553 | char *s = intel_parser.disp; | |
5554 | i.mem_operands++; | |
5555 | ||
5556 | /* Add the displacement expression. */ | |
5557 | if (*s != '\0') | |
a4622f40 AM |
5558 | ret = i386_displacement (s, s + strlen (s)); |
5559 | if (ret) | |
5560 | ret = i386_index_check (operand_string); | |
64a0c779 DN |
5561 | } |
5562 | } | |
5563 | ||
5564 | /* Constant and OFFSET expressions are handled by i386_immediate. */ | |
5565 | else if (intel_parser.op_modifier == OFFSET_FLAT | |
5566 | || intel_parser.reg == NULL) | |
5567 | ret = i386_immediate (intel_parser.disp); | |
5568 | } | |
5569 | ||
5570 | free (p); | |
5571 | free (intel_parser.disp); | |
5572 | ||
5573 | return ret; | |
5574 | } | |
5575 | ||
64a0c779 | 5576 | /* expr SHORT e05 |
b77a7acd | 5577 | | e05 */ |
64a0c779 DN |
5578 | static int |
5579 | intel_expr () | |
5580 | { | |
5581 | /* expr SHORT e05 */ | |
5582 | if (cur_token.code == T_SHORT) | |
5583 | { | |
5584 | intel_parser.op_modifier = SHORT; | |
5585 | intel_match_token (T_SHORT); | |
5586 | ||
5587 | return (intel_e05 ()); | |
5588 | } | |
5589 | ||
5590 | /* expr e05 */ | |
5591 | else | |
5592 | return intel_e05 (); | |
5593 | } | |
5594 | ||
64a0c779 DN |
5595 | /* e05 e06 e05' |
5596 | ||
4a1805b1 | 5597 | e05' addOp e06 e05' |
64a0c779 DN |
5598 | | Empty */ |
5599 | static int | |
5600 | intel_e05 () | |
5601 | { | |
5602 | return (intel_e06 () && intel_e05_1 ()); | |
5603 | } | |
5604 | ||
5605 | static int | |
5606 | intel_e05_1 () | |
5607 | { | |
5608 | /* e05' addOp e06 e05' */ | |
0477af35 NC |
5609 | if (cur_token.code == '+' || cur_token.code == '-' |
5610 | || cur_token.code == '&' || cur_token.code == '|' | |
5611 | || cur_token.code == T_SHIFTOP) | |
64a0c779 DN |
5612 | { |
5613 | strcat (intel_parser.disp, cur_token.str); | |
5614 | intel_match_token (cur_token.code); | |
5615 | ||
5616 | return (intel_e06 () && intel_e05_1 ()); | |
5617 | } | |
5618 | ||
5619 | /* e05' Empty */ | |
5620 | else | |
5621 | return 1; | |
4a1805b1 | 5622 | } |
64a0c779 DN |
5623 | |
5624 | /* e06 e09 e06' | |
5625 | ||
5626 | e06' mulOp e09 e06' | |
b77a7acd | 5627 | | Empty */ |
64a0c779 DN |
5628 | static int |
5629 | intel_e06 () | |
5630 | { | |
5631 | return (intel_e09 () && intel_e06_1 ()); | |
5632 | } | |
5633 | ||
5634 | static int | |
5635 | intel_e06_1 () | |
5636 | { | |
5637 | /* e06' mulOp e09 e06' */ | |
5638 | if (cur_token.code == '*' || cur_token.code == '/') | |
5639 | { | |
5640 | strcat (intel_parser.disp, cur_token.str); | |
5641 | intel_match_token (cur_token.code); | |
5642 | ||
5643 | return (intel_e09 () && intel_e06_1 ()); | |
5644 | } | |
4a1805b1 | 5645 | |
64a0c779 | 5646 | /* e06' Empty */ |
4a1805b1 | 5647 | else |
64a0c779 DN |
5648 | return 1; |
5649 | } | |
5650 | ||
64a0c779 | 5651 | /* e09 OFFSET e10 e09' |
b77a7acd | 5652 | | e10 e09' |
64a0c779 DN |
5653 | |
5654 | e09' PTR e10 e09' | |
b77a7acd | 5655 | | : e10 e09' |
64a0c779 DN |
5656 | | Empty */ |
5657 | static int | |
5658 | intel_e09 () | |
5659 | { | |
5660 | /* e09 OFFSET e10 e09' */ | |
5661 | if (cur_token.code == T_OFFSET) | |
5662 | { | |
5663 | intel_parser.is_mem = 0; | |
5664 | intel_parser.op_modifier = OFFSET_FLAT; | |
5665 | intel_match_token (T_OFFSET); | |
5666 | ||
5667 | return (intel_e10 () && intel_e09_1 ()); | |
5668 | } | |
5669 | ||
5670 | /* e09 e10 e09' */ | |
5671 | else | |
5672 | return (intel_e10 () && intel_e09_1 ()); | |
5673 | } | |
5674 | ||
5675 | static int | |
5676 | intel_e09_1 () | |
5677 | { | |
5678 | /* e09' PTR e10 e09' */ | |
5679 | if (cur_token.code == T_PTR) | |
5680 | { | |
5681 | if (prev_token.code == T_BYTE) | |
5682 | i.suffix = BYTE_MNEM_SUFFIX; | |
5683 | ||
5684 | else if (prev_token.code == T_WORD) | |
5685 | { | |
5686 | if (intel_parser.got_a_float == 2) /* "fi..." */ | |
5687 | i.suffix = SHORT_MNEM_SUFFIX; | |
5688 | else | |
5689 | i.suffix = WORD_MNEM_SUFFIX; | |
5690 | } | |
5691 | ||
5692 | else if (prev_token.code == T_DWORD) | |
5693 | { | |
5694 | if (intel_parser.got_a_float == 1) /* "f..." */ | |
5695 | i.suffix = SHORT_MNEM_SUFFIX; | |
5696 | else | |
5697 | i.suffix = LONG_MNEM_SUFFIX; | |
5698 | } | |
5699 | ||
5700 | else if (prev_token.code == T_QWORD) | |
f16b83df JH |
5701 | { |
5702 | if (intel_parser.got_a_float == 1) /* "f..." */ | |
5703 | i.suffix = LONG_MNEM_SUFFIX; | |
5704 | else | |
3e73aa7c | 5705 | i.suffix = QWORD_MNEM_SUFFIX; |
f16b83df | 5706 | } |
64a0c779 DN |
5707 | |
5708 | else if (prev_token.code == T_XWORD) | |
5709 | i.suffix = LONG_DOUBLE_MNEM_SUFFIX; | |
5710 | ||
5711 | else | |
5712 | { | |
0477af35 | 5713 | as_bad (_("Unknown operand modifier `%s'"), prev_token.str); |
64a0c779 DN |
5714 | return 0; |
5715 | } | |
5716 | ||
5717 | intel_match_token (T_PTR); | |
5718 | ||
5719 | return (intel_e10 () && intel_e09_1 ()); | |
5720 | } | |
5721 | ||
5722 | /* e09 : e10 e09' */ | |
5723 | else if (cur_token.code == ':') | |
5724 | { | |
21d6c4af DN |
5725 | /* Mark as a memory operand only if it's not already known to be an |
5726 | offset expression. */ | |
5727 | if (intel_parser.op_modifier != OFFSET_FLAT) | |
5728 | intel_parser.is_mem = 1; | |
64a0c779 DN |
5729 | |
5730 | return (intel_match_token (':') && intel_e10 () && intel_e09_1 ()); | |
5731 | } | |
5732 | ||
5733 | /* e09' Empty */ | |
5734 | else | |
5735 | return 1; | |
5736 | } | |
5737 | ||
5738 | /* e10 e11 e10' | |
5739 | ||
5740 | e10' [ expr ] e10' | |
b77a7acd | 5741 | | Empty */ |
64a0c779 DN |
5742 | static int |
5743 | intel_e10 () | |
5744 | { | |
5745 | return (intel_e11 () && intel_e10_1 ()); | |
5746 | } | |
5747 | ||
5748 | static int | |
5749 | intel_e10_1 () | |
5750 | { | |
5751 | /* e10' [ expr ] e10' */ | |
5752 | if (cur_token.code == '[') | |
5753 | { | |
5754 | intel_match_token ('['); | |
21d6c4af DN |
5755 | |
5756 | /* Mark as a memory operand only if it's not already known to be an | |
5757 | offset expression. If it's an offset expression, we need to keep | |
5758 | the brace in. */ | |
5759 | if (intel_parser.op_modifier != OFFSET_FLAT) | |
5760 | intel_parser.is_mem = 1; | |
5761 | else | |
5762 | strcat (intel_parser.disp, "["); | |
4a1805b1 | 5763 | |
64a0c779 | 5764 | /* Add a '+' to the displacement string if necessary. */ |
21d6c4af DN |
5765 | if (*intel_parser.disp != '\0' |
5766 | && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') | |
64a0c779 DN |
5767 | strcat (intel_parser.disp, "+"); |
5768 | ||
21d6c4af DN |
5769 | if (intel_expr () && intel_match_token (']')) |
5770 | { | |
5771 | /* Preserve brackets when the operand is an offset expression. */ | |
5772 | if (intel_parser.op_modifier == OFFSET_FLAT) | |
5773 | strcat (intel_parser.disp, "]"); | |
5774 | ||
5775 | return intel_e10_1 (); | |
5776 | } | |
5777 | else | |
5778 | return 0; | |
64a0c779 DN |
5779 | } |
5780 | ||
5781 | /* e10' Empty */ | |
5782 | else | |
5783 | return 1; | |
5784 | } | |
5785 | ||
64a0c779 | 5786 | /* e11 ( expr ) |
b77a7acd | 5787 | | [ expr ] |
64a0c779 DN |
5788 | | BYTE |
5789 | | WORD | |
5790 | | DWORD | |
5791 | | QWORD | |
5792 | | XWORD | |
4a1805b1 | 5793 | | $ |
64a0c779 DN |
5794 | | . |
5795 | | register | |
5796 | | id | |
0477af35 | 5797 | | ~ |
64a0c779 DN |
5798 | | constant */ |
5799 | static int | |
5800 | intel_e11 () | |
5801 | { | |
5802 | /* e11 ( expr ) */ | |
5803 | if (cur_token.code == '(') | |
5804 | { | |
5805 | intel_match_token ('('); | |
5806 | strcat (intel_parser.disp, "("); | |
5807 | ||
5808 | if (intel_expr () && intel_match_token (')')) | |
e5cb08ac KH |
5809 | { |
5810 | strcat (intel_parser.disp, ")"); | |
5811 | return 1; | |
5812 | } | |
64a0c779 DN |
5813 | else |
5814 | return 0; | |
5815 | } | |
5816 | ||
0477af35 NC |
5817 | /* e11 ~ expr */ |
5818 | else if (cur_token.code == '~') | |
5819 | { | |
5820 | strcat (intel_parser.disp, "~"); | |
5821 | intel_match_token ('~'); | |
5822 | ||
5823 | return (intel_e11 ()); | |
5824 | } | |
5825 | ||
64a0c779 DN |
5826 | /* e11 [ expr ] */ |
5827 | else if (cur_token.code == '[') | |
5828 | { | |
5829 | intel_match_token ('['); | |
21d6c4af DN |
5830 | |
5831 | /* Mark as a memory operand only if it's not already known to be an | |
5832 | offset expression. If it's an offset expression, we need to keep | |
5833 | the brace in. */ | |
5834 | if (intel_parser.op_modifier != OFFSET_FLAT) | |
5835 | intel_parser.is_mem = 1; | |
5836 | else | |
5837 | strcat (intel_parser.disp, "["); | |
4a1805b1 | 5838 | |
64a0c779 DN |
5839 | /* Operands for jump/call inside brackets denote absolute addresses. */ |
5840 | if (current_templates->start->opcode_modifier & Jump | |
5841 | || current_templates->start->opcode_modifier & JumpDword | |
5842 | || current_templates->start->opcode_modifier & JumpByte | |
5843 | || current_templates->start->opcode_modifier & JumpInterSegment) | |
5844 | i.types[this_operand] |= JumpAbsolute; | |
5845 | ||
5846 | /* Add a '+' to the displacement string if necessary. */ | |
21d6c4af DN |
5847 | if (*intel_parser.disp != '\0' |
5848 | && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') | |
64a0c779 DN |
5849 | strcat (intel_parser.disp, "+"); |
5850 | ||
21d6c4af DN |
5851 | if (intel_expr () && intel_match_token (']')) |
5852 | { | |
5853 | /* Preserve brackets when the operand is an offset expression. */ | |
5854 | if (intel_parser.op_modifier == OFFSET_FLAT) | |
5855 | strcat (intel_parser.disp, "]"); | |
5856 | ||
5857 | return 1; | |
5858 | } | |
5859 | else | |
5860 | return 0; | |
64a0c779 DN |
5861 | } |
5862 | ||
4a1805b1 | 5863 | /* e11 BYTE |
64a0c779 DN |
5864 | | WORD |
5865 | | DWORD | |
5866 | | QWORD | |
5867 | | XWORD */ | |
5868 | else if (cur_token.code == T_BYTE | |
5869 | || cur_token.code == T_WORD | |
5870 | || cur_token.code == T_DWORD | |
5871 | || cur_token.code == T_QWORD | |
5872 | || cur_token.code == T_XWORD) | |
5873 | { | |
5874 | intel_match_token (cur_token.code); | |
5875 | ||
5876 | return 1; | |
5877 | } | |
5878 | ||
5879 | /* e11 $ | |
5880 | | . */ | |
5881 | else if (cur_token.code == '$' || cur_token.code == '.') | |
5882 | { | |
5883 | strcat (intel_parser.disp, cur_token.str); | |
5884 | intel_match_token (cur_token.code); | |
21d6c4af DN |
5885 | |
5886 | /* Mark as a memory operand only if it's not already known to be an | |
5887 | offset expression. */ | |
5888 | if (intel_parser.op_modifier != OFFSET_FLAT) | |
5889 | intel_parser.is_mem = 1; | |
64a0c779 DN |
5890 | |
5891 | return 1; | |
5892 | } | |
5893 | ||
5894 | /* e11 register */ | |
5895 | else if (cur_token.code == T_REG) | |
5896 | { | |
5897 | const reg_entry *reg = intel_parser.reg = cur_token.reg; | |
5898 | ||
5899 | intel_match_token (T_REG); | |
5900 | ||
5901 | /* Check for segment change. */ | |
5902 | if (cur_token.code == ':') | |
5903 | { | |
5904 | if (reg->reg_type & (SReg2 | SReg3)) | |
5905 | { | |
5906 | switch (reg->reg_num) | |
5907 | { | |
5908 | case 0: | |
5909 | i.seg[i.mem_operands] = &es; | |
5910 | break; | |
5911 | case 1: | |
5912 | i.seg[i.mem_operands] = &cs; | |
5913 | break; | |
5914 | case 2: | |
5915 | i.seg[i.mem_operands] = &ss; | |
5916 | break; | |
5917 | case 3: | |
5918 | i.seg[i.mem_operands] = &ds; | |
5919 | break; | |
5920 | case 4: | |
5921 | i.seg[i.mem_operands] = &fs; | |
5922 | break; | |
5923 | case 5: | |
5924 | i.seg[i.mem_operands] = &gs; | |
5925 | break; | |
5926 | } | |
5927 | } | |
5928 | else | |
5929 | { | |
5930 | as_bad (_("`%s' is not a valid segment register"), reg->reg_name); | |
5931 | return 0; | |
5932 | } | |
5933 | } | |
5934 | ||
5935 | /* Not a segment register. Check for register scaling. */ | |
5936 | else if (cur_token.code == '*') | |
5937 | { | |
5938 | if (!intel_parser.is_mem) | |
5939 | { | |
5940 | as_bad (_("Register scaling only allowed in memory operands.")); | |
5941 | return 0; | |
5942 | } | |
5943 | ||
4a1805b1 | 5944 | /* What follows must be a valid scale. */ |
64a0c779 DN |
5945 | if (intel_match_token ('*') |
5946 | && strchr ("01248", *cur_token.str)) | |
5947 | { | |
5948 | i.index_reg = reg; | |
5949 | i.types[this_operand] |= BaseIndex; | |
5950 | ||
5951 | /* Set the scale after setting the register (otherwise, | |
5952 | i386_scale will complain) */ | |
5953 | i386_scale (cur_token.str); | |
5954 | intel_match_token (T_CONST); | |
5955 | } | |
5956 | else | |
5957 | { | |
5958 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
5959 | cur_token.str); | |
5960 | return 0; | |
5961 | } | |
5962 | } | |
5963 | ||
5964 | /* No scaling. If this is a memory operand, the register is either a | |
5965 | base register (first occurrence) or an index register (second | |
5966 | occurrence). */ | |
5967 | else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3))) | |
5968 | { | |
5969 | if (i.base_reg && i.index_reg) | |
5970 | { | |
0477af35 | 5971 | as_bad (_("Too many register references in memory operand.")); |
64a0c779 DN |
5972 | return 0; |
5973 | } | |
5974 | ||
5975 | if (i.base_reg == NULL) | |
5976 | i.base_reg = reg; | |
5977 | else | |
5978 | i.index_reg = reg; | |
5979 | ||
5980 | i.types[this_operand] |= BaseIndex; | |
5981 | } | |
5982 | ||
5983 | /* Offset modifier. Add the register to the displacement string to be | |
5984 | parsed as an immediate expression after we're done. */ | |
5985 | else if (intel_parser.op_modifier == OFFSET_FLAT) | |
5986 | strcat (intel_parser.disp, reg->reg_name); | |
4a1805b1 | 5987 | |
64a0c779 DN |
5988 | /* It's neither base nor index nor offset. */ |
5989 | else | |
5990 | { | |
5991 | i.types[this_operand] |= reg->reg_type & ~BaseIndex; | |
5992 | i.op[this_operand].regs = reg; | |
5993 | i.reg_operands++; | |
5994 | } | |
5995 | ||
5996 | /* Since registers are not part of the displacement string (except | |
5997 | when we're parsing offset operands), we may need to remove any | |
5998 | preceding '+' from the displacement string. */ | |
5999 | if (*intel_parser.disp != '\0' | |
6000 | && intel_parser.op_modifier != OFFSET_FLAT) | |
6001 | { | |
6002 | char *s = intel_parser.disp; | |
6003 | s += strlen (s) - 1; | |
6004 | if (*s == '+') | |
6005 | *s = '\0'; | |
6006 | } | |
6007 | ||
6008 | return 1; | |
6009 | } | |
4a1805b1 | 6010 | |
64a0c779 DN |
6011 | /* e11 id */ |
6012 | else if (cur_token.code == T_ID) | |
6013 | { | |
6014 | /* Add the identifier to the displacement string. */ | |
6015 | strcat (intel_parser.disp, cur_token.str); | |
6016 | intel_match_token (T_ID); | |
6017 | ||
6018 | /* The identifier represents a memory reference only if it's not | |
6019 | preceded by an offset modifier. */ | |
21d6c4af | 6020 | if (intel_parser.op_modifier != OFFSET_FLAT) |
64a0c779 DN |
6021 | intel_parser.is_mem = 1; |
6022 | ||
6023 | return 1; | |
6024 | } | |
6025 | ||
6026 | /* e11 constant */ | |
6027 | else if (cur_token.code == T_CONST | |
e5cb08ac | 6028 | || cur_token.code == '-' |
64a0c779 DN |
6029 | || cur_token.code == '+') |
6030 | { | |
6031 | char *save_str; | |
6032 | ||
6033 | /* Allow constants that start with `+' or `-'. */ | |
6034 | if (cur_token.code == '-' || cur_token.code == '+') | |
6035 | { | |
6036 | strcat (intel_parser.disp, cur_token.str); | |
6037 | intel_match_token (cur_token.code); | |
6038 | if (cur_token.code != T_CONST) | |
6039 | { | |
0477af35 | 6040 | as_bad (_("Syntax error. Expecting a constant. Got `%s'."), |
64a0c779 DN |
6041 | cur_token.str); |
6042 | return 0; | |
6043 | } | |
6044 | } | |
6045 | ||
e5cb08ac | 6046 | save_str = (char *) malloc (strlen (cur_token.str) + 1); |
64a0c779 | 6047 | if (save_str == NULL) |
bc805888 | 6048 | abort (); |
64a0c779 DN |
6049 | strcpy (save_str, cur_token.str); |
6050 | ||
6051 | /* Get the next token to check for register scaling. */ | |
6052 | intel_match_token (cur_token.code); | |
6053 | ||
6054 | /* Check if this constant is a scaling factor for an index register. */ | |
6055 | if (cur_token.code == '*') | |
6056 | { | |
6057 | if (intel_match_token ('*') && cur_token.code == T_REG) | |
6058 | { | |
6059 | if (!intel_parser.is_mem) | |
6060 | { | |
6061 | as_bad (_("Register scaling only allowed in memory operands.")); | |
6062 | return 0; | |
6063 | } | |
6064 | ||
4a1805b1 | 6065 | /* The constant is followed by `* reg', so it must be |
64a0c779 DN |
6066 | a valid scale. */ |
6067 | if (strchr ("01248", *save_str)) | |
6068 | { | |
6069 | i.index_reg = cur_token.reg; | |
6070 | i.types[this_operand] |= BaseIndex; | |
6071 | ||
6072 | /* Set the scale after setting the register (otherwise, | |
6073 | i386_scale will complain) */ | |
6074 | i386_scale (save_str); | |
6075 | intel_match_token (T_REG); | |
6076 | ||
6077 | /* Since registers are not part of the displacement | |
6078 | string, we may need to remove any preceding '+' from | |
6079 | the displacement string. */ | |
6080 | if (*intel_parser.disp != '\0') | |
6081 | { | |
6082 | char *s = intel_parser.disp; | |
6083 | s += strlen (s) - 1; | |
6084 | if (*s == '+') | |
6085 | *s = '\0'; | |
6086 | } | |
6087 | ||
6088 | free (save_str); | |
6089 | ||
6090 | return 1; | |
6091 | } | |
6092 | else | |
6093 | return 0; | |
6094 | } | |
6095 | ||
6096 | /* The constant was not used for register scaling. Since we have | |
6097 | already consumed the token following `*' we now need to put it | |
6098 | back in the stream. */ | |
6099 | else | |
6100 | intel_putback_token (); | |
6101 | } | |
6102 | ||
6103 | /* Add the constant to the displacement string. */ | |
6104 | strcat (intel_parser.disp, save_str); | |
6105 | free (save_str); | |
6106 | ||
6107 | return 1; | |
6108 | } | |
6109 | ||
64a0c779 DN |
6110 | as_bad (_("Unrecognized token '%s'"), cur_token.str); |
6111 | return 0; | |
6112 | } | |
6113 | ||
64a0c779 DN |
6114 | /* Match the given token against cur_token. If they match, read the next |
6115 | token from the operand string. */ | |
6116 | static int | |
6117 | intel_match_token (code) | |
e5cb08ac | 6118 | int code; |
64a0c779 DN |
6119 | { |
6120 | if (cur_token.code == code) | |
6121 | { | |
6122 | intel_get_token (); | |
6123 | return 1; | |
6124 | } | |
6125 | else | |
6126 | { | |
0477af35 | 6127 | as_bad (_("Unexpected token `%s'"), cur_token.str); |
64a0c779 DN |
6128 | return 0; |
6129 | } | |
6130 | } | |
6131 | ||
64a0c779 DN |
6132 | /* Read a new token from intel_parser.op_string and store it in cur_token. */ |
6133 | static void | |
6134 | intel_get_token () | |
6135 | { | |
6136 | char *end_op; | |
6137 | const reg_entry *reg; | |
6138 | struct intel_token new_token; | |
6139 | ||
6140 | new_token.code = T_NIL; | |
6141 | new_token.reg = NULL; | |
6142 | new_token.str = NULL; | |
6143 | ||
4a1805b1 | 6144 | /* Free the memory allocated to the previous token and move |
64a0c779 DN |
6145 | cur_token to prev_token. */ |
6146 | if (prev_token.str) | |
6147 | free (prev_token.str); | |
6148 | ||
6149 | prev_token = cur_token; | |
6150 | ||
6151 | /* Skip whitespace. */ | |
6152 | while (is_space_char (*intel_parser.op_string)) | |
6153 | intel_parser.op_string++; | |
6154 | ||
6155 | /* Return an empty token if we find nothing else on the line. */ | |
6156 | if (*intel_parser.op_string == '\0') | |
6157 | { | |
6158 | cur_token = new_token; | |
6159 | return; | |
6160 | } | |
6161 | ||
6162 | /* The new token cannot be larger than the remainder of the operand | |
6163 | string. */ | |
e5cb08ac | 6164 | new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1); |
64a0c779 | 6165 | if (new_token.str == NULL) |
bc805888 | 6166 | abort (); |
64a0c779 DN |
6167 | new_token.str[0] = '\0'; |
6168 | ||
6169 | if (strchr ("0123456789", *intel_parser.op_string)) | |
6170 | { | |
6171 | char *p = new_token.str; | |
6172 | char *q = intel_parser.op_string; | |
6173 | new_token.code = T_CONST; | |
6174 | ||
6175 | /* Allow any kind of identifier char to encompass floating point and | |
6176 | hexadecimal numbers. */ | |
6177 | while (is_identifier_char (*q)) | |
6178 | *p++ = *q++; | |
6179 | *p = '\0'; | |
6180 | ||
6181 | /* Recognize special symbol names [0-9][bf]. */ | |
6182 | if (strlen (intel_parser.op_string) == 2 | |
4a1805b1 | 6183 | && (intel_parser.op_string[1] == 'b' |
64a0c779 DN |
6184 | || intel_parser.op_string[1] == 'f')) |
6185 | new_token.code = T_ID; | |
6186 | } | |
6187 | ||
0477af35 NC |
6188 | else if (strchr ("<>", *intel_parser.op_string) |
6189 | && *intel_parser.op_string == *(intel_parser.op_string + 1)) | |
6190 | { | |
6191 | new_token.code = T_SHIFTOP; | |
6192 | new_token.str[0] = *intel_parser.op_string; | |
6193 | new_token.str[1] = *intel_parser.op_string; | |
6194 | new_token.str[2] = '\0'; | |
6195 | } | |
6196 | ||
6197 | else if (strchr ("+-/*&|:[]()~", *intel_parser.op_string)) | |
64a0c779 DN |
6198 | { |
6199 | new_token.code = *intel_parser.op_string; | |
6200 | new_token.str[0] = *intel_parser.op_string; | |
6201 | new_token.str[1] = '\0'; | |
6202 | } | |
6203 | ||
6204 | else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg) | |
6205 | && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)) | |
6206 | { | |
6207 | new_token.code = T_REG; | |
6208 | new_token.reg = reg; | |
6209 | ||
6210 | if (*intel_parser.op_string == REGISTER_PREFIX) | |
6211 | { | |
6212 | new_token.str[0] = REGISTER_PREFIX; | |
6213 | new_token.str[1] = '\0'; | |
6214 | } | |
6215 | ||
6216 | strcat (new_token.str, reg->reg_name); | |
6217 | } | |
6218 | ||
6219 | else if (is_identifier_char (*intel_parser.op_string)) | |
6220 | { | |
6221 | char *p = new_token.str; | |
6222 | char *q = intel_parser.op_string; | |
6223 | ||
6224 | /* A '.' or '$' followed by an identifier char is an identifier. | |
6225 | Otherwise, it's operator '.' followed by an expression. */ | |
6226 | if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1))) | |
6227 | { | |
6228 | new_token.code = *q; | |
6229 | new_token.str[0] = *q; | |
6230 | new_token.str[1] = '\0'; | |
6231 | } | |
6232 | else | |
6233 | { | |
6234 | while (is_identifier_char (*q) || *q == '@') | |
6235 | *p++ = *q++; | |
6236 | *p = '\0'; | |
6237 | ||
6238 | if (strcasecmp (new_token.str, "BYTE") == 0) | |
6239 | new_token.code = T_BYTE; | |
6240 | ||
6241 | else if (strcasecmp (new_token.str, "WORD") == 0) | |
6242 | new_token.code = T_WORD; | |
6243 | ||
6244 | else if (strcasecmp (new_token.str, "DWORD") == 0) | |
6245 | new_token.code = T_DWORD; | |
6246 | ||
6247 | else if (strcasecmp (new_token.str, "QWORD") == 0) | |
6248 | new_token.code = T_QWORD; | |
6249 | ||
6250 | else if (strcasecmp (new_token.str, "XWORD") == 0) | |
6251 | new_token.code = T_XWORD; | |
6252 | ||
6253 | else if (strcasecmp (new_token.str, "PTR") == 0) | |
6254 | new_token.code = T_PTR; | |
6255 | ||
6256 | else if (strcasecmp (new_token.str, "SHORT") == 0) | |
6257 | new_token.code = T_SHORT; | |
6258 | ||
6259 | else if (strcasecmp (new_token.str, "OFFSET") == 0) | |
6260 | { | |
6261 | new_token.code = T_OFFSET; | |
6262 | ||
6263 | /* ??? This is not mentioned in the MASM grammar but gcc | |
6264 | makes use of it with -mintel-syntax. OFFSET may be | |
6265 | followed by FLAT: */ | |
6266 | if (strncasecmp (q, " FLAT:", 6) == 0) | |
6267 | strcat (new_token.str, " FLAT:"); | |
6268 | } | |
6269 | ||
6270 | /* ??? This is not mentioned in the MASM grammar. */ | |
6271 | else if (strcasecmp (new_token.str, "FLAT") == 0) | |
6272 | new_token.code = T_OFFSET; | |
6273 | ||
6274 | else | |
6275 | new_token.code = T_ID; | |
6276 | } | |
6277 | } | |
6278 | ||
6279 | else | |
0477af35 | 6280 | as_bad (_("Unrecognized token `%s'"), intel_parser.op_string); |
64a0c779 DN |
6281 | |
6282 | intel_parser.op_string += strlen (new_token.str); | |
6283 | cur_token = new_token; | |
6284 | } | |
6285 | ||
64a0c779 DN |
6286 | /* Put cur_token back into the token stream and make cur_token point to |
6287 | prev_token. */ | |
6288 | static void | |
6289 | intel_putback_token () | |
6290 | { | |
6291 | intel_parser.op_string -= strlen (cur_token.str); | |
6292 | free (cur_token.str); | |
6293 | cur_token = prev_token; | |
4a1805b1 | 6294 | |
64a0c779 DN |
6295 | /* Forget prev_token. */ |
6296 | prev_token.code = T_NIL; | |
6297 | prev_token.reg = NULL; | |
6298 | prev_token.str = NULL; | |
6299 | } | |
54cfded0 | 6300 | |
a4447b93 | 6301 | int |
54cfded0 AM |
6302 | tc_x86_regname_to_dw2regnum (const char *regname) |
6303 | { | |
6304 | unsigned int regnum; | |
6305 | unsigned int regnames_count; | |
6306 | char *regnames_32[] = | |
6307 | { | |
a4447b93 RH |
6308 | "eax", "ecx", "edx", "ebx", |
6309 | "esp", "ebp", "esi", "edi", | |
54cfded0 AM |
6310 | "eip" |
6311 | }; | |
6312 | char *regnames_64[] = | |
6313 | { | |
6314 | "rax", "rbx", "rcx", "rdx", | |
6315 | "rdi", "rsi", "rbp", "rsp", | |
6316 | "r8", "r9", "r10", "r11", | |
6317 | "r12", "r13", "r14", "r15", | |
6318 | "rip" | |
6319 | }; | |
6320 | char **regnames; | |
6321 | ||
6322 | if (flag_code == CODE_64BIT) | |
6323 | { | |
6324 | regnames = regnames_64; | |
0cea6190 | 6325 | regnames_count = ARRAY_SIZE (regnames_64); |
54cfded0 AM |
6326 | } |
6327 | else | |
6328 | { | |
6329 | regnames = regnames_32; | |
0cea6190 | 6330 | regnames_count = ARRAY_SIZE (regnames_32); |
54cfded0 AM |
6331 | } |
6332 | ||
6333 | for (regnum = 0; regnum < regnames_count; regnum++) | |
6334 | if (strcmp (regname, regnames[regnum]) == 0) | |
6335 | return regnum; | |
6336 | ||
54cfded0 AM |
6337 | return -1; |
6338 | } | |
6339 | ||
6340 | void | |
6341 | tc_x86_frame_initial_instructions (void) | |
6342 | { | |
a4447b93 RH |
6343 | static unsigned int sp_regno; |
6344 | ||
6345 | if (!sp_regno) | |
6346 | sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT | |
6347 | ? "rsp" : "esp"); | |
6348 | ||
6349 | cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment); | |
6350 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 6351 | } |
d2b2c203 DJ |
6352 | |
6353 | int | |
6354 | i386_elf_section_type (const char *str, size_t len) | |
6355 | { | |
6356 | if (flag_code == CODE_64BIT | |
6357 | && len == sizeof ("unwind") - 1 | |
6358 | && strncmp (str, "unwind", 6) == 0) | |
6359 | return SHT_X86_64_UNWIND; | |
6360 | ||
6361 | return -1; | |
6362 | } |