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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
82704155 | 2 | Copyright (C) 1989-2019 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
d2b2c203 | 33 | #include "elf/x86-64.h" |
40fb9820 | 34 | #include "opcodes/i386-init.h" |
252b5132 | 35 | |
41fd2579 L |
36 | #ifdef HAVE_LIMITS_H |
37 | #include <limits.h> | |
38 | #else | |
39 | #ifdef HAVE_SYS_PARAM_H | |
40 | #include <sys/param.h> | |
41 | #endif | |
42 | #ifndef INT_MAX | |
43 | #define INT_MAX (int) (((unsigned) (-1)) >> 1) | |
44 | #endif | |
45 | #endif | |
46 | ||
252b5132 RH |
47 | #ifndef REGISTER_WARNINGS |
48 | #define REGISTER_WARNINGS 1 | |
49 | #endif | |
50 | ||
c3332e24 | 51 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 52 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
53 | #endif |
54 | ||
29b0f896 AM |
55 | #ifndef DEFAULT_ARCH |
56 | #define DEFAULT_ARCH "i386" | |
246fcdee | 57 | #endif |
252b5132 | 58 | |
edde18a5 AM |
59 | #ifndef INLINE |
60 | #if __GNUC__ >= 2 | |
61 | #define INLINE __inline__ | |
62 | #else | |
63 | #define INLINE | |
64 | #endif | |
65 | #endif | |
66 | ||
6305a203 L |
67 | /* Prefixes will be emitted in the order defined below. |
68 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
69 | instruction, and so must come before any prefixes. | |
70 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 71 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
72 | #define WAIT_PREFIX 0 |
73 | #define SEG_PREFIX 1 | |
74 | #define ADDR_PREFIX 2 | |
75 | #define DATA_PREFIX 3 | |
c32fa91d | 76 | #define REP_PREFIX 4 |
42164a71 | 77 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 78 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 79 | #define LOCK_PREFIX 5 |
4e9ac44a L |
80 | #define REX_PREFIX 6 /* must come last. */ |
81 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
82 | |
83 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
84 | #define REGISTER_PREFIX '%' | |
85 | #define IMMEDIATE_PREFIX '$' | |
86 | #define ABSOLUTE_PREFIX '*' | |
87 | ||
88 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
89 | memory operand size in Intel syntax. */ | |
90 | #define WORD_MNEM_SUFFIX 'w' | |
91 | #define BYTE_MNEM_SUFFIX 'b' | |
92 | #define SHORT_MNEM_SUFFIX 's' | |
93 | #define LONG_MNEM_SUFFIX 'l' | |
94 | #define QWORD_MNEM_SUFFIX 'q' | |
6305a203 L |
95 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
96 | in instructions. */ | |
97 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
98 | ||
99 | #define END_OF_INSN '\0' | |
100 | ||
79dec6b7 JB |
101 | /* This matches the C -> StaticRounding alias in the opcode table. */ |
102 | #define commutative staticrounding | |
103 | ||
6305a203 L |
104 | /* |
105 | 'templates' is for grouping together 'template' structures for opcodes | |
106 | of the same name. This is only used for storing the insns in the grand | |
107 | ole hash table of insns. | |
108 | The templates themselves start at START and range up to (but not including) | |
109 | END. | |
110 | */ | |
111 | typedef struct | |
112 | { | |
d3ce72d0 NC |
113 | const insn_template *start; |
114 | const insn_template *end; | |
6305a203 L |
115 | } |
116 | templates; | |
117 | ||
118 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
119 | typedef struct | |
120 | { | |
121 | unsigned int regmem; /* codes register or memory operand */ | |
122 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
123 | unsigned int mode; /* how to interpret regmem & reg */ | |
124 | } | |
125 | modrm_byte; | |
126 | ||
127 | /* x86-64 extension prefix. */ | |
128 | typedef int rex_byte; | |
129 | ||
6305a203 L |
130 | /* 386 opcode byte to code indirect addressing. */ |
131 | typedef struct | |
132 | { | |
133 | unsigned base; | |
134 | unsigned index; | |
135 | unsigned scale; | |
136 | } | |
137 | sib_byte; | |
138 | ||
6305a203 L |
139 | /* x86 arch names, types and features */ |
140 | typedef struct | |
141 | { | |
142 | const char *name; /* arch name */ | |
8a2c8fef | 143 | unsigned int len; /* arch string length */ |
6305a203 L |
144 | enum processor_type type; /* arch type */ |
145 | i386_cpu_flags flags; /* cpu feature flags */ | |
8a2c8fef | 146 | unsigned int skip; /* show_arch should skip this. */ |
6305a203 L |
147 | } |
148 | arch_entry; | |
149 | ||
293f5f65 L |
150 | /* Used to turn off indicated flags. */ |
151 | typedef struct | |
152 | { | |
153 | const char *name; /* arch name */ | |
154 | unsigned int len; /* arch string length */ | |
155 | i386_cpu_flags flags; /* cpu feature flags */ | |
156 | } | |
157 | noarch_entry; | |
158 | ||
78f12dd3 | 159 | static void update_code_flag (int, int); |
e3bb37b5 L |
160 | static void set_code_flag (int); |
161 | static void set_16bit_gcc_code_flag (int); | |
162 | static void set_intel_syntax (int); | |
1efbbeb4 | 163 | static void set_intel_mnemonic (int); |
db51cc60 | 164 | static void set_allow_index_reg (int); |
7bab8ab5 | 165 | static void set_check (int); |
e3bb37b5 | 166 | static void set_cpu_arch (int); |
6482c264 | 167 | #ifdef TE_PE |
e3bb37b5 | 168 | static void pe_directive_secrel (int); |
6482c264 | 169 | #endif |
e3bb37b5 L |
170 | static void signed_cons (int); |
171 | static char *output_invalid (int c); | |
ee86248c JB |
172 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
173 | const char *); | |
174 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
175 | const char *); | |
a7619375 | 176 | static int i386_att_operand (char *); |
e3bb37b5 | 177 | static int i386_intel_operand (char *, int); |
ee86248c JB |
178 | static int i386_intel_simplify (expressionS *); |
179 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
180 | static const reg_entry *parse_register (char *, char **); |
181 | static char *parse_insn (char *, char *); | |
182 | static char *parse_operands (char *, const char *); | |
183 | static void swap_operands (void); | |
4d456e3d | 184 | static void swap_2_operands (int, int); |
e3bb37b5 L |
185 | static void optimize_imm (void); |
186 | static void optimize_disp (void); | |
83b16ac6 | 187 | static const insn_template *match_template (char); |
e3bb37b5 L |
188 | static int check_string (void); |
189 | static int process_suffix (void); | |
190 | static int check_byte_reg (void); | |
191 | static int check_long_reg (void); | |
192 | static int check_qword_reg (void); | |
193 | static int check_word_reg (void); | |
194 | static int finalize_imm (void); | |
195 | static int process_operands (void); | |
196 | static const seg_entry *build_modrm_byte (void); | |
197 | static void output_insn (void); | |
198 | static void output_imm (fragS *, offsetT); | |
199 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 200 | #ifndef I386COFF |
e3bb37b5 | 201 | static void s_bss (int); |
252b5132 | 202 | #endif |
17d4e2a2 L |
203 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
204 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
b4a3a7b4 L |
205 | |
206 | /* GNU_PROPERTY_X86_ISA_1_USED. */ | |
207 | static unsigned int x86_isa_1_used; | |
208 | /* GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
209 | static unsigned int x86_feature_2_used; | |
210 | /* Generate x86 used ISA and feature properties. */ | |
211 | static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE; | |
17d4e2a2 | 212 | #endif |
252b5132 | 213 | |
a847613f | 214 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 215 | |
43234a1e L |
216 | /* This struct describes rounding control and SAE in the instruction. */ |
217 | struct RC_Operation | |
218 | { | |
219 | enum rc_type | |
220 | { | |
221 | rne = 0, | |
222 | rd, | |
223 | ru, | |
224 | rz, | |
225 | saeonly | |
226 | } type; | |
227 | int operand; | |
228 | }; | |
229 | ||
230 | static struct RC_Operation rc_op; | |
231 | ||
232 | /* The struct describes masking, applied to OPERAND in the instruction. | |
233 | MASK is a pointer to the corresponding mask register. ZEROING tells | |
234 | whether merging or zeroing mask is used. */ | |
235 | struct Mask_Operation | |
236 | { | |
237 | const reg_entry *mask; | |
238 | unsigned int zeroing; | |
239 | /* The operand where this operation is associated. */ | |
240 | int operand; | |
241 | }; | |
242 | ||
243 | static struct Mask_Operation mask_op; | |
244 | ||
245 | /* The struct describes broadcasting, applied to OPERAND. FACTOR is | |
246 | broadcast factor. */ | |
247 | struct Broadcast_Operation | |
248 | { | |
8e6e0792 | 249 | /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */ |
43234a1e L |
250 | int type; |
251 | ||
252 | /* Index of broadcasted operand. */ | |
253 | int operand; | |
4a1b91ea L |
254 | |
255 | /* Number of bytes to broadcast. */ | |
256 | int bytes; | |
43234a1e L |
257 | }; |
258 | ||
259 | static struct Broadcast_Operation broadcast_op; | |
260 | ||
c0f3af97 L |
261 | /* VEX prefix. */ |
262 | typedef struct | |
263 | { | |
43234a1e L |
264 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
265 | unsigned char bytes[4]; | |
c0f3af97 L |
266 | unsigned int length; |
267 | /* Destination or source register specifier. */ | |
268 | const reg_entry *register_specifier; | |
269 | } vex_prefix; | |
270 | ||
252b5132 | 271 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 272 | i386_insn. */ |
252b5132 | 273 | |
520dc8e8 AM |
274 | union i386_op |
275 | { | |
276 | expressionS *disps; | |
277 | expressionS *imms; | |
278 | const reg_entry *regs; | |
279 | }; | |
280 | ||
a65babc9 L |
281 | enum i386_error |
282 | { | |
86e026a4 | 283 | operand_size_mismatch, |
a65babc9 L |
284 | operand_type_mismatch, |
285 | register_type_mismatch, | |
286 | number_of_operands_mismatch, | |
287 | invalid_instruction_suffix, | |
288 | bad_imm4, | |
a65babc9 L |
289 | unsupported_with_intel_mnemonic, |
290 | unsupported_syntax, | |
6c30d220 L |
291 | unsupported, |
292 | invalid_vsib_address, | |
7bab8ab5 | 293 | invalid_vector_register_set, |
43234a1e L |
294 | unsupported_vector_index_register, |
295 | unsupported_broadcast, | |
43234a1e L |
296 | broadcast_needed, |
297 | unsupported_masking, | |
298 | mask_not_on_destination, | |
299 | no_default_mask, | |
300 | unsupported_rc_sae, | |
301 | rc_sae_operand_not_last_imm, | |
302 | invalid_register_operand, | |
a65babc9 L |
303 | }; |
304 | ||
252b5132 RH |
305 | struct _i386_insn |
306 | { | |
47926f60 | 307 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 308 | insn_template tm; |
252b5132 | 309 | |
7d5e4556 L |
310 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
311 | or qword, if given. */ | |
252b5132 RH |
312 | char suffix; |
313 | ||
47926f60 | 314 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
315 | unsigned int operands; |
316 | ||
317 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
318 | of given register, displacement, memory operands and immediate | |
47926f60 | 319 | operands. */ |
252b5132 RH |
320 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
321 | ||
322 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 323 | use OP[i] for the corresponding operand. */ |
40fb9820 | 324 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 325 | |
520dc8e8 AM |
326 | /* Displacement expression, immediate expression, or register for each |
327 | operand. */ | |
328 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 329 | |
3e73aa7c JH |
330 | /* Flags for operands. */ |
331 | unsigned int flags[MAX_OPERANDS]; | |
332 | #define Operand_PCrel 1 | |
c48dadc9 | 333 | #define Operand_Mem 2 |
3e73aa7c | 334 | |
252b5132 | 335 | /* Relocation type for operand */ |
f86103b7 | 336 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 337 | |
252b5132 RH |
338 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
339 | the base index byte below. */ | |
340 | const reg_entry *base_reg; | |
341 | const reg_entry *index_reg; | |
342 | unsigned int log2_scale_factor; | |
343 | ||
344 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 345 | explicit segment overrides are given. */ |
ce8a8b2f | 346 | const seg_entry *seg[2]; |
252b5132 | 347 | |
8325cc63 JB |
348 | /* Copied first memory operand string, for re-checking. */ |
349 | char *memop1_string; | |
350 | ||
252b5132 RH |
351 | /* PREFIX holds all the given prefix opcodes (usually null). |
352 | PREFIXES is the number of prefix opcodes. */ | |
353 | unsigned int prefixes; | |
354 | unsigned char prefix[MAX_PREFIXES]; | |
355 | ||
b4a3a7b4 L |
356 | /* Has MMX register operands. */ |
357 | bfd_boolean has_regmmx; | |
358 | ||
359 | /* Has XMM register operands. */ | |
360 | bfd_boolean has_regxmm; | |
361 | ||
362 | /* Has YMM register operands. */ | |
363 | bfd_boolean has_regymm; | |
364 | ||
365 | /* Has ZMM register operands. */ | |
366 | bfd_boolean has_regzmm; | |
367 | ||
252b5132 | 368 | /* RM and SIB are the modrm byte and the sib byte where the |
c1e679ec | 369 | addressing modes of this insn are encoded. */ |
252b5132 | 370 | modrm_byte rm; |
3e73aa7c | 371 | rex_byte rex; |
43234a1e | 372 | rex_byte vrex; |
252b5132 | 373 | sib_byte sib; |
c0f3af97 | 374 | vex_prefix vex; |
b6169b20 | 375 | |
43234a1e L |
376 | /* Masking attributes. */ |
377 | struct Mask_Operation *mask; | |
378 | ||
379 | /* Rounding control and SAE attributes. */ | |
380 | struct RC_Operation *rounding; | |
381 | ||
382 | /* Broadcasting attributes. */ | |
383 | struct Broadcast_Operation *broadcast; | |
384 | ||
385 | /* Compressed disp8*N attribute. */ | |
386 | unsigned int memshift; | |
387 | ||
86fa6981 L |
388 | /* Prefer load or store in encoding. */ |
389 | enum | |
390 | { | |
391 | dir_encoding_default = 0, | |
392 | dir_encoding_load, | |
64c49ab3 JB |
393 | dir_encoding_store, |
394 | dir_encoding_swap | |
86fa6981 | 395 | } dir_encoding; |
891edac4 | 396 | |
a501d77e L |
397 | /* Prefer 8bit or 32bit displacement in encoding. */ |
398 | enum | |
399 | { | |
400 | disp_encoding_default = 0, | |
401 | disp_encoding_8bit, | |
402 | disp_encoding_32bit | |
403 | } disp_encoding; | |
f8a5c266 | 404 | |
6b6b6807 L |
405 | /* Prefer the REX byte in encoding. */ |
406 | bfd_boolean rex_encoding; | |
407 | ||
b6f8c7c4 L |
408 | /* Disable instruction size optimization. */ |
409 | bfd_boolean no_optimize; | |
410 | ||
86fa6981 L |
411 | /* How to encode vector instructions. */ |
412 | enum | |
413 | { | |
414 | vex_encoding_default = 0, | |
415 | vex_encoding_vex2, | |
416 | vex_encoding_vex3, | |
417 | vex_encoding_evex | |
418 | } vec_encoding; | |
419 | ||
d5de92cf L |
420 | /* REP prefix. */ |
421 | const char *rep_prefix; | |
422 | ||
165de32a L |
423 | /* HLE prefix. */ |
424 | const char *hle_prefix; | |
42164a71 | 425 | |
7e8b059b L |
426 | /* Have BND prefix. */ |
427 | const char *bnd_prefix; | |
428 | ||
04ef582a L |
429 | /* Have NOTRACK prefix. */ |
430 | const char *notrack_prefix; | |
431 | ||
891edac4 | 432 | /* Error message. */ |
a65babc9 | 433 | enum i386_error error; |
252b5132 RH |
434 | }; |
435 | ||
436 | typedef struct _i386_insn i386_insn; | |
437 | ||
43234a1e L |
438 | /* Link RC type with corresponding string, that'll be looked for in |
439 | asm. */ | |
440 | struct RC_name | |
441 | { | |
442 | enum rc_type type; | |
443 | const char *name; | |
444 | unsigned int len; | |
445 | }; | |
446 | ||
447 | static const struct RC_name RC_NamesTable[] = | |
448 | { | |
449 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
450 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
451 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
452 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
453 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
454 | }; | |
455 | ||
252b5132 RH |
456 | /* List of chars besides those in app.c:symbol_chars that can start an |
457 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 458 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 459 | #ifdef LEX_AT |
32137342 NC |
460 | "@" |
461 | #endif | |
462 | #ifdef LEX_QM | |
463 | "?" | |
252b5132 | 464 | #endif |
32137342 | 465 | ; |
252b5132 | 466 | |
29b0f896 AM |
467 | #if (defined (TE_I386AIX) \ |
468 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 469 | && !defined (TE_GNU) \ |
29b0f896 | 470 | && !defined (TE_LINUX) \ |
8d63c93e | 471 | && !defined (TE_NACL) \ |
29b0f896 | 472 | && !defined (TE_FreeBSD) \ |
5b806d27 | 473 | && !defined (TE_DragonFly) \ |
29b0f896 | 474 | && !defined (TE_NetBSD))) |
252b5132 | 475 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
476 | pre-processor is disabled, these aren't very useful. The option |
477 | --divide will remove '/' from this list. */ | |
478 | const char *i386_comment_chars = "#/"; | |
479 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 480 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 481 | |
b3b91714 AM |
482 | #else |
483 | const char *i386_comment_chars = "#"; | |
484 | #define PREFIX_SEPARATOR '/' | |
485 | #endif | |
486 | ||
252b5132 RH |
487 | /* This array holds the chars that only start a comment at the beginning of |
488 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
489 | .line and .file directives will appear in the pre-processed output. |
490 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 491 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
492 | #NO_APP at the beginning of its output. |
493 | Also note that comments started like this one will always work if | |
252b5132 | 494 | '/' isn't otherwise defined. */ |
b3b91714 | 495 | const char line_comment_chars[] = "#/"; |
252b5132 | 496 | |
63a0b638 | 497 | const char line_separator_chars[] = ";"; |
252b5132 | 498 | |
ce8a8b2f AM |
499 | /* Chars that can be used to separate mant from exp in floating point |
500 | nums. */ | |
252b5132 RH |
501 | const char EXP_CHARS[] = "eE"; |
502 | ||
ce8a8b2f AM |
503 | /* Chars that mean this number is a floating point constant |
504 | As in 0f12.456 | |
505 | or 0d1.2345e12. */ | |
252b5132 RH |
506 | const char FLT_CHARS[] = "fFdDxX"; |
507 | ||
ce8a8b2f | 508 | /* Tables for lexical analysis. */ |
252b5132 RH |
509 | static char mnemonic_chars[256]; |
510 | static char register_chars[256]; | |
511 | static char operand_chars[256]; | |
512 | static char identifier_chars[256]; | |
513 | static char digit_chars[256]; | |
514 | ||
ce8a8b2f | 515 | /* Lexical macros. */ |
252b5132 RH |
516 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
517 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
518 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
519 | #define is_space_char(x) ((x) == ' ') | |
520 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
521 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
522 | ||
0234cb7c | 523 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
524 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
525 | ||
526 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
527 | effect this we maintain a stack of saved characters that we've smashed | |
528 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 529 | assembler instruction). */ |
252b5132 | 530 | static char save_stack[32]; |
ce8a8b2f | 531 | static char *save_stack_p; |
252b5132 RH |
532 | #define END_STRING_AND_SAVE(s) \ |
533 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
534 | #define RESTORE_END_STRING(s) \ | |
535 | do { *(s) = *--save_stack_p; } while (0) | |
536 | ||
47926f60 | 537 | /* The instruction we're assembling. */ |
252b5132 RH |
538 | static i386_insn i; |
539 | ||
540 | /* Possible templates for current insn. */ | |
541 | static const templates *current_templates; | |
542 | ||
31b2323c L |
543 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
544 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
545 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 546 | |
47926f60 | 547 | /* Current operand we are working on. */ |
ee86248c | 548 | static int this_operand = -1; |
252b5132 | 549 | |
3e73aa7c JH |
550 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
551 | these. */ | |
552 | ||
553 | enum flag_code { | |
554 | CODE_32BIT, | |
555 | CODE_16BIT, | |
556 | CODE_64BIT }; | |
557 | ||
558 | static enum flag_code flag_code; | |
4fa24527 | 559 | static unsigned int object_64bit; |
862be3fb | 560 | static unsigned int disallow_64bit_reloc; |
3e73aa7c JH |
561 | static int use_rela_relocations = 0; |
562 | ||
7af8ed2d NC |
563 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
564 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
565 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
566 | ||
351f65ca L |
567 | /* The ELF ABI to use. */ |
568 | enum x86_elf_abi | |
569 | { | |
570 | I386_ABI, | |
7f56bc95 L |
571 | X86_64_ABI, |
572 | X86_64_X32_ABI | |
351f65ca L |
573 | }; |
574 | ||
575 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 576 | #endif |
351f65ca | 577 | |
167ad85b TG |
578 | #if defined (TE_PE) || defined (TE_PEP) |
579 | /* Use big object file format. */ | |
580 | static int use_big_obj = 0; | |
581 | #endif | |
582 | ||
8dcea932 L |
583 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
584 | /* 1 if generating code for a shared library. */ | |
585 | static int shared = 0; | |
586 | #endif | |
587 | ||
47926f60 KH |
588 | /* 1 for intel syntax, |
589 | 0 if att syntax. */ | |
590 | static int intel_syntax = 0; | |
252b5132 | 591 | |
e89c5eaa L |
592 | /* 1 for Intel64 ISA, |
593 | 0 if AMD64 ISA. */ | |
594 | static int intel64; | |
595 | ||
1efbbeb4 L |
596 | /* 1 for intel mnemonic, |
597 | 0 if att mnemonic. */ | |
598 | static int intel_mnemonic = !SYSV386_COMPAT; | |
599 | ||
a60de03c JB |
600 | /* 1 if pseudo registers are permitted. */ |
601 | static int allow_pseudo_reg = 0; | |
602 | ||
47926f60 KH |
603 | /* 1 if register prefix % not required. */ |
604 | static int allow_naked_reg = 0; | |
252b5132 | 605 | |
33eaf5de | 606 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
607 | instructions supporting it, even if this prefix wasn't specified |
608 | explicitly. */ | |
609 | static int add_bnd_prefix = 0; | |
610 | ||
ba104c83 | 611 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
612 | static int allow_index_reg = 0; |
613 | ||
d022bddd IT |
614 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
615 | specified explicitly. */ | |
616 | static int omit_lock_prefix = 0; | |
617 | ||
e4e00185 AS |
618 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
619 | "lock addl $0, (%{re}sp)". */ | |
620 | static int avoid_fence = 0; | |
621 | ||
0cb4071e L |
622 | /* 1 if the assembler should generate relax relocations. */ |
623 | ||
624 | static int generate_relax_relocations | |
625 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
626 | ||
7bab8ab5 | 627 | static enum check_kind |
daf50ae7 | 628 | { |
7bab8ab5 JB |
629 | check_none = 0, |
630 | check_warning, | |
631 | check_error | |
daf50ae7 | 632 | } |
7bab8ab5 | 633 | sse_check, operand_check = check_warning; |
daf50ae7 | 634 | |
b6f8c7c4 L |
635 | /* Optimization: |
636 | 1. Clear the REX_W bit with register operand if possible. | |
637 | 2. Above plus use 128bit vector instruction to clear the full vector | |
638 | register. | |
639 | */ | |
640 | static int optimize = 0; | |
641 | ||
642 | /* Optimization: | |
643 | 1. Clear the REX_W bit with register operand if possible. | |
644 | 2. Above plus use 128bit vector instruction to clear the full vector | |
645 | register. | |
646 | 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to | |
647 | "testb $imm7,%r8". | |
648 | */ | |
649 | static int optimize_for_space = 0; | |
650 | ||
2ca3ace5 L |
651 | /* Register prefix used for error message. */ |
652 | static const char *register_prefix = "%"; | |
653 | ||
47926f60 KH |
654 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
655 | leave, push, and pop instructions so that gcc has the same stack | |
656 | frame as in 32 bit mode. */ | |
657 | static char stackop_size = '\0'; | |
eecb386c | 658 | |
12b55ccc L |
659 | /* Non-zero to optimize code alignment. */ |
660 | int optimize_align_code = 1; | |
661 | ||
47926f60 KH |
662 | /* Non-zero to quieten some warnings. */ |
663 | static int quiet_warnings = 0; | |
a38cf1db | 664 | |
47926f60 KH |
665 | /* CPU name. */ |
666 | static const char *cpu_arch_name = NULL; | |
6305a203 | 667 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 668 | |
47926f60 | 669 | /* CPU feature flags. */ |
40fb9820 L |
670 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
671 | ||
ccc9c027 L |
672 | /* If we have selected a cpu we are generating instructions for. */ |
673 | static int cpu_arch_tune_set = 0; | |
674 | ||
9103f4f4 | 675 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 676 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
677 | |
678 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 679 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 680 | |
ccc9c027 | 681 | /* CPU instruction set architecture used. */ |
fbf3f584 | 682 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 683 | |
9103f4f4 | 684 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 685 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 686 | |
fddf5b5b AM |
687 | /* If set, conditional jumps are not automatically promoted to handle |
688 | larger than a byte offset. */ | |
689 | static unsigned int no_cond_jump_promotion = 0; | |
690 | ||
c0f3af97 L |
691 | /* Encode SSE instructions with VEX prefix. */ |
692 | static unsigned int sse2avx; | |
693 | ||
539f890d L |
694 | /* Encode scalar AVX instructions with specific vector length. */ |
695 | static enum | |
696 | { | |
697 | vex128 = 0, | |
698 | vex256 | |
699 | } avxscalar; | |
700 | ||
03751133 L |
701 | /* Encode VEX WIG instructions with specific vex.w. */ |
702 | static enum | |
703 | { | |
704 | vexw0 = 0, | |
705 | vexw1 | |
706 | } vexwig; | |
707 | ||
43234a1e L |
708 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
709 | static enum | |
710 | { | |
711 | evexl128 = 0, | |
712 | evexl256, | |
713 | evexl512 | |
714 | } evexlig; | |
715 | ||
716 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
717 | static enum | |
718 | { | |
719 | evexw0 = 0, | |
720 | evexw1 | |
721 | } evexwig; | |
722 | ||
d3d3c6db IT |
723 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
724 | static enum rc_type evexrcig = rne; | |
725 | ||
29b0f896 | 726 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 727 | static symbolS *GOT_symbol; |
29b0f896 | 728 | |
a4447b93 RH |
729 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
730 | unsigned int x86_dwarf2_return_column; | |
731 | ||
732 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
733 | int x86_cie_data_alignment; | |
734 | ||
252b5132 | 735 | /* Interface to relax_segment. |
fddf5b5b AM |
736 | There are 3 major relax states for 386 jump insns because the |
737 | different types of jumps add different sizes to frags when we're | |
738 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 739 | |
47926f60 | 740 | /* Types. */ |
93c2a809 AM |
741 | #define UNCOND_JUMP 0 |
742 | #define COND_JUMP 1 | |
743 | #define COND_JUMP86 2 | |
fddf5b5b | 744 | |
47926f60 | 745 | /* Sizes. */ |
252b5132 RH |
746 | #define CODE16 1 |
747 | #define SMALL 0 | |
29b0f896 | 748 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 749 | #define BIG 2 |
29b0f896 | 750 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
751 | |
752 | #ifndef INLINE | |
753 | #ifdef __GNUC__ | |
754 | #define INLINE __inline__ | |
755 | #else | |
756 | #define INLINE | |
757 | #endif | |
758 | #endif | |
759 | ||
fddf5b5b AM |
760 | #define ENCODE_RELAX_STATE(type, size) \ |
761 | ((relax_substateT) (((type) << 2) | (size))) | |
762 | #define TYPE_FROM_RELAX_STATE(s) \ | |
763 | ((s) >> 2) | |
764 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
765 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
766 | |
767 | /* This table is used by relax_frag to promote short jumps to long | |
768 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
769 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
770 | don't allow a short jump in a 32 bit code segment to be promoted to | |
771 | a 16 bit offset jump because it's slower (requires data size | |
772 | prefix), and doesn't work, unless the destination is in the bottom | |
773 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
774 | ||
775 | const relax_typeS md_relax_table[] = | |
776 | { | |
24eab124 AM |
777 | /* The fields are: |
778 | 1) most positive reach of this state, | |
779 | 2) most negative reach of this state, | |
93c2a809 | 780 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 781 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 782 | |
fddf5b5b | 783 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
784 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
785 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
786 | /* dword jmp adds 4 bytes to frag: | |
787 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 788 | {0, 0, 4, 0}, |
93c2a809 AM |
789 | /* word jmp adds 2 byte2 to frag: |
790 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
791 | {0, 0, 2, 0}, |
792 | ||
93c2a809 AM |
793 | /* COND_JUMP states. */ |
794 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
795 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
796 | /* dword conditionals adds 5 bytes to frag: | |
797 | 1 extra opcode byte, 4 displacement bytes. */ | |
798 | {0, 0, 5, 0}, | |
fddf5b5b | 799 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
800 | 1 extra opcode byte, 2 displacement bytes. */ |
801 | {0, 0, 3, 0}, | |
802 | ||
803 | /* COND_JUMP86 states. */ | |
804 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
805 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
806 | /* dword conditionals adds 5 bytes to frag: | |
807 | 1 extra opcode byte, 4 displacement bytes. */ | |
808 | {0, 0, 5, 0}, | |
809 | /* word conditionals add 4 bytes to frag: | |
810 | 1 displacement byte and a 3 byte long branch insn. */ | |
811 | {0, 0, 4, 0} | |
252b5132 RH |
812 | }; |
813 | ||
9103f4f4 L |
814 | static const arch_entry cpu_arch[] = |
815 | { | |
89507696 JB |
816 | /* Do not replace the first two entries - i386_target_format() |
817 | relies on them being there in this order. */ | |
8a2c8fef | 818 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
293f5f65 | 819 | CPU_GENERIC32_FLAGS, 0 }, |
8a2c8fef | 820 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
293f5f65 | 821 | CPU_GENERIC64_FLAGS, 0 }, |
8a2c8fef | 822 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
293f5f65 | 823 | CPU_NONE_FLAGS, 0 }, |
8a2c8fef | 824 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
293f5f65 | 825 | CPU_I186_FLAGS, 0 }, |
8a2c8fef | 826 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
293f5f65 | 827 | CPU_I286_FLAGS, 0 }, |
8a2c8fef | 828 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
293f5f65 | 829 | CPU_I386_FLAGS, 0 }, |
8a2c8fef | 830 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
293f5f65 | 831 | CPU_I486_FLAGS, 0 }, |
8a2c8fef | 832 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
293f5f65 | 833 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 834 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 835 | CPU_I686_FLAGS, 0 }, |
8a2c8fef | 836 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
293f5f65 | 837 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 838 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 839 | CPU_PENTIUMPRO_FLAGS, 0 }, |
8a2c8fef | 840 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 841 | CPU_P2_FLAGS, 0 }, |
8a2c8fef | 842 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
293f5f65 | 843 | CPU_P3_FLAGS, 0 }, |
8a2c8fef | 844 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
293f5f65 | 845 | CPU_P4_FLAGS, 0 }, |
8a2c8fef | 846 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
293f5f65 | 847 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 848 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
293f5f65 | 849 | CPU_NOCONA_FLAGS, 0 }, |
8a2c8fef | 850 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
293f5f65 | 851 | CPU_CORE_FLAGS, 1 }, |
8a2c8fef | 852 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
293f5f65 | 853 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 854 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
293f5f65 | 855 | CPU_CORE2_FLAGS, 1 }, |
8a2c8fef | 856 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
293f5f65 | 857 | CPU_CORE2_FLAGS, 0 }, |
8a2c8fef | 858 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
293f5f65 | 859 | CPU_COREI7_FLAGS, 0 }, |
8a2c8fef | 860 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
293f5f65 | 861 | CPU_L1OM_FLAGS, 0 }, |
7a9068fe | 862 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
293f5f65 | 863 | CPU_K1OM_FLAGS, 0 }, |
81486035 | 864 | { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, |
293f5f65 | 865 | CPU_IAMCU_FLAGS, 0 }, |
8a2c8fef | 866 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
293f5f65 | 867 | CPU_K6_FLAGS, 0 }, |
8a2c8fef | 868 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
293f5f65 | 869 | CPU_K6_2_FLAGS, 0 }, |
8a2c8fef | 870 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
293f5f65 | 871 | CPU_ATHLON_FLAGS, 0 }, |
8a2c8fef | 872 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
293f5f65 | 873 | CPU_K8_FLAGS, 1 }, |
8a2c8fef | 874 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
293f5f65 | 875 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 876 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
293f5f65 | 877 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 878 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
293f5f65 | 879 | CPU_AMDFAM10_FLAGS, 0 }, |
8aedb9fe | 880 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
293f5f65 | 881 | CPU_BDVER1_FLAGS, 0 }, |
8aedb9fe | 882 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
293f5f65 | 883 | CPU_BDVER2_FLAGS, 0 }, |
5e5c50d3 | 884 | { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, |
293f5f65 | 885 | CPU_BDVER3_FLAGS, 0 }, |
c7b0bd56 | 886 | { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, |
293f5f65 | 887 | CPU_BDVER4_FLAGS, 0 }, |
029f3522 | 888 | { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, |
293f5f65 | 889 | CPU_ZNVER1_FLAGS, 0 }, |
a9660a6f AP |
890 | { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER, |
891 | CPU_ZNVER2_FLAGS, 0 }, | |
7b458c12 | 892 | { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, |
293f5f65 | 893 | CPU_BTVER1_FLAGS, 0 }, |
7b458c12 | 894 | { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, |
293f5f65 | 895 | CPU_BTVER2_FLAGS, 0 }, |
8a2c8fef | 896 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
293f5f65 | 897 | CPU_8087_FLAGS, 0 }, |
8a2c8fef | 898 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
293f5f65 | 899 | CPU_287_FLAGS, 0 }, |
8a2c8fef | 900 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
293f5f65 | 901 | CPU_387_FLAGS, 0 }, |
1848e567 L |
902 | { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, |
903 | CPU_687_FLAGS, 0 }, | |
d871f3f4 L |
904 | { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN, |
905 | CPU_CMOV_FLAGS, 0 }, | |
906 | { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN, | |
907 | CPU_FXSR_FLAGS, 0 }, | |
8a2c8fef | 908 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 909 | CPU_MMX_FLAGS, 0 }, |
8a2c8fef | 910 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
293f5f65 | 911 | CPU_SSE_FLAGS, 0 }, |
8a2c8fef | 912 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
293f5f65 | 913 | CPU_SSE2_FLAGS, 0 }, |
8a2c8fef | 914 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 915 | CPU_SSE3_FLAGS, 0 }, |
8a2c8fef | 916 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 917 | CPU_SSSE3_FLAGS, 0 }, |
8a2c8fef | 918 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
293f5f65 | 919 | CPU_SSE4_1_FLAGS, 0 }, |
8a2c8fef | 920 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
293f5f65 | 921 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 922 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
293f5f65 | 923 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 924 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
293f5f65 | 925 | CPU_AVX_FLAGS, 0 }, |
6c30d220 | 926 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
293f5f65 | 927 | CPU_AVX2_FLAGS, 0 }, |
43234a1e | 928 | { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, |
293f5f65 | 929 | CPU_AVX512F_FLAGS, 0 }, |
43234a1e | 930 | { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, |
293f5f65 | 931 | CPU_AVX512CD_FLAGS, 0 }, |
43234a1e | 932 | { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, |
293f5f65 | 933 | CPU_AVX512ER_FLAGS, 0 }, |
43234a1e | 934 | { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, |
293f5f65 | 935 | CPU_AVX512PF_FLAGS, 0 }, |
1dfc6506 | 936 | { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, |
293f5f65 | 937 | CPU_AVX512DQ_FLAGS, 0 }, |
1dfc6506 | 938 | { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, |
293f5f65 | 939 | CPU_AVX512BW_FLAGS, 0 }, |
1dfc6506 | 940 | { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, |
293f5f65 | 941 | CPU_AVX512VL_FLAGS, 0 }, |
8a2c8fef | 942 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 943 | CPU_VMX_FLAGS, 0 }, |
8729a6f6 | 944 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
293f5f65 | 945 | CPU_VMFUNC_FLAGS, 0 }, |
8a2c8fef | 946 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
293f5f65 | 947 | CPU_SMX_FLAGS, 0 }, |
8a2c8fef | 948 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
293f5f65 | 949 | CPU_XSAVE_FLAGS, 0 }, |
c7b8aa3a | 950 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 951 | CPU_XSAVEOPT_FLAGS, 0 }, |
1dfc6506 | 952 | { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, |
293f5f65 | 953 | CPU_XSAVEC_FLAGS, 0 }, |
1dfc6506 | 954 | { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, |
293f5f65 | 955 | CPU_XSAVES_FLAGS, 0 }, |
8a2c8fef | 956 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
293f5f65 | 957 | CPU_AES_FLAGS, 0 }, |
8a2c8fef | 958 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 959 | CPU_PCLMUL_FLAGS, 0 }, |
8a2c8fef | 960 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 961 | CPU_PCLMUL_FLAGS, 1 }, |
c7b8aa3a | 962 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
293f5f65 | 963 | CPU_FSGSBASE_FLAGS, 0 }, |
c7b8aa3a | 964 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
293f5f65 | 965 | CPU_RDRND_FLAGS, 0 }, |
c7b8aa3a | 966 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
293f5f65 | 967 | CPU_F16C_FLAGS, 0 }, |
6c30d220 | 968 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
293f5f65 | 969 | CPU_BMI2_FLAGS, 0 }, |
8a2c8fef | 970 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
293f5f65 | 971 | CPU_FMA_FLAGS, 0 }, |
8a2c8fef | 972 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
293f5f65 | 973 | CPU_FMA4_FLAGS, 0 }, |
8a2c8fef | 974 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
293f5f65 | 975 | CPU_XOP_FLAGS, 0 }, |
8a2c8fef | 976 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
293f5f65 | 977 | CPU_LWP_FLAGS, 0 }, |
8a2c8fef | 978 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
293f5f65 | 979 | CPU_MOVBE_FLAGS, 0 }, |
60aa667e | 980 | { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, |
293f5f65 | 981 | CPU_CX16_FLAGS, 0 }, |
8a2c8fef | 982 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
293f5f65 | 983 | CPU_EPT_FLAGS, 0 }, |
6c30d220 | 984 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
293f5f65 | 985 | CPU_LZCNT_FLAGS, 0 }, |
42164a71 | 986 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
293f5f65 | 987 | CPU_HLE_FLAGS, 0 }, |
42164a71 | 988 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, |
293f5f65 | 989 | CPU_RTM_FLAGS, 0 }, |
6c30d220 | 990 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
293f5f65 | 991 | CPU_INVPCID_FLAGS, 0 }, |
8a2c8fef | 992 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
293f5f65 | 993 | CPU_CLFLUSH_FLAGS, 0 }, |
22109423 | 994 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, |
293f5f65 | 995 | CPU_NOP_FLAGS, 0 }, |
8a2c8fef | 996 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
293f5f65 | 997 | CPU_SYSCALL_FLAGS, 0 }, |
8a2c8fef | 998 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
293f5f65 | 999 | CPU_RDTSCP_FLAGS, 0 }, |
8a2c8fef | 1000 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
293f5f65 | 1001 | CPU_3DNOW_FLAGS, 0 }, |
8a2c8fef | 1002 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
293f5f65 | 1003 | CPU_3DNOWA_FLAGS, 0 }, |
8a2c8fef | 1004 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
293f5f65 | 1005 | CPU_PADLOCK_FLAGS, 0 }, |
8a2c8fef | 1006 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
293f5f65 | 1007 | CPU_SVME_FLAGS, 1 }, |
8a2c8fef | 1008 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
293f5f65 | 1009 | CPU_SVME_FLAGS, 0 }, |
8a2c8fef | 1010 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
293f5f65 | 1011 | CPU_SSE4A_FLAGS, 0 }, |
8a2c8fef | 1012 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1013 | CPU_ABM_FLAGS, 0 }, |
87973e9f | 1014 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1015 | CPU_BMI_FLAGS, 0 }, |
2a2a0f38 | 1016 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1017 | CPU_TBM_FLAGS, 0 }, |
e2e1fcde | 1018 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1019 | CPU_ADX_FLAGS, 0 }, |
e2e1fcde | 1020 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, |
293f5f65 | 1021 | CPU_RDSEED_FLAGS, 0 }, |
e2e1fcde | 1022 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, |
293f5f65 | 1023 | CPU_PRFCHW_FLAGS, 0 }, |
5c111e37 | 1024 | { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, |
293f5f65 | 1025 | CPU_SMAP_FLAGS, 0 }, |
7e8b059b | 1026 | { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1027 | CPU_MPX_FLAGS, 0 }, |
a0046408 | 1028 | { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, |
293f5f65 | 1029 | CPU_SHA_FLAGS, 0 }, |
963f3586 | 1030 | { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1031 | CPU_CLFLUSHOPT_FLAGS, 0 }, |
dcf893b5 | 1032 | { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1033 | CPU_PREFETCHWT1_FLAGS, 0 }, |
2cf200a4 | 1034 | { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1035 | CPU_SE1_FLAGS, 0 }, |
c5e7287a | 1036 | { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, |
293f5f65 | 1037 | CPU_CLWB_FLAGS, 0 }, |
2cc1b5aa | 1038 | { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, |
293f5f65 | 1039 | CPU_AVX512IFMA_FLAGS, 0 }, |
14f195c9 | 1040 | { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1041 | CPU_AVX512VBMI_FLAGS, 0 }, |
920d2ddc IT |
1042 | { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN, |
1043 | CPU_AVX512_4FMAPS_FLAGS, 0 }, | |
47acf0bd IT |
1044 | { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN, |
1045 | CPU_AVX512_4VNNIW_FLAGS, 0 }, | |
620214f7 IT |
1046 | { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN, |
1047 | CPU_AVX512_VPOPCNTDQ_FLAGS, 0 }, | |
53467f57 IT |
1048 | { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN, |
1049 | CPU_AVX512_VBMI2_FLAGS, 0 }, | |
8cfcb765 IT |
1050 | { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN, |
1051 | CPU_AVX512_VNNI_FLAGS, 0 }, | |
ee6872be IT |
1052 | { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN, |
1053 | CPU_AVX512_BITALG_FLAGS, 0 }, | |
029f3522 | 1054 | { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, |
293f5f65 | 1055 | CPU_CLZERO_FLAGS, 0 }, |
9916071f | 1056 | { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1057 | CPU_MWAITX_FLAGS, 0 }, |
8eab4136 | 1058 | { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, |
293f5f65 | 1059 | CPU_OSPKE_FLAGS, 0 }, |
8bc52696 | 1060 | { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1061 | CPU_RDPID_FLAGS, 0 }, |
6b40c462 L |
1062 | { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN, |
1063 | CPU_PTWRITE_FLAGS, 0 }, | |
d777820b IT |
1064 | { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN, |
1065 | CPU_IBT_FLAGS, 0 }, | |
1066 | { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN, | |
1067 | CPU_SHSTK_FLAGS, 0 }, | |
48521003 IT |
1068 | { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN, |
1069 | CPU_GFNI_FLAGS, 0 }, | |
8dcf1fad IT |
1070 | { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN, |
1071 | CPU_VAES_FLAGS, 0 }, | |
ff1982d5 IT |
1072 | { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN, |
1073 | CPU_VPCLMULQDQ_FLAGS, 0 }, | |
3233d7d0 IT |
1074 | { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN, |
1075 | CPU_WBNOINVD_FLAGS, 0 }, | |
be3a8dca IT |
1076 | { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN, |
1077 | CPU_PCONFIG_FLAGS, 0 }, | |
de89d0a3 IT |
1078 | { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN, |
1079 | CPU_WAITPKG_FLAGS, 0 }, | |
c48935d7 IT |
1080 | { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN, |
1081 | CPU_CLDEMOTE_FLAGS, 0 }, | |
c0a30a9f L |
1082 | { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN, |
1083 | CPU_MOVDIRI_FLAGS, 0 }, | |
1084 | { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN, | |
1085 | CPU_MOVDIR64B_FLAGS, 0 }, | |
d6aab7a1 XG |
1086 | { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN, |
1087 | CPU_AVX512_BF16_FLAGS, 0 }, | |
9186c494 L |
1088 | { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN, |
1089 | CPU_AVX512_VP2INTERSECT_FLAGS, 0 }, | |
dd455cf5 L |
1090 | { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN, |
1091 | CPU_ENQCMD_FLAGS, 0 }, | |
142861df JB |
1092 | { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN, |
1093 | CPU_RDPRU_FLAGS, 0 }, | |
1094 | { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN, | |
1095 | CPU_MCOMMIT_FLAGS, 0 }, | |
293f5f65 L |
1096 | }; |
1097 | ||
1098 | static const noarch_entry cpu_noarch[] = | |
1099 | { | |
1100 | { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, | |
1848e567 L |
1101 | { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, |
1102 | { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, | |
1103 | { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, | |
d871f3f4 L |
1104 | { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS }, |
1105 | { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS }, | |
293f5f65 L |
1106 | { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, |
1107 | { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, | |
1848e567 L |
1108 | { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, |
1109 | { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, | |
1110 | { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, | |
1111 | { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, | |
1112 | { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, | |
1113 | { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, | |
293f5f65 | 1114 | { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, |
1848e567 | 1115 | { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, |
144b71e2 L |
1116 | { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, |
1117 | { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, | |
1118 | { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, | |
1119 | { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, | |
1120 | { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, | |
1121 | { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, | |
1122 | { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, | |
1123 | { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, | |
1124 | { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, | |
920d2ddc | 1125 | { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS }, |
47acf0bd | 1126 | { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS }, |
620214f7 | 1127 | { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, |
53467f57 | 1128 | { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS }, |
8cfcb765 | 1129 | { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS }, |
ee6872be | 1130 | { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS }, |
d777820b IT |
1131 | { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS }, |
1132 | { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS }, | |
c0a30a9f L |
1133 | { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS }, |
1134 | { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS }, | |
d6aab7a1 | 1135 | { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS }, |
9186c494 | 1136 | { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS }, |
dd455cf5 | 1137 | { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS }, |
e413e4e9 AM |
1138 | }; |
1139 | ||
704209c0 | 1140 | #ifdef I386COFF |
a6c24e68 NC |
1141 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1142 | is allowed to be optional. */ | |
1143 | ||
1144 | static symbolS * | |
1145 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1146 | { | |
1147 | addressT align = 0; | |
1148 | ||
1149 | SKIP_WHITESPACE (); | |
1150 | ||
7ab9ffdd | 1151 | if (needs_align |
a6c24e68 NC |
1152 | && *input_line_pointer == ',') |
1153 | { | |
1154 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1155 | |
a6c24e68 NC |
1156 | if (align == (addressT) -1) |
1157 | return NULL; | |
1158 | } | |
1159 | else | |
1160 | { | |
1161 | if (size >= 8) | |
1162 | align = 3; | |
1163 | else if (size >= 4) | |
1164 | align = 2; | |
1165 | else if (size >= 2) | |
1166 | align = 1; | |
1167 | else | |
1168 | align = 0; | |
1169 | } | |
1170 | ||
1171 | bss_alloc (symbolP, size, align); | |
1172 | return symbolP; | |
1173 | } | |
1174 | ||
704209c0 | 1175 | static void |
a6c24e68 NC |
1176 | pe_lcomm (int needs_align) |
1177 | { | |
1178 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1179 | } | |
704209c0 | 1180 | #endif |
a6c24e68 | 1181 | |
29b0f896 AM |
1182 | const pseudo_typeS md_pseudo_table[] = |
1183 | { | |
1184 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1185 | {"align", s_align_bytes, 0}, | |
1186 | #else | |
1187 | {"align", s_align_ptwo, 0}, | |
1188 | #endif | |
1189 | {"arch", set_cpu_arch, 0}, | |
1190 | #ifndef I386COFF | |
1191 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
1192 | #else |
1193 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
1194 | #endif |
1195 | {"ffloat", float_cons, 'f'}, | |
1196 | {"dfloat", float_cons, 'd'}, | |
1197 | {"tfloat", float_cons, 'x'}, | |
1198 | {"value", cons, 2}, | |
d182319b | 1199 | {"slong", signed_cons, 4}, |
29b0f896 AM |
1200 | {"noopt", s_ignore, 0}, |
1201 | {"optim", s_ignore, 0}, | |
1202 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1203 | {"code16", set_code_flag, CODE_16BIT}, | |
1204 | {"code32", set_code_flag, CODE_32BIT}, | |
da5f19a2 | 1205 | #ifdef BFD64 |
29b0f896 | 1206 | {"code64", set_code_flag, CODE_64BIT}, |
da5f19a2 | 1207 | #endif |
29b0f896 AM |
1208 | {"intel_syntax", set_intel_syntax, 1}, |
1209 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1210 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1211 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1212 | {"allow_index_reg", set_allow_index_reg, 1}, |
1213 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1214 | {"sse_check", set_check, 0}, |
1215 | {"operand_check", set_check, 1}, | |
3b22753a L |
1216 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1217 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1218 | #else |
68d20676 | 1219 | {"file", dwarf2_directive_file, 0}, |
07a53e5c RH |
1220 | {"loc", dwarf2_directive_loc, 0}, |
1221 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1222 | #endif |
6482c264 NC |
1223 | #ifdef TE_PE |
1224 | {"secrel32", pe_directive_secrel, 0}, | |
1225 | #endif | |
29b0f896 AM |
1226 | {0, 0, 0} |
1227 | }; | |
1228 | ||
1229 | /* For interface with expression (). */ | |
1230 | extern char *input_line_pointer; | |
1231 | ||
1232 | /* Hash table for instruction mnemonic lookup. */ | |
1233 | static struct hash_control *op_hash; | |
1234 | ||
1235 | /* Hash table for register lookup. */ | |
1236 | static struct hash_control *reg_hash; | |
1237 | \f | |
ce8a8b2f AM |
1238 | /* Various efficient no-op patterns for aligning code labels. |
1239 | Note: Don't try to assemble the instructions in the comments. | |
1240 | 0L and 0w are not legal. */ | |
62a02d25 L |
1241 | static const unsigned char f32_1[] = |
1242 | {0x90}; /* nop */ | |
1243 | static const unsigned char f32_2[] = | |
1244 | {0x66,0x90}; /* xchg %ax,%ax */ | |
1245 | static const unsigned char f32_3[] = | |
1246 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
1247 | static const unsigned char f32_4[] = | |
1248 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
62a02d25 L |
1249 | static const unsigned char f32_6[] = |
1250 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
1251 | static const unsigned char f32_7[] = | |
1252 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
62a02d25 | 1253 | static const unsigned char f16_3[] = |
3ae729d5 | 1254 | {0x8d,0x74,0x00}; /* lea 0(%si),%si */ |
62a02d25 | 1255 | static const unsigned char f16_4[] = |
3ae729d5 L |
1256 | {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */ |
1257 | static const unsigned char jump_disp8[] = | |
1258 | {0xeb}; /* jmp disp8 */ | |
1259 | static const unsigned char jump32_disp32[] = | |
1260 | {0xe9}; /* jmp disp32 */ | |
1261 | static const unsigned char jump16_disp32[] = | |
1262 | {0x66,0xe9}; /* jmp disp32 */ | |
62a02d25 L |
1263 | /* 32-bit NOPs patterns. */ |
1264 | static const unsigned char *const f32_patt[] = { | |
3ae729d5 | 1265 | f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7 |
62a02d25 L |
1266 | }; |
1267 | /* 16-bit NOPs patterns. */ | |
1268 | static const unsigned char *const f16_patt[] = { | |
3ae729d5 | 1269 | f32_1, f32_2, f16_3, f16_4 |
62a02d25 L |
1270 | }; |
1271 | /* nopl (%[re]ax) */ | |
1272 | static const unsigned char alt_3[] = | |
1273 | {0x0f,0x1f,0x00}; | |
1274 | /* nopl 0(%[re]ax) */ | |
1275 | static const unsigned char alt_4[] = | |
1276 | {0x0f,0x1f,0x40,0x00}; | |
1277 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
1278 | static const unsigned char alt_5[] = | |
1279 | {0x0f,0x1f,0x44,0x00,0x00}; | |
1280 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
1281 | static const unsigned char alt_6[] = | |
1282 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1283 | /* nopl 0L(%[re]ax) */ | |
1284 | static const unsigned char alt_7[] = | |
1285 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1286 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
1287 | static const unsigned char alt_8[] = | |
1288 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1289 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
1290 | static const unsigned char alt_9[] = | |
1291 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1292 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
1293 | static const unsigned char alt_10[] = | |
1294 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
3ae729d5 L |
1295 | /* data16 nopw %cs:0L(%eax,%eax,1) */ |
1296 | static const unsigned char alt_11[] = | |
1297 | {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
62a02d25 L |
1298 | /* 32-bit and 64-bit NOPs patterns. */ |
1299 | static const unsigned char *const alt_patt[] = { | |
1300 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
3ae729d5 | 1301 | alt_9, alt_10, alt_11 |
62a02d25 L |
1302 | }; |
1303 | ||
1304 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum | |
1305 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ | |
1306 | ||
1307 | static void | |
1308 | i386_output_nops (char *where, const unsigned char *const *patt, | |
1309 | int count, int max_single_nop_size) | |
1310 | ||
1311 | { | |
3ae729d5 L |
1312 | /* Place the longer NOP first. */ |
1313 | int last; | |
1314 | int offset; | |
3076e594 NC |
1315 | const unsigned char *nops; |
1316 | ||
1317 | if (max_single_nop_size < 1) | |
1318 | { | |
1319 | as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"), | |
1320 | max_single_nop_size); | |
1321 | return; | |
1322 | } | |
1323 | ||
1324 | nops = patt[max_single_nop_size - 1]; | |
3ae729d5 L |
1325 | |
1326 | /* Use the smaller one if the requsted one isn't available. */ | |
1327 | if (nops == NULL) | |
62a02d25 | 1328 | { |
3ae729d5 L |
1329 | max_single_nop_size--; |
1330 | nops = patt[max_single_nop_size - 1]; | |
62a02d25 L |
1331 | } |
1332 | ||
3ae729d5 L |
1333 | last = count % max_single_nop_size; |
1334 | ||
1335 | count -= last; | |
1336 | for (offset = 0; offset < count; offset += max_single_nop_size) | |
1337 | memcpy (where + offset, nops, max_single_nop_size); | |
1338 | ||
1339 | if (last) | |
1340 | { | |
1341 | nops = patt[last - 1]; | |
1342 | if (nops == NULL) | |
1343 | { | |
1344 | /* Use the smaller one plus one-byte NOP if the needed one | |
1345 | isn't available. */ | |
1346 | last--; | |
1347 | nops = patt[last - 1]; | |
1348 | memcpy (where + offset, nops, last); | |
1349 | where[offset + last] = *patt[0]; | |
1350 | } | |
1351 | else | |
1352 | memcpy (where + offset, nops, last); | |
1353 | } | |
62a02d25 L |
1354 | } |
1355 | ||
3ae729d5 L |
1356 | static INLINE int |
1357 | fits_in_imm7 (offsetT num) | |
1358 | { | |
1359 | return (num & 0x7f) == num; | |
1360 | } | |
1361 | ||
1362 | static INLINE int | |
1363 | fits_in_imm31 (offsetT num) | |
1364 | { | |
1365 | return (num & 0x7fffffff) == num; | |
1366 | } | |
62a02d25 L |
1367 | |
1368 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a | |
1369 | single NOP instruction LIMIT. */ | |
1370 | ||
1371 | void | |
3ae729d5 | 1372 | i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit) |
62a02d25 | 1373 | { |
3ae729d5 | 1374 | const unsigned char *const *patt = NULL; |
62a02d25 | 1375 | int max_single_nop_size; |
3ae729d5 L |
1376 | /* Maximum number of NOPs before switching to jump over NOPs. */ |
1377 | int max_number_of_nops; | |
62a02d25 | 1378 | |
3ae729d5 | 1379 | switch (fragP->fr_type) |
62a02d25 | 1380 | { |
3ae729d5 L |
1381 | case rs_fill_nop: |
1382 | case rs_align_code: | |
1383 | break; | |
1384 | default: | |
62a02d25 L |
1385 | return; |
1386 | } | |
1387 | ||
ccc9c027 L |
1388 | /* We need to decide which NOP sequence to use for 32bit and |
1389 | 64bit. When -mtune= is used: | |
4eed87de | 1390 | |
76bc74dc L |
1391 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1392 | PROCESSOR_GENERIC32, f32_patt will be used. | |
80b8656c L |
1393 | 2. For the rest, alt_patt will be used. |
1394 | ||
1395 | When -mtune= isn't used, alt_patt will be used if | |
22109423 | 1396 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1397 | be used. |
ccc9c027 L |
1398 | |
1399 | When -march= or .arch is used, we can't use anything beyond | |
1400 | cpu_arch_isa_flags. */ | |
1401 | ||
1402 | if (flag_code == CODE_16BIT) | |
1403 | { | |
3ae729d5 L |
1404 | patt = f16_patt; |
1405 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); | |
1406 | /* Limit number of NOPs to 2 in 16-bit mode. */ | |
1407 | max_number_of_nops = 2; | |
252b5132 | 1408 | } |
33fef721 | 1409 | else |
ccc9c027 | 1410 | { |
fbf3f584 | 1411 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1412 | { |
1413 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1414 | switch (cpu_arch_tune) | |
1415 | { | |
1416 | case PROCESSOR_UNKNOWN: | |
1417 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1418 | optimize with nops. */ |
1419 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1420 | patt = alt_patt; |
ccc9c027 L |
1421 | else |
1422 | patt = f32_patt; | |
1423 | break; | |
ccc9c027 L |
1424 | case PROCESSOR_PENTIUM4: |
1425 | case PROCESSOR_NOCONA: | |
ef05d495 | 1426 | case PROCESSOR_CORE: |
76bc74dc | 1427 | case PROCESSOR_CORE2: |
bd5295b2 | 1428 | case PROCESSOR_COREI7: |
3632d14b | 1429 | case PROCESSOR_L1OM: |
7a9068fe | 1430 | case PROCESSOR_K1OM: |
76bc74dc | 1431 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1432 | case PROCESSOR_K6: |
1433 | case PROCESSOR_ATHLON: | |
1434 | case PROCESSOR_K8: | |
4eed87de | 1435 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1436 | case PROCESSOR_BD: |
029f3522 | 1437 | case PROCESSOR_ZNVER: |
7b458c12 | 1438 | case PROCESSOR_BT: |
80b8656c | 1439 | patt = alt_patt; |
ccc9c027 | 1440 | break; |
76bc74dc | 1441 | case PROCESSOR_I386: |
ccc9c027 L |
1442 | case PROCESSOR_I486: |
1443 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1444 | case PROCESSOR_PENTIUMPRO: |
81486035 | 1445 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1446 | case PROCESSOR_GENERIC32: |
1447 | patt = f32_patt; | |
1448 | break; | |
4eed87de | 1449 | } |
ccc9c027 L |
1450 | } |
1451 | else | |
1452 | { | |
fbf3f584 | 1453 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1454 | { |
1455 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1456 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1457 | PROCESSOR_UNKNOWN. */ |
1458 | abort (); | |
1459 | break; | |
1460 | ||
76bc74dc | 1461 | case PROCESSOR_I386: |
ccc9c027 L |
1462 | case PROCESSOR_I486: |
1463 | case PROCESSOR_PENTIUM: | |
81486035 | 1464 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1465 | case PROCESSOR_K6: |
1466 | case PROCESSOR_ATHLON: | |
1467 | case PROCESSOR_K8: | |
4eed87de | 1468 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1469 | case PROCESSOR_BD: |
029f3522 | 1470 | case PROCESSOR_ZNVER: |
7b458c12 | 1471 | case PROCESSOR_BT: |
ccc9c027 L |
1472 | case PROCESSOR_GENERIC32: |
1473 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1474 | with nops. */ |
1475 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1476 | patt = alt_patt; |
ccc9c027 L |
1477 | else |
1478 | patt = f32_patt; | |
1479 | break; | |
76bc74dc L |
1480 | case PROCESSOR_PENTIUMPRO: |
1481 | case PROCESSOR_PENTIUM4: | |
1482 | case PROCESSOR_NOCONA: | |
1483 | case PROCESSOR_CORE: | |
ef05d495 | 1484 | case PROCESSOR_CORE2: |
bd5295b2 | 1485 | case PROCESSOR_COREI7: |
3632d14b | 1486 | case PROCESSOR_L1OM: |
7a9068fe | 1487 | case PROCESSOR_K1OM: |
22109423 | 1488 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
80b8656c | 1489 | patt = alt_patt; |
ccc9c027 L |
1490 | else |
1491 | patt = f32_patt; | |
1492 | break; | |
1493 | case PROCESSOR_GENERIC64: | |
80b8656c | 1494 | patt = alt_patt; |
ccc9c027 | 1495 | break; |
4eed87de | 1496 | } |
ccc9c027 L |
1497 | } |
1498 | ||
76bc74dc L |
1499 | if (patt == f32_patt) |
1500 | { | |
3ae729d5 L |
1501 | max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]); |
1502 | /* Limit number of NOPs to 2 for older processors. */ | |
1503 | max_number_of_nops = 2; | |
76bc74dc L |
1504 | } |
1505 | else | |
1506 | { | |
3ae729d5 L |
1507 | max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]); |
1508 | /* Limit number of NOPs to 7 for newer processors. */ | |
1509 | max_number_of_nops = 7; | |
1510 | } | |
1511 | } | |
1512 | ||
1513 | if (limit == 0) | |
1514 | limit = max_single_nop_size; | |
1515 | ||
1516 | if (fragP->fr_type == rs_fill_nop) | |
1517 | { | |
1518 | /* Output NOPs for .nop directive. */ | |
1519 | if (limit > max_single_nop_size) | |
1520 | { | |
1521 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1522 | _("invalid single nop size: %d " | |
1523 | "(expect within [0, %d])"), | |
1524 | limit, max_single_nop_size); | |
1525 | return; | |
1526 | } | |
1527 | } | |
1528 | else | |
1529 | fragP->fr_var = count; | |
1530 | ||
1531 | if ((count / max_single_nop_size) > max_number_of_nops) | |
1532 | { | |
1533 | /* Generate jump over NOPs. */ | |
1534 | offsetT disp = count - 2; | |
1535 | if (fits_in_imm7 (disp)) | |
1536 | { | |
1537 | /* Use "jmp disp8" if possible. */ | |
1538 | count = disp; | |
1539 | where[0] = jump_disp8[0]; | |
1540 | where[1] = count; | |
1541 | where += 2; | |
1542 | } | |
1543 | else | |
1544 | { | |
1545 | unsigned int size_of_jump; | |
1546 | ||
1547 | if (flag_code == CODE_16BIT) | |
1548 | { | |
1549 | where[0] = jump16_disp32[0]; | |
1550 | where[1] = jump16_disp32[1]; | |
1551 | size_of_jump = 2; | |
1552 | } | |
1553 | else | |
1554 | { | |
1555 | where[0] = jump32_disp32[0]; | |
1556 | size_of_jump = 1; | |
1557 | } | |
1558 | ||
1559 | count -= size_of_jump + 4; | |
1560 | if (!fits_in_imm31 (count)) | |
1561 | { | |
1562 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1563 | _("jump over nop padding out of range")); | |
1564 | return; | |
1565 | } | |
1566 | ||
1567 | md_number_to_chars (where + size_of_jump, count, 4); | |
1568 | where += size_of_jump + 4; | |
76bc74dc | 1569 | } |
ccc9c027 | 1570 | } |
3ae729d5 L |
1571 | |
1572 | /* Generate multiple NOPs. */ | |
1573 | i386_output_nops (where, patt, count, limit); | |
252b5132 RH |
1574 | } |
1575 | ||
c6fb90c8 | 1576 | static INLINE int |
0dfbf9d7 | 1577 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1578 | { |
0dfbf9d7 | 1579 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1580 | { |
1581 | case 3: | |
0dfbf9d7 | 1582 | if (x->array[2]) |
c6fb90c8 | 1583 | return 0; |
1a0670f3 | 1584 | /* Fall through. */ |
c6fb90c8 | 1585 | case 2: |
0dfbf9d7 | 1586 | if (x->array[1]) |
c6fb90c8 | 1587 | return 0; |
1a0670f3 | 1588 | /* Fall through. */ |
c6fb90c8 | 1589 | case 1: |
0dfbf9d7 | 1590 | return !x->array[0]; |
c6fb90c8 L |
1591 | default: |
1592 | abort (); | |
1593 | } | |
40fb9820 L |
1594 | } |
1595 | ||
c6fb90c8 | 1596 | static INLINE void |
0dfbf9d7 | 1597 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1598 | { |
0dfbf9d7 | 1599 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1600 | { |
1601 | case 3: | |
0dfbf9d7 | 1602 | x->array[2] = v; |
1a0670f3 | 1603 | /* Fall through. */ |
c6fb90c8 | 1604 | case 2: |
0dfbf9d7 | 1605 | x->array[1] = v; |
1a0670f3 | 1606 | /* Fall through. */ |
c6fb90c8 | 1607 | case 1: |
0dfbf9d7 | 1608 | x->array[0] = v; |
1a0670f3 | 1609 | /* Fall through. */ |
c6fb90c8 L |
1610 | break; |
1611 | default: | |
1612 | abort (); | |
1613 | } | |
bab6aec1 JB |
1614 | |
1615 | x->bitfield.class = ClassNone; | |
c6fb90c8 | 1616 | } |
40fb9820 | 1617 | |
c6fb90c8 | 1618 | static INLINE int |
0dfbf9d7 L |
1619 | operand_type_equal (const union i386_operand_type *x, |
1620 | const union i386_operand_type *y) | |
c6fb90c8 | 1621 | { |
0dfbf9d7 | 1622 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1623 | { |
1624 | case 3: | |
0dfbf9d7 | 1625 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1626 | return 0; |
1a0670f3 | 1627 | /* Fall through. */ |
c6fb90c8 | 1628 | case 2: |
0dfbf9d7 | 1629 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1630 | return 0; |
1a0670f3 | 1631 | /* Fall through. */ |
c6fb90c8 | 1632 | case 1: |
0dfbf9d7 | 1633 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1634 | break; |
1635 | default: | |
1636 | abort (); | |
1637 | } | |
1638 | } | |
40fb9820 | 1639 | |
0dfbf9d7 L |
1640 | static INLINE int |
1641 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1642 | { | |
1643 | switch (ARRAY_SIZE(x->array)) | |
1644 | { | |
53467f57 IT |
1645 | case 4: |
1646 | if (x->array[3]) | |
1647 | return 0; | |
1648 | /* Fall through. */ | |
0dfbf9d7 L |
1649 | case 3: |
1650 | if (x->array[2]) | |
1651 | return 0; | |
1a0670f3 | 1652 | /* Fall through. */ |
0dfbf9d7 L |
1653 | case 2: |
1654 | if (x->array[1]) | |
1655 | return 0; | |
1a0670f3 | 1656 | /* Fall through. */ |
0dfbf9d7 L |
1657 | case 1: |
1658 | return !x->array[0]; | |
1659 | default: | |
1660 | abort (); | |
1661 | } | |
1662 | } | |
1663 | ||
0dfbf9d7 L |
1664 | static INLINE int |
1665 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1666 | const union i386_cpu_flags *y) | |
1667 | { | |
1668 | switch (ARRAY_SIZE(x->array)) | |
1669 | { | |
53467f57 IT |
1670 | case 4: |
1671 | if (x->array[3] != y->array[3]) | |
1672 | return 0; | |
1673 | /* Fall through. */ | |
0dfbf9d7 L |
1674 | case 3: |
1675 | if (x->array[2] != y->array[2]) | |
1676 | return 0; | |
1a0670f3 | 1677 | /* Fall through. */ |
0dfbf9d7 L |
1678 | case 2: |
1679 | if (x->array[1] != y->array[1]) | |
1680 | return 0; | |
1a0670f3 | 1681 | /* Fall through. */ |
0dfbf9d7 L |
1682 | case 1: |
1683 | return x->array[0] == y->array[0]; | |
1684 | break; | |
1685 | default: | |
1686 | abort (); | |
1687 | } | |
1688 | } | |
c6fb90c8 L |
1689 | |
1690 | static INLINE int | |
1691 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1692 | { | |
1693 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1694 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1695 | } |
1696 | ||
c6fb90c8 L |
1697 | static INLINE i386_cpu_flags |
1698 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1699 | { |
c6fb90c8 L |
1700 | switch (ARRAY_SIZE (x.array)) |
1701 | { | |
53467f57 IT |
1702 | case 4: |
1703 | x.array [3] &= y.array [3]; | |
1704 | /* Fall through. */ | |
c6fb90c8 L |
1705 | case 3: |
1706 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1707 | /* Fall through. */ |
c6fb90c8 L |
1708 | case 2: |
1709 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1710 | /* Fall through. */ |
c6fb90c8 L |
1711 | case 1: |
1712 | x.array [0] &= y.array [0]; | |
1713 | break; | |
1714 | default: | |
1715 | abort (); | |
1716 | } | |
1717 | return x; | |
1718 | } | |
40fb9820 | 1719 | |
c6fb90c8 L |
1720 | static INLINE i386_cpu_flags |
1721 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1722 | { |
c6fb90c8 | 1723 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1724 | { |
53467f57 IT |
1725 | case 4: |
1726 | x.array [3] |= y.array [3]; | |
1727 | /* Fall through. */ | |
c6fb90c8 L |
1728 | case 3: |
1729 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1730 | /* Fall through. */ |
c6fb90c8 L |
1731 | case 2: |
1732 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1733 | /* Fall through. */ |
c6fb90c8 L |
1734 | case 1: |
1735 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1736 | break; |
1737 | default: | |
1738 | abort (); | |
1739 | } | |
40fb9820 L |
1740 | return x; |
1741 | } | |
1742 | ||
309d3373 JB |
1743 | static INLINE i386_cpu_flags |
1744 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1745 | { | |
1746 | switch (ARRAY_SIZE (x.array)) | |
1747 | { | |
53467f57 IT |
1748 | case 4: |
1749 | x.array [3] &= ~y.array [3]; | |
1750 | /* Fall through. */ | |
309d3373 JB |
1751 | case 3: |
1752 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1753 | /* Fall through. */ |
309d3373 JB |
1754 | case 2: |
1755 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1756 | /* Fall through. */ |
309d3373 JB |
1757 | case 1: |
1758 | x.array [0] &= ~y.array [0]; | |
1759 | break; | |
1760 | default: | |
1761 | abort (); | |
1762 | } | |
1763 | return x; | |
1764 | } | |
1765 | ||
c0f3af97 L |
1766 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1767 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
1768 | ||
c0f3af97 | 1769 | #define CPU_FLAGS_PERFECT_MATCH \ |
db12e14e | 1770 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH) |
c0f3af97 L |
1771 | |
1772 | /* Return CPU flags match bits. */ | |
3629bb00 | 1773 | |
40fb9820 | 1774 | static int |
d3ce72d0 | 1775 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1776 | { |
c0f3af97 L |
1777 | i386_cpu_flags x = t->cpu_flags; |
1778 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1779 | |
1780 | x.bitfield.cpu64 = 0; | |
1781 | x.bitfield.cpuno64 = 0; | |
1782 | ||
0dfbf9d7 | 1783 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1784 | { |
1785 | /* This instruction is available on all archs. */ | |
db12e14e | 1786 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1787 | } |
3629bb00 L |
1788 | else |
1789 | { | |
c0f3af97 | 1790 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1791 | i386_cpu_flags cpu = cpu_arch_flags; |
1792 | ||
ab592e75 JB |
1793 | /* AVX512VL is no standalone feature - match it and then strip it. */ |
1794 | if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl) | |
1795 | return match; | |
1796 | x.bitfield.cpuavx512vl = 0; | |
1797 | ||
3629bb00 | 1798 | cpu = cpu_flags_and (x, cpu); |
c0f3af97 L |
1799 | if (!cpu_flags_all_zero (&cpu)) |
1800 | { | |
a5ff0eb2 L |
1801 | if (x.bitfield.cpuavx) |
1802 | { | |
929f69fa | 1803 | /* We need to check a few extra flags with AVX. */ |
b9d49817 JB |
1804 | if (cpu.bitfield.cpuavx |
1805 | && (!t->opcode_modifier.sse2avx || sse2avx) | |
1806 | && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
929f69fa | 1807 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) |
b9d49817 JB |
1808 | && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul)) |
1809 | match |= CPU_FLAGS_ARCH_MATCH; | |
a5ff0eb2 | 1810 | } |
929f69fa JB |
1811 | else if (x.bitfield.cpuavx512f) |
1812 | { | |
1813 | /* We need to check a few extra flags with AVX512F. */ | |
1814 | if (cpu.bitfield.cpuavx512f | |
1815 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) | |
1816 | && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes) | |
1817 | && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq)) | |
1818 | match |= CPU_FLAGS_ARCH_MATCH; | |
1819 | } | |
a5ff0eb2 | 1820 | else |
db12e14e | 1821 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1822 | } |
3629bb00 | 1823 | } |
c0f3af97 | 1824 | return match; |
40fb9820 L |
1825 | } |
1826 | ||
c6fb90c8 L |
1827 | static INLINE i386_operand_type |
1828 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1829 | { |
bab6aec1 JB |
1830 | if (x.bitfield.class != y.bitfield.class) |
1831 | x.bitfield.class = ClassNone; | |
1832 | ||
c6fb90c8 L |
1833 | switch (ARRAY_SIZE (x.array)) |
1834 | { | |
1835 | case 3: | |
1836 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1837 | /* Fall through. */ |
c6fb90c8 L |
1838 | case 2: |
1839 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1840 | /* Fall through. */ |
c6fb90c8 L |
1841 | case 1: |
1842 | x.array [0] &= y.array [0]; | |
1843 | break; | |
1844 | default: | |
1845 | abort (); | |
1846 | } | |
1847 | return x; | |
40fb9820 L |
1848 | } |
1849 | ||
73053c1f JB |
1850 | static INLINE i386_operand_type |
1851 | operand_type_and_not (i386_operand_type x, i386_operand_type y) | |
1852 | { | |
bab6aec1 JB |
1853 | gas_assert (y.bitfield.class == ClassNone); |
1854 | ||
73053c1f JB |
1855 | switch (ARRAY_SIZE (x.array)) |
1856 | { | |
1857 | case 3: | |
1858 | x.array [2] &= ~y.array [2]; | |
1859 | /* Fall through. */ | |
1860 | case 2: | |
1861 | x.array [1] &= ~y.array [1]; | |
1862 | /* Fall through. */ | |
1863 | case 1: | |
1864 | x.array [0] &= ~y.array [0]; | |
1865 | break; | |
1866 | default: | |
1867 | abort (); | |
1868 | } | |
1869 | return x; | |
1870 | } | |
1871 | ||
c6fb90c8 L |
1872 | static INLINE i386_operand_type |
1873 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1874 | { |
bab6aec1 JB |
1875 | gas_assert (x.bitfield.class == ClassNone || |
1876 | y.bitfield.class == ClassNone || | |
1877 | x.bitfield.class == y.bitfield.class); | |
1878 | ||
c6fb90c8 | 1879 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1880 | { |
c6fb90c8 L |
1881 | case 3: |
1882 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1883 | /* Fall through. */ |
c6fb90c8 L |
1884 | case 2: |
1885 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1886 | /* Fall through. */ |
c6fb90c8 L |
1887 | case 1: |
1888 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1889 | break; |
1890 | default: | |
1891 | abort (); | |
1892 | } | |
c6fb90c8 L |
1893 | return x; |
1894 | } | |
40fb9820 | 1895 | |
c6fb90c8 L |
1896 | static INLINE i386_operand_type |
1897 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1898 | { | |
bab6aec1 JB |
1899 | gas_assert (y.bitfield.class == ClassNone); |
1900 | ||
c6fb90c8 L |
1901 | switch (ARRAY_SIZE (x.array)) |
1902 | { | |
1903 | case 3: | |
1904 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 1905 | /* Fall through. */ |
c6fb90c8 L |
1906 | case 2: |
1907 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 1908 | /* Fall through. */ |
c6fb90c8 L |
1909 | case 1: |
1910 | x.array [0] ^= y.array [0]; | |
1911 | break; | |
1912 | default: | |
1913 | abort (); | |
1914 | } | |
40fb9820 L |
1915 | return x; |
1916 | } | |
1917 | ||
40fb9820 L |
1918 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; |
1919 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
1920 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
1921 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
bab6aec1 JB |
1922 | static const i386_operand_type anydisp = OPERAND_TYPE_ANYDISP; |
1923 | static const i386_operand_type anyimm = OPERAND_TYPE_ANYIMM; | |
40fb9820 | 1924 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
43234a1e | 1925 | static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; |
40fb9820 L |
1926 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
1927 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
1928 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
1929 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
1930 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
1931 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
1932 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
1933 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
1934 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
1935 | ||
1936 | enum operand_type | |
1937 | { | |
1938 | reg, | |
40fb9820 L |
1939 | imm, |
1940 | disp, | |
1941 | anymem | |
1942 | }; | |
1943 | ||
c6fb90c8 | 1944 | static INLINE int |
40fb9820 L |
1945 | operand_type_check (i386_operand_type t, enum operand_type c) |
1946 | { | |
1947 | switch (c) | |
1948 | { | |
1949 | case reg: | |
bab6aec1 | 1950 | return t.bitfield.class == Reg; |
40fb9820 | 1951 | |
40fb9820 L |
1952 | case imm: |
1953 | return (t.bitfield.imm8 | |
1954 | || t.bitfield.imm8s | |
1955 | || t.bitfield.imm16 | |
1956 | || t.bitfield.imm32 | |
1957 | || t.bitfield.imm32s | |
1958 | || t.bitfield.imm64); | |
1959 | ||
1960 | case disp: | |
1961 | return (t.bitfield.disp8 | |
1962 | || t.bitfield.disp16 | |
1963 | || t.bitfield.disp32 | |
1964 | || t.bitfield.disp32s | |
1965 | || t.bitfield.disp64); | |
1966 | ||
1967 | case anymem: | |
1968 | return (t.bitfield.disp8 | |
1969 | || t.bitfield.disp16 | |
1970 | || t.bitfield.disp32 | |
1971 | || t.bitfield.disp32s | |
1972 | || t.bitfield.disp64 | |
1973 | || t.bitfield.baseindex); | |
1974 | ||
1975 | default: | |
1976 | abort (); | |
1977 | } | |
2cfe26b6 AM |
1978 | |
1979 | return 0; | |
40fb9820 L |
1980 | } |
1981 | ||
7a54636a L |
1982 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size |
1983 | between operand GIVEN and opeand WANTED for instruction template T. */ | |
5c07affc L |
1984 | |
1985 | static INLINE int | |
7a54636a L |
1986 | match_operand_size (const insn_template *t, unsigned int wanted, |
1987 | unsigned int given) | |
5c07affc | 1988 | { |
3ac21baa JB |
1989 | return !((i.types[given].bitfield.byte |
1990 | && !t->operand_types[wanted].bitfield.byte) | |
1991 | || (i.types[given].bitfield.word | |
1992 | && !t->operand_types[wanted].bitfield.word) | |
1993 | || (i.types[given].bitfield.dword | |
1994 | && !t->operand_types[wanted].bitfield.dword) | |
1995 | || (i.types[given].bitfield.qword | |
1996 | && !t->operand_types[wanted].bitfield.qword) | |
1997 | || (i.types[given].bitfield.tbyte | |
1998 | && !t->operand_types[wanted].bitfield.tbyte)); | |
5c07affc L |
1999 | } |
2000 | ||
dd40ce22 L |
2001 | /* Return 1 if there is no conflict in SIMD register between operand |
2002 | GIVEN and opeand WANTED for instruction template T. */ | |
1b54b8d7 JB |
2003 | |
2004 | static INLINE int | |
dd40ce22 L |
2005 | match_simd_size (const insn_template *t, unsigned int wanted, |
2006 | unsigned int given) | |
1b54b8d7 | 2007 | { |
3ac21baa JB |
2008 | return !((i.types[given].bitfield.xmmword |
2009 | && !t->operand_types[wanted].bitfield.xmmword) | |
2010 | || (i.types[given].bitfield.ymmword | |
2011 | && !t->operand_types[wanted].bitfield.ymmword) | |
2012 | || (i.types[given].bitfield.zmmword | |
2013 | && !t->operand_types[wanted].bitfield.zmmword)); | |
1b54b8d7 JB |
2014 | } |
2015 | ||
7a54636a L |
2016 | /* Return 1 if there is no conflict in any size between operand GIVEN |
2017 | and opeand WANTED for instruction template T. */ | |
5c07affc L |
2018 | |
2019 | static INLINE int | |
dd40ce22 L |
2020 | match_mem_size (const insn_template *t, unsigned int wanted, |
2021 | unsigned int given) | |
5c07affc | 2022 | { |
7a54636a | 2023 | return (match_operand_size (t, wanted, given) |
3ac21baa | 2024 | && !((i.types[given].bitfield.unspecified |
af508cb9 | 2025 | && !i.broadcast |
3ac21baa JB |
2026 | && !t->operand_types[wanted].bitfield.unspecified) |
2027 | || (i.types[given].bitfield.fword | |
2028 | && !t->operand_types[wanted].bitfield.fword) | |
1b54b8d7 JB |
2029 | /* For scalar opcode templates to allow register and memory |
2030 | operands at the same time, some special casing is needed | |
d6793fa1 JB |
2031 | here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and |
2032 | down-conversion vpmov*. */ | |
3528c362 | 2033 | || ((t->operand_types[wanted].bitfield.class == RegSIMD |
1b54b8d7 | 2034 | && !t->opcode_modifier.broadcast |
3ac21baa JB |
2035 | && (t->operand_types[wanted].bitfield.byte |
2036 | || t->operand_types[wanted].bitfield.word | |
2037 | || t->operand_types[wanted].bitfield.dword | |
2038 | || t->operand_types[wanted].bitfield.qword)) | |
2039 | ? (i.types[given].bitfield.xmmword | |
2040 | || i.types[given].bitfield.ymmword | |
2041 | || i.types[given].bitfield.zmmword) | |
2042 | : !match_simd_size(t, wanted, given)))); | |
5c07affc L |
2043 | } |
2044 | ||
3ac21baa JB |
2045 | /* Return value has MATCH_STRAIGHT set if there is no size conflict on any |
2046 | operands for instruction template T, and it has MATCH_REVERSE set if there | |
2047 | is no size conflict on any operands for the template with operands reversed | |
2048 | (and the template allows for reversing in the first place). */ | |
5c07affc | 2049 | |
3ac21baa JB |
2050 | #define MATCH_STRAIGHT 1 |
2051 | #define MATCH_REVERSE 2 | |
2052 | ||
2053 | static INLINE unsigned int | |
d3ce72d0 | 2054 | operand_size_match (const insn_template *t) |
5c07affc | 2055 | { |
3ac21baa | 2056 | unsigned int j, match = MATCH_STRAIGHT; |
5c07affc L |
2057 | |
2058 | /* Don't check jump instructions. */ | |
2059 | if (t->opcode_modifier.jump | |
2060 | || t->opcode_modifier.jumpbyte | |
2061 | || t->opcode_modifier.jumpdword | |
2062 | || t->opcode_modifier.jumpintersegment) | |
2063 | return match; | |
2064 | ||
2065 | /* Check memory and accumulator operand size. */ | |
2066 | for (j = 0; j < i.operands; j++) | |
2067 | { | |
3528c362 JB |
2068 | if (i.types[j].bitfield.class != Reg |
2069 | && i.types[j].bitfield.class != RegSIMD | |
1b54b8d7 | 2070 | && t->operand_types[j].bitfield.anysize) |
5c07affc L |
2071 | continue; |
2072 | ||
bab6aec1 | 2073 | if (t->operand_types[j].bitfield.class == Reg |
7a54636a | 2074 | && !match_operand_size (t, j, j)) |
5c07affc L |
2075 | { |
2076 | match = 0; | |
2077 | break; | |
2078 | } | |
2079 | ||
3528c362 | 2080 | if (t->operand_types[j].bitfield.class == RegSIMD |
3ac21baa | 2081 | && !match_simd_size (t, j, j)) |
1b54b8d7 JB |
2082 | { |
2083 | match = 0; | |
2084 | break; | |
2085 | } | |
2086 | ||
2087 | if (t->operand_types[j].bitfield.acc | |
7a54636a | 2088 | && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j))) |
1b54b8d7 JB |
2089 | { |
2090 | match = 0; | |
2091 | break; | |
2092 | } | |
2093 | ||
c48dadc9 | 2094 | if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j)) |
5c07affc L |
2095 | { |
2096 | match = 0; | |
2097 | break; | |
2098 | } | |
2099 | } | |
2100 | ||
3ac21baa | 2101 | if (!t->opcode_modifier.d) |
891edac4 L |
2102 | { |
2103 | mismatch: | |
3ac21baa JB |
2104 | if (!match) |
2105 | i.error = operand_size_mismatch; | |
2106 | return match; | |
891edac4 | 2107 | } |
5c07affc L |
2108 | |
2109 | /* Check reverse. */ | |
f5eb1d70 | 2110 | gas_assert (i.operands >= 2 && i.operands <= 3); |
5c07affc | 2111 | |
f5eb1d70 | 2112 | for (j = 0; j < i.operands; j++) |
5c07affc | 2113 | { |
f5eb1d70 JB |
2114 | unsigned int given = i.operands - j - 1; |
2115 | ||
bab6aec1 | 2116 | if (t->operand_types[j].bitfield.class == Reg |
f5eb1d70 | 2117 | && !match_operand_size (t, j, given)) |
891edac4 | 2118 | goto mismatch; |
5c07affc | 2119 | |
3528c362 | 2120 | if (t->operand_types[j].bitfield.class == RegSIMD |
f5eb1d70 | 2121 | && !match_simd_size (t, j, given)) |
dbbc8b7e JB |
2122 | goto mismatch; |
2123 | ||
2124 | if (t->operand_types[j].bitfield.acc | |
f5eb1d70 JB |
2125 | && (!match_operand_size (t, j, given) |
2126 | || !match_simd_size (t, j, given))) | |
dbbc8b7e JB |
2127 | goto mismatch; |
2128 | ||
f5eb1d70 | 2129 | if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given)) |
891edac4 | 2130 | goto mismatch; |
5c07affc L |
2131 | } |
2132 | ||
3ac21baa | 2133 | return match | MATCH_REVERSE; |
5c07affc L |
2134 | } |
2135 | ||
c6fb90c8 | 2136 | static INLINE int |
40fb9820 L |
2137 | operand_type_match (i386_operand_type overlap, |
2138 | i386_operand_type given) | |
2139 | { | |
2140 | i386_operand_type temp = overlap; | |
2141 | ||
2142 | temp.bitfield.jumpabsolute = 0; | |
7d5e4556 | 2143 | temp.bitfield.unspecified = 0; |
5c07affc L |
2144 | temp.bitfield.byte = 0; |
2145 | temp.bitfield.word = 0; | |
2146 | temp.bitfield.dword = 0; | |
2147 | temp.bitfield.fword = 0; | |
2148 | temp.bitfield.qword = 0; | |
2149 | temp.bitfield.tbyte = 0; | |
2150 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 2151 | temp.bitfield.ymmword = 0; |
43234a1e | 2152 | temp.bitfield.zmmword = 0; |
0dfbf9d7 | 2153 | if (operand_type_all_zero (&temp)) |
891edac4 | 2154 | goto mismatch; |
40fb9820 | 2155 | |
891edac4 L |
2156 | if (given.bitfield.baseindex == overlap.bitfield.baseindex |
2157 | && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute) | |
2158 | return 1; | |
2159 | ||
2160 | mismatch: | |
a65babc9 | 2161 | i.error = operand_type_mismatch; |
891edac4 | 2162 | return 0; |
40fb9820 L |
2163 | } |
2164 | ||
7d5e4556 | 2165 | /* If given types g0 and g1 are registers they must be of the same type |
10c17abd JB |
2166 | unless the expected operand type register overlap is null. |
2167 | Memory operand size of certain SIMD instructions is also being checked | |
2168 | here. */ | |
40fb9820 | 2169 | |
c6fb90c8 | 2170 | static INLINE int |
dc821c5f | 2171 | operand_type_register_match (i386_operand_type g0, |
40fb9820 | 2172 | i386_operand_type t0, |
40fb9820 L |
2173 | i386_operand_type g1, |
2174 | i386_operand_type t1) | |
2175 | { | |
bab6aec1 | 2176 | if (g0.bitfield.class != Reg |
3528c362 | 2177 | && g0.bitfield.class != RegSIMD |
10c17abd JB |
2178 | && (!operand_type_check (g0, anymem) |
2179 | || g0.bitfield.unspecified | |
3528c362 | 2180 | || t0.bitfield.class != RegSIMD)) |
40fb9820 L |
2181 | return 1; |
2182 | ||
bab6aec1 | 2183 | if (g1.bitfield.class != Reg |
3528c362 | 2184 | && g1.bitfield.class != RegSIMD |
10c17abd JB |
2185 | && (!operand_type_check (g1, anymem) |
2186 | || g1.bitfield.unspecified | |
3528c362 | 2187 | || t1.bitfield.class != RegSIMD)) |
40fb9820 L |
2188 | return 1; |
2189 | ||
dc821c5f JB |
2190 | if (g0.bitfield.byte == g1.bitfield.byte |
2191 | && g0.bitfield.word == g1.bitfield.word | |
2192 | && g0.bitfield.dword == g1.bitfield.dword | |
10c17abd JB |
2193 | && g0.bitfield.qword == g1.bitfield.qword |
2194 | && g0.bitfield.xmmword == g1.bitfield.xmmword | |
2195 | && g0.bitfield.ymmword == g1.bitfield.ymmword | |
2196 | && g0.bitfield.zmmword == g1.bitfield.zmmword) | |
40fb9820 L |
2197 | return 1; |
2198 | ||
dc821c5f JB |
2199 | if (!(t0.bitfield.byte & t1.bitfield.byte) |
2200 | && !(t0.bitfield.word & t1.bitfield.word) | |
2201 | && !(t0.bitfield.dword & t1.bitfield.dword) | |
10c17abd JB |
2202 | && !(t0.bitfield.qword & t1.bitfield.qword) |
2203 | && !(t0.bitfield.xmmword & t1.bitfield.xmmword) | |
2204 | && !(t0.bitfield.ymmword & t1.bitfield.ymmword) | |
2205 | && !(t0.bitfield.zmmword & t1.bitfield.zmmword)) | |
891edac4 L |
2206 | return 1; |
2207 | ||
a65babc9 | 2208 | i.error = register_type_mismatch; |
891edac4 L |
2209 | |
2210 | return 0; | |
40fb9820 L |
2211 | } |
2212 | ||
4c692bc7 JB |
2213 | static INLINE unsigned int |
2214 | register_number (const reg_entry *r) | |
2215 | { | |
2216 | unsigned int nr = r->reg_num; | |
2217 | ||
2218 | if (r->reg_flags & RegRex) | |
2219 | nr += 8; | |
2220 | ||
200cbe0f L |
2221 | if (r->reg_flags & RegVRex) |
2222 | nr += 16; | |
2223 | ||
4c692bc7 JB |
2224 | return nr; |
2225 | } | |
2226 | ||
252b5132 | 2227 | static INLINE unsigned int |
40fb9820 | 2228 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 2229 | { |
b5014f7a | 2230 | if (t.bitfield.disp8) |
40fb9820 L |
2231 | return 1; |
2232 | else if (t.bitfield.disp16 | |
2233 | || t.bitfield.disp32 | |
2234 | || t.bitfield.disp32s) | |
2235 | return 2; | |
2236 | else | |
2237 | return 0; | |
252b5132 RH |
2238 | } |
2239 | ||
2240 | static INLINE int | |
65879393 | 2241 | fits_in_signed_byte (addressT num) |
252b5132 | 2242 | { |
65879393 | 2243 | return num + 0x80 <= 0xff; |
47926f60 | 2244 | } |
252b5132 RH |
2245 | |
2246 | static INLINE int | |
65879393 | 2247 | fits_in_unsigned_byte (addressT num) |
252b5132 | 2248 | { |
65879393 | 2249 | return num <= 0xff; |
47926f60 | 2250 | } |
252b5132 RH |
2251 | |
2252 | static INLINE int | |
65879393 | 2253 | fits_in_unsigned_word (addressT num) |
252b5132 | 2254 | { |
65879393 | 2255 | return num <= 0xffff; |
47926f60 | 2256 | } |
252b5132 RH |
2257 | |
2258 | static INLINE int | |
65879393 | 2259 | fits_in_signed_word (addressT num) |
252b5132 | 2260 | { |
65879393 | 2261 | return num + 0x8000 <= 0xffff; |
47926f60 | 2262 | } |
2a962e6d | 2263 | |
3e73aa7c | 2264 | static INLINE int |
65879393 | 2265 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2266 | { |
2267 | #ifndef BFD64 | |
2268 | return 1; | |
2269 | #else | |
65879393 | 2270 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2271 | #endif |
2272 | } /* fits_in_signed_long() */ | |
2a962e6d | 2273 | |
3e73aa7c | 2274 | static INLINE int |
65879393 | 2275 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2276 | { |
2277 | #ifndef BFD64 | |
2278 | return 1; | |
2279 | #else | |
65879393 | 2280 | return num <= 0xffffffff; |
3e73aa7c JH |
2281 | #endif |
2282 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2283 | |
43234a1e | 2284 | static INLINE int |
b5014f7a | 2285 | fits_in_disp8 (offsetT num) |
43234a1e L |
2286 | { |
2287 | int shift = i.memshift; | |
2288 | unsigned int mask; | |
2289 | ||
2290 | if (shift == -1) | |
2291 | abort (); | |
2292 | ||
2293 | mask = (1 << shift) - 1; | |
2294 | ||
2295 | /* Return 0 if NUM isn't properly aligned. */ | |
2296 | if ((num & mask)) | |
2297 | return 0; | |
2298 | ||
2299 | /* Check if NUM will fit in 8bit after shift. */ | |
2300 | return fits_in_signed_byte (num >> shift); | |
2301 | } | |
2302 | ||
a683cc34 SP |
2303 | static INLINE int |
2304 | fits_in_imm4 (offsetT num) | |
2305 | { | |
2306 | return (num & 0xf) == num; | |
2307 | } | |
2308 | ||
40fb9820 | 2309 | static i386_operand_type |
e3bb37b5 | 2310 | smallest_imm_type (offsetT num) |
252b5132 | 2311 | { |
40fb9820 | 2312 | i386_operand_type t; |
7ab9ffdd | 2313 | |
0dfbf9d7 | 2314 | operand_type_set (&t, 0); |
40fb9820 L |
2315 | t.bitfield.imm64 = 1; |
2316 | ||
2317 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2318 | { |
2319 | /* This code is disabled on the 486 because all the Imm1 forms | |
2320 | in the opcode table are slower on the i486. They're the | |
2321 | versions with the implicitly specified single-position | |
2322 | displacement, which has another syntax if you really want to | |
2323 | use that form. */ | |
40fb9820 L |
2324 | t.bitfield.imm1 = 1; |
2325 | t.bitfield.imm8 = 1; | |
2326 | t.bitfield.imm8s = 1; | |
2327 | t.bitfield.imm16 = 1; | |
2328 | t.bitfield.imm32 = 1; | |
2329 | t.bitfield.imm32s = 1; | |
2330 | } | |
2331 | else if (fits_in_signed_byte (num)) | |
2332 | { | |
2333 | t.bitfield.imm8 = 1; | |
2334 | t.bitfield.imm8s = 1; | |
2335 | t.bitfield.imm16 = 1; | |
2336 | t.bitfield.imm32 = 1; | |
2337 | t.bitfield.imm32s = 1; | |
2338 | } | |
2339 | else if (fits_in_unsigned_byte (num)) | |
2340 | { | |
2341 | t.bitfield.imm8 = 1; | |
2342 | t.bitfield.imm16 = 1; | |
2343 | t.bitfield.imm32 = 1; | |
2344 | t.bitfield.imm32s = 1; | |
2345 | } | |
2346 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2347 | { | |
2348 | t.bitfield.imm16 = 1; | |
2349 | t.bitfield.imm32 = 1; | |
2350 | t.bitfield.imm32s = 1; | |
2351 | } | |
2352 | else if (fits_in_signed_long (num)) | |
2353 | { | |
2354 | t.bitfield.imm32 = 1; | |
2355 | t.bitfield.imm32s = 1; | |
2356 | } | |
2357 | else if (fits_in_unsigned_long (num)) | |
2358 | t.bitfield.imm32 = 1; | |
2359 | ||
2360 | return t; | |
47926f60 | 2361 | } |
252b5132 | 2362 | |
847f7ad4 | 2363 | static offsetT |
e3bb37b5 | 2364 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2365 | { |
508866be | 2366 | addressT mask; |
ba2adb93 | 2367 | |
847f7ad4 AM |
2368 | switch (size) |
2369 | { | |
508866be L |
2370 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2371 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 2372 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
2373 | #ifdef BFD64 |
2374 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
2375 | #endif | |
47926f60 | 2376 | default: abort (); |
847f7ad4 AM |
2377 | } |
2378 | ||
9de868bf L |
2379 | #ifdef BFD64 |
2380 | /* If BFD64, sign extend val for 32bit address mode. */ | |
2381 | if (flag_code != CODE_64BIT | |
2382 | || i.prefix[ADDR_PREFIX]) | |
3e73aa7c JH |
2383 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
2384 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
fa289fb8 | 2385 | #endif |
ba2adb93 | 2386 | |
47926f60 | 2387 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
2388 | { |
2389 | char buf1[40], buf2[40]; | |
2390 | ||
2391 | sprint_value (buf1, val); | |
2392 | sprint_value (buf2, val & mask); | |
2393 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
2394 | } | |
2395 | return val & mask; | |
2396 | } | |
2397 | ||
c32fa91d L |
2398 | enum PREFIX_GROUP |
2399 | { | |
2400 | PREFIX_EXIST = 0, | |
2401 | PREFIX_LOCK, | |
2402 | PREFIX_REP, | |
04ef582a | 2403 | PREFIX_DS, |
c32fa91d L |
2404 | PREFIX_OTHER |
2405 | }; | |
2406 | ||
2407 | /* Returns | |
2408 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2409 | same class already exists. | |
2410 | b. PREFIX_LOCK if lock prefix is added. | |
2411 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2412 | d. PREFIX_DS if ds prefix is added. |
2413 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2414 | */ |
2415 | ||
2416 | static enum PREFIX_GROUP | |
e3bb37b5 | 2417 | add_prefix (unsigned int prefix) |
252b5132 | 2418 | { |
c32fa91d | 2419 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2420 | unsigned int q; |
252b5132 | 2421 | |
29b0f896 AM |
2422 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2423 | && flag_code == CODE_64BIT) | |
b1905489 | 2424 | { |
161a04f6 | 2425 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
44846f29 JB |
2426 | || (i.prefix[REX_PREFIX] & prefix & REX_R) |
2427 | || (i.prefix[REX_PREFIX] & prefix & REX_X) | |
2428 | || (i.prefix[REX_PREFIX] & prefix & REX_B)) | |
c32fa91d | 2429 | ret = PREFIX_EXIST; |
b1905489 JB |
2430 | q = REX_PREFIX; |
2431 | } | |
3e73aa7c | 2432 | else |
b1905489 JB |
2433 | { |
2434 | switch (prefix) | |
2435 | { | |
2436 | default: | |
2437 | abort (); | |
2438 | ||
b1905489 | 2439 | case DS_PREFIX_OPCODE: |
04ef582a L |
2440 | ret = PREFIX_DS; |
2441 | /* Fall through. */ | |
2442 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2443 | case ES_PREFIX_OPCODE: |
2444 | case FS_PREFIX_OPCODE: | |
2445 | case GS_PREFIX_OPCODE: | |
2446 | case SS_PREFIX_OPCODE: | |
2447 | q = SEG_PREFIX; | |
2448 | break; | |
2449 | ||
2450 | case REPNE_PREFIX_OPCODE: | |
2451 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2452 | q = REP_PREFIX; |
2453 | ret = PREFIX_REP; | |
2454 | break; | |
2455 | ||
b1905489 | 2456 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2457 | q = LOCK_PREFIX; |
2458 | ret = PREFIX_LOCK; | |
b1905489 JB |
2459 | break; |
2460 | ||
2461 | case FWAIT_OPCODE: | |
2462 | q = WAIT_PREFIX; | |
2463 | break; | |
2464 | ||
2465 | case ADDR_PREFIX_OPCODE: | |
2466 | q = ADDR_PREFIX; | |
2467 | break; | |
2468 | ||
2469 | case DATA_PREFIX_OPCODE: | |
2470 | q = DATA_PREFIX; | |
2471 | break; | |
2472 | } | |
2473 | if (i.prefix[q] != 0) | |
c32fa91d | 2474 | ret = PREFIX_EXIST; |
b1905489 | 2475 | } |
252b5132 | 2476 | |
b1905489 | 2477 | if (ret) |
252b5132 | 2478 | { |
b1905489 JB |
2479 | if (!i.prefix[q]) |
2480 | ++i.prefixes; | |
2481 | i.prefix[q] |= prefix; | |
252b5132 | 2482 | } |
b1905489 JB |
2483 | else |
2484 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2485 | |
252b5132 RH |
2486 | return ret; |
2487 | } | |
2488 | ||
2489 | static void | |
78f12dd3 | 2490 | update_code_flag (int value, int check) |
eecb386c | 2491 | { |
78f12dd3 L |
2492 | PRINTF_LIKE ((*as_error)); |
2493 | ||
1e9cc1c2 | 2494 | flag_code = (enum flag_code) value; |
40fb9820 L |
2495 | if (flag_code == CODE_64BIT) |
2496 | { | |
2497 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2498 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2499 | } |
2500 | else | |
2501 | { | |
2502 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2503 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2504 | } |
2505 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2506 | { |
78f12dd3 L |
2507 | if (check) |
2508 | as_error = as_fatal; | |
2509 | else | |
2510 | as_error = as_bad; | |
2511 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2512 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2513 | } |
40fb9820 | 2514 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2515 | { |
78f12dd3 L |
2516 | if (check) |
2517 | as_error = as_fatal; | |
2518 | else | |
2519 | as_error = as_bad; | |
2520 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2521 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2522 | } |
eecb386c AM |
2523 | stackop_size = '\0'; |
2524 | } | |
2525 | ||
78f12dd3 L |
2526 | static void |
2527 | set_code_flag (int value) | |
2528 | { | |
2529 | update_code_flag (value, 0); | |
2530 | } | |
2531 | ||
eecb386c | 2532 | static void |
e3bb37b5 | 2533 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2534 | { |
1e9cc1c2 | 2535 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2536 | if (flag_code != CODE_16BIT) |
2537 | abort (); | |
2538 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2539 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2540 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2541 | } |
2542 | ||
2543 | static void | |
e3bb37b5 | 2544 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2545 | { |
2546 | /* Find out if register prefixing is specified. */ | |
2547 | int ask_naked_reg = 0; | |
2548 | ||
2549 | SKIP_WHITESPACE (); | |
29b0f896 | 2550 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2551 | { |
d02603dc NC |
2552 | char *string; |
2553 | int e = get_symbol_name (&string); | |
252b5132 | 2554 | |
47926f60 | 2555 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2556 | ask_naked_reg = 1; |
47926f60 | 2557 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2558 | ask_naked_reg = -1; |
2559 | else | |
d0b47220 | 2560 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2561 | (void) restore_line_pointer (e); |
252b5132 RH |
2562 | } |
2563 | demand_empty_rest_of_line (); | |
c3332e24 | 2564 | |
252b5132 RH |
2565 | intel_syntax = syntax_flag; |
2566 | ||
2567 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2568 | allow_naked_reg = (intel_syntax |
2569 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2570 | else |
2571 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2572 | |
ee86248c | 2573 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2574 | |
e4a3b5a4 | 2575 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2576 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2577 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2578 | } |
2579 | ||
1efbbeb4 L |
2580 | static void |
2581 | set_intel_mnemonic (int mnemonic_flag) | |
2582 | { | |
e1d4d893 | 2583 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2584 | } |
2585 | ||
db51cc60 L |
2586 | static void |
2587 | set_allow_index_reg (int flag) | |
2588 | { | |
2589 | allow_index_reg = flag; | |
2590 | } | |
2591 | ||
cb19c032 | 2592 | static void |
7bab8ab5 | 2593 | set_check (int what) |
cb19c032 | 2594 | { |
7bab8ab5 JB |
2595 | enum check_kind *kind; |
2596 | const char *str; | |
2597 | ||
2598 | if (what) | |
2599 | { | |
2600 | kind = &operand_check; | |
2601 | str = "operand"; | |
2602 | } | |
2603 | else | |
2604 | { | |
2605 | kind = &sse_check; | |
2606 | str = "sse"; | |
2607 | } | |
2608 | ||
cb19c032 L |
2609 | SKIP_WHITESPACE (); |
2610 | ||
2611 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2612 | { | |
d02603dc NC |
2613 | char *string; |
2614 | int e = get_symbol_name (&string); | |
cb19c032 L |
2615 | |
2616 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2617 | *kind = check_none; |
cb19c032 | 2618 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2619 | *kind = check_warning; |
cb19c032 | 2620 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2621 | *kind = check_error; |
cb19c032 | 2622 | else |
7bab8ab5 | 2623 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2624 | (void) restore_line_pointer (e); |
cb19c032 L |
2625 | } |
2626 | else | |
7bab8ab5 | 2627 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2628 | |
2629 | demand_empty_rest_of_line (); | |
2630 | } | |
2631 | ||
8a9036a4 L |
2632 | static void |
2633 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2634 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2635 | { |
2636 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2637 | static const char *arch; | |
2638 | ||
2639 | /* Intel LIOM is only supported on ELF. */ | |
2640 | if (!IS_ELF) | |
2641 | return; | |
2642 | ||
2643 | if (!arch) | |
2644 | { | |
2645 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2646 | use default_arch. */ | |
2647 | arch = cpu_arch_name; | |
2648 | if (!arch) | |
2649 | arch = default_arch; | |
2650 | } | |
2651 | ||
81486035 L |
2652 | /* If we are targeting Intel MCU, we must enable it. */ |
2653 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU | |
2654 | || new_flag.bitfield.cpuiamcu) | |
2655 | return; | |
2656 | ||
3632d14b | 2657 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 | 2658 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1e9cc1c2 | 2659 | || new_flag.bitfield.cpul1om) |
8a9036a4 | 2660 | return; |
76ba9986 | 2661 | |
7a9068fe L |
2662 | /* If we are targeting Intel K1OM, we must enable it. */ |
2663 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM | |
2664 | || new_flag.bitfield.cpuk1om) | |
2665 | return; | |
2666 | ||
8a9036a4 L |
2667 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2668 | #endif | |
2669 | } | |
2670 | ||
e413e4e9 | 2671 | static void |
e3bb37b5 | 2672 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2673 | { |
47926f60 | 2674 | SKIP_WHITESPACE (); |
e413e4e9 | 2675 | |
29b0f896 | 2676 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 | 2677 | { |
d02603dc NC |
2678 | char *string; |
2679 | int e = get_symbol_name (&string); | |
91d6fa6a | 2680 | unsigned int j; |
40fb9820 | 2681 | i386_cpu_flags flags; |
e413e4e9 | 2682 | |
91d6fa6a | 2683 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
e413e4e9 | 2684 | { |
91d6fa6a | 2685 | if (strcmp (string, cpu_arch[j].name) == 0) |
e413e4e9 | 2686 | { |
91d6fa6a | 2687 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
8a9036a4 | 2688 | |
5c6af06e JB |
2689 | if (*string != '.') |
2690 | { | |
91d6fa6a | 2691 | cpu_arch_name = cpu_arch[j].name; |
5c6af06e | 2692 | cpu_sub_arch_name = NULL; |
91d6fa6a | 2693 | cpu_arch_flags = cpu_arch[j].flags; |
40fb9820 L |
2694 | if (flag_code == CODE_64BIT) |
2695 | { | |
2696 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2697 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2698 | } | |
2699 | else | |
2700 | { | |
2701 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2702 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2703 | } | |
91d6fa6a NC |
2704 | cpu_arch_isa = cpu_arch[j].type; |
2705 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
ccc9c027 L |
2706 | if (!cpu_arch_tune_set) |
2707 | { | |
2708 | cpu_arch_tune = cpu_arch_isa; | |
2709 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2710 | } | |
5c6af06e JB |
2711 | break; |
2712 | } | |
40fb9820 | 2713 | |
293f5f65 L |
2714 | flags = cpu_flags_or (cpu_arch_flags, |
2715 | cpu_arch[j].flags); | |
81486035 | 2716 | |
5b64d091 | 2717 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2718 | { |
6305a203 L |
2719 | if (cpu_sub_arch_name) |
2720 | { | |
2721 | char *name = cpu_sub_arch_name; | |
2722 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 2723 | cpu_arch[j].name, |
1bf57e9f | 2724 | (const char *) NULL); |
6305a203 L |
2725 | free (name); |
2726 | } | |
2727 | else | |
91d6fa6a | 2728 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
40fb9820 | 2729 | cpu_arch_flags = flags; |
a586129e | 2730 | cpu_arch_isa_flags = flags; |
5c6af06e | 2731 | } |
0089dace L |
2732 | else |
2733 | cpu_arch_isa_flags | |
2734 | = cpu_flags_or (cpu_arch_isa_flags, | |
2735 | cpu_arch[j].flags); | |
d02603dc | 2736 | (void) restore_line_pointer (e); |
5c6af06e JB |
2737 | demand_empty_rest_of_line (); |
2738 | return; | |
e413e4e9 AM |
2739 | } |
2740 | } | |
293f5f65 L |
2741 | |
2742 | if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) | |
2743 | { | |
33eaf5de | 2744 | /* Disable an ISA extension. */ |
293f5f65 L |
2745 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
2746 | if (strcmp (string + 1, cpu_noarch [j].name) == 0) | |
2747 | { | |
2748 | flags = cpu_flags_and_not (cpu_arch_flags, | |
2749 | cpu_noarch[j].flags); | |
2750 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2751 | { | |
2752 | if (cpu_sub_arch_name) | |
2753 | { | |
2754 | char *name = cpu_sub_arch_name; | |
2755 | cpu_sub_arch_name = concat (name, string, | |
2756 | (const char *) NULL); | |
2757 | free (name); | |
2758 | } | |
2759 | else | |
2760 | cpu_sub_arch_name = xstrdup (string); | |
2761 | cpu_arch_flags = flags; | |
2762 | cpu_arch_isa_flags = flags; | |
2763 | } | |
2764 | (void) restore_line_pointer (e); | |
2765 | demand_empty_rest_of_line (); | |
2766 | return; | |
2767 | } | |
2768 | ||
2769 | j = ARRAY_SIZE (cpu_arch); | |
2770 | } | |
2771 | ||
91d6fa6a | 2772 | if (j >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2773 | as_bad (_("no such architecture: `%s'"), string); |
2774 | ||
2775 | *input_line_pointer = e; | |
2776 | } | |
2777 | else | |
2778 | as_bad (_("missing cpu architecture")); | |
2779 | ||
fddf5b5b AM |
2780 | no_cond_jump_promotion = 0; |
2781 | if (*input_line_pointer == ',' | |
29b0f896 | 2782 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 2783 | { |
d02603dc NC |
2784 | char *string; |
2785 | char e; | |
2786 | ||
2787 | ++input_line_pointer; | |
2788 | e = get_symbol_name (&string); | |
fddf5b5b AM |
2789 | |
2790 | if (strcmp (string, "nojumps") == 0) | |
2791 | no_cond_jump_promotion = 1; | |
2792 | else if (strcmp (string, "jumps") == 0) | |
2793 | ; | |
2794 | else | |
2795 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2796 | ||
d02603dc | 2797 | (void) restore_line_pointer (e); |
fddf5b5b AM |
2798 | } |
2799 | ||
e413e4e9 AM |
2800 | demand_empty_rest_of_line (); |
2801 | } | |
2802 | ||
8a9036a4 L |
2803 | enum bfd_architecture |
2804 | i386_arch (void) | |
2805 | { | |
3632d14b | 2806 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2807 | { |
2808 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2809 | || flag_code != CODE_64BIT) | |
2810 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2811 | return bfd_arch_l1om; | |
2812 | } | |
7a9068fe L |
2813 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2814 | { | |
2815 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2816 | || flag_code != CODE_64BIT) | |
2817 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2818 | return bfd_arch_k1om; | |
2819 | } | |
81486035 L |
2820 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
2821 | { | |
2822 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2823 | || flag_code == CODE_64BIT) | |
2824 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2825 | return bfd_arch_iamcu; | |
2826 | } | |
8a9036a4 L |
2827 | else |
2828 | return bfd_arch_i386; | |
2829 | } | |
2830 | ||
b9d79e03 | 2831 | unsigned long |
7016a5d5 | 2832 | i386_mach (void) |
b9d79e03 | 2833 | { |
351f65ca | 2834 | if (!strncmp (default_arch, "x86_64", 6)) |
8a9036a4 | 2835 | { |
3632d14b | 2836 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 2837 | { |
351f65ca L |
2838 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
2839 | || default_arch[6] != '\0') | |
8a9036a4 L |
2840 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
2841 | return bfd_mach_l1om; | |
2842 | } | |
7a9068fe L |
2843 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2844 | { | |
2845 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2846 | || default_arch[6] != '\0') | |
2847 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2848 | return bfd_mach_k1om; | |
2849 | } | |
351f65ca | 2850 | else if (default_arch[6] == '\0') |
8a9036a4 | 2851 | return bfd_mach_x86_64; |
351f65ca L |
2852 | else |
2853 | return bfd_mach_x64_32; | |
8a9036a4 | 2854 | } |
5197d474 L |
2855 | else if (!strcmp (default_arch, "i386") |
2856 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
2857 | { |
2858 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
2859 | { | |
2860 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
2861 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2862 | return bfd_mach_i386_iamcu; | |
2863 | } | |
2864 | else | |
2865 | return bfd_mach_i386_i386; | |
2866 | } | |
b9d79e03 | 2867 | else |
2b5d6a91 | 2868 | as_fatal (_("unknown architecture")); |
b9d79e03 | 2869 | } |
b9d79e03 | 2870 | \f |
252b5132 | 2871 | void |
7016a5d5 | 2872 | md_begin (void) |
252b5132 RH |
2873 | { |
2874 | const char *hash_err; | |
2875 | ||
86fa6981 L |
2876 | /* Support pseudo prefixes like {disp32}. */ |
2877 | lex_type ['{'] = LEX_BEGIN_NAME; | |
2878 | ||
47926f60 | 2879 | /* Initialize op_hash hash table. */ |
252b5132 RH |
2880 | op_hash = hash_new (); |
2881 | ||
2882 | { | |
d3ce72d0 | 2883 | const insn_template *optab; |
29b0f896 | 2884 | templates *core_optab; |
252b5132 | 2885 | |
47926f60 KH |
2886 | /* Setup for loop. */ |
2887 | optab = i386_optab; | |
add39d23 | 2888 | core_optab = XNEW (templates); |
252b5132 RH |
2889 | core_optab->start = optab; |
2890 | ||
2891 | while (1) | |
2892 | { | |
2893 | ++optab; | |
2894 | if (optab->name == NULL | |
2895 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
2896 | { | |
2897 | /* different name --> ship out current template list; | |
47926f60 | 2898 | add to hash table; & begin anew. */ |
252b5132 RH |
2899 | core_optab->end = optab; |
2900 | hash_err = hash_insert (op_hash, | |
2901 | (optab - 1)->name, | |
5a49b8ac | 2902 | (void *) core_optab); |
252b5132 RH |
2903 | if (hash_err) |
2904 | { | |
b37df7c4 | 2905 | as_fatal (_("can't hash %s: %s"), |
252b5132 RH |
2906 | (optab - 1)->name, |
2907 | hash_err); | |
2908 | } | |
2909 | if (optab->name == NULL) | |
2910 | break; | |
add39d23 | 2911 | core_optab = XNEW (templates); |
252b5132 RH |
2912 | core_optab->start = optab; |
2913 | } | |
2914 | } | |
2915 | } | |
2916 | ||
47926f60 | 2917 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
2918 | reg_hash = hash_new (); |
2919 | { | |
29b0f896 | 2920 | const reg_entry *regtab; |
c3fe08fa | 2921 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 2922 | |
c3fe08fa | 2923 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 2924 | { |
5a49b8ac | 2925 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 2926 | if (hash_err) |
b37df7c4 | 2927 | as_fatal (_("can't hash %s: %s"), |
3e73aa7c JH |
2928 | regtab->reg_name, |
2929 | hash_err); | |
252b5132 RH |
2930 | } |
2931 | } | |
2932 | ||
47926f60 | 2933 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 2934 | { |
29b0f896 AM |
2935 | int c; |
2936 | char *p; | |
252b5132 RH |
2937 | |
2938 | for (c = 0; c < 256; c++) | |
2939 | { | |
3882b010 | 2940 | if (ISDIGIT (c)) |
252b5132 RH |
2941 | { |
2942 | digit_chars[c] = c; | |
2943 | mnemonic_chars[c] = c; | |
2944 | register_chars[c] = c; | |
2945 | operand_chars[c] = c; | |
2946 | } | |
3882b010 | 2947 | else if (ISLOWER (c)) |
252b5132 RH |
2948 | { |
2949 | mnemonic_chars[c] = c; | |
2950 | register_chars[c] = c; | |
2951 | operand_chars[c] = c; | |
2952 | } | |
3882b010 | 2953 | else if (ISUPPER (c)) |
252b5132 | 2954 | { |
3882b010 | 2955 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
2956 | register_chars[c] = mnemonic_chars[c]; |
2957 | operand_chars[c] = c; | |
2958 | } | |
43234a1e | 2959 | else if (c == '{' || c == '}') |
86fa6981 L |
2960 | { |
2961 | mnemonic_chars[c] = c; | |
2962 | operand_chars[c] = c; | |
2963 | } | |
252b5132 | 2964 | |
3882b010 | 2965 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
2966 | identifier_chars[c] = c; |
2967 | else if (c >= 128) | |
2968 | { | |
2969 | identifier_chars[c] = c; | |
2970 | operand_chars[c] = c; | |
2971 | } | |
2972 | } | |
2973 | ||
2974 | #ifdef LEX_AT | |
2975 | identifier_chars['@'] = '@'; | |
32137342 NC |
2976 | #endif |
2977 | #ifdef LEX_QM | |
2978 | identifier_chars['?'] = '?'; | |
2979 | operand_chars['?'] = '?'; | |
252b5132 | 2980 | #endif |
252b5132 | 2981 | digit_chars['-'] = '-'; |
c0f3af97 | 2982 | mnemonic_chars['_'] = '_'; |
791fe849 | 2983 | mnemonic_chars['-'] = '-'; |
0003779b | 2984 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
2985 | identifier_chars['_'] = '_'; |
2986 | identifier_chars['.'] = '.'; | |
2987 | ||
2988 | for (p = operand_special_chars; *p != '\0'; p++) | |
2989 | operand_chars[(unsigned char) *p] = *p; | |
2990 | } | |
2991 | ||
a4447b93 RH |
2992 | if (flag_code == CODE_64BIT) |
2993 | { | |
ca19b261 KT |
2994 | #if defined (OBJ_COFF) && defined (TE_PE) |
2995 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
2996 | ? 32 : 16); | |
2997 | #else | |
a4447b93 | 2998 | x86_dwarf2_return_column = 16; |
ca19b261 | 2999 | #endif |
61ff971f | 3000 | x86_cie_data_alignment = -8; |
a4447b93 RH |
3001 | } |
3002 | else | |
3003 | { | |
3004 | x86_dwarf2_return_column = 8; | |
3005 | x86_cie_data_alignment = -4; | |
3006 | } | |
252b5132 RH |
3007 | } |
3008 | ||
3009 | void | |
e3bb37b5 | 3010 | i386_print_statistics (FILE *file) |
252b5132 RH |
3011 | { |
3012 | hash_print_statistics (file, "i386 opcode", op_hash); | |
3013 | hash_print_statistics (file, "i386 register", reg_hash); | |
3014 | } | |
3015 | \f | |
252b5132 RH |
3016 | #ifdef DEBUG386 |
3017 | ||
ce8a8b2f | 3018 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 3019 | static void pte (insn_template *); |
40fb9820 | 3020 | static void pt (i386_operand_type); |
e3bb37b5 L |
3021 | static void pe (expressionS *); |
3022 | static void ps (symbolS *); | |
252b5132 RH |
3023 | |
3024 | static void | |
2c703856 | 3025 | pi (const char *line, i386_insn *x) |
252b5132 | 3026 | { |
09137c09 | 3027 | unsigned int j; |
252b5132 RH |
3028 | |
3029 | fprintf (stdout, "%s: template ", line); | |
3030 | pte (&x->tm); | |
09f131f2 JH |
3031 | fprintf (stdout, " address: base %s index %s scale %x\n", |
3032 | x->base_reg ? x->base_reg->reg_name : "none", | |
3033 | x->index_reg ? x->index_reg->reg_name : "none", | |
3034 | x->log2_scale_factor); | |
3035 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 3036 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
3037 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
3038 | x->sib.base, x->sib.index, x->sib.scale); | |
3039 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
3040 | (x->rex & REX_W) != 0, |
3041 | (x->rex & REX_R) != 0, | |
3042 | (x->rex & REX_X) != 0, | |
3043 | (x->rex & REX_B) != 0); | |
09137c09 | 3044 | for (j = 0; j < x->operands; j++) |
252b5132 | 3045 | { |
09137c09 SP |
3046 | fprintf (stdout, " #%d: ", j + 1); |
3047 | pt (x->types[j]); | |
252b5132 | 3048 | fprintf (stdout, "\n"); |
bab6aec1 | 3049 | if (x->types[j].bitfield.class == Reg |
3528c362 JB |
3050 | || x->types[j].bitfield.class == RegMMX |
3051 | || x->types[j].bitfield.class == RegSIMD | |
00cee14f | 3052 | || x->types[j].bitfield.class == SReg |
4a5c67ed JB |
3053 | || x->types[j].bitfield.class == RegCR |
3054 | || x->types[j].bitfield.class == RegDR | |
3055 | || x->types[j].bitfield.class == RegTR) | |
09137c09 SP |
3056 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); |
3057 | if (operand_type_check (x->types[j], imm)) | |
3058 | pe (x->op[j].imms); | |
3059 | if (operand_type_check (x->types[j], disp)) | |
3060 | pe (x->op[j].disps); | |
252b5132 RH |
3061 | } |
3062 | } | |
3063 | ||
3064 | static void | |
d3ce72d0 | 3065 | pte (insn_template *t) |
252b5132 | 3066 | { |
09137c09 | 3067 | unsigned int j; |
252b5132 | 3068 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 3069 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
3070 | if (t->extension_opcode != None) |
3071 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 3072 | if (t->opcode_modifier.d) |
252b5132 | 3073 | fprintf (stdout, "D"); |
40fb9820 | 3074 | if (t->opcode_modifier.w) |
252b5132 RH |
3075 | fprintf (stdout, "W"); |
3076 | fprintf (stdout, "\n"); | |
09137c09 | 3077 | for (j = 0; j < t->operands; j++) |
252b5132 | 3078 | { |
09137c09 SP |
3079 | fprintf (stdout, " #%d type ", j + 1); |
3080 | pt (t->operand_types[j]); | |
252b5132 RH |
3081 | fprintf (stdout, "\n"); |
3082 | } | |
3083 | } | |
3084 | ||
3085 | static void | |
e3bb37b5 | 3086 | pe (expressionS *e) |
252b5132 | 3087 | { |
24eab124 | 3088 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
3089 | fprintf (stdout, " add_number %ld (%lx)\n", |
3090 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
3091 | if (e->X_add_symbol) |
3092 | { | |
3093 | fprintf (stdout, " add_symbol "); | |
3094 | ps (e->X_add_symbol); | |
3095 | fprintf (stdout, "\n"); | |
3096 | } | |
3097 | if (e->X_op_symbol) | |
3098 | { | |
3099 | fprintf (stdout, " op_symbol "); | |
3100 | ps (e->X_op_symbol); | |
3101 | fprintf (stdout, "\n"); | |
3102 | } | |
3103 | } | |
3104 | ||
3105 | static void | |
e3bb37b5 | 3106 | ps (symbolS *s) |
252b5132 RH |
3107 | { |
3108 | fprintf (stdout, "%s type %s%s", | |
3109 | S_GET_NAME (s), | |
3110 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
3111 | segment_name (S_GET_SEGMENT (s))); | |
3112 | } | |
3113 | ||
7b81dfbb | 3114 | static struct type_name |
252b5132 | 3115 | { |
40fb9820 L |
3116 | i386_operand_type mask; |
3117 | const char *name; | |
252b5132 | 3118 | } |
7b81dfbb | 3119 | const type_names[] = |
252b5132 | 3120 | { |
40fb9820 L |
3121 | { OPERAND_TYPE_REG8, "r8" }, |
3122 | { OPERAND_TYPE_REG16, "r16" }, | |
3123 | { OPERAND_TYPE_REG32, "r32" }, | |
3124 | { OPERAND_TYPE_REG64, "r64" }, | |
2c703856 JB |
3125 | { OPERAND_TYPE_ACC8, "acc8" }, |
3126 | { OPERAND_TYPE_ACC16, "acc16" }, | |
3127 | { OPERAND_TYPE_ACC32, "acc32" }, | |
3128 | { OPERAND_TYPE_ACC64, "acc64" }, | |
40fb9820 L |
3129 | { OPERAND_TYPE_IMM8, "i8" }, |
3130 | { OPERAND_TYPE_IMM8, "i8s" }, | |
3131 | { OPERAND_TYPE_IMM16, "i16" }, | |
3132 | { OPERAND_TYPE_IMM32, "i32" }, | |
3133 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
3134 | { OPERAND_TYPE_IMM64, "i64" }, | |
3135 | { OPERAND_TYPE_IMM1, "i1" }, | |
3136 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
3137 | { OPERAND_TYPE_DISP8, "d8" }, | |
3138 | { OPERAND_TYPE_DISP16, "d16" }, | |
3139 | { OPERAND_TYPE_DISP32, "d32" }, | |
3140 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
3141 | { OPERAND_TYPE_DISP64, "d64" }, | |
3142 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
3143 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
3144 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
3145 | { OPERAND_TYPE_TEST, "test reg" }, | |
3146 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
3147 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
3148 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
21df382b | 3149 | { OPERAND_TYPE_SREG, "SReg" }, |
40fb9820 L |
3150 | { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, |
3151 | { OPERAND_TYPE_REGMMX, "rMMX" }, | |
3152 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 3153 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
43234a1e L |
3154 | { OPERAND_TYPE_REGZMM, "rZMM" }, |
3155 | { OPERAND_TYPE_REGMASK, "Mask reg" }, | |
40fb9820 | 3156 | { OPERAND_TYPE_ESSEG, "es" }, |
252b5132 RH |
3157 | }; |
3158 | ||
3159 | static void | |
40fb9820 | 3160 | pt (i386_operand_type t) |
252b5132 | 3161 | { |
40fb9820 | 3162 | unsigned int j; |
c6fb90c8 | 3163 | i386_operand_type a; |
252b5132 | 3164 | |
40fb9820 | 3165 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
3166 | { |
3167 | a = operand_type_and (t, type_names[j].mask); | |
2c703856 | 3168 | if (operand_type_equal (&a, &type_names[j].mask)) |
c6fb90c8 L |
3169 | fprintf (stdout, "%s, ", type_names[j].name); |
3170 | } | |
252b5132 RH |
3171 | fflush (stdout); |
3172 | } | |
3173 | ||
3174 | #endif /* DEBUG386 */ | |
3175 | \f | |
252b5132 | 3176 | static bfd_reloc_code_real_type |
3956db08 | 3177 | reloc (unsigned int size, |
64e74474 AM |
3178 | int pcrel, |
3179 | int sign, | |
3180 | bfd_reloc_code_real_type other) | |
252b5132 | 3181 | { |
47926f60 | 3182 | if (other != NO_RELOC) |
3956db08 | 3183 | { |
91d6fa6a | 3184 | reloc_howto_type *rel; |
3956db08 JB |
3185 | |
3186 | if (size == 8) | |
3187 | switch (other) | |
3188 | { | |
64e74474 AM |
3189 | case BFD_RELOC_X86_64_GOT32: |
3190 | return BFD_RELOC_X86_64_GOT64; | |
3191 | break; | |
553d1284 L |
3192 | case BFD_RELOC_X86_64_GOTPLT64: |
3193 | return BFD_RELOC_X86_64_GOTPLT64; | |
3194 | break; | |
64e74474 AM |
3195 | case BFD_RELOC_X86_64_PLTOFF64: |
3196 | return BFD_RELOC_X86_64_PLTOFF64; | |
3197 | break; | |
3198 | case BFD_RELOC_X86_64_GOTPC32: | |
3199 | other = BFD_RELOC_X86_64_GOTPC64; | |
3200 | break; | |
3201 | case BFD_RELOC_X86_64_GOTPCREL: | |
3202 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
3203 | break; | |
3204 | case BFD_RELOC_X86_64_TPOFF32: | |
3205 | other = BFD_RELOC_X86_64_TPOFF64; | |
3206 | break; | |
3207 | case BFD_RELOC_X86_64_DTPOFF32: | |
3208 | other = BFD_RELOC_X86_64_DTPOFF64; | |
3209 | break; | |
3210 | default: | |
3211 | break; | |
3956db08 | 3212 | } |
e05278af | 3213 | |
8ce3d284 | 3214 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
3215 | if (other == BFD_RELOC_SIZE32) |
3216 | { | |
3217 | if (size == 8) | |
1ab668bf | 3218 | other = BFD_RELOC_SIZE64; |
8fd4256d | 3219 | if (pcrel) |
1ab668bf AM |
3220 | { |
3221 | as_bad (_("there are no pc-relative size relocations")); | |
3222 | return NO_RELOC; | |
3223 | } | |
8fd4256d | 3224 | } |
8ce3d284 | 3225 | #endif |
8fd4256d | 3226 | |
e05278af | 3227 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 3228 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
3229 | sign = -1; |
3230 | ||
91d6fa6a NC |
3231 | rel = bfd_reloc_type_lookup (stdoutput, other); |
3232 | if (!rel) | |
3956db08 | 3233 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 3234 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 3235 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 3236 | bfd_get_reloc_size (rel), |
3956db08 | 3237 | size); |
91d6fa6a | 3238 | else if (pcrel && !rel->pc_relative) |
3956db08 | 3239 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 3240 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 3241 | && !sign) |
91d6fa6a | 3242 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 3243 | && sign > 0)) |
3956db08 JB |
3244 | as_bad (_("relocated field and relocation type differ in signedness")); |
3245 | else | |
3246 | return other; | |
3247 | return NO_RELOC; | |
3248 | } | |
252b5132 RH |
3249 | |
3250 | if (pcrel) | |
3251 | { | |
3e73aa7c | 3252 | if (!sign) |
3956db08 | 3253 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3254 | switch (size) |
3255 | { | |
3256 | case 1: return BFD_RELOC_8_PCREL; | |
3257 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3258 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3259 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3260 | } |
3956db08 | 3261 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3262 | } |
3263 | else | |
3264 | { | |
3956db08 | 3265 | if (sign > 0) |
e5cb08ac | 3266 | switch (size) |
3e73aa7c JH |
3267 | { |
3268 | case 4: return BFD_RELOC_X86_64_32S; | |
3269 | } | |
3270 | else | |
3271 | switch (size) | |
3272 | { | |
3273 | case 1: return BFD_RELOC_8; | |
3274 | case 2: return BFD_RELOC_16; | |
3275 | case 4: return BFD_RELOC_32; | |
3276 | case 8: return BFD_RELOC_64; | |
3277 | } | |
3956db08 JB |
3278 | as_bad (_("cannot do %s %u byte relocation"), |
3279 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3280 | } |
3281 | ||
0cc9e1d3 | 3282 | return NO_RELOC; |
252b5132 RH |
3283 | } |
3284 | ||
47926f60 KH |
3285 | /* Here we decide which fixups can be adjusted to make them relative to |
3286 | the beginning of the section instead of the symbol. Basically we need | |
3287 | to make sure that the dynamic relocations are done correctly, so in | |
3288 | some cases we force the original symbol to be used. */ | |
3289 | ||
252b5132 | 3290 | int |
e3bb37b5 | 3291 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 3292 | { |
6d249963 | 3293 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 3294 | if (!IS_ELF) |
31312f95 AM |
3295 | return 1; |
3296 | ||
a161fe53 AM |
3297 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3298 | mode. */ | |
3299 | if (use_rela_relocations | |
3300 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3301 | && fixP->fx_pcrel) | |
252b5132 | 3302 | return 0; |
31312f95 | 3303 | |
8d01d9a9 AJ |
3304 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3305 | and changed later by validate_fix. */ | |
3306 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3307 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3308 | return 0; | |
3309 | ||
8fd4256d L |
3310 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3311 | for size relocations. */ | |
3312 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3313 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3314 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 RH |
3315 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 |
3316 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
02a86693 | 3317 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3318 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3319 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3320 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3321 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3322 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3323 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3324 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3325 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3326 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3327 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c JH |
3328 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
3329 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 3330 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3331 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3332 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
bffbf940 JJ |
3333 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3334 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3335 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3336 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
3337 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
3338 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
3339 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3340 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
3341 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
3342 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
3343 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3344 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3345 | return 0; | |
31312f95 | 3346 | #endif |
252b5132 RH |
3347 | return 1; |
3348 | } | |
252b5132 | 3349 | |
b4cac588 | 3350 | static int |
e3bb37b5 | 3351 | intel_float_operand (const char *mnemonic) |
252b5132 | 3352 | { |
9306ca4a JB |
3353 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3354 | operands, hence the code here is free to improperly handle opcodes that | |
3355 | have no operands (for better performance and smaller code). */ | |
3356 | ||
3357 | if (mnemonic[0] != 'f') | |
3358 | return 0; /* non-math */ | |
3359 | ||
3360 | switch (mnemonic[1]) | |
3361 | { | |
3362 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3363 | the fs segment override prefix not currently handled because no | |
3364 | call path can make opcodes without operands get here */ | |
3365 | case 'i': | |
3366 | return 2 /* integer op */; | |
3367 | case 'l': | |
3368 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3369 | return 3; /* fldcw/fldenv */ | |
3370 | break; | |
3371 | case 'n': | |
3372 | if (mnemonic[2] != 'o' /* fnop */) | |
3373 | return 3; /* non-waiting control op */ | |
3374 | break; | |
3375 | case 'r': | |
3376 | if (mnemonic[2] == 's') | |
3377 | return 3; /* frstor/frstpm */ | |
3378 | break; | |
3379 | case 's': | |
3380 | if (mnemonic[2] == 'a') | |
3381 | return 3; /* fsave */ | |
3382 | if (mnemonic[2] == 't') | |
3383 | { | |
3384 | switch (mnemonic[3]) | |
3385 | { | |
3386 | case 'c': /* fstcw */ | |
3387 | case 'd': /* fstdw */ | |
3388 | case 'e': /* fstenv */ | |
3389 | case 's': /* fsts[gw] */ | |
3390 | return 3; | |
3391 | } | |
3392 | } | |
3393 | break; | |
3394 | case 'x': | |
3395 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3396 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3397 | break; | |
3398 | } | |
252b5132 | 3399 | |
9306ca4a | 3400 | return 1; |
252b5132 RH |
3401 | } |
3402 | ||
c0f3af97 L |
3403 | /* Build the VEX prefix. */ |
3404 | ||
3405 | static void | |
d3ce72d0 | 3406 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3407 | { |
3408 | unsigned int register_specifier; | |
3409 | unsigned int implied_prefix; | |
3410 | unsigned int vector_length; | |
03751133 | 3411 | unsigned int w; |
c0f3af97 L |
3412 | |
3413 | /* Check register specifier. */ | |
3414 | if (i.vex.register_specifier) | |
43234a1e L |
3415 | { |
3416 | register_specifier = | |
3417 | ~register_number (i.vex.register_specifier) & 0xf; | |
3418 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3419 | } | |
c0f3af97 L |
3420 | else |
3421 | register_specifier = 0xf; | |
3422 | ||
79f0fa25 L |
3423 | /* Use 2-byte VEX prefix by swapping destination and source operand |
3424 | if there are more than 1 register operand. */ | |
3425 | if (i.reg_operands > 1 | |
3426 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3427 | && i.dir_encoding == dir_encoding_default |
fa99fab2 | 3428 | && i.operands == i.reg_operands |
dbbc8b7e | 3429 | && operand_type_equal (&i.types[0], &i.types[i.operands - 1]) |
7f399153 | 3430 | && i.tm.opcode_modifier.vexopcode == VEX0F |
dbbc8b7e | 3431 | && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d) |
fa99fab2 L |
3432 | && i.rex == REX_B) |
3433 | { | |
3434 | unsigned int xchg = i.operands - 1; | |
3435 | union i386_op temp_op; | |
3436 | i386_operand_type temp_type; | |
3437 | ||
3438 | temp_type = i.types[xchg]; | |
3439 | i.types[xchg] = i.types[0]; | |
3440 | i.types[0] = temp_type; | |
3441 | temp_op = i.op[xchg]; | |
3442 | i.op[xchg] = i.op[0]; | |
3443 | i.op[0] = temp_op; | |
3444 | ||
9c2799c2 | 3445 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3446 | |
3447 | i.rex = REX_R; | |
3448 | xchg = i.rm.regmem; | |
3449 | i.rm.regmem = i.rm.reg; | |
3450 | i.rm.reg = xchg; | |
3451 | ||
dbbc8b7e JB |
3452 | if (i.tm.opcode_modifier.d) |
3453 | i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e | |
3454 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
3455 | else /* Use the next insn. */ | |
3456 | i.tm = t[1]; | |
fa99fab2 L |
3457 | } |
3458 | ||
79dec6b7 JB |
3459 | /* Use 2-byte VEX prefix by swapping commutative source operands if there |
3460 | are no memory operands and at least 3 register ones. */ | |
3461 | if (i.reg_operands >= 3 | |
3462 | && i.vec_encoding != vex_encoding_vex3 | |
3463 | && i.reg_operands == i.operands - i.imm_operands | |
3464 | && i.tm.opcode_modifier.vex | |
3465 | && i.tm.opcode_modifier.commutative | |
3466 | && (i.tm.opcode_modifier.sse2avx || optimize > 1) | |
3467 | && i.rex == REX_B | |
3468 | && i.vex.register_specifier | |
3469 | && !(i.vex.register_specifier->reg_flags & RegRex)) | |
3470 | { | |
3471 | unsigned int xchg = i.operands - i.reg_operands; | |
3472 | union i386_op temp_op; | |
3473 | i386_operand_type temp_type; | |
3474 | ||
3475 | gas_assert (i.tm.opcode_modifier.vexopcode == VEX0F); | |
3476 | gas_assert (!i.tm.opcode_modifier.sae); | |
3477 | gas_assert (operand_type_equal (&i.types[i.operands - 2], | |
3478 | &i.types[i.operands - 3])); | |
3479 | gas_assert (i.rm.mode == 3); | |
3480 | ||
3481 | temp_type = i.types[xchg]; | |
3482 | i.types[xchg] = i.types[xchg + 1]; | |
3483 | i.types[xchg + 1] = temp_type; | |
3484 | temp_op = i.op[xchg]; | |
3485 | i.op[xchg] = i.op[xchg + 1]; | |
3486 | i.op[xchg + 1] = temp_op; | |
3487 | ||
3488 | i.rex = 0; | |
3489 | xchg = i.rm.regmem | 8; | |
3490 | i.rm.regmem = ~register_specifier & 0xf; | |
3491 | gas_assert (!(i.rm.regmem & 8)); | |
3492 | i.vex.register_specifier += xchg - i.rm.regmem; | |
3493 | register_specifier = ~xchg & 0xf; | |
3494 | } | |
3495 | ||
539f890d L |
3496 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3497 | vector_length = avxscalar; | |
10c17abd JB |
3498 | else if (i.tm.opcode_modifier.vex == VEX256) |
3499 | vector_length = 1; | |
539f890d | 3500 | else |
10c17abd | 3501 | { |
56522fc5 | 3502 | unsigned int op; |
10c17abd | 3503 | |
c7213af9 L |
3504 | /* Determine vector length from the last multi-length vector |
3505 | operand. */ | |
10c17abd | 3506 | vector_length = 0; |
56522fc5 | 3507 | for (op = t->operands; op--;) |
10c17abd JB |
3508 | if (t->operand_types[op].bitfield.xmmword |
3509 | && t->operand_types[op].bitfield.ymmword | |
3510 | && i.types[op].bitfield.ymmword) | |
3511 | { | |
3512 | vector_length = 1; | |
3513 | break; | |
3514 | } | |
3515 | } | |
c0f3af97 L |
3516 | |
3517 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3518 | { | |
3519 | case 0: | |
3520 | implied_prefix = 0; | |
3521 | break; | |
3522 | case DATA_PREFIX_OPCODE: | |
3523 | implied_prefix = 1; | |
3524 | break; | |
3525 | case REPE_PREFIX_OPCODE: | |
3526 | implied_prefix = 2; | |
3527 | break; | |
3528 | case REPNE_PREFIX_OPCODE: | |
3529 | implied_prefix = 3; | |
3530 | break; | |
3531 | default: | |
3532 | abort (); | |
3533 | } | |
3534 | ||
03751133 L |
3535 | /* Check the REX.W bit and VEXW. */ |
3536 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3537 | w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3538 | else if (i.tm.opcode_modifier.vexw) | |
3539 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3540 | else | |
931d03b7 | 3541 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0; |
03751133 | 3542 | |
c0f3af97 | 3543 | /* Use 2-byte VEX prefix if possible. */ |
03751133 L |
3544 | if (w == 0 |
3545 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3546 | && i.tm.opcode_modifier.vexopcode == VEX0F |
c0f3af97 L |
3547 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3548 | { | |
3549 | /* 2-byte VEX prefix. */ | |
3550 | unsigned int r; | |
3551 | ||
3552 | i.vex.length = 2; | |
3553 | i.vex.bytes[0] = 0xc5; | |
3554 | ||
3555 | /* Check the REX.R bit. */ | |
3556 | r = (i.rex & REX_R) ? 0 : 1; | |
3557 | i.vex.bytes[1] = (r << 7 | |
3558 | | register_specifier << 3 | |
3559 | | vector_length << 2 | |
3560 | | implied_prefix); | |
3561 | } | |
3562 | else | |
3563 | { | |
3564 | /* 3-byte VEX prefix. */ | |
03751133 | 3565 | unsigned int m; |
c0f3af97 | 3566 | |
f88c9eb0 | 3567 | i.vex.length = 3; |
f88c9eb0 | 3568 | |
7f399153 | 3569 | switch (i.tm.opcode_modifier.vexopcode) |
5dd85c99 | 3570 | { |
7f399153 L |
3571 | case VEX0F: |
3572 | m = 0x1; | |
80de6e00 | 3573 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3574 | break; |
3575 | case VEX0F38: | |
3576 | m = 0x2; | |
80de6e00 | 3577 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3578 | break; |
3579 | case VEX0F3A: | |
3580 | m = 0x3; | |
80de6e00 | 3581 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3582 | break; |
3583 | case XOP08: | |
5dd85c99 SP |
3584 | m = 0x8; |
3585 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3586 | break; |
3587 | case XOP09: | |
f88c9eb0 SP |
3588 | m = 0x9; |
3589 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3590 | break; |
3591 | case XOP0A: | |
f88c9eb0 SP |
3592 | m = 0xa; |
3593 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3594 | break; |
3595 | default: | |
3596 | abort (); | |
f88c9eb0 | 3597 | } |
c0f3af97 | 3598 | |
c0f3af97 L |
3599 | /* The high 3 bits of the second VEX byte are 1's compliment |
3600 | of RXB bits from REX. */ | |
3601 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3602 | ||
c0f3af97 L |
3603 | i.vex.bytes[2] = (w << 7 |
3604 | | register_specifier << 3 | |
3605 | | vector_length << 2 | |
3606 | | implied_prefix); | |
3607 | } | |
3608 | } | |
3609 | ||
e771e7c9 JB |
3610 | static INLINE bfd_boolean |
3611 | is_evex_encoding (const insn_template *t) | |
3612 | { | |
7091c612 | 3613 | return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift |
e771e7c9 | 3614 | || t->opcode_modifier.broadcast || t->opcode_modifier.masking |
a80195f1 | 3615 | || t->opcode_modifier.sae; |
e771e7c9 JB |
3616 | } |
3617 | ||
7a8655d2 JB |
3618 | static INLINE bfd_boolean |
3619 | is_any_vex_encoding (const insn_template *t) | |
3620 | { | |
3621 | return t->opcode_modifier.vex || t->opcode_modifier.vexopcode | |
3622 | || is_evex_encoding (t); | |
3623 | } | |
3624 | ||
43234a1e L |
3625 | /* Build the EVEX prefix. */ |
3626 | ||
3627 | static void | |
3628 | build_evex_prefix (void) | |
3629 | { | |
3630 | unsigned int register_specifier; | |
3631 | unsigned int implied_prefix; | |
3632 | unsigned int m, w; | |
3633 | rex_byte vrex_used = 0; | |
3634 | ||
3635 | /* Check register specifier. */ | |
3636 | if (i.vex.register_specifier) | |
3637 | { | |
3638 | gas_assert ((i.vrex & REX_X) == 0); | |
3639 | ||
3640 | register_specifier = i.vex.register_specifier->reg_num; | |
3641 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
3642 | register_specifier += 8; | |
3643 | /* The upper 16 registers are encoded in the fourth byte of the | |
3644 | EVEX prefix. */ | |
3645 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
3646 | i.vex.bytes[3] = 0x8; | |
3647 | register_specifier = ~register_specifier & 0xf; | |
3648 | } | |
3649 | else | |
3650 | { | |
3651 | register_specifier = 0xf; | |
3652 | ||
3653 | /* Encode upper 16 vector index register in the fourth byte of | |
3654 | the EVEX prefix. */ | |
3655 | if (!(i.vrex & REX_X)) | |
3656 | i.vex.bytes[3] = 0x8; | |
3657 | else | |
3658 | vrex_used |= REX_X; | |
3659 | } | |
3660 | ||
3661 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3662 | { | |
3663 | case 0: | |
3664 | implied_prefix = 0; | |
3665 | break; | |
3666 | case DATA_PREFIX_OPCODE: | |
3667 | implied_prefix = 1; | |
3668 | break; | |
3669 | case REPE_PREFIX_OPCODE: | |
3670 | implied_prefix = 2; | |
3671 | break; | |
3672 | case REPNE_PREFIX_OPCODE: | |
3673 | implied_prefix = 3; | |
3674 | break; | |
3675 | default: | |
3676 | abort (); | |
3677 | } | |
3678 | ||
3679 | /* 4 byte EVEX prefix. */ | |
3680 | i.vex.length = 4; | |
3681 | i.vex.bytes[0] = 0x62; | |
3682 | ||
3683 | /* mmmm bits. */ | |
3684 | switch (i.tm.opcode_modifier.vexopcode) | |
3685 | { | |
3686 | case VEX0F: | |
3687 | m = 1; | |
3688 | break; | |
3689 | case VEX0F38: | |
3690 | m = 2; | |
3691 | break; | |
3692 | case VEX0F3A: | |
3693 | m = 3; | |
3694 | break; | |
3695 | default: | |
3696 | abort (); | |
3697 | break; | |
3698 | } | |
3699 | ||
3700 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB | |
3701 | bits from REX. */ | |
3702 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3703 | ||
3704 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
3705 | REX_R bit in VREX. */ | |
3706 | if (!(i.vrex & REX_R)) | |
3707 | i.vex.bytes[1] |= 0x10; | |
3708 | else | |
3709 | vrex_used |= REX_R; | |
3710 | ||
3711 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
3712 | { | |
3713 | /* When all operands are registers, the REX_X bit in REX is not | |
3714 | used. We reuse it to encode the upper 16 registers, which is | |
3715 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
3716 | as 1's compliment. */ | |
3717 | if ((i.vrex & REX_B)) | |
3718 | { | |
3719 | vrex_used |= REX_B; | |
3720 | i.vex.bytes[1] &= ~0x40; | |
3721 | } | |
3722 | } | |
3723 | ||
3724 | /* EVEX instructions shouldn't need the REX prefix. */ | |
3725 | i.vrex &= ~vrex_used; | |
3726 | gas_assert (i.vrex == 0); | |
3727 | ||
6865c043 L |
3728 | /* Check the REX.W bit and VEXW. */ |
3729 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3730 | w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3731 | else if (i.tm.opcode_modifier.vexw) | |
3732 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3733 | else | |
931d03b7 | 3734 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0; |
43234a1e L |
3735 | |
3736 | /* Encode the U bit. */ | |
3737 | implied_prefix |= 0x4; | |
3738 | ||
3739 | /* The third byte of the EVEX prefix. */ | |
3740 | i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix); | |
3741 | ||
3742 | /* The fourth byte of the EVEX prefix. */ | |
3743 | /* The zeroing-masking bit. */ | |
3744 | if (i.mask && i.mask->zeroing) | |
3745 | i.vex.bytes[3] |= 0x80; | |
3746 | ||
3747 | /* Don't always set the broadcast bit if there is no RC. */ | |
3748 | if (!i.rounding) | |
3749 | { | |
3750 | /* Encode the vector length. */ | |
3751 | unsigned int vec_length; | |
3752 | ||
e771e7c9 JB |
3753 | if (!i.tm.opcode_modifier.evex |
3754 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
3755 | { | |
56522fc5 | 3756 | unsigned int op; |
e771e7c9 | 3757 | |
c7213af9 L |
3758 | /* Determine vector length from the last multi-length vector |
3759 | operand. */ | |
e771e7c9 | 3760 | vec_length = 0; |
56522fc5 | 3761 | for (op = i.operands; op--;) |
e771e7c9 JB |
3762 | if (i.tm.operand_types[op].bitfield.xmmword |
3763 | + i.tm.operand_types[op].bitfield.ymmword | |
3764 | + i.tm.operand_types[op].bitfield.zmmword > 1) | |
3765 | { | |
3766 | if (i.types[op].bitfield.zmmword) | |
c7213af9 L |
3767 | { |
3768 | i.tm.opcode_modifier.evex = EVEX512; | |
3769 | break; | |
3770 | } | |
e771e7c9 | 3771 | else if (i.types[op].bitfield.ymmword) |
c7213af9 L |
3772 | { |
3773 | i.tm.opcode_modifier.evex = EVEX256; | |
3774 | break; | |
3775 | } | |
e771e7c9 | 3776 | else if (i.types[op].bitfield.xmmword) |
c7213af9 L |
3777 | { |
3778 | i.tm.opcode_modifier.evex = EVEX128; | |
3779 | break; | |
3780 | } | |
625cbd7a JB |
3781 | else if (i.broadcast && (int) op == i.broadcast->operand) |
3782 | { | |
4a1b91ea | 3783 | switch (i.broadcast->bytes) |
625cbd7a JB |
3784 | { |
3785 | case 64: | |
3786 | i.tm.opcode_modifier.evex = EVEX512; | |
3787 | break; | |
3788 | case 32: | |
3789 | i.tm.opcode_modifier.evex = EVEX256; | |
3790 | break; | |
3791 | case 16: | |
3792 | i.tm.opcode_modifier.evex = EVEX128; | |
3793 | break; | |
3794 | default: | |
c7213af9 | 3795 | abort (); |
625cbd7a | 3796 | } |
c7213af9 | 3797 | break; |
625cbd7a | 3798 | } |
e771e7c9 | 3799 | } |
c7213af9 | 3800 | |
56522fc5 | 3801 | if (op >= MAX_OPERANDS) |
c7213af9 | 3802 | abort (); |
e771e7c9 JB |
3803 | } |
3804 | ||
43234a1e L |
3805 | switch (i.tm.opcode_modifier.evex) |
3806 | { | |
3807 | case EVEXLIG: /* LL' is ignored */ | |
3808 | vec_length = evexlig << 5; | |
3809 | break; | |
3810 | case EVEX128: | |
3811 | vec_length = 0 << 5; | |
3812 | break; | |
3813 | case EVEX256: | |
3814 | vec_length = 1 << 5; | |
3815 | break; | |
3816 | case EVEX512: | |
3817 | vec_length = 2 << 5; | |
3818 | break; | |
3819 | default: | |
3820 | abort (); | |
3821 | break; | |
3822 | } | |
3823 | i.vex.bytes[3] |= vec_length; | |
3824 | /* Encode the broadcast bit. */ | |
3825 | if (i.broadcast) | |
3826 | i.vex.bytes[3] |= 0x10; | |
3827 | } | |
3828 | else | |
3829 | { | |
3830 | if (i.rounding->type != saeonly) | |
3831 | i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5); | |
3832 | else | |
d3d3c6db | 3833 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e L |
3834 | } |
3835 | ||
3836 | if (i.mask && i.mask->mask) | |
3837 | i.vex.bytes[3] |= i.mask->mask->reg_num; | |
3838 | } | |
3839 | ||
65da13b5 L |
3840 | static void |
3841 | process_immext (void) | |
3842 | { | |
3843 | expressionS *exp; | |
3844 | ||
4c692bc7 JB |
3845 | if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme) |
3846 | && i.operands > 0) | |
65da13b5 | 3847 | { |
4c692bc7 JB |
3848 | /* MONITOR/MWAIT as well as SVME instructions have fixed operands |
3849 | with an opcode suffix which is coded in the same place as an | |
3850 | 8-bit immediate field would be. | |
3851 | Here we check those operands and remove them afterwards. */ | |
65da13b5 L |
3852 | unsigned int x; |
3853 | ||
3854 | for (x = 0; x < i.operands; x++) | |
4c692bc7 | 3855 | if (register_number (i.op[x].regs) != x) |
65da13b5 | 3856 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), |
1fed0ba1 L |
3857 | register_prefix, i.op[x].regs->reg_name, x + 1, |
3858 | i.tm.name); | |
3859 | ||
3860 | i.operands = 0; | |
65da13b5 L |
3861 | } |
3862 | ||
9916071f AP |
3863 | if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0) |
3864 | { | |
3865 | /* MONITORX/MWAITX instructions have fixed operands with an opcode | |
3866 | suffix which is coded in the same place as an 8-bit immediate | |
3867 | field would be. | |
3868 | Here we check those operands and remove them afterwards. */ | |
3869 | unsigned int x; | |
3870 | ||
3871 | if (i.operands != 3) | |
3872 | abort(); | |
3873 | ||
3874 | for (x = 0; x < 2; x++) | |
3875 | if (register_number (i.op[x].regs) != x) | |
3876 | goto bad_register_operand; | |
3877 | ||
3878 | /* Check for third operand for mwaitx/monitorx insn. */ | |
3879 | if (register_number (i.op[x].regs) | |
3880 | != (x + (i.tm.extension_opcode == 0xfb))) | |
3881 | { | |
3882 | bad_register_operand: | |
3883 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), | |
3884 | register_prefix, i.op[x].regs->reg_name, x+1, | |
3885 | i.tm.name); | |
3886 | } | |
3887 | ||
3888 | i.operands = 0; | |
3889 | } | |
3890 | ||
c0f3af97 | 3891 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
3892 | which is coded in the same place as an 8-bit immediate field |
3893 | would be. Here we fake an 8-bit immediate operand from the | |
3894 | opcode suffix stored in tm.extension_opcode. | |
3895 | ||
c1e679ec | 3896 | AVX instructions also use this encoding, for some of |
c0f3af97 | 3897 | 3 argument instructions. */ |
65da13b5 | 3898 | |
43234a1e | 3899 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 3900 | && (i.operands <= 2 |
7a8655d2 | 3901 | || (is_any_vex_encoding (&i.tm) |
7ab9ffdd | 3902 | && i.operands <= 4))); |
65da13b5 L |
3903 | |
3904 | exp = &im_expressions[i.imm_operands++]; | |
3905 | i.op[i.operands].imms = exp; | |
3906 | i.types[i.operands] = imm8; | |
3907 | i.operands++; | |
3908 | exp->X_op = O_constant; | |
3909 | exp->X_add_number = i.tm.extension_opcode; | |
3910 | i.tm.extension_opcode = None; | |
3911 | } | |
3912 | ||
42164a71 L |
3913 | |
3914 | static int | |
3915 | check_hle (void) | |
3916 | { | |
3917 | switch (i.tm.opcode_modifier.hleprefixok) | |
3918 | { | |
3919 | default: | |
3920 | abort (); | |
82c2def5 | 3921 | case HLEPrefixNone: |
165de32a L |
3922 | as_bad (_("invalid instruction `%s' after `%s'"), |
3923 | i.tm.name, i.hle_prefix); | |
42164a71 | 3924 | return 0; |
82c2def5 | 3925 | case HLEPrefixLock: |
42164a71 L |
3926 | if (i.prefix[LOCK_PREFIX]) |
3927 | return 1; | |
165de32a | 3928 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 3929 | return 0; |
82c2def5 | 3930 | case HLEPrefixAny: |
42164a71 | 3931 | return 1; |
82c2def5 | 3932 | case HLEPrefixRelease: |
42164a71 L |
3933 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
3934 | { | |
3935 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
3936 | i.tm.name); | |
3937 | return 0; | |
3938 | } | |
8dc0818e | 3939 | if (i.mem_operands == 0 || !(i.flags[i.operands - 1] & Operand_Mem)) |
42164a71 L |
3940 | { |
3941 | as_bad (_("memory destination needed for instruction `%s'" | |
3942 | " after `xrelease'"), i.tm.name); | |
3943 | return 0; | |
3944 | } | |
3945 | return 1; | |
3946 | } | |
3947 | } | |
3948 | ||
b6f8c7c4 L |
3949 | /* Try the shortest encoding by shortening operand size. */ |
3950 | ||
3951 | static void | |
3952 | optimize_encoding (void) | |
3953 | { | |
a0a1771e | 3954 | unsigned int j; |
b6f8c7c4 L |
3955 | |
3956 | if (optimize_for_space | |
3957 | && i.reg_operands == 1 | |
3958 | && i.imm_operands == 1 | |
3959 | && !i.types[1].bitfield.byte | |
3960 | && i.op[0].imms->X_op == O_constant | |
3961 | && fits_in_imm7 (i.op[0].imms->X_add_number) | |
3962 | && ((i.tm.base_opcode == 0xa8 | |
3963 | && i.tm.extension_opcode == None) | |
3964 | || (i.tm.base_opcode == 0xf6 | |
3965 | && i.tm.extension_opcode == 0x0))) | |
3966 | { | |
3967 | /* Optimize: -Os: | |
3968 | test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 | |
3969 | */ | |
3970 | unsigned int base_regnum = i.op[1].regs->reg_num; | |
3971 | if (flag_code == CODE_64BIT || base_regnum < 4) | |
3972 | { | |
3973 | i.types[1].bitfield.byte = 1; | |
3974 | /* Ignore the suffix. */ | |
3975 | i.suffix = 0; | |
3976 | if (base_regnum >= 4 | |
3977 | && !(i.op[1].regs->reg_flags & RegRex)) | |
3978 | { | |
3979 | /* Handle SP, BP, SI and DI registers. */ | |
3980 | if (i.types[1].bitfield.word) | |
3981 | j = 16; | |
3982 | else if (i.types[1].bitfield.dword) | |
3983 | j = 32; | |
3984 | else | |
3985 | j = 48; | |
3986 | i.op[1].regs -= j; | |
3987 | } | |
3988 | } | |
3989 | } | |
3990 | else if (flag_code == CODE_64BIT | |
d3d50934 L |
3991 | && ((i.types[1].bitfield.qword |
3992 | && i.reg_operands == 1 | |
b6f8c7c4 L |
3993 | && i.imm_operands == 1 |
3994 | && i.op[0].imms->X_op == O_constant | |
507916b8 | 3995 | && ((i.tm.base_opcode == 0xb8 |
b6f8c7c4 L |
3996 | && i.tm.extension_opcode == None |
3997 | && fits_in_unsigned_long (i.op[0].imms->X_add_number)) | |
3998 | || (fits_in_imm31 (i.op[0].imms->X_add_number) | |
3999 | && (((i.tm.base_opcode == 0x24 | |
4000 | || i.tm.base_opcode == 0xa8) | |
4001 | && i.tm.extension_opcode == None) | |
4002 | || (i.tm.base_opcode == 0x80 | |
4003 | && i.tm.extension_opcode == 0x4) | |
4004 | || ((i.tm.base_opcode == 0xf6 | |
507916b8 | 4005 | || (i.tm.base_opcode | 1) == 0xc7) |
b8364fa7 JB |
4006 | && i.tm.extension_opcode == 0x0))) |
4007 | || (fits_in_imm7 (i.op[0].imms->X_add_number) | |
4008 | && i.tm.base_opcode == 0x83 | |
4009 | && i.tm.extension_opcode == 0x4))) | |
d3d50934 L |
4010 | || (i.types[0].bitfield.qword |
4011 | && ((i.reg_operands == 2 | |
4012 | && i.op[0].regs == i.op[1].regs | |
4013 | && ((i.tm.base_opcode == 0x30 | |
4014 | || i.tm.base_opcode == 0x28) | |
4015 | && i.tm.extension_opcode == None)) | |
4016 | || (i.reg_operands == 1 | |
4017 | && i.operands == 1 | |
4018 | && i.tm.base_opcode == 0x30 | |
4019 | && i.tm.extension_opcode == None))))) | |
b6f8c7c4 L |
4020 | { |
4021 | /* Optimize: -O: | |
4022 | andq $imm31, %r64 -> andl $imm31, %r32 | |
b8364fa7 | 4023 | andq $imm7, %r64 -> andl $imm7, %r32 |
b6f8c7c4 L |
4024 | testq $imm31, %r64 -> testl $imm31, %r32 |
4025 | xorq %r64, %r64 -> xorl %r32, %r32 | |
4026 | subq %r64, %r64 -> subl %r32, %r32 | |
4027 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4028 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4029 | */ | |
4030 | i.tm.opcode_modifier.norex64 = 1; | |
507916b8 | 4031 | if (i.tm.base_opcode == 0xb8 || (i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4032 | { |
4033 | /* Handle | |
4034 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4035 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4036 | */ | |
4037 | i.tm.operand_types[0].bitfield.imm32 = 1; | |
4038 | i.tm.operand_types[0].bitfield.imm32s = 0; | |
4039 | i.tm.operand_types[0].bitfield.imm64 = 0; | |
4040 | i.types[0].bitfield.imm32 = 1; | |
4041 | i.types[0].bitfield.imm32s = 0; | |
4042 | i.types[0].bitfield.imm64 = 0; | |
4043 | i.types[1].bitfield.dword = 1; | |
4044 | i.types[1].bitfield.qword = 0; | |
507916b8 | 4045 | if ((i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4046 | { |
4047 | /* Handle | |
4048 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4049 | */ | |
507916b8 | 4050 | i.tm.base_opcode = 0xb8; |
b6f8c7c4 | 4051 | i.tm.extension_opcode = None; |
507916b8 | 4052 | i.tm.opcode_modifier.w = 0; |
b6f8c7c4 L |
4053 | i.tm.opcode_modifier.shortform = 1; |
4054 | i.tm.opcode_modifier.modrm = 0; | |
4055 | } | |
4056 | } | |
4057 | } | |
5641ec01 JB |
4058 | else if (optimize > 1 |
4059 | && !optimize_for_space | |
4060 | && i.reg_operands == 2 | |
4061 | && i.op[0].regs == i.op[1].regs | |
4062 | && ((i.tm.base_opcode & ~(Opcode_D | 1)) == 0x8 | |
4063 | || (i.tm.base_opcode & ~(Opcode_D | 1)) == 0x20) | |
4064 | && (flag_code != CODE_64BIT || !i.types[0].bitfield.dword)) | |
4065 | { | |
4066 | /* Optimize: -O2: | |
4067 | andb %rN, %rN -> testb %rN, %rN | |
4068 | andw %rN, %rN -> testw %rN, %rN | |
4069 | andq %rN, %rN -> testq %rN, %rN | |
4070 | orb %rN, %rN -> testb %rN, %rN | |
4071 | orw %rN, %rN -> testw %rN, %rN | |
4072 | orq %rN, %rN -> testq %rN, %rN | |
4073 | ||
4074 | and outside of 64-bit mode | |
4075 | ||
4076 | andl %rN, %rN -> testl %rN, %rN | |
4077 | orl %rN, %rN -> testl %rN, %rN | |
4078 | */ | |
4079 | i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1); | |
4080 | } | |
99112332 | 4081 | else if (i.reg_operands == 3 |
b6f8c7c4 L |
4082 | && i.op[0].regs == i.op[1].regs |
4083 | && !i.types[2].bitfield.xmmword | |
4084 | && (i.tm.opcode_modifier.vex | |
7a69eac3 | 4085 | || ((!i.mask || i.mask->zeroing) |
b6f8c7c4 | 4086 | && !i.rounding |
e771e7c9 | 4087 | && is_evex_encoding (&i.tm) |
80c34c38 | 4088 | && (i.vec_encoding != vex_encoding_evex |
dd22218c | 4089 | || cpu_arch_isa_flags.bitfield.cpuavx512vl |
80c34c38 | 4090 | || i.tm.cpu_flags.bitfield.cpuavx512vl |
7091c612 | 4091 | || (i.tm.operand_types[2].bitfield.zmmword |
dd22218c | 4092 | && i.types[2].bitfield.ymmword)))) |
b6f8c7c4 L |
4093 | && ((i.tm.base_opcode == 0x55 |
4094 | || i.tm.base_opcode == 0x6655 | |
4095 | || i.tm.base_opcode == 0x66df | |
4096 | || i.tm.base_opcode == 0x57 | |
4097 | || i.tm.base_opcode == 0x6657 | |
8305403a L |
4098 | || i.tm.base_opcode == 0x66ef |
4099 | || i.tm.base_opcode == 0x66f8 | |
4100 | || i.tm.base_opcode == 0x66f9 | |
4101 | || i.tm.base_opcode == 0x66fa | |
1424ad86 JB |
4102 | || i.tm.base_opcode == 0x66fb |
4103 | || i.tm.base_opcode == 0x42 | |
4104 | || i.tm.base_opcode == 0x6642 | |
4105 | || i.tm.base_opcode == 0x47 | |
4106 | || i.tm.base_opcode == 0x6647) | |
b6f8c7c4 L |
4107 | && i.tm.extension_opcode == None)) |
4108 | { | |
99112332 | 4109 | /* Optimize: -O1: |
8305403a L |
4110 | VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, |
4111 | vpsubq and vpsubw: | |
b6f8c7c4 L |
4112 | EVEX VOP %zmmM, %zmmM, %zmmN |
4113 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4114 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4115 | EVEX VOP %ymmM, %ymmM, %ymmN |
4116 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4117 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4118 | VEX VOP %ymmM, %ymmM, %ymmN |
4119 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4120 | VOP, one of vpandn and vpxor: | |
4121 | VEX VOP %ymmM, %ymmM, %ymmN | |
4122 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4123 | VOP, one of vpandnd and vpandnq: | |
4124 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4125 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4126 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4127 | EVEX VOP %ymmM, %ymmM, %ymmN |
4128 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4129 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4130 | VOP, one of vpxord and vpxorq: |
4131 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4132 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4133 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4134 | EVEX VOP %ymmM, %ymmM, %ymmN |
4135 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4136 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
1424ad86 JB |
4137 | VOP, one of kxord and kxorq: |
4138 | VEX VOP %kM, %kM, %kN | |
4139 | -> VEX kxorw %kM, %kM, %kN | |
4140 | VOP, one of kandnd and kandnq: | |
4141 | VEX VOP %kM, %kM, %kN | |
4142 | -> VEX kandnw %kM, %kM, %kN | |
b6f8c7c4 | 4143 | */ |
e771e7c9 | 4144 | if (is_evex_encoding (&i.tm)) |
b6f8c7c4 | 4145 | { |
7b1d7ca1 | 4146 | if (i.vec_encoding != vex_encoding_evex) |
b6f8c7c4 L |
4147 | { |
4148 | i.tm.opcode_modifier.vex = VEX128; | |
4149 | i.tm.opcode_modifier.vexw = VEXW0; | |
4150 | i.tm.opcode_modifier.evex = 0; | |
4151 | } | |
7b1d7ca1 | 4152 | else if (optimize > 1) |
dd22218c L |
4153 | i.tm.opcode_modifier.evex = EVEX128; |
4154 | else | |
4155 | return; | |
b6f8c7c4 | 4156 | } |
1424ad86 JB |
4157 | else if (i.tm.operand_types[0].bitfield.regmask) |
4158 | { | |
4159 | i.tm.base_opcode &= 0xff; | |
4160 | i.tm.opcode_modifier.vexw = VEXW0; | |
4161 | } | |
b6f8c7c4 L |
4162 | else |
4163 | i.tm.opcode_modifier.vex = VEX128; | |
4164 | ||
4165 | if (i.tm.opcode_modifier.vex) | |
4166 | for (j = 0; j < 3; j++) | |
4167 | { | |
4168 | i.types[j].bitfield.xmmword = 1; | |
4169 | i.types[j].bitfield.ymmword = 0; | |
4170 | } | |
4171 | } | |
392a5972 | 4172 | else if (i.vec_encoding != vex_encoding_evex |
97ed31ae | 4173 | && !i.types[0].bitfield.zmmword |
392a5972 | 4174 | && !i.types[1].bitfield.zmmword |
97ed31ae | 4175 | && !i.mask |
a0a1771e | 4176 | && !i.broadcast |
97ed31ae | 4177 | && is_evex_encoding (&i.tm) |
392a5972 L |
4178 | && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x666f |
4179 | || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf36f | |
a0a1771e JB |
4180 | || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f |
4181 | || (i.tm.base_opcode & ~4) == 0x66db | |
4182 | || (i.tm.base_opcode & ~4) == 0x66eb) | |
97ed31ae L |
4183 | && i.tm.extension_opcode == None) |
4184 | { | |
4185 | /* Optimize: -O1: | |
4186 | VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, | |
4187 | vmovdqu32 and vmovdqu64: | |
4188 | EVEX VOP %xmmM, %xmmN | |
4189 | -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16) | |
4190 | EVEX VOP %ymmM, %ymmN | |
4191 | -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16) | |
4192 | EVEX VOP %xmmM, mem | |
4193 | -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16) | |
4194 | EVEX VOP %ymmM, mem | |
4195 | -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16) | |
4196 | EVEX VOP mem, %xmmN | |
4197 | -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16) | |
4198 | EVEX VOP mem, %ymmN | |
4199 | -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16) | |
a0a1771e JB |
4200 | VOP, one of vpand, vpandn, vpor, vpxor: |
4201 | EVEX VOP{d,q} %xmmL, %xmmM, %xmmN | |
4202 | -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16) | |
4203 | EVEX VOP{d,q} %ymmL, %ymmM, %ymmN | |
4204 | -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16) | |
4205 | EVEX VOP{d,q} mem, %xmmM, %xmmN | |
4206 | -> VEX VOP mem, %xmmM, %xmmN (M and N < 16) | |
4207 | EVEX VOP{d,q} mem, %ymmM, %ymmN | |
4208 | -> VEX VOP mem, %ymmM, %ymmN (M and N < 16) | |
97ed31ae | 4209 | */ |
a0a1771e | 4210 | for (j = 0; j < i.operands; j++) |
392a5972 L |
4211 | if (operand_type_check (i.types[j], disp) |
4212 | && i.op[j].disps->X_op == O_constant) | |
4213 | { | |
4214 | /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix | |
4215 | has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4 | |
4216 | bytes, we choose EVEX Disp8 over VEX Disp32. */ | |
4217 | int evex_disp8, vex_disp8; | |
4218 | unsigned int memshift = i.memshift; | |
4219 | offsetT n = i.op[j].disps->X_add_number; | |
4220 | ||
4221 | evex_disp8 = fits_in_disp8 (n); | |
4222 | i.memshift = 0; | |
4223 | vex_disp8 = fits_in_disp8 (n); | |
4224 | if (evex_disp8 != vex_disp8) | |
4225 | { | |
4226 | i.memshift = memshift; | |
4227 | return; | |
4228 | } | |
4229 | ||
4230 | i.types[j].bitfield.disp8 = vex_disp8; | |
4231 | break; | |
4232 | } | |
4233 | if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f) | |
4234 | i.tm.base_opcode ^= 0xf36f ^ 0xf26f; | |
97ed31ae L |
4235 | i.tm.opcode_modifier.vex |
4236 | = i.types[0].bitfield.ymmword ? VEX256 : VEX128; | |
4237 | i.tm.opcode_modifier.vexw = VEXW0; | |
79dec6b7 JB |
4238 | /* VPAND, VPOR, and VPXOR are commutative. */ |
4239 | if (i.reg_operands == 3 && i.tm.base_opcode != 0x66df) | |
4240 | i.tm.opcode_modifier.commutative = 1; | |
97ed31ae L |
4241 | i.tm.opcode_modifier.evex = 0; |
4242 | i.tm.opcode_modifier.masking = 0; | |
a0a1771e | 4243 | i.tm.opcode_modifier.broadcast = 0; |
97ed31ae L |
4244 | i.tm.opcode_modifier.disp8memshift = 0; |
4245 | i.memshift = 0; | |
a0a1771e JB |
4246 | if (j < i.operands) |
4247 | i.types[j].bitfield.disp8 | |
4248 | = fits_in_disp8 (i.op[j].disps->X_add_number); | |
97ed31ae | 4249 | } |
b6f8c7c4 L |
4250 | } |
4251 | ||
252b5132 RH |
4252 | /* This is the guts of the machine-dependent assembler. LINE points to a |
4253 | machine dependent instruction. This function is supposed to emit | |
4254 | the frags/bytes it assembles to. */ | |
4255 | ||
4256 | void | |
65da13b5 | 4257 | md_assemble (char *line) |
252b5132 | 4258 | { |
40fb9820 | 4259 | unsigned int j; |
83b16ac6 | 4260 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix; |
d3ce72d0 | 4261 | const insn_template *t; |
252b5132 | 4262 | |
47926f60 | 4263 | /* Initialize globals. */ |
252b5132 RH |
4264 | memset (&i, '\0', sizeof (i)); |
4265 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 4266 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
4267 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
4268 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 4269 | save_stack_p = save_stack; |
252b5132 RH |
4270 | |
4271 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
4272 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 4273 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 4274 | |
29b0f896 AM |
4275 | line = parse_insn (line, mnemonic); |
4276 | if (line == NULL) | |
4277 | return; | |
83b16ac6 | 4278 | mnem_suffix = i.suffix; |
252b5132 | 4279 | |
29b0f896 | 4280 | line = parse_operands (line, mnemonic); |
ee86248c | 4281 | this_operand = -1; |
8325cc63 JB |
4282 | xfree (i.memop1_string); |
4283 | i.memop1_string = NULL; | |
29b0f896 AM |
4284 | if (line == NULL) |
4285 | return; | |
252b5132 | 4286 | |
29b0f896 AM |
4287 | /* Now we've parsed the mnemonic into a set of templates, and have the |
4288 | operands at hand. */ | |
4289 | ||
4290 | /* All intel opcodes have reversed operands except for "bound" and | |
4291 | "enter". We also don't reverse intersegment "jmp" and "call" | |
4292 | instructions with 2 immediate operands so that the immediate segment | |
050dfa73 | 4293 | precedes the offset, as it does when in AT&T mode. */ |
4d456e3d L |
4294 | if (intel_syntax |
4295 | && i.operands > 1 | |
29b0f896 | 4296 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 4297 | && (strcmp (mnemonic, "invlpga") != 0) |
40fb9820 L |
4298 | && !(operand_type_check (i.types[0], imm) |
4299 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
4300 | swap_operands (); |
4301 | ||
ec56d5c0 JB |
4302 | /* The order of the immediates should be reversed |
4303 | for 2 immediates extrq and insertq instructions */ | |
4304 | if (i.imm_operands == 2 | |
4305 | && (strcmp (mnemonic, "extrq") == 0 | |
4306 | || strcmp (mnemonic, "insertq") == 0)) | |
4307 | swap_2_operands (0, 1); | |
4308 | ||
29b0f896 AM |
4309 | if (i.imm_operands) |
4310 | optimize_imm (); | |
4311 | ||
b300c311 L |
4312 | /* Don't optimize displacement for movabs since it only takes 64bit |
4313 | displacement. */ | |
4314 | if (i.disp_operands | |
a501d77e | 4315 | && i.disp_encoding != disp_encoding_32bit |
862be3fb L |
4316 | && (flag_code != CODE_64BIT |
4317 | || strcmp (mnemonic, "movabs") != 0)) | |
4318 | optimize_disp (); | |
29b0f896 AM |
4319 | |
4320 | /* Next, we find a template that matches the given insn, | |
4321 | making sure the overlap of the given operands types is consistent | |
4322 | with the template operand types. */ | |
252b5132 | 4323 | |
83b16ac6 | 4324 | if (!(t = match_template (mnem_suffix))) |
29b0f896 | 4325 | return; |
252b5132 | 4326 | |
7bab8ab5 | 4327 | if (sse_check != check_none |
81f8a913 | 4328 | && !i.tm.opcode_modifier.noavx |
6e3e5c9e | 4329 | && !i.tm.cpu_flags.bitfield.cpuavx |
daf50ae7 L |
4330 | && (i.tm.cpu_flags.bitfield.cpusse |
4331 | || i.tm.cpu_flags.bitfield.cpusse2 | |
4332 | || i.tm.cpu_flags.bitfield.cpusse3 | |
4333 | || i.tm.cpu_flags.bitfield.cpussse3 | |
4334 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
6e3e5c9e JB |
4335 | || i.tm.cpu_flags.bitfield.cpusse4_2 |
4336 | || i.tm.cpu_flags.bitfield.cpupclmul | |
4337 | || i.tm.cpu_flags.bitfield.cpuaes | |
4338 | || i.tm.cpu_flags.bitfield.cpugfni)) | |
daf50ae7 | 4339 | { |
7bab8ab5 | 4340 | (sse_check == check_warning |
daf50ae7 L |
4341 | ? as_warn |
4342 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
4343 | } | |
4344 | ||
321fd21e L |
4345 | /* Zap movzx and movsx suffix. The suffix has been set from |
4346 | "word ptr" or "byte ptr" on the source operand in Intel syntax | |
4347 | or extracted from mnemonic in AT&T syntax. But we'll use | |
4348 | the destination register to choose the suffix for encoding. */ | |
4349 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
cd61ebfe | 4350 | { |
321fd21e L |
4351 | /* In Intel syntax, there must be a suffix. In AT&T syntax, if |
4352 | there is no suffix, the default will be byte extension. */ | |
4353 | if (i.reg_operands != 2 | |
4354 | && !i.suffix | |
7ab9ffdd | 4355 | && intel_syntax) |
321fd21e L |
4356 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
4357 | ||
4358 | i.suffix = 0; | |
cd61ebfe | 4359 | } |
24eab124 | 4360 | |
40fb9820 | 4361 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
4362 | if (!add_prefix (FWAIT_OPCODE)) |
4363 | return; | |
252b5132 | 4364 | |
d5de92cf L |
4365 | /* Check if REP prefix is OK. */ |
4366 | if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok) | |
4367 | { | |
4368 | as_bad (_("invalid instruction `%s' after `%s'"), | |
4369 | i.tm.name, i.rep_prefix); | |
4370 | return; | |
4371 | } | |
4372 | ||
c1ba0266 L |
4373 | /* Check for lock without a lockable instruction. Destination operand |
4374 | must be memory unless it is xchg (0x86). */ | |
c32fa91d L |
4375 | if (i.prefix[LOCK_PREFIX] |
4376 | && (!i.tm.opcode_modifier.islockable | |
c1ba0266 L |
4377 | || i.mem_operands == 0 |
4378 | || (i.tm.base_opcode != 0x86 | |
8dc0818e | 4379 | && !(i.flags[i.operands - 1] & Operand_Mem)))) |
c32fa91d L |
4380 | { |
4381 | as_bad (_("expecting lockable instruction after `lock'")); | |
4382 | return; | |
4383 | } | |
4384 | ||
7a8655d2 JB |
4385 | /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */ |
4386 | if (i.prefix[DATA_PREFIX] && is_any_vex_encoding (&i.tm)) | |
4387 | { | |
4388 | as_bad (_("data size prefix invalid with `%s'"), i.tm.name); | |
4389 | return; | |
4390 | } | |
4391 | ||
42164a71 | 4392 | /* Check if HLE prefix is OK. */ |
165de32a | 4393 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
4394 | return; |
4395 | ||
7e8b059b L |
4396 | /* Check BND prefix. */ |
4397 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
4398 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
4399 | ||
04ef582a | 4400 | /* Check NOTRACK prefix. */ |
9fef80d6 L |
4401 | if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok) |
4402 | as_bad (_("expecting indirect branch instruction after `notrack'")); | |
04ef582a | 4403 | |
327e8c42 JB |
4404 | if (i.tm.cpu_flags.bitfield.cpumpx) |
4405 | { | |
4406 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
4407 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
4408 | else if (flag_code != CODE_16BIT | |
4409 | ? i.prefix[ADDR_PREFIX] | |
4410 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
4411 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
4412 | } | |
7e8b059b L |
4413 | |
4414 | /* Insert BND prefix. */ | |
76d3a78a JB |
4415 | if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok) |
4416 | { | |
4417 | if (!i.prefix[BND_PREFIX]) | |
4418 | add_prefix (BND_PREFIX_OPCODE); | |
4419 | else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE) | |
4420 | { | |
4421 | as_warn (_("replacing `rep'/`repe' prefix by `bnd'")); | |
4422 | i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE; | |
4423 | } | |
4424 | } | |
7e8b059b | 4425 | |
29b0f896 | 4426 | /* Check string instruction segment overrides. */ |
40fb9820 | 4427 | if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) |
29b0f896 AM |
4428 | { |
4429 | if (!check_string ()) | |
5dd0794d | 4430 | return; |
fc0763e6 | 4431 | i.disp_operands = 0; |
29b0f896 | 4432 | } |
5dd0794d | 4433 | |
b6f8c7c4 L |
4434 | if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize) |
4435 | optimize_encoding (); | |
4436 | ||
29b0f896 AM |
4437 | if (!process_suffix ()) |
4438 | return; | |
e413e4e9 | 4439 | |
bc0844ae L |
4440 | /* Update operand types. */ |
4441 | for (j = 0; j < i.operands; j++) | |
4442 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
4443 | ||
29b0f896 AM |
4444 | /* Make still unresolved immediate matches conform to size of immediate |
4445 | given in i.suffix. */ | |
4446 | if (!finalize_imm ()) | |
4447 | return; | |
252b5132 | 4448 | |
40fb9820 | 4449 | if (i.types[0].bitfield.imm1) |
29b0f896 | 4450 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 4451 | |
9afe6eb8 L |
4452 | /* We only need to check those implicit registers for instructions |
4453 | with 3 operands or less. */ | |
4454 | if (i.operands <= 3) | |
4455 | for (j = 0; j < i.operands; j++) | |
4456 | if (i.types[j].bitfield.inoutportreg | |
4457 | || i.types[j].bitfield.shiftcount | |
1b54b8d7 | 4458 | || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword)) |
9afe6eb8 | 4459 | i.reg_operands--; |
40fb9820 | 4460 | |
c0f3af97 L |
4461 | /* ImmExt should be processed after SSE2AVX. */ |
4462 | if (!i.tm.opcode_modifier.sse2avx | |
4463 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 4464 | process_immext (); |
252b5132 | 4465 | |
29b0f896 AM |
4466 | /* For insns with operands there are more diddles to do to the opcode. */ |
4467 | if (i.operands) | |
4468 | { | |
4469 | if (!process_operands ()) | |
4470 | return; | |
4471 | } | |
40fb9820 | 4472 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
4473 | { |
4474 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
4475 | as_warn (_("translating to `%sp'"), i.tm.name); | |
4476 | } | |
252b5132 | 4477 | |
7a8655d2 | 4478 | if (is_any_vex_encoding (&i.tm)) |
9e5e5283 | 4479 | { |
c1dc7af5 | 4480 | if (!cpu_arch_flags.bitfield.cpui286) |
9e5e5283 | 4481 | { |
c1dc7af5 | 4482 | as_bad (_("instruction `%s' isn't supported outside of protected mode."), |
9e5e5283 L |
4483 | i.tm.name); |
4484 | return; | |
4485 | } | |
c0f3af97 | 4486 | |
9e5e5283 L |
4487 | if (i.tm.opcode_modifier.vex) |
4488 | build_vex_prefix (t); | |
4489 | else | |
4490 | build_evex_prefix (); | |
4491 | } | |
43234a1e | 4492 | |
5dd85c99 SP |
4493 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
4494 | instructions may define INT_OPCODE as well, so avoid this corner | |
4495 | case for those instructions that use MODRM. */ | |
4496 | if (i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
4497 | && !i.tm.opcode_modifier.modrm |
4498 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
4499 | { |
4500 | i.tm.base_opcode = INT3_OPCODE; | |
4501 | i.imm_operands = 0; | |
4502 | } | |
252b5132 | 4503 | |
40fb9820 L |
4504 | if ((i.tm.opcode_modifier.jump |
4505 | || i.tm.opcode_modifier.jumpbyte | |
4506 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 AM |
4507 | && i.op[0].disps->X_op == O_constant) |
4508 | { | |
4509 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
4510 | the absolute address given by the constant. Since ix86 jumps and | |
4511 | calls are pc relative, we need to generate a reloc. */ | |
4512 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
4513 | i.op[0].disps->X_op = O_symbol; | |
4514 | } | |
252b5132 | 4515 | |
40fb9820 | 4516 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 4517 | i.rex |= REX_W; |
252b5132 | 4518 | |
29b0f896 AM |
4519 | /* For 8 bit registers we need an empty rex prefix. Also if the |
4520 | instruction already has a prefix, we need to convert old | |
4521 | registers to new ones. */ | |
773f551c | 4522 | |
bab6aec1 | 4523 | if ((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte |
29b0f896 | 4524 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
bab6aec1 | 4525 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte |
29b0f896 | 4526 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
bab6aec1 JB |
4527 | || (((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte) |
4528 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte)) | |
29b0f896 AM |
4529 | && i.rex != 0)) |
4530 | { | |
4531 | int x; | |
726c5dcd | 4532 | |
29b0f896 AM |
4533 | i.rex |= REX_OPCODE; |
4534 | for (x = 0; x < 2; x++) | |
4535 | { | |
4536 | /* Look for 8 bit operand that uses old registers. */ | |
bab6aec1 | 4537 | if (i.types[x].bitfield.class == Reg && i.types[x].bitfield.byte |
29b0f896 | 4538 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 4539 | { |
29b0f896 AM |
4540 | /* In case it is "hi" register, give up. */ |
4541 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 4542 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 4543 | "instruction requiring REX prefix."), |
a540244d | 4544 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 4545 | |
29b0f896 AM |
4546 | /* Otherwise it is equivalent to the extended register. |
4547 | Since the encoding doesn't change this is merely | |
4548 | cosmetic cleanup for debug output. */ | |
4549 | ||
4550 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 4551 | } |
29b0f896 AM |
4552 | } |
4553 | } | |
773f551c | 4554 | |
6b6b6807 L |
4555 | if (i.rex == 0 && i.rex_encoding) |
4556 | { | |
4557 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand | |
4558 | that uses legacy register. If it is "hi" register, don't add | |
4559 | the REX_OPCODE byte. */ | |
4560 | int x; | |
4561 | for (x = 0; x < 2; x++) | |
bab6aec1 | 4562 | if (i.types[x].bitfield.class == Reg |
6b6b6807 L |
4563 | && i.types[x].bitfield.byte |
4564 | && (i.op[x].regs->reg_flags & RegRex64) == 0 | |
4565 | && i.op[x].regs->reg_num > 3) | |
4566 | { | |
4567 | i.rex_encoding = FALSE; | |
4568 | break; | |
4569 | } | |
4570 | ||
4571 | if (i.rex_encoding) | |
4572 | i.rex = REX_OPCODE; | |
4573 | } | |
4574 | ||
7ab9ffdd | 4575 | if (i.rex != 0) |
29b0f896 AM |
4576 | add_prefix (REX_OPCODE | i.rex); |
4577 | ||
4578 | /* We are ready to output the insn. */ | |
4579 | output_insn (); | |
4580 | } | |
4581 | ||
4582 | static char * | |
e3bb37b5 | 4583 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
4584 | { |
4585 | char *l = line; | |
4586 | char *token_start = l; | |
4587 | char *mnem_p; | |
5c6af06e | 4588 | int supported; |
d3ce72d0 | 4589 | const insn_template *t; |
b6169b20 | 4590 | char *dot_p = NULL; |
29b0f896 | 4591 | |
29b0f896 AM |
4592 | while (1) |
4593 | { | |
4594 | mnem_p = mnemonic; | |
4595 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
4596 | { | |
b6169b20 L |
4597 | if (*mnem_p == '.') |
4598 | dot_p = mnem_p; | |
29b0f896 AM |
4599 | mnem_p++; |
4600 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 4601 | { |
29b0f896 AM |
4602 | as_bad (_("no such instruction: `%s'"), token_start); |
4603 | return NULL; | |
4604 | } | |
4605 | l++; | |
4606 | } | |
4607 | if (!is_space_char (*l) | |
4608 | && *l != END_OF_INSN | |
e44823cf JB |
4609 | && (intel_syntax |
4610 | || (*l != PREFIX_SEPARATOR | |
4611 | && *l != ','))) | |
29b0f896 AM |
4612 | { |
4613 | as_bad (_("invalid character %s in mnemonic"), | |
4614 | output_invalid (*l)); | |
4615 | return NULL; | |
4616 | } | |
4617 | if (token_start == l) | |
4618 | { | |
e44823cf | 4619 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
4620 | as_bad (_("expecting prefix; got nothing")); |
4621 | else | |
4622 | as_bad (_("expecting mnemonic; got nothing")); | |
4623 | return NULL; | |
4624 | } | |
45288df1 | 4625 | |
29b0f896 | 4626 | /* Look up instruction (or prefix) via hash table. */ |
d3ce72d0 | 4627 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
47926f60 | 4628 | |
29b0f896 AM |
4629 | if (*l != END_OF_INSN |
4630 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
4631 | && current_templates | |
40fb9820 | 4632 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 4633 | { |
c6fb90c8 | 4634 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
4635 | { |
4636 | as_bad ((flag_code != CODE_64BIT | |
4637 | ? _("`%s' is only supported in 64-bit mode") | |
4638 | : _("`%s' is not supported in 64-bit mode")), | |
4639 | current_templates->start->name); | |
4640 | return NULL; | |
4641 | } | |
29b0f896 AM |
4642 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
4643 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
673fe0f0 JB |
4644 | if ((current_templates->start->opcode_modifier.size == SIZE16 |
4645 | || current_templates->start->opcode_modifier.size == SIZE32) | |
29b0f896 | 4646 | && flag_code != CODE_64BIT |
673fe0f0 | 4647 | && ((current_templates->start->opcode_modifier.size == SIZE32) |
29b0f896 AM |
4648 | ^ (flag_code == CODE_16BIT))) |
4649 | { | |
4650 | as_bad (_("redundant %s prefix"), | |
4651 | current_templates->start->name); | |
4652 | return NULL; | |
45288df1 | 4653 | } |
86fa6981 | 4654 | if (current_templates->start->opcode_length == 0) |
29b0f896 | 4655 | { |
86fa6981 L |
4656 | /* Handle pseudo prefixes. */ |
4657 | switch (current_templates->start->base_opcode) | |
4658 | { | |
4659 | case 0x0: | |
4660 | /* {disp8} */ | |
4661 | i.disp_encoding = disp_encoding_8bit; | |
4662 | break; | |
4663 | case 0x1: | |
4664 | /* {disp32} */ | |
4665 | i.disp_encoding = disp_encoding_32bit; | |
4666 | break; | |
4667 | case 0x2: | |
4668 | /* {load} */ | |
4669 | i.dir_encoding = dir_encoding_load; | |
4670 | break; | |
4671 | case 0x3: | |
4672 | /* {store} */ | |
4673 | i.dir_encoding = dir_encoding_store; | |
4674 | break; | |
4675 | case 0x4: | |
4676 | /* {vex2} */ | |
4677 | i.vec_encoding = vex_encoding_vex2; | |
4678 | break; | |
4679 | case 0x5: | |
4680 | /* {vex3} */ | |
4681 | i.vec_encoding = vex_encoding_vex3; | |
4682 | break; | |
4683 | case 0x6: | |
4684 | /* {evex} */ | |
4685 | i.vec_encoding = vex_encoding_evex; | |
4686 | break; | |
6b6b6807 L |
4687 | case 0x7: |
4688 | /* {rex} */ | |
4689 | i.rex_encoding = TRUE; | |
4690 | break; | |
b6f8c7c4 L |
4691 | case 0x8: |
4692 | /* {nooptimize} */ | |
4693 | i.no_optimize = TRUE; | |
4694 | break; | |
86fa6981 L |
4695 | default: |
4696 | abort (); | |
4697 | } | |
4698 | } | |
4699 | else | |
4700 | { | |
4701 | /* Add prefix, checking for repeated prefixes. */ | |
4e9ac44a | 4702 | switch (add_prefix (current_templates->start->base_opcode)) |
86fa6981 | 4703 | { |
4e9ac44a L |
4704 | case PREFIX_EXIST: |
4705 | return NULL; | |
4706 | case PREFIX_DS: | |
d777820b | 4707 | if (current_templates->start->cpu_flags.bitfield.cpuibt) |
4e9ac44a L |
4708 | i.notrack_prefix = current_templates->start->name; |
4709 | break; | |
4710 | case PREFIX_REP: | |
4711 | if (current_templates->start->cpu_flags.bitfield.cpuhle) | |
4712 | i.hle_prefix = current_templates->start->name; | |
4713 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) | |
4714 | i.bnd_prefix = current_templates->start->name; | |
4715 | else | |
4716 | i.rep_prefix = current_templates->start->name; | |
4717 | break; | |
4718 | default: | |
4719 | break; | |
86fa6981 | 4720 | } |
29b0f896 AM |
4721 | } |
4722 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
4723 | token_start = ++l; | |
4724 | } | |
4725 | else | |
4726 | break; | |
4727 | } | |
45288df1 | 4728 | |
30a55f88 | 4729 | if (!current_templates) |
b6169b20 | 4730 | { |
07d5e953 JB |
4731 | /* Deprecated functionality (new code should use pseudo-prefixes instead): |
4732 | Check if we should swap operand or force 32bit displacement in | |
f8a5c266 | 4733 | encoding. */ |
30a55f88 | 4734 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
64c49ab3 | 4735 | i.dir_encoding = dir_encoding_swap; |
8d63c93e | 4736 | else if (mnem_p - 3 == dot_p |
a501d77e L |
4737 | && dot_p[1] == 'd' |
4738 | && dot_p[2] == '8') | |
4739 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 4740 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
4741 | && dot_p[1] == 'd' |
4742 | && dot_p[2] == '3' | |
4743 | && dot_p[3] == '2') | |
a501d77e | 4744 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
4745 | else |
4746 | goto check_suffix; | |
4747 | mnem_p = dot_p; | |
4748 | *dot_p = '\0'; | |
d3ce72d0 | 4749 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
b6169b20 L |
4750 | } |
4751 | ||
29b0f896 AM |
4752 | if (!current_templates) |
4753 | { | |
b6169b20 | 4754 | check_suffix: |
1c529385 | 4755 | if (mnem_p > mnemonic) |
29b0f896 | 4756 | { |
1c529385 LH |
4757 | /* See if we can get a match by trimming off a suffix. */ |
4758 | switch (mnem_p[-1]) | |
29b0f896 | 4759 | { |
1c529385 LH |
4760 | case WORD_MNEM_SUFFIX: |
4761 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) | |
29b0f896 AM |
4762 | i.suffix = SHORT_MNEM_SUFFIX; |
4763 | else | |
1c529385 LH |
4764 | /* Fall through. */ |
4765 | case BYTE_MNEM_SUFFIX: | |
4766 | case QWORD_MNEM_SUFFIX: | |
4767 | i.suffix = mnem_p[-1]; | |
29b0f896 | 4768 | mnem_p[-1] = '\0'; |
d3ce72d0 | 4769 | current_templates = (const templates *) hash_find (op_hash, |
1c529385 LH |
4770 | mnemonic); |
4771 | break; | |
4772 | case SHORT_MNEM_SUFFIX: | |
4773 | case LONG_MNEM_SUFFIX: | |
4774 | if (!intel_syntax) | |
4775 | { | |
4776 | i.suffix = mnem_p[-1]; | |
4777 | mnem_p[-1] = '\0'; | |
4778 | current_templates = (const templates *) hash_find (op_hash, | |
4779 | mnemonic); | |
4780 | } | |
4781 | break; | |
4782 | ||
4783 | /* Intel Syntax. */ | |
4784 | case 'd': | |
4785 | if (intel_syntax) | |
4786 | { | |
4787 | if (intel_float_operand (mnemonic) == 1) | |
4788 | i.suffix = SHORT_MNEM_SUFFIX; | |
4789 | else | |
4790 | i.suffix = LONG_MNEM_SUFFIX; | |
4791 | mnem_p[-1] = '\0'; | |
4792 | current_templates = (const templates *) hash_find (op_hash, | |
4793 | mnemonic); | |
4794 | } | |
4795 | break; | |
29b0f896 | 4796 | } |
29b0f896 | 4797 | } |
1c529385 | 4798 | |
29b0f896 AM |
4799 | if (!current_templates) |
4800 | { | |
4801 | as_bad (_("no such instruction: `%s'"), token_start); | |
4802 | return NULL; | |
4803 | } | |
4804 | } | |
252b5132 | 4805 | |
40fb9820 L |
4806 | if (current_templates->start->opcode_modifier.jump |
4807 | || current_templates->start->opcode_modifier.jumpbyte) | |
29b0f896 AM |
4808 | { |
4809 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
4810 | predict taken and predict not taken respectively. | |
4811 | I'm not sure that branch hints actually do anything on loop | |
4812 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
4813 | may work in the future and it doesn't hurt to accept them | |
4814 | now. */ | |
4815 | if (l[0] == ',' && l[1] == 'p') | |
4816 | { | |
4817 | if (l[2] == 't') | |
4818 | { | |
4819 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
4820 | return NULL; | |
4821 | l += 3; | |
4822 | } | |
4823 | else if (l[2] == 'n') | |
4824 | { | |
4825 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
4826 | return NULL; | |
4827 | l += 3; | |
4828 | } | |
4829 | } | |
4830 | } | |
4831 | /* Any other comma loses. */ | |
4832 | if (*l == ',') | |
4833 | { | |
4834 | as_bad (_("invalid character %s in mnemonic"), | |
4835 | output_invalid (*l)); | |
4836 | return NULL; | |
4837 | } | |
252b5132 | 4838 | |
29b0f896 | 4839 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
4840 | supported = 0; |
4841 | for (t = current_templates->start; t < current_templates->end; ++t) | |
4842 | { | |
c0f3af97 L |
4843 | supported |= cpu_flags_match (t); |
4844 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
548d0ee6 JB |
4845 | { |
4846 | if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT)) | |
4847 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
3629bb00 | 4848 | |
548d0ee6 JB |
4849 | return l; |
4850 | } | |
29b0f896 | 4851 | } |
3629bb00 | 4852 | |
548d0ee6 JB |
4853 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
4854 | as_bad (flag_code == CODE_64BIT | |
4855 | ? _("`%s' is not supported in 64-bit mode") | |
4856 | : _("`%s' is only supported in 64-bit mode"), | |
4857 | current_templates->start->name); | |
4858 | else | |
4859 | as_bad (_("`%s' is not supported on `%s%s'"), | |
4860 | current_templates->start->name, | |
4861 | cpu_arch_name ? cpu_arch_name : default_arch, | |
4862 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
252b5132 | 4863 | |
548d0ee6 | 4864 | return NULL; |
29b0f896 | 4865 | } |
252b5132 | 4866 | |
29b0f896 | 4867 | static char * |
e3bb37b5 | 4868 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
4869 | { |
4870 | char *token_start; | |
3138f287 | 4871 | |
29b0f896 AM |
4872 | /* 1 if operand is pending after ','. */ |
4873 | unsigned int expecting_operand = 0; | |
252b5132 | 4874 | |
29b0f896 AM |
4875 | /* Non-zero if operand parens not balanced. */ |
4876 | unsigned int paren_not_balanced; | |
4877 | ||
4878 | while (*l != END_OF_INSN) | |
4879 | { | |
4880 | /* Skip optional white space before operand. */ | |
4881 | if (is_space_char (*l)) | |
4882 | ++l; | |
d02603dc | 4883 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
4884 | { |
4885 | as_bad (_("invalid character %s before operand %d"), | |
4886 | output_invalid (*l), | |
4887 | i.operands + 1); | |
4888 | return NULL; | |
4889 | } | |
d02603dc | 4890 | token_start = l; /* After white space. */ |
29b0f896 AM |
4891 | paren_not_balanced = 0; |
4892 | while (paren_not_balanced || *l != ',') | |
4893 | { | |
4894 | if (*l == END_OF_INSN) | |
4895 | { | |
4896 | if (paren_not_balanced) | |
4897 | { | |
4898 | if (!intel_syntax) | |
4899 | as_bad (_("unbalanced parenthesis in operand %d."), | |
4900 | i.operands + 1); | |
4901 | else | |
4902 | as_bad (_("unbalanced brackets in operand %d."), | |
4903 | i.operands + 1); | |
4904 | return NULL; | |
4905 | } | |
4906 | else | |
4907 | break; /* we are done */ | |
4908 | } | |
d02603dc | 4909 | else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') |
29b0f896 AM |
4910 | { |
4911 | as_bad (_("invalid character %s in operand %d"), | |
4912 | output_invalid (*l), | |
4913 | i.operands + 1); | |
4914 | return NULL; | |
4915 | } | |
4916 | if (!intel_syntax) | |
4917 | { | |
4918 | if (*l == '(') | |
4919 | ++paren_not_balanced; | |
4920 | if (*l == ')') | |
4921 | --paren_not_balanced; | |
4922 | } | |
4923 | else | |
4924 | { | |
4925 | if (*l == '[') | |
4926 | ++paren_not_balanced; | |
4927 | if (*l == ']') | |
4928 | --paren_not_balanced; | |
4929 | } | |
4930 | l++; | |
4931 | } | |
4932 | if (l != token_start) | |
4933 | { /* Yes, we've read in another operand. */ | |
4934 | unsigned int operand_ok; | |
4935 | this_operand = i.operands++; | |
4936 | if (i.operands > MAX_OPERANDS) | |
4937 | { | |
4938 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
4939 | MAX_OPERANDS); | |
4940 | return NULL; | |
4941 | } | |
9d46ce34 | 4942 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
4943 | /* Now parse operand adding info to 'i' as we go along. */ |
4944 | END_STRING_AND_SAVE (l); | |
4945 | ||
1286ab78 L |
4946 | if (i.mem_operands > 1) |
4947 | { | |
4948 | as_bad (_("too many memory references for `%s'"), | |
4949 | mnemonic); | |
4950 | return 0; | |
4951 | } | |
4952 | ||
29b0f896 AM |
4953 | if (intel_syntax) |
4954 | operand_ok = | |
4955 | i386_intel_operand (token_start, | |
4956 | intel_float_operand (mnemonic)); | |
4957 | else | |
a7619375 | 4958 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
4959 | |
4960 | RESTORE_END_STRING (l); | |
4961 | if (!operand_ok) | |
4962 | return NULL; | |
4963 | } | |
4964 | else | |
4965 | { | |
4966 | if (expecting_operand) | |
4967 | { | |
4968 | expecting_operand_after_comma: | |
4969 | as_bad (_("expecting operand after ','; got nothing")); | |
4970 | return NULL; | |
4971 | } | |
4972 | if (*l == ',') | |
4973 | { | |
4974 | as_bad (_("expecting operand before ','; got nothing")); | |
4975 | return NULL; | |
4976 | } | |
4977 | } | |
7f3f1ea2 | 4978 | |
29b0f896 AM |
4979 | /* Now *l must be either ',' or END_OF_INSN. */ |
4980 | if (*l == ',') | |
4981 | { | |
4982 | if (*++l == END_OF_INSN) | |
4983 | { | |
4984 | /* Just skip it, if it's \n complain. */ | |
4985 | goto expecting_operand_after_comma; | |
4986 | } | |
4987 | expecting_operand = 1; | |
4988 | } | |
4989 | } | |
4990 | return l; | |
4991 | } | |
7f3f1ea2 | 4992 | |
050dfa73 | 4993 | static void |
4d456e3d | 4994 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
4995 | { |
4996 | union i386_op temp_op; | |
40fb9820 | 4997 | i386_operand_type temp_type; |
c48dadc9 | 4998 | unsigned int temp_flags; |
050dfa73 | 4999 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 5000 | |
050dfa73 MM |
5001 | temp_type = i.types[xchg2]; |
5002 | i.types[xchg2] = i.types[xchg1]; | |
5003 | i.types[xchg1] = temp_type; | |
c48dadc9 JB |
5004 | |
5005 | temp_flags = i.flags[xchg2]; | |
5006 | i.flags[xchg2] = i.flags[xchg1]; | |
5007 | i.flags[xchg1] = temp_flags; | |
5008 | ||
050dfa73 MM |
5009 | temp_op = i.op[xchg2]; |
5010 | i.op[xchg2] = i.op[xchg1]; | |
5011 | i.op[xchg1] = temp_op; | |
c48dadc9 | 5012 | |
050dfa73 MM |
5013 | temp_reloc = i.reloc[xchg2]; |
5014 | i.reloc[xchg2] = i.reloc[xchg1]; | |
5015 | i.reloc[xchg1] = temp_reloc; | |
43234a1e L |
5016 | |
5017 | if (i.mask) | |
5018 | { | |
5019 | if (i.mask->operand == xchg1) | |
5020 | i.mask->operand = xchg2; | |
5021 | else if (i.mask->operand == xchg2) | |
5022 | i.mask->operand = xchg1; | |
5023 | } | |
5024 | if (i.broadcast) | |
5025 | { | |
5026 | if (i.broadcast->operand == xchg1) | |
5027 | i.broadcast->operand = xchg2; | |
5028 | else if (i.broadcast->operand == xchg2) | |
5029 | i.broadcast->operand = xchg1; | |
5030 | } | |
5031 | if (i.rounding) | |
5032 | { | |
5033 | if (i.rounding->operand == xchg1) | |
5034 | i.rounding->operand = xchg2; | |
5035 | else if (i.rounding->operand == xchg2) | |
5036 | i.rounding->operand = xchg1; | |
5037 | } | |
050dfa73 MM |
5038 | } |
5039 | ||
29b0f896 | 5040 | static void |
e3bb37b5 | 5041 | swap_operands (void) |
29b0f896 | 5042 | { |
b7c61d9a | 5043 | switch (i.operands) |
050dfa73 | 5044 | { |
c0f3af97 | 5045 | case 5: |
b7c61d9a | 5046 | case 4: |
4d456e3d | 5047 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 5048 | /* Fall through. */ |
b7c61d9a L |
5049 | case 3: |
5050 | case 2: | |
4d456e3d | 5051 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
5052 | break; |
5053 | default: | |
5054 | abort (); | |
29b0f896 | 5055 | } |
29b0f896 AM |
5056 | |
5057 | if (i.mem_operands == 2) | |
5058 | { | |
5059 | const seg_entry *temp_seg; | |
5060 | temp_seg = i.seg[0]; | |
5061 | i.seg[0] = i.seg[1]; | |
5062 | i.seg[1] = temp_seg; | |
5063 | } | |
5064 | } | |
252b5132 | 5065 | |
29b0f896 AM |
5066 | /* Try to ensure constant immediates are represented in the smallest |
5067 | opcode possible. */ | |
5068 | static void | |
e3bb37b5 | 5069 | optimize_imm (void) |
29b0f896 AM |
5070 | { |
5071 | char guess_suffix = 0; | |
5072 | int op; | |
252b5132 | 5073 | |
29b0f896 AM |
5074 | if (i.suffix) |
5075 | guess_suffix = i.suffix; | |
5076 | else if (i.reg_operands) | |
5077 | { | |
5078 | /* Figure out a suffix from the last register operand specified. | |
5079 | We can't do this properly yet, ie. excluding InOutPortReg, | |
5080 | but the following works for instructions with immediates. | |
5081 | In any case, we can't set i.suffix yet. */ | |
5082 | for (op = i.operands; --op >= 0;) | |
bab6aec1 JB |
5083 | if (i.types[op].bitfield.class != Reg) |
5084 | continue; | |
5085 | else if (i.types[op].bitfield.byte) | |
7ab9ffdd | 5086 | { |
40fb9820 L |
5087 | guess_suffix = BYTE_MNEM_SUFFIX; |
5088 | break; | |
5089 | } | |
bab6aec1 | 5090 | else if (i.types[op].bitfield.word) |
252b5132 | 5091 | { |
40fb9820 L |
5092 | guess_suffix = WORD_MNEM_SUFFIX; |
5093 | break; | |
5094 | } | |
bab6aec1 | 5095 | else if (i.types[op].bitfield.dword) |
40fb9820 L |
5096 | { |
5097 | guess_suffix = LONG_MNEM_SUFFIX; | |
5098 | break; | |
5099 | } | |
bab6aec1 | 5100 | else if (i.types[op].bitfield.qword) |
40fb9820 L |
5101 | { |
5102 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 5103 | break; |
252b5132 | 5104 | } |
29b0f896 AM |
5105 | } |
5106 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
5107 | guess_suffix = WORD_MNEM_SUFFIX; | |
5108 | ||
5109 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 5110 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
5111 | { |
5112 | switch (i.op[op].imms->X_op) | |
252b5132 | 5113 | { |
29b0f896 AM |
5114 | case O_constant: |
5115 | /* If a suffix is given, this operand may be shortened. */ | |
5116 | switch (guess_suffix) | |
252b5132 | 5117 | { |
29b0f896 | 5118 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
5119 | i.types[op].bitfield.imm32 = 1; |
5120 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5121 | break; |
5122 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
5123 | i.types[op].bitfield.imm16 = 1; |
5124 | i.types[op].bitfield.imm32 = 1; | |
5125 | i.types[op].bitfield.imm32s = 1; | |
5126 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5127 | break; |
5128 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
5129 | i.types[op].bitfield.imm8 = 1; |
5130 | i.types[op].bitfield.imm8s = 1; | |
5131 | i.types[op].bitfield.imm16 = 1; | |
5132 | i.types[op].bitfield.imm32 = 1; | |
5133 | i.types[op].bitfield.imm32s = 1; | |
5134 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 5135 | break; |
252b5132 | 5136 | } |
252b5132 | 5137 | |
29b0f896 AM |
5138 | /* If this operand is at most 16 bits, convert it |
5139 | to a signed 16 bit number before trying to see | |
5140 | whether it will fit in an even smaller size. | |
5141 | This allows a 16-bit operand such as $0xffe0 to | |
5142 | be recognised as within Imm8S range. */ | |
40fb9820 | 5143 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 5144 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 5145 | { |
29b0f896 AM |
5146 | i.op[op].imms->X_add_number = |
5147 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
5148 | } | |
a28def75 L |
5149 | #ifdef BFD64 |
5150 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 5151 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
5152 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
5153 | == 0)) | |
5154 | { | |
5155 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
5156 | ^ ((offsetT) 1 << 31)) | |
5157 | - ((offsetT) 1 << 31)); | |
5158 | } | |
a28def75 | 5159 | #endif |
40fb9820 | 5160 | i.types[op] |
c6fb90c8 L |
5161 | = operand_type_or (i.types[op], |
5162 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 5163 | |
29b0f896 AM |
5164 | /* We must avoid matching of Imm32 templates when 64bit |
5165 | only immediate is available. */ | |
5166 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 5167 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 5168 | break; |
252b5132 | 5169 | |
29b0f896 AM |
5170 | case O_absent: |
5171 | case O_register: | |
5172 | abort (); | |
5173 | ||
5174 | /* Symbols and expressions. */ | |
5175 | default: | |
9cd96992 JB |
5176 | /* Convert symbolic operand to proper sizes for matching, but don't |
5177 | prevent matching a set of insns that only supports sizes other | |
5178 | than those matching the insn suffix. */ | |
5179 | { | |
40fb9820 | 5180 | i386_operand_type mask, allowed; |
d3ce72d0 | 5181 | const insn_template *t; |
9cd96992 | 5182 | |
0dfbf9d7 L |
5183 | operand_type_set (&mask, 0); |
5184 | operand_type_set (&allowed, 0); | |
40fb9820 | 5185 | |
4eed87de AM |
5186 | for (t = current_templates->start; |
5187 | t < current_templates->end; | |
5188 | ++t) | |
bab6aec1 JB |
5189 | { |
5190 | allowed = operand_type_or (allowed, t->operand_types[op]); | |
5191 | allowed = operand_type_and (allowed, anyimm); | |
5192 | } | |
9cd96992 JB |
5193 | switch (guess_suffix) |
5194 | { | |
5195 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
5196 | mask.bitfield.imm64 = 1; |
5197 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
5198 | break; |
5199 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 5200 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
5201 | break; |
5202 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 5203 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
5204 | break; |
5205 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 5206 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
5207 | break; |
5208 | default: | |
9cd96992 JB |
5209 | break; |
5210 | } | |
c6fb90c8 | 5211 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 5212 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 5213 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 5214 | } |
29b0f896 | 5215 | break; |
252b5132 | 5216 | } |
29b0f896 AM |
5217 | } |
5218 | } | |
47926f60 | 5219 | |
29b0f896 AM |
5220 | /* Try to use the smallest displacement type too. */ |
5221 | static void | |
e3bb37b5 | 5222 | optimize_disp (void) |
29b0f896 AM |
5223 | { |
5224 | int op; | |
3e73aa7c | 5225 | |
29b0f896 | 5226 | for (op = i.operands; --op >= 0;) |
40fb9820 | 5227 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 5228 | { |
b300c311 | 5229 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 5230 | { |
91d6fa6a | 5231 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 5232 | |
40fb9820 | 5233 | if (i.types[op].bitfield.disp16 |
91d6fa6a | 5234 | && (op_disp & ~(offsetT) 0xffff) == 0) |
b300c311 L |
5235 | { |
5236 | /* If this operand is at most 16 bits, convert | |
5237 | to a signed 16 bit number and don't use 64bit | |
5238 | displacement. */ | |
91d6fa6a | 5239 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
40fb9820 | 5240 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5241 | } |
a28def75 L |
5242 | #ifdef BFD64 |
5243 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ | |
40fb9820 | 5244 | if (i.types[op].bitfield.disp32 |
91d6fa6a | 5245 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
b300c311 L |
5246 | { |
5247 | /* If this operand is at most 32 bits, convert | |
5248 | to a signed 32 bit number and don't use 64bit | |
5249 | displacement. */ | |
91d6fa6a NC |
5250 | op_disp &= (((offsetT) 2 << 31) - 1); |
5251 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 5252 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5253 | } |
a28def75 | 5254 | #endif |
91d6fa6a | 5255 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 5256 | { |
40fb9820 L |
5257 | i.types[op].bitfield.disp8 = 0; |
5258 | i.types[op].bitfield.disp16 = 0; | |
5259 | i.types[op].bitfield.disp32 = 0; | |
5260 | i.types[op].bitfield.disp32s = 0; | |
5261 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
5262 | i.op[op].disps = 0; |
5263 | i.disp_operands--; | |
5264 | } | |
5265 | else if (flag_code == CODE_64BIT) | |
5266 | { | |
91d6fa6a | 5267 | if (fits_in_signed_long (op_disp)) |
28a9d8f5 | 5268 | { |
40fb9820 L |
5269 | i.types[op].bitfield.disp64 = 0; |
5270 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 5271 | } |
0e1147d9 | 5272 | if (i.prefix[ADDR_PREFIX] |
91d6fa6a | 5273 | && fits_in_unsigned_long (op_disp)) |
40fb9820 | 5274 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 5275 | } |
40fb9820 L |
5276 | if ((i.types[op].bitfield.disp32 |
5277 | || i.types[op].bitfield.disp32s | |
5278 | || i.types[op].bitfield.disp16) | |
b5014f7a | 5279 | && fits_in_disp8 (op_disp)) |
40fb9820 | 5280 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 5281 | } |
67a4f2b7 AO |
5282 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
5283 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
5284 | { | |
5285 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
5286 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
5287 | i.types[op].bitfield.disp8 = 0; |
5288 | i.types[op].bitfield.disp16 = 0; | |
5289 | i.types[op].bitfield.disp32 = 0; | |
5290 | i.types[op].bitfield.disp32s = 0; | |
5291 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
5292 | } |
5293 | else | |
b300c311 | 5294 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 5295 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 5296 | } |
29b0f896 AM |
5297 | } |
5298 | ||
4a1b91ea L |
5299 | /* Return 1 if there is a match in broadcast bytes between operand |
5300 | GIVEN and instruction template T. */ | |
5301 | ||
5302 | static INLINE int | |
5303 | match_broadcast_size (const insn_template *t, unsigned int given) | |
5304 | { | |
5305 | return ((t->opcode_modifier.broadcast == BYTE_BROADCAST | |
5306 | && i.types[given].bitfield.byte) | |
5307 | || (t->opcode_modifier.broadcast == WORD_BROADCAST | |
5308 | && i.types[given].bitfield.word) | |
5309 | || (t->opcode_modifier.broadcast == DWORD_BROADCAST | |
5310 | && i.types[given].bitfield.dword) | |
5311 | || (t->opcode_modifier.broadcast == QWORD_BROADCAST | |
5312 | && i.types[given].bitfield.qword)); | |
5313 | } | |
5314 | ||
6c30d220 L |
5315 | /* Check if operands are valid for the instruction. */ |
5316 | ||
5317 | static int | |
5318 | check_VecOperands (const insn_template *t) | |
5319 | { | |
43234a1e | 5320 | unsigned int op; |
e2195274 JB |
5321 | i386_cpu_flags cpu; |
5322 | static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; | |
5323 | ||
5324 | /* Templates allowing for ZMMword as well as YMMword and/or XMMword for | |
5325 | any one operand are implicity requiring AVX512VL support if the actual | |
5326 | operand size is YMMword or XMMword. Since this function runs after | |
5327 | template matching, there's no need to check for YMMword/XMMword in | |
5328 | the template. */ | |
5329 | cpu = cpu_flags_and (t->cpu_flags, avx512); | |
5330 | if (!cpu_flags_all_zero (&cpu) | |
5331 | && !t->cpu_flags.bitfield.cpuavx512vl | |
5332 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
5333 | { | |
5334 | for (op = 0; op < t->operands; ++op) | |
5335 | { | |
5336 | if (t->operand_types[op].bitfield.zmmword | |
5337 | && (i.types[op].bitfield.ymmword | |
5338 | || i.types[op].bitfield.xmmword)) | |
5339 | { | |
5340 | i.error = unsupported; | |
5341 | return 1; | |
5342 | } | |
5343 | } | |
5344 | } | |
43234a1e | 5345 | |
6c30d220 L |
5346 | /* Without VSIB byte, we can't have a vector register for index. */ |
5347 | if (!t->opcode_modifier.vecsib | |
5348 | && i.index_reg | |
1b54b8d7 JB |
5349 | && (i.index_reg->reg_type.bitfield.xmmword |
5350 | || i.index_reg->reg_type.bitfield.ymmword | |
5351 | || i.index_reg->reg_type.bitfield.zmmword)) | |
6c30d220 L |
5352 | { |
5353 | i.error = unsupported_vector_index_register; | |
5354 | return 1; | |
5355 | } | |
5356 | ||
ad8ecc81 MZ |
5357 | /* Check if default mask is allowed. */ |
5358 | if (t->opcode_modifier.nodefmask | |
5359 | && (!i.mask || i.mask->mask->reg_num == 0)) | |
5360 | { | |
5361 | i.error = no_default_mask; | |
5362 | return 1; | |
5363 | } | |
5364 | ||
7bab8ab5 JB |
5365 | /* For VSIB byte, we need a vector register for index, and all vector |
5366 | registers must be distinct. */ | |
5367 | if (t->opcode_modifier.vecsib) | |
5368 | { | |
5369 | if (!i.index_reg | |
6c30d220 | 5370 | || !((t->opcode_modifier.vecsib == VecSIB128 |
1b54b8d7 | 5371 | && i.index_reg->reg_type.bitfield.xmmword) |
6c30d220 | 5372 | || (t->opcode_modifier.vecsib == VecSIB256 |
1b54b8d7 | 5373 | && i.index_reg->reg_type.bitfield.ymmword) |
43234a1e | 5374 | || (t->opcode_modifier.vecsib == VecSIB512 |
1b54b8d7 | 5375 | && i.index_reg->reg_type.bitfield.zmmword))) |
7bab8ab5 JB |
5376 | { |
5377 | i.error = invalid_vsib_address; | |
5378 | return 1; | |
5379 | } | |
5380 | ||
43234a1e L |
5381 | gas_assert (i.reg_operands == 2 || i.mask); |
5382 | if (i.reg_operands == 2 && !i.mask) | |
5383 | { | |
3528c362 | 5384 | gas_assert (i.types[0].bitfield.class == RegSIMD); |
1b54b8d7 JB |
5385 | gas_assert (i.types[0].bitfield.xmmword |
5386 | || i.types[0].bitfield.ymmword); | |
3528c362 | 5387 | gas_assert (i.types[2].bitfield.class == RegSIMD); |
1b54b8d7 JB |
5388 | gas_assert (i.types[2].bitfield.xmmword |
5389 | || i.types[2].bitfield.ymmword); | |
43234a1e L |
5390 | if (operand_check == check_none) |
5391 | return 0; | |
5392 | if (register_number (i.op[0].regs) | |
5393 | != register_number (i.index_reg) | |
5394 | && register_number (i.op[2].regs) | |
5395 | != register_number (i.index_reg) | |
5396 | && register_number (i.op[0].regs) | |
5397 | != register_number (i.op[2].regs)) | |
5398 | return 0; | |
5399 | if (operand_check == check_error) | |
5400 | { | |
5401 | i.error = invalid_vector_register_set; | |
5402 | return 1; | |
5403 | } | |
5404 | as_warn (_("mask, index, and destination registers should be distinct")); | |
5405 | } | |
8444f82a MZ |
5406 | else if (i.reg_operands == 1 && i.mask) |
5407 | { | |
3528c362 | 5408 | if (i.types[1].bitfield.class == RegSIMD |
1b54b8d7 JB |
5409 | && (i.types[1].bitfield.xmmword |
5410 | || i.types[1].bitfield.ymmword | |
5411 | || i.types[1].bitfield.zmmword) | |
8444f82a MZ |
5412 | && (register_number (i.op[1].regs) |
5413 | == register_number (i.index_reg))) | |
5414 | { | |
5415 | if (operand_check == check_error) | |
5416 | { | |
5417 | i.error = invalid_vector_register_set; | |
5418 | return 1; | |
5419 | } | |
5420 | if (operand_check != check_none) | |
5421 | as_warn (_("index and destination registers should be distinct")); | |
5422 | } | |
5423 | } | |
43234a1e | 5424 | } |
7bab8ab5 | 5425 | |
43234a1e L |
5426 | /* Check if broadcast is supported by the instruction and is applied |
5427 | to the memory operand. */ | |
5428 | if (i.broadcast) | |
5429 | { | |
8e6e0792 | 5430 | i386_operand_type type, overlap; |
43234a1e L |
5431 | |
5432 | /* Check if specified broadcast is supported in this instruction, | |
4a1b91ea | 5433 | and its broadcast bytes match the memory operand. */ |
32546502 | 5434 | op = i.broadcast->operand; |
8e6e0792 | 5435 | if (!t->opcode_modifier.broadcast |
c48dadc9 | 5436 | || !(i.flags[op] & Operand_Mem) |
c39e5b26 | 5437 | || (!i.types[op].bitfield.unspecified |
4a1b91ea | 5438 | && !match_broadcast_size (t, op))) |
43234a1e L |
5439 | { |
5440 | bad_broadcast: | |
5441 | i.error = unsupported_broadcast; | |
5442 | return 1; | |
5443 | } | |
8e6e0792 | 5444 | |
4a1b91ea L |
5445 | i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1)) |
5446 | * i.broadcast->type); | |
8e6e0792 | 5447 | operand_type_set (&type, 0); |
4a1b91ea | 5448 | switch (i.broadcast->bytes) |
8e6e0792 | 5449 | { |
4a1b91ea L |
5450 | case 2: |
5451 | type.bitfield.word = 1; | |
5452 | break; | |
5453 | case 4: | |
5454 | type.bitfield.dword = 1; | |
5455 | break; | |
8e6e0792 JB |
5456 | case 8: |
5457 | type.bitfield.qword = 1; | |
5458 | break; | |
5459 | case 16: | |
5460 | type.bitfield.xmmword = 1; | |
5461 | break; | |
5462 | case 32: | |
5463 | type.bitfield.ymmword = 1; | |
5464 | break; | |
5465 | case 64: | |
5466 | type.bitfield.zmmword = 1; | |
5467 | break; | |
5468 | default: | |
5469 | goto bad_broadcast; | |
5470 | } | |
5471 | ||
5472 | overlap = operand_type_and (type, t->operand_types[op]); | |
5473 | if (operand_type_all_zero (&overlap)) | |
5474 | goto bad_broadcast; | |
5475 | ||
5476 | if (t->opcode_modifier.checkregsize) | |
5477 | { | |
5478 | unsigned int j; | |
5479 | ||
e2195274 | 5480 | type.bitfield.baseindex = 1; |
8e6e0792 JB |
5481 | for (j = 0; j < i.operands; ++j) |
5482 | { | |
5483 | if (j != op | |
5484 | && !operand_type_register_match(i.types[j], | |
5485 | t->operand_types[j], | |
5486 | type, | |
5487 | t->operand_types[op])) | |
5488 | goto bad_broadcast; | |
5489 | } | |
5490 | } | |
43234a1e L |
5491 | } |
5492 | /* If broadcast is supported in this instruction, we need to check if | |
5493 | operand of one-element size isn't specified without broadcast. */ | |
5494 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
5495 | { | |
5496 | /* Find memory operand. */ | |
5497 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 5498 | if (i.flags[op] & Operand_Mem) |
43234a1e L |
5499 | break; |
5500 | gas_assert (op < i.operands); | |
5501 | /* Check size of the memory operand. */ | |
4a1b91ea | 5502 | if (match_broadcast_size (t, op)) |
43234a1e L |
5503 | { |
5504 | i.error = broadcast_needed; | |
5505 | return 1; | |
5506 | } | |
5507 | } | |
c39e5b26 JB |
5508 | else |
5509 | op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */ | |
43234a1e L |
5510 | |
5511 | /* Check if requested masking is supported. */ | |
ae2387fe | 5512 | if (i.mask) |
43234a1e | 5513 | { |
ae2387fe JB |
5514 | switch (t->opcode_modifier.masking) |
5515 | { | |
5516 | case BOTH_MASKING: | |
5517 | break; | |
5518 | case MERGING_MASKING: | |
5519 | if (i.mask->zeroing) | |
5520 | { | |
5521 | case 0: | |
5522 | i.error = unsupported_masking; | |
5523 | return 1; | |
5524 | } | |
5525 | break; | |
5526 | case DYNAMIC_MASKING: | |
5527 | /* Memory destinations allow only merging masking. */ | |
5528 | if (i.mask->zeroing && i.mem_operands) | |
5529 | { | |
5530 | /* Find memory operand. */ | |
5531 | for (op = 0; op < i.operands; op++) | |
c48dadc9 | 5532 | if (i.flags[op] & Operand_Mem) |
ae2387fe JB |
5533 | break; |
5534 | gas_assert (op < i.operands); | |
5535 | if (op == i.operands - 1) | |
5536 | { | |
5537 | i.error = unsupported_masking; | |
5538 | return 1; | |
5539 | } | |
5540 | } | |
5541 | break; | |
5542 | default: | |
5543 | abort (); | |
5544 | } | |
43234a1e L |
5545 | } |
5546 | ||
5547 | /* Check if masking is applied to dest operand. */ | |
5548 | if (i.mask && (i.mask->operand != (int) (i.operands - 1))) | |
5549 | { | |
5550 | i.error = mask_not_on_destination; | |
5551 | return 1; | |
5552 | } | |
5553 | ||
43234a1e L |
5554 | /* Check RC/SAE. */ |
5555 | if (i.rounding) | |
5556 | { | |
a80195f1 JB |
5557 | if (!t->opcode_modifier.sae |
5558 | || (i.rounding->type != saeonly && !t->opcode_modifier.staticrounding)) | |
43234a1e L |
5559 | { |
5560 | i.error = unsupported_rc_sae; | |
5561 | return 1; | |
5562 | } | |
5563 | /* If the instruction has several immediate operands and one of | |
5564 | them is rounding, the rounding operand should be the last | |
5565 | immediate operand. */ | |
5566 | if (i.imm_operands > 1 | |
5567 | && i.rounding->operand != (int) (i.imm_operands - 1)) | |
7bab8ab5 | 5568 | { |
43234a1e | 5569 | i.error = rc_sae_operand_not_last_imm; |
7bab8ab5 JB |
5570 | return 1; |
5571 | } | |
6c30d220 L |
5572 | } |
5573 | ||
43234a1e | 5574 | /* Check vector Disp8 operand. */ |
b5014f7a JB |
5575 | if (t->opcode_modifier.disp8memshift |
5576 | && i.disp_encoding != disp_encoding_32bit) | |
43234a1e L |
5577 | { |
5578 | if (i.broadcast) | |
4a1b91ea | 5579 | i.memshift = t->opcode_modifier.broadcast - 1; |
7091c612 | 5580 | else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL) |
43234a1e | 5581 | i.memshift = t->opcode_modifier.disp8memshift; |
7091c612 JB |
5582 | else |
5583 | { | |
5584 | const i386_operand_type *type = NULL; | |
5585 | ||
5586 | i.memshift = 0; | |
5587 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 5588 | if (i.flags[op] & Operand_Mem) |
7091c612 | 5589 | { |
4174bfff JB |
5590 | if (t->opcode_modifier.evex == EVEXLIG) |
5591 | i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX); | |
5592 | else if (t->operand_types[op].bitfield.xmmword | |
5593 | + t->operand_types[op].bitfield.ymmword | |
5594 | + t->operand_types[op].bitfield.zmmword <= 1) | |
7091c612 JB |
5595 | type = &t->operand_types[op]; |
5596 | else if (!i.types[op].bitfield.unspecified) | |
5597 | type = &i.types[op]; | |
5598 | } | |
3528c362 | 5599 | else if (i.types[op].bitfield.class == RegSIMD |
4174bfff | 5600 | && t->opcode_modifier.evex != EVEXLIG) |
7091c612 JB |
5601 | { |
5602 | if (i.types[op].bitfield.zmmword) | |
5603 | i.memshift = 6; | |
5604 | else if (i.types[op].bitfield.ymmword && i.memshift < 5) | |
5605 | i.memshift = 5; | |
5606 | else if (i.types[op].bitfield.xmmword && i.memshift < 4) | |
5607 | i.memshift = 4; | |
5608 | } | |
5609 | ||
5610 | if (type) | |
5611 | { | |
5612 | if (type->bitfield.zmmword) | |
5613 | i.memshift = 6; | |
5614 | else if (type->bitfield.ymmword) | |
5615 | i.memshift = 5; | |
5616 | else if (type->bitfield.xmmword) | |
5617 | i.memshift = 4; | |
5618 | } | |
5619 | ||
5620 | /* For the check in fits_in_disp8(). */ | |
5621 | if (i.memshift == 0) | |
5622 | i.memshift = -1; | |
5623 | } | |
43234a1e L |
5624 | |
5625 | for (op = 0; op < i.operands; op++) | |
5626 | if (operand_type_check (i.types[op], disp) | |
5627 | && i.op[op].disps->X_op == O_constant) | |
5628 | { | |
b5014f7a | 5629 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
43234a1e | 5630 | { |
b5014f7a JB |
5631 | i.types[op].bitfield.disp8 = 1; |
5632 | return 0; | |
43234a1e | 5633 | } |
b5014f7a | 5634 | i.types[op].bitfield.disp8 = 0; |
43234a1e L |
5635 | } |
5636 | } | |
b5014f7a JB |
5637 | |
5638 | i.memshift = 0; | |
43234a1e | 5639 | |
6c30d220 L |
5640 | return 0; |
5641 | } | |
5642 | ||
43f3e2ee | 5643 | /* Check if operands are valid for the instruction. Update VEX |
a683cc34 SP |
5644 | operand types. */ |
5645 | ||
5646 | static int | |
5647 | VEX_check_operands (const insn_template *t) | |
5648 | { | |
86fa6981 | 5649 | if (i.vec_encoding == vex_encoding_evex) |
43234a1e | 5650 | { |
86fa6981 | 5651 | /* This instruction must be encoded with EVEX prefix. */ |
e771e7c9 | 5652 | if (!is_evex_encoding (t)) |
86fa6981 L |
5653 | { |
5654 | i.error = unsupported; | |
5655 | return 1; | |
5656 | } | |
5657 | return 0; | |
43234a1e L |
5658 | } |
5659 | ||
a683cc34 | 5660 | if (!t->opcode_modifier.vex) |
86fa6981 L |
5661 | { |
5662 | /* This instruction template doesn't have VEX prefix. */ | |
5663 | if (i.vec_encoding != vex_encoding_default) | |
5664 | { | |
5665 | i.error = unsupported; | |
5666 | return 1; | |
5667 | } | |
5668 | return 0; | |
5669 | } | |
a683cc34 | 5670 | |
9d3bf266 JB |
5671 | /* Check the special Imm4 cases; must be the first operand. */ |
5672 | if (t->cpu_flags.bitfield.cpuxop && t->operands == 5) | |
a683cc34 SP |
5673 | { |
5674 | if (i.op[0].imms->X_op != O_constant | |
5675 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
891edac4 | 5676 | { |
a65babc9 | 5677 | i.error = bad_imm4; |
891edac4 L |
5678 | return 1; |
5679 | } | |
a683cc34 | 5680 | |
9d3bf266 JB |
5681 | /* Turn off Imm<N> so that update_imm won't complain. */ |
5682 | operand_type_set (&i.types[0], 0); | |
a683cc34 SP |
5683 | } |
5684 | ||
5685 | return 0; | |
5686 | } | |
5687 | ||
d3ce72d0 | 5688 | static const insn_template * |
83b16ac6 | 5689 | match_template (char mnem_suffix) |
29b0f896 AM |
5690 | { |
5691 | /* Points to template once we've found it. */ | |
d3ce72d0 | 5692 | const insn_template *t; |
40fb9820 | 5693 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 5694 | i386_operand_type overlap4; |
29b0f896 | 5695 | unsigned int found_reverse_match; |
83b16ac6 | 5696 | i386_opcode_modifier suffix_check, mnemsuf_check; |
40fb9820 | 5697 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 5698 | int addr_prefix_disp; |
a5c311ca | 5699 | unsigned int j; |
3ac21baa | 5700 | unsigned int found_cpu_match, size_match; |
45664ddb | 5701 | unsigned int check_register; |
5614d22c | 5702 | enum i386_error specific_error = 0; |
29b0f896 | 5703 | |
c0f3af97 L |
5704 | #if MAX_OPERANDS != 5 |
5705 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
5706 | #endif |
5707 | ||
29b0f896 | 5708 | found_reverse_match = 0; |
539e75ad | 5709 | addr_prefix_disp = -1; |
40fb9820 L |
5710 | |
5711 | memset (&suffix_check, 0, sizeof (suffix_check)); | |
e2195274 JB |
5712 | if (intel_syntax && i.broadcast) |
5713 | /* nothing */; | |
5714 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
40fb9820 L |
5715 | suffix_check.no_bsuf = 1; |
5716 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
5717 | suffix_check.no_wsuf = 1; | |
5718 | else if (i.suffix == SHORT_MNEM_SUFFIX) | |
5719 | suffix_check.no_ssuf = 1; | |
5720 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
5721 | suffix_check.no_lsuf = 1; | |
5722 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
5723 | suffix_check.no_qsuf = 1; | |
5724 | else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
7ce189b3 | 5725 | suffix_check.no_ldsuf = 1; |
29b0f896 | 5726 | |
83b16ac6 JB |
5727 | memset (&mnemsuf_check, 0, sizeof (mnemsuf_check)); |
5728 | if (intel_syntax) | |
5729 | { | |
5730 | switch (mnem_suffix) | |
5731 | { | |
5732 | case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break; | |
5733 | case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break; | |
5734 | case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break; | |
5735 | case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break; | |
5736 | case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break; | |
5737 | } | |
5738 | } | |
5739 | ||
01559ecc L |
5740 | /* Must have right number of operands. */ |
5741 | i.error = number_of_operands_mismatch; | |
5742 | ||
45aa61fe | 5743 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 5744 | { |
539e75ad | 5745 | addr_prefix_disp = -1; |
dbbc8b7e | 5746 | found_reverse_match = 0; |
539e75ad | 5747 | |
29b0f896 AM |
5748 | if (i.operands != t->operands) |
5749 | continue; | |
5750 | ||
50aecf8c | 5751 | /* Check processor support. */ |
a65babc9 | 5752 | i.error = unsupported; |
c0f3af97 L |
5753 | found_cpu_match = (cpu_flags_match (t) |
5754 | == CPU_FLAGS_PERFECT_MATCH); | |
50aecf8c L |
5755 | if (!found_cpu_match) |
5756 | continue; | |
5757 | ||
e1d4d893 | 5758 | /* Check AT&T mnemonic. */ |
a65babc9 | 5759 | i.error = unsupported_with_intel_mnemonic; |
e1d4d893 | 5760 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
5761 | continue; |
5762 | ||
e92bae62 | 5763 | /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */ |
a65babc9 | 5764 | i.error = unsupported_syntax; |
5c07affc | 5765 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
e92bae62 L |
5766 | || (!intel_syntax && t->opcode_modifier.intelsyntax) |
5767 | || (intel64 && t->opcode_modifier.amd64) | |
5768 | || (!intel64 && t->opcode_modifier.intel64)) | |
1efbbeb4 L |
5769 | continue; |
5770 | ||
20592a94 | 5771 | /* Check the suffix, except for some instructions in intel mode. */ |
a65babc9 | 5772 | i.error = invalid_instruction_suffix; |
567e4e96 L |
5773 | if ((!intel_syntax || !t->opcode_modifier.ignoresize) |
5774 | && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) | |
5775 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
5776 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
5777 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
5778 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
5779 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) | |
29b0f896 | 5780 | continue; |
83b16ac6 JB |
5781 | /* In Intel mode all mnemonic suffixes must be explicitly allowed. */ |
5782 | if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf) | |
5783 | || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf) | |
5784 | || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf) | |
5785 | || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf) | |
5786 | || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf) | |
5787 | || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf)) | |
5788 | continue; | |
29b0f896 | 5789 | |
3ac21baa JB |
5790 | size_match = operand_size_match (t); |
5791 | if (!size_match) | |
7d5e4556 | 5792 | continue; |
539e75ad | 5793 | |
5c07affc L |
5794 | for (j = 0; j < MAX_OPERANDS; j++) |
5795 | operand_types[j] = t->operand_types[j]; | |
5796 | ||
45aa61fe AM |
5797 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
5798 | if (i.suffix == QWORD_MNEM_SUFFIX | |
5799 | && flag_code != CODE_64BIT | |
5800 | && (intel_syntax | |
40fb9820 | 5801 | ? (!t->opcode_modifier.ignoresize |
625cbd7a | 5802 | && !t->opcode_modifier.broadcast |
45aa61fe AM |
5803 | && !intel_float_operand (t->name)) |
5804 | : intel_float_operand (t->name) != 2) | |
3528c362 JB |
5805 | && ((operand_types[0].bitfield.class != RegMMX |
5806 | && operand_types[0].bitfield.class != RegSIMD) | |
5807 | || (operand_types[t->operands > 1].bitfield.class != RegMMX | |
5808 | && operand_types[t->operands > 1].bitfield.class != RegSIMD)) | |
45aa61fe AM |
5809 | && (t->base_opcode != 0x0fc7 |
5810 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
5811 | continue; | |
5812 | ||
192dc9c6 JB |
5813 | /* In general, don't allow 32-bit operands on pre-386. */ |
5814 | else if (i.suffix == LONG_MNEM_SUFFIX | |
5815 | && !cpu_arch_flags.bitfield.cpui386 | |
5816 | && (intel_syntax | |
5817 | ? (!t->opcode_modifier.ignoresize | |
5818 | && !intel_float_operand (t->name)) | |
5819 | : intel_float_operand (t->name) != 2) | |
3528c362 JB |
5820 | && ((operand_types[0].bitfield.class != RegMMX |
5821 | && operand_types[0].bitfield.class != RegSIMD) | |
5822 | || (operand_types[t->operands > 1].bitfield.class != RegMMX | |
5823 | && operand_types[t->operands > 1].bitfield.class | |
5824 | != RegSIMD))) | |
192dc9c6 JB |
5825 | continue; |
5826 | ||
29b0f896 | 5827 | /* Do not verify operands when there are none. */ |
50aecf8c | 5828 | else |
29b0f896 | 5829 | { |
c6fb90c8 | 5830 | if (!t->operands) |
2dbab7d5 L |
5831 | /* We've found a match; break out of loop. */ |
5832 | break; | |
29b0f896 | 5833 | } |
252b5132 | 5834 | |
539e75ad L |
5835 | /* Address size prefix will turn Disp64/Disp32/Disp16 operand |
5836 | into Disp32/Disp16/Disp32 operand. */ | |
5837 | if (i.prefix[ADDR_PREFIX] != 0) | |
5838 | { | |
40fb9820 | 5839 | /* There should be only one Disp operand. */ |
539e75ad L |
5840 | switch (flag_code) |
5841 | { | |
5842 | case CODE_16BIT: | |
40fb9820 L |
5843 | for (j = 0; j < MAX_OPERANDS; j++) |
5844 | { | |
5845 | if (operand_types[j].bitfield.disp16) | |
5846 | { | |
5847 | addr_prefix_disp = j; | |
5848 | operand_types[j].bitfield.disp32 = 1; | |
5849 | operand_types[j].bitfield.disp16 = 0; | |
5850 | break; | |
5851 | } | |
5852 | } | |
539e75ad L |
5853 | break; |
5854 | case CODE_32BIT: | |
40fb9820 L |
5855 | for (j = 0; j < MAX_OPERANDS; j++) |
5856 | { | |
5857 | if (operand_types[j].bitfield.disp32) | |
5858 | { | |
5859 | addr_prefix_disp = j; | |
5860 | operand_types[j].bitfield.disp32 = 0; | |
5861 | operand_types[j].bitfield.disp16 = 1; | |
5862 | break; | |
5863 | } | |
5864 | } | |
539e75ad L |
5865 | break; |
5866 | case CODE_64BIT: | |
40fb9820 L |
5867 | for (j = 0; j < MAX_OPERANDS; j++) |
5868 | { | |
5869 | if (operand_types[j].bitfield.disp64) | |
5870 | { | |
5871 | addr_prefix_disp = j; | |
5872 | operand_types[j].bitfield.disp64 = 0; | |
5873 | operand_types[j].bitfield.disp32 = 1; | |
5874 | break; | |
5875 | } | |
5876 | } | |
539e75ad L |
5877 | break; |
5878 | } | |
539e75ad L |
5879 | } |
5880 | ||
02a86693 L |
5881 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ |
5882 | if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0) | |
5883 | continue; | |
5884 | ||
56ffb741 | 5885 | /* We check register size if needed. */ |
e2195274 JB |
5886 | if (t->opcode_modifier.checkregsize) |
5887 | { | |
5888 | check_register = (1 << t->operands) - 1; | |
5889 | if (i.broadcast) | |
5890 | check_register &= ~(1 << i.broadcast->operand); | |
5891 | } | |
5892 | else | |
5893 | check_register = 0; | |
5894 | ||
c6fb90c8 | 5895 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
5896 | switch (t->operands) |
5897 | { | |
5898 | case 1: | |
40fb9820 | 5899 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
5900 | continue; |
5901 | break; | |
5902 | case 2: | |
33eaf5de | 5903 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
5904 | only in 32bit mode and we can use opcode 0x90. In 64bit |
5905 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
5906 | zero-extend %eax to %rax. */ | |
5907 | if (flag_code == CODE_64BIT | |
5908 | && t->base_opcode == 0x90 | |
2c703856 JB |
5909 | && i.types[0].bitfield.acc && i.types[0].bitfield.dword |
5910 | && i.types[1].bitfield.acc && i.types[1].bitfield.dword) | |
8b38ad71 | 5911 | continue; |
1212781b JB |
5912 | /* xrelease mov %eax, <disp> is another special case. It must not |
5913 | match the accumulator-only encoding of mov. */ | |
5914 | if (flag_code != CODE_64BIT | |
5915 | && i.hle_prefix | |
5916 | && t->base_opcode == 0xa0 | |
5917 | && i.types[0].bitfield.acc | |
8dc0818e | 5918 | && (i.flags[1] & Operand_Mem)) |
1212781b | 5919 | continue; |
f5eb1d70 JB |
5920 | /* Fall through. */ |
5921 | ||
5922 | case 3: | |
3ac21baa JB |
5923 | if (!(size_match & MATCH_STRAIGHT)) |
5924 | goto check_reverse; | |
64c49ab3 JB |
5925 | /* Reverse direction of operands if swapping is possible in the first |
5926 | place (operands need to be symmetric) and | |
5927 | - the load form is requested, and the template is a store form, | |
5928 | - the store form is requested, and the template is a load form, | |
5929 | - the non-default (swapped) form is requested. */ | |
5930 | overlap1 = operand_type_and (operand_types[0], operand_types[1]); | |
f5eb1d70 | 5931 | if (t->opcode_modifier.d && i.reg_operands == i.operands |
64c49ab3 JB |
5932 | && !operand_type_all_zero (&overlap1)) |
5933 | switch (i.dir_encoding) | |
5934 | { | |
5935 | case dir_encoding_load: | |
5936 | if (operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 5937 | || t->opcode_modifier.regmem) |
64c49ab3 JB |
5938 | goto check_reverse; |
5939 | break; | |
5940 | ||
5941 | case dir_encoding_store: | |
5942 | if (!operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 5943 | && !t->opcode_modifier.regmem) |
64c49ab3 JB |
5944 | goto check_reverse; |
5945 | break; | |
5946 | ||
5947 | case dir_encoding_swap: | |
5948 | goto check_reverse; | |
5949 | ||
5950 | case dir_encoding_default: | |
5951 | break; | |
5952 | } | |
86fa6981 | 5953 | /* If we want store form, we skip the current load. */ |
64c49ab3 JB |
5954 | if ((i.dir_encoding == dir_encoding_store |
5955 | || i.dir_encoding == dir_encoding_swap) | |
86fa6981 L |
5956 | && i.mem_operands == 0 |
5957 | && t->opcode_modifier.load) | |
fa99fab2 | 5958 | continue; |
1a0670f3 | 5959 | /* Fall through. */ |
f48ff2ae | 5960 | case 4: |
c0f3af97 | 5961 | case 5: |
c6fb90c8 | 5962 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
5963 | if (!operand_type_match (overlap0, i.types[0]) |
5964 | || !operand_type_match (overlap1, i.types[1]) | |
e2195274 | 5965 | || ((check_register & 3) == 3 |
dc821c5f | 5966 | && !operand_type_register_match (i.types[0], |
40fb9820 | 5967 | operand_types[0], |
dc821c5f | 5968 | i.types[1], |
40fb9820 | 5969 | operand_types[1]))) |
29b0f896 AM |
5970 | { |
5971 | /* Check if other direction is valid ... */ | |
38e314eb | 5972 | if (!t->opcode_modifier.d) |
29b0f896 AM |
5973 | continue; |
5974 | ||
b6169b20 | 5975 | check_reverse: |
3ac21baa JB |
5976 | if (!(size_match & MATCH_REVERSE)) |
5977 | continue; | |
29b0f896 | 5978 | /* Try reversing direction of operands. */ |
f5eb1d70 JB |
5979 | overlap0 = operand_type_and (i.types[0], operand_types[i.operands - 1]); |
5980 | overlap1 = operand_type_and (i.types[i.operands - 1], operand_types[0]); | |
40fb9820 | 5981 | if (!operand_type_match (overlap0, i.types[0]) |
f5eb1d70 | 5982 | || !operand_type_match (overlap1, i.types[i.operands - 1]) |
45664ddb | 5983 | || (check_register |
dc821c5f | 5984 | && !operand_type_register_match (i.types[0], |
f5eb1d70 JB |
5985 | operand_types[i.operands - 1], |
5986 | i.types[i.operands - 1], | |
45664ddb | 5987 | operand_types[0]))) |
29b0f896 AM |
5988 | { |
5989 | /* Does not match either direction. */ | |
5990 | continue; | |
5991 | } | |
38e314eb | 5992 | /* found_reverse_match holds which of D or FloatR |
29b0f896 | 5993 | we've found. */ |
38e314eb JB |
5994 | if (!t->opcode_modifier.d) |
5995 | found_reverse_match = 0; | |
5996 | else if (operand_types[0].bitfield.tbyte) | |
8a2ed489 | 5997 | found_reverse_match = Opcode_FloatD; |
dbbc8b7e | 5998 | else if (operand_types[0].bitfield.xmmword |
f5eb1d70 | 5999 | || operand_types[i.operands - 1].bitfield.xmmword |
3528c362 JB |
6000 | || operand_types[0].bitfield.class == RegMMX |
6001 | || operand_types[i.operands - 1].bitfield.class == RegMMX | |
dbbc8b7e JB |
6002 | || is_any_vex_encoding(t)) |
6003 | found_reverse_match = (t->base_opcode & 0xee) != 0x6e | |
6004 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
8a2ed489 | 6005 | else |
38e314eb | 6006 | found_reverse_match = Opcode_D; |
40fb9820 | 6007 | if (t->opcode_modifier.floatr) |
8a2ed489 | 6008 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 6009 | } |
f48ff2ae | 6010 | else |
29b0f896 | 6011 | { |
f48ff2ae | 6012 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
6013 | switch (t->operands) |
6014 | { | |
c0f3af97 L |
6015 | case 5: |
6016 | overlap4 = operand_type_and (i.types[4], | |
6017 | operand_types[4]); | |
1a0670f3 | 6018 | /* Fall through. */ |
d1cbb4db | 6019 | case 4: |
c6fb90c8 L |
6020 | overlap3 = operand_type_and (i.types[3], |
6021 | operand_types[3]); | |
1a0670f3 | 6022 | /* Fall through. */ |
d1cbb4db | 6023 | case 3: |
c6fb90c8 L |
6024 | overlap2 = operand_type_and (i.types[2], |
6025 | operand_types[2]); | |
d1cbb4db L |
6026 | break; |
6027 | } | |
29b0f896 | 6028 | |
f48ff2ae L |
6029 | switch (t->operands) |
6030 | { | |
c0f3af97 L |
6031 | case 5: |
6032 | if (!operand_type_match (overlap4, i.types[4]) | |
dc821c5f | 6033 | || !operand_type_register_match (i.types[3], |
c0f3af97 | 6034 | operand_types[3], |
c0f3af97 L |
6035 | i.types[4], |
6036 | operand_types[4])) | |
6037 | continue; | |
1a0670f3 | 6038 | /* Fall through. */ |
f48ff2ae | 6039 | case 4: |
40fb9820 | 6040 | if (!operand_type_match (overlap3, i.types[3]) |
e2195274 JB |
6041 | || ((check_register & 0xa) == 0xa |
6042 | && !operand_type_register_match (i.types[1], | |
f7768225 JB |
6043 | operand_types[1], |
6044 | i.types[3], | |
e2195274 JB |
6045 | operand_types[3])) |
6046 | || ((check_register & 0xc) == 0xc | |
6047 | && !operand_type_register_match (i.types[2], | |
6048 | operand_types[2], | |
6049 | i.types[3], | |
6050 | operand_types[3]))) | |
f48ff2ae | 6051 | continue; |
1a0670f3 | 6052 | /* Fall through. */ |
f48ff2ae L |
6053 | case 3: |
6054 | /* Here we make use of the fact that there are no | |
23e42951 | 6055 | reverse match 3 operand instructions. */ |
40fb9820 | 6056 | if (!operand_type_match (overlap2, i.types[2]) |
e2195274 JB |
6057 | || ((check_register & 5) == 5 |
6058 | && !operand_type_register_match (i.types[0], | |
23e42951 JB |
6059 | operand_types[0], |
6060 | i.types[2], | |
e2195274 JB |
6061 | operand_types[2])) |
6062 | || ((check_register & 6) == 6 | |
6063 | && !operand_type_register_match (i.types[1], | |
6064 | operand_types[1], | |
6065 | i.types[2], | |
6066 | operand_types[2]))) | |
f48ff2ae L |
6067 | continue; |
6068 | break; | |
6069 | } | |
29b0f896 | 6070 | } |
f48ff2ae | 6071 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
6072 | slip through to break. */ |
6073 | } | |
3629bb00 | 6074 | if (!found_cpu_match) |
dbbc8b7e | 6075 | continue; |
c0f3af97 | 6076 | |
5614d22c JB |
6077 | /* Check if vector and VEX operands are valid. */ |
6078 | if (check_VecOperands (t) || VEX_check_operands (t)) | |
6079 | { | |
6080 | specific_error = i.error; | |
6081 | continue; | |
6082 | } | |
a683cc34 | 6083 | |
29b0f896 AM |
6084 | /* We've found a match; break out of loop. */ |
6085 | break; | |
6086 | } | |
6087 | ||
6088 | if (t == current_templates->end) | |
6089 | { | |
6090 | /* We found no match. */ | |
a65babc9 | 6091 | const char *err_msg; |
5614d22c | 6092 | switch (specific_error ? specific_error : i.error) |
a65babc9 L |
6093 | { |
6094 | default: | |
6095 | abort (); | |
86e026a4 | 6096 | case operand_size_mismatch: |
a65babc9 L |
6097 | err_msg = _("operand size mismatch"); |
6098 | break; | |
6099 | case operand_type_mismatch: | |
6100 | err_msg = _("operand type mismatch"); | |
6101 | break; | |
6102 | case register_type_mismatch: | |
6103 | err_msg = _("register type mismatch"); | |
6104 | break; | |
6105 | case number_of_operands_mismatch: | |
6106 | err_msg = _("number of operands mismatch"); | |
6107 | break; | |
6108 | case invalid_instruction_suffix: | |
6109 | err_msg = _("invalid instruction suffix"); | |
6110 | break; | |
6111 | case bad_imm4: | |
4a2608e3 | 6112 | err_msg = _("constant doesn't fit in 4 bits"); |
a65babc9 | 6113 | break; |
a65babc9 L |
6114 | case unsupported_with_intel_mnemonic: |
6115 | err_msg = _("unsupported with Intel mnemonic"); | |
6116 | break; | |
6117 | case unsupported_syntax: | |
6118 | err_msg = _("unsupported syntax"); | |
6119 | break; | |
6120 | case unsupported: | |
35262a23 | 6121 | as_bad (_("unsupported instruction `%s'"), |
10efe3f6 L |
6122 | current_templates->start->name); |
6123 | return NULL; | |
6c30d220 L |
6124 | case invalid_vsib_address: |
6125 | err_msg = _("invalid VSIB address"); | |
6126 | break; | |
7bab8ab5 JB |
6127 | case invalid_vector_register_set: |
6128 | err_msg = _("mask, index, and destination registers must be distinct"); | |
6129 | break; | |
6c30d220 L |
6130 | case unsupported_vector_index_register: |
6131 | err_msg = _("unsupported vector index register"); | |
6132 | break; | |
43234a1e L |
6133 | case unsupported_broadcast: |
6134 | err_msg = _("unsupported broadcast"); | |
6135 | break; | |
43234a1e L |
6136 | case broadcast_needed: |
6137 | err_msg = _("broadcast is needed for operand of such type"); | |
6138 | break; | |
6139 | case unsupported_masking: | |
6140 | err_msg = _("unsupported masking"); | |
6141 | break; | |
6142 | case mask_not_on_destination: | |
6143 | err_msg = _("mask not on destination operand"); | |
6144 | break; | |
6145 | case no_default_mask: | |
6146 | err_msg = _("default mask isn't allowed"); | |
6147 | break; | |
6148 | case unsupported_rc_sae: | |
6149 | err_msg = _("unsupported static rounding/sae"); | |
6150 | break; | |
6151 | case rc_sae_operand_not_last_imm: | |
6152 | if (intel_syntax) | |
6153 | err_msg = _("RC/SAE operand must precede immediate operands"); | |
6154 | else | |
6155 | err_msg = _("RC/SAE operand must follow immediate operands"); | |
6156 | break; | |
6157 | case invalid_register_operand: | |
6158 | err_msg = _("invalid register operand"); | |
6159 | break; | |
a65babc9 L |
6160 | } |
6161 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 6162 | current_templates->start->name); |
fa99fab2 | 6163 | return NULL; |
29b0f896 | 6164 | } |
252b5132 | 6165 | |
29b0f896 AM |
6166 | if (!quiet_warnings) |
6167 | { | |
6168 | if (!intel_syntax | |
40fb9820 L |
6169 | && (i.types[0].bitfield.jumpabsolute |
6170 | != operand_types[0].bitfield.jumpabsolute)) | |
29b0f896 AM |
6171 | { |
6172 | as_warn (_("indirect %s without `*'"), t->name); | |
6173 | } | |
6174 | ||
40fb9820 L |
6175 | if (t->opcode_modifier.isprefix |
6176 | && t->opcode_modifier.ignoresize) | |
29b0f896 AM |
6177 | { |
6178 | /* Warn them that a data or address size prefix doesn't | |
6179 | affect assembly of the next line of code. */ | |
6180 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
6181 | } | |
6182 | } | |
6183 | ||
6184 | /* Copy the template we found. */ | |
6185 | i.tm = *t; | |
539e75ad L |
6186 | |
6187 | if (addr_prefix_disp != -1) | |
6188 | i.tm.operand_types[addr_prefix_disp] | |
6189 | = operand_types[addr_prefix_disp]; | |
6190 | ||
29b0f896 AM |
6191 | if (found_reverse_match) |
6192 | { | |
dfd69174 JB |
6193 | /* If we found a reverse match we must alter the opcode direction |
6194 | bit and clear/flip the regmem modifier one. found_reverse_match | |
6195 | holds bits to change (different for int & float insns). */ | |
29b0f896 AM |
6196 | |
6197 | i.tm.base_opcode ^= found_reverse_match; | |
6198 | ||
f5eb1d70 JB |
6199 | i.tm.operand_types[0] = operand_types[i.operands - 1]; |
6200 | i.tm.operand_types[i.operands - 1] = operand_types[0]; | |
dfd69174 JB |
6201 | |
6202 | /* Certain SIMD insns have their load forms specified in the opcode | |
6203 | table, and hence we need to _set_ RegMem instead of clearing it. | |
6204 | We need to avoid setting the bit though on insns like KMOVW. */ | |
6205 | i.tm.opcode_modifier.regmem | |
6206 | = i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d | |
6207 | && i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx | |
6208 | && !i.tm.opcode_modifier.regmem; | |
29b0f896 AM |
6209 | } |
6210 | ||
fa99fab2 | 6211 | return t; |
29b0f896 AM |
6212 | } |
6213 | ||
6214 | static int | |
e3bb37b5 | 6215 | check_string (void) |
29b0f896 | 6216 | { |
8dc0818e JB |
6217 | unsigned int mem_op = i.flags[0] & Operand_Mem ? 0 : 1; |
6218 | ||
40fb9820 | 6219 | if (i.tm.operand_types[mem_op].bitfield.esseg) |
29b0f896 AM |
6220 | { |
6221 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
6222 | { | |
a87af027 | 6223 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 6224 | i.tm.name, |
d241b910 | 6225 | intel_syntax ? i.tm.operands - mem_op : mem_op + 1, |
a87af027 | 6226 | register_prefix); |
29b0f896 AM |
6227 | return 0; |
6228 | } | |
6229 | /* There's only ever one segment override allowed per instruction. | |
6230 | This instruction possibly has a legal segment override on the | |
6231 | second operand, so copy the segment to where non-string | |
6232 | instructions store it, allowing common code. */ | |
6233 | i.seg[0] = i.seg[1]; | |
6234 | } | |
40fb9820 | 6235 | else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) |
29b0f896 AM |
6236 | { |
6237 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
6238 | { | |
a87af027 | 6239 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 6240 | i.tm.name, |
d241b910 | 6241 | intel_syntax ? i.tm.operands - mem_op - 1 : mem_op + 2, |
a87af027 | 6242 | register_prefix); |
29b0f896 AM |
6243 | return 0; |
6244 | } | |
6245 | } | |
6246 | return 1; | |
6247 | } | |
6248 | ||
6249 | static int | |
543613e9 | 6250 | process_suffix (void) |
29b0f896 AM |
6251 | { |
6252 | /* If matched instruction specifies an explicit instruction mnemonic | |
6253 | suffix, use it. */ | |
673fe0f0 | 6254 | if (i.tm.opcode_modifier.size == SIZE16) |
40fb9820 | 6255 | i.suffix = WORD_MNEM_SUFFIX; |
673fe0f0 | 6256 | else if (i.tm.opcode_modifier.size == SIZE32) |
40fb9820 | 6257 | i.suffix = LONG_MNEM_SUFFIX; |
673fe0f0 | 6258 | else if (i.tm.opcode_modifier.size == SIZE64) |
40fb9820 | 6259 | i.suffix = QWORD_MNEM_SUFFIX; |
29b0f896 AM |
6260 | else if (i.reg_operands) |
6261 | { | |
6262 | /* If there's no instruction mnemonic suffix we try to invent one | |
6263 | based on register operands. */ | |
6264 | if (!i.suffix) | |
6265 | { | |
6266 | /* We take i.suffix from the last register operand specified, | |
6267 | Destination register type is more significant than source | |
381d071f L |
6268 | register type. crc32 in SSE4.2 prefers source register |
6269 | type. */ | |
bab6aec1 JB |
6270 | if (i.tm.base_opcode == 0xf20f38f0 |
6271 | && i.types[0].bitfield.class == Reg) | |
381d071f | 6272 | { |
556059dd JB |
6273 | if (i.types[0].bitfield.byte) |
6274 | i.suffix = BYTE_MNEM_SUFFIX; | |
6275 | else if (i.types[0].bitfield.word) | |
40fb9820 | 6276 | i.suffix = WORD_MNEM_SUFFIX; |
556059dd | 6277 | else if (i.types[0].bitfield.dword) |
40fb9820 | 6278 | i.suffix = LONG_MNEM_SUFFIX; |
556059dd | 6279 | else if (i.types[0].bitfield.qword) |
40fb9820 | 6280 | i.suffix = QWORD_MNEM_SUFFIX; |
381d071f L |
6281 | } |
6282 | ||
6283 | if (!i.suffix) | |
6284 | { | |
6285 | int op; | |
6286 | ||
556059dd | 6287 | if (i.tm.base_opcode == 0xf20f38f0) |
20592a94 L |
6288 | { |
6289 | /* We have to know the operand size for crc32. */ | |
6290 | as_bad (_("ambiguous memory operand size for `%s`"), | |
6291 | i.tm.name); | |
6292 | return 0; | |
6293 | } | |
6294 | ||
381d071f | 6295 | for (op = i.operands; --op >= 0;) |
b76bc5d5 JB |
6296 | if (!i.tm.operand_types[op].bitfield.inoutportreg |
6297 | && !i.tm.operand_types[op].bitfield.shiftcount) | |
381d071f | 6298 | { |
bab6aec1 | 6299 | if (i.types[op].bitfield.class != Reg) |
8819ada6 JB |
6300 | continue; |
6301 | if (i.types[op].bitfield.byte) | |
6302 | i.suffix = BYTE_MNEM_SUFFIX; | |
6303 | else if (i.types[op].bitfield.word) | |
6304 | i.suffix = WORD_MNEM_SUFFIX; | |
6305 | else if (i.types[op].bitfield.dword) | |
6306 | i.suffix = LONG_MNEM_SUFFIX; | |
6307 | else if (i.types[op].bitfield.qword) | |
6308 | i.suffix = QWORD_MNEM_SUFFIX; | |
6309 | else | |
6310 | continue; | |
6311 | break; | |
381d071f L |
6312 | } |
6313 | } | |
29b0f896 AM |
6314 | } |
6315 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
6316 | { | |
2eb952a4 L |
6317 | if (intel_syntax |
6318 | && i.tm.opcode_modifier.ignoresize | |
6319 | && i.tm.opcode_modifier.no_bsuf) | |
6320 | i.suffix = 0; | |
6321 | else if (!check_byte_reg ()) | |
29b0f896 AM |
6322 | return 0; |
6323 | } | |
6324 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
6325 | { | |
2eb952a4 L |
6326 | if (intel_syntax |
6327 | && i.tm.opcode_modifier.ignoresize | |
9f123b91 JB |
6328 | && i.tm.opcode_modifier.no_lsuf |
6329 | && !i.tm.opcode_modifier.todword | |
6330 | && !i.tm.opcode_modifier.toqword) | |
2eb952a4 L |
6331 | i.suffix = 0; |
6332 | else if (!check_long_reg ()) | |
29b0f896 AM |
6333 | return 0; |
6334 | } | |
6335 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6336 | { | |
955e1e6a L |
6337 | if (intel_syntax |
6338 | && i.tm.opcode_modifier.ignoresize | |
9f123b91 JB |
6339 | && i.tm.opcode_modifier.no_qsuf |
6340 | && !i.tm.opcode_modifier.todword | |
6341 | && !i.tm.opcode_modifier.toqword) | |
955e1e6a L |
6342 | i.suffix = 0; |
6343 | else if (!check_qword_reg ()) | |
29b0f896 AM |
6344 | return 0; |
6345 | } | |
6346 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6347 | { | |
2eb952a4 L |
6348 | if (intel_syntax |
6349 | && i.tm.opcode_modifier.ignoresize | |
6350 | && i.tm.opcode_modifier.no_wsuf) | |
6351 | i.suffix = 0; | |
6352 | else if (!check_word_reg ()) | |
29b0f896 AM |
6353 | return 0; |
6354 | } | |
40fb9820 | 6355 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
29b0f896 AM |
6356 | /* Do nothing if the instruction is going to ignore the prefix. */ |
6357 | ; | |
6358 | else | |
6359 | abort (); | |
6360 | } | |
40fb9820 | 6361 | else if (i.tm.opcode_modifier.defaultsize |
9306ca4a JB |
6362 | && !i.suffix |
6363 | /* exclude fldenv/frstor/fsave/fstenv */ | |
40fb9820 | 6364 | && i.tm.opcode_modifier.no_ssuf) |
29b0f896 | 6365 | { |
06f74c5c L |
6366 | if (stackop_size == LONG_MNEM_SUFFIX |
6367 | && i.tm.base_opcode == 0xcf) | |
6368 | { | |
6369 | /* stackop_size is set to LONG_MNEM_SUFFIX for the | |
6370 | .code16gcc directive to support 16-bit mode with | |
6371 | 32-bit address. For IRET without a suffix, generate | |
6372 | 16-bit IRET (opcode 0xcf) to return from an interrupt | |
6373 | handler. */ | |
6374 | i.suffix = WORD_MNEM_SUFFIX; | |
6375 | as_warn (_("generating 16-bit `iret' for .code16gcc directive")); | |
6376 | } | |
6377 | else | |
6378 | i.suffix = stackop_size; | |
29b0f896 | 6379 | } |
9306ca4a JB |
6380 | else if (intel_syntax |
6381 | && !i.suffix | |
40fb9820 L |
6382 | && (i.tm.operand_types[0].bitfield.jumpabsolute |
6383 | || i.tm.opcode_modifier.jumpbyte | |
6384 | || i.tm.opcode_modifier.jumpintersegment | |
64e74474 AM |
6385 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
6386 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
6387 | { |
6388 | switch (flag_code) | |
6389 | { | |
6390 | case CODE_64BIT: | |
40fb9820 | 6391 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
6392 | { |
6393 | i.suffix = QWORD_MNEM_SUFFIX; | |
6394 | break; | |
6395 | } | |
1a0670f3 | 6396 | /* Fall through. */ |
9306ca4a | 6397 | case CODE_32BIT: |
40fb9820 | 6398 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
6399 | i.suffix = LONG_MNEM_SUFFIX; |
6400 | break; | |
6401 | case CODE_16BIT: | |
40fb9820 | 6402 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
6403 | i.suffix = WORD_MNEM_SUFFIX; |
6404 | break; | |
6405 | } | |
6406 | } | |
252b5132 | 6407 | |
9306ca4a | 6408 | if (!i.suffix) |
29b0f896 | 6409 | { |
9306ca4a JB |
6410 | if (!intel_syntax) |
6411 | { | |
40fb9820 | 6412 | if (i.tm.opcode_modifier.w) |
9306ca4a | 6413 | { |
4eed87de AM |
6414 | as_bad (_("no instruction mnemonic suffix given and " |
6415 | "no register operands; can't size instruction")); | |
9306ca4a JB |
6416 | return 0; |
6417 | } | |
6418 | } | |
6419 | else | |
6420 | { | |
40fb9820 | 6421 | unsigned int suffixes; |
7ab9ffdd | 6422 | |
40fb9820 L |
6423 | suffixes = !i.tm.opcode_modifier.no_bsuf; |
6424 | if (!i.tm.opcode_modifier.no_wsuf) | |
6425 | suffixes |= 1 << 1; | |
6426 | if (!i.tm.opcode_modifier.no_lsuf) | |
6427 | suffixes |= 1 << 2; | |
fc4adea1 | 6428 | if (!i.tm.opcode_modifier.no_ldsuf) |
40fb9820 L |
6429 | suffixes |= 1 << 3; |
6430 | if (!i.tm.opcode_modifier.no_ssuf) | |
6431 | suffixes |= 1 << 4; | |
c2b9da16 | 6432 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) |
40fb9820 L |
6433 | suffixes |= 1 << 5; |
6434 | ||
6435 | /* There are more than suffix matches. */ | |
6436 | if (i.tm.opcode_modifier.w | |
9306ca4a | 6437 | || ((suffixes & (suffixes - 1)) |
40fb9820 L |
6438 | && !i.tm.opcode_modifier.defaultsize |
6439 | && !i.tm.opcode_modifier.ignoresize)) | |
9306ca4a JB |
6440 | { |
6441 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
6442 | return 0; | |
6443 | } | |
6444 | } | |
29b0f896 | 6445 | } |
252b5132 | 6446 | |
d2224064 JB |
6447 | /* Change the opcode based on the operand size given by i.suffix. */ |
6448 | switch (i.suffix) | |
29b0f896 | 6449 | { |
d2224064 JB |
6450 | /* Size floating point instruction. */ |
6451 | case LONG_MNEM_SUFFIX: | |
6452 | if (i.tm.opcode_modifier.floatmf) | |
6453 | { | |
6454 | i.tm.base_opcode ^= 4; | |
6455 | break; | |
6456 | } | |
6457 | /* fall through */ | |
6458 | case WORD_MNEM_SUFFIX: | |
6459 | case QWORD_MNEM_SUFFIX: | |
29b0f896 | 6460 | /* It's not a byte, select word/dword operation. */ |
40fb9820 | 6461 | if (i.tm.opcode_modifier.w) |
29b0f896 | 6462 | { |
40fb9820 | 6463 | if (i.tm.opcode_modifier.shortform) |
29b0f896 AM |
6464 | i.tm.base_opcode |= 8; |
6465 | else | |
6466 | i.tm.base_opcode |= 1; | |
6467 | } | |
d2224064 JB |
6468 | /* fall through */ |
6469 | case SHORT_MNEM_SUFFIX: | |
29b0f896 AM |
6470 | /* Now select between word & dword operations via the operand |
6471 | size prefix, except for instructions that will ignore this | |
6472 | prefix anyway. */ | |
75c0a438 | 6473 | if (i.reg_operands > 0 |
bab6aec1 | 6474 | && i.types[0].bitfield.class == Reg |
75c0a438 L |
6475 | && i.tm.opcode_modifier.addrprefixopreg |
6476 | && (i.tm.opcode_modifier.immext | |
6477 | || i.operands == 1)) | |
cb712a9e | 6478 | { |
ca61edf2 L |
6479 | /* The address size override prefix changes the size of the |
6480 | first operand. */ | |
40fb9820 | 6481 | if ((flag_code == CODE_32BIT |
75c0a438 | 6482 | && i.op[0].regs->reg_type.bitfield.word) |
40fb9820 | 6483 | || (flag_code != CODE_32BIT |
75c0a438 | 6484 | && i.op[0].regs->reg_type.bitfield.dword)) |
cb712a9e L |
6485 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
6486 | return 0; | |
6487 | } | |
6488 | else if (i.suffix != QWORD_MNEM_SUFFIX | |
40fb9820 L |
6489 | && !i.tm.opcode_modifier.ignoresize |
6490 | && !i.tm.opcode_modifier.floatmf | |
a38d7118 | 6491 | && !is_any_vex_encoding (&i.tm) |
cb712a9e L |
6492 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
6493 | || (flag_code == CODE_64BIT | |
40fb9820 | 6494 | && i.tm.opcode_modifier.jumpbyte))) |
24eab124 AM |
6495 | { |
6496 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 6497 | |
40fb9820 | 6498 | if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ |
29b0f896 | 6499 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 6500 | |
29b0f896 AM |
6501 | if (!add_prefix (prefix)) |
6502 | return 0; | |
24eab124 | 6503 | } |
252b5132 | 6504 | |
29b0f896 AM |
6505 | /* Set mode64 for an operand. */ |
6506 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 6507 | && flag_code == CODE_64BIT |
d2224064 | 6508 | && !i.tm.opcode_modifier.norex64 |
46e883c5 | 6509 | /* Special case for xchg %rax,%rax. It is NOP and doesn't |
d2224064 JB |
6510 | need rex64. */ |
6511 | && ! (i.operands == 2 | |
6512 | && i.tm.base_opcode == 0x90 | |
6513 | && i.tm.extension_opcode == None | |
2c703856 JB |
6514 | && i.types[0].bitfield.acc && i.types[0].bitfield.qword |
6515 | && i.types[1].bitfield.acc && i.types[1].bitfield.qword)) | |
d2224064 | 6516 | i.rex |= REX_W; |
3e73aa7c | 6517 | |
d2224064 | 6518 | break; |
29b0f896 | 6519 | } |
7ecd2f8b | 6520 | |
c0a30a9f L |
6521 | if (i.reg_operands != 0 |
6522 | && i.operands > 1 | |
6523 | && i.tm.opcode_modifier.addrprefixopreg | |
6524 | && !i.tm.opcode_modifier.immext) | |
6525 | { | |
6526 | /* Check invalid register operand when the address size override | |
6527 | prefix changes the size of register operands. */ | |
6528 | unsigned int op; | |
6529 | enum { need_word, need_dword, need_qword } need; | |
6530 | ||
6531 | if (flag_code == CODE_32BIT) | |
6532 | need = i.prefix[ADDR_PREFIX] ? need_word : need_dword; | |
6533 | else | |
6534 | { | |
6535 | if (i.prefix[ADDR_PREFIX]) | |
6536 | need = need_dword; | |
6537 | else | |
6538 | need = flag_code == CODE_64BIT ? need_qword : need_word; | |
6539 | } | |
6540 | ||
6541 | for (op = 0; op < i.operands; op++) | |
bab6aec1 | 6542 | if (i.types[op].bitfield.class == Reg |
c0a30a9f L |
6543 | && ((need == need_word |
6544 | && !i.op[op].regs->reg_type.bitfield.word) | |
6545 | || (need == need_dword | |
6546 | && !i.op[op].regs->reg_type.bitfield.dword) | |
6547 | || (need == need_qword | |
6548 | && !i.op[op].regs->reg_type.bitfield.qword))) | |
6549 | { | |
6550 | as_bad (_("invalid register operand size for `%s'"), | |
6551 | i.tm.name); | |
6552 | return 0; | |
6553 | } | |
6554 | } | |
6555 | ||
29b0f896 AM |
6556 | return 1; |
6557 | } | |
3e73aa7c | 6558 | |
29b0f896 | 6559 | static int |
543613e9 | 6560 | check_byte_reg (void) |
29b0f896 AM |
6561 | { |
6562 | int op; | |
543613e9 | 6563 | |
29b0f896 AM |
6564 | for (op = i.operands; --op >= 0;) |
6565 | { | |
dc821c5f | 6566 | /* Skip non-register operands. */ |
bab6aec1 | 6567 | if (i.types[op].bitfield.class != Reg) |
dc821c5f JB |
6568 | continue; |
6569 | ||
29b0f896 AM |
6570 | /* If this is an eight bit register, it's OK. If it's the 16 or |
6571 | 32 bit version of an eight bit register, we will just use the | |
6572 | low portion, and that's OK too. */ | |
dc821c5f | 6573 | if (i.types[op].bitfield.byte) |
29b0f896 AM |
6574 | continue; |
6575 | ||
5a819eb9 JB |
6576 | /* I/O port address operands are OK too. */ |
6577 | if (i.tm.operand_types[op].bitfield.inoutportreg) | |
6578 | continue; | |
6579 | ||
9344ff29 L |
6580 | /* crc32 doesn't generate this warning. */ |
6581 | if (i.tm.base_opcode == 0xf20f38f0) | |
6582 | continue; | |
6583 | ||
dc821c5f JB |
6584 | if ((i.types[op].bitfield.word |
6585 | || i.types[op].bitfield.dword | |
6586 | || i.types[op].bitfield.qword) | |
5a819eb9 JB |
6587 | && i.op[op].regs->reg_num < 4 |
6588 | /* Prohibit these changes in 64bit mode, since the lowering | |
6589 | would be more complicated. */ | |
6590 | && flag_code != CODE_64BIT) | |
29b0f896 | 6591 | { |
29b0f896 | 6592 | #if REGISTER_WARNINGS |
5a819eb9 | 6593 | if (!quiet_warnings) |
a540244d L |
6594 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6595 | register_prefix, | |
dc821c5f | 6596 | (i.op[op].regs + (i.types[op].bitfield.word |
29b0f896 AM |
6597 | ? REGNAM_AL - REGNAM_AX |
6598 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
a540244d | 6599 | register_prefix, |
29b0f896 AM |
6600 | i.op[op].regs->reg_name, |
6601 | i.suffix); | |
6602 | #endif | |
6603 | continue; | |
6604 | } | |
6605 | /* Any other register is bad. */ | |
bab6aec1 | 6606 | if (i.types[op].bitfield.class == Reg |
3528c362 JB |
6607 | || i.types[op].bitfield.class == RegMMX |
6608 | || i.types[op].bitfield.class == RegSIMD | |
00cee14f | 6609 | || i.types[op].bitfield.class == SReg |
4a5c67ed JB |
6610 | || i.types[op].bitfield.class == RegCR |
6611 | || i.types[op].bitfield.class == RegDR | |
6612 | || i.types[op].bitfield.class == RegTR) | |
29b0f896 | 6613 | { |
a540244d L |
6614 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6615 | register_prefix, | |
29b0f896 AM |
6616 | i.op[op].regs->reg_name, |
6617 | i.tm.name, | |
6618 | i.suffix); | |
6619 | return 0; | |
6620 | } | |
6621 | } | |
6622 | return 1; | |
6623 | } | |
6624 | ||
6625 | static int | |
e3bb37b5 | 6626 | check_long_reg (void) |
29b0f896 AM |
6627 | { |
6628 | int op; | |
6629 | ||
6630 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 6631 | /* Skip non-register operands. */ |
bab6aec1 | 6632 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 6633 | continue; |
29b0f896 AM |
6634 | /* Reject eight bit registers, except where the template requires |
6635 | them. (eg. movzb) */ | |
dc821c5f | 6636 | else if (i.types[op].bitfield.byte |
bab6aec1 | 6637 | && (i.tm.operand_types[op].bitfield.class == Reg |
dc821c5f JB |
6638 | || i.tm.operand_types[op].bitfield.acc) |
6639 | && (i.tm.operand_types[op].bitfield.word | |
6640 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6641 | { |
a540244d L |
6642 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6643 | register_prefix, | |
29b0f896 AM |
6644 | i.op[op].regs->reg_name, |
6645 | i.tm.name, | |
6646 | i.suffix); | |
6647 | return 0; | |
6648 | } | |
e4630f71 | 6649 | /* Warn if the e prefix on a general reg is missing. */ |
29b0f896 | 6650 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
dc821c5f | 6651 | && i.types[op].bitfield.word |
bab6aec1 | 6652 | && (i.tm.operand_types[op].bitfield.class == Reg |
dc821c5f JB |
6653 | || i.tm.operand_types[op].bitfield.acc) |
6654 | && i.tm.operand_types[op].bitfield.dword) | |
29b0f896 AM |
6655 | { |
6656 | /* Prohibit these changes in the 64bit mode, since the | |
6657 | lowering is more complicated. */ | |
6658 | if (flag_code == CODE_64BIT) | |
252b5132 | 6659 | { |
2b5d6a91 | 6660 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 6661 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
6662 | i.suffix); |
6663 | return 0; | |
252b5132 | 6664 | } |
29b0f896 | 6665 | #if REGISTER_WARNINGS |
cecf1424 JB |
6666 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6667 | register_prefix, | |
6668 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, | |
6669 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 | 6670 | #endif |
252b5132 | 6671 | } |
e4630f71 | 6672 | /* Warn if the r prefix on a general reg is present. */ |
dc821c5f | 6673 | else if (i.types[op].bitfield.qword |
bab6aec1 | 6674 | && (i.tm.operand_types[op].bitfield.class == Reg |
dc821c5f JB |
6675 | || i.tm.operand_types[op].bitfield.acc) |
6676 | && i.tm.operand_types[op].bitfield.dword) | |
252b5132 | 6677 | { |
34828aad | 6678 | if (intel_syntax |
ca61edf2 | 6679 | && i.tm.opcode_modifier.toqword |
3528c362 | 6680 | && i.types[0].bitfield.class != RegSIMD) |
34828aad | 6681 | { |
ca61edf2 | 6682 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
6683 | i.suffix = QWORD_MNEM_SUFFIX; |
6684 | } | |
6685 | else | |
6686 | { | |
2b5d6a91 | 6687 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6688 | register_prefix, i.op[op].regs->reg_name, |
6689 | i.suffix); | |
6690 | return 0; | |
6691 | } | |
29b0f896 AM |
6692 | } |
6693 | return 1; | |
6694 | } | |
252b5132 | 6695 | |
29b0f896 | 6696 | static int |
e3bb37b5 | 6697 | check_qword_reg (void) |
29b0f896 AM |
6698 | { |
6699 | int op; | |
252b5132 | 6700 | |
29b0f896 | 6701 | for (op = i.operands; --op >= 0; ) |
dc821c5f | 6702 | /* Skip non-register operands. */ |
bab6aec1 | 6703 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 6704 | continue; |
29b0f896 AM |
6705 | /* Reject eight bit registers, except where the template requires |
6706 | them. (eg. movzb) */ | |
dc821c5f | 6707 | else if (i.types[op].bitfield.byte |
bab6aec1 | 6708 | && (i.tm.operand_types[op].bitfield.class == Reg |
dc821c5f JB |
6709 | || i.tm.operand_types[op].bitfield.acc) |
6710 | && (i.tm.operand_types[op].bitfield.word | |
6711 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6712 | { |
a540244d L |
6713 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6714 | register_prefix, | |
29b0f896 AM |
6715 | i.op[op].regs->reg_name, |
6716 | i.tm.name, | |
6717 | i.suffix); | |
6718 | return 0; | |
6719 | } | |
e4630f71 | 6720 | /* Warn if the r prefix on a general reg is missing. */ |
dc821c5f JB |
6721 | else if ((i.types[op].bitfield.word |
6722 | || i.types[op].bitfield.dword) | |
bab6aec1 | 6723 | && (i.tm.operand_types[op].bitfield.class == Reg |
dc821c5f JB |
6724 | || i.tm.operand_types[op].bitfield.acc) |
6725 | && i.tm.operand_types[op].bitfield.qword) | |
29b0f896 AM |
6726 | { |
6727 | /* Prohibit these changes in the 64bit mode, since the | |
6728 | lowering is more complicated. */ | |
34828aad | 6729 | if (intel_syntax |
ca61edf2 | 6730 | && i.tm.opcode_modifier.todword |
3528c362 | 6731 | && i.types[0].bitfield.class != RegSIMD) |
34828aad | 6732 | { |
ca61edf2 | 6733 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
6734 | i.suffix = LONG_MNEM_SUFFIX; |
6735 | } | |
6736 | else | |
6737 | { | |
2b5d6a91 | 6738 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6739 | register_prefix, i.op[op].regs->reg_name, |
6740 | i.suffix); | |
6741 | return 0; | |
6742 | } | |
252b5132 | 6743 | } |
29b0f896 AM |
6744 | return 1; |
6745 | } | |
252b5132 | 6746 | |
29b0f896 | 6747 | static int |
e3bb37b5 | 6748 | check_word_reg (void) |
29b0f896 AM |
6749 | { |
6750 | int op; | |
6751 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 6752 | /* Skip non-register operands. */ |
bab6aec1 | 6753 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 6754 | continue; |
29b0f896 AM |
6755 | /* Reject eight bit registers, except where the template requires |
6756 | them. (eg. movzb) */ | |
dc821c5f | 6757 | else if (i.types[op].bitfield.byte |
bab6aec1 | 6758 | && (i.tm.operand_types[op].bitfield.class == Reg |
dc821c5f JB |
6759 | || i.tm.operand_types[op].bitfield.acc) |
6760 | && (i.tm.operand_types[op].bitfield.word | |
6761 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6762 | { |
a540244d L |
6763 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6764 | register_prefix, | |
29b0f896 AM |
6765 | i.op[op].regs->reg_name, |
6766 | i.tm.name, | |
6767 | i.suffix); | |
6768 | return 0; | |
6769 | } | |
e4630f71 | 6770 | /* Warn if the e or r prefix on a general reg is present. */ |
29b0f896 | 6771 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
dc821c5f JB |
6772 | && (i.types[op].bitfield.dword |
6773 | || i.types[op].bitfield.qword) | |
bab6aec1 | 6774 | && (i.tm.operand_types[op].bitfield.class == Reg |
dc821c5f JB |
6775 | || i.tm.operand_types[op].bitfield.acc) |
6776 | && i.tm.operand_types[op].bitfield.word) | |
252b5132 | 6777 | { |
29b0f896 AM |
6778 | /* Prohibit these changes in the 64bit mode, since the |
6779 | lowering is more complicated. */ | |
6780 | if (flag_code == CODE_64BIT) | |
252b5132 | 6781 | { |
2b5d6a91 | 6782 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 6783 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
6784 | i.suffix); |
6785 | return 0; | |
252b5132 | 6786 | } |
29b0f896 | 6787 | #if REGISTER_WARNINGS |
cecf1424 JB |
6788 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6789 | register_prefix, | |
6790 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, | |
6791 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 AM |
6792 | #endif |
6793 | } | |
6794 | return 1; | |
6795 | } | |
252b5132 | 6796 | |
29b0f896 | 6797 | static int |
40fb9820 | 6798 | update_imm (unsigned int j) |
29b0f896 | 6799 | { |
bc0844ae | 6800 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
6801 | if ((overlap.bitfield.imm8 |
6802 | || overlap.bitfield.imm8s | |
6803 | || overlap.bitfield.imm16 | |
6804 | || overlap.bitfield.imm32 | |
6805 | || overlap.bitfield.imm32s | |
6806 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
6807 | && !operand_type_equal (&overlap, &imm8) |
6808 | && !operand_type_equal (&overlap, &imm8s) | |
6809 | && !operand_type_equal (&overlap, &imm16) | |
6810 | && !operand_type_equal (&overlap, &imm32) | |
6811 | && !operand_type_equal (&overlap, &imm32s) | |
6812 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
6813 | { |
6814 | if (i.suffix) | |
6815 | { | |
40fb9820 L |
6816 | i386_operand_type temp; |
6817 | ||
0dfbf9d7 | 6818 | operand_type_set (&temp, 0); |
7ab9ffdd | 6819 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
6820 | { |
6821 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
6822 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
6823 | } | |
6824 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6825 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
6826 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6827 | { | |
6828 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
6829 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
6830 | } | |
6831 | else | |
6832 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
6833 | overlap = temp; | |
29b0f896 | 6834 | } |
0dfbf9d7 L |
6835 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
6836 | || operand_type_equal (&overlap, &imm16_32) | |
6837 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 6838 | { |
40fb9820 | 6839 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 6840 | overlap = imm16; |
40fb9820 | 6841 | else |
65da13b5 | 6842 | overlap = imm32s; |
29b0f896 | 6843 | } |
0dfbf9d7 L |
6844 | if (!operand_type_equal (&overlap, &imm8) |
6845 | && !operand_type_equal (&overlap, &imm8s) | |
6846 | && !operand_type_equal (&overlap, &imm16) | |
6847 | && !operand_type_equal (&overlap, &imm32) | |
6848 | && !operand_type_equal (&overlap, &imm32s) | |
6849 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 6850 | { |
4eed87de AM |
6851 | as_bad (_("no instruction mnemonic suffix given; " |
6852 | "can't determine immediate size")); | |
29b0f896 AM |
6853 | return 0; |
6854 | } | |
6855 | } | |
40fb9820 | 6856 | i.types[j] = overlap; |
29b0f896 | 6857 | |
40fb9820 L |
6858 | return 1; |
6859 | } | |
6860 | ||
6861 | static int | |
6862 | finalize_imm (void) | |
6863 | { | |
bc0844ae | 6864 | unsigned int j, n; |
29b0f896 | 6865 | |
bc0844ae L |
6866 | /* Update the first 2 immediate operands. */ |
6867 | n = i.operands > 2 ? 2 : i.operands; | |
6868 | if (n) | |
6869 | { | |
6870 | for (j = 0; j < n; j++) | |
6871 | if (update_imm (j) == 0) | |
6872 | return 0; | |
40fb9820 | 6873 | |
bc0844ae L |
6874 | /* The 3rd operand can't be immediate operand. */ |
6875 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
6876 | } | |
29b0f896 AM |
6877 | |
6878 | return 1; | |
6879 | } | |
6880 | ||
6881 | static int | |
e3bb37b5 | 6882 | process_operands (void) |
29b0f896 AM |
6883 | { |
6884 | /* Default segment register this instruction will use for memory | |
6885 | accesses. 0 means unknown. This is only for optimizing out | |
6886 | unnecessary segment overrides. */ | |
6887 | const seg_entry *default_seg = 0; | |
6888 | ||
2426c15f | 6889 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 6890 | { |
91d6fa6a NC |
6891 | unsigned int dupl = i.operands; |
6892 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
6893 | unsigned int j; |
6894 | ||
c0f3af97 | 6895 | /* The destination must be an xmm register. */ |
9c2799c2 | 6896 | gas_assert (i.reg_operands |
91d6fa6a | 6897 | && MAX_OPERANDS > dupl |
7ab9ffdd | 6898 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 | 6899 | |
1b54b8d7 JB |
6900 | if (i.tm.operand_types[0].bitfield.acc |
6901 | && i.tm.operand_types[0].bitfield.xmmword) | |
e2ec9d29 | 6902 | { |
8cd7925b | 6903 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
6904 | { |
6905 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
6906 | sources. */ | |
1b54b8d7 | 6907 | i.tm.operand_types[0].bitfield.acc = 0; |
3528c362 | 6908 | i.tm.operand_types[0].bitfield.class = RegSIMD; |
c0f3af97 L |
6909 | goto duplicate; |
6910 | } | |
e2ec9d29 | 6911 | else |
c0f3af97 L |
6912 | { |
6913 | /* We remove the first xmm0 and keep the number of | |
6914 | operands unchanged, which in fact duplicates the | |
6915 | destination. */ | |
6916 | for (j = 1; j < i.operands; j++) | |
6917 | { | |
6918 | i.op[j - 1] = i.op[j]; | |
6919 | i.types[j - 1] = i.types[j]; | |
6920 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
8dc0818e | 6921 | i.flags[j - 1] = i.flags[j]; |
c0f3af97 L |
6922 | } |
6923 | } | |
6924 | } | |
6925 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 6926 | { |
91d6fa6a | 6927 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
6928 | && (i.tm.opcode_modifier.vexsources |
6929 | == VEX3SOURCES)); | |
c0f3af97 L |
6930 | |
6931 | /* Add the implicit xmm0 for instructions with VEX prefix | |
6932 | and 3 sources. */ | |
6933 | for (j = i.operands; j > 0; j--) | |
6934 | { | |
6935 | i.op[j] = i.op[j - 1]; | |
6936 | i.types[j] = i.types[j - 1]; | |
6937 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
8dc0818e | 6938 | i.flags[j] = i.flags[j - 1]; |
c0f3af97 L |
6939 | } |
6940 | i.op[0].regs | |
6941 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
7ab9ffdd | 6942 | i.types[0] = regxmm; |
c0f3af97 L |
6943 | i.tm.operand_types[0] = regxmm; |
6944 | ||
6945 | i.operands += 2; | |
6946 | i.reg_operands += 2; | |
6947 | i.tm.operands += 2; | |
6948 | ||
91d6fa6a | 6949 | dupl++; |
c0f3af97 | 6950 | dest++; |
91d6fa6a NC |
6951 | i.op[dupl] = i.op[dest]; |
6952 | i.types[dupl] = i.types[dest]; | |
6953 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 6954 | i.flags[dupl] = i.flags[dest]; |
e2ec9d29 | 6955 | } |
c0f3af97 L |
6956 | else |
6957 | { | |
6958 | duplicate: | |
6959 | i.operands++; | |
6960 | i.reg_operands++; | |
6961 | i.tm.operands++; | |
6962 | ||
91d6fa6a NC |
6963 | i.op[dupl] = i.op[dest]; |
6964 | i.types[dupl] = i.types[dest]; | |
6965 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 6966 | i.flags[dupl] = i.flags[dest]; |
c0f3af97 L |
6967 | } |
6968 | ||
6969 | if (i.tm.opcode_modifier.immext) | |
6970 | process_immext (); | |
6971 | } | |
1b54b8d7 JB |
6972 | else if (i.tm.operand_types[0].bitfield.acc |
6973 | && i.tm.operand_types[0].bitfield.xmmword) | |
c0f3af97 L |
6974 | { |
6975 | unsigned int j; | |
6976 | ||
9fcfb3d7 L |
6977 | for (j = 1; j < i.operands; j++) |
6978 | { | |
6979 | i.op[j - 1] = i.op[j]; | |
6980 | i.types[j - 1] = i.types[j]; | |
6981 | ||
6982 | /* We need to adjust fields in i.tm since they are used by | |
6983 | build_modrm_byte. */ | |
6984 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
8dc0818e JB |
6985 | |
6986 | i.flags[j - 1] = i.flags[j]; | |
9fcfb3d7 L |
6987 | } |
6988 | ||
e2ec9d29 L |
6989 | i.operands--; |
6990 | i.reg_operands--; | |
e2ec9d29 L |
6991 | i.tm.operands--; |
6992 | } | |
920d2ddc IT |
6993 | else if (i.tm.opcode_modifier.implicitquadgroup) |
6994 | { | |
a477a8c4 JB |
6995 | unsigned int regnum, first_reg_in_group, last_reg_in_group; |
6996 | ||
920d2ddc | 6997 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ |
3528c362 | 6998 | gas_assert (i.operands >= 2 && i.types[1].bitfield.class == RegSIMD); |
a477a8c4 JB |
6999 | regnum = register_number (i.op[1].regs); |
7000 | first_reg_in_group = regnum & ~3; | |
7001 | last_reg_in_group = first_reg_in_group + 3; | |
7002 | if (regnum != first_reg_in_group) | |
7003 | as_warn (_("source register `%s%s' implicitly denotes" | |
7004 | " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"), | |
7005 | register_prefix, i.op[1].regs->reg_name, | |
7006 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
7007 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
7008 | i.tm.name); | |
7009 | } | |
e2ec9d29 L |
7010 | else if (i.tm.opcode_modifier.regkludge) |
7011 | { | |
7012 | /* The imul $imm, %reg instruction is converted into | |
7013 | imul $imm, %reg, %reg, and the clr %reg instruction | |
7014 | is converted into xor %reg, %reg. */ | |
7015 | ||
7016 | unsigned int first_reg_op; | |
7017 | ||
7018 | if (operand_type_check (i.types[0], reg)) | |
7019 | first_reg_op = 0; | |
7020 | else | |
7021 | first_reg_op = 1; | |
7022 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 7023 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 7024 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
7025 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
7026 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
7027 | i.operands++; | |
7028 | i.reg_operands++; | |
29b0f896 AM |
7029 | } |
7030 | ||
85b80b0f | 7031 | if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
7032 | { |
7033 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
7034 | must be put into the modrm byte). Now, we make the modrm and |
7035 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
7036 | |
7037 | default_seg = build_modrm_byte (); | |
7038 | } | |
00cee14f | 7039 | else if (i.types[0].bitfield.class == SReg) |
85b80b0f JB |
7040 | { |
7041 | if (flag_code != CODE_64BIT | |
7042 | ? i.tm.base_opcode == POP_SEG_SHORT | |
7043 | && i.op[0].regs->reg_num == 1 | |
7044 | : (i.tm.base_opcode | 1) == POP_SEG386_SHORT | |
7045 | && i.op[0].regs->reg_num < 4) | |
7046 | { | |
7047 | as_bad (_("you can't `%s %s%s'"), | |
7048 | i.tm.name, register_prefix, i.op[0].regs->reg_name); | |
7049 | return 0; | |
7050 | } | |
7051 | if ( i.op[0].regs->reg_num > 3 && i.tm.opcode_length == 1 ) | |
7052 | { | |
7053 | i.tm.base_opcode ^= POP_SEG_SHORT ^ POP_SEG386_SHORT; | |
7054 | i.tm.opcode_length = 2; | |
7055 | } | |
7056 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); | |
7057 | } | |
8a2ed489 | 7058 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
7059 | { |
7060 | default_seg = &ds; | |
7061 | } | |
40fb9820 | 7062 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
7063 | { |
7064 | /* For the string instructions that allow a segment override | |
7065 | on one of their operands, the default segment is ds. */ | |
7066 | default_seg = &ds; | |
7067 | } | |
85b80b0f JB |
7068 | else if (i.tm.opcode_modifier.shortform) |
7069 | { | |
7070 | /* The register or float register operand is in operand | |
7071 | 0 or 1. */ | |
bab6aec1 | 7072 | unsigned int op = i.tm.operand_types[0].bitfield.class != Reg; |
85b80b0f JB |
7073 | |
7074 | /* Register goes in low 3 bits of opcode. */ | |
7075 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
7076 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7077 | i.rex |= REX_B; | |
7078 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) | |
7079 | { | |
7080 | /* Warn about some common errors, but press on regardless. | |
7081 | The first case can be generated by gcc (<= 2.8.1). */ | |
7082 | if (i.operands == 2) | |
7083 | { | |
7084 | /* Reversed arguments on faddp, fsubp, etc. */ | |
7085 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, | |
7086 | register_prefix, i.op[!intel_syntax].regs->reg_name, | |
7087 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
7088 | } | |
7089 | else | |
7090 | { | |
7091 | /* Extraneous `l' suffix on fp insn. */ | |
7092 | as_warn (_("translating to `%s %s%s'"), i.tm.name, | |
7093 | register_prefix, i.op[0].regs->reg_name); | |
7094 | } | |
7095 | } | |
7096 | } | |
29b0f896 | 7097 | |
75178d9d L |
7098 | if (i.tm.base_opcode == 0x8d /* lea */ |
7099 | && i.seg[0] | |
7100 | && !quiet_warnings) | |
30123838 | 7101 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
52271982 AM |
7102 | |
7103 | /* If a segment was explicitly specified, and the specified segment | |
7104 | is not the default, use an opcode prefix to select it. If we | |
7105 | never figured out what the default segment is, then default_seg | |
7106 | will be zero at this point, and the specified segment prefix will | |
7107 | always be used. */ | |
29b0f896 AM |
7108 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
7109 | { | |
7110 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
7111 | return 0; | |
7112 | } | |
7113 | return 1; | |
7114 | } | |
7115 | ||
7116 | static const seg_entry * | |
e3bb37b5 | 7117 | build_modrm_byte (void) |
29b0f896 AM |
7118 | { |
7119 | const seg_entry *default_seg = 0; | |
c0f3af97 | 7120 | unsigned int source, dest; |
8cd7925b | 7121 | int vex_3_sources; |
c0f3af97 | 7122 | |
8cd7925b | 7123 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
7124 | if (vex_3_sources) |
7125 | { | |
91d6fa6a | 7126 | unsigned int nds, reg_slot; |
4c2c6516 | 7127 | expressionS *exp; |
c0f3af97 | 7128 | |
6b8d3588 | 7129 | dest = i.operands - 1; |
c0f3af97 | 7130 | nds = dest - 1; |
922d8de8 | 7131 | |
a683cc34 | 7132 | /* There are 2 kinds of instructions: |
bed3d976 | 7133 | 1. 5 operands: 4 register operands or 3 register operands |
9d3bf266 | 7134 | plus 1 memory operand plus one Imm4 operand, VexXDS, and |
bed3d976 | 7135 | VexW0 or VexW1. The destination must be either XMM, YMM or |
43234a1e | 7136 | ZMM register. |
bed3d976 | 7137 | 2. 4 operands: 4 register operands or 3 register operands |
2f1bada2 | 7138 | plus 1 memory operand, with VexXDS. */ |
922d8de8 | 7139 | gas_assert ((i.reg_operands == 4 |
bed3d976 JB |
7140 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
7141 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
dcd7e323 | 7142 | && i.tm.opcode_modifier.vexw |
3528c362 | 7143 | && i.tm.operand_types[dest].bitfield.class == RegSIMD); |
a683cc34 | 7144 | |
48db9223 JB |
7145 | /* If VexW1 is set, the first non-immediate operand is the source and |
7146 | the second non-immediate one is encoded in the immediate operand. */ | |
7147 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
7148 | { | |
7149 | source = i.imm_operands; | |
7150 | reg_slot = i.imm_operands + 1; | |
7151 | } | |
7152 | else | |
7153 | { | |
7154 | source = i.imm_operands + 1; | |
7155 | reg_slot = i.imm_operands; | |
7156 | } | |
7157 | ||
a683cc34 | 7158 | if (i.imm_operands == 0) |
bed3d976 JB |
7159 | { |
7160 | /* When there is no immediate operand, generate an 8bit | |
7161 | immediate operand to encode the first operand. */ | |
7162 | exp = &im_expressions[i.imm_operands++]; | |
7163 | i.op[i.operands].imms = exp; | |
7164 | i.types[i.operands] = imm8; | |
7165 | i.operands++; | |
7166 | ||
3528c362 | 7167 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
bed3d976 JB |
7168 | exp->X_op = O_constant; |
7169 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; | |
43234a1e L |
7170 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
7171 | } | |
922d8de8 | 7172 | else |
bed3d976 | 7173 | { |
9d3bf266 JB |
7174 | gas_assert (i.imm_operands == 1); |
7175 | gas_assert (fits_in_imm4 (i.op[0].imms->X_add_number)); | |
7176 | gas_assert (!i.tm.opcode_modifier.immext); | |
a683cc34 | 7177 | |
9d3bf266 JB |
7178 | /* Turn on Imm8 again so that output_imm will generate it. */ |
7179 | i.types[0].bitfield.imm8 = 1; | |
bed3d976 | 7180 | |
3528c362 | 7181 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
9d3bf266 | 7182 | i.op[0].imms->X_add_number |
bed3d976 | 7183 | |= register_number (i.op[reg_slot].regs) << 4; |
43234a1e | 7184 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
bed3d976 | 7185 | } |
a683cc34 | 7186 | |
3528c362 | 7187 | gas_assert (i.tm.operand_types[nds].bitfield.class == RegSIMD); |
dae39acc | 7188 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
7189 | } |
7190 | else | |
7191 | source = dest = 0; | |
29b0f896 AM |
7192 | |
7193 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
7194 | implicit registers do not count. If there are 3 register |
7195 | operands, it must be a instruction with VexNDS. For a | |
7196 | instruction with VexNDD, the destination register is encoded | |
7197 | in VEX prefix. If there are 4 register operands, it must be | |
7198 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
7199 | if (i.mem_operands == 0 |
7200 | && ((i.reg_operands == 2 | |
2426c15f | 7201 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 7202 | || (i.reg_operands == 3 |
2426c15f | 7203 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 7204 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 7205 | { |
cab737b9 L |
7206 | switch (i.operands) |
7207 | { | |
7208 | case 2: | |
7209 | source = 0; | |
7210 | break; | |
7211 | case 3: | |
c81128dc L |
7212 | /* When there are 3 operands, one of them may be immediate, |
7213 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
7214 | the first operand must be shift count register (cl) or it |
7215 | is an instruction with VexNDS. */ | |
9c2799c2 | 7216 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 7217 | || (i.imm_operands == 0 |
2426c15f | 7218 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd | 7219 | || i.types[0].bitfield.shiftcount))); |
40fb9820 L |
7220 | if (operand_type_check (i.types[0], imm) |
7221 | || i.types[0].bitfield.shiftcount) | |
7222 | source = 1; | |
7223 | else | |
7224 | source = 0; | |
cab737b9 L |
7225 | break; |
7226 | case 4: | |
368d64cc L |
7227 | /* When there are 4 operands, the first two must be 8bit |
7228 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
7229 | one. |
7230 | ||
7231 | For instructions with VexNDS, if the first operand | |
7232 | an imm8, the source operand is the 2nd one. If the last | |
7233 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 7234 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
7235 | && i.types[0].bitfield.imm8 |
7236 | && i.types[1].bitfield.imm8) | |
2426c15f | 7237 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
7238 | && i.imm_operands == 1 |
7239 | && (i.types[0].bitfield.imm8 | |
43234a1e L |
7240 | || i.types[i.operands - 1].bitfield.imm8 |
7241 | || i.rounding))); | |
9f2670f2 L |
7242 | if (i.imm_operands == 2) |
7243 | source = 2; | |
7244 | else | |
c0f3af97 L |
7245 | { |
7246 | if (i.types[0].bitfield.imm8) | |
7247 | source = 1; | |
7248 | else | |
7249 | source = 0; | |
7250 | } | |
c0f3af97 L |
7251 | break; |
7252 | case 5: | |
e771e7c9 | 7253 | if (is_evex_encoding (&i.tm)) |
43234a1e L |
7254 | { |
7255 | /* For EVEX instructions, when there are 5 operands, the | |
7256 | first one must be immediate operand. If the second one | |
7257 | is immediate operand, the source operand is the 3th | |
7258 | one. If the last one is immediate operand, the source | |
7259 | operand is the 2nd one. */ | |
7260 | gas_assert (i.imm_operands == 2 | |
7261 | && i.tm.opcode_modifier.sae | |
7262 | && operand_type_check (i.types[0], imm)); | |
7263 | if (operand_type_check (i.types[1], imm)) | |
7264 | source = 2; | |
7265 | else if (operand_type_check (i.types[4], imm)) | |
7266 | source = 1; | |
7267 | else | |
7268 | abort (); | |
7269 | } | |
cab737b9 L |
7270 | break; |
7271 | default: | |
7272 | abort (); | |
7273 | } | |
7274 | ||
c0f3af97 L |
7275 | if (!vex_3_sources) |
7276 | { | |
7277 | dest = source + 1; | |
7278 | ||
43234a1e L |
7279 | /* RC/SAE operand could be between DEST and SRC. That happens |
7280 | when one operand is GPR and the other one is XMM/YMM/ZMM | |
7281 | register. */ | |
7282 | if (i.rounding && i.rounding->operand == (int) dest) | |
7283 | dest++; | |
7284 | ||
2426c15f | 7285 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 | 7286 | { |
43234a1e | 7287 | /* For instructions with VexNDS, the register-only source |
c5d0745b | 7288 | operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask |
dfd69174 | 7289 | register. It is encoded in VEX prefix. */ |
f12dc422 L |
7290 | |
7291 | i386_operand_type op; | |
7292 | unsigned int vvvv; | |
7293 | ||
7294 | /* Check register-only source operand when two source | |
7295 | operands are swapped. */ | |
7296 | if (!i.tm.operand_types[source].bitfield.baseindex | |
7297 | && i.tm.operand_types[dest].bitfield.baseindex) | |
7298 | { | |
7299 | vvvv = source; | |
7300 | source = dest; | |
7301 | } | |
7302 | else | |
7303 | vvvv = dest; | |
7304 | ||
7305 | op = i.tm.operand_types[vvvv]; | |
c0f3af97 | 7306 | if ((dest + 1) >= i.operands |
bab6aec1 | 7307 | || ((op.bitfield.class != Reg |
dc821c5f | 7308 | || (!op.bitfield.dword && !op.bitfield.qword)) |
3528c362 | 7309 | && op.bitfield.class != RegSIMD |
43234a1e | 7310 | && !operand_type_equal (&op, ®mask))) |
c0f3af97 | 7311 | abort (); |
f12dc422 | 7312 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
7313 | dest++; |
7314 | } | |
7315 | } | |
29b0f896 AM |
7316 | |
7317 | i.rm.mode = 3; | |
dfd69174 JB |
7318 | /* One of the register operands will be encoded in the i.rm.reg |
7319 | field, the other in the combined i.rm.mode and i.rm.regmem | |
29b0f896 AM |
7320 | fields. If no form of this instruction supports a memory |
7321 | destination operand, then we assume the source operand may | |
7322 | sometimes be a memory operand and so we need to store the | |
7323 | destination in the i.rm.reg field. */ | |
dfd69174 | 7324 | if (!i.tm.opcode_modifier.regmem |
40fb9820 | 7325 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) |
29b0f896 AM |
7326 | { |
7327 | i.rm.reg = i.op[dest].regs->reg_num; | |
7328 | i.rm.regmem = i.op[source].regs->reg_num; | |
3528c362 JB |
7329 | if (i.op[dest].regs->reg_type.bitfield.class == RegMMX |
7330 | || i.op[source].regs->reg_type.bitfield.class == RegMMX) | |
b4a3a7b4 | 7331 | i.has_regmmx = TRUE; |
3528c362 JB |
7332 | else if (i.op[dest].regs->reg_type.bitfield.class == RegSIMD |
7333 | || i.op[source].regs->reg_type.bitfield.class == RegSIMD) | |
b4a3a7b4 L |
7334 | { |
7335 | if (i.types[dest].bitfield.zmmword | |
7336 | || i.types[source].bitfield.zmmword) | |
7337 | i.has_regzmm = TRUE; | |
7338 | else if (i.types[dest].bitfield.ymmword | |
7339 | || i.types[source].bitfield.ymmword) | |
7340 | i.has_regymm = TRUE; | |
7341 | else | |
7342 | i.has_regxmm = TRUE; | |
7343 | } | |
29b0f896 | 7344 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7345 | i.rex |= REX_R; |
43234a1e L |
7346 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
7347 | i.vrex |= REX_R; | |
29b0f896 | 7348 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7349 | i.rex |= REX_B; |
43234a1e L |
7350 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
7351 | i.vrex |= REX_B; | |
29b0f896 AM |
7352 | } |
7353 | else | |
7354 | { | |
7355 | i.rm.reg = i.op[source].regs->reg_num; | |
7356 | i.rm.regmem = i.op[dest].regs->reg_num; | |
7357 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 7358 | i.rex |= REX_B; |
43234a1e L |
7359 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
7360 | i.vrex |= REX_B; | |
29b0f896 | 7361 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7362 | i.rex |= REX_R; |
43234a1e L |
7363 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
7364 | i.vrex |= REX_R; | |
29b0f896 | 7365 | } |
e0c7f900 | 7366 | if (flag_code != CODE_64BIT && (i.rex & REX_R)) |
c4a530c5 | 7367 | { |
4a5c67ed | 7368 | if (i.types[!i.tm.opcode_modifier.regmem].bitfield.class != RegCR) |
c4a530c5 | 7369 | abort (); |
e0c7f900 | 7370 | i.rex &= ~REX_R; |
c4a530c5 JB |
7371 | add_prefix (LOCK_PREFIX_OPCODE); |
7372 | } | |
29b0f896 AM |
7373 | } |
7374 | else | |
7375 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
7376 | unsigned int mem; |
7377 | ||
29b0f896 AM |
7378 | if (i.mem_operands) |
7379 | { | |
7380 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 7381 | unsigned int op; |
4eed87de | 7382 | |
7ab9ffdd | 7383 | for (op = 0; op < i.operands; op++) |
8dc0818e | 7384 | if (i.flags[op] & Operand_Mem) |
7ab9ffdd | 7385 | break; |
7ab9ffdd | 7386 | gas_assert (op < i.operands); |
29b0f896 | 7387 | |
6c30d220 L |
7388 | if (i.tm.opcode_modifier.vecsib) |
7389 | { | |
e968fc9b | 7390 | if (i.index_reg->reg_num == RegIZ) |
6c30d220 L |
7391 | abort (); |
7392 | ||
7393 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
7394 | if (!i.base_reg) | |
7395 | { | |
7396 | i.sib.base = NO_BASE_REGISTER; | |
7397 | i.sib.scale = i.log2_scale_factor; | |
7398 | i.types[op].bitfield.disp8 = 0; | |
7399 | i.types[op].bitfield.disp16 = 0; | |
7400 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 7401 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
6c30d220 L |
7402 | { |
7403 | /* Must be 32 bit */ | |
7404 | i.types[op].bitfield.disp32 = 1; | |
7405 | i.types[op].bitfield.disp32s = 0; | |
7406 | } | |
7407 | else | |
7408 | { | |
7409 | i.types[op].bitfield.disp32 = 0; | |
7410 | i.types[op].bitfield.disp32s = 1; | |
7411 | } | |
7412 | } | |
7413 | i.sib.index = i.index_reg->reg_num; | |
7414 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
7415 | i.rex |= REX_X; | |
43234a1e L |
7416 | if ((i.index_reg->reg_flags & RegVRex) != 0) |
7417 | i.vrex |= REX_X; | |
6c30d220 L |
7418 | } |
7419 | ||
29b0f896 AM |
7420 | default_seg = &ds; |
7421 | ||
7422 | if (i.base_reg == 0) | |
7423 | { | |
7424 | i.rm.mode = 0; | |
7425 | if (!i.disp_operands) | |
9bb129e8 | 7426 | fake_zero_displacement = 1; |
29b0f896 AM |
7427 | if (i.index_reg == 0) |
7428 | { | |
73053c1f JB |
7429 | i386_operand_type newdisp; |
7430 | ||
6c30d220 | 7431 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 7432 | /* Operand is just <disp> */ |
20f0a1fc | 7433 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
7434 | { |
7435 | /* 64bit mode overwrites the 32bit absolute | |
7436 | addressing by RIP relative addressing and | |
7437 | absolute addressing is encoded by one of the | |
7438 | redundant SIB forms. */ | |
7439 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
7440 | i.sib.base = NO_BASE_REGISTER; | |
7441 | i.sib.index = NO_INDEX_REGISTER; | |
73053c1f | 7442 | newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32); |
20f0a1fc | 7443 | } |
fc225355 L |
7444 | else if ((flag_code == CODE_16BIT) |
7445 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
7446 | { |
7447 | i.rm.regmem = NO_BASE_REGISTER_16; | |
73053c1f | 7448 | newdisp = disp16; |
20f0a1fc NC |
7449 | } |
7450 | else | |
7451 | { | |
7452 | i.rm.regmem = NO_BASE_REGISTER; | |
73053c1f | 7453 | newdisp = disp32; |
29b0f896 | 7454 | } |
73053c1f JB |
7455 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
7456 | i.types[op] = operand_type_or (i.types[op], newdisp); | |
29b0f896 | 7457 | } |
6c30d220 | 7458 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7459 | { |
6c30d220 | 7460 | /* !i.base_reg && i.index_reg */ |
e968fc9b | 7461 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
7462 | i.sib.index = NO_INDEX_REGISTER; |
7463 | else | |
7464 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7465 | i.sib.base = NO_BASE_REGISTER; |
7466 | i.sib.scale = i.log2_scale_factor; | |
7467 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
7468 | i.types[op].bitfield.disp8 = 0; |
7469 | i.types[op].bitfield.disp16 = 0; | |
7470 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 7471 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
40fb9820 L |
7472 | { |
7473 | /* Must be 32 bit */ | |
7474 | i.types[op].bitfield.disp32 = 1; | |
7475 | i.types[op].bitfield.disp32s = 0; | |
7476 | } | |
29b0f896 | 7477 | else |
40fb9820 L |
7478 | { |
7479 | i.types[op].bitfield.disp32 = 0; | |
7480 | i.types[op].bitfield.disp32s = 1; | |
7481 | } | |
29b0f896 | 7482 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7483 | i.rex |= REX_X; |
29b0f896 AM |
7484 | } |
7485 | } | |
7486 | /* RIP addressing for 64bit mode. */ | |
e968fc9b | 7487 | else if (i.base_reg->reg_num == RegIP) |
29b0f896 | 7488 | { |
6c30d220 | 7489 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 7490 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
7491 | i.types[op].bitfield.disp8 = 0; |
7492 | i.types[op].bitfield.disp16 = 0; | |
7493 | i.types[op].bitfield.disp32 = 0; | |
7494 | i.types[op].bitfield.disp32s = 1; | |
7495 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 7496 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
7497 | if (! i.disp_operands) |
7498 | fake_zero_displacement = 1; | |
29b0f896 | 7499 | } |
dc821c5f | 7500 | else if (i.base_reg->reg_type.bitfield.word) |
29b0f896 | 7501 | { |
6c30d220 | 7502 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
7503 | switch (i.base_reg->reg_num) |
7504 | { | |
7505 | case 3: /* (%bx) */ | |
7506 | if (i.index_reg == 0) | |
7507 | i.rm.regmem = 7; | |
7508 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
7509 | i.rm.regmem = i.index_reg->reg_num - 6; | |
7510 | break; | |
7511 | case 5: /* (%bp) */ | |
7512 | default_seg = &ss; | |
7513 | if (i.index_reg == 0) | |
7514 | { | |
7515 | i.rm.regmem = 6; | |
40fb9820 | 7516 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
7517 | { |
7518 | /* fake (%bp) into 0(%bp) */ | |
b5014f7a | 7519 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 7520 | fake_zero_displacement = 1; |
29b0f896 AM |
7521 | } |
7522 | } | |
7523 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
7524 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
7525 | break; | |
7526 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
7527 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
7528 | } | |
7529 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
7530 | } | |
7531 | else /* i.base_reg and 32/64 bit mode */ | |
7532 | { | |
7533 | if (flag_code == CODE_64BIT | |
40fb9820 L |
7534 | && operand_type_check (i.types[op], disp)) |
7535 | { | |
73053c1f JB |
7536 | i.types[op].bitfield.disp16 = 0; |
7537 | i.types[op].bitfield.disp64 = 0; | |
40fb9820 | 7538 | if (i.prefix[ADDR_PREFIX] == 0) |
73053c1f JB |
7539 | { |
7540 | i.types[op].bitfield.disp32 = 0; | |
7541 | i.types[op].bitfield.disp32s = 1; | |
7542 | } | |
40fb9820 | 7543 | else |
73053c1f JB |
7544 | { |
7545 | i.types[op].bitfield.disp32 = 1; | |
7546 | i.types[op].bitfield.disp32s = 0; | |
7547 | } | |
40fb9820 | 7548 | } |
20f0a1fc | 7549 | |
6c30d220 L |
7550 | if (!i.tm.opcode_modifier.vecsib) |
7551 | i.rm.regmem = i.base_reg->reg_num; | |
29b0f896 | 7552 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7553 | i.rex |= REX_B; |
29b0f896 AM |
7554 | i.sib.base = i.base_reg->reg_num; |
7555 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
7556 | complications. */ | |
848930b2 JB |
7557 | if (!(i.base_reg->reg_flags & RegRex) |
7558 | && (i.base_reg->reg_num == EBP_REG_NUM | |
7559 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
29b0f896 | 7560 | default_seg = &ss; |
848930b2 | 7561 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 7562 | { |
848930b2 | 7563 | fake_zero_displacement = 1; |
b5014f7a | 7564 | i.types[op].bitfield.disp8 = 1; |
29b0f896 AM |
7565 | } |
7566 | i.sib.scale = i.log2_scale_factor; | |
7567 | if (i.index_reg == 0) | |
7568 | { | |
6c30d220 | 7569 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
7570 | /* <disp>(%esp) becomes two byte modrm with no index |
7571 | register. We've already stored the code for esp | |
7572 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
7573 | Any base register besides %esp will not use the | |
7574 | extra modrm byte. */ | |
7575 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 7576 | } |
6c30d220 | 7577 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7578 | { |
e968fc9b | 7579 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
7580 | i.sib.index = NO_INDEX_REGISTER; |
7581 | else | |
7582 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7583 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
7584 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 7585 | i.rex |= REX_X; |
29b0f896 | 7586 | } |
67a4f2b7 AO |
7587 | |
7588 | if (i.disp_operands | |
7589 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
7590 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
7591 | i.rm.mode = 0; | |
7592 | else | |
a501d77e L |
7593 | { |
7594 | if (!fake_zero_displacement | |
7595 | && !i.disp_operands | |
7596 | && i.disp_encoding) | |
7597 | { | |
7598 | fake_zero_displacement = 1; | |
7599 | if (i.disp_encoding == disp_encoding_8bit) | |
7600 | i.types[op].bitfield.disp8 = 1; | |
7601 | else | |
7602 | i.types[op].bitfield.disp32 = 1; | |
7603 | } | |
7604 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
7605 | } | |
29b0f896 | 7606 | } |
252b5132 | 7607 | |
29b0f896 AM |
7608 | if (fake_zero_displacement) |
7609 | { | |
7610 | /* Fakes a zero displacement assuming that i.types[op] | |
7611 | holds the correct displacement size. */ | |
7612 | expressionS *exp; | |
7613 | ||
9c2799c2 | 7614 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
7615 | exp = &disp_expressions[i.disp_operands++]; |
7616 | i.op[op].disps = exp; | |
7617 | exp->X_op = O_constant; | |
7618 | exp->X_add_number = 0; | |
7619 | exp->X_add_symbol = (symbolS *) 0; | |
7620 | exp->X_op_symbol = (symbolS *) 0; | |
7621 | } | |
c0f3af97 L |
7622 | |
7623 | mem = op; | |
29b0f896 | 7624 | } |
c0f3af97 L |
7625 | else |
7626 | mem = ~0; | |
252b5132 | 7627 | |
8c43a48b | 7628 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
7629 | { |
7630 | if (operand_type_check (i.types[0], imm)) | |
7631 | i.vex.register_specifier = NULL; | |
7632 | else | |
7633 | { | |
7634 | /* VEX.vvvv encodes one of the sources when the first | |
7635 | operand is not an immediate. */ | |
1ef99a7b | 7636 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7637 | i.vex.register_specifier = i.op[0].regs; |
7638 | else | |
7639 | i.vex.register_specifier = i.op[1].regs; | |
7640 | } | |
7641 | ||
7642 | /* Destination is a XMM register encoded in the ModRM.reg | |
7643 | and VEX.R bit. */ | |
7644 | i.rm.reg = i.op[2].regs->reg_num; | |
7645 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
7646 | i.rex |= REX_R; | |
7647 | ||
7648 | /* ModRM.rm and VEX.B encodes the other source. */ | |
7649 | if (!i.mem_operands) | |
7650 | { | |
7651 | i.rm.mode = 3; | |
7652 | ||
1ef99a7b | 7653 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7654 | i.rm.regmem = i.op[1].regs->reg_num; |
7655 | else | |
7656 | i.rm.regmem = i.op[0].regs->reg_num; | |
7657 | ||
7658 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7659 | i.rex |= REX_B; | |
7660 | } | |
7661 | } | |
2426c15f | 7662 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
7663 | { |
7664 | i.vex.register_specifier = i.op[2].regs; | |
7665 | if (!i.mem_operands) | |
7666 | { | |
7667 | i.rm.mode = 3; | |
7668 | i.rm.regmem = i.op[1].regs->reg_num; | |
7669 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7670 | i.rex |= REX_B; | |
7671 | } | |
7672 | } | |
29b0f896 AM |
7673 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
7674 | (if any) based on i.tm.extension_opcode. Again, we must be | |
7675 | careful to make sure that segment/control/debug/test/MMX | |
7676 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 7677 | else if (i.reg_operands) |
29b0f896 | 7678 | { |
99018f42 | 7679 | unsigned int op; |
7ab9ffdd L |
7680 | unsigned int vex_reg = ~0; |
7681 | ||
7682 | for (op = 0; op < i.operands; op++) | |
b4a3a7b4 | 7683 | { |
bab6aec1 | 7684 | if (i.types[op].bitfield.class == Reg |
b4a3a7b4 L |
7685 | || i.types[op].bitfield.regbnd |
7686 | || i.types[op].bitfield.regmask | |
00cee14f | 7687 | || i.types[op].bitfield.class == SReg |
4a5c67ed JB |
7688 | || i.types[op].bitfield.class == RegCR |
7689 | || i.types[op].bitfield.class == RegDR | |
7690 | || i.types[op].bitfield.class == RegTR) | |
b4a3a7b4 | 7691 | break; |
3528c362 | 7692 | if (i.types[op].bitfield.class == RegSIMD) |
b4a3a7b4 L |
7693 | { |
7694 | if (i.types[op].bitfield.zmmword) | |
7695 | i.has_regzmm = TRUE; | |
7696 | else if (i.types[op].bitfield.ymmword) | |
7697 | i.has_regymm = TRUE; | |
7698 | else | |
7699 | i.has_regxmm = TRUE; | |
7700 | break; | |
7701 | } | |
3528c362 | 7702 | if (i.types[op].bitfield.class == RegMMX) |
b4a3a7b4 L |
7703 | { |
7704 | i.has_regmmx = TRUE; | |
7705 | break; | |
7706 | } | |
7707 | } | |
c0209578 | 7708 | |
7ab9ffdd L |
7709 | if (vex_3_sources) |
7710 | op = dest; | |
2426c15f | 7711 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
7712 | { |
7713 | /* For instructions with VexNDS, the register-only | |
7714 | source operand is encoded in VEX prefix. */ | |
7715 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 7716 | |
7ab9ffdd | 7717 | if (op > mem) |
c0f3af97 | 7718 | { |
7ab9ffdd L |
7719 | vex_reg = op++; |
7720 | gas_assert (op < i.operands); | |
c0f3af97 L |
7721 | } |
7722 | else | |
c0f3af97 | 7723 | { |
f12dc422 L |
7724 | /* Check register-only source operand when two source |
7725 | operands are swapped. */ | |
7726 | if (!i.tm.operand_types[op].bitfield.baseindex | |
7727 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
7728 | { | |
7729 | vex_reg = op; | |
7730 | op += 2; | |
7731 | gas_assert (mem == (vex_reg + 1) | |
7732 | && op < i.operands); | |
7733 | } | |
7734 | else | |
7735 | { | |
7736 | vex_reg = op + 1; | |
7737 | gas_assert (vex_reg < i.operands); | |
7738 | } | |
c0f3af97 | 7739 | } |
7ab9ffdd | 7740 | } |
2426c15f | 7741 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 7742 | { |
f12dc422 | 7743 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 7744 | is encoded in VEX prefix. */ |
f12dc422 L |
7745 | if (i.mem_operands == 0) |
7746 | { | |
7747 | /* There is no memory operand. */ | |
7748 | gas_assert ((op + 2) == i.operands); | |
7749 | vex_reg = op + 1; | |
7750 | } | |
7751 | else | |
8d63c93e | 7752 | { |
ed438a93 JB |
7753 | /* There are only 2 non-immediate operands. */ |
7754 | gas_assert (op < i.imm_operands + 2 | |
7755 | && i.operands == i.imm_operands + 2); | |
7756 | vex_reg = i.imm_operands + 1; | |
f12dc422 | 7757 | } |
7ab9ffdd L |
7758 | } |
7759 | else | |
7760 | gas_assert (op < i.operands); | |
99018f42 | 7761 | |
7ab9ffdd L |
7762 | if (vex_reg != (unsigned int) ~0) |
7763 | { | |
f12dc422 | 7764 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 7765 | |
bab6aec1 | 7766 | if ((type->bitfield.class != Reg |
dc821c5f | 7767 | || (!type->bitfield.dword && !type->bitfield.qword)) |
3528c362 | 7768 | && type->bitfield.class != RegSIMD |
43234a1e | 7769 | && !operand_type_equal (type, ®mask)) |
7ab9ffdd | 7770 | abort (); |
f88c9eb0 | 7771 | |
7ab9ffdd L |
7772 | i.vex.register_specifier = i.op[vex_reg].regs; |
7773 | } | |
7774 | ||
1b9f0c97 L |
7775 | /* Don't set OP operand twice. */ |
7776 | if (vex_reg != op) | |
7ab9ffdd | 7777 | { |
1b9f0c97 L |
7778 | /* If there is an extension opcode to put here, the |
7779 | register number must be put into the regmem field. */ | |
7780 | if (i.tm.extension_opcode != None) | |
7781 | { | |
7782 | i.rm.regmem = i.op[op].regs->reg_num; | |
7783 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7784 | i.rex |= REX_B; | |
43234a1e L |
7785 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7786 | i.vrex |= REX_B; | |
1b9f0c97 L |
7787 | } |
7788 | else | |
7789 | { | |
7790 | i.rm.reg = i.op[op].regs->reg_num; | |
7791 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7792 | i.rex |= REX_R; | |
43234a1e L |
7793 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7794 | i.vrex |= REX_R; | |
1b9f0c97 | 7795 | } |
7ab9ffdd | 7796 | } |
252b5132 | 7797 | |
29b0f896 AM |
7798 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
7799 | must set it to 3 to indicate this is a register operand | |
7800 | in the regmem field. */ | |
7801 | if (!i.mem_operands) | |
7802 | i.rm.mode = 3; | |
7803 | } | |
252b5132 | 7804 | |
29b0f896 | 7805 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 7806 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
7807 | i.rm.reg = i.tm.extension_opcode; |
7808 | } | |
7809 | return default_seg; | |
7810 | } | |
252b5132 | 7811 | |
29b0f896 | 7812 | static void |
e3bb37b5 | 7813 | output_branch (void) |
29b0f896 AM |
7814 | { |
7815 | char *p; | |
f8a5c266 | 7816 | int size; |
29b0f896 AM |
7817 | int code16; |
7818 | int prefix; | |
7819 | relax_substateT subtype; | |
7820 | symbolS *sym; | |
7821 | offsetT off; | |
7822 | ||
f8a5c266 | 7823 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
a501d77e | 7824 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
29b0f896 AM |
7825 | |
7826 | prefix = 0; | |
7827 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 7828 | { |
29b0f896 AM |
7829 | prefix = 1; |
7830 | i.prefixes -= 1; | |
7831 | code16 ^= CODE16; | |
252b5132 | 7832 | } |
29b0f896 AM |
7833 | /* Pentium4 branch hints. */ |
7834 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
7835 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 7836 | { |
29b0f896 AM |
7837 | prefix++; |
7838 | i.prefixes--; | |
7839 | } | |
7840 | if (i.prefix[REX_PREFIX] != 0) | |
7841 | { | |
7842 | prefix++; | |
7843 | i.prefixes--; | |
2f66722d AM |
7844 | } |
7845 | ||
7e8b059b L |
7846 | /* BND prefixed jump. */ |
7847 | if (i.prefix[BND_PREFIX] != 0) | |
7848 | { | |
7849 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
7850 | i.prefixes -= 1; | |
7851 | } | |
7852 | ||
29b0f896 AM |
7853 | if (i.prefixes != 0 && !intel_syntax) |
7854 | as_warn (_("skipping prefixes on this instruction")); | |
7855 | ||
7856 | /* It's always a symbol; End frag & setup for relax. | |
7857 | Make sure there is enough room in this frag for the largest | |
7858 | instruction we may generate in md_convert_frag. This is 2 | |
7859 | bytes for the opcode and room for the prefix and largest | |
7860 | displacement. */ | |
7861 | frag_grow (prefix + 2 + 4); | |
7862 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
7863 | p = frag_more (prefix + 1); | |
7864 | if (i.prefix[DATA_PREFIX] != 0) | |
7865 | *p++ = DATA_PREFIX_OPCODE; | |
7866 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
7867 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
7868 | *p++ = i.prefix[SEG_PREFIX]; | |
7869 | if (i.prefix[REX_PREFIX] != 0) | |
7870 | *p++ = i.prefix[REX_PREFIX]; | |
7871 | *p = i.tm.base_opcode; | |
7872 | ||
7873 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 7874 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 7875 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 7876 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 7877 | else |
f8a5c266 | 7878 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 7879 | subtype |= code16; |
3e73aa7c | 7880 | |
29b0f896 AM |
7881 | sym = i.op[0].disps->X_add_symbol; |
7882 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 7883 | |
29b0f896 AM |
7884 | if (i.op[0].disps->X_op != O_constant |
7885 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 7886 | { |
29b0f896 AM |
7887 | /* Handle complex expressions. */ |
7888 | sym = make_expr_symbol (i.op[0].disps); | |
7889 | off = 0; | |
7890 | } | |
3e73aa7c | 7891 | |
29b0f896 AM |
7892 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
7893 | Pass reloc in fr_var. */ | |
d258b828 | 7894 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 7895 | } |
3e73aa7c | 7896 | |
bd7ab16b L |
7897 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7898 | /* Return TRUE iff PLT32 relocation should be used for branching to | |
7899 | symbol S. */ | |
7900 | ||
7901 | static bfd_boolean | |
7902 | need_plt32_p (symbolS *s) | |
7903 | { | |
7904 | /* PLT32 relocation is ELF only. */ | |
7905 | if (!IS_ELF) | |
7906 | return FALSE; | |
7907 | ||
a5def729 RO |
7908 | #ifdef TE_SOLARIS |
7909 | /* Don't emit PLT32 relocation on Solaris: neither native linker nor | |
7910 | krtld support it. */ | |
7911 | return FALSE; | |
7912 | #endif | |
7913 | ||
bd7ab16b L |
7914 | /* Since there is no need to prepare for PLT branch on x86-64, we |
7915 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can | |
7916 | be used as a marker for 32-bit PC-relative branches. */ | |
7917 | if (!object_64bit) | |
7918 | return FALSE; | |
7919 | ||
7920 | /* Weak or undefined symbol need PLT32 relocation. */ | |
7921 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) | |
7922 | return TRUE; | |
7923 | ||
7924 | /* Non-global symbol doesn't need PLT32 relocation. */ | |
7925 | if (! S_IS_EXTERNAL (s)) | |
7926 | return FALSE; | |
7927 | ||
7928 | /* Other global symbols need PLT32 relocation. NB: Symbol with | |
7929 | non-default visibilities are treated as normal global symbol | |
7930 | so that PLT32 relocation can be used as a marker for 32-bit | |
7931 | PC-relative branches. It is useful for linker relaxation. */ | |
7932 | return TRUE; | |
7933 | } | |
7934 | #endif | |
7935 | ||
29b0f896 | 7936 | static void |
e3bb37b5 | 7937 | output_jump (void) |
29b0f896 AM |
7938 | { |
7939 | char *p; | |
7940 | int size; | |
3e02c1cc | 7941 | fixS *fixP; |
bd7ab16b | 7942 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
29b0f896 | 7943 | |
40fb9820 | 7944 | if (i.tm.opcode_modifier.jumpbyte) |
29b0f896 AM |
7945 | { |
7946 | /* This is a loop or jecxz type instruction. */ | |
7947 | size = 1; | |
7948 | if (i.prefix[ADDR_PREFIX] != 0) | |
7949 | { | |
7950 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
7951 | i.prefixes -= 1; | |
7952 | } | |
7953 | /* Pentium4 branch hints. */ | |
7954 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
7955 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
7956 | { | |
7957 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
7958 | i.prefixes--; | |
3e73aa7c JH |
7959 | } |
7960 | } | |
29b0f896 AM |
7961 | else |
7962 | { | |
7963 | int code16; | |
3e73aa7c | 7964 | |
29b0f896 AM |
7965 | code16 = 0; |
7966 | if (flag_code == CODE_16BIT) | |
7967 | code16 = CODE16; | |
3e73aa7c | 7968 | |
29b0f896 AM |
7969 | if (i.prefix[DATA_PREFIX] != 0) |
7970 | { | |
7971 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
7972 | i.prefixes -= 1; | |
7973 | code16 ^= CODE16; | |
7974 | } | |
252b5132 | 7975 | |
29b0f896 AM |
7976 | size = 4; |
7977 | if (code16) | |
7978 | size = 2; | |
7979 | } | |
9fcc94b6 | 7980 | |
29b0f896 AM |
7981 | if (i.prefix[REX_PREFIX] != 0) |
7982 | { | |
7983 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
7984 | i.prefixes -= 1; | |
7985 | } | |
252b5132 | 7986 | |
7e8b059b L |
7987 | /* BND prefixed jump. */ |
7988 | if (i.prefix[BND_PREFIX] != 0) | |
7989 | { | |
7990 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
7991 | i.prefixes -= 1; | |
7992 | } | |
7993 | ||
29b0f896 AM |
7994 | if (i.prefixes != 0 && !intel_syntax) |
7995 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 7996 | |
42164a71 L |
7997 | p = frag_more (i.tm.opcode_length + size); |
7998 | switch (i.tm.opcode_length) | |
7999 | { | |
8000 | case 2: | |
8001 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 8002 | /* Fall through. */ |
42164a71 L |
8003 | case 1: |
8004 | *p++ = i.tm.base_opcode; | |
8005 | break; | |
8006 | default: | |
8007 | abort (); | |
8008 | } | |
e0890092 | 8009 | |
bd7ab16b L |
8010 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8011 | if (size == 4 | |
8012 | && jump_reloc == NO_RELOC | |
8013 | && need_plt32_p (i.op[0].disps->X_add_symbol)) | |
8014 | jump_reloc = BFD_RELOC_X86_64_PLT32; | |
8015 | #endif | |
8016 | ||
8017 | jump_reloc = reloc (size, 1, 1, jump_reloc); | |
8018 | ||
3e02c1cc | 8019 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
bd7ab16b | 8020 | i.op[0].disps, 1, jump_reloc); |
3e02c1cc AM |
8021 | |
8022 | /* All jumps handled here are signed, but don't use a signed limit | |
8023 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
8024 | 4G and 64k respectively. */ | |
8025 | if (size == 1) | |
8026 | fixP->fx_signed = 1; | |
29b0f896 | 8027 | } |
e0890092 | 8028 | |
29b0f896 | 8029 | static void |
e3bb37b5 | 8030 | output_interseg_jump (void) |
29b0f896 AM |
8031 | { |
8032 | char *p; | |
8033 | int size; | |
8034 | int prefix; | |
8035 | int code16; | |
252b5132 | 8036 | |
29b0f896 AM |
8037 | code16 = 0; |
8038 | if (flag_code == CODE_16BIT) | |
8039 | code16 = CODE16; | |
a217f122 | 8040 | |
29b0f896 AM |
8041 | prefix = 0; |
8042 | if (i.prefix[DATA_PREFIX] != 0) | |
8043 | { | |
8044 | prefix = 1; | |
8045 | i.prefixes -= 1; | |
8046 | code16 ^= CODE16; | |
8047 | } | |
8048 | if (i.prefix[REX_PREFIX] != 0) | |
8049 | { | |
8050 | prefix++; | |
8051 | i.prefixes -= 1; | |
8052 | } | |
252b5132 | 8053 | |
29b0f896 AM |
8054 | size = 4; |
8055 | if (code16) | |
8056 | size = 2; | |
252b5132 | 8057 | |
29b0f896 AM |
8058 | if (i.prefixes != 0 && !intel_syntax) |
8059 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 8060 | |
29b0f896 AM |
8061 | /* 1 opcode; 2 segment; offset */ |
8062 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 8063 | |
29b0f896 AM |
8064 | if (i.prefix[DATA_PREFIX] != 0) |
8065 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 8066 | |
29b0f896 AM |
8067 | if (i.prefix[REX_PREFIX] != 0) |
8068 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 8069 | |
29b0f896 AM |
8070 | *p++ = i.tm.base_opcode; |
8071 | if (i.op[1].imms->X_op == O_constant) | |
8072 | { | |
8073 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 8074 | |
29b0f896 AM |
8075 | if (size == 2 |
8076 | && !fits_in_unsigned_word (n) | |
8077 | && !fits_in_signed_word (n)) | |
8078 | { | |
8079 | as_bad (_("16-bit jump out of range")); | |
8080 | return; | |
8081 | } | |
8082 | md_number_to_chars (p, n, size); | |
8083 | } | |
8084 | else | |
8085 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 8086 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
29b0f896 AM |
8087 | if (i.op[0].imms->X_op != O_constant) |
8088 | as_bad (_("can't handle non absolute segment in `%s'"), | |
8089 | i.tm.name); | |
8090 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
8091 | } | |
a217f122 | 8092 | |
b4a3a7b4 L |
8093 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8094 | void | |
8095 | x86_cleanup (void) | |
8096 | { | |
8097 | char *p; | |
8098 | asection *seg = now_seg; | |
8099 | subsegT subseg = now_subseg; | |
8100 | asection *sec; | |
8101 | unsigned int alignment, align_size_1; | |
8102 | unsigned int isa_1_descsz, feature_2_descsz, descsz; | |
8103 | unsigned int isa_1_descsz_raw, feature_2_descsz_raw; | |
8104 | unsigned int padding; | |
8105 | ||
8106 | if (!IS_ELF || !x86_used_note) | |
8107 | return; | |
8108 | ||
b4a3a7b4 L |
8109 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86; |
8110 | ||
8111 | /* The .note.gnu.property section layout: | |
8112 | ||
8113 | Field Length Contents | |
8114 | ---- ---- ---- | |
8115 | n_namsz 4 4 | |
8116 | n_descsz 4 The note descriptor size | |
8117 | n_type 4 NT_GNU_PROPERTY_TYPE_0 | |
8118 | n_name 4 "GNU" | |
8119 | n_desc n_descsz The program property array | |
8120 | .... .... .... | |
8121 | */ | |
8122 | ||
8123 | /* Create the .note.gnu.property section. */ | |
8124 | sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0); | |
fd361982 | 8125 | bfd_set_section_flags (sec, |
b4a3a7b4 L |
8126 | (SEC_ALLOC |
8127 | | SEC_LOAD | |
8128 | | SEC_DATA | |
8129 | | SEC_HAS_CONTENTS | |
8130 | | SEC_READONLY)); | |
8131 | ||
8132 | if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64) | |
8133 | { | |
8134 | align_size_1 = 7; | |
8135 | alignment = 3; | |
8136 | } | |
8137 | else | |
8138 | { | |
8139 | align_size_1 = 3; | |
8140 | alignment = 2; | |
8141 | } | |
8142 | ||
fd361982 | 8143 | bfd_set_section_alignment (sec, alignment); |
b4a3a7b4 L |
8144 | elf_section_type (sec) = SHT_NOTE; |
8145 | ||
8146 | /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size | |
8147 | + 4-byte data */ | |
8148 | isa_1_descsz_raw = 4 + 4 + 4; | |
8149 | /* Align GNU_PROPERTY_X86_ISA_1_USED. */ | |
8150 | isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1; | |
8151 | ||
8152 | feature_2_descsz_raw = isa_1_descsz; | |
8153 | /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size | |
8154 | + 4-byte data */ | |
8155 | feature_2_descsz_raw += 4 + 4 + 4; | |
8156 | /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
8157 | feature_2_descsz = ((feature_2_descsz_raw + align_size_1) | |
8158 | & ~align_size_1); | |
8159 | ||
8160 | descsz = feature_2_descsz; | |
8161 | /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */ | |
8162 | p = frag_more (4 + 4 + 4 + 4 + descsz); | |
8163 | ||
8164 | /* Write n_namsz. */ | |
8165 | md_number_to_chars (p, (valueT) 4, 4); | |
8166 | ||
8167 | /* Write n_descsz. */ | |
8168 | md_number_to_chars (p + 4, (valueT) descsz, 4); | |
8169 | ||
8170 | /* Write n_type. */ | |
8171 | md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4); | |
8172 | ||
8173 | /* Write n_name. */ | |
8174 | memcpy (p + 4 * 3, "GNU", 4); | |
8175 | ||
8176 | /* Write 4-byte type. */ | |
8177 | md_number_to_chars (p + 4 * 4, | |
8178 | (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4); | |
8179 | ||
8180 | /* Write 4-byte data size. */ | |
8181 | md_number_to_chars (p + 4 * 5, (valueT) 4, 4); | |
8182 | ||
8183 | /* Write 4-byte data. */ | |
8184 | md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4); | |
8185 | ||
8186 | /* Zero out paddings. */ | |
8187 | padding = isa_1_descsz - isa_1_descsz_raw; | |
8188 | if (padding) | |
8189 | memset (p + 4 * 7, 0, padding); | |
8190 | ||
8191 | /* Write 4-byte type. */ | |
8192 | md_number_to_chars (p + isa_1_descsz + 4 * 4, | |
8193 | (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4); | |
8194 | ||
8195 | /* Write 4-byte data size. */ | |
8196 | md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4); | |
8197 | ||
8198 | /* Write 4-byte data. */ | |
8199 | md_number_to_chars (p + isa_1_descsz + 4 * 6, | |
8200 | (valueT) x86_feature_2_used, 4); | |
8201 | ||
8202 | /* Zero out paddings. */ | |
8203 | padding = feature_2_descsz - feature_2_descsz_raw; | |
8204 | if (padding) | |
8205 | memset (p + isa_1_descsz + 4 * 7, 0, padding); | |
8206 | ||
8207 | /* We probably can't restore the current segment, for there likely | |
8208 | isn't one yet... */ | |
8209 | if (seg && subseg) | |
8210 | subseg_set (seg, subseg); | |
8211 | } | |
8212 | #endif | |
8213 | ||
9c33702b JB |
8214 | static unsigned int |
8215 | encoding_length (const fragS *start_frag, offsetT start_off, | |
8216 | const char *frag_now_ptr) | |
8217 | { | |
8218 | unsigned int len = 0; | |
8219 | ||
8220 | if (start_frag != frag_now) | |
8221 | { | |
8222 | const fragS *fr = start_frag; | |
8223 | ||
8224 | do { | |
8225 | len += fr->fr_fix; | |
8226 | fr = fr->fr_next; | |
8227 | } while (fr && fr != frag_now); | |
8228 | } | |
8229 | ||
8230 | return len - start_off + (frag_now_ptr - frag_now->fr_literal); | |
8231 | } | |
8232 | ||
29b0f896 | 8233 | static void |
e3bb37b5 | 8234 | output_insn (void) |
29b0f896 | 8235 | { |
2bbd9c25 JJ |
8236 | fragS *insn_start_frag; |
8237 | offsetT insn_start_off; | |
8238 | ||
b4a3a7b4 L |
8239 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8240 | if (IS_ELF && x86_used_note) | |
8241 | { | |
8242 | if (i.tm.cpu_flags.bitfield.cpucmov) | |
8243 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_CMOV; | |
8244 | if (i.tm.cpu_flags.bitfield.cpusse) | |
8245 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE; | |
8246 | if (i.tm.cpu_flags.bitfield.cpusse2) | |
8247 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE2; | |
8248 | if (i.tm.cpu_flags.bitfield.cpusse3) | |
8249 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE3; | |
8250 | if (i.tm.cpu_flags.bitfield.cpussse3) | |
8251 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSSE3; | |
8252 | if (i.tm.cpu_flags.bitfield.cpusse4_1) | |
8253 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_1; | |
8254 | if (i.tm.cpu_flags.bitfield.cpusse4_2) | |
8255 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_2; | |
8256 | if (i.tm.cpu_flags.bitfield.cpuavx) | |
8257 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX; | |
8258 | if (i.tm.cpu_flags.bitfield.cpuavx2) | |
8259 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX2; | |
8260 | if (i.tm.cpu_flags.bitfield.cpufma) | |
8261 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_FMA; | |
8262 | if (i.tm.cpu_flags.bitfield.cpuavx512f) | |
8263 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512F; | |
8264 | if (i.tm.cpu_flags.bitfield.cpuavx512cd) | |
8265 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512CD; | |
8266 | if (i.tm.cpu_flags.bitfield.cpuavx512er) | |
8267 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512ER; | |
8268 | if (i.tm.cpu_flags.bitfield.cpuavx512pf) | |
8269 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512PF; | |
8270 | if (i.tm.cpu_flags.bitfield.cpuavx512vl) | |
8271 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512VL; | |
8272 | if (i.tm.cpu_flags.bitfield.cpuavx512dq) | |
8273 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512DQ; | |
8274 | if (i.tm.cpu_flags.bitfield.cpuavx512bw) | |
8275 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512BW; | |
8276 | if (i.tm.cpu_flags.bitfield.cpuavx512_4fmaps) | |
8277 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS; | |
8278 | if (i.tm.cpu_flags.bitfield.cpuavx512_4vnniw) | |
8279 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW; | |
8280 | if (i.tm.cpu_flags.bitfield.cpuavx512_bitalg) | |
8281 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG; | |
8282 | if (i.tm.cpu_flags.bitfield.cpuavx512ifma) | |
8283 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA; | |
8284 | if (i.tm.cpu_flags.bitfield.cpuavx512vbmi) | |
8285 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI; | |
8286 | if (i.tm.cpu_flags.bitfield.cpuavx512_vbmi2) | |
8287 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2; | |
8288 | if (i.tm.cpu_flags.bitfield.cpuavx512_vnni) | |
8289 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI; | |
462cac58 L |
8290 | if (i.tm.cpu_flags.bitfield.cpuavx512_bf16) |
8291 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BF16; | |
b4a3a7b4 L |
8292 | |
8293 | if (i.tm.cpu_flags.bitfield.cpu8087 | |
8294 | || i.tm.cpu_flags.bitfield.cpu287 | |
8295 | || i.tm.cpu_flags.bitfield.cpu387 | |
8296 | || i.tm.cpu_flags.bitfield.cpu687 | |
8297 | || i.tm.cpu_flags.bitfield.cpufisttp) | |
8298 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87; | |
8299 | /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor | |
8300 | Xfence instructions. */ | |
8301 | if (i.tm.base_opcode != 0xf18 | |
8302 | && i.tm.base_opcode != 0xf0d | |
c3949f43 | 8303 | && i.tm.base_opcode != 0xfaef8 |
b4a3a7b4 L |
8304 | && (i.has_regmmx |
8305 | || i.tm.cpu_flags.bitfield.cpummx | |
8306 | || i.tm.cpu_flags.bitfield.cpua3dnow | |
8307 | || i.tm.cpu_flags.bitfield.cpua3dnowa)) | |
8308 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX; | |
8309 | if (i.has_regxmm) | |
8310 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM; | |
8311 | if (i.has_regymm) | |
8312 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM; | |
8313 | if (i.has_regzmm) | |
8314 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM; | |
8315 | if (i.tm.cpu_flags.bitfield.cpufxsr) | |
8316 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR; | |
8317 | if (i.tm.cpu_flags.bitfield.cpuxsave) | |
8318 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE; | |
8319 | if (i.tm.cpu_flags.bitfield.cpuxsaveopt) | |
8320 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT; | |
8321 | if (i.tm.cpu_flags.bitfield.cpuxsavec) | |
8322 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC; | |
8323 | } | |
8324 | #endif | |
8325 | ||
29b0f896 AM |
8326 | /* Tie dwarf2 debug info to the address at the start of the insn. |
8327 | We can't do this after the insn has been output as the current | |
8328 | frag may have been closed off. eg. by frag_var. */ | |
8329 | dwarf2_emit_insn (0); | |
8330 | ||
2bbd9c25 JJ |
8331 | insn_start_frag = frag_now; |
8332 | insn_start_off = frag_now_fix (); | |
8333 | ||
29b0f896 | 8334 | /* Output jumps. */ |
40fb9820 | 8335 | if (i.tm.opcode_modifier.jump) |
29b0f896 | 8336 | output_branch (); |
40fb9820 L |
8337 | else if (i.tm.opcode_modifier.jumpbyte |
8338 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 | 8339 | output_jump (); |
40fb9820 | 8340 | else if (i.tm.opcode_modifier.jumpintersegment) |
29b0f896 AM |
8341 | output_interseg_jump (); |
8342 | else | |
8343 | { | |
8344 | /* Output normal instructions here. */ | |
8345 | char *p; | |
8346 | unsigned char *q; | |
47465058 | 8347 | unsigned int j; |
331d2d0d | 8348 | unsigned int prefix; |
4dffcebc | 8349 | |
e4e00185 | 8350 | if (avoid_fence |
c3949f43 JB |
8351 | && (i.tm.base_opcode == 0xfaee8 |
8352 | || i.tm.base_opcode == 0xfaef0 | |
8353 | || i.tm.base_opcode == 0xfaef8)) | |
e4e00185 AS |
8354 | { |
8355 | /* Encode lfence, mfence, and sfence as | |
8356 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
8357 | offsetT val = 0x240483f0ULL; | |
8358 | p = frag_more (5); | |
8359 | md_number_to_chars (p, val, 5); | |
8360 | return; | |
8361 | } | |
8362 | ||
d022bddd IT |
8363 | /* Some processors fail on LOCK prefix. This options makes |
8364 | assembler ignore LOCK prefix and serves as a workaround. */ | |
8365 | if (omit_lock_prefix) | |
8366 | { | |
8367 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE) | |
8368 | return; | |
8369 | i.prefix[LOCK_PREFIX] = 0; | |
8370 | } | |
8371 | ||
43234a1e L |
8372 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
8373 | don't need the explicit prefix. */ | |
8374 | if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) | |
bc4bd9ab | 8375 | { |
c0f3af97 | 8376 | switch (i.tm.opcode_length) |
bc4bd9ab | 8377 | { |
c0f3af97 L |
8378 | case 3: |
8379 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 8380 | { |
c0f3af97 | 8381 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
c3949f43 JB |
8382 | if (!i.tm.cpu_flags.bitfield.cpupadlock |
8383 | || prefix != REPE_PREFIX_OPCODE | |
8384 | || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE)) | |
8385 | add_prefix (prefix); | |
c0f3af97 L |
8386 | } |
8387 | break; | |
8388 | case 2: | |
8389 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
8390 | { | |
8391 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
c3949f43 | 8392 | add_prefix (prefix); |
4dffcebc | 8393 | } |
c0f3af97 L |
8394 | break; |
8395 | case 1: | |
8396 | break; | |
390c91cf L |
8397 | case 0: |
8398 | /* Check for pseudo prefixes. */ | |
8399 | as_bad_where (insn_start_frag->fr_file, | |
8400 | insn_start_frag->fr_line, | |
8401 | _("pseudo prefix without instruction")); | |
8402 | return; | |
c0f3af97 L |
8403 | default: |
8404 | abort (); | |
bc4bd9ab | 8405 | } |
c0f3af97 | 8406 | |
6d19a37a | 8407 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
8408 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
8409 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
8410 | perform IE->LE optimization. */ | |
8411 | if (x86_elf_abi == X86_64_X32_ABI | |
8412 | && i.operands == 2 | |
8413 | && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF | |
8414 | && i.prefix[REX_PREFIX] == 0) | |
8415 | add_prefix (REX_OPCODE); | |
6d19a37a | 8416 | #endif |
cf61b747 | 8417 | |
c0f3af97 L |
8418 | /* The prefix bytes. */ |
8419 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
8420 | if (*q) | |
8421 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 8422 | } |
ae5c1c7b | 8423 | else |
c0f3af97 L |
8424 | { |
8425 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
8426 | if (*q) | |
8427 | switch (j) | |
8428 | { | |
8429 | case REX_PREFIX: | |
8430 | /* REX byte is encoded in VEX prefix. */ | |
8431 | break; | |
8432 | case SEG_PREFIX: | |
8433 | case ADDR_PREFIX: | |
8434 | FRAG_APPEND_1_CHAR (*q); | |
8435 | break; | |
8436 | default: | |
8437 | /* There should be no other prefixes for instructions | |
8438 | with VEX prefix. */ | |
8439 | abort (); | |
8440 | } | |
8441 | ||
43234a1e L |
8442 | /* For EVEX instructions i.vrex should become 0 after |
8443 | build_evex_prefix. For VEX instructions upper 16 registers | |
8444 | aren't available, so VREX should be 0. */ | |
8445 | if (i.vrex) | |
8446 | abort (); | |
c0f3af97 L |
8447 | /* Now the VEX prefix. */ |
8448 | p = frag_more (i.vex.length); | |
8449 | for (j = 0; j < i.vex.length; j++) | |
8450 | p[j] = i.vex.bytes[j]; | |
8451 | } | |
252b5132 | 8452 | |
29b0f896 | 8453 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 8454 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
8455 | { |
8456 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
8457 | } | |
8458 | else | |
8459 | { | |
4dffcebc | 8460 | switch (i.tm.opcode_length) |
331d2d0d | 8461 | { |
43234a1e L |
8462 | case 4: |
8463 | p = frag_more (4); | |
8464 | *p++ = (i.tm.base_opcode >> 24) & 0xff; | |
8465 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
8466 | break; | |
4dffcebc | 8467 | case 3: |
331d2d0d L |
8468 | p = frag_more (3); |
8469 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
8470 | break; |
8471 | case 2: | |
8472 | p = frag_more (2); | |
8473 | break; | |
8474 | default: | |
8475 | abort (); | |
8476 | break; | |
331d2d0d | 8477 | } |
0f10071e | 8478 | |
29b0f896 AM |
8479 | /* Put out high byte first: can't use md_number_to_chars! */ |
8480 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
8481 | *p = i.tm.base_opcode & 0xff; | |
8482 | } | |
3e73aa7c | 8483 | |
29b0f896 | 8484 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 8485 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 8486 | { |
4a3523fa L |
8487 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
8488 | | i.rm.reg << 3 | |
8489 | | i.rm.mode << 6)); | |
29b0f896 AM |
8490 | /* If i.rm.regmem == ESP (4) |
8491 | && i.rm.mode != (Register mode) | |
8492 | && not 16 bit | |
8493 | ==> need second modrm byte. */ | |
8494 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
8495 | && i.rm.mode != 3 | |
dc821c5f | 8496 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
4a3523fa L |
8497 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
8498 | | i.sib.index << 3 | |
8499 | | i.sib.scale << 6)); | |
29b0f896 | 8500 | } |
3e73aa7c | 8501 | |
29b0f896 | 8502 | if (i.disp_operands) |
2bbd9c25 | 8503 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 8504 | |
29b0f896 | 8505 | if (i.imm_operands) |
2bbd9c25 | 8506 | output_imm (insn_start_frag, insn_start_off); |
9c33702b JB |
8507 | |
8508 | /* | |
8509 | * frag_now_fix () returning plain abs_section_offset when we're in the | |
8510 | * absolute section, and abs_section_offset not getting updated as data | |
8511 | * gets added to the frag breaks the logic below. | |
8512 | */ | |
8513 | if (now_seg != absolute_section) | |
8514 | { | |
8515 | j = encoding_length (insn_start_frag, insn_start_off, frag_more (0)); | |
8516 | if (j > 15) | |
8517 | as_warn (_("instruction length of %u bytes exceeds the limit of 15"), | |
8518 | j); | |
8519 | } | |
29b0f896 | 8520 | } |
252b5132 | 8521 | |
29b0f896 AM |
8522 | #ifdef DEBUG386 |
8523 | if (flag_debug) | |
8524 | { | |
7b81dfbb | 8525 | pi ("" /*line*/, &i); |
29b0f896 AM |
8526 | } |
8527 | #endif /* DEBUG386 */ | |
8528 | } | |
252b5132 | 8529 | |
e205caa7 L |
8530 | /* Return the size of the displacement operand N. */ |
8531 | ||
8532 | static int | |
8533 | disp_size (unsigned int n) | |
8534 | { | |
8535 | int size = 4; | |
43234a1e | 8536 | |
b5014f7a | 8537 | if (i.types[n].bitfield.disp64) |
40fb9820 L |
8538 | size = 8; |
8539 | else if (i.types[n].bitfield.disp8) | |
8540 | size = 1; | |
8541 | else if (i.types[n].bitfield.disp16) | |
8542 | size = 2; | |
e205caa7 L |
8543 | return size; |
8544 | } | |
8545 | ||
8546 | /* Return the size of the immediate operand N. */ | |
8547 | ||
8548 | static int | |
8549 | imm_size (unsigned int n) | |
8550 | { | |
8551 | int size = 4; | |
40fb9820 L |
8552 | if (i.types[n].bitfield.imm64) |
8553 | size = 8; | |
8554 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
8555 | size = 1; | |
8556 | else if (i.types[n].bitfield.imm16) | |
8557 | size = 2; | |
e205caa7 L |
8558 | return size; |
8559 | } | |
8560 | ||
29b0f896 | 8561 | static void |
64e74474 | 8562 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
8563 | { |
8564 | char *p; | |
8565 | unsigned int n; | |
252b5132 | 8566 | |
29b0f896 AM |
8567 | for (n = 0; n < i.operands; n++) |
8568 | { | |
b5014f7a | 8569 | if (operand_type_check (i.types[n], disp)) |
29b0f896 AM |
8570 | { |
8571 | if (i.op[n].disps->X_op == O_constant) | |
8572 | { | |
e205caa7 | 8573 | int size = disp_size (n); |
43234a1e | 8574 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 8575 | |
629cfaf1 JB |
8576 | val = offset_in_range (val >> (size == 1 ? i.memshift : 0), |
8577 | size); | |
29b0f896 AM |
8578 | p = frag_more (size); |
8579 | md_number_to_chars (p, val, size); | |
8580 | } | |
8581 | else | |
8582 | { | |
f86103b7 | 8583 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 8584 | int size = disp_size (n); |
40fb9820 | 8585 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 | 8586 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
02a86693 | 8587 | fixS *fixP; |
29b0f896 | 8588 | |
e205caa7 | 8589 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 8590 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 8591 | |
29b0f896 AM |
8592 | /* The PC relative address is computed relative |
8593 | to the instruction boundary, so in case immediate | |
8594 | fields follows, we need to adjust the value. */ | |
8595 | if (pcrel && i.imm_operands) | |
8596 | { | |
29b0f896 | 8597 | unsigned int n1; |
e205caa7 | 8598 | int sz = 0; |
252b5132 | 8599 | |
29b0f896 | 8600 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 8601 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 8602 | { |
e205caa7 L |
8603 | /* Only one immediate is allowed for PC |
8604 | relative address. */ | |
9c2799c2 | 8605 | gas_assert (sz == 0); |
e205caa7 L |
8606 | sz = imm_size (n1); |
8607 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 8608 | } |
29b0f896 | 8609 | /* We should find the immediate. */ |
9c2799c2 | 8610 | gas_assert (sz != 0); |
29b0f896 | 8611 | } |
520dc8e8 | 8612 | |
29b0f896 | 8613 | p = frag_more (size); |
d258b828 | 8614 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 8615 | if (GOT_symbol |
2bbd9c25 | 8616 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 8617 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
8618 | || reloc_type == BFD_RELOC_X86_64_32S |
8619 | || (reloc_type == BFD_RELOC_64 | |
8620 | && object_64bit)) | |
d6ab8113 JB |
8621 | && (i.op[n].disps->X_op == O_symbol |
8622 | || (i.op[n].disps->X_op == O_add | |
8623 | && ((symbol_get_value_expression | |
8624 | (i.op[n].disps->X_op_symbol)->X_op) | |
8625 | == O_subtract)))) | |
8626 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 | 8627 | { |
4fa24527 | 8628 | if (!object_64bit) |
7b81dfbb AJ |
8629 | { |
8630 | reloc_type = BFD_RELOC_386_GOTPC; | |
d583596c JB |
8631 | i.op[n].imms->X_add_number += |
8632 | encoding_length (insn_start_frag, insn_start_off, p); | |
7b81dfbb AJ |
8633 | } |
8634 | else if (reloc_type == BFD_RELOC_64) | |
8635 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 8636 | else |
7b81dfbb AJ |
8637 | /* Don't do the adjustment for x86-64, as there |
8638 | the pcrel addressing is relative to the _next_ | |
8639 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 8640 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 8641 | } |
02a86693 L |
8642 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
8643 | size, i.op[n].disps, pcrel, | |
8644 | reloc_type); | |
8645 | /* Check for "call/jmp *mem", "mov mem, %reg", | |
8646 | "test %reg, mem" and "binop mem, %reg" where binop | |
8647 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
e60f4d3b L |
8648 | instructions without data prefix. Always generate |
8649 | R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */ | |
8650 | if (i.prefix[DATA_PREFIX] == 0 | |
8651 | && (generate_relax_relocations | |
8652 | || (!object_64bit | |
8653 | && i.rm.mode == 0 | |
8654 | && i.rm.regmem == 5)) | |
0cb4071e L |
8655 | && (i.rm.mode == 2 |
8656 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
02a86693 L |
8657 | && ((i.operands == 1 |
8658 | && i.tm.base_opcode == 0xff | |
8659 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
8660 | || (i.operands == 2 | |
8661 | && (i.tm.base_opcode == 0x8b | |
8662 | || i.tm.base_opcode == 0x85 | |
8663 | || (i.tm.base_opcode & 0xc7) == 0x03)))) | |
8664 | { | |
8665 | if (object_64bit) | |
8666 | { | |
8667 | fixP->fx_tcbit = i.rex != 0; | |
8668 | if (i.base_reg | |
e968fc9b | 8669 | && (i.base_reg->reg_num == RegIP)) |
02a86693 L |
8670 | fixP->fx_tcbit2 = 1; |
8671 | } | |
8672 | else | |
8673 | fixP->fx_tcbit2 = 1; | |
8674 | } | |
29b0f896 AM |
8675 | } |
8676 | } | |
8677 | } | |
8678 | } | |
252b5132 | 8679 | |
29b0f896 | 8680 | static void |
64e74474 | 8681 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
8682 | { |
8683 | char *p; | |
8684 | unsigned int n; | |
252b5132 | 8685 | |
29b0f896 AM |
8686 | for (n = 0; n < i.operands; n++) |
8687 | { | |
43234a1e L |
8688 | /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ |
8689 | if (i.rounding && (int) n == i.rounding->operand) | |
8690 | continue; | |
8691 | ||
40fb9820 | 8692 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
8693 | { |
8694 | if (i.op[n].imms->X_op == O_constant) | |
8695 | { | |
e205caa7 | 8696 | int size = imm_size (n); |
29b0f896 | 8697 | offsetT val; |
b4cac588 | 8698 | |
29b0f896 AM |
8699 | val = offset_in_range (i.op[n].imms->X_add_number, |
8700 | size); | |
8701 | p = frag_more (size); | |
8702 | md_number_to_chars (p, val, size); | |
8703 | } | |
8704 | else | |
8705 | { | |
8706 | /* Not absolute_section. | |
8707 | Need a 32-bit fixup (don't support 8bit | |
8708 | non-absolute imms). Try to support other | |
8709 | sizes ... */ | |
f86103b7 | 8710 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
8711 | int size = imm_size (n); |
8712 | int sign; | |
29b0f896 | 8713 | |
40fb9820 | 8714 | if (i.types[n].bitfield.imm32s |
a7d61044 | 8715 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 8716 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 8717 | sign = 1; |
e205caa7 L |
8718 | else |
8719 | sign = 0; | |
520dc8e8 | 8720 | |
29b0f896 | 8721 | p = frag_more (size); |
d258b828 | 8722 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 8723 | |
2bbd9c25 JJ |
8724 | /* This is tough to explain. We end up with this one if we |
8725 | * have operands that look like | |
8726 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
8727 | * obtain the absolute address of the GOT, and it is strongly | |
8728 | * preferable from a performance point of view to avoid using | |
8729 | * a runtime relocation for this. The actual sequence of | |
8730 | * instructions often look something like: | |
8731 | * | |
8732 | * call .L66 | |
8733 | * .L66: | |
8734 | * popl %ebx | |
8735 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
8736 | * | |
8737 | * The call and pop essentially return the absolute address | |
8738 | * of the label .L66 and store it in %ebx. The linker itself | |
8739 | * will ultimately change the first operand of the addl so | |
8740 | * that %ebx points to the GOT, but to keep things simple, the | |
8741 | * .o file must have this operand set so that it generates not | |
8742 | * the absolute address of .L66, but the absolute address of | |
8743 | * itself. This allows the linker itself simply treat a GOTPC | |
8744 | * relocation as asking for a pcrel offset to the GOT to be | |
8745 | * added in, and the addend of the relocation is stored in the | |
8746 | * operand field for the instruction itself. | |
8747 | * | |
8748 | * Our job here is to fix the operand so that it would add | |
8749 | * the correct offset so that %ebx would point to itself. The | |
8750 | * thing that is tricky is that .-.L66 will point to the | |
8751 | * beginning of the instruction, so we need to further modify | |
8752 | * the operand so that it will point to itself. There are | |
8753 | * other cases where you have something like: | |
8754 | * | |
8755 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
8756 | * | |
8757 | * and here no correction would be required. Internally in | |
8758 | * the assembler we treat operands of this form as not being | |
8759 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
8760 | * whether it would simplify matters to do it this way. Who | |
8761 | * knows. In earlier versions of the PIC patches, the | |
8762 | * pcrel_adjust field was used to store the correction, but | |
8763 | * since the expression is not pcrel, I felt it would be | |
8764 | * confusing to do it this way. */ | |
8765 | ||
d6ab8113 | 8766 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
8767 | || reloc_type == BFD_RELOC_X86_64_32S |
8768 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
8769 | && GOT_symbol |
8770 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
8771 | && (i.op[n].imms->X_op == O_symbol | |
8772 | || (i.op[n].imms->X_op == O_add | |
8773 | && ((symbol_get_value_expression | |
8774 | (i.op[n].imms->X_op_symbol)->X_op) | |
8775 | == O_subtract)))) | |
8776 | { | |
4fa24527 | 8777 | if (!object_64bit) |
d6ab8113 | 8778 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 8779 | else if (size == 4) |
d6ab8113 | 8780 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
8781 | else if (size == 8) |
8782 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d583596c JB |
8783 | i.op[n].imms->X_add_number += |
8784 | encoding_length (insn_start_frag, insn_start_off, p); | |
29b0f896 | 8785 | } |
29b0f896 AM |
8786 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
8787 | i.op[n].imms, 0, reloc_type); | |
8788 | } | |
8789 | } | |
8790 | } | |
252b5132 RH |
8791 | } |
8792 | \f | |
d182319b JB |
8793 | /* x86_cons_fix_new is called via the expression parsing code when a |
8794 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
8795 | static int cons_sign = -1; |
8796 | ||
8797 | void | |
e3bb37b5 | 8798 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 8799 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 8800 | { |
d258b828 | 8801 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
8802 | |
8803 | #ifdef TE_PE | |
8804 | if (exp->X_op == O_secrel) | |
8805 | { | |
8806 | exp->X_op = O_symbol; | |
8807 | r = BFD_RELOC_32_SECREL; | |
8808 | } | |
8809 | #endif | |
8810 | ||
8811 | fix_new_exp (frag, off, len, exp, 0, r); | |
8812 | } | |
8813 | ||
357d1bd8 L |
8814 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
8815 | purpose of the `.dc.a' internal pseudo-op. */ | |
8816 | ||
8817 | int | |
8818 | x86_address_bytes (void) | |
8819 | { | |
8820 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
8821 | return 4; | |
8822 | return stdoutput->arch_info->bits_per_address / 8; | |
8823 | } | |
8824 | ||
d382c579 TG |
8825 | #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
8826 | || defined (LEX_AT) | |
d258b828 | 8827 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 8828 | #else |
f3c180ae AM |
8829 | /* Parse operands of the form |
8830 | <symbol>@GOTOFF+<nnn> | |
8831 | and similar .plt or .got references. | |
8832 | ||
8833 | If we find one, set up the correct relocation in RELOC and copy the | |
8834 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
8835 | parsing by the calling routine. Return this buffer, and if ADJUST | |
8836 | is non-null set it to the length of the string we removed from the | |
8837 | input line. Otherwise return NULL. */ | |
8838 | static char * | |
91d6fa6a | 8839 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 8840 | int *adjust, |
d258b828 | 8841 | i386_operand_type *types) |
f3c180ae | 8842 | { |
7b81dfbb AJ |
8843 | /* Some of the relocations depend on the size of what field is to |
8844 | be relocated. But in our callers i386_immediate and i386_displacement | |
8845 | we don't yet know the operand size (this will be set by insn | |
8846 | matching). Hence we record the word32 relocation here, | |
8847 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
8848 | static const struct { |
8849 | const char *str; | |
cff8d58a | 8850 | int len; |
4fa24527 | 8851 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 8852 | const i386_operand_type types64; |
f3c180ae | 8853 | } gotrel[] = { |
8ce3d284 | 8854 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
8855 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
8856 | BFD_RELOC_SIZE32 }, | |
8857 | OPERAND_TYPE_IMM32_64 }, | |
8ce3d284 | 8858 | #endif |
cff8d58a L |
8859 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
8860 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 8861 | OPERAND_TYPE_IMM64 }, |
cff8d58a L |
8862 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
8863 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 8864 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8865 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
8866 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 8867 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
8868 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
8869 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 8870 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
8871 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
8872 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 8873 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8874 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
8875 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 8876 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8877 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
8878 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8879 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8880 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
8881 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 8882 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8883 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
8884 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 8885 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8886 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
8887 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 8888 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
8889 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
8890 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8891 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8892 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
8893 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 | 8894 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
8895 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
8896 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8897 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8898 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
8899 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8900 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8901 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
8902 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 8903 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
cff8d58a L |
8904 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
8905 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 8906 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8907 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
8908 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 8909 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
8910 | }; |
8911 | char *cp; | |
8912 | unsigned int j; | |
8913 | ||
d382c579 | 8914 | #if defined (OBJ_MAYBE_ELF) |
718ddfc0 JB |
8915 | if (!IS_ELF) |
8916 | return NULL; | |
d382c579 | 8917 | #endif |
718ddfc0 | 8918 | |
f3c180ae | 8919 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 8920 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
8921 | return NULL; |
8922 | ||
47465058 | 8923 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 8924 | { |
cff8d58a | 8925 | int len = gotrel[j].len; |
28f81592 | 8926 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 8927 | { |
4fa24527 | 8928 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 8929 | { |
28f81592 AM |
8930 | int first, second; |
8931 | char *tmpbuf, *past_reloc; | |
f3c180ae | 8932 | |
91d6fa6a | 8933 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 8934 | |
3956db08 JB |
8935 | if (types) |
8936 | { | |
8937 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
8938 | { |
8939 | types->bitfield.imm32 = 1; | |
8940 | types->bitfield.disp32 = 1; | |
8941 | } | |
3956db08 JB |
8942 | else |
8943 | *types = gotrel[j].types64; | |
8944 | } | |
8945 | ||
8fd4256d | 8946 | if (j != 0 && GOT_symbol == NULL) |
f3c180ae AM |
8947 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
8948 | ||
28f81592 | 8949 | /* The length of the first part of our input line. */ |
f3c180ae | 8950 | first = cp - input_line_pointer; |
28f81592 AM |
8951 | |
8952 | /* The second part goes from after the reloc token until | |
67c11a9b | 8953 | (and including) an end_of_line char or comma. */ |
28f81592 | 8954 | past_reloc = cp + 1 + len; |
67c11a9b AM |
8955 | cp = past_reloc; |
8956 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
8957 | ++cp; | |
8958 | second = cp + 1 - past_reloc; | |
28f81592 AM |
8959 | |
8960 | /* Allocate and copy string. The trailing NUL shouldn't | |
8961 | be necessary, but be safe. */ | |
add39d23 | 8962 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 8963 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
8964 | if (second != 0 && *past_reloc != ' ') |
8965 | /* Replace the relocation token with ' ', so that | |
8966 | errors like foo@GOTOFF1 will be detected. */ | |
8967 | tmpbuf[first++] = ' '; | |
af89796a L |
8968 | else |
8969 | /* Increment length by 1 if the relocation token is | |
8970 | removed. */ | |
8971 | len++; | |
8972 | if (adjust) | |
8973 | *adjust = len; | |
0787a12d AM |
8974 | memcpy (tmpbuf + first, past_reloc, second); |
8975 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
8976 | return tmpbuf; |
8977 | } | |
8978 | ||
4fa24527 JB |
8979 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
8980 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
8981 | return NULL; |
8982 | } | |
8983 | } | |
8984 | ||
8985 | /* Might be a symbol version string. Don't as_bad here. */ | |
8986 | return NULL; | |
8987 | } | |
4e4f7c87 | 8988 | #endif |
f3c180ae | 8989 | |
a988325c NC |
8990 | #ifdef TE_PE |
8991 | #ifdef lex_got | |
8992 | #undef lex_got | |
8993 | #endif | |
8994 | /* Parse operands of the form | |
8995 | <symbol>@SECREL32+<nnn> | |
8996 | ||
8997 | If we find one, set up the correct relocation in RELOC and copy the | |
8998 | input string, minus the `@SECREL32' into a malloc'd buffer for | |
8999 | parsing by the calling routine. Return this buffer, and if ADJUST | |
9000 | is non-null set it to the length of the string we removed from the | |
34bca508 L |
9001 | input line. Otherwise return NULL. |
9002 | ||
a988325c NC |
9003 | This function is copied from the ELF version above adjusted for PE targets. */ |
9004 | ||
9005 | static char * | |
9006 | lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, | |
9007 | int *adjust ATTRIBUTE_UNUSED, | |
d258b828 | 9008 | i386_operand_type *types) |
a988325c NC |
9009 | { |
9010 | static const struct | |
9011 | { | |
9012 | const char *str; | |
9013 | int len; | |
9014 | const enum bfd_reloc_code_real rel[2]; | |
9015 | const i386_operand_type types64; | |
9016 | } | |
9017 | gotrel[] = | |
9018 | { | |
9019 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
9020 | BFD_RELOC_32_SECREL }, | |
9021 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
9022 | }; | |
9023 | ||
9024 | char *cp; | |
9025 | unsigned j; | |
9026 | ||
9027 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
9028 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') | |
9029 | return NULL; | |
9030 | ||
9031 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) | |
9032 | { | |
9033 | int len = gotrel[j].len; | |
9034 | ||
9035 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) | |
9036 | { | |
9037 | if (gotrel[j].rel[object_64bit] != 0) | |
9038 | { | |
9039 | int first, second; | |
9040 | char *tmpbuf, *past_reloc; | |
9041 | ||
9042 | *rel = gotrel[j].rel[object_64bit]; | |
9043 | if (adjust) | |
9044 | *adjust = len; | |
9045 | ||
9046 | if (types) | |
9047 | { | |
9048 | if (flag_code != CODE_64BIT) | |
9049 | { | |
9050 | types->bitfield.imm32 = 1; | |
9051 | types->bitfield.disp32 = 1; | |
9052 | } | |
9053 | else | |
9054 | *types = gotrel[j].types64; | |
9055 | } | |
9056 | ||
9057 | /* The length of the first part of our input line. */ | |
9058 | first = cp - input_line_pointer; | |
9059 | ||
9060 | /* The second part goes from after the reloc token until | |
9061 | (and including) an end_of_line char or comma. */ | |
9062 | past_reloc = cp + 1 + len; | |
9063 | cp = past_reloc; | |
9064 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
9065 | ++cp; | |
9066 | second = cp + 1 - past_reloc; | |
9067 | ||
9068 | /* Allocate and copy string. The trailing NUL shouldn't | |
9069 | be necessary, but be safe. */ | |
add39d23 | 9070 | tmpbuf = XNEWVEC (char, first + second + 2); |
a988325c NC |
9071 | memcpy (tmpbuf, input_line_pointer, first); |
9072 | if (second != 0 && *past_reloc != ' ') | |
9073 | /* Replace the relocation token with ' ', so that | |
9074 | errors like foo@SECLREL321 will be detected. */ | |
9075 | tmpbuf[first++] = ' '; | |
9076 | memcpy (tmpbuf + first, past_reloc, second); | |
9077 | tmpbuf[first + second] = '\0'; | |
9078 | return tmpbuf; | |
9079 | } | |
9080 | ||
9081 | as_bad (_("@%s reloc is not supported with %d-bit output format"), | |
9082 | gotrel[j].str, 1 << (5 + object_64bit)); | |
9083 | return NULL; | |
9084 | } | |
9085 | } | |
9086 | ||
9087 | /* Might be a symbol version string. Don't as_bad here. */ | |
9088 | return NULL; | |
9089 | } | |
9090 | ||
9091 | #endif /* TE_PE */ | |
9092 | ||
62ebcb5c | 9093 | bfd_reloc_code_real_type |
e3bb37b5 | 9094 | x86_cons (expressionS *exp, int size) |
f3c180ae | 9095 | { |
62ebcb5c AM |
9096 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
9097 | ||
ee86248c JB |
9098 | intel_syntax = -intel_syntax; |
9099 | ||
3c7b9c2c | 9100 | exp->X_md = 0; |
4fa24527 | 9101 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
9102 | { |
9103 | /* Handle @GOTOFF and the like in an expression. */ | |
9104 | char *save; | |
9105 | char *gotfree_input_line; | |
4a57f2cf | 9106 | int adjust = 0; |
f3c180ae AM |
9107 | |
9108 | save = input_line_pointer; | |
d258b828 | 9109 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
9110 | if (gotfree_input_line) |
9111 | input_line_pointer = gotfree_input_line; | |
9112 | ||
9113 | expression (exp); | |
9114 | ||
9115 | if (gotfree_input_line) | |
9116 | { | |
9117 | /* expression () has merrily parsed up to the end of line, | |
9118 | or a comma - in the wrong buffer. Transfer how far | |
9119 | input_line_pointer has moved to the right buffer. */ | |
9120 | input_line_pointer = (save | |
9121 | + (input_line_pointer - gotfree_input_line) | |
9122 | + adjust); | |
9123 | free (gotfree_input_line); | |
3992d3b7 AM |
9124 | if (exp->X_op == O_constant |
9125 | || exp->X_op == O_absent | |
9126 | || exp->X_op == O_illegal | |
0398aac5 | 9127 | || exp->X_op == O_register |
3992d3b7 AM |
9128 | || exp->X_op == O_big) |
9129 | { | |
9130 | char c = *input_line_pointer; | |
9131 | *input_line_pointer = 0; | |
9132 | as_bad (_("missing or invalid expression `%s'"), save); | |
9133 | *input_line_pointer = c; | |
9134 | } | |
b9519cfe L |
9135 | else if ((got_reloc == BFD_RELOC_386_PLT32 |
9136 | || got_reloc == BFD_RELOC_X86_64_PLT32) | |
9137 | && exp->X_op != O_symbol) | |
9138 | { | |
9139 | char c = *input_line_pointer; | |
9140 | *input_line_pointer = 0; | |
9141 | as_bad (_("invalid PLT expression `%s'"), save); | |
9142 | *input_line_pointer = c; | |
9143 | } | |
f3c180ae AM |
9144 | } |
9145 | } | |
9146 | else | |
9147 | expression (exp); | |
ee86248c JB |
9148 | |
9149 | intel_syntax = -intel_syntax; | |
9150 | ||
9151 | if (intel_syntax) | |
9152 | i386_intel_simplify (exp); | |
62ebcb5c AM |
9153 | |
9154 | return got_reloc; | |
f3c180ae | 9155 | } |
f3c180ae | 9156 | |
9f32dd5b L |
9157 | static void |
9158 | signed_cons (int size) | |
6482c264 | 9159 | { |
d182319b JB |
9160 | if (flag_code == CODE_64BIT) |
9161 | cons_sign = 1; | |
9162 | cons (size); | |
9163 | cons_sign = -1; | |
6482c264 NC |
9164 | } |
9165 | ||
d182319b | 9166 | #ifdef TE_PE |
6482c264 | 9167 | static void |
7016a5d5 | 9168 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
9169 | { |
9170 | expressionS exp; | |
9171 | ||
9172 | do | |
9173 | { | |
9174 | expression (&exp); | |
9175 | if (exp.X_op == O_symbol) | |
9176 | exp.X_op = O_secrel; | |
9177 | ||
9178 | emit_expr (&exp, 4); | |
9179 | } | |
9180 | while (*input_line_pointer++ == ','); | |
9181 | ||
9182 | input_line_pointer--; | |
9183 | demand_empty_rest_of_line (); | |
9184 | } | |
6482c264 NC |
9185 | #endif |
9186 | ||
43234a1e L |
9187 | /* Handle Vector operations. */ |
9188 | ||
9189 | static char * | |
9190 | check_VecOperations (char *op_string, char *op_end) | |
9191 | { | |
9192 | const reg_entry *mask; | |
9193 | const char *saved; | |
9194 | char *end_op; | |
9195 | ||
9196 | while (*op_string | |
9197 | && (op_end == NULL || op_string < op_end)) | |
9198 | { | |
9199 | saved = op_string; | |
9200 | if (*op_string == '{') | |
9201 | { | |
9202 | op_string++; | |
9203 | ||
9204 | /* Check broadcasts. */ | |
9205 | if (strncmp (op_string, "1to", 3) == 0) | |
9206 | { | |
9207 | int bcst_type; | |
9208 | ||
9209 | if (i.broadcast) | |
9210 | goto duplicated_vec_op; | |
9211 | ||
9212 | op_string += 3; | |
9213 | if (*op_string == '8') | |
8e6e0792 | 9214 | bcst_type = 8; |
b28d1bda | 9215 | else if (*op_string == '4') |
8e6e0792 | 9216 | bcst_type = 4; |
b28d1bda | 9217 | else if (*op_string == '2') |
8e6e0792 | 9218 | bcst_type = 2; |
43234a1e L |
9219 | else if (*op_string == '1' |
9220 | && *(op_string+1) == '6') | |
9221 | { | |
8e6e0792 | 9222 | bcst_type = 16; |
43234a1e L |
9223 | op_string++; |
9224 | } | |
9225 | else | |
9226 | { | |
9227 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
9228 | return NULL; | |
9229 | } | |
9230 | op_string++; | |
9231 | ||
9232 | broadcast_op.type = bcst_type; | |
9233 | broadcast_op.operand = this_operand; | |
1f75763a | 9234 | broadcast_op.bytes = 0; |
43234a1e L |
9235 | i.broadcast = &broadcast_op; |
9236 | } | |
9237 | /* Check masking operation. */ | |
9238 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
9239 | { | |
9240 | /* k0 can't be used for write mask. */ | |
6d2cd6b2 | 9241 | if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0) |
43234a1e | 9242 | { |
6d2cd6b2 JB |
9243 | as_bad (_("`%s%s' can't be used for write mask"), |
9244 | register_prefix, mask->reg_name); | |
43234a1e L |
9245 | return NULL; |
9246 | } | |
9247 | ||
9248 | if (!i.mask) | |
9249 | { | |
9250 | mask_op.mask = mask; | |
9251 | mask_op.zeroing = 0; | |
9252 | mask_op.operand = this_operand; | |
9253 | i.mask = &mask_op; | |
9254 | } | |
9255 | else | |
9256 | { | |
9257 | if (i.mask->mask) | |
9258 | goto duplicated_vec_op; | |
9259 | ||
9260 | i.mask->mask = mask; | |
9261 | ||
9262 | /* Only "{z}" is allowed here. No need to check | |
9263 | zeroing mask explicitly. */ | |
9264 | if (i.mask->operand != this_operand) | |
9265 | { | |
9266 | as_bad (_("invalid write mask `%s'"), saved); | |
9267 | return NULL; | |
9268 | } | |
9269 | } | |
9270 | ||
9271 | op_string = end_op; | |
9272 | } | |
9273 | /* Check zeroing-flag for masking operation. */ | |
9274 | else if (*op_string == 'z') | |
9275 | { | |
9276 | if (!i.mask) | |
9277 | { | |
9278 | mask_op.mask = NULL; | |
9279 | mask_op.zeroing = 1; | |
9280 | mask_op.operand = this_operand; | |
9281 | i.mask = &mask_op; | |
9282 | } | |
9283 | else | |
9284 | { | |
9285 | if (i.mask->zeroing) | |
9286 | { | |
9287 | duplicated_vec_op: | |
9288 | as_bad (_("duplicated `%s'"), saved); | |
9289 | return NULL; | |
9290 | } | |
9291 | ||
9292 | i.mask->zeroing = 1; | |
9293 | ||
9294 | /* Only "{%k}" is allowed here. No need to check mask | |
9295 | register explicitly. */ | |
9296 | if (i.mask->operand != this_operand) | |
9297 | { | |
9298 | as_bad (_("invalid zeroing-masking `%s'"), | |
9299 | saved); | |
9300 | return NULL; | |
9301 | } | |
9302 | } | |
9303 | ||
9304 | op_string++; | |
9305 | } | |
9306 | else | |
9307 | goto unknown_vec_op; | |
9308 | ||
9309 | if (*op_string != '}') | |
9310 | { | |
9311 | as_bad (_("missing `}' in `%s'"), saved); | |
9312 | return NULL; | |
9313 | } | |
9314 | op_string++; | |
0ba3a731 L |
9315 | |
9316 | /* Strip whitespace since the addition of pseudo prefixes | |
9317 | changed how the scrubber treats '{'. */ | |
9318 | if (is_space_char (*op_string)) | |
9319 | ++op_string; | |
9320 | ||
43234a1e L |
9321 | continue; |
9322 | } | |
9323 | unknown_vec_op: | |
9324 | /* We don't know this one. */ | |
9325 | as_bad (_("unknown vector operation: `%s'"), saved); | |
9326 | return NULL; | |
9327 | } | |
9328 | ||
6d2cd6b2 JB |
9329 | if (i.mask && i.mask->zeroing && !i.mask->mask) |
9330 | { | |
9331 | as_bad (_("zeroing-masking only allowed with write mask")); | |
9332 | return NULL; | |
9333 | } | |
9334 | ||
43234a1e L |
9335 | return op_string; |
9336 | } | |
9337 | ||
252b5132 | 9338 | static int |
70e41ade | 9339 | i386_immediate (char *imm_start) |
252b5132 RH |
9340 | { |
9341 | char *save_input_line_pointer; | |
f3c180ae | 9342 | char *gotfree_input_line; |
252b5132 | 9343 | segT exp_seg = 0; |
47926f60 | 9344 | expressionS *exp; |
40fb9820 L |
9345 | i386_operand_type types; |
9346 | ||
0dfbf9d7 | 9347 | operand_type_set (&types, ~0); |
252b5132 RH |
9348 | |
9349 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
9350 | { | |
31b2323c L |
9351 | as_bad (_("at most %d immediate operands are allowed"), |
9352 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
9353 | return 0; |
9354 | } | |
9355 | ||
9356 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 9357 | i.op[this_operand].imms = exp; |
252b5132 RH |
9358 | |
9359 | if (is_space_char (*imm_start)) | |
9360 | ++imm_start; | |
9361 | ||
9362 | save_input_line_pointer = input_line_pointer; | |
9363 | input_line_pointer = imm_start; | |
9364 | ||
d258b828 | 9365 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
9366 | if (gotfree_input_line) |
9367 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
9368 | |
9369 | exp_seg = expression (exp); | |
9370 | ||
83183c0c | 9371 | SKIP_WHITESPACE (); |
43234a1e L |
9372 | |
9373 | /* Handle vector operations. */ | |
9374 | if (*input_line_pointer == '{') | |
9375 | { | |
9376 | input_line_pointer = check_VecOperations (input_line_pointer, | |
9377 | NULL); | |
9378 | if (input_line_pointer == NULL) | |
9379 | return 0; | |
9380 | } | |
9381 | ||
252b5132 | 9382 | if (*input_line_pointer) |
f3c180ae | 9383 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
9384 | |
9385 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 9386 | if (gotfree_input_line) |
ee86248c JB |
9387 | { |
9388 | free (gotfree_input_line); | |
9389 | ||
9390 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
9391 | exp->X_op = O_illegal; | |
9392 | } | |
9393 | ||
9394 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); | |
9395 | } | |
252b5132 | 9396 | |
ee86248c JB |
9397 | static int |
9398 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
9399 | i386_operand_type types, const char *imm_start) | |
9400 | { | |
9401 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 9402 | { |
313c53d1 L |
9403 | if (imm_start) |
9404 | as_bad (_("missing or invalid immediate expression `%s'"), | |
9405 | imm_start); | |
3992d3b7 | 9406 | return 0; |
252b5132 | 9407 | } |
3e73aa7c | 9408 | else if (exp->X_op == O_constant) |
252b5132 | 9409 | { |
47926f60 | 9410 | /* Size it properly later. */ |
40fb9820 | 9411 | i.types[this_operand].bitfield.imm64 = 1; |
13f864ae L |
9412 | /* If not 64bit, sign extend val. */ |
9413 | if (flag_code != CODE_64BIT | |
4eed87de AM |
9414 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
9415 | exp->X_add_number | |
9416 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 9417 | } |
4c63da97 | 9418 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 9419 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 9420 | && exp_seg != absolute_section |
47926f60 | 9421 | && exp_seg != text_section |
24eab124 AM |
9422 | && exp_seg != data_section |
9423 | && exp_seg != bss_section | |
9424 | && exp_seg != undefined_section | |
f86103b7 | 9425 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 9426 | { |
d0b47220 | 9427 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
9428 | return 0; |
9429 | } | |
9430 | #endif | |
a841bdf5 | 9431 | else if (!intel_syntax && exp_seg == reg_section) |
bb8f5920 | 9432 | { |
313c53d1 L |
9433 | if (imm_start) |
9434 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
bb8f5920 L |
9435 | return 0; |
9436 | } | |
252b5132 RH |
9437 | else |
9438 | { | |
9439 | /* This is an address. The size of the address will be | |
24eab124 | 9440 | determined later, depending on destination register, |
3e73aa7c | 9441 | suffix, or the default for the section. */ |
40fb9820 L |
9442 | i.types[this_operand].bitfield.imm8 = 1; |
9443 | i.types[this_operand].bitfield.imm16 = 1; | |
9444 | i.types[this_operand].bitfield.imm32 = 1; | |
9445 | i.types[this_operand].bitfield.imm32s = 1; | |
9446 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
9447 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
9448 | types); | |
252b5132 RH |
9449 | } |
9450 | ||
9451 | return 1; | |
9452 | } | |
9453 | ||
551c1ca1 | 9454 | static char * |
e3bb37b5 | 9455 | i386_scale (char *scale) |
252b5132 | 9456 | { |
551c1ca1 AM |
9457 | offsetT val; |
9458 | char *save = input_line_pointer; | |
252b5132 | 9459 | |
551c1ca1 AM |
9460 | input_line_pointer = scale; |
9461 | val = get_absolute_expression (); | |
9462 | ||
9463 | switch (val) | |
252b5132 | 9464 | { |
551c1ca1 | 9465 | case 1: |
252b5132 RH |
9466 | i.log2_scale_factor = 0; |
9467 | break; | |
551c1ca1 | 9468 | case 2: |
252b5132 RH |
9469 | i.log2_scale_factor = 1; |
9470 | break; | |
551c1ca1 | 9471 | case 4: |
252b5132 RH |
9472 | i.log2_scale_factor = 2; |
9473 | break; | |
551c1ca1 | 9474 | case 8: |
252b5132 RH |
9475 | i.log2_scale_factor = 3; |
9476 | break; | |
9477 | default: | |
a724f0f4 JB |
9478 | { |
9479 | char sep = *input_line_pointer; | |
9480 | ||
9481 | *input_line_pointer = '\0'; | |
9482 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
9483 | scale); | |
9484 | *input_line_pointer = sep; | |
9485 | input_line_pointer = save; | |
9486 | return NULL; | |
9487 | } | |
252b5132 | 9488 | } |
29b0f896 | 9489 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
9490 | { |
9491 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 9492 | 1 << i.log2_scale_factor); |
252b5132 | 9493 | i.log2_scale_factor = 0; |
252b5132 | 9494 | } |
551c1ca1 AM |
9495 | scale = input_line_pointer; |
9496 | input_line_pointer = save; | |
9497 | return scale; | |
252b5132 RH |
9498 | } |
9499 | ||
252b5132 | 9500 | static int |
e3bb37b5 | 9501 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 9502 | { |
29b0f896 | 9503 | expressionS *exp; |
252b5132 RH |
9504 | segT exp_seg = 0; |
9505 | char *save_input_line_pointer; | |
f3c180ae | 9506 | char *gotfree_input_line; |
40fb9820 L |
9507 | int override; |
9508 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 9509 | int ret; |
252b5132 | 9510 | |
31b2323c L |
9511 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
9512 | { | |
9513 | as_bad (_("at most %d displacement operands are allowed"), | |
9514 | MAX_MEMORY_OPERANDS); | |
9515 | return 0; | |
9516 | } | |
9517 | ||
0dfbf9d7 | 9518 | operand_type_set (&bigdisp, 0); |
40fb9820 L |
9519 | if ((i.types[this_operand].bitfield.jumpabsolute) |
9520 | || (!current_templates->start->opcode_modifier.jump | |
9521 | && !current_templates->start->opcode_modifier.jumpdword)) | |
e05278af | 9522 | { |
40fb9820 | 9523 | bigdisp.bitfield.disp32 = 1; |
e05278af | 9524 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
9525 | if (flag_code == CODE_64BIT) |
9526 | { | |
9527 | if (!override) | |
9528 | { | |
9529 | bigdisp.bitfield.disp32s = 1; | |
9530 | bigdisp.bitfield.disp64 = 1; | |
9531 | } | |
9532 | } | |
9533 | else if ((flag_code == CODE_16BIT) ^ override) | |
9534 | { | |
9535 | bigdisp.bitfield.disp32 = 0; | |
9536 | bigdisp.bitfield.disp16 = 1; | |
9537 | } | |
e05278af JB |
9538 | } |
9539 | else | |
9540 | { | |
9541 | /* For PC-relative branches, the width of the displacement | |
9542 | is dependent upon data size, not address size. */ | |
e05278af | 9543 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
9544 | if (flag_code == CODE_64BIT) |
9545 | { | |
9546 | if (override || i.suffix == WORD_MNEM_SUFFIX) | |
9547 | bigdisp.bitfield.disp16 = 1; | |
9548 | else | |
9549 | { | |
9550 | bigdisp.bitfield.disp32 = 1; | |
9551 | bigdisp.bitfield.disp32s = 1; | |
9552 | } | |
9553 | } | |
9554 | else | |
e05278af JB |
9555 | { |
9556 | if (!override) | |
9557 | override = (i.suffix == (flag_code != CODE_16BIT | |
9558 | ? WORD_MNEM_SUFFIX | |
9559 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
9560 | bigdisp.bitfield.disp32 = 1; |
9561 | if ((flag_code == CODE_16BIT) ^ override) | |
9562 | { | |
9563 | bigdisp.bitfield.disp32 = 0; | |
9564 | bigdisp.bitfield.disp16 = 1; | |
9565 | } | |
e05278af | 9566 | } |
e05278af | 9567 | } |
c6fb90c8 L |
9568 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
9569 | bigdisp); | |
252b5132 RH |
9570 | |
9571 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 9572 | i.op[this_operand].disps = exp; |
252b5132 RH |
9573 | i.disp_operands++; |
9574 | save_input_line_pointer = input_line_pointer; | |
9575 | input_line_pointer = disp_start; | |
9576 | END_STRING_AND_SAVE (disp_end); | |
9577 | ||
9578 | #ifndef GCC_ASM_O_HACK | |
9579 | #define GCC_ASM_O_HACK 0 | |
9580 | #endif | |
9581 | #if GCC_ASM_O_HACK | |
9582 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 9583 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 9584 | && displacement_string_end[-1] == '+') |
252b5132 RH |
9585 | { |
9586 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
9587 | constraint within gcc asm statements. |
9588 | For instance: | |
9589 | ||
9590 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
9591 | __asm__ __volatile__ ( \ | |
9592 | "movw %w2,%0\n\t" \ | |
9593 | "movw %w1,2+%0\n\t" \ | |
9594 | "rorl $16,%1\n\t" \ | |
9595 | "movb %b1,4+%0\n\t" \ | |
9596 | "movb %4,5+%0\n\t" \ | |
9597 | "movb $0,6+%0\n\t" \ | |
9598 | "movb %h1,7+%0\n\t" \ | |
9599 | "rorl $16,%1" \ | |
9600 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
9601 | ||
9602 | This works great except that the output assembler ends | |
9603 | up looking a bit weird if it turns out that there is | |
9604 | no offset. You end up producing code that looks like: | |
9605 | ||
9606 | #APP | |
9607 | movw $235,(%eax) | |
9608 | movw %dx,2+(%eax) | |
9609 | rorl $16,%edx | |
9610 | movb %dl,4+(%eax) | |
9611 | movb $137,5+(%eax) | |
9612 | movb $0,6+(%eax) | |
9613 | movb %dh,7+(%eax) | |
9614 | rorl $16,%edx | |
9615 | #NO_APP | |
9616 | ||
47926f60 | 9617 | So here we provide the missing zero. */ |
24eab124 AM |
9618 | |
9619 | *displacement_string_end = '0'; | |
252b5132 RH |
9620 | } |
9621 | #endif | |
d258b828 | 9622 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
9623 | if (gotfree_input_line) |
9624 | input_line_pointer = gotfree_input_line; | |
252b5132 | 9625 | |
24eab124 | 9626 | exp_seg = expression (exp); |
252b5132 | 9627 | |
636c26b0 AM |
9628 | SKIP_WHITESPACE (); |
9629 | if (*input_line_pointer) | |
9630 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
9631 | #if GCC_ASM_O_HACK | |
9632 | RESTORE_END_STRING (disp_end + 1); | |
9633 | #endif | |
636c26b0 | 9634 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 9635 | if (gotfree_input_line) |
ee86248c JB |
9636 | { |
9637 | free (gotfree_input_line); | |
9638 | ||
9639 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
9640 | exp->X_op = O_illegal; | |
9641 | } | |
9642 | ||
9643 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
9644 | ||
9645 | RESTORE_END_STRING (disp_end); | |
9646 | ||
9647 | return ret; | |
9648 | } | |
9649 | ||
9650 | static int | |
9651 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
9652 | i386_operand_type types, const char *disp_start) | |
9653 | { | |
9654 | i386_operand_type bigdisp; | |
9655 | int ret = 1; | |
636c26b0 | 9656 | |
24eab124 AM |
9657 | /* We do this to make sure that the section symbol is in |
9658 | the symbol table. We will ultimately change the relocation | |
47926f60 | 9659 | to be relative to the beginning of the section. */ |
1ae12ab7 | 9660 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
9661 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
9662 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 9663 | { |
636c26b0 | 9664 | if (exp->X_op != O_symbol) |
3992d3b7 | 9665 | goto inv_disp; |
636c26b0 | 9666 | |
e5cb08ac | 9667 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
9668 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
9669 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 9670 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
9671 | exp->X_op = O_subtract; |
9672 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 9673 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 9674 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
9675 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
9676 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 9677 | else |
29b0f896 | 9678 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 9679 | } |
252b5132 | 9680 | |
3992d3b7 AM |
9681 | else if (exp->X_op == O_absent |
9682 | || exp->X_op == O_illegal | |
ee86248c | 9683 | || exp->X_op == O_big) |
2daf4fd8 | 9684 | { |
3992d3b7 AM |
9685 | inv_disp: |
9686 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 9687 | disp_start); |
3992d3b7 | 9688 | ret = 0; |
2daf4fd8 AM |
9689 | } |
9690 | ||
0e1147d9 L |
9691 | else if (flag_code == CODE_64BIT |
9692 | && !i.prefix[ADDR_PREFIX] | |
9693 | && exp->X_op == O_constant) | |
9694 | { | |
9695 | /* Since displacement is signed extended to 64bit, don't allow | |
9696 | disp32 and turn off disp32s if they are out of range. */ | |
9697 | i.types[this_operand].bitfield.disp32 = 0; | |
9698 | if (!fits_in_signed_long (exp->X_add_number)) | |
9699 | { | |
9700 | i.types[this_operand].bitfield.disp32s = 0; | |
9701 | if (i.types[this_operand].bitfield.baseindex) | |
9702 | { | |
9703 | as_bad (_("0x%lx out range of signed 32bit displacement"), | |
9704 | (long) exp->X_add_number); | |
9705 | ret = 0; | |
9706 | } | |
9707 | } | |
9708 | } | |
9709 | ||
4c63da97 | 9710 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
9711 | else if (exp->X_op != O_constant |
9712 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
9713 | && exp_seg != absolute_section | |
9714 | && exp_seg != text_section | |
9715 | && exp_seg != data_section | |
9716 | && exp_seg != bss_section | |
9717 | && exp_seg != undefined_section | |
9718 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 9719 | { |
d0b47220 | 9720 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 9721 | ret = 0; |
24eab124 | 9722 | } |
252b5132 | 9723 | #endif |
3956db08 | 9724 | |
40fb9820 L |
9725 | /* Check if this is a displacement only operand. */ |
9726 | bigdisp = i.types[this_operand]; | |
9727 | bigdisp.bitfield.disp8 = 0; | |
9728 | bigdisp.bitfield.disp16 = 0; | |
9729 | bigdisp.bitfield.disp32 = 0; | |
9730 | bigdisp.bitfield.disp32s = 0; | |
9731 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 9732 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
9733 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
9734 | types); | |
3956db08 | 9735 | |
3992d3b7 | 9736 | return ret; |
252b5132 RH |
9737 | } |
9738 | ||
2abc2bec JB |
9739 | /* Return the active addressing mode, taking address override and |
9740 | registers forming the address into consideration. Update the | |
9741 | address override prefix if necessary. */ | |
47926f60 | 9742 | |
2abc2bec JB |
9743 | static enum flag_code |
9744 | i386_addressing_mode (void) | |
252b5132 | 9745 | { |
be05d201 L |
9746 | enum flag_code addr_mode; |
9747 | ||
9748 | if (i.prefix[ADDR_PREFIX]) | |
9749 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
9750 | else | |
9751 | { | |
9752 | addr_mode = flag_code; | |
9753 | ||
24eab124 | 9754 | #if INFER_ADDR_PREFIX |
be05d201 L |
9755 | if (i.mem_operands == 0) |
9756 | { | |
9757 | /* Infer address prefix from the first memory operand. */ | |
9758 | const reg_entry *addr_reg = i.base_reg; | |
9759 | ||
9760 | if (addr_reg == NULL) | |
9761 | addr_reg = i.index_reg; | |
eecb386c | 9762 | |
be05d201 L |
9763 | if (addr_reg) |
9764 | { | |
e968fc9b | 9765 | if (addr_reg->reg_type.bitfield.dword) |
be05d201 L |
9766 | addr_mode = CODE_32BIT; |
9767 | else if (flag_code != CODE_64BIT | |
dc821c5f | 9768 | && addr_reg->reg_type.bitfield.word) |
be05d201 L |
9769 | addr_mode = CODE_16BIT; |
9770 | ||
9771 | if (addr_mode != flag_code) | |
9772 | { | |
9773 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
9774 | i.prefixes += 1; | |
9775 | /* Change the size of any displacement too. At most one | |
9776 | of Disp16 or Disp32 is set. | |
9777 | FIXME. There doesn't seem to be any real need for | |
9778 | separate Disp16 and Disp32 flags. The same goes for | |
9779 | Imm16 and Imm32. Removing them would probably clean | |
9780 | up the code quite a lot. */ | |
9781 | if (flag_code != CODE_64BIT | |
9782 | && (i.types[this_operand].bitfield.disp16 | |
9783 | || i.types[this_operand].bitfield.disp32)) | |
9784 | i.types[this_operand] | |
9785 | = operand_type_xor (i.types[this_operand], disp16_32); | |
9786 | } | |
9787 | } | |
9788 | } | |
24eab124 | 9789 | #endif |
be05d201 L |
9790 | } |
9791 | ||
2abc2bec JB |
9792 | return addr_mode; |
9793 | } | |
9794 | ||
9795 | /* Make sure the memory operand we've been dealt is valid. | |
9796 | Return 1 on success, 0 on a failure. */ | |
9797 | ||
9798 | static int | |
9799 | i386_index_check (const char *operand_string) | |
9800 | { | |
9801 | const char *kind = "base/index"; | |
9802 | enum flag_code addr_mode = i386_addressing_mode (); | |
9803 | ||
fc0763e6 | 9804 | if (current_templates->start->opcode_modifier.isstring |
c3949f43 | 9805 | && !current_templates->start->cpu_flags.bitfield.cpupadlock |
fc0763e6 JB |
9806 | && (current_templates->end[-1].opcode_modifier.isstring |
9807 | || i.mem_operands)) | |
9808 | { | |
9809 | /* Memory operands of string insns are special in that they only allow | |
9810 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 L |
9811 | const reg_entry *expected_reg; |
9812 | static const char *di_si[][2] = | |
9813 | { | |
9814 | { "esi", "edi" }, | |
9815 | { "si", "di" }, | |
9816 | { "rsi", "rdi" } | |
9817 | }; | |
9818 | static const char *bx[] = { "ebx", "bx", "rbx" }; | |
fc0763e6 JB |
9819 | |
9820 | kind = "string address"; | |
9821 | ||
8325cc63 | 9822 | if (current_templates->start->opcode_modifier.repprefixok) |
fc0763e6 JB |
9823 | { |
9824 | i386_operand_type type = current_templates->end[-1].operand_types[0]; | |
9825 | ||
9826 | if (!type.bitfield.baseindex | |
9827 | || ((!i.mem_operands != !intel_syntax) | |
9828 | && current_templates->end[-1].operand_types[1] | |
9829 | .bitfield.baseindex)) | |
9830 | type = current_templates->end[-1].operand_types[1]; | |
be05d201 L |
9831 | expected_reg = hash_find (reg_hash, |
9832 | di_si[addr_mode][type.bitfield.esseg]); | |
9833 | ||
fc0763e6 JB |
9834 | } |
9835 | else | |
be05d201 | 9836 | expected_reg = hash_find (reg_hash, bx[addr_mode]); |
fc0763e6 | 9837 | |
be05d201 L |
9838 | if (i.base_reg != expected_reg |
9839 | || i.index_reg | |
fc0763e6 | 9840 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 9841 | { |
be05d201 L |
9842 | /* The second memory operand must have the same size as |
9843 | the first one. */ | |
9844 | if (i.mem_operands | |
9845 | && i.base_reg | |
9846 | && !((addr_mode == CODE_64BIT | |
dc821c5f | 9847 | && i.base_reg->reg_type.bitfield.qword) |
be05d201 | 9848 | || (addr_mode == CODE_32BIT |
dc821c5f JB |
9849 | ? i.base_reg->reg_type.bitfield.dword |
9850 | : i.base_reg->reg_type.bitfield.word))) | |
be05d201 L |
9851 | goto bad_address; |
9852 | ||
fc0763e6 JB |
9853 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
9854 | operand_string, | |
9855 | intel_syntax ? '[' : '(', | |
9856 | register_prefix, | |
be05d201 | 9857 | expected_reg->reg_name, |
fc0763e6 | 9858 | intel_syntax ? ']' : ')'); |
be05d201 | 9859 | return 1; |
fc0763e6 | 9860 | } |
be05d201 L |
9861 | else |
9862 | return 1; | |
9863 | ||
9864 | bad_address: | |
9865 | as_bad (_("`%s' is not a valid %s expression"), | |
9866 | operand_string, kind); | |
9867 | return 0; | |
3e73aa7c JH |
9868 | } |
9869 | else | |
9870 | { | |
be05d201 L |
9871 | if (addr_mode != CODE_16BIT) |
9872 | { | |
9873 | /* 32-bit/64-bit checks. */ | |
9874 | if ((i.base_reg | |
e968fc9b JB |
9875 | && ((addr_mode == CODE_64BIT |
9876 | ? !i.base_reg->reg_type.bitfield.qword | |
9877 | : !i.base_reg->reg_type.bitfield.dword) | |
9878 | || (i.index_reg && i.base_reg->reg_num == RegIP) | |
9879 | || i.base_reg->reg_num == RegIZ)) | |
be05d201 | 9880 | || (i.index_reg |
1b54b8d7 JB |
9881 | && !i.index_reg->reg_type.bitfield.xmmword |
9882 | && !i.index_reg->reg_type.bitfield.ymmword | |
9883 | && !i.index_reg->reg_type.bitfield.zmmword | |
be05d201 | 9884 | && ((addr_mode == CODE_64BIT |
e968fc9b JB |
9885 | ? !i.index_reg->reg_type.bitfield.qword |
9886 | : !i.index_reg->reg_type.bitfield.dword) | |
be05d201 L |
9887 | || !i.index_reg->reg_type.bitfield.baseindex))) |
9888 | goto bad_address; | |
8178be5b JB |
9889 | |
9890 | /* bndmk, bndldx, and bndstx have special restrictions. */ | |
9891 | if (current_templates->start->base_opcode == 0xf30f1b | |
9892 | || (current_templates->start->base_opcode & ~1) == 0x0f1a) | |
9893 | { | |
9894 | /* They cannot use RIP-relative addressing. */ | |
e968fc9b | 9895 | if (i.base_reg && i.base_reg->reg_num == RegIP) |
8178be5b JB |
9896 | { |
9897 | as_bad (_("`%s' cannot be used here"), operand_string); | |
9898 | return 0; | |
9899 | } | |
9900 | ||
9901 | /* bndldx and bndstx ignore their scale factor. */ | |
9902 | if (current_templates->start->base_opcode != 0xf30f1b | |
9903 | && i.log2_scale_factor) | |
9904 | as_warn (_("register scaling is being ignored here")); | |
9905 | } | |
be05d201 L |
9906 | } |
9907 | else | |
3e73aa7c | 9908 | { |
be05d201 | 9909 | /* 16-bit checks. */ |
3e73aa7c | 9910 | if ((i.base_reg |
dc821c5f | 9911 | && (!i.base_reg->reg_type.bitfield.word |
40fb9820 | 9912 | || !i.base_reg->reg_type.bitfield.baseindex)) |
3e73aa7c | 9913 | || (i.index_reg |
dc821c5f | 9914 | && (!i.index_reg->reg_type.bitfield.word |
40fb9820 | 9915 | || !i.index_reg->reg_type.bitfield.baseindex |
29b0f896 AM |
9916 | || !(i.base_reg |
9917 | && i.base_reg->reg_num < 6 | |
9918 | && i.index_reg->reg_num >= 6 | |
9919 | && i.log2_scale_factor == 0)))) | |
be05d201 | 9920 | goto bad_address; |
3e73aa7c JH |
9921 | } |
9922 | } | |
be05d201 | 9923 | return 1; |
24eab124 | 9924 | } |
252b5132 | 9925 | |
43234a1e L |
9926 | /* Handle vector immediates. */ |
9927 | ||
9928 | static int | |
9929 | RC_SAE_immediate (const char *imm_start) | |
9930 | { | |
9931 | unsigned int match_found, j; | |
9932 | const char *pstr = imm_start; | |
9933 | expressionS *exp; | |
9934 | ||
9935 | if (*pstr != '{') | |
9936 | return 0; | |
9937 | ||
9938 | pstr++; | |
9939 | match_found = 0; | |
9940 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
9941 | { | |
9942 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
9943 | { | |
9944 | if (!i.rounding) | |
9945 | { | |
9946 | rc_op.type = RC_NamesTable[j].type; | |
9947 | rc_op.operand = this_operand; | |
9948 | i.rounding = &rc_op; | |
9949 | } | |
9950 | else | |
9951 | { | |
9952 | as_bad (_("duplicated `%s'"), imm_start); | |
9953 | return 0; | |
9954 | } | |
9955 | pstr += RC_NamesTable[j].len; | |
9956 | match_found = 1; | |
9957 | break; | |
9958 | } | |
9959 | } | |
9960 | if (!match_found) | |
9961 | return 0; | |
9962 | ||
9963 | if (*pstr++ != '}') | |
9964 | { | |
9965 | as_bad (_("Missing '}': '%s'"), imm_start); | |
9966 | return 0; | |
9967 | } | |
9968 | /* RC/SAE immediate string should contain nothing more. */; | |
9969 | if (*pstr != 0) | |
9970 | { | |
9971 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
9972 | return 0; | |
9973 | } | |
9974 | ||
9975 | exp = &im_expressions[i.imm_operands++]; | |
9976 | i.op[this_operand].imms = exp; | |
9977 | ||
9978 | exp->X_op = O_constant; | |
9979 | exp->X_add_number = 0; | |
9980 | exp->X_add_symbol = (symbolS *) 0; | |
9981 | exp->X_op_symbol = (symbolS *) 0; | |
9982 | ||
9983 | i.types[this_operand].bitfield.imm8 = 1; | |
9984 | return 1; | |
9985 | } | |
9986 | ||
8325cc63 JB |
9987 | /* Only string instructions can have a second memory operand, so |
9988 | reduce current_templates to just those if it contains any. */ | |
9989 | static int | |
9990 | maybe_adjust_templates (void) | |
9991 | { | |
9992 | const insn_template *t; | |
9993 | ||
9994 | gas_assert (i.mem_operands == 1); | |
9995 | ||
9996 | for (t = current_templates->start; t < current_templates->end; ++t) | |
9997 | if (t->opcode_modifier.isstring) | |
9998 | break; | |
9999 | ||
10000 | if (t < current_templates->end) | |
10001 | { | |
10002 | static templates aux_templates; | |
10003 | bfd_boolean recheck; | |
10004 | ||
10005 | aux_templates.start = t; | |
10006 | for (; t < current_templates->end; ++t) | |
10007 | if (!t->opcode_modifier.isstring) | |
10008 | break; | |
10009 | aux_templates.end = t; | |
10010 | ||
10011 | /* Determine whether to re-check the first memory operand. */ | |
10012 | recheck = (aux_templates.start != current_templates->start | |
10013 | || t != current_templates->end); | |
10014 | ||
10015 | current_templates = &aux_templates; | |
10016 | ||
10017 | if (recheck) | |
10018 | { | |
10019 | i.mem_operands = 0; | |
10020 | if (i.memop1_string != NULL | |
10021 | && i386_index_check (i.memop1_string) == 0) | |
10022 | return 0; | |
10023 | i.mem_operands = 1; | |
10024 | } | |
10025 | } | |
10026 | ||
10027 | return 1; | |
10028 | } | |
10029 | ||
fc0763e6 | 10030 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 10031 | on error. */ |
252b5132 | 10032 | |
252b5132 | 10033 | static int |
a7619375 | 10034 | i386_att_operand (char *operand_string) |
252b5132 | 10035 | { |
af6bdddf AM |
10036 | const reg_entry *r; |
10037 | char *end_op; | |
24eab124 | 10038 | char *op_string = operand_string; |
252b5132 | 10039 | |
24eab124 | 10040 | if (is_space_char (*op_string)) |
252b5132 RH |
10041 | ++op_string; |
10042 | ||
24eab124 | 10043 | /* We check for an absolute prefix (differentiating, |
47926f60 | 10044 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
10045 | if (*op_string == ABSOLUTE_PREFIX) |
10046 | { | |
10047 | ++op_string; | |
10048 | if (is_space_char (*op_string)) | |
10049 | ++op_string; | |
40fb9820 | 10050 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 | 10051 | } |
252b5132 | 10052 | |
47926f60 | 10053 | /* Check if operand is a register. */ |
4d1bb795 | 10054 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 10055 | { |
40fb9820 L |
10056 | i386_operand_type temp; |
10057 | ||
24eab124 AM |
10058 | /* Check for a segment override by searching for ':' after a |
10059 | segment register. */ | |
10060 | op_string = end_op; | |
10061 | if (is_space_char (*op_string)) | |
10062 | ++op_string; | |
00cee14f | 10063 | if (*op_string == ':' && r->reg_type.bitfield.class == SReg) |
24eab124 AM |
10064 | { |
10065 | switch (r->reg_num) | |
10066 | { | |
10067 | case 0: | |
10068 | i.seg[i.mem_operands] = &es; | |
10069 | break; | |
10070 | case 1: | |
10071 | i.seg[i.mem_operands] = &cs; | |
10072 | break; | |
10073 | case 2: | |
10074 | i.seg[i.mem_operands] = &ss; | |
10075 | break; | |
10076 | case 3: | |
10077 | i.seg[i.mem_operands] = &ds; | |
10078 | break; | |
10079 | case 4: | |
10080 | i.seg[i.mem_operands] = &fs; | |
10081 | break; | |
10082 | case 5: | |
10083 | i.seg[i.mem_operands] = &gs; | |
10084 | break; | |
10085 | } | |
252b5132 | 10086 | |
24eab124 | 10087 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
10088 | ++op_string; |
10089 | if (is_space_char (*op_string)) | |
24eab124 | 10090 | ++op_string; |
252b5132 | 10091 | |
24eab124 AM |
10092 | if (!is_digit_char (*op_string) |
10093 | && !is_identifier_char (*op_string) | |
10094 | && *op_string != '(' | |
10095 | && *op_string != ABSOLUTE_PREFIX) | |
10096 | { | |
10097 | as_bad (_("bad memory operand `%s'"), op_string); | |
10098 | return 0; | |
10099 | } | |
47926f60 | 10100 | /* Handle case of %es:*foo. */ |
24eab124 AM |
10101 | if (*op_string == ABSOLUTE_PREFIX) |
10102 | { | |
10103 | ++op_string; | |
10104 | if (is_space_char (*op_string)) | |
10105 | ++op_string; | |
40fb9820 | 10106 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 AM |
10107 | } |
10108 | goto do_memory_reference; | |
10109 | } | |
43234a1e L |
10110 | |
10111 | /* Handle vector operations. */ | |
10112 | if (*op_string == '{') | |
10113 | { | |
10114 | op_string = check_VecOperations (op_string, NULL); | |
10115 | if (op_string == NULL) | |
10116 | return 0; | |
10117 | } | |
10118 | ||
24eab124 AM |
10119 | if (*op_string) |
10120 | { | |
d0b47220 | 10121 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
10122 | return 0; |
10123 | } | |
40fb9820 L |
10124 | temp = r->reg_type; |
10125 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
10126 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
10127 | temp); | |
7d5e4556 | 10128 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 10129 | i.op[this_operand].regs = r; |
24eab124 AM |
10130 | i.reg_operands++; |
10131 | } | |
af6bdddf AM |
10132 | else if (*op_string == REGISTER_PREFIX) |
10133 | { | |
10134 | as_bad (_("bad register name `%s'"), op_string); | |
10135 | return 0; | |
10136 | } | |
24eab124 | 10137 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 10138 | { |
24eab124 | 10139 | ++op_string; |
40fb9820 | 10140 | if (i.types[this_operand].bitfield.jumpabsolute) |
24eab124 | 10141 | { |
d0b47220 | 10142 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
10143 | return 0; |
10144 | } | |
10145 | if (!i386_immediate (op_string)) | |
10146 | return 0; | |
10147 | } | |
43234a1e L |
10148 | else if (RC_SAE_immediate (operand_string)) |
10149 | { | |
10150 | /* If it is a RC or SAE immediate, do nothing. */ | |
10151 | ; | |
10152 | } | |
24eab124 AM |
10153 | else if (is_digit_char (*op_string) |
10154 | || is_identifier_char (*op_string) | |
d02603dc | 10155 | || *op_string == '"' |
e5cb08ac | 10156 | || *op_string == '(') |
24eab124 | 10157 | { |
47926f60 | 10158 | /* This is a memory reference of some sort. */ |
af6bdddf | 10159 | char *base_string; |
252b5132 | 10160 | |
47926f60 | 10161 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
10162 | char *displacement_string_start; |
10163 | char *displacement_string_end; | |
43234a1e | 10164 | char *vop_start; |
252b5132 | 10165 | |
24eab124 | 10166 | do_memory_reference: |
8325cc63 JB |
10167 | if (i.mem_operands == 1 && !maybe_adjust_templates ()) |
10168 | return 0; | |
24eab124 | 10169 | if ((i.mem_operands == 1 |
40fb9820 | 10170 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
10171 | || i.mem_operands == 2) |
10172 | { | |
10173 | as_bad (_("too many memory references for `%s'"), | |
10174 | current_templates->start->name); | |
10175 | return 0; | |
10176 | } | |
252b5132 | 10177 | |
24eab124 AM |
10178 | /* Check for base index form. We detect the base index form by |
10179 | looking for an ')' at the end of the operand, searching | |
10180 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
10181 | after the '('. */ | |
af6bdddf | 10182 | base_string = op_string + strlen (op_string); |
c3332e24 | 10183 | |
43234a1e L |
10184 | /* Handle vector operations. */ |
10185 | vop_start = strchr (op_string, '{'); | |
10186 | if (vop_start && vop_start < base_string) | |
10187 | { | |
10188 | if (check_VecOperations (vop_start, base_string) == NULL) | |
10189 | return 0; | |
10190 | base_string = vop_start; | |
10191 | } | |
10192 | ||
af6bdddf AM |
10193 | --base_string; |
10194 | if (is_space_char (*base_string)) | |
10195 | --base_string; | |
252b5132 | 10196 | |
47926f60 | 10197 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
10198 | displacement_string_start = op_string; |
10199 | displacement_string_end = base_string + 1; | |
252b5132 | 10200 | |
24eab124 AM |
10201 | if (*base_string == ')') |
10202 | { | |
af6bdddf | 10203 | char *temp_string; |
24eab124 AM |
10204 | unsigned int parens_balanced = 1; |
10205 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 10206 | equal, so this loop will not be infinite. */ |
24eab124 AM |
10207 | do |
10208 | { | |
10209 | base_string--; | |
10210 | if (*base_string == ')') | |
10211 | parens_balanced++; | |
10212 | if (*base_string == '(') | |
10213 | parens_balanced--; | |
10214 | } | |
10215 | while (parens_balanced); | |
c3332e24 | 10216 | |
af6bdddf | 10217 | temp_string = base_string; |
c3332e24 | 10218 | |
24eab124 | 10219 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
10220 | ++base_string; |
10221 | if (is_space_char (*base_string)) | |
24eab124 | 10222 | ++base_string; |
252b5132 | 10223 | |
af6bdddf | 10224 | if (*base_string == ',' |
4eed87de AM |
10225 | || ((i.base_reg = parse_register (base_string, &end_op)) |
10226 | != NULL)) | |
252b5132 | 10227 | { |
af6bdddf | 10228 | displacement_string_end = temp_string; |
252b5132 | 10229 | |
40fb9820 | 10230 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 10231 | |
af6bdddf | 10232 | if (i.base_reg) |
24eab124 | 10233 | { |
24eab124 AM |
10234 | base_string = end_op; |
10235 | if (is_space_char (*base_string)) | |
10236 | ++base_string; | |
af6bdddf AM |
10237 | } |
10238 | ||
10239 | /* There may be an index reg or scale factor here. */ | |
10240 | if (*base_string == ',') | |
10241 | { | |
10242 | ++base_string; | |
10243 | if (is_space_char (*base_string)) | |
10244 | ++base_string; | |
10245 | ||
4eed87de AM |
10246 | if ((i.index_reg = parse_register (base_string, &end_op)) |
10247 | != NULL) | |
24eab124 | 10248 | { |
af6bdddf | 10249 | base_string = end_op; |
24eab124 AM |
10250 | if (is_space_char (*base_string)) |
10251 | ++base_string; | |
af6bdddf AM |
10252 | if (*base_string == ',') |
10253 | { | |
10254 | ++base_string; | |
10255 | if (is_space_char (*base_string)) | |
10256 | ++base_string; | |
10257 | } | |
e5cb08ac | 10258 | else if (*base_string != ')') |
af6bdddf | 10259 | { |
4eed87de AM |
10260 | as_bad (_("expecting `,' or `)' " |
10261 | "after index register in `%s'"), | |
af6bdddf AM |
10262 | operand_string); |
10263 | return 0; | |
10264 | } | |
24eab124 | 10265 | } |
af6bdddf | 10266 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 10267 | { |
f76bf5e0 L |
10268 | end_op = strchr (base_string, ','); |
10269 | if (end_op) | |
10270 | *end_op = '\0'; | |
af6bdddf | 10271 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
10272 | return 0; |
10273 | } | |
252b5132 | 10274 | |
47926f60 | 10275 | /* Check for scale factor. */ |
551c1ca1 | 10276 | if (*base_string != ')') |
af6bdddf | 10277 | { |
551c1ca1 AM |
10278 | char *end_scale = i386_scale (base_string); |
10279 | ||
10280 | if (!end_scale) | |
af6bdddf | 10281 | return 0; |
24eab124 | 10282 | |
551c1ca1 | 10283 | base_string = end_scale; |
af6bdddf AM |
10284 | if (is_space_char (*base_string)) |
10285 | ++base_string; | |
10286 | if (*base_string != ')') | |
10287 | { | |
4eed87de AM |
10288 | as_bad (_("expecting `)' " |
10289 | "after scale factor in `%s'"), | |
af6bdddf AM |
10290 | operand_string); |
10291 | return 0; | |
10292 | } | |
10293 | } | |
10294 | else if (!i.index_reg) | |
24eab124 | 10295 | { |
4eed87de AM |
10296 | as_bad (_("expecting index register or scale factor " |
10297 | "after `,'; got '%c'"), | |
af6bdddf | 10298 | *base_string); |
24eab124 AM |
10299 | return 0; |
10300 | } | |
10301 | } | |
af6bdddf | 10302 | else if (*base_string != ')') |
24eab124 | 10303 | { |
4eed87de AM |
10304 | as_bad (_("expecting `,' or `)' " |
10305 | "after base register in `%s'"), | |
af6bdddf | 10306 | operand_string); |
24eab124 AM |
10307 | return 0; |
10308 | } | |
c3332e24 | 10309 | } |
af6bdddf | 10310 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 10311 | { |
f76bf5e0 L |
10312 | end_op = strchr (base_string, ','); |
10313 | if (end_op) | |
10314 | *end_op = '\0'; | |
af6bdddf | 10315 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 10316 | return 0; |
c3332e24 | 10317 | } |
24eab124 AM |
10318 | } |
10319 | ||
10320 | /* If there's an expression beginning the operand, parse it, | |
10321 | assuming displacement_string_start and | |
10322 | displacement_string_end are meaningful. */ | |
10323 | if (displacement_string_start != displacement_string_end) | |
10324 | { | |
10325 | if (!i386_displacement (displacement_string_start, | |
10326 | displacement_string_end)) | |
10327 | return 0; | |
10328 | } | |
10329 | ||
10330 | /* Special case for (%dx) while doing input/output op. */ | |
10331 | if (i.base_reg | |
2fb5be8d | 10332 | && i.base_reg->reg_type.bitfield.inoutportreg |
24eab124 AM |
10333 | && i.index_reg == 0 |
10334 | && i.log2_scale_factor == 0 | |
10335 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 10336 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 10337 | { |
2fb5be8d | 10338 | i.types[this_operand] = i.base_reg->reg_type; |
24eab124 AM |
10339 | return 1; |
10340 | } | |
10341 | ||
eecb386c AM |
10342 | if (i386_index_check (operand_string) == 0) |
10343 | return 0; | |
c48dadc9 | 10344 | i.flags[this_operand] |= Operand_Mem; |
8325cc63 JB |
10345 | if (i.mem_operands == 0) |
10346 | i.memop1_string = xstrdup (operand_string); | |
24eab124 AM |
10347 | i.mem_operands++; |
10348 | } | |
10349 | else | |
ce8a8b2f AM |
10350 | { |
10351 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
10352 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
10353 | output_invalid (*op_string), | |
10354 | this_operand + 1, | |
10355 | op_string); | |
10356 | return 0; | |
10357 | } | |
47926f60 | 10358 | return 1; /* Normal return. */ |
252b5132 RH |
10359 | } |
10360 | \f | |
fa94de6b RM |
10361 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
10362 | that an rs_machine_dependent frag may reach. */ | |
10363 | ||
10364 | unsigned int | |
10365 | i386_frag_max_var (fragS *frag) | |
10366 | { | |
10367 | /* The only relaxable frags are for jumps. | |
10368 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
10369 | gas_assert (frag->fr_type == rs_machine_dependent); | |
10370 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
10371 | } | |
10372 | ||
b084df0b L |
10373 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10374 | static int | |
8dcea932 | 10375 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
10376 | { |
10377 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
10378 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
10379 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
10380 | return 0; | |
10381 | ||
10382 | if (!S_IS_EXTERNAL (fr_symbol)) | |
10383 | /* Symbol may be weak or local. */ | |
10384 | return !S_IS_WEAK (fr_symbol); | |
10385 | ||
8dcea932 L |
10386 | /* Global symbols with non-default visibility can't be preempted. */ |
10387 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
10388 | return 1; | |
10389 | ||
10390 | if (fr_var != NO_RELOC) | |
10391 | switch ((enum bfd_reloc_code_real) fr_var) | |
10392 | { | |
10393 | case BFD_RELOC_386_PLT32: | |
10394 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 10395 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
10396 | return 0; |
10397 | default: | |
10398 | abort (); | |
10399 | } | |
10400 | ||
b084df0b L |
10401 | /* Global symbols with default visibility in a shared library may be |
10402 | preempted by another definition. */ | |
8dcea932 | 10403 | return !shared; |
b084df0b L |
10404 | } |
10405 | #endif | |
10406 | ||
ee7fcc42 AM |
10407 | /* md_estimate_size_before_relax() |
10408 | ||
10409 | Called just before relax() for rs_machine_dependent frags. The x86 | |
10410 | assembler uses these frags to handle variable size jump | |
10411 | instructions. | |
10412 | ||
10413 | Any symbol that is now undefined will not become defined. | |
10414 | Return the correct fr_subtype in the frag. | |
10415 | Return the initial "guess for variable size of frag" to caller. | |
10416 | The guess is actually the growth beyond the fixed part. Whatever | |
10417 | we do to grow the fixed or variable part contributes to our | |
10418 | returned value. */ | |
10419 | ||
252b5132 | 10420 | int |
7016a5d5 | 10421 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 10422 | { |
252b5132 | 10423 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
10424 | check for un-relaxable symbols. On an ELF system, we can't relax |
10425 | an externally visible symbol, because it may be overridden by a | |
10426 | shared library. */ | |
10427 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 10428 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 10429 | || (IS_ELF |
8dcea932 L |
10430 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
10431 | fragP->fr_var)) | |
fbeb56a4 DK |
10432 | #endif |
10433 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 10434 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 10435 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
10436 | #endif |
10437 | ) | |
252b5132 | 10438 | { |
b98ef147 AM |
10439 | /* Symbol is undefined in this segment, or we need to keep a |
10440 | reloc so that weak symbols can be overridden. */ | |
10441 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 10442 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
10443 | unsigned char *opcode; |
10444 | int old_fr_fix; | |
f6af82bd | 10445 | |
ee7fcc42 | 10446 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 10447 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 10448 | else if (size == 2) |
f6af82bd | 10449 | reloc_type = BFD_RELOC_16_PCREL; |
bd7ab16b L |
10450 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10451 | else if (need_plt32_p (fragP->fr_symbol)) | |
10452 | reloc_type = BFD_RELOC_X86_64_PLT32; | |
10453 | #endif | |
f6af82bd AM |
10454 | else |
10455 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 10456 | |
ee7fcc42 AM |
10457 | old_fr_fix = fragP->fr_fix; |
10458 | opcode = (unsigned char *) fragP->fr_opcode; | |
10459 | ||
fddf5b5b | 10460 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 10461 | { |
fddf5b5b AM |
10462 | case UNCOND_JUMP: |
10463 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 10464 | opcode[0] = 0xe9; |
252b5132 | 10465 | fragP->fr_fix += size; |
062cd5e7 AS |
10466 | fix_new (fragP, old_fr_fix, size, |
10467 | fragP->fr_symbol, | |
10468 | fragP->fr_offset, 1, | |
10469 | reloc_type); | |
252b5132 RH |
10470 | break; |
10471 | ||
fddf5b5b | 10472 | case COND_JUMP86: |
412167cb AM |
10473 | if (size == 2 |
10474 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
10475 | { |
10476 | /* Negate the condition, and branch past an | |
10477 | unconditional jump. */ | |
10478 | opcode[0] ^= 1; | |
10479 | opcode[1] = 3; | |
10480 | /* Insert an unconditional jump. */ | |
10481 | opcode[2] = 0xe9; | |
10482 | /* We added two extra opcode bytes, and have a two byte | |
10483 | offset. */ | |
10484 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
10485 | fix_new (fragP, old_fr_fix + 2, 2, |
10486 | fragP->fr_symbol, | |
10487 | fragP->fr_offset, 1, | |
10488 | reloc_type); | |
fddf5b5b AM |
10489 | break; |
10490 | } | |
10491 | /* Fall through. */ | |
10492 | ||
10493 | case COND_JUMP: | |
412167cb AM |
10494 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
10495 | { | |
3e02c1cc AM |
10496 | fixS *fixP; |
10497 | ||
412167cb | 10498 | fragP->fr_fix += 1; |
3e02c1cc AM |
10499 | fixP = fix_new (fragP, old_fr_fix, 1, |
10500 | fragP->fr_symbol, | |
10501 | fragP->fr_offset, 1, | |
10502 | BFD_RELOC_8_PCREL); | |
10503 | fixP->fx_signed = 1; | |
412167cb AM |
10504 | break; |
10505 | } | |
93c2a809 | 10506 | |
24eab124 | 10507 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 10508 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 10509 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 10510 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
10511 | /* We've added an opcode byte. */ |
10512 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
10513 | fix_new (fragP, old_fr_fix + 1, size, |
10514 | fragP->fr_symbol, | |
10515 | fragP->fr_offset, 1, | |
10516 | reloc_type); | |
252b5132 | 10517 | break; |
fddf5b5b AM |
10518 | |
10519 | default: | |
10520 | BAD_CASE (fragP->fr_subtype); | |
10521 | break; | |
252b5132 RH |
10522 | } |
10523 | frag_wane (fragP); | |
ee7fcc42 | 10524 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 10525 | } |
93c2a809 | 10526 | |
93c2a809 AM |
10527 | /* Guess size depending on current relax state. Initially the relax |
10528 | state will correspond to a short jump and we return 1, because | |
10529 | the variable part of the frag (the branch offset) is one byte | |
10530 | long. However, we can relax a section more than once and in that | |
10531 | case we must either set fr_subtype back to the unrelaxed state, | |
10532 | or return the value for the appropriate branch. */ | |
10533 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
10534 | } |
10535 | ||
47926f60 KH |
10536 | /* Called after relax() is finished. |
10537 | ||
10538 | In: Address of frag. | |
10539 | fr_type == rs_machine_dependent. | |
10540 | fr_subtype is what the address relaxed to. | |
10541 | ||
10542 | Out: Any fixSs and constants are set up. | |
10543 | Caller will turn frag into a ".space 0". */ | |
10544 | ||
252b5132 | 10545 | void |
7016a5d5 TG |
10546 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
10547 | fragS *fragP) | |
252b5132 | 10548 | { |
29b0f896 | 10549 | unsigned char *opcode; |
252b5132 | 10550 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
10551 | offsetT target_address; |
10552 | offsetT opcode_address; | |
252b5132 | 10553 | unsigned int extension = 0; |
847f7ad4 | 10554 | offsetT displacement_from_opcode_start; |
252b5132 RH |
10555 | |
10556 | opcode = (unsigned char *) fragP->fr_opcode; | |
10557 | ||
47926f60 | 10558 | /* Address we want to reach in file space. */ |
252b5132 | 10559 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 10560 | |
47926f60 | 10561 | /* Address opcode resides at in file space. */ |
252b5132 RH |
10562 | opcode_address = fragP->fr_address + fragP->fr_fix; |
10563 | ||
47926f60 | 10564 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
10565 | displacement_from_opcode_start = target_address - opcode_address; |
10566 | ||
fddf5b5b | 10567 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 10568 | { |
47926f60 KH |
10569 | /* Don't have to change opcode. */ |
10570 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 10571 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
10572 | } |
10573 | else | |
10574 | { | |
10575 | if (no_cond_jump_promotion | |
10576 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
10577 | as_warn_where (fragP->fr_file, fragP->fr_line, |
10578 | _("long jump required")); | |
252b5132 | 10579 | |
fddf5b5b AM |
10580 | switch (fragP->fr_subtype) |
10581 | { | |
10582 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
10583 | extension = 4; /* 1 opcode + 4 displacement */ | |
10584 | opcode[0] = 0xe9; | |
10585 | where_to_put_displacement = &opcode[1]; | |
10586 | break; | |
252b5132 | 10587 | |
fddf5b5b AM |
10588 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
10589 | extension = 2; /* 1 opcode + 2 displacement */ | |
10590 | opcode[0] = 0xe9; | |
10591 | where_to_put_displacement = &opcode[1]; | |
10592 | break; | |
252b5132 | 10593 | |
fddf5b5b AM |
10594 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
10595 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
10596 | extension = 5; /* 2 opcode + 4 displacement */ | |
10597 | opcode[1] = opcode[0] + 0x10; | |
10598 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
10599 | where_to_put_displacement = &opcode[2]; | |
10600 | break; | |
252b5132 | 10601 | |
fddf5b5b AM |
10602 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
10603 | extension = 3; /* 2 opcode + 2 displacement */ | |
10604 | opcode[1] = opcode[0] + 0x10; | |
10605 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
10606 | where_to_put_displacement = &opcode[2]; | |
10607 | break; | |
252b5132 | 10608 | |
fddf5b5b AM |
10609 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
10610 | extension = 4; | |
10611 | opcode[0] ^= 1; | |
10612 | opcode[1] = 3; | |
10613 | opcode[2] = 0xe9; | |
10614 | where_to_put_displacement = &opcode[3]; | |
10615 | break; | |
10616 | ||
10617 | default: | |
10618 | BAD_CASE (fragP->fr_subtype); | |
10619 | break; | |
10620 | } | |
252b5132 | 10621 | } |
fddf5b5b | 10622 | |
7b81dfbb AJ |
10623 | /* If size if less then four we are sure that the operand fits, |
10624 | but if it's 4, then it could be that the displacement is larger | |
10625 | then -/+ 2GB. */ | |
10626 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
10627 | && object_64bit | |
10628 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
10629 | + ((addressT) 1 << 31)) |
10630 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
10631 | { |
10632 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
10633 | _("jump target out of range")); | |
10634 | /* Make us emit 0. */ | |
10635 | displacement_from_opcode_start = extension; | |
10636 | } | |
47926f60 | 10637 | /* Now put displacement after opcode. */ |
252b5132 RH |
10638 | md_number_to_chars ((char *) where_to_put_displacement, |
10639 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 10640 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
10641 | fragP->fr_fix += extension; |
10642 | } | |
10643 | \f | |
7016a5d5 | 10644 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
10645 | by our caller that we have all the info we need to fix it up. |
10646 | ||
7016a5d5 TG |
10647 | Parameter valP is the pointer to the value of the bits. |
10648 | ||
252b5132 RH |
10649 | On the 386, immediates, displacements, and data pointers are all in |
10650 | the same (little-endian) format, so we don't need to care about which | |
10651 | we are handling. */ | |
10652 | ||
94f592af | 10653 | void |
7016a5d5 | 10654 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 10655 | { |
94f592af | 10656 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 10657 | valueT value = *valP; |
252b5132 | 10658 | |
f86103b7 | 10659 | #if !defined (TE_Mach) |
93382f6d AM |
10660 | if (fixP->fx_pcrel) |
10661 | { | |
10662 | switch (fixP->fx_r_type) | |
10663 | { | |
5865bb77 ILT |
10664 | default: |
10665 | break; | |
10666 | ||
d6ab8113 JB |
10667 | case BFD_RELOC_64: |
10668 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
10669 | break; | |
93382f6d | 10670 | case BFD_RELOC_32: |
ae8887b5 | 10671 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
10672 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
10673 | break; | |
10674 | case BFD_RELOC_16: | |
10675 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
10676 | break; | |
10677 | case BFD_RELOC_8: | |
10678 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
10679 | break; | |
10680 | } | |
10681 | } | |
252b5132 | 10682 | |
a161fe53 | 10683 | if (fixP->fx_addsy != NULL |
31312f95 | 10684 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 10685 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 10686 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 10687 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 10688 | && !use_rela_relocations) |
252b5132 | 10689 | { |
31312f95 AM |
10690 | /* This is a hack. There should be a better way to handle this. |
10691 | This covers for the fact that bfd_install_relocation will | |
10692 | subtract the current location (for partial_inplace, PC relative | |
10693 | relocations); see more below. */ | |
252b5132 | 10694 | #ifndef OBJ_AOUT |
718ddfc0 | 10695 | if (IS_ELF |
252b5132 RH |
10696 | #ifdef TE_PE |
10697 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
10698 | #endif | |
10699 | ) | |
10700 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
10701 | #endif | |
10702 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 10703 | if (IS_ELF) |
252b5132 | 10704 | { |
6539b54b | 10705 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 10706 | |
6539b54b | 10707 | if ((sym_seg == seg |
2f66722d | 10708 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 10709 | && sym_seg != absolute_section)) |
af65af87 | 10710 | && !generic_force_reloc (fixP)) |
2f66722d AM |
10711 | { |
10712 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
10713 | bfd_install_relocation subtracts them out again. I think |
10714 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
10715 | it. FIXME. */ |
10716 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
10717 | } | |
252b5132 RH |
10718 | } |
10719 | #endif | |
10720 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
10721 | /* For some reason, the PE format does not store a |
10722 | section address offset for a PC relative symbol. */ | |
10723 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 10724 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
10725 | value += md_pcrel_from (fixP); |
10726 | #endif | |
10727 | } | |
fbeb56a4 | 10728 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
10729 | if (fixP->fx_addsy != NULL |
10730 | && S_IS_WEAK (fixP->fx_addsy) | |
10731 | /* PR 16858: Do not modify weak function references. */ | |
10732 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 10733 | { |
296a8689 NC |
10734 | #if !defined (TE_PEP) |
10735 | /* For x86 PE weak function symbols are neither PC-relative | |
10736 | nor do they set S_IS_FUNCTION. So the only reliable way | |
10737 | to detect them is to check the flags of their containing | |
10738 | section. */ | |
10739 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
10740 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
10741 | ; | |
10742 | else | |
10743 | #endif | |
fbeb56a4 DK |
10744 | value -= S_GET_VALUE (fixP->fx_addsy); |
10745 | } | |
10746 | #endif | |
252b5132 RH |
10747 | |
10748 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 10749 | and we must not disappoint it. */ |
252b5132 | 10750 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 10751 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
10752 | switch (fixP->fx_r_type) |
10753 | { | |
10754 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 10755 | case BFD_RELOC_X86_64_PLT32: |
b9519cfe L |
10756 | /* Make the jump instruction point to the address of the operand. |
10757 | At runtime we merely add the offset to the actual PLT entry. | |
10758 | NB: Subtract the offset size only for jump instructions. */ | |
10759 | if (fixP->fx_pcrel) | |
10760 | value = -4; | |
47926f60 | 10761 | break; |
31312f95 | 10762 | |
13ae64f3 JJ |
10763 | case BFD_RELOC_386_TLS_GD: |
10764 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 10765 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
10766 | case BFD_RELOC_386_TLS_IE: |
10767 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 10768 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
10769 | case BFD_RELOC_X86_64_TLSGD: |
10770 | case BFD_RELOC_X86_64_TLSLD: | |
10771 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 10772 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
10773 | value = 0; /* Fully resolved at runtime. No addend. */ |
10774 | /* Fallthrough */ | |
10775 | case BFD_RELOC_386_TLS_LE: | |
10776 | case BFD_RELOC_386_TLS_LDO_32: | |
10777 | case BFD_RELOC_386_TLS_LE_32: | |
10778 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 10779 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 10780 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 10781 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
10782 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
10783 | break; | |
10784 | ||
67a4f2b7 AO |
10785 | case BFD_RELOC_386_TLS_DESC_CALL: |
10786 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
10787 | value = 0; /* Fully resolved at runtime. No addend. */ | |
10788 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
10789 | fixP->fx_done = 0; | |
10790 | return; | |
10791 | ||
47926f60 KH |
10792 | case BFD_RELOC_VTABLE_INHERIT: |
10793 | case BFD_RELOC_VTABLE_ENTRY: | |
10794 | fixP->fx_done = 0; | |
94f592af | 10795 | return; |
47926f60 KH |
10796 | |
10797 | default: | |
10798 | break; | |
10799 | } | |
10800 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 10801 | *valP = value; |
f86103b7 | 10802 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 10803 | |
3e73aa7c | 10804 | /* Are we finished with this relocation now? */ |
c6682705 | 10805 | if (fixP->fx_addsy == NULL) |
3e73aa7c | 10806 | fixP->fx_done = 1; |
fbeb56a4 DK |
10807 | #if defined (OBJ_COFF) && defined (TE_PE) |
10808 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
10809 | { | |
10810 | fixP->fx_done = 0; | |
10811 | /* Remember value for tc_gen_reloc. */ | |
10812 | fixP->fx_addnumber = value; | |
10813 | /* Clear out the frag for now. */ | |
10814 | value = 0; | |
10815 | } | |
10816 | #endif | |
3e73aa7c JH |
10817 | else if (use_rela_relocations) |
10818 | { | |
10819 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
10820 | /* Remember value for tc_gen_reloc. */ |
10821 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
10822 | value = 0; |
10823 | } | |
f86103b7 | 10824 | |
94f592af | 10825 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 10826 | } |
252b5132 | 10827 | \f |
6d4af3c2 | 10828 | const char * |
499ac353 | 10829 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 10830 | { |
499ac353 NC |
10831 | /* This outputs the LITTLENUMs in REVERSE order; |
10832 | in accord with the bigendian 386. */ | |
10833 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
10834 | } |
10835 | \f | |
2d545b82 | 10836 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 10837 | |
252b5132 | 10838 | static char * |
e3bb37b5 | 10839 | output_invalid (int c) |
252b5132 | 10840 | { |
3882b010 | 10841 | if (ISPRINT (c)) |
f9f21a03 L |
10842 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
10843 | "'%c'", c); | |
252b5132 | 10844 | else |
f9f21a03 | 10845 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 10846 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
10847 | return output_invalid_buf; |
10848 | } | |
10849 | ||
af6bdddf | 10850 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
10851 | |
10852 | static const reg_entry * | |
4d1bb795 | 10853 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 10854 | { |
af6bdddf AM |
10855 | char *s = reg_string; |
10856 | char *p; | |
252b5132 RH |
10857 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
10858 | const reg_entry *r; | |
10859 | ||
10860 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
10861 | if (*s == REGISTER_PREFIX) | |
10862 | ++s; | |
10863 | ||
10864 | if (is_space_char (*s)) | |
10865 | ++s; | |
10866 | ||
10867 | p = reg_name_given; | |
af6bdddf | 10868 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
10869 | { |
10870 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
10871 | return (const reg_entry *) NULL; |
10872 | s++; | |
252b5132 RH |
10873 | } |
10874 | ||
6588847e DN |
10875 | /* For naked regs, make sure that we are not dealing with an identifier. |
10876 | This prevents confusing an identifier like `eax_var' with register | |
10877 | `eax'. */ | |
10878 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
10879 | return (const reg_entry *) NULL; | |
10880 | ||
af6bdddf | 10881 | *end_op = s; |
252b5132 RH |
10882 | |
10883 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
10884 | ||
5f47d35b | 10885 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 10886 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 10887 | { |
0e0eea78 JB |
10888 | if (!cpu_arch_flags.bitfield.cpu8087 |
10889 | && !cpu_arch_flags.bitfield.cpu287 | |
10890 | && !cpu_arch_flags.bitfield.cpu387) | |
10891 | return (const reg_entry *) NULL; | |
10892 | ||
5f47d35b AM |
10893 | if (is_space_char (*s)) |
10894 | ++s; | |
10895 | if (*s == '(') | |
10896 | { | |
af6bdddf | 10897 | ++s; |
5f47d35b AM |
10898 | if (is_space_char (*s)) |
10899 | ++s; | |
10900 | if (*s >= '0' && *s <= '7') | |
10901 | { | |
db557034 | 10902 | int fpr = *s - '0'; |
af6bdddf | 10903 | ++s; |
5f47d35b AM |
10904 | if (is_space_char (*s)) |
10905 | ++s; | |
10906 | if (*s == ')') | |
10907 | { | |
10908 | *end_op = s + 1; | |
1e9cc1c2 | 10909 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
db557034 AM |
10910 | know (r); |
10911 | return r + fpr; | |
5f47d35b | 10912 | } |
5f47d35b | 10913 | } |
47926f60 | 10914 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
10915 | return (const reg_entry *) NULL; |
10916 | } | |
10917 | } | |
10918 | ||
a60de03c JB |
10919 | if (r == NULL || allow_pseudo_reg) |
10920 | return r; | |
10921 | ||
0dfbf9d7 | 10922 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
10923 | return (const reg_entry *) NULL; |
10924 | ||
dc821c5f | 10925 | if ((r->reg_type.bitfield.dword |
00cee14f | 10926 | || (r->reg_type.bitfield.class == SReg && r->reg_num > 3) |
4a5c67ed JB |
10927 | || r->reg_type.bitfield.class == RegCR |
10928 | || r->reg_type.bitfield.class == RegDR | |
10929 | || r->reg_type.bitfield.class == RegTR) | |
192dc9c6 JB |
10930 | && !cpu_arch_flags.bitfield.cpui386) |
10931 | return (const reg_entry *) NULL; | |
10932 | ||
3528c362 | 10933 | if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx) |
192dc9c6 JB |
10934 | return (const reg_entry *) NULL; |
10935 | ||
6e041cf4 JB |
10936 | if (!cpu_arch_flags.bitfield.cpuavx512f) |
10937 | { | |
10938 | if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask) | |
10939 | return (const reg_entry *) NULL; | |
40f12533 | 10940 | |
6e041cf4 JB |
10941 | if (!cpu_arch_flags.bitfield.cpuavx) |
10942 | { | |
10943 | if (r->reg_type.bitfield.ymmword) | |
10944 | return (const reg_entry *) NULL; | |
1848e567 | 10945 | |
6e041cf4 JB |
10946 | if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword) |
10947 | return (const reg_entry *) NULL; | |
10948 | } | |
10949 | } | |
43234a1e | 10950 | |
1adf7f56 JB |
10951 | if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx) |
10952 | return (const reg_entry *) NULL; | |
10953 | ||
db51cc60 | 10954 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
e968fc9b | 10955 | if (!allow_index_reg && r->reg_num == RegIZ) |
db51cc60 L |
10956 | return (const reg_entry *) NULL; |
10957 | ||
1d3f8286 JB |
10958 | /* Upper 16 vector registers are only available with VREX in 64bit |
10959 | mode, and require EVEX encoding. */ | |
10960 | if (r->reg_flags & RegVRex) | |
43234a1e | 10961 | { |
e951d5ca | 10962 | if (!cpu_arch_flags.bitfield.cpuavx512f |
43234a1e L |
10963 | || flag_code != CODE_64BIT) |
10964 | return (const reg_entry *) NULL; | |
1d3f8286 JB |
10965 | |
10966 | i.vec_encoding = vex_encoding_evex; | |
43234a1e L |
10967 | } |
10968 | ||
4787f4a5 | 10969 | if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword) |
4a5c67ed | 10970 | && (!cpu_arch_flags.bitfield.cpulm || r->reg_type.bitfield.class != RegCR) |
1ae00879 | 10971 | && flag_code != CODE_64BIT) |
20f0a1fc | 10972 | return (const reg_entry *) NULL; |
1ae00879 | 10973 | |
00cee14f JB |
10974 | if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat |
10975 | && !intel_syntax) | |
b7240065 JB |
10976 | return (const reg_entry *) NULL; |
10977 | ||
252b5132 RH |
10978 | return r; |
10979 | } | |
4d1bb795 JB |
10980 | |
10981 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
10982 | ||
10983 | static const reg_entry * | |
10984 | parse_register (char *reg_string, char **end_op) | |
10985 | { | |
10986 | const reg_entry *r; | |
10987 | ||
10988 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
10989 | r = parse_real_register (reg_string, end_op); | |
10990 | else | |
10991 | r = NULL; | |
10992 | if (!r) | |
10993 | { | |
10994 | char *save = input_line_pointer; | |
10995 | char c; | |
10996 | symbolS *symbolP; | |
10997 | ||
10998 | input_line_pointer = reg_string; | |
d02603dc | 10999 | c = get_symbol_name (®_string); |
4d1bb795 JB |
11000 | symbolP = symbol_find (reg_string); |
11001 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
11002 | { | |
11003 | const expressionS *e = symbol_get_value_expression (symbolP); | |
11004 | ||
0398aac5 | 11005 | know (e->X_op == O_register); |
4eed87de | 11006 | know (e->X_add_number >= 0 |
c3fe08fa | 11007 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 | 11008 | r = i386_regtab + e->X_add_number; |
d3bb6b49 | 11009 | if ((r->reg_flags & RegVRex)) |
86fa6981 | 11010 | i.vec_encoding = vex_encoding_evex; |
4d1bb795 JB |
11011 | *end_op = input_line_pointer; |
11012 | } | |
11013 | *input_line_pointer = c; | |
11014 | input_line_pointer = save; | |
11015 | } | |
11016 | return r; | |
11017 | } | |
11018 | ||
11019 | int | |
11020 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
11021 | { | |
11022 | const reg_entry *r; | |
11023 | char *end = input_line_pointer; | |
11024 | ||
11025 | *end = *nextcharP; | |
11026 | r = parse_register (name, &input_line_pointer); | |
11027 | if (r && end <= input_line_pointer) | |
11028 | { | |
11029 | *nextcharP = *input_line_pointer; | |
11030 | *input_line_pointer = 0; | |
11031 | e->X_op = O_register; | |
11032 | e->X_add_number = r - i386_regtab; | |
11033 | return 1; | |
11034 | } | |
11035 | input_line_pointer = end; | |
11036 | *end = 0; | |
ee86248c | 11037 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
11038 | } |
11039 | ||
11040 | void | |
11041 | md_operand (expressionS *e) | |
11042 | { | |
ee86248c JB |
11043 | char *end; |
11044 | const reg_entry *r; | |
4d1bb795 | 11045 | |
ee86248c JB |
11046 | switch (*input_line_pointer) |
11047 | { | |
11048 | case REGISTER_PREFIX: | |
11049 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
11050 | if (r) |
11051 | { | |
11052 | e->X_op = O_register; | |
11053 | e->X_add_number = r - i386_regtab; | |
11054 | input_line_pointer = end; | |
11055 | } | |
ee86248c JB |
11056 | break; |
11057 | ||
11058 | case '[': | |
9c2799c2 | 11059 | gas_assert (intel_syntax); |
ee86248c JB |
11060 | end = input_line_pointer++; |
11061 | expression (e); | |
11062 | if (*input_line_pointer == ']') | |
11063 | { | |
11064 | ++input_line_pointer; | |
11065 | e->X_op_symbol = make_expr_symbol (e); | |
11066 | e->X_add_symbol = NULL; | |
11067 | e->X_add_number = 0; | |
11068 | e->X_op = O_index; | |
11069 | } | |
11070 | else | |
11071 | { | |
11072 | e->X_op = O_absent; | |
11073 | input_line_pointer = end; | |
11074 | } | |
11075 | break; | |
4d1bb795 JB |
11076 | } |
11077 | } | |
11078 | ||
252b5132 | 11079 | \f |
4cc782b5 | 11080 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b6f8c7c4 | 11081 | const char *md_shortopts = "kVQ:sqnO::"; |
252b5132 | 11082 | #else |
b6f8c7c4 | 11083 | const char *md_shortopts = "qnO::"; |
252b5132 | 11084 | #endif |
6e0b89ee | 11085 | |
3e73aa7c | 11086 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
11087 | #define OPTION_64 (OPTION_MD_BASE + 1) |
11088 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
11089 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
11090 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
11091 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
11092 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
11093 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
11094 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
bd5dea88 | 11095 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9) |
c0f3af97 | 11096 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 11097 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
11098 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
11099 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
11100 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 11101 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
11102 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
11103 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 11104 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 11105 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 11106 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 11107 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
11108 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
11109 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 11110 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
b4a3a7b4 | 11111 | #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25) |
03751133 | 11112 | #define OPTION_MVEXWIG (OPTION_MD_BASE + 26) |
b3b91714 | 11113 | |
99ad8390 NC |
11114 | struct option md_longopts[] = |
11115 | { | |
3e73aa7c | 11116 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 11117 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 11118 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 11119 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
11120 | #endif |
11121 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 11122 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 11123 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
b4a3a7b4 | 11124 | {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE}, |
6e0b89ee | 11125 | #endif |
b3b91714 | 11126 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
11127 | {"march", required_argument, NULL, OPTION_MARCH}, |
11128 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
11129 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
11130 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
11131 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
11132 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
c0f3af97 | 11133 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 11134 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 11135 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 11136 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
03751133 | 11137 | {"mvexwig", required_argument, NULL, OPTION_MVEXWIG}, |
7e8b059b | 11138 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
11139 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
11140 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
11141 | # if defined (TE_PE) || defined (TE_PEP) |
11142 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
11143 | #endif | |
d1982f93 | 11144 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 11145 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 11146 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 11147 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
5db04b09 L |
11148 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
11149 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
11150 | {NULL, no_argument, NULL, 0} |
11151 | }; | |
11152 | size_t md_longopts_size = sizeof (md_longopts); | |
11153 | ||
11154 | int | |
17b9d67d | 11155 | md_parse_option (int c, const char *arg) |
252b5132 | 11156 | { |
91d6fa6a | 11157 | unsigned int j; |
293f5f65 | 11158 | char *arch, *next, *saved; |
9103f4f4 | 11159 | |
252b5132 RH |
11160 | switch (c) |
11161 | { | |
12b55ccc L |
11162 | case 'n': |
11163 | optimize_align_code = 0; | |
11164 | break; | |
11165 | ||
a38cf1db AM |
11166 | case 'q': |
11167 | quiet_warnings = 1; | |
252b5132 RH |
11168 | break; |
11169 | ||
11170 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
11171 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
11172 | should be emitted or not. FIXME: Not implemented. */ | |
11173 | case 'Q': | |
d4693039 JB |
11174 | if ((arg[0] != 'y' && arg[0] != 'n') || arg[1]) |
11175 | return 0; | |
252b5132 RH |
11176 | break; |
11177 | ||
11178 | /* -V: SVR4 argument to print version ID. */ | |
11179 | case 'V': | |
11180 | print_version_id (); | |
11181 | break; | |
11182 | ||
a38cf1db AM |
11183 | /* -k: Ignore for FreeBSD compatibility. */ |
11184 | case 'k': | |
252b5132 | 11185 | break; |
4cc782b5 ILT |
11186 | |
11187 | case 's': | |
11188 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 11189 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 11190 | break; |
8dcea932 L |
11191 | |
11192 | case OPTION_MSHARED: | |
11193 | shared = 1; | |
11194 | break; | |
b4a3a7b4 L |
11195 | |
11196 | case OPTION_X86_USED_NOTE: | |
11197 | if (strcasecmp (arg, "yes") == 0) | |
11198 | x86_used_note = 1; | |
11199 | else if (strcasecmp (arg, "no") == 0) | |
11200 | x86_used_note = 0; | |
11201 | else | |
11202 | as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg); | |
11203 | break; | |
11204 | ||
11205 | ||
99ad8390 | 11206 | #endif |
321098a5 | 11207 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 11208 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
11209 | case OPTION_64: |
11210 | { | |
11211 | const char **list, **l; | |
11212 | ||
3e73aa7c JH |
11213 | list = bfd_target_list (); |
11214 | for (l = list; *l != NULL; l++) | |
8620418b | 11215 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
11216 | || strcmp (*l, "coff-x86-64") == 0 |
11217 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
11218 | || strcmp (*l, "pei-x86-64") == 0 |
11219 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
11220 | { |
11221 | default_arch = "x86_64"; | |
11222 | break; | |
11223 | } | |
3e73aa7c | 11224 | if (*l == NULL) |
2b5d6a91 | 11225 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
11226 | free (list); |
11227 | } | |
11228 | break; | |
11229 | #endif | |
252b5132 | 11230 | |
351f65ca | 11231 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 11232 | case OPTION_X32: |
351f65ca L |
11233 | if (IS_ELF) |
11234 | { | |
11235 | const char **list, **l; | |
11236 | ||
11237 | list = bfd_target_list (); | |
11238 | for (l = list; *l != NULL; l++) | |
11239 | if (CONST_STRNEQ (*l, "elf32-x86-64")) | |
11240 | { | |
11241 | default_arch = "x86_64:32"; | |
11242 | break; | |
11243 | } | |
11244 | if (*l == NULL) | |
2b5d6a91 | 11245 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
11246 | free (list); |
11247 | } | |
11248 | else | |
11249 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
11250 | break; | |
11251 | #endif | |
11252 | ||
6e0b89ee AM |
11253 | case OPTION_32: |
11254 | default_arch = "i386"; | |
11255 | break; | |
11256 | ||
b3b91714 AM |
11257 | case OPTION_DIVIDE: |
11258 | #ifdef SVR4_COMMENT_CHARS | |
11259 | { | |
11260 | char *n, *t; | |
11261 | const char *s; | |
11262 | ||
add39d23 | 11263 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
11264 | t = n; |
11265 | for (s = i386_comment_chars; *s != '\0'; s++) | |
11266 | if (*s != '/') | |
11267 | *t++ = *s; | |
11268 | *t = '\0'; | |
11269 | i386_comment_chars = n; | |
11270 | } | |
11271 | #endif | |
11272 | break; | |
11273 | ||
9103f4f4 | 11274 | case OPTION_MARCH: |
293f5f65 L |
11275 | saved = xstrdup (arg); |
11276 | arch = saved; | |
11277 | /* Allow -march=+nosse. */ | |
11278 | if (*arch == '+') | |
11279 | arch++; | |
6305a203 | 11280 | do |
9103f4f4 | 11281 | { |
6305a203 | 11282 | if (*arch == '.') |
2b5d6a91 | 11283 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
11284 | next = strchr (arch, '+'); |
11285 | if (next) | |
11286 | *next++ = '\0'; | |
91d6fa6a | 11287 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 11288 | { |
91d6fa6a | 11289 | if (strcmp (arch, cpu_arch [j].name) == 0) |
ccc9c027 | 11290 | { |
6305a203 | 11291 | /* Processor. */ |
1ded5609 JB |
11292 | if (! cpu_arch[j].flags.bitfield.cpui386) |
11293 | continue; | |
11294 | ||
91d6fa6a | 11295 | cpu_arch_name = cpu_arch[j].name; |
6305a203 | 11296 | cpu_sub_arch_name = NULL; |
91d6fa6a NC |
11297 | cpu_arch_flags = cpu_arch[j].flags; |
11298 | cpu_arch_isa = cpu_arch[j].type; | |
11299 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
6305a203 L |
11300 | if (!cpu_arch_tune_set) |
11301 | { | |
11302 | cpu_arch_tune = cpu_arch_isa; | |
11303 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
11304 | } | |
11305 | break; | |
11306 | } | |
91d6fa6a NC |
11307 | else if (*cpu_arch [j].name == '.' |
11308 | && strcmp (arch, cpu_arch [j].name + 1) == 0) | |
6305a203 | 11309 | { |
33eaf5de | 11310 | /* ISA extension. */ |
6305a203 | 11311 | i386_cpu_flags flags; |
309d3373 | 11312 | |
293f5f65 L |
11313 | flags = cpu_flags_or (cpu_arch_flags, |
11314 | cpu_arch[j].flags); | |
81486035 | 11315 | |
5b64d091 | 11316 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
11317 | { |
11318 | if (cpu_sub_arch_name) | |
11319 | { | |
11320 | char *name = cpu_sub_arch_name; | |
11321 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 11322 | cpu_arch[j].name, |
1bf57e9f | 11323 | (const char *) NULL); |
6305a203 L |
11324 | free (name); |
11325 | } | |
11326 | else | |
91d6fa6a | 11327 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
6305a203 | 11328 | cpu_arch_flags = flags; |
a586129e | 11329 | cpu_arch_isa_flags = flags; |
6305a203 | 11330 | } |
0089dace L |
11331 | else |
11332 | cpu_arch_isa_flags | |
11333 | = cpu_flags_or (cpu_arch_isa_flags, | |
11334 | cpu_arch[j].flags); | |
6305a203 | 11335 | break; |
ccc9c027 | 11336 | } |
9103f4f4 | 11337 | } |
6305a203 | 11338 | |
293f5f65 L |
11339 | if (j >= ARRAY_SIZE (cpu_arch)) |
11340 | { | |
33eaf5de | 11341 | /* Disable an ISA extension. */ |
293f5f65 L |
11342 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
11343 | if (strcmp (arch, cpu_noarch [j].name) == 0) | |
11344 | { | |
11345 | i386_cpu_flags flags; | |
11346 | ||
11347 | flags = cpu_flags_and_not (cpu_arch_flags, | |
11348 | cpu_noarch[j].flags); | |
11349 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
11350 | { | |
11351 | if (cpu_sub_arch_name) | |
11352 | { | |
11353 | char *name = cpu_sub_arch_name; | |
11354 | cpu_sub_arch_name = concat (arch, | |
11355 | (const char *) NULL); | |
11356 | free (name); | |
11357 | } | |
11358 | else | |
11359 | cpu_sub_arch_name = xstrdup (arch); | |
11360 | cpu_arch_flags = flags; | |
11361 | cpu_arch_isa_flags = flags; | |
11362 | } | |
11363 | break; | |
11364 | } | |
11365 | ||
11366 | if (j >= ARRAY_SIZE (cpu_noarch)) | |
11367 | j = ARRAY_SIZE (cpu_arch); | |
11368 | } | |
11369 | ||
91d6fa6a | 11370 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 11371 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
11372 | |
11373 | arch = next; | |
9103f4f4 | 11374 | } |
293f5f65 L |
11375 | while (next != NULL); |
11376 | free (saved); | |
9103f4f4 L |
11377 | break; |
11378 | ||
11379 | case OPTION_MTUNE: | |
11380 | if (*arg == '.') | |
2b5d6a91 | 11381 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 11382 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 11383 | { |
91d6fa6a | 11384 | if (strcmp (arg, cpu_arch [j].name) == 0) |
9103f4f4 | 11385 | { |
ccc9c027 | 11386 | cpu_arch_tune_set = 1; |
91d6fa6a NC |
11387 | cpu_arch_tune = cpu_arch [j].type; |
11388 | cpu_arch_tune_flags = cpu_arch[j].flags; | |
9103f4f4 L |
11389 | break; |
11390 | } | |
11391 | } | |
91d6fa6a | 11392 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 11393 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
11394 | break; |
11395 | ||
1efbbeb4 L |
11396 | case OPTION_MMNEMONIC: |
11397 | if (strcasecmp (arg, "att") == 0) | |
11398 | intel_mnemonic = 0; | |
11399 | else if (strcasecmp (arg, "intel") == 0) | |
11400 | intel_mnemonic = 1; | |
11401 | else | |
2b5d6a91 | 11402 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
11403 | break; |
11404 | ||
11405 | case OPTION_MSYNTAX: | |
11406 | if (strcasecmp (arg, "att") == 0) | |
11407 | intel_syntax = 0; | |
11408 | else if (strcasecmp (arg, "intel") == 0) | |
11409 | intel_syntax = 1; | |
11410 | else | |
2b5d6a91 | 11411 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
11412 | break; |
11413 | ||
11414 | case OPTION_MINDEX_REG: | |
11415 | allow_index_reg = 1; | |
11416 | break; | |
11417 | ||
11418 | case OPTION_MNAKED_REG: | |
11419 | allow_naked_reg = 1; | |
11420 | break; | |
11421 | ||
c0f3af97 L |
11422 | case OPTION_MSSE2AVX: |
11423 | sse2avx = 1; | |
11424 | break; | |
11425 | ||
daf50ae7 L |
11426 | case OPTION_MSSE_CHECK: |
11427 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 11428 | sse_check = check_error; |
daf50ae7 | 11429 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 11430 | sse_check = check_warning; |
daf50ae7 | 11431 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 11432 | sse_check = check_none; |
daf50ae7 | 11433 | else |
2b5d6a91 | 11434 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
11435 | break; |
11436 | ||
7bab8ab5 JB |
11437 | case OPTION_MOPERAND_CHECK: |
11438 | if (strcasecmp (arg, "error") == 0) | |
11439 | operand_check = check_error; | |
11440 | else if (strcasecmp (arg, "warning") == 0) | |
11441 | operand_check = check_warning; | |
11442 | else if (strcasecmp (arg, "none") == 0) | |
11443 | operand_check = check_none; | |
11444 | else | |
11445 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
11446 | break; | |
11447 | ||
539f890d L |
11448 | case OPTION_MAVXSCALAR: |
11449 | if (strcasecmp (arg, "128") == 0) | |
11450 | avxscalar = vex128; | |
11451 | else if (strcasecmp (arg, "256") == 0) | |
11452 | avxscalar = vex256; | |
11453 | else | |
2b5d6a91 | 11454 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
11455 | break; |
11456 | ||
03751133 L |
11457 | case OPTION_MVEXWIG: |
11458 | if (strcmp (arg, "0") == 0) | |
40c9c8de | 11459 | vexwig = vexw0; |
03751133 | 11460 | else if (strcmp (arg, "1") == 0) |
40c9c8de | 11461 | vexwig = vexw1; |
03751133 L |
11462 | else |
11463 | as_fatal (_("invalid -mvexwig= option: `%s'"), arg); | |
11464 | break; | |
11465 | ||
7e8b059b L |
11466 | case OPTION_MADD_BND_PREFIX: |
11467 | add_bnd_prefix = 1; | |
11468 | break; | |
11469 | ||
43234a1e L |
11470 | case OPTION_MEVEXLIG: |
11471 | if (strcmp (arg, "128") == 0) | |
11472 | evexlig = evexl128; | |
11473 | else if (strcmp (arg, "256") == 0) | |
11474 | evexlig = evexl256; | |
11475 | else if (strcmp (arg, "512") == 0) | |
11476 | evexlig = evexl512; | |
11477 | else | |
11478 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
11479 | break; | |
11480 | ||
d3d3c6db IT |
11481 | case OPTION_MEVEXRCIG: |
11482 | if (strcmp (arg, "rne") == 0) | |
11483 | evexrcig = rne; | |
11484 | else if (strcmp (arg, "rd") == 0) | |
11485 | evexrcig = rd; | |
11486 | else if (strcmp (arg, "ru") == 0) | |
11487 | evexrcig = ru; | |
11488 | else if (strcmp (arg, "rz") == 0) | |
11489 | evexrcig = rz; | |
11490 | else | |
11491 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
11492 | break; | |
11493 | ||
43234a1e L |
11494 | case OPTION_MEVEXWIG: |
11495 | if (strcmp (arg, "0") == 0) | |
11496 | evexwig = evexw0; | |
11497 | else if (strcmp (arg, "1") == 0) | |
11498 | evexwig = evexw1; | |
11499 | else | |
11500 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
11501 | break; | |
11502 | ||
167ad85b TG |
11503 | # if defined (TE_PE) || defined (TE_PEP) |
11504 | case OPTION_MBIG_OBJ: | |
11505 | use_big_obj = 1; | |
11506 | break; | |
11507 | #endif | |
11508 | ||
d1982f93 | 11509 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
11510 | if (strcasecmp (arg, "yes") == 0) |
11511 | omit_lock_prefix = 1; | |
11512 | else if (strcasecmp (arg, "no") == 0) | |
11513 | omit_lock_prefix = 0; | |
11514 | else | |
11515 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
11516 | break; | |
11517 | ||
e4e00185 AS |
11518 | case OPTION_MFENCE_AS_LOCK_ADD: |
11519 | if (strcasecmp (arg, "yes") == 0) | |
11520 | avoid_fence = 1; | |
11521 | else if (strcasecmp (arg, "no") == 0) | |
11522 | avoid_fence = 0; | |
11523 | else | |
11524 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
11525 | break; | |
11526 | ||
0cb4071e L |
11527 | case OPTION_MRELAX_RELOCATIONS: |
11528 | if (strcasecmp (arg, "yes") == 0) | |
11529 | generate_relax_relocations = 1; | |
11530 | else if (strcasecmp (arg, "no") == 0) | |
11531 | generate_relax_relocations = 0; | |
11532 | else | |
11533 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
11534 | break; | |
11535 | ||
5db04b09 | 11536 | case OPTION_MAMD64: |
e89c5eaa | 11537 | intel64 = 0; |
5db04b09 L |
11538 | break; |
11539 | ||
11540 | case OPTION_MINTEL64: | |
e89c5eaa | 11541 | intel64 = 1; |
5db04b09 L |
11542 | break; |
11543 | ||
b6f8c7c4 L |
11544 | case 'O': |
11545 | if (arg == NULL) | |
11546 | { | |
11547 | optimize = 1; | |
11548 | /* Turn off -Os. */ | |
11549 | optimize_for_space = 0; | |
11550 | } | |
11551 | else if (*arg == 's') | |
11552 | { | |
11553 | optimize_for_space = 1; | |
11554 | /* Turn on all encoding optimizations. */ | |
41fd2579 | 11555 | optimize = INT_MAX; |
b6f8c7c4 L |
11556 | } |
11557 | else | |
11558 | { | |
11559 | optimize = atoi (arg); | |
11560 | /* Turn off -Os. */ | |
11561 | optimize_for_space = 0; | |
11562 | } | |
11563 | break; | |
11564 | ||
252b5132 RH |
11565 | default: |
11566 | return 0; | |
11567 | } | |
11568 | return 1; | |
11569 | } | |
11570 | ||
8a2c8fef L |
11571 | #define MESSAGE_TEMPLATE \ |
11572 | " " | |
11573 | ||
293f5f65 L |
11574 | static char * |
11575 | output_message (FILE *stream, char *p, char *message, char *start, | |
11576 | int *left_p, const char *name, int len) | |
11577 | { | |
11578 | int size = sizeof (MESSAGE_TEMPLATE); | |
11579 | int left = *left_p; | |
11580 | ||
11581 | /* Reserve 2 spaces for ", " or ",\0" */ | |
11582 | left -= len + 2; | |
11583 | ||
11584 | /* Check if there is any room. */ | |
11585 | if (left >= 0) | |
11586 | { | |
11587 | if (p != start) | |
11588 | { | |
11589 | *p++ = ','; | |
11590 | *p++ = ' '; | |
11591 | } | |
11592 | p = mempcpy (p, name, len); | |
11593 | } | |
11594 | else | |
11595 | { | |
11596 | /* Output the current message now and start a new one. */ | |
11597 | *p++ = ','; | |
11598 | *p = '\0'; | |
11599 | fprintf (stream, "%s\n", message); | |
11600 | p = start; | |
11601 | left = size - (start - message) - len - 2; | |
11602 | ||
11603 | gas_assert (left >= 0); | |
11604 | ||
11605 | p = mempcpy (p, name, len); | |
11606 | } | |
11607 | ||
11608 | *left_p = left; | |
11609 | return p; | |
11610 | } | |
11611 | ||
8a2c8fef | 11612 | static void |
1ded5609 | 11613 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
11614 | { |
11615 | static char message[] = MESSAGE_TEMPLATE; | |
11616 | char *start = message + 27; | |
11617 | char *p; | |
11618 | int size = sizeof (MESSAGE_TEMPLATE); | |
11619 | int left; | |
11620 | const char *name; | |
11621 | int len; | |
11622 | unsigned int j; | |
11623 | ||
11624 | p = start; | |
11625 | left = size - (start - message); | |
11626 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
11627 | { | |
11628 | /* Should it be skipped? */ | |
11629 | if (cpu_arch [j].skip) | |
11630 | continue; | |
11631 | ||
11632 | name = cpu_arch [j].name; | |
11633 | len = cpu_arch [j].len; | |
11634 | if (*name == '.') | |
11635 | { | |
11636 | /* It is an extension. Skip if we aren't asked to show it. */ | |
11637 | if (ext) | |
11638 | { | |
11639 | name++; | |
11640 | len--; | |
11641 | } | |
11642 | else | |
11643 | continue; | |
11644 | } | |
11645 | else if (ext) | |
11646 | { | |
11647 | /* It is an processor. Skip if we show only extension. */ | |
11648 | continue; | |
11649 | } | |
1ded5609 JB |
11650 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
11651 | { | |
11652 | /* It is an impossible processor - skip. */ | |
11653 | continue; | |
11654 | } | |
8a2c8fef | 11655 | |
293f5f65 | 11656 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
11657 | } |
11658 | ||
293f5f65 L |
11659 | /* Display disabled extensions. */ |
11660 | if (ext) | |
11661 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) | |
11662 | { | |
11663 | name = cpu_noarch [j].name; | |
11664 | len = cpu_noarch [j].len; | |
11665 | p = output_message (stream, p, message, start, &left, name, | |
11666 | len); | |
11667 | } | |
11668 | ||
8a2c8fef L |
11669 | *p = '\0'; |
11670 | fprintf (stream, "%s\n", message); | |
11671 | } | |
11672 | ||
252b5132 | 11673 | void |
8a2c8fef | 11674 | md_show_usage (FILE *stream) |
252b5132 | 11675 | { |
4cc782b5 ILT |
11676 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11677 | fprintf (stream, _("\ | |
d4693039 | 11678 | -Qy, -Qn ignored\n\ |
a38cf1db | 11679 | -V print assembler version number\n\ |
b3b91714 AM |
11680 | -k ignored\n")); |
11681 | #endif | |
11682 | fprintf (stream, _("\ | |
12b55ccc | 11683 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
11684 | -q quieten some warnings\n")); |
11685 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11686 | fprintf (stream, _("\ | |
a38cf1db | 11687 | -s ignored\n")); |
b3b91714 | 11688 | #endif |
d7f449c0 L |
11689 | #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
11690 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c | 11691 | fprintf (stream, _("\ |
570561f7 | 11692 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
751d281c | 11693 | #endif |
b3b91714 AM |
11694 | #ifdef SVR4_COMMENT_CHARS |
11695 | fprintf (stream, _("\ | |
11696 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
11697 | #else |
11698 | fprintf (stream, _("\ | |
b3b91714 | 11699 | --divide ignored\n")); |
4cc782b5 | 11700 | #endif |
9103f4f4 | 11701 | fprintf (stream, _("\ |
6305a203 | 11702 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 11703 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 11704 | show_arch (stream, 0, 1); |
8a2c8fef L |
11705 | fprintf (stream, _("\ |
11706 | EXTENSION is combination of:\n")); | |
1ded5609 | 11707 | show_arch (stream, 1, 0); |
6305a203 | 11708 | fprintf (stream, _("\ |
8a2c8fef | 11709 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 11710 | show_arch (stream, 0, 0); |
ba104c83 | 11711 | fprintf (stream, _("\ |
c0f3af97 L |
11712 | -msse2avx encode SSE instructions with VEX prefix\n")); |
11713 | fprintf (stream, _("\ | |
7c5c05ef | 11714 | -msse-check=[none|error|warning] (default: warning)\n\ |
daf50ae7 L |
11715 | check SSE instructions\n")); |
11716 | fprintf (stream, _("\ | |
7c5c05ef | 11717 | -moperand-check=[none|error|warning] (default: warning)\n\ |
7bab8ab5 JB |
11718 | check operand combinations for validity\n")); |
11719 | fprintf (stream, _("\ | |
7c5c05ef L |
11720 | -mavxscalar=[128|256] (default: 128)\n\ |
11721 | encode scalar AVX instructions with specific vector\n\ | |
539f890d L |
11722 | length\n")); |
11723 | fprintf (stream, _("\ | |
03751133 L |
11724 | -mvexwig=[0|1] (default: 0)\n\ |
11725 | encode VEX instructions with specific VEX.W value\n\ | |
11726 | for VEX.W bit ignored instructions\n")); | |
11727 | fprintf (stream, _("\ | |
7c5c05ef L |
11728 | -mevexlig=[128|256|512] (default: 128)\n\ |
11729 | encode scalar EVEX instructions with specific vector\n\ | |
43234a1e L |
11730 | length\n")); |
11731 | fprintf (stream, _("\ | |
7c5c05ef L |
11732 | -mevexwig=[0|1] (default: 0)\n\ |
11733 | encode EVEX instructions with specific EVEX.W value\n\ | |
43234a1e L |
11734 | for EVEX.W bit ignored instructions\n")); |
11735 | fprintf (stream, _("\ | |
7c5c05ef | 11736 | -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\ |
d3d3c6db IT |
11737 | encode EVEX instructions with specific EVEX.RC value\n\ |
11738 | for SAE-only ignored instructions\n")); | |
11739 | fprintf (stream, _("\ | |
7c5c05ef L |
11740 | -mmnemonic=[att|intel] ")); |
11741 | if (SYSV386_COMPAT) | |
11742 | fprintf (stream, _("(default: att)\n")); | |
11743 | else | |
11744 | fprintf (stream, _("(default: intel)\n")); | |
11745 | fprintf (stream, _("\ | |
11746 | use AT&T/Intel mnemonic\n")); | |
ba104c83 | 11747 | fprintf (stream, _("\ |
7c5c05ef L |
11748 | -msyntax=[att|intel] (default: att)\n\ |
11749 | use AT&T/Intel syntax\n")); | |
ba104c83 L |
11750 | fprintf (stream, _("\ |
11751 | -mindex-reg support pseudo index registers\n")); | |
11752 | fprintf (stream, _("\ | |
11753 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
11754 | fprintf (stream, _("\ | |
7e8b059b | 11755 | -madd-bnd-prefix add BND prefix for all valid branches\n")); |
b4a3a7b4 | 11756 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8dcea932 L |
11757 | fprintf (stream, _("\ |
11758 | -mshared disable branch optimization for shared code\n")); | |
b4a3a7b4 L |
11759 | fprintf (stream, _("\ |
11760 | -mx86-used-note=[no|yes] ")); | |
11761 | if (DEFAULT_X86_USED_NOTE) | |
11762 | fprintf (stream, _("(default: yes)\n")); | |
11763 | else | |
11764 | fprintf (stream, _("(default: no)\n")); | |
11765 | fprintf (stream, _("\ | |
11766 | generate x86 used ISA and feature properties\n")); | |
11767 | #endif | |
11768 | #if defined (TE_PE) || defined (TE_PEP) | |
167ad85b TG |
11769 | fprintf (stream, _("\ |
11770 | -mbig-obj generate big object files\n")); | |
11771 | #endif | |
d022bddd | 11772 | fprintf (stream, _("\ |
7c5c05ef | 11773 | -momit-lock-prefix=[no|yes] (default: no)\n\ |
d022bddd | 11774 | strip all lock prefixes\n")); |
5db04b09 | 11775 | fprintf (stream, _("\ |
7c5c05ef | 11776 | -mfence-as-lock-add=[no|yes] (default: no)\n\ |
e4e00185 AS |
11777 | encode lfence, mfence and sfence as\n\ |
11778 | lock addl $0x0, (%%{re}sp)\n")); | |
11779 | fprintf (stream, _("\ | |
7c5c05ef L |
11780 | -mrelax-relocations=[no|yes] ")); |
11781 | if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS) | |
11782 | fprintf (stream, _("(default: yes)\n")); | |
11783 | else | |
11784 | fprintf (stream, _("(default: no)\n")); | |
11785 | fprintf (stream, _("\ | |
0cb4071e L |
11786 | generate relax relocations\n")); |
11787 | fprintf (stream, _("\ | |
7c5c05ef | 11788 | -mamd64 accept only AMD64 ISA [default]\n")); |
5db04b09 L |
11789 | fprintf (stream, _("\ |
11790 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
11791 | } |
11792 | ||
3e73aa7c | 11793 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 11794 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 11795 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
11796 | |
11797 | /* Pick the target format to use. */ | |
11798 | ||
47926f60 | 11799 | const char * |
e3bb37b5 | 11800 | i386_target_format (void) |
252b5132 | 11801 | { |
351f65ca L |
11802 | if (!strncmp (default_arch, "x86_64", 6)) |
11803 | { | |
11804 | update_code_flag (CODE_64BIT, 1); | |
11805 | if (default_arch[6] == '\0') | |
7f56bc95 | 11806 | x86_elf_abi = X86_64_ABI; |
351f65ca | 11807 | else |
7f56bc95 | 11808 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 11809 | } |
3e73aa7c | 11810 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 11811 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
11812 | else if (!strcmp (default_arch, "iamcu")) |
11813 | { | |
11814 | update_code_flag (CODE_32BIT, 1); | |
11815 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
11816 | { | |
11817 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
11818 | cpu_arch_name = "iamcu"; | |
11819 | cpu_sub_arch_name = NULL; | |
11820 | cpu_arch_flags = iamcu_flags; | |
11821 | cpu_arch_isa = PROCESSOR_IAMCU; | |
11822 | cpu_arch_isa_flags = iamcu_flags; | |
11823 | if (!cpu_arch_tune_set) | |
11824 | { | |
11825 | cpu_arch_tune = cpu_arch_isa; | |
11826 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
11827 | } | |
11828 | } | |
8d471ec1 | 11829 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
11830 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
11831 | cpu_arch_name); | |
11832 | } | |
3e73aa7c | 11833 | else |
2b5d6a91 | 11834 | as_fatal (_("unknown architecture")); |
89507696 JB |
11835 | |
11836 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
11837 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
11838 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) | |
11839 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
11840 | ||
252b5132 RH |
11841 | switch (OUTPUT_FLAVOR) |
11842 | { | |
9384f2ff | 11843 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 11844 | case bfd_target_aout_flavour: |
47926f60 | 11845 | return AOUT_TARGET_FORMAT; |
4c63da97 | 11846 | #endif |
9384f2ff AM |
11847 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
11848 | # if defined (TE_PE) || defined (TE_PEP) | |
11849 | case bfd_target_coff_flavour: | |
167ad85b TG |
11850 | if (flag_code == CODE_64BIT) |
11851 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
11852 | else | |
11853 | return "pe-i386"; | |
9384f2ff | 11854 | # elif defined (TE_GO32) |
0561d57c JK |
11855 | case bfd_target_coff_flavour: |
11856 | return "coff-go32"; | |
9384f2ff | 11857 | # else |
252b5132 RH |
11858 | case bfd_target_coff_flavour: |
11859 | return "coff-i386"; | |
9384f2ff | 11860 | # endif |
4c63da97 | 11861 | #endif |
3e73aa7c | 11862 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 11863 | case bfd_target_elf_flavour: |
3e73aa7c | 11864 | { |
351f65ca L |
11865 | const char *format; |
11866 | ||
11867 | switch (x86_elf_abi) | |
4fa24527 | 11868 | { |
351f65ca L |
11869 | default: |
11870 | format = ELF_TARGET_FORMAT; | |
11871 | break; | |
7f56bc95 | 11872 | case X86_64_ABI: |
351f65ca | 11873 | use_rela_relocations = 1; |
4fa24527 | 11874 | object_64bit = 1; |
351f65ca L |
11875 | format = ELF_TARGET_FORMAT64; |
11876 | break; | |
7f56bc95 | 11877 | case X86_64_X32_ABI: |
4fa24527 | 11878 | use_rela_relocations = 1; |
351f65ca | 11879 | object_64bit = 1; |
862be3fb | 11880 | disallow_64bit_reloc = 1; |
351f65ca L |
11881 | format = ELF_TARGET_FORMAT32; |
11882 | break; | |
4fa24527 | 11883 | } |
3632d14b | 11884 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 11885 | { |
7f56bc95 | 11886 | if (x86_elf_abi != X86_64_ABI) |
8a9036a4 L |
11887 | as_fatal (_("Intel L1OM is 64bit only")); |
11888 | return ELF_TARGET_L1OM_FORMAT; | |
11889 | } | |
b49f93f6 | 11890 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
7a9068fe L |
11891 | { |
11892 | if (x86_elf_abi != X86_64_ABI) | |
11893 | as_fatal (_("Intel K1OM is 64bit only")); | |
11894 | return ELF_TARGET_K1OM_FORMAT; | |
11895 | } | |
81486035 L |
11896 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
11897 | { | |
11898 | if (x86_elf_abi != I386_ABI) | |
11899 | as_fatal (_("Intel MCU is 32bit only")); | |
11900 | return ELF_TARGET_IAMCU_FORMAT; | |
11901 | } | |
8a9036a4 | 11902 | else |
351f65ca | 11903 | return format; |
3e73aa7c | 11904 | } |
e57f8c65 TG |
11905 | #endif |
11906 | #if defined (OBJ_MACH_O) | |
11907 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
11908 | if (flag_code == CODE_64BIT) |
11909 | { | |
11910 | use_rela_relocations = 1; | |
11911 | object_64bit = 1; | |
11912 | return "mach-o-x86-64"; | |
11913 | } | |
11914 | else | |
11915 | return "mach-o-i386"; | |
4c63da97 | 11916 | #endif |
252b5132 RH |
11917 | default: |
11918 | abort (); | |
11919 | return NULL; | |
11920 | } | |
11921 | } | |
11922 | ||
47926f60 | 11923 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 11924 | \f |
252b5132 | 11925 | symbolS * |
7016a5d5 | 11926 | md_undefined_symbol (char *name) |
252b5132 | 11927 | { |
18dc2407 ILT |
11928 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
11929 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
11930 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
11931 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
11932 | { |
11933 | if (!GOT_symbol) | |
11934 | { | |
11935 | if (symbol_find (name)) | |
11936 | as_bad (_("GOT already in symbol table")); | |
11937 | GOT_symbol = symbol_new (name, undefined_section, | |
11938 | (valueT) 0, &zero_address_frag); | |
11939 | }; | |
11940 | return GOT_symbol; | |
11941 | } | |
252b5132 RH |
11942 | return 0; |
11943 | } | |
11944 | ||
11945 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 11946 | |
252b5132 | 11947 | valueT |
7016a5d5 | 11948 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 11949 | { |
4c63da97 AM |
11950 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
11951 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
11952 | { | |
11953 | /* For a.out, force the section size to be aligned. If we don't do | |
11954 | this, BFD will align it for us, but it will not write out the | |
11955 | final bytes of the section. This may be a bug in BFD, but it is | |
11956 | easier to fix it here since that is how the other a.out targets | |
11957 | work. */ | |
11958 | int align; | |
11959 | ||
fd361982 | 11960 | align = bfd_section_alignment (segment); |
8d3842cd | 11961 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 11962 | } |
252b5132 RH |
11963 | #endif |
11964 | ||
11965 | return size; | |
11966 | } | |
11967 | ||
11968 | /* On the i386, PC-relative offsets are relative to the start of the | |
11969 | next instruction. That is, the address of the offset, plus its | |
11970 | size, since the offset is always the last part of the insn. */ | |
11971 | ||
11972 | long | |
e3bb37b5 | 11973 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
11974 | { |
11975 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
11976 | } | |
11977 | ||
11978 | #ifndef I386COFF | |
11979 | ||
11980 | static void | |
e3bb37b5 | 11981 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 11982 | { |
29b0f896 | 11983 | int temp; |
252b5132 | 11984 | |
8a75718c JB |
11985 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11986 | if (IS_ELF) | |
11987 | obj_elf_section_change_hook (); | |
11988 | #endif | |
252b5132 RH |
11989 | temp = get_absolute_expression (); |
11990 | subseg_set (bss_section, (subsegT) temp); | |
11991 | demand_empty_rest_of_line (); | |
11992 | } | |
11993 | ||
11994 | #endif | |
11995 | ||
252b5132 | 11996 | void |
e3bb37b5 | 11997 | i386_validate_fix (fixS *fixp) |
252b5132 | 11998 | { |
02a86693 | 11999 | if (fixp->fx_subsy) |
252b5132 | 12000 | { |
02a86693 | 12001 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 12002 | { |
02a86693 L |
12003 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
12004 | { | |
12005 | if (!object_64bit) | |
12006 | abort (); | |
12007 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
12008 | if (fixp->fx_tcbit2) | |
56ceb5b5 L |
12009 | fixp->fx_r_type = (fixp->fx_tcbit |
12010 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
12011 | : BFD_RELOC_X86_64_GOTPCRELX); | |
02a86693 L |
12012 | else |
12013 | #endif | |
12014 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
12015 | } | |
d6ab8113 | 12016 | else |
02a86693 L |
12017 | { |
12018 | if (!object_64bit) | |
12019 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
12020 | else | |
12021 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
12022 | } | |
12023 | fixp->fx_subsy = 0; | |
23df1078 | 12024 | } |
252b5132 | 12025 | } |
02a86693 L |
12026 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12027 | else if (!object_64bit) | |
12028 | { | |
12029 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
12030 | && fixp->fx_tcbit2) | |
12031 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
12032 | } | |
12033 | #endif | |
252b5132 RH |
12034 | } |
12035 | ||
252b5132 | 12036 | arelent * |
7016a5d5 | 12037 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
12038 | { |
12039 | arelent *rel; | |
12040 | bfd_reloc_code_real_type code; | |
12041 | ||
12042 | switch (fixp->fx_r_type) | |
12043 | { | |
8ce3d284 | 12044 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
12045 | case BFD_RELOC_SIZE32: |
12046 | case BFD_RELOC_SIZE64: | |
12047 | if (S_IS_DEFINED (fixp->fx_addsy) | |
12048 | && !S_IS_EXTERNAL (fixp->fx_addsy)) | |
12049 | { | |
12050 | /* Resolve size relocation against local symbol to size of | |
12051 | the symbol plus addend. */ | |
12052 | valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset; | |
12053 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
12054 | && !fits_in_unsigned_long (value)) | |
12055 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12056 | _("symbol size computation overflow")); | |
12057 | fixp->fx_addsy = NULL; | |
12058 | fixp->fx_subsy = NULL; | |
12059 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
12060 | return NULL; | |
12061 | } | |
8ce3d284 | 12062 | #endif |
1a0670f3 | 12063 | /* Fall through. */ |
8fd4256d | 12064 | |
3e73aa7c JH |
12065 | case BFD_RELOC_X86_64_PLT32: |
12066 | case BFD_RELOC_X86_64_GOT32: | |
12067 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
12068 | case BFD_RELOC_X86_64_GOTPCRELX: |
12069 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
252b5132 RH |
12070 | case BFD_RELOC_386_PLT32: |
12071 | case BFD_RELOC_386_GOT32: | |
02a86693 | 12072 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
12073 | case BFD_RELOC_386_GOTOFF: |
12074 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
12075 | case BFD_RELOC_386_TLS_GD: |
12076 | case BFD_RELOC_386_TLS_LDM: | |
12077 | case BFD_RELOC_386_TLS_LDO_32: | |
12078 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
12079 | case BFD_RELOC_386_TLS_IE: |
12080 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
12081 | case BFD_RELOC_386_TLS_LE_32: |
12082 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
12083 | case BFD_RELOC_386_TLS_GOTDESC: |
12084 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
12085 | case BFD_RELOC_X86_64_TLSGD: |
12086 | case BFD_RELOC_X86_64_TLSLD: | |
12087 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 12088 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
12089 | case BFD_RELOC_X86_64_GOTTPOFF: |
12090 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
12091 | case BFD_RELOC_X86_64_TPOFF64: |
12092 | case BFD_RELOC_X86_64_GOTOFF64: | |
12093 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
12094 | case BFD_RELOC_X86_64_GOT64: |
12095 | case BFD_RELOC_X86_64_GOTPCREL64: | |
12096 | case BFD_RELOC_X86_64_GOTPC64: | |
12097 | case BFD_RELOC_X86_64_GOTPLT64: | |
12098 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
12099 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
12100 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
12101 | case BFD_RELOC_RVA: |
12102 | case BFD_RELOC_VTABLE_ENTRY: | |
12103 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
12104 | #ifdef TE_PE |
12105 | case BFD_RELOC_32_SECREL: | |
12106 | #endif | |
252b5132 RH |
12107 | code = fixp->fx_r_type; |
12108 | break; | |
dbbaec26 L |
12109 | case BFD_RELOC_X86_64_32S: |
12110 | if (!fixp->fx_pcrel) | |
12111 | { | |
12112 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
12113 | code = fixp->fx_r_type; | |
12114 | break; | |
12115 | } | |
1a0670f3 | 12116 | /* Fall through. */ |
252b5132 | 12117 | default: |
93382f6d | 12118 | if (fixp->fx_pcrel) |
252b5132 | 12119 | { |
93382f6d AM |
12120 | switch (fixp->fx_size) |
12121 | { | |
12122 | default: | |
b091f402 AM |
12123 | as_bad_where (fixp->fx_file, fixp->fx_line, |
12124 | _("can not do %d byte pc-relative relocation"), | |
12125 | fixp->fx_size); | |
93382f6d AM |
12126 | code = BFD_RELOC_32_PCREL; |
12127 | break; | |
12128 | case 1: code = BFD_RELOC_8_PCREL; break; | |
12129 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 12130 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
12131 | #ifdef BFD64 |
12132 | case 8: code = BFD_RELOC_64_PCREL; break; | |
12133 | #endif | |
93382f6d AM |
12134 | } |
12135 | } | |
12136 | else | |
12137 | { | |
12138 | switch (fixp->fx_size) | |
12139 | { | |
12140 | default: | |
b091f402 AM |
12141 | as_bad_where (fixp->fx_file, fixp->fx_line, |
12142 | _("can not do %d byte relocation"), | |
12143 | fixp->fx_size); | |
93382f6d AM |
12144 | code = BFD_RELOC_32; |
12145 | break; | |
12146 | case 1: code = BFD_RELOC_8; break; | |
12147 | case 2: code = BFD_RELOC_16; break; | |
12148 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 12149 | #ifdef BFD64 |
3e73aa7c | 12150 | case 8: code = BFD_RELOC_64; break; |
937149dd | 12151 | #endif |
93382f6d | 12152 | } |
252b5132 RH |
12153 | } |
12154 | break; | |
12155 | } | |
252b5132 | 12156 | |
d182319b JB |
12157 | if ((code == BFD_RELOC_32 |
12158 | || code == BFD_RELOC_32_PCREL | |
12159 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
12160 | && GOT_symbol |
12161 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 12162 | { |
4fa24527 | 12163 | if (!object_64bit) |
d6ab8113 JB |
12164 | code = BFD_RELOC_386_GOTPC; |
12165 | else | |
12166 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 12167 | } |
7b81dfbb AJ |
12168 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
12169 | && GOT_symbol | |
12170 | && fixp->fx_addsy == GOT_symbol) | |
12171 | { | |
12172 | code = BFD_RELOC_X86_64_GOTPC64; | |
12173 | } | |
252b5132 | 12174 | |
add39d23 TS |
12175 | rel = XNEW (arelent); |
12176 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 12177 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
12178 | |
12179 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 12180 | |
3e73aa7c JH |
12181 | if (!use_rela_relocations) |
12182 | { | |
12183 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
12184 | vtable entry to be used in the relocation's section offset. */ | |
12185 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12186 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
12187 | #if defined (OBJ_COFF) && defined (TE_PE) |
12188 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
12189 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
12190 | else | |
12191 | #endif | |
c6682705 | 12192 | rel->addend = 0; |
3e73aa7c JH |
12193 | } |
12194 | /* Use the rela in 64bit mode. */ | |
252b5132 | 12195 | else |
3e73aa7c | 12196 | { |
862be3fb L |
12197 | if (disallow_64bit_reloc) |
12198 | switch (code) | |
12199 | { | |
862be3fb L |
12200 | case BFD_RELOC_X86_64_DTPOFF64: |
12201 | case BFD_RELOC_X86_64_TPOFF64: | |
12202 | case BFD_RELOC_64_PCREL: | |
12203 | case BFD_RELOC_X86_64_GOTOFF64: | |
12204 | case BFD_RELOC_X86_64_GOT64: | |
12205 | case BFD_RELOC_X86_64_GOTPCREL64: | |
12206 | case BFD_RELOC_X86_64_GOTPC64: | |
12207 | case BFD_RELOC_X86_64_GOTPLT64: | |
12208 | case BFD_RELOC_X86_64_PLTOFF64: | |
12209 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12210 | _("cannot represent relocation type %s in x32 mode"), | |
12211 | bfd_get_reloc_code_name (code)); | |
12212 | break; | |
12213 | default: | |
12214 | break; | |
12215 | } | |
12216 | ||
062cd5e7 AS |
12217 | if (!fixp->fx_pcrel) |
12218 | rel->addend = fixp->fx_offset; | |
12219 | else | |
12220 | switch (code) | |
12221 | { | |
12222 | case BFD_RELOC_X86_64_PLT32: | |
12223 | case BFD_RELOC_X86_64_GOT32: | |
12224 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
12225 | case BFD_RELOC_X86_64_GOTPCRELX: |
12226 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
bffbf940 JJ |
12227 | case BFD_RELOC_X86_64_TLSGD: |
12228 | case BFD_RELOC_X86_64_TLSLD: | |
12229 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
12230 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
12231 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
12232 | rel->addend = fixp->fx_offset - fixp->fx_size; |
12233 | break; | |
12234 | default: | |
12235 | rel->addend = (section->vma | |
12236 | - fixp->fx_size | |
12237 | + fixp->fx_addnumber | |
12238 | + md_pcrel_from (fixp)); | |
12239 | break; | |
12240 | } | |
3e73aa7c JH |
12241 | } |
12242 | ||
252b5132 RH |
12243 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
12244 | if (rel->howto == NULL) | |
12245 | { | |
12246 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 12247 | _("cannot represent relocation type %s"), |
252b5132 RH |
12248 | bfd_get_reloc_code_name (code)); |
12249 | /* Set howto to a garbage value so that we can keep going. */ | |
12250 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 12251 | gas_assert (rel->howto != NULL); |
252b5132 RH |
12252 | } |
12253 | ||
12254 | return rel; | |
12255 | } | |
12256 | ||
ee86248c | 12257 | #include "tc-i386-intel.c" |
54cfded0 | 12258 | |
a60de03c JB |
12259 | void |
12260 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 12261 | { |
a60de03c JB |
12262 | int saved_naked_reg; |
12263 | char saved_register_dot; | |
54cfded0 | 12264 | |
a60de03c JB |
12265 | saved_naked_reg = allow_naked_reg; |
12266 | allow_naked_reg = 1; | |
12267 | saved_register_dot = register_chars['.']; | |
12268 | register_chars['.'] = '.'; | |
12269 | allow_pseudo_reg = 1; | |
12270 | expression_and_evaluate (exp); | |
12271 | allow_pseudo_reg = 0; | |
12272 | register_chars['.'] = saved_register_dot; | |
12273 | allow_naked_reg = saved_naked_reg; | |
12274 | ||
e96d56a1 | 12275 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 12276 | { |
a60de03c JB |
12277 | if ((addressT) exp->X_add_number < i386_regtab_size) |
12278 | { | |
12279 | exp->X_op = O_constant; | |
12280 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
12281 | .dw2_regnum[flag_code >> 1]; | |
12282 | } | |
12283 | else | |
12284 | exp->X_op = O_illegal; | |
54cfded0 | 12285 | } |
54cfded0 AM |
12286 | } |
12287 | ||
12288 | void | |
12289 | tc_x86_frame_initial_instructions (void) | |
12290 | { | |
a60de03c JB |
12291 | static unsigned int sp_regno[2]; |
12292 | ||
12293 | if (!sp_regno[flag_code >> 1]) | |
12294 | { | |
12295 | char *saved_input = input_line_pointer; | |
12296 | char sp[][4] = {"esp", "rsp"}; | |
12297 | expressionS exp; | |
a4447b93 | 12298 | |
a60de03c JB |
12299 | input_line_pointer = sp[flag_code >> 1]; |
12300 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 12301 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
12302 | sp_regno[flag_code >> 1] = exp.X_add_number; |
12303 | input_line_pointer = saved_input; | |
12304 | } | |
a4447b93 | 12305 | |
61ff971f L |
12306 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
12307 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 12308 | } |
d2b2c203 | 12309 | |
d7921315 L |
12310 | int |
12311 | x86_dwarf2_addr_size (void) | |
12312 | { | |
12313 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
12314 | if (x86_elf_abi == X86_64_X32_ABI) | |
12315 | return 4; | |
12316 | #endif | |
12317 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
12318 | } | |
12319 | ||
d2b2c203 DJ |
12320 | int |
12321 | i386_elf_section_type (const char *str, size_t len) | |
12322 | { | |
12323 | if (flag_code == CODE_64BIT | |
12324 | && len == sizeof ("unwind") - 1 | |
12325 | && strncmp (str, "unwind", 6) == 0) | |
12326 | return SHT_X86_64_UNWIND; | |
12327 | ||
12328 | return -1; | |
12329 | } | |
bb41ade5 | 12330 | |
ad5fec3b EB |
12331 | #ifdef TE_SOLARIS |
12332 | void | |
12333 | i386_solaris_fix_up_eh_frame (segT sec) | |
12334 | { | |
12335 | if (flag_code == CODE_64BIT) | |
12336 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
12337 | } | |
12338 | #endif | |
12339 | ||
bb41ade5 AM |
12340 | #ifdef TE_PE |
12341 | void | |
12342 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
12343 | { | |
91d6fa6a | 12344 | expressionS exp; |
bb41ade5 | 12345 | |
91d6fa6a NC |
12346 | exp.X_op = O_secrel; |
12347 | exp.X_add_symbol = symbol; | |
12348 | exp.X_add_number = 0; | |
12349 | emit_expr (&exp, size); | |
bb41ade5 AM |
12350 | } |
12351 | #endif | |
3b22753a L |
12352 | |
12353 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
12354 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
12355 | ||
01e1a5bc | 12356 | bfd_vma |
6d4af3c2 | 12357 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
12358 | { |
12359 | if (flag_code == CODE_64BIT) | |
12360 | { | |
12361 | if (letter == 'l') | |
12362 | return SHF_X86_64_LARGE; | |
12363 | ||
8f3bae45 | 12364 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 12365 | } |
3b22753a | 12366 | else |
8f3bae45 | 12367 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
12368 | return -1; |
12369 | } | |
12370 | ||
01e1a5bc | 12371 | bfd_vma |
3b22753a L |
12372 | x86_64_section_word (char *str, size_t len) |
12373 | { | |
8620418b | 12374 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
12375 | return SHF_X86_64_LARGE; |
12376 | ||
12377 | return -1; | |
12378 | } | |
12379 | ||
12380 | static void | |
12381 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
12382 | { | |
12383 | if (flag_code != CODE_64BIT) | |
12384 | { | |
12385 | s_comm_internal (0, elf_common_parse); | |
12386 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
12387 | } | |
12388 | else | |
12389 | { | |
12390 | static segT lbss_section; | |
12391 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
12392 | asection *saved_bss_section = bss_section; | |
12393 | ||
12394 | if (lbss_section == NULL) | |
12395 | { | |
12396 | flagword applicable; | |
12397 | segT seg = now_seg; | |
12398 | subsegT subseg = now_subseg; | |
12399 | ||
12400 | /* The .lbss section is for local .largecomm symbols. */ | |
12401 | lbss_section = subseg_new (".lbss", 0); | |
12402 | applicable = bfd_applicable_section_flags (stdoutput); | |
fd361982 | 12403 | bfd_set_section_flags (lbss_section, applicable & SEC_ALLOC); |
3b22753a L |
12404 | seg_info (lbss_section)->bss = 1; |
12405 | ||
12406 | subseg_set (seg, subseg); | |
12407 | } | |
12408 | ||
12409 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
12410 | bss_section = lbss_section; | |
12411 | ||
12412 | s_comm_internal (0, elf_common_parse); | |
12413 | ||
12414 | elf_com_section_ptr = saved_com_section_ptr; | |
12415 | bss_section = saved_bss_section; | |
12416 | } | |
12417 | } | |
12418 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |